1 /*
  2  * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
  3  * Copyright (c) 2015, 2020, Red Hat Inc. All rights reserved.
  4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  5  *
  6  * This code is free software; you can redistribute it and/or modify it
  7  * under the terms of the GNU General Public License version 2 only, as
  8  * published by the Free Software Foundation.
  9  *
 10  * This code is distributed in the hope that it will be useful, but WITHOUT
 11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 13  * version 2 for more details (a copy is included in the LICENSE file that
 14  * accompanied this code).
 15  *
 16  * You should have received a copy of the GNU General Public License version
 17  * 2 along with this work; if not, write to the Free Software Foundation,
 18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 19  *
 20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 21  * or visit www.oracle.com if you need additional information or have any
 22  * questions.
 23  *
 24  */
 25 
 26 #include "precompiled.hpp"
 27 #include "pauth_aarch64.hpp"
 28 #include "runtime/arguments.hpp"
 29 #include "runtime/globals_extension.hpp"
 30 #include "runtime/java.hpp"
 31 #include "runtime/os.inline.hpp"
 32 #include "runtime/vm_version.hpp"
 33 #include "utilities/formatBuffer.hpp"
 34 #include "utilities/macros.hpp"
 35 
 36 int VM_Version::_cpu;
 37 int VM_Version::_model;
 38 int VM_Version::_model2;
 39 int VM_Version::_variant;
 40 int VM_Version::_revision;
 41 int VM_Version::_stepping;
 42 
 43 int VM_Version::_zva_length;
 44 int VM_Version::_dcache_line_size;
 45 int VM_Version::_icache_line_size;
 46 int VM_Version::_initial_sve_vector_length;
 47 bool VM_Version::_rop_protection;
 48 uintptr_t VM_Version::_pac_mask;
 49 
 50 SpinWait VM_Version::_spin_wait;
 51 
 52 static SpinWait get_spin_wait_desc() {
 53   if (strcmp(OnSpinWaitInst, "nop") == 0) {
 54     return SpinWait(SpinWait::NOP, OnSpinWaitInstCount);
 55   } else if (strcmp(OnSpinWaitInst, "isb") == 0) {
 56     return SpinWait(SpinWait::ISB, OnSpinWaitInstCount);
 57   } else if (strcmp(OnSpinWaitInst, "yield") == 0) {
 58     return SpinWait(SpinWait::YIELD, OnSpinWaitInstCount);
 59   } else if (strcmp(OnSpinWaitInst, "none") != 0) {
 60     vm_exit_during_initialization("The options for OnSpinWaitInst are nop, isb, yield, and none", OnSpinWaitInst);
 61   }
 62 
 63   if (!FLAG_IS_DEFAULT(OnSpinWaitInstCount) && OnSpinWaitInstCount > 0) {
 64     vm_exit_during_initialization("OnSpinWaitInstCount cannot be used for OnSpinWaitInst 'none'");
 65   }
 66 
 67   return SpinWait{};
 68 }
 69 
 70 void VM_Version::initialize() {
 71   _supports_cx8 = true;
 72   _supports_atomic_getset4 = true;
 73   _supports_atomic_getadd4 = true;
 74   _supports_atomic_getset8 = true;
 75   _supports_atomic_getadd8 = true;
 76 
 77   get_os_cpu_info();
 78 
 79   int dcache_line = VM_Version::dcache_line_size();
 80 
 81   // Limit AllocatePrefetchDistance so that it does not exceed the
 82   // constraint in AllocatePrefetchDistanceConstraintFunc.
 83   if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
 84     FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
 85 
 86   if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
 87     FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
 88   if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
 89     FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
 90   if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
 91     FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
 92   if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
 93     FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
 94 
 95   if (PrefetchCopyIntervalInBytes != -1 &&
 96        ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
 97     warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
 98     PrefetchCopyIntervalInBytes &= ~7;
 99     if (PrefetchCopyIntervalInBytes >= 32768)
100       PrefetchCopyIntervalInBytes = 32760;
101   }
102 
103   if (AllocatePrefetchDistance !=-1 && (AllocatePrefetchDistance & 7)) {
104     warning("AllocatePrefetchDistance must be multiple of 8");
105     AllocatePrefetchDistance &= ~7;
106   }
107 
108   if (AllocatePrefetchStepSize & 7) {
109     warning("AllocatePrefetchStepSize must be multiple of 8");
110     AllocatePrefetchStepSize &= ~7;
111   }
112 
113   if (SoftwarePrefetchHintDistance != -1 &&
114        (SoftwarePrefetchHintDistance & 7)) {
115     warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
116     SoftwarePrefetchHintDistance &= ~7;
117   }
118 
119   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (dcache_line > ContendedPaddingWidth)) {
120     ContendedPaddingWidth = dcache_line;
121   }
122 
123   if (os::supports_map_sync()) {
124     // if dcpop is available publish data cache line flush size via
125     // generic field, otherwise let if default to zero thereby
126     // disabling writeback
127     if (VM_Version::supports_dcpop()) {
128       _data_cache_line_flush_size = dcache_line;
129     }
130   }
131 
132   // Enable vendor specific features
133 
134   // Ampere eMAG
135   if (_cpu == CPU_AMCC && (_model == CPU_MODEL_EMAG) && (_variant == 0x3)) {
136     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
137       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
138     }
139     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
140       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
141     }
142     if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
143       FLAG_SET_DEFAULT(UseSIMDForArrayEquals, !(_revision == 1 || _revision == 2));
144     }
145   }
146 
147   // Ampere CPUs: Ampere-1 and Ampere-1A
148   if (_cpu == CPU_AMPERE && ((_model == CPU_MODEL_AMPERE_1) || (_model == CPU_MODEL_AMPERE_1A))) {
149     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
150       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
151     }
152   }
153 
154   // ThunderX
155   if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
156     guarantee(_variant != 0, "Pre-release hardware no longer supported.");
157     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
158       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
159     }
160     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
161       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
162     }
163     if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
164       FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
165     }
166   }
167 
168   // ThunderX2
169   if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
170       (_cpu == CPU_BROADCOM && (_model == 0x516))) {
171     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
172       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
173     }
174     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
175       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
176     }
177   }
178 
179   // HiSilicon TSV110
180   if (_cpu == CPU_HISILICON && _model == 0xd01) {
181     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
182       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
183     }
184     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
185       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
186     }
187   }
188 
189   // Cortex A53
190   if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) {
191     _features |= CPU_A53MAC;
192     if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
193       FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
194     }
195   }
196 
197   // Cortex A73
198   if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) {
199     if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
200       FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
201     }
202     // A73 is faster with short-and-easy-for-speculative-execution-loop
203     if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
204       FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
205     }
206   }
207 
208   // Neoverse N1, N2 and V1
209   if (_cpu == CPU_ARM && ((_model == 0xd0c || _model2 == 0xd0c)
210                           || (_model == 0xd49 || _model2 == 0xd49)
211                           || (_model == 0xd40 || _model2 == 0xd40))) {
212     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
213       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
214     }
215 
216     if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
217       FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
218     }
219 
220     if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
221       FLAG_SET_DEFAULT(OnSpinWaitInstCount, 1);
222     }
223   }
224 
225   if (_cpu == CPU_ARM) {
226     if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) {
227       FLAG_SET_DEFAULT(UseSignumIntrinsic, true);
228     }
229   }
230 
231   char buf[512];
232   int buf_used_len = os::snprintf_checked(buf, sizeof(buf), "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
233   if (_model2) os::snprintf_checked(buf + buf_used_len, sizeof(buf) - buf_used_len, "(0x%03x)", _model2);
234 #define ADD_FEATURE_IF_SUPPORTED(id, name, bit) if (VM_Version::supports_##name()) strcat(buf, ", " #name);
235   CPU_FEATURE_FLAGS(ADD_FEATURE_IF_SUPPORTED)
236 #undef ADD_FEATURE_IF_SUPPORTED
237 
238   _features_string = os::strdup(buf);
239 
240   if (FLAG_IS_DEFAULT(UseCRC32)) {
241     UseCRC32 = VM_Version::supports_crc32();
242   }
243 
244   if (UseCRC32 && !VM_Version::supports_crc32()) {
245     warning("UseCRC32 specified, but not supported on this CPU");
246     FLAG_SET_DEFAULT(UseCRC32, false);
247   }
248 
249   // Neoverse V1
250   if (_cpu == CPU_ARM && (_model == 0xd40 || _model2 == 0xd40)) {
251     if (FLAG_IS_DEFAULT(UseCryptoPmullForCRC32)) {
252       FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, true);
253     }
254   }
255 
256   if (UseCryptoPmullForCRC32 && (!VM_Version::supports_pmull() || !VM_Version::supports_sha3() || !VM_Version::supports_crc32())) {
257     warning("UseCryptoPmullForCRC32 specified, but not supported on this CPU");
258     FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, false);
259   }
260 
261   if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
262     FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
263   }
264 
265   if (UseVectorizedMismatchIntrinsic) {
266     warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
267     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
268   }
269 
270   if (VM_Version::supports_lse()) {
271     if (FLAG_IS_DEFAULT(UseLSE))
272       FLAG_SET_DEFAULT(UseLSE, true);
273   } else {
274     if (UseLSE) {
275       warning("UseLSE specified, but not supported on this CPU");
276       FLAG_SET_DEFAULT(UseLSE, false);
277     }
278   }
279 
280   if (VM_Version::supports_aes()) {
281     UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
282     UseAESIntrinsics =
283         UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
284     if (UseAESIntrinsics && !UseAES) {
285       warning("UseAESIntrinsics enabled, but UseAES not, enabling");
286       UseAES = true;
287     }
288     if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
289       FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
290     }
291   } else {
292     if (UseAES) {
293       warning("AES instructions are not available on this CPU");
294       FLAG_SET_DEFAULT(UseAES, false);
295     }
296     if (UseAESIntrinsics) {
297       warning("AES intrinsics are not available on this CPU");
298       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
299     }
300     if (UseAESCTRIntrinsics) {
301       warning("AES/CTR intrinsics are not available on this CPU");
302       FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
303     }
304   }
305 
306 
307   if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
308     UseCRC32Intrinsics = true;
309   }
310 
311   if (VM_Version::supports_crc32()) {
312     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
313       FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
314     }
315   } else if (UseCRC32CIntrinsics) {
316     warning("CRC32C is not available on the CPU");
317     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
318   }
319 
320   if (FLAG_IS_DEFAULT(UseFMA)) {
321     FLAG_SET_DEFAULT(UseFMA, true);
322   }
323 
324   if (FLAG_IS_DEFAULT(UseMD5Intrinsics)) {
325     UseMD5Intrinsics = true;
326   }
327 
328   if (VM_Version::supports_sha1() || VM_Version::supports_sha256() ||
329       VM_Version::supports_sha3() || VM_Version::supports_sha512()) {
330     if (FLAG_IS_DEFAULT(UseSHA)) {
331       FLAG_SET_DEFAULT(UseSHA, true);
332     }
333   } else if (UseSHA) {
334     warning("SHA instructions are not available on this CPU");
335     FLAG_SET_DEFAULT(UseSHA, false);
336   }
337 
338   if (UseSHA && VM_Version::supports_sha1()) {
339     if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
340       FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
341     }
342   } else if (UseSHA1Intrinsics) {
343     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
344     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
345   }
346 
347   if (UseSHA && VM_Version::supports_sha256()) {
348     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
349       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
350     }
351   } else if (UseSHA256Intrinsics) {
352     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
353     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
354   }
355 
356   if (UseSHA && VM_Version::supports_sha3()) {
357     // Auto-enable UseSHA3Intrinsics on hardware with performance benefit.
358     // Note that the evaluation of UseSHA3Intrinsics shows better performance
359     // on Apple silicon but worse performance on Neoverse V1 and N2.
360     if (_cpu == CPU_APPLE) {  // Apple silicon
361       if (FLAG_IS_DEFAULT(UseSHA3Intrinsics)) {
362         FLAG_SET_DEFAULT(UseSHA3Intrinsics, true);
363       }
364     }
365   } else if (UseSHA3Intrinsics) {
366     warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
367     FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
368   }
369 
370   if (UseSHA && VM_Version::supports_sha512()) {
371     if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
372       FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
373     }
374   } else if (UseSHA512Intrinsics) {
375     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
376     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
377   }
378 
379   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA3Intrinsics || UseSHA512Intrinsics)) {
380     FLAG_SET_DEFAULT(UseSHA, false);
381   }
382 
383   if (VM_Version::supports_pmull()) {
384     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
385       FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
386     }
387   } else if (UseGHASHIntrinsics) {
388     warning("GHASH intrinsics are not available on this CPU");
389     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
390   }
391 
392   if (_features & CPU_ASIMD) {
393       if (FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
394           UseChaCha20Intrinsics = true;
395       }
396   } else if (UseChaCha20Intrinsics) {
397       if (!FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
398           warning("ChaCha20 intrinsic requires ASIMD instructions");
399       }
400       FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
401   }
402 
403   if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
404     UseBASE64Intrinsics = true;
405   }
406 
407   if (is_zva_enabled()) {
408     if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
409       FLAG_SET_DEFAULT(UseBlockZeroing, true);
410     }
411     if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
412       FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
413     }
414   } else if (UseBlockZeroing) {
415     warning("DC ZVA is not available on this CPU");
416     FLAG_SET_DEFAULT(UseBlockZeroing, false);
417   }
418 
419   if (VM_Version::supports_sve2()) {
420     if (FLAG_IS_DEFAULT(UseSVE)) {
421       FLAG_SET_DEFAULT(UseSVE, 2);
422     }
423   } else if (VM_Version::supports_sve()) {
424     if (FLAG_IS_DEFAULT(UseSVE)) {
425       FLAG_SET_DEFAULT(UseSVE, 1);
426     } else if (UseSVE > 1) {
427       warning("SVE2 specified, but not supported on current CPU. Using SVE.");
428       FLAG_SET_DEFAULT(UseSVE, 1);
429     }
430   } else if (UseSVE > 0) {
431     warning("UseSVE specified, but not supported on current CPU. Disabling SVE.");
432     FLAG_SET_DEFAULT(UseSVE, 0);
433   }
434 
435   if (UseSVE > 0) {
436     _initial_sve_vector_length = get_current_sve_vector_length();
437   }
438 
439   // This machine allows unaligned memory accesses
440   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
441     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
442   }
443 
444   if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
445     FLAG_SET_DEFAULT(UsePopCountInstruction, true);
446   }
447 
448   if (!UsePopCountInstruction) {
449     warning("UsePopCountInstruction is always enabled on this CPU");
450     UsePopCountInstruction = true;
451   }
452 
453   if (UseBranchProtection == nullptr || strcmp(UseBranchProtection, "none") == 0) {
454     _rop_protection = false;
455   } else if (strcmp(UseBranchProtection, "standard") == 0 ||
456              strcmp(UseBranchProtection, "pac-ret") == 0) {
457     _rop_protection = false;
458     // Enable ROP-protection if
459     // 1) this code has been built with branch-protection,
460     // 2) the CPU/OS supports it, and
461     // 3) incompatible VMContinuations isn't enabled.
462 #ifdef __ARM_FEATURE_PAC_DEFAULT
463     if (!VM_Version::supports_paca()) {
464       // Disable PAC to prevent illegal instruction crashes.
465       warning("ROP-protection specified, but not supported on this CPU. Disabling ROP-protection.");
466     } else if (VMContinuations) {
467       // Not currently compatible with continuation freeze/thaw.
468       warning("ROP-protection is incompatible with VMContinuations. Disabling ROP-protection.");
469     } else {
470       _rop_protection = true;
471     }
472 #else
473     warning("ROP-protection specified, but this VM was built without ROP-protection support. Disabling ROP-protection.");
474 #endif
475   } else {
476     vm_exit_during_initialization(err_msg("Unsupported UseBranchProtection: %s", UseBranchProtection));
477   }
478 
479   if (_rop_protection == true) {
480     // Determine the mask of address bits used for PAC. Clear bit 55 of
481     // the input to make it look like a user address.
482     _pac_mask = (uintptr_t)pauth_strip_pointer((address)~(UINT64_C(1) << 55));
483 
484     // The frame pointer must be preserved for ROP protection.
485     if (FLAG_IS_DEFAULT(PreserveFramePointer) == false && PreserveFramePointer == false ) {
486       vm_exit_during_initialization(err_msg("PreserveFramePointer cannot be disabled for ROP-protection"));
487     }
488     PreserveFramePointer = true;
489   }
490 
491 #ifdef COMPILER2
492   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
493     UseMultiplyToLenIntrinsic = true;
494   }
495 
496   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
497     UseSquareToLenIntrinsic = true;
498   }
499 
500   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
501     UseMulAddIntrinsic = true;
502   }
503 
504   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
505     UseMontgomeryMultiplyIntrinsic = true;
506   }
507   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
508     UseMontgomerySquareIntrinsic = true;
509   }
510 
511   if (UseSVE > 0) {
512     if (FLAG_IS_DEFAULT(MaxVectorSize)) {
513       MaxVectorSize = _initial_sve_vector_length;
514     } else if (MaxVectorSize < 16) {
515       warning("SVE does not support vector length less than 16 bytes. Disabling SVE.");
516       UseSVE = 0;
517     } else if ((MaxVectorSize % 16) == 0 && is_power_of_2(MaxVectorSize)) {
518       int new_vl = set_and_get_current_sve_vector_length(MaxVectorSize);
519       _initial_sve_vector_length = new_vl;
520       // Update MaxVectorSize to the largest supported value.
521       if (new_vl < 0) {
522         vm_exit_during_initialization(
523           err_msg("Current system does not support SVE vector length for MaxVectorSize: %d",
524                   (int)MaxVectorSize));
525       } else if (new_vl != MaxVectorSize) {
526         warning("Current system only supports max SVE vector length %d. Set MaxVectorSize to %d",
527                 new_vl, new_vl);
528       }
529       MaxVectorSize = new_vl;
530     } else {
531       vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
532     }
533   }
534 
535   if (UseSVE == 0) {  // NEON
536     int min_vector_size = 8;
537     int max_vector_size = 16;
538     if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
539       if (!is_power_of_2(MaxVectorSize)) {
540         vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
541       } else if (MaxVectorSize < min_vector_size) {
542         warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
543         FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
544       } else if (MaxVectorSize > max_vector_size) {
545         warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
546         FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
547       }
548     } else {
549       FLAG_SET_DEFAULT(MaxVectorSize, 16);
550     }
551   }
552 
553   int inline_size = (UseSVE > 0 && MaxVectorSize >= 16) ? MaxVectorSize : 0;
554   if (FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize)) {
555     FLAG_SET_DEFAULT(ArrayOperationPartialInlineSize, inline_size);
556   } else if (ArrayOperationPartialInlineSize != 0 && ArrayOperationPartialInlineSize != inline_size) {
557     warning("Setting ArrayOperationPartialInlineSize to %d", inline_size);
558     ArrayOperationPartialInlineSize = inline_size;
559   }
560 
561   if (FLAG_IS_DEFAULT(OptoScheduling)) {
562     OptoScheduling = true;
563   }
564 
565   if (FLAG_IS_DEFAULT(AlignVector)) {
566     AlignVector = AvoidUnalignedAccesses;
567   }
568 
569   if (FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
570     FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true);
571   }
572 #endif
573 
574   _spin_wait = get_spin_wait_desc();
575 
576   check_virtualizations();
577 }
578 
579 #if defined(LINUX)
580 static bool check_info_file(const char* fpath,
581                             const char* virt1, VirtualizationType vt1,
582                             const char* virt2, VirtualizationType vt2) {
583   char line[500];
584   FILE* fp = os::fopen(fpath, "r");
585   if (fp == nullptr) {
586     return false;
587   }
588   while (fgets(line, sizeof(line), fp) != nullptr) {
589     if (strcasestr(line, virt1) != 0) {
590       Abstract_VM_Version::_detected_virtualization = vt1;
591       fclose(fp);
592       return true;
593     }
594     if (virt2 != nullptr && strcasestr(line, virt2) != 0) {
595       Abstract_VM_Version::_detected_virtualization = vt2;
596       fclose(fp);
597       return true;
598     }
599   }
600   fclose(fp);
601   return false;
602 }
603 #endif
604 
605 void VM_Version::check_virtualizations() {
606 #if defined(LINUX)
607   const char* pname_file = "/sys/devices/virtual/dmi/id/product_name";
608   const char* tname_file = "/sys/hypervisor/type";
609   if (check_info_file(pname_file, "KVM", KVM, "VMWare", VMWare)) {
610     return;
611   }
612   check_info_file(tname_file, "Xen", XenPVHVM, nullptr, NoDetectedVirtualization);
613 #endif
614 }
615 
616 void VM_Version::print_platform_virtualization_info(outputStream* st) {
617 #if defined(LINUX)
618   VirtualizationType vrt = VM_Version::get_detected_virtualization();
619   if (vrt == KVM) {
620     st->print_cr("KVM virtualization detected");
621   } else if (vrt == VMWare) {
622     st->print_cr("VMWare virtualization detected");
623   } else if (vrt == XenPVHVM) {
624     st->print_cr("Xen virtualization detected");
625   }
626 #endif
627 }
628 
629 void VM_Version::initialize_cpu_information(void) {
630   // do nothing if cpu info has been initialized
631   if (_initialized) {
632     return;
633   }
634 
635   _no_of_cores  = os::processor_count();
636   _no_of_threads = _no_of_cores;
637   _no_of_sockets = _no_of_cores;
638   snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "AArch64");
639 
640   int desc_len = snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "AArch64 ");
641   get_compatible_board(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len);
642   desc_len = (int)strlen(_cpu_desc);
643   snprintf(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len, " %s", _features_string);
644 
645   _initialized = true;
646 }