1 /*
  2  * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
  3  * Copyright (c) 2015, 2020, Red Hat Inc. All rights reserved.
  4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  5  *
  6  * This code is free software; you can redistribute it and/or modify it
  7  * under the terms of the GNU General Public License version 2 only, as
  8  * published by the Free Software Foundation.
  9  *
 10  * This code is distributed in the hope that it will be useful, but WITHOUT
 11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 13  * version 2 for more details (a copy is included in the LICENSE file that
 14  * accompanied this code).
 15  *
 16  * You should have received a copy of the GNU General Public License version
 17  * 2 along with this work; if not, write to the Free Software Foundation,
 18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 19  *
 20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 21  * or visit www.oracle.com if you need additional information or have any
 22  * questions.
 23  *
 24  */
 25 
 26 #include "precompiled.hpp"
 27 #include "pauth_aarch64.hpp"
 28 #include "runtime/arguments.hpp"
 29 #include "runtime/globals_extension.hpp"
 30 #include "runtime/java.hpp"
 31 #include "runtime/os.inline.hpp"
 32 #include "runtime/vm_version.hpp"
 33 #include "utilities/formatBuffer.hpp"
 34 #include "utilities/macros.hpp"
 35 
 36 int VM_Version::_cpu;
 37 int VM_Version::_model;
 38 int VM_Version::_model2;
 39 int VM_Version::_variant;
 40 int VM_Version::_revision;
 41 int VM_Version::_stepping;
 42 
 43 int VM_Version::_zva_length;
 44 int VM_Version::_dcache_line_size;
 45 int VM_Version::_icache_line_size;
 46 int VM_Version::_initial_sve_vector_length;
 47 bool VM_Version::_rop_protection;
 48 uintptr_t VM_Version::_pac_mask;
 49 
 50 SpinWait VM_Version::_spin_wait;
 51 
 52 static SpinWait get_spin_wait_desc() {
 53   if (strcmp(OnSpinWaitInst, "nop") == 0) {
 54     return SpinWait(SpinWait::NOP, OnSpinWaitInstCount);
 55   } else if (strcmp(OnSpinWaitInst, "isb") == 0) {
 56     return SpinWait(SpinWait::ISB, OnSpinWaitInstCount);
 57   } else if (strcmp(OnSpinWaitInst, "yield") == 0) {
 58     return SpinWait(SpinWait::YIELD, OnSpinWaitInstCount);
 59   } else if (strcmp(OnSpinWaitInst, "none") != 0) {
 60     vm_exit_during_initialization("The options for OnSpinWaitInst are nop, isb, yield, and none", OnSpinWaitInst);
 61   }
 62 
 63   if (!FLAG_IS_DEFAULT(OnSpinWaitInstCount) && OnSpinWaitInstCount > 0) {
 64     vm_exit_during_initialization("OnSpinWaitInstCount cannot be used for OnSpinWaitInst 'none'");
 65   }
 66 
 67   return SpinWait{};
 68 }
 69 
 70 void VM_Version::initialize() {
 71   _supports_cx8 = true;
 72   _supports_atomic_getset4 = true;
 73   _supports_atomic_getadd4 = true;
 74   _supports_atomic_getset8 = true;
 75   _supports_atomic_getadd8 = true;
 76 
 77   get_os_cpu_info();
 78 
 79   int dcache_line = VM_Version::dcache_line_size();
 80 
 81   // Limit AllocatePrefetchDistance so that it does not exceed the
 82   // constraint in AllocatePrefetchDistanceConstraintFunc.
 83   if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
 84     FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
 85 
 86   if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
 87     FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
 88   if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
 89     FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
 90   if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
 91     FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
 92   if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
 93     FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
 94 
 95   if (PrefetchCopyIntervalInBytes != -1 &&
 96        ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
 97     warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
 98     PrefetchCopyIntervalInBytes &= ~7;
 99     if (PrefetchCopyIntervalInBytes >= 32768)
100       PrefetchCopyIntervalInBytes = 32760;
101   }
102 
103   if (AllocatePrefetchDistance !=-1 && (AllocatePrefetchDistance & 7)) {
104     warning("AllocatePrefetchDistance must be multiple of 8");
105     AllocatePrefetchDistance &= ~7;
106   }
107 
108   if (AllocatePrefetchStepSize & 7) {
109     warning("AllocatePrefetchStepSize must be multiple of 8");
110     AllocatePrefetchStepSize &= ~7;
111   }
112 
113   if (SoftwarePrefetchHintDistance != -1 &&
114        (SoftwarePrefetchHintDistance & 7)) {
115     warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
116     SoftwarePrefetchHintDistance &= ~7;
117   }
118 
119   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (dcache_line > ContendedPaddingWidth)) {
120     ContendedPaddingWidth = dcache_line;
121   }
122 
123   if (os::supports_map_sync()) {
124     // if dcpop is available publish data cache line flush size via
125     // generic field, otherwise let if default to zero thereby
126     // disabling writeback
127     if (VM_Version::supports_dcpop()) {
128       _data_cache_line_flush_size = dcache_line;
129     }
130   }
131 
132   // Enable vendor specific features
133 
134   // Ampere eMAG
135   if (_cpu == CPU_AMCC && (_model == CPU_MODEL_EMAG) && (_variant == 0x3)) {
136     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
137       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
138     }
139     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
140       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
141     }
142     if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
143       FLAG_SET_DEFAULT(UseSIMDForArrayEquals, !(_revision == 1 || _revision == 2));
144     }
145   }
146 
147   // Ampere CPUs
148   if (_cpu == CPU_AMPERE && ((_model == CPU_MODEL_AMPERE_1)  ||
149                              (_model == CPU_MODEL_AMPERE_1A) ||
150                              (_model == CPU_MODEL_AMPERE_1B))) {
151     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
152       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
153     }
154     if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
155       FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
156     }
157     if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
158       FLAG_SET_DEFAULT(OnSpinWaitInstCount, 2);
159     }
160   }
161 
162   // ThunderX
163   if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
164     guarantee(_variant != 0, "Pre-release hardware no longer supported.");
165     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
166       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
167     }
168     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
169       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
170     }
171     if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
172       FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
173     }
174   }
175 
176   // ThunderX2
177   if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
178       (_cpu == CPU_BROADCOM && (_model == 0x516))) {
179     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
180       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
181     }
182     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
183       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
184     }
185   }
186 
187   // HiSilicon TSV110
188   if (_cpu == CPU_HISILICON && _model == 0xd01) {
189     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
190       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
191     }
192     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
193       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
194     }
195   }
196 
197   // Cortex A53
198   if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) {
199     _features |= CPU_A53MAC;
200     if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
201       FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
202     }
203   }
204 
205   // Cortex A73
206   if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) {
207     if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
208       FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
209     }
210     // A73 is faster with short-and-easy-for-speculative-execution-loop
211     if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
212       FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
213     }
214   }
215 
216   // Neoverse N1, N2 and V1
217   if (_cpu == CPU_ARM && ((_model == 0xd0c || _model2 == 0xd0c)
218                           || (_model == 0xd49 || _model2 == 0xd49)
219                           || (_model == 0xd40 || _model2 == 0xd40))) {
220     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
221       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
222     }
223 
224     if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
225       FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
226     }
227 
228     if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
229       FLAG_SET_DEFAULT(OnSpinWaitInstCount, 1);
230     }
231   }
232 
233   if (_cpu == CPU_ARM) {
234     if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) {
235       FLAG_SET_DEFAULT(UseSignumIntrinsic, true);
236     }
237   }
238 
239   char buf[512];
240   int buf_used_len = os::snprintf_checked(buf, sizeof(buf), "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
241   if (_model2) os::snprintf_checked(buf + buf_used_len, sizeof(buf) - buf_used_len, "(0x%03x)", _model2);
242 #define ADD_FEATURE_IF_SUPPORTED(id, name, bit) if (VM_Version::supports_##name()) strcat(buf, ", " #name);
243   CPU_FEATURE_FLAGS(ADD_FEATURE_IF_SUPPORTED)
244 #undef ADD_FEATURE_IF_SUPPORTED
245 
246   _features_string = os::strdup(buf);
247 
248   if (FLAG_IS_DEFAULT(UseCRC32)) {
249     UseCRC32 = VM_Version::supports_crc32();
250   }
251 
252   if (UseCRC32 && !VM_Version::supports_crc32()) {
253     warning("UseCRC32 specified, but not supported on this CPU");
254     FLAG_SET_DEFAULT(UseCRC32, false);
255   }
256 
257   // Neoverse V1
258   if (_cpu == CPU_ARM && (_model == 0xd40 || _model2 == 0xd40)) {
259     if (FLAG_IS_DEFAULT(UseCryptoPmullForCRC32)) {
260       FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, true);
261     }
262   }
263 
264   if (UseCryptoPmullForCRC32 && (!VM_Version::supports_pmull() || !VM_Version::supports_sha3() || !VM_Version::supports_crc32())) {
265     warning("UseCryptoPmullForCRC32 specified, but not supported on this CPU");
266     FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, false);
267   }
268 
269   if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
270     FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
271   }
272 
273   if (UseVectorizedMismatchIntrinsic) {
274     warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
275     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
276   }
277 
278   if (VM_Version::supports_lse()) {
279     if (FLAG_IS_DEFAULT(UseLSE))
280       FLAG_SET_DEFAULT(UseLSE, true);
281   } else {
282     if (UseLSE) {
283       warning("UseLSE specified, but not supported on this CPU");
284       FLAG_SET_DEFAULT(UseLSE, false);
285     }
286   }
287 
288   if (VM_Version::supports_aes()) {
289     UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
290     UseAESIntrinsics =
291         UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
292     if (UseAESIntrinsics && !UseAES) {
293       warning("UseAESIntrinsics enabled, but UseAES not, enabling");
294       UseAES = true;
295     }
296     if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
297       FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
298     }
299   } else {
300     if (UseAES) {
301       warning("AES instructions are not available on this CPU");
302       FLAG_SET_DEFAULT(UseAES, false);
303     }
304     if (UseAESIntrinsics) {
305       warning("AES intrinsics are not available on this CPU");
306       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
307     }
308     if (UseAESCTRIntrinsics) {
309       warning("AES/CTR intrinsics are not available on this CPU");
310       FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
311     }
312   }
313 
314 
315   if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
316     UseCRC32Intrinsics = true;
317   }
318 
319   if (VM_Version::supports_crc32()) {
320     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
321       FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
322     }
323   } else if (UseCRC32CIntrinsics) {
324     warning("CRC32C is not available on the CPU");
325     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
326   }
327 
328   if (FLAG_IS_DEFAULT(UseFMA)) {
329     FLAG_SET_DEFAULT(UseFMA, true);
330   }
331 
332   if (FLAG_IS_DEFAULT(UseMD5Intrinsics)) {
333     UseMD5Intrinsics = true;
334   }
335 
336   if (VM_Version::supports_sha1() || VM_Version::supports_sha256() ||
337       VM_Version::supports_sha3() || VM_Version::supports_sha512()) {
338     if (FLAG_IS_DEFAULT(UseSHA)) {
339       FLAG_SET_DEFAULT(UseSHA, true);
340     }
341   } else if (UseSHA) {
342     warning("SHA instructions are not available on this CPU");
343     FLAG_SET_DEFAULT(UseSHA, false);
344   }
345 
346   if (UseSHA && VM_Version::supports_sha1()) {
347     if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
348       FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
349     }
350   } else if (UseSHA1Intrinsics) {
351     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
352     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
353   }
354 
355   if (UseSHA && VM_Version::supports_sha256()) {
356     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
357       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
358     }
359   } else if (UseSHA256Intrinsics) {
360     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
361     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
362   }
363 
364   if (UseSHA && VM_Version::supports_sha3()) {
365     // Auto-enable UseSHA3Intrinsics on hardware with performance benefit.
366     // Note that the evaluation of UseSHA3Intrinsics shows better performance
367     // on Apple silicon but worse performance on Neoverse V1 and N2.
368     if (_cpu == CPU_APPLE) {  // Apple silicon
369       if (FLAG_IS_DEFAULT(UseSHA3Intrinsics)) {
370         FLAG_SET_DEFAULT(UseSHA3Intrinsics, true);
371       }
372     }
373   } else if (UseSHA3Intrinsics) {
374     warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
375     FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
376   }
377 
378   if (UseSHA && VM_Version::supports_sha512()) {
379     if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
380       FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
381     }
382   } else if (UseSHA512Intrinsics) {
383     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
384     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
385   }
386 
387   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA3Intrinsics || UseSHA512Intrinsics)) {
388     FLAG_SET_DEFAULT(UseSHA, false);
389   }
390 
391   if (VM_Version::supports_pmull()) {
392     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
393       FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
394     }
395   } else if (UseGHASHIntrinsics) {
396     warning("GHASH intrinsics are not available on this CPU");
397     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
398   }
399 
400   if (_features & CPU_ASIMD) {
401       if (FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
402           UseChaCha20Intrinsics = true;
403       }
404   } else if (UseChaCha20Intrinsics) {
405       if (!FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
406           warning("ChaCha20 intrinsic requires ASIMD instructions");
407       }
408       FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
409   }
410 
411   if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
412     UseBASE64Intrinsics = true;
413   }
414 
415   if (is_zva_enabled()) {
416     if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
417       FLAG_SET_DEFAULT(UseBlockZeroing, true);
418     }
419     if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
420       FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
421     }
422   } else if (UseBlockZeroing) {
423     warning("DC ZVA is not available on this CPU");
424     FLAG_SET_DEFAULT(UseBlockZeroing, false);
425   }
426 
427   if (VM_Version::supports_sve2()) {
428     if (FLAG_IS_DEFAULT(UseSVE)) {
429       FLAG_SET_DEFAULT(UseSVE, 2);
430     }
431   } else if (VM_Version::supports_sve()) {
432     if (FLAG_IS_DEFAULT(UseSVE)) {
433       FLAG_SET_DEFAULT(UseSVE, 1);
434     } else if (UseSVE > 1) {
435       warning("SVE2 specified, but not supported on current CPU. Using SVE.");
436       FLAG_SET_DEFAULT(UseSVE, 1);
437     }
438   } else if (UseSVE > 0) {
439     warning("UseSVE specified, but not supported on current CPU. Disabling SVE.");
440     FLAG_SET_DEFAULT(UseSVE, 0);
441   }
442 
443   if (UseSVE > 0) {
444     _initial_sve_vector_length = get_current_sve_vector_length();
445   }
446 
447   // This machine allows unaligned memory accesses
448   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
449     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
450   }
451 
452   if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
453     FLAG_SET_DEFAULT(UsePopCountInstruction, true);
454   }
455 
456   if (!UsePopCountInstruction) {
457     warning("UsePopCountInstruction is always enabled on this CPU");
458     UsePopCountInstruction = true;
459   }
460 
461   if (UseBranchProtection == nullptr || strcmp(UseBranchProtection, "none") == 0) {
462     _rop_protection = false;
463   } else if (strcmp(UseBranchProtection, "standard") == 0 ||
464              strcmp(UseBranchProtection, "pac-ret") == 0) {
465     _rop_protection = false;
466     // Enable ROP-protection if
467     // 1) this code has been built with branch-protection,
468     // 2) the CPU/OS supports it, and
469     // 3) incompatible VMContinuations isn't enabled.
470 #ifdef __ARM_FEATURE_PAC_DEFAULT
471     if (!VM_Version::supports_paca()) {
472       // Disable PAC to prevent illegal instruction crashes.
473       warning("ROP-protection specified, but not supported on this CPU. Disabling ROP-protection.");
474     } else if (VMContinuations) {
475       // Not currently compatible with continuation freeze/thaw.
476       warning("ROP-protection is incompatible with VMContinuations. Disabling ROP-protection.");
477     } else {
478       _rop_protection = true;
479     }
480 #else
481     warning("ROP-protection specified, but this VM was built without ROP-protection support. Disabling ROP-protection.");
482 #endif
483   } else {
484     vm_exit_during_initialization(err_msg("Unsupported UseBranchProtection: %s", UseBranchProtection));
485   }
486 
487   if (_rop_protection == true) {
488     // Determine the mask of address bits used for PAC. Clear bit 55 of
489     // the input to make it look like a user address.
490     _pac_mask = (uintptr_t)pauth_strip_pointer((address)~(UINT64_C(1) << 55));
491 
492     // The frame pointer must be preserved for ROP protection.
493     if (FLAG_IS_DEFAULT(PreserveFramePointer) == false && PreserveFramePointer == false ) {
494       vm_exit_during_initialization(err_msg("PreserveFramePointer cannot be disabled for ROP-protection"));
495     }
496     PreserveFramePointer = true;
497   }
498 
499 #ifdef COMPILER2
500   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
501     UseMultiplyToLenIntrinsic = true;
502   }
503 
504   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
505     UseSquareToLenIntrinsic = true;
506   }
507 
508   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
509     UseMulAddIntrinsic = true;
510   }
511 
512   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
513     UseMontgomeryMultiplyIntrinsic = true;
514   }
515   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
516     UseMontgomerySquareIntrinsic = true;
517   }
518 
519   if (UseSVE > 0) {
520     if (FLAG_IS_DEFAULT(MaxVectorSize)) {
521       MaxVectorSize = _initial_sve_vector_length;
522     } else if (MaxVectorSize < 16) {
523       warning("SVE does not support vector length less than 16 bytes. Disabling SVE.");
524       UseSVE = 0;
525     } else if ((MaxVectorSize % 16) == 0 && is_power_of_2(MaxVectorSize)) {
526       int new_vl = set_and_get_current_sve_vector_length(MaxVectorSize);
527       _initial_sve_vector_length = new_vl;
528       // Update MaxVectorSize to the largest supported value.
529       if (new_vl < 0) {
530         vm_exit_during_initialization(
531           err_msg("Current system does not support SVE vector length for MaxVectorSize: %d",
532                   (int)MaxVectorSize));
533       } else if (new_vl != MaxVectorSize) {
534         warning("Current system only supports max SVE vector length %d. Set MaxVectorSize to %d",
535                 new_vl, new_vl);
536       }
537       MaxVectorSize = new_vl;
538     } else {
539       vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
540     }
541   }
542 
543   if (UseSVE == 0) {  // NEON
544     int min_vector_size = 8;
545     int max_vector_size = 16;
546     if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
547       if (!is_power_of_2(MaxVectorSize)) {
548         vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
549       } else if (MaxVectorSize < min_vector_size) {
550         warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
551         FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
552       } else if (MaxVectorSize > max_vector_size) {
553         warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
554         FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
555       }
556     } else {
557       FLAG_SET_DEFAULT(MaxVectorSize, 16);
558     }
559   }
560 
561   int inline_size = (UseSVE > 0 && MaxVectorSize >= 16) ? MaxVectorSize : 0;
562   if (FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize)) {
563     FLAG_SET_DEFAULT(ArrayOperationPartialInlineSize, inline_size);
564   } else if (ArrayOperationPartialInlineSize != 0 && ArrayOperationPartialInlineSize != inline_size) {
565     warning("Setting ArrayOperationPartialInlineSize to %d", inline_size);
566     ArrayOperationPartialInlineSize = inline_size;
567   }
568 
569   if (FLAG_IS_DEFAULT(OptoScheduling)) {
570     OptoScheduling = true;
571   }
572 
573   if (FLAG_IS_DEFAULT(AlignVector)) {
574     AlignVector = AvoidUnalignedAccesses;
575   }
576 
577   if (FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
578     FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true);
579   }
580 #endif
581 
582   _spin_wait = get_spin_wait_desc();
583 
584   check_virtualizations();
585 }
586 
587 #if defined(LINUX)
588 static bool check_info_file(const char* fpath,
589                             const char* virt1, VirtualizationType vt1,
590                             const char* virt2, VirtualizationType vt2) {
591   char line[500];
592   FILE* fp = os::fopen(fpath, "r");
593   if (fp == nullptr) {
594     return false;
595   }
596   while (fgets(line, sizeof(line), fp) != nullptr) {
597     if (strcasestr(line, virt1) != 0) {
598       Abstract_VM_Version::_detected_virtualization = vt1;
599       fclose(fp);
600       return true;
601     }
602     if (virt2 != nullptr && strcasestr(line, virt2) != 0) {
603       Abstract_VM_Version::_detected_virtualization = vt2;
604       fclose(fp);
605       return true;
606     }
607   }
608   fclose(fp);
609   return false;
610 }
611 #endif
612 
613 void VM_Version::check_virtualizations() {
614 #if defined(LINUX)
615   const char* pname_file = "/sys/devices/virtual/dmi/id/product_name";
616   const char* tname_file = "/sys/hypervisor/type";
617   if (check_info_file(pname_file, "KVM", KVM, "VMWare", VMWare)) {
618     return;
619   }
620   check_info_file(tname_file, "Xen", XenPVHVM, nullptr, NoDetectedVirtualization);
621 #endif
622 }
623 
624 void VM_Version::print_platform_virtualization_info(outputStream* st) {
625 #if defined(LINUX)
626   VirtualizationType vrt = VM_Version::get_detected_virtualization();
627   if (vrt == KVM) {
628     st->print_cr("KVM virtualization detected");
629   } else if (vrt == VMWare) {
630     st->print_cr("VMWare virtualization detected");
631   } else if (vrt == XenPVHVM) {
632     st->print_cr("Xen virtualization detected");
633   }
634 #endif
635 }
636 
637 void VM_Version::initialize_cpu_information(void) {
638   // do nothing if cpu info has been initialized
639   if (_initialized) {
640     return;
641   }
642 
643   _no_of_cores  = os::processor_count();
644   _no_of_threads = _no_of_cores;
645   _no_of_sockets = _no_of_cores;
646   snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "AArch64");
647 
648   int desc_len = snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "AArch64 ");
649   get_compatible_board(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len);
650   desc_len = (int)strlen(_cpu_desc);
651   snprintf(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len, " %s", _features_string);
652 
653   _initialized = true;
654 }