26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
31 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
32 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"
33
34 #define __ masm->masm()->
35
36 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler *masm) {
37 __ block_comment("LIR_OpShenandoahCompareAndSwap (shenandaohgc) {");
38
39 Register addr = _addr->as_register_lo();
40 Register new_val = _new_value->as_register();
41 Register cmp_val = _cmp_value->as_register();
42 Register tmp1 = _tmp1->as_register();
43 Register tmp2 = _tmp2->as_register();
44 Register result = result_opr()->as_register();
45
46 if (ShenandoahIUBarrier) {
47 ShenandoahBarrierSet::assembler()->iu_barrier(masm->masm(), new_val, tmp1, tmp2,
48 MacroAssembler::PRESERVATION_FRAME_LR_GP_FP_REGS);
49 }
50
51 if (UseCompressedOops) {
52 __ encode_heap_oop(cmp_val, cmp_val);
53 __ encode_heap_oop(new_val, new_val);
54 }
55
56 // There might be a volatile load before this Unsafe CAS.
57 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
58 __ sync();
59 } else {
60 __ lwsync();
61 }
62
63 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmp_val, new_val, tmp1, tmp2,
64 false, result);
65
66 if (UseCompressedOops) {
67 __ decode_heap_oop(cmp_val);
68 __ decode_heap_oop(new_val);
69 }
70
90
91 if (access.is_oop()) {
92 LIRGenerator* gen = access.gen();
93
94 if (ShenandoahSATBBarrier) {
95 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
96 LIR_OprFact::illegalOpr);
97 }
98
99 if (ShenandoahCASBarrier) {
100 cmp_value.load_item();
101 new_value.load_item();
102
103 LIR_Opr t1 = gen->new_register(T_OBJECT);
104 LIR_Opr t2 = gen->new_register(T_OBJECT);
105 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
106 LIR_Opr result = gen->new_register(T_INT);
107
108 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));
109
110 return result;
111 }
112 }
113
114 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
115 }
116
117 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess &access, LIRItem &value) {
118 LIRGenerator* gen = access.gen();
119 BasicType type = access.type();
120
121 LIR_Opr result = gen->new_register(type);
122 value.load_item();
123 LIR_Opr value_opr = value.result();
124
125 if (access.is_oop()) {
126 value_opr = iu_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());
127 }
128
129 assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type");
130 LIR_Opr tmp_xchg = gen->new_register(T_INT);
131 __ xchg(access.resolved_addr(), value_opr, result, tmp_xchg);
132
133 if (access.is_oop()) {
134 result = load_reference_barrier_impl(access.gen(), result, LIR_OprFact::addressConst(0),
135 access.decorators());
136
137 LIR_Opr tmp_barrier = gen->new_register(type);
138 __ move(result, tmp_barrier);
139 result = tmp_barrier;
140
141 if (ShenandoahSATBBarrier) {
142 pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr, result);
143 }
144 }
145
146 return result;
147 }
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26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
31 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
32 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"
33
34 #define __ masm->masm()->
35
36 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler *masm) {
37 __ block_comment("LIR_OpShenandoahCompareAndSwap (shenandaohgc) {");
38
39 Register addr = _addr->as_register_lo();
40 Register new_val = _new_value->as_register();
41 Register cmp_val = _cmp_value->as_register();
42 Register tmp1 = _tmp1->as_register();
43 Register tmp2 = _tmp2->as_register();
44 Register result = result_opr()->as_register();
45
46 if (UseCompressedOops) {
47 __ encode_heap_oop(cmp_val, cmp_val);
48 __ encode_heap_oop(new_val, new_val);
49 }
50
51 // There might be a volatile load before this Unsafe CAS.
52 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
53 __ sync();
54 } else {
55 __ lwsync();
56 }
57
58 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmp_val, new_val, tmp1, tmp2,
59 false, result);
60
61 if (UseCompressedOops) {
62 __ decode_heap_oop(cmp_val);
63 __ decode_heap_oop(new_val);
64 }
65
85
86 if (access.is_oop()) {
87 LIRGenerator* gen = access.gen();
88
89 if (ShenandoahSATBBarrier) {
90 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
91 LIR_OprFact::illegalOpr);
92 }
93
94 if (ShenandoahCASBarrier) {
95 cmp_value.load_item();
96 new_value.load_item();
97
98 LIR_Opr t1 = gen->new_register(T_OBJECT);
99 LIR_Opr t2 = gen->new_register(T_OBJECT);
100 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
101 LIR_Opr result = gen->new_register(T_INT);
102
103 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));
104
105 if (ShenandoahCardBarrier) {
106 post_barrier(access, access.resolved_addr(), new_value.result());
107 }
108
109 return result;
110 }
111 }
112
113 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
114 }
115
116 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess &access, LIRItem &value) {
117 LIRGenerator* gen = access.gen();
118 BasicType type = access.type();
119
120 LIR_Opr result = gen->new_register(type);
121 value.load_item();
122 LIR_Opr value_opr = value.result();
123
124 assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type");
125 LIR_Opr tmp_xchg = gen->new_register(T_INT);
126 __ xchg(access.resolved_addr(), value_opr, result, tmp_xchg);
127
128 if (access.is_oop()) {
129 result = load_reference_barrier_impl(access.gen(), result, LIR_OprFact::addressConst(0),
130 access.decorators());
131
132 LIR_Opr tmp_barrier = gen->new_register(type);
133 __ move(result, tmp_barrier);
134 result = tmp_barrier;
135
136 if (ShenandoahSATBBarrier) {
137 pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr, result);
138 }
139
140 if (ShenandoahCardBarrier) {
141 post_barrier(access, access.resolved_addr(), result);
142 }
143 }
144
145 return result;
146 }
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