1 /*
2 * Copyright (c) 2018, 2021, Red Hat, Inc. All rights reserved.
3 * Copyright Amazon.com Inc. or its affiliates. All Rights Reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "gc/shared/gc_globals.hpp"
30 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
31 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
32 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"
33
34 #define __ masm->masm()->
35
36 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) {
37 NOT_LP64(assert(_addr->is_single_cpu(), "must be single");)
38 Register addr = _addr->is_single_cpu() ? _addr->as_register() : _addr->as_register_lo();
39 Register newval = _new_value->as_register();
40 Register cmpval = _cmp_value->as_register();
41 Register tmp1 = _tmp1->as_register();
42 Register tmp2 = _tmp2->as_register();
43 Register result = result_opr()->as_register();
44 assert(cmpval == rax, "wrong register");
45 assert(newval != noreg, "new val must be register");
46 assert(cmpval != newval, "cmp and new values must be in different registers");
47 assert(cmpval != addr, "cmp and addr must be in different registers");
48 assert(newval != addr, "new value and addr must be in different registers");
49
50 // Apply IU barrier to newval.
51 ShenandoahBarrierSet::assembler()->iu_barrier(masm->masm(), newval, tmp1);
52
53 #ifdef _LP64
54 if (UseCompressedOops) {
55 __ encode_heap_oop(cmpval);
56 __ mov(rscratch1, newval);
57 __ encode_heap_oop(rscratch1);
58 newval = rscratch1;
59 }
60 #endif
61
62 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), result, Address(addr, 0), cmpval, newval, false, tmp1, tmp2);
63 }
64
65 #undef __
66
67 #ifdef ASSERT
68 #define __ gen->lir(__FILE__, __LINE__)->
69 #else
70 #define __ gen->lir()->
71 #endif
72
73 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {
74
75 if (access.is_oop()) {
76 LIRGenerator* gen = access.gen();
77 if (ShenandoahSATBBarrier) {
78 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
79 LIR_OprFact::illegalOpr /* pre_val */);
80 }
81 if (ShenandoahCASBarrier) {
82 cmp_value.load_item_force(FrameMap::rax_oop_opr);
83 new_value.load_item();
84
85 LIR_Opr t1 = gen->new_register(T_OBJECT);
86 LIR_Opr t2 = gen->new_register(T_OBJECT);
87 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
88 LIR_Opr result = gen->new_register(T_INT);
89
90 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));
91
92 if (ShenandoahCardBarrier) {
93 post_barrier(access, access.resolved_addr(), new_value.result());
94 }
95 return result;
96 }
97 }
98 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
99 }
100
101 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) {
102 LIRGenerator* gen = access.gen();
103 BasicType type = access.type();
104
105 LIR_Opr result = gen->new_register(type);
106 value.load_item();
107 LIR_Opr value_opr = value.result();
108
109 if (access.is_oop()) {
110 value_opr = iu_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());
111 }
112
113 // Because we want a 2-arg form of xchg and xadd
114 __ move(value_opr, result);
115
116 assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type");
117 __ xchg(access.resolved_addr(), result, result, LIR_OprFact::illegalOpr);
118
119 if (access.is_oop()) {
120 result = load_reference_barrier(access.gen(), result, LIR_OprFact::addressConst(0), access.decorators());
121 LIR_Opr tmp = gen->new_register(type);
122 __ move(result, tmp);
123 result = tmp;
124 if (ShenandoahSATBBarrier) {
125 pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr,
126 result /* pre_val */);
127 }
128 if (ShenandoahCardBarrier) {
129 post_barrier(access, access.resolved_addr(), result);
130 }
131 }
132
133 return result;
134 }