1 /*
   2  * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2020 Red Hat Inc. All rights reserved.
   4  * reserved.  DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE
   5  * HEADER.
   6  *
   7  * This code is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 only, as
   9  * published by the Free Software Foundation.
  10  *
  11  * This code is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * version 2 for more details (a copy is included in the LICENSE file that
  15  * accompanied this code).
  16  *
  17  * You should have received a copy of the GNU General Public License version
  18  * 2 along with this work; if not, write to the Free Software Foundation,
  19  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  20  *
  21  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  22  * or visit www.oracle.com if you need additional information or have any
  23  * questions.
  24  *
  25  */
  26 
  27 #include <stdio.h>
  28 #include <sys/types.h>
  29 
  30 #include "precompiled.hpp"
  31 #include "asm/assembler.hpp"
  32 #include "asm/assembler.inline.hpp"
  33 #include "interpreter/interpreter.hpp"
  34 
  35 #ifndef PRODUCT
  36 const unsigned long Assembler::asm_bp = 0x0000007fa8092b5c;
  37 #endif
  38 
  39 #include "compiler/disassembler.hpp"
  40 #include "memory/resourceArea.hpp"
  41 #include "runtime/interfaceSupport.hpp"
  42 #include "runtime/sharedRuntime.hpp"
  43 #include "immediate_aarch64.hpp"
  44 
  45 // #include "gc_interface/collectedHeap.inline.hpp"
  46 // #include "interpreter/interpreter.hpp"
  47 // #include "memory/cardTableModRefBS.hpp"
  48 // #include "prims/methodHandles.hpp"
  49 // #include "runtime/biasedLocking.hpp"
  50 // #include "runtime/interfaceSupport.hpp"
  51 // #include "runtime/objectMonitor.hpp"
  52 // #include "runtime/os.hpp"
  53 // #include "runtime/sharedRuntime.hpp"
  54 // #include "runtime/stubRoutines.hpp"
  55 // #if INCLUDE_ALL_GCS
  56 // #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
  57 // #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
  58 // #include "gc_implementation/g1/heapRegion.hpp"
  59 // #endif
  60 
  61 
  62 extern "C" void entry(CodeBuffer *cb);
  63 
  64 #define __ _masm.
  65 #ifdef PRODUCT
  66 #define BLOCK_COMMENT(str) /* nothing */
  67 #else
  68 #define BLOCK_COMMENT(str) block_comment(str)
  69 #endif
  70 
  71 #define BIND(label) bind(label); __ BLOCK_COMMENT(#label ":")
  72 
  73 static float unpack(unsigned value);
  74 
  75 #ifdef ASSERT
  76 
  77 void entry(CodeBuffer *cb) {
  78 
  79   // {
  80   //   for (int i = 0; i < 256; i+=16)
  81   //     {
  82   //    printf("\"%20.20g\", ", unpack(i));
  83   //    printf("\"%20.20g\", ", unpack(i+1));
  84   //     }
  85   //   printf("\n");
  86   // }
  87 
  88   Assembler _masm(cb);
  89   address entry = __ pc();
  90 
  91   // Smoke test for assembler
  92 
  93 // BEGIN  Generated code -- do not edit
  94 // Generated by aarch64-asmtest.py
  95     Label back, forth;
  96     __ bind(back);
  97 
  98 // ArithOp
  99     __ add(r19, r22, r7, Assembler::LSL, 28);          //       add     x19, x22, x7, LSL #28
 100     __ sub(r16, r11, r10, Assembler::LSR, 13);         //       sub     x16, x11, x10, LSR #13
 101     __ adds(r27, r13, r28, Assembler::ASR, 2);         //       adds    x27, x13, x28, ASR #2
 102     __ subs(r20, r28, r26, Assembler::ASR, 41);        //       subs    x20, x28, x26, ASR #41
 103     __ addw(r8, r19, r19, Assembler::ASR, 19);         //       add     w8, w19, w19, ASR #19
 104     __ subw(r4, r9, r10, Assembler::LSL, 14);          //       sub     w4, w9, w10, LSL #14
 105     __ addsw(r8, r11, r30, Assembler::LSL, 13);        //       adds    w8, w11, w30, LSL #13
 106     __ subsw(r0, r25, r19, Assembler::LSL, 9);         //       subs    w0, w25, w19, LSL #9
 107     __ andr(r20, r0, r21, Assembler::LSL, 19);         //       and     x20, x0, x21, LSL #19
 108     __ orr(r21, r14, r20, Assembler::LSL, 17);         //       orr     x21, x14, x20, LSL #17
 109     __ eor(r25, r28, r1, Assembler::LSL, 51);          //       eor     x25, x28, x1, LSL #51
 110     __ ands(r10, r27, r11, Assembler::ASR, 15);        //       ands    x10, x27, x11, ASR #15
 111     __ andw(r25, r5, r12, Assembler::ASR, 23);         //       and     w25, w5, w12, ASR #23
 112     __ orrw(r18, r14, r10, Assembler::LSR, 4);         //       orr     w18, w14, w10, LSR #4
 113     __ eorw(r4, r21, r5, Assembler::ASR, 22);          //       eor     w4, w21, w5, ASR #22
 114     __ andsw(r21, r0, r5, Assembler::ASR, 29);         //       ands    w21, w0, w5, ASR #29
 115     __ bic(r26, r30, r6, Assembler::ASR, 37);          //       bic     x26, x30, x6, ASR #37
 116     __ orn(r3, r1, r13, Assembler::LSR, 29);           //       orn     x3, x1, x13, LSR #29
 117     __ eon(r0, r28, r9, Assembler::LSL, 47);           //       eon     x0, x28, x9, LSL #47
 118     __ bics(r29, r5, r28, Assembler::LSL, 46);         //       bics    x29, x5, x28, LSL #46
 119     __ bicw(r9, r18, r7, Assembler::LSR, 20);          //       bic     w9, w18, w7, LSR #20
 120     __ ornw(r26, r13, r25, Assembler::ASR, 24);        //       orn     w26, w13, w25, ASR #24
 121     __ eonw(r25, r4, r19, Assembler::LSL, 6);          //       eon     w25, w4, w19, LSL #6
 122     __ bicsw(r5, r26, r4, Assembler::LSR, 24);         //       bics    w5, w26, w4, LSR #24
 123 
 124 // AddSubImmOp
 125     __ addw(r7, r19, 340u);                            //       add     w7, w19, #340
 126     __ addsw(r8, r0, 401u);                            //       adds    w8, w0, #401
 127     __ subw(r29, r20, 163u);                           //       sub     w29, w20, #163
 128     __ subsw(r8, r23, 759u);                           //       subs    w8, w23, #759
 129     __ add(r1, r12, 523u);                             //       add     x1, x12, #523
 130     __ adds(r2, r11, 426u);                            //       adds    x2, x11, #426
 131     __ sub(r14, r29, 716u);                            //       sub     x14, x29, #716
 132     __ subs(r11, r5, 582u);                            //       subs    x11, x5, #582
 133 
 134 // LogicalImmOp
 135     __ andw(r23, r22, 32768ul);                        //       and     w23, w22, #0x8000
 136     __ orrw(r4, r10, 4042322160ul);                    //       orr     w4, w10, #0xf0f0f0f0
 137     __ eorw(r0, r24, 4042322160ul);                    //       eor     w0, w24, #0xf0f0f0f0
 138     __ andsw(r19, r29, 2139127680ul);                  //       ands    w19, w29, #0x7f807f80
 139     __ andr(r5, r10, 4503599627354112ul);              //       and     x5, x10, #0xfffffffffc000
 140     __ orr(r12, r30, 18445618178097414144ul);          //       orr     x12, x30, #0xfffc0000fffc0000
 141     __ eor(r30, r5, 262128ul);                         //       eor     x30, x5, #0x3fff0
 142     __ ands(r26, r23, 4194300ul);                      //       ands    x26, x23, #0x3ffffc
 143 
 144 // AbsOp
 145     __ b(__ pc());                                     //       b       .
 146     __ b(back);                                        //       b       back
 147     __ b(forth);                                       //       b       forth
 148     __ bl(__ pc());                                    //       bl      .
 149     __ bl(back);                                       //       bl      back
 150     __ bl(forth);                                      //       bl      forth
 151 
 152 // RegAndAbsOp
 153     __ cbzw(r12, __ pc());                             //       cbz     w12, .
 154     __ cbzw(r12, back);                                //       cbz     w12, back
 155     __ cbzw(r12, forth);                               //       cbz     w12, forth
 156     __ cbnzw(r20, __ pc());                            //       cbnz    w20, .
 157     __ cbnzw(r20, back);                               //       cbnz    w20, back
 158     __ cbnzw(r20, forth);                              //       cbnz    w20, forth
 159     __ cbz(r12, __ pc());                              //       cbz     x12, .
 160     __ cbz(r12, back);                                 //       cbz     x12, back
 161     __ cbz(r12, forth);                                //       cbz     x12, forth
 162     __ cbnz(r24, __ pc());                             //       cbnz    x24, .
 163     __ cbnz(r24, back);                                //       cbnz    x24, back
 164     __ cbnz(r24, forth);                               //       cbnz    x24, forth
 165     __ adr(r6, __ pc());                               //       adr     x6, .
 166     __ adr(r6, back);                                  //       adr     x6, back
 167     __ adr(r6, forth);                                 //       adr     x6, forth
 168     __ _adrp(r21, __ pc());                             //      adrp    x21, .
 169 
 170 // RegImmAbsOp
 171     __ tbz(r1, 1, __ pc());                            //       tbz     x1, #1, .
 172     __ tbz(r1, 1, back);                               //       tbz     x1, #1, back
 173     __ tbz(r1, 1, forth);                              //       tbz     x1, #1, forth
 174     __ tbnz(r8, 9, __ pc());                           //       tbnz    x8, #9, .
 175     __ tbnz(r8, 9, back);                              //       tbnz    x8, #9, back
 176     __ tbnz(r8, 9, forth);                             //       tbnz    x8, #9, forth
 177 
 178 // MoveWideImmOp
 179     __ movnw(r12, 23175, 0);                           //       movn    w12, #23175, lsl 0
 180     __ movzw(r11, 20476, 16);                          //       movz    w11, #20476, lsl 16
 181     __ movkw(r21, 3716, 0);                            //       movk    w21, #3716, lsl 0
 182     __ movn(r29, 28661, 48);                           //       movn    x29, #28661, lsl 48
 183     __ movz(r3, 6927, 0);                              //       movz    x3, #6927, lsl 0
 184     __ movk(r22, 9828, 16);                            //       movk    x22, #9828, lsl 16
 185 
 186 // BitfieldOp
 187     __ sbfm(r12, r8, 6, 22);                           //       sbfm    x12, x8, #6, #22
 188     __ bfmw(r19, r25, 25, 19);                         //       bfm     w19, w25, #25, #19
 189     __ ubfmw(r9, r12, 29, 15);                         //       ubfm    w9, w12, #29, #15
 190     __ sbfm(r28, r25, 16, 16);                         //       sbfm    x28, x25, #16, #16
 191     __ bfm(r12, r5, 4, 25);                            //       bfm     x12, x5, #4, #25
 192     __ ubfm(r0, r10, 6, 8);                            //       ubfm    x0, x10, #6, #8
 193 
 194 // ExtractOp
 195     __ extrw(r4, r13, r26, 24);                        //       extr    w4, w13, w26, #24
 196     __ extr(r23, r30, r24, 31);                        //       extr    x23, x30, x24, #31
 197 
 198 // CondBranchOp
 199     __ br(Assembler::EQ, __ pc());                     //       b.EQ    .
 200     __ br(Assembler::EQ, back);                        //       b.EQ    back
 201     __ br(Assembler::EQ, forth);                       //       b.EQ    forth
 202     __ br(Assembler::NE, __ pc());                     //       b.NE    .
 203     __ br(Assembler::NE, back);                        //       b.NE    back
 204     __ br(Assembler::NE, forth);                       //       b.NE    forth
 205     __ br(Assembler::HS, __ pc());                     //       b.HS    .
 206     __ br(Assembler::HS, back);                        //       b.HS    back
 207     __ br(Assembler::HS, forth);                       //       b.HS    forth
 208     __ br(Assembler::CS, __ pc());                     //       b.CS    .
 209     __ br(Assembler::CS, back);                        //       b.CS    back
 210     __ br(Assembler::CS, forth);                       //       b.CS    forth
 211     __ br(Assembler::LO, __ pc());                     //       b.LO    .
 212     __ br(Assembler::LO, back);                        //       b.LO    back
 213     __ br(Assembler::LO, forth);                       //       b.LO    forth
 214     __ br(Assembler::CC, __ pc());                     //       b.CC    .
 215     __ br(Assembler::CC, back);                        //       b.CC    back
 216     __ br(Assembler::CC, forth);                       //       b.CC    forth
 217     __ br(Assembler::MI, __ pc());                     //       b.MI    .
 218     __ br(Assembler::MI, back);                        //       b.MI    back
 219     __ br(Assembler::MI, forth);                       //       b.MI    forth
 220     __ br(Assembler::PL, __ pc());                     //       b.PL    .
 221     __ br(Assembler::PL, back);                        //       b.PL    back
 222     __ br(Assembler::PL, forth);                       //       b.PL    forth
 223     __ br(Assembler::VS, __ pc());                     //       b.VS    .
 224     __ br(Assembler::VS, back);                        //       b.VS    back
 225     __ br(Assembler::VS, forth);                       //       b.VS    forth
 226     __ br(Assembler::VC, __ pc());                     //       b.VC    .
 227     __ br(Assembler::VC, back);                        //       b.VC    back
 228     __ br(Assembler::VC, forth);                       //       b.VC    forth
 229     __ br(Assembler::HI, __ pc());                     //       b.HI    .
 230     __ br(Assembler::HI, back);                        //       b.HI    back
 231     __ br(Assembler::HI, forth);                       //       b.HI    forth
 232     __ br(Assembler::LS, __ pc());                     //       b.LS    .
 233     __ br(Assembler::LS, back);                        //       b.LS    back
 234     __ br(Assembler::LS, forth);                       //       b.LS    forth
 235     __ br(Assembler::GE, __ pc());                     //       b.GE    .
 236     __ br(Assembler::GE, back);                        //       b.GE    back
 237     __ br(Assembler::GE, forth);                       //       b.GE    forth
 238     __ br(Assembler::LT, __ pc());                     //       b.LT    .
 239     __ br(Assembler::LT, back);                        //       b.LT    back
 240     __ br(Assembler::LT, forth);                       //       b.LT    forth
 241     __ br(Assembler::GT, __ pc());                     //       b.GT    .
 242     __ br(Assembler::GT, back);                        //       b.GT    back
 243     __ br(Assembler::GT, forth);                       //       b.GT    forth
 244     __ br(Assembler::LE, __ pc());                     //       b.LE    .
 245     __ br(Assembler::LE, back);                        //       b.LE    back
 246     __ br(Assembler::LE, forth);                       //       b.LE    forth
 247     __ br(Assembler::AL, __ pc());                     //       b.AL    .
 248     __ br(Assembler::AL, back);                        //       b.AL    back
 249     __ br(Assembler::AL, forth);                       //       b.AL    forth
 250     __ br(Assembler::NV, __ pc());                     //       b.NV    .
 251     __ br(Assembler::NV, back);                        //       b.NV    back
 252     __ br(Assembler::NV, forth);                       //       b.NV    forth
 253 
 254 // ImmOp
 255     __ svc(12729);                                     //       svc     #12729
 256     __ hvc(6788);                                      //       hvc     #6788
 257     __ smc(1535);                                      //       smc     #1535
 258     __ brk(16766);                                     //       brk     #16766
 259     __ hlt(9753);                                      //       hlt     #9753
 260 
 261 // Op
 262     __ nop();                                          //       nop     
 263     __ eret();                                         //       eret    
 264     __ drps();                                         //       drps    
 265     __ isb();                                          //       isb     
 266 
 267 // SystemOp
 268     __ dsb(Assembler::SY);                             //       dsb     SY
 269     __ dmb(Assembler::ISHST);                          //       dmb     ISHST
 270 
 271 // OneRegOp
 272     __ br(r2);                                         //       br      x2
 273     __ blr(r5);                                        //       blr     x5
 274 
 275 // LoadStoreExclusiveOp
 276     __ stxr(r20, r21, r2);                             //       stxr    w20, x21, [x2]
 277     __ stlxr(r5, r29, r7);                             //       stlxr   w5, x29, [x7]
 278     __ ldxr(r5, r16);                                  //       ldxr    x5, [x16]
 279     __ ldaxr(r27, r29);                                //       ldaxr   x27, [x29]
 280     __ stlr(r0, r29);                                  //       stlr    x0, [x29]
 281     __ ldar(r21, r28);                                 //       ldar    x21, [x28]
 282 
 283 // LoadStoreExclusiveOp
 284     __ stxrw(r21, r24, r7);                            //       stxr    w21, w24, [x7]
 285     __ stlxrw(r21, r26, r28);                          //       stlxr   w21, w26, [x28]
 286     __ ldxrw(r21, r6);                                 //       ldxr    w21, [x6]
 287     __ ldaxrw(r15, r30);                               //       ldaxr   w15, [x30]
 288     __ stlrw(r19, r3);                                 //       stlr    w19, [x3]
 289     __ ldarw(r22, r2);                                 //       ldar    w22, [x2]
 290 
 291 // LoadStoreExclusiveOp
 292     __ stxrh(r18, r15, r0);                            //       stxrh   w18, w15, [x0]
 293     __ stlxrh(r11, r5, r28);                           //       stlxrh  w11, w5, [x28]
 294     __ ldxrh(r29, r6);                                 //       ldxrh   w29, [x6]
 295     __ ldaxrh(r18, r7);                                //       ldaxrh  w18, [x7]
 296     __ stlrh(r25, r28);                                //       stlrh   w25, [x28]
 297     __ ldarh(r2, r19);                                 //       ldarh   w2, [x19]
 298 
 299 // LoadStoreExclusiveOp
 300     __ stxrb(r10, r30, r1);                            //       stxrb   w10, w30, [x1]
 301     __ stlxrb(r20, r21, r22);                          //       stlxrb  w20, w21, [x22]
 302     __ ldxrb(r25, r2);                                 //       ldxrb   w25, [x2]
 303     __ ldaxrb(r24, r5);                                //       ldaxrb  w24, [x5]
 304     __ stlrb(r16, r3);                                 //       stlrb   w16, [x3]
 305     __ ldarb(r22, r29);                                //       ldarb   w22, [x29]
 306 
 307 // LoadStoreExclusiveOp
 308     __ ldxp(r8, r2, r19);                              //       ldxp    x8, x2, [x19]
 309     __ ldaxp(r7, r19, r14);                            //       ldaxp   x7, x19, [x14]
 310     __ stxp(r8, r27, r28, r5);                         //       stxp    w8, x27, x28, [x5]
 311     __ stlxp(r5, r8, r14, r6);                         //       stlxp   w5, x8, x14, [x6]
 312 
 313 // LoadStoreExclusiveOp
 314     __ ldxpw(r25, r4, r22);                            //       ldxp    w25, w4, [x22]
 315     __ ldaxpw(r13, r14, r15);                          //       ldaxp   w13, w14, [x15]
 316     __ stxpw(r20, r26, r8, r10);                       //       stxp    w20, w26, w8, [x10]
 317     __ stlxpw(r23, r18, r18, r18);                     //       stlxp   w23, w18, w18, [x18]
 318 
 319 // base_plus_unscaled_offset 
 320 // LoadStoreOp
 321     __ str(r30, Address(r11, 99));                     //       str     x30, [x11, 99]
 322     __ strw(r23, Address(r25, -77));                   //       str     w23, [x25, -77]
 323     __ strb(r2, Address(r14, 3));                      //       strb    w2, [x14, 3]
 324     __ strh(r9, Address(r10, 5));                      //       strh    w9, [x10, 5]
 325     __ ldr(r20, Address(r15, 57));                     //       ldr     x20, [x15, 57]
 326     __ ldrw(r12, Address(r16, -78));                   //       ldr     w12, [x16, -78]
 327     __ ldrb(r22, Address(r26, -3));                    //       ldrb    w22, [x26, -3]
 328     __ ldrh(r30, Address(r19, -47));                   //       ldrh    w30, [x19, -47]
 329     __ ldrsb(r9, Address(r10, -12));                   //       ldrsb   x9, [x10, -12]
 330     __ ldrsh(r28, Address(r17, 14));                   //       ldrsh   x28, [x17, 14]
 331     __ ldrshw(r3, Address(r5, 10));                    //       ldrsh   w3, [x5, 10]
 332     __ ldrsw(r17, Address(r17, -91));                  //       ldrsw   x17, [x17, -91]
 333     __ ldrd(v2, Address(r20, -17));                    //       ldr     d2, [x20, -17]
 334     __ ldrs(v22, Address(r7, -10));                    //       ldr     s22, [x7, -10]
 335     __ strd(v30, Address(r18, -223));                  //       str     d30, [x18, -223]
 336     __ strs(v13, Address(r22, 21));                    //       str     s13, [x22, 21]
 337 
 338 // pre 
 339 // LoadStoreOp
 340     __ str(r9, Address(__ pre(r18, -112)));            //       str     x9, [x18, -112]!
 341     __ strw(r29, Address(__ pre(r23, 11)));            //       str     w29, [x23, 11]!
 342     __ strb(r18, Address(__ pre(r12, -1)));            //       strb    w18, [x12, -1]!
 343     __ strh(r16, Address(__ pre(r20, -23)));           //       strh    w16, [x20, -23]!
 344     __ ldr(r3, Address(__ pre(r29, 9)));               //       ldr     x3, [x29, 9]!
 345     __ ldrw(r25, Address(__ pre(r3, 19)));             //       ldr     w25, [x3, 19]!
 346     __ ldrb(r1, Address(__ pre(r29, -1)));             //       ldrb    w1, [x29, -1]!
 347     __ ldrh(r8, Address(__ pre(r29, -57)));            //       ldrh    w8, [x29, -57]!
 348     __ ldrsb(r5, Address(__ pre(r14, -13)));           //       ldrsb   x5, [x14, -13]!
 349     __ ldrsh(r10, Address(__ pre(r27, 1)));            //       ldrsh   x10, [x27, 1]!
 350     __ ldrshw(r11, Address(__ pre(r10, 25)));          //       ldrsh   w11, [x10, 25]!
 351     __ ldrsw(r4, Address(__ pre(r22, -92)));           //       ldrsw   x4, [x22, -92]!
 352     __ ldrd(v11, Address(__ pre(r23, 8)));             //       ldr     d11, [x23, 8]!
 353     __ ldrs(v25, Address(__ pre(r19, 54)));            //       ldr     s25, [x19, 54]!
 354     __ strd(v1, Address(__ pre(r7, -174)));            //       str     d1, [x7, -174]!
 355     __ strs(v8, Address(__ pre(r25, 54)));             //       str     s8, [x25, 54]!
 356 
 357 // post 
 358 // LoadStoreOp
 359     __ str(r5, Address(__ post(r11, 37)));             //       str     x5, [x11], 37
 360     __ strw(r24, Address(__ post(r15, 19)));           //       str     w24, [x15], 19
 361     __ strb(r15, Address(__ post(r26, -1)));           //       strb    w15, [x26], -1
 362     __ strh(r18, Address(__ post(r18, -6)));           //       strh    w18, [x18], -6
 363     __ ldr(r7, Address(__ post(r2, -230)));            //       ldr     x7, [x2], -230
 364     __ ldrw(r27, Address(__ post(r11, -27)));          //       ldr     w27, [x11], -27
 365     __ ldrb(r18, Address(__ post(r3, -25)));           //       ldrb    w18, [x3], -25
 366     __ ldrh(r10, Address(__ post(r24, -32)));          //       ldrh    w10, [x24], -32
 367     __ ldrsb(r22, Address(__ post(r10, 4)));           //       ldrsb   x22, [x10], 4
 368     __ ldrsh(r17, Address(__ post(r12, 25)));          //       ldrsh   x17, [x12], 25
 369     __ ldrshw(r8, Address(__ post(r7, -62)));          //       ldrsh   w8, [x7], -62
 370     __ ldrsw(r23, Address(__ post(r22, -51)));         //       ldrsw   x23, [x22], -51
 371     __ ldrd(v24, Address(__ post(r25, 48)));           //       ldr     d24, [x25], 48
 372     __ ldrs(v21, Address(__ post(r12, -10)));          //       ldr     s21, [x12], -10
 373     __ strd(v18, Address(__ post(r13, -222)));         //       str     d18, [x13], -222
 374     __ strs(v16, Address(__ post(r1, -41)));           //       str     s16, [x1], -41
 375 
 376 // base_plus_reg 
 377 // LoadStoreOp
 378     __ str(r2, Address(r22, r15, Address::sxtw(0)));   //       str     x2, [x22, w15, sxtw #0]
 379     __ strw(r2, Address(r16, r29, Address::lsl(0)));   //       str     w2, [x16, x29, lsl #0]
 380     __ strb(r20, Address(r18, r14, Address::uxtw(0))); //       strb    w20, [x18, w14, uxtw #0]
 381     __ strh(r6, Address(r19, r20, Address::sxtx(1)));  //       strh    w6, [x19, x20, sxtx #1]
 382     __ ldr(r14, Address(r29, r14, Address::sxtw(0)));  //       ldr     x14, [x29, w14, sxtw #0]
 383     __ ldrw(r16, Address(r20, r12, Address::sxtw(2))); //       ldr     w16, [x20, w12, sxtw #2]
 384     __ ldrb(r9, Address(r12, r0, Address::sxtw(0)));   //       ldrb    w9, [x12, w0, sxtw #0]
 385     __ ldrh(r12, Address(r17, r3, Address::lsl(1)));   //       ldrh    w12, [x17, x3, lsl #1]
 386     __ ldrsb(r2, Address(r17, r3, Address::sxtx(0)));  //       ldrsb   x2, [x17, x3, sxtx #0]
 387     __ ldrsh(r7, Address(r1, r17, Address::uxtw(1)));  //       ldrsh   x7, [x1, w17, uxtw #1]
 388     __ ldrshw(r25, Address(r15, r18, Address::sxtw(1))); //     ldrsh   w25, [x15, w18, sxtw #1]
 389     __ ldrsw(r23, Address(r21, r12, Address::lsl(0))); //       ldrsw   x23, [x21, x12, lsl #0]
 390     __ ldrd(v5, Address(r13, r8, Address::lsl(3)));    //       ldr     d5, [x13, x8, lsl #3]
 391     __ ldrs(v3, Address(r10, r22, Address::lsl(2)));   //       ldr     s3, [x10, x22, lsl #2]
 392     __ strd(v14, Address(r2, r27, Address::sxtw(0)));  //       str     d14, [x2, w27, sxtw #0]
 393     __ strs(v20, Address(r6, r25, Address::lsl(0)));   //       str     s20, [x6, x25, lsl #0]
 394 
 395 // base_plus_scaled_offset 
 396 // LoadStoreOp
 397     __ str(r30, Address(r7, 16256));                   //       str     x30, [x7, 16256]
 398     __ strw(r15, Address(r8, 7588));                   //       str     w15, [x8, 7588]
 399     __ strb(r11, Address(r0, 1866));                   //       strb    w11, [x0, 1866]
 400     __ strh(r3, Address(r17, 3734));                   //       strh    w3, [x17, 3734]
 401     __ ldr(r2, Address(r7, 14224));                    //       ldr     x2, [x7, 14224]
 402     __ ldrw(r5, Address(r9, 7396));                    //       ldr     w5, [x9, 7396]
 403     __ ldrb(r28, Address(r9, 1721));                   //       ldrb    w28, [x9, 1721]
 404     __ ldrh(r2, Address(r20, 3656));                   //       ldrh    w2, [x20, 3656]
 405     __ ldrsb(r22, Address(r14, 1887));                 //       ldrsb   x22, [x14, 1887]
 406     __ ldrsh(r8, Address(r0, 4080));                   //       ldrsh   x8, [x0, 4080]
 407     __ ldrshw(r0, Address(r30, 3916));                 //       ldrsh   w0, [x30, 3916]
 408     __ ldrsw(r24, Address(r19, 6828));                 //       ldrsw   x24, [x19, 6828]
 409     __ ldrd(v24, Address(r12, 13032));                 //       ldr     d24, [x12, 13032]
 410     __ ldrs(v8, Address(r8, 7452));                    //       ldr     s8, [x8, 7452]
 411     __ strd(v10, Address(r15, 15992));                 //       str     d10, [x15, 15992]
 412     __ strs(v26, Address(r19, 6688));                  //       str     s26, [x19, 6688]
 413 
 414 // pcrel 
 415 // LoadStoreOp
 416     __ ldr(r10, forth);                                //       ldr     x10, forth
 417     __ ldrw(r3, __ pc());                              //       ldr     w3, .
 418 
 419 // LoadStoreOp
 420     __ prfm(Address(r23, 9));                          //       prfm    PLDL1KEEP, [x23, 9]
 421 
 422 // LoadStoreOp
 423     __ prfm(back);                                     //       prfm    PLDL1KEEP, back
 424 
 425 // LoadStoreOp
 426     __ prfm(Address(r3, r8, Address::uxtw(0)));        //       prfm    PLDL1KEEP, [x3, w8, uxtw #0]
 427 
 428 // LoadStoreOp
 429     __ prfm(Address(r11, 15080));                      //       prfm    PLDL1KEEP, [x11, 15080]
 430 
 431 // AddSubCarryOp
 432     __ adcw(r13, r9, r28);                             //       adc     w13, w9, w28
 433     __ adcsw(r27, r19, r28);                           //       adcs    w27, w19, w28
 434     __ sbcw(r19, r18, r6);                             //       sbc     w19, w18, w6
 435     __ sbcsw(r14, r20, r3);                            //       sbcs    w14, w20, w3
 436     __ adc(r16, r14, r8);                              //       adc     x16, x14, x8
 437     __ adcs(r0, r29, r8);                              //       adcs    x0, x29, x8
 438     __ sbc(r8, r24, r20);                              //       sbc     x8, x24, x20
 439     __ sbcs(r12, r28, r0);                             //       sbcs    x12, x28, x0
 440 
 441 // AddSubExtendedOp
 442     __ addw(r23, r6, r16, ext::uxtb, 4);               //       add     w23, w6, w16, uxtb #4
 443     __ addsw(r25, r25, r23, ext::sxth, 2);             //       adds    w25, w25, w23, sxth #2
 444     __ sub(r26, r22, r4, ext::uxtx, 1);                //       sub     x26, x22, x4, uxtx #1
 445     __ subsw(r17, r29, r19, ext::sxtx, 3);             //       subs    w17, w29, w19, sxtx #3
 446     __ add(r11, r30, r21, ext::uxtb, 3);               //       add     x11, x30, x21, uxtb #3
 447     __ adds(r16, r19, r0, ext::sxtb, 2);               //       adds    x16, x19, x0, sxtb #2
 448     __ sub(r11, r9, r25, ext::sxtx, 1);                //       sub     x11, x9, x25, sxtx #1
 449     __ subs(r17, r20, r12, ext::sxtb, 4);              //       subs    x17, x20, x12, sxtb #4
 450 
 451 // ConditionalCompareOp
 452     __ ccmnw(r13, r11, 3u, Assembler::LE);             //       ccmn    w13, w11, #3, LE
 453     __ ccmpw(r13, r12, 2u, Assembler::HI);             //       ccmp    w13, w12, #2, HI
 454     __ ccmn(r3, r2, 12u, Assembler::NE);               //       ccmn    x3, x2, #12, NE
 455     __ ccmp(r7, r21, 3u, Assembler::VS);               //       ccmp    x7, x21, #3, VS
 456 
 457 // ConditionalCompareImmedOp
 458     __ ccmnw(r2, 14, 4, Assembler::CC);                //       ccmn    w2, #14, #4, CC
 459     __ ccmpw(r17, 17, 6, Assembler::PL);               //       ccmp    w17, #17, #6, PL
 460     __ ccmn(r10, 12, 0, Assembler::CS);                //       ccmn    x10, #12, #0, CS
 461     __ ccmp(r21, 18, 14, Assembler::GE);               //       ccmp    x21, #18, #14, GE
 462 
 463 // ConditionalSelectOp
 464     __ cselw(r21, r13, r12, Assembler::GT);            //       csel    w21, w13, w12, GT
 465     __ csincw(r10, r27, r15, Assembler::LS);           //       csinc   w10, w27, w15, LS
 466     __ csinvw(r0, r13, r9, Assembler::HI);             //       csinv   w0, w13, w9, HI
 467     __ csnegw(r18, r4, r26, Assembler::VS);            //       csneg   w18, w4, w26, VS
 468     __ csel(r12, r29, r7, Assembler::LS);              //       csel    x12, x29, x7, LS
 469     __ csinc(r6, r7, r20, Assembler::VC);              //       csinc   x6, x7, x20, VC
 470     __ csinv(r22, r21, r3, Assembler::LE);             //       csinv   x22, x21, x3, LE
 471     __ csneg(r19, r12, r27, Assembler::LS);            //       csneg   x19, x12, x27, LS
 472 
 473 // TwoRegOp
 474     __ rbitw(r0, r16);                                 //       rbit    w0, w16
 475     __ rev16w(r17, r23);                               //       rev16   w17, w23
 476     __ revw(r17, r14);                                 //       rev     w17, w14
 477     __ clzw(r24, r30);                                 //       clz     w24, w30
 478     __ clsw(r24, r22);                                 //       cls     w24, w22
 479     __ rbit(r3, r17);                                  //       rbit    x3, x17
 480     __ rev16(r12, r13);                                //       rev16   x12, x13
 481     __ rev32(r9, r22);                                 //       rev32   x9, x22
 482     __ rev(r0, r0);                                    //       rev     x0, x0
 483     __ clz(r5, r16);                                   //       clz     x5, x16
 484     __ cls(r25, r22);                                  //       cls     x25, x22
 485 
 486 // ThreeRegOp
 487     __ udivw(r29, r4, r0);                             //       udiv    w29, w4, w0
 488     __ sdivw(r0, r29, r29);                            //       sdiv    w0, w29, w29
 489     __ lslvw(r5, r17, r21);                            //       lslv    w5, w17, w21
 490     __ lsrvw(r9, r9, r18);                             //       lsrv    w9, w9, w18
 491     __ asrvw(r1, r27, r8);                             //       asrv    w1, w27, w8
 492     __ rorvw(r18, r20, r13);                           //       rorv    w18, w20, w13
 493     __ udiv(r8, r25, r12);                             //       udiv    x8, x25, x12
 494     __ sdiv(r7, r5, r28);                              //       sdiv    x7, x5, x28
 495     __ lslv(r5, r17, r27);                             //       lslv    x5, x17, x27
 496     __ lsrv(r23, r26, r20);                            //       lsrv    x23, x26, x20
 497     __ asrv(r28, r8, r28);                             //       asrv    x28, x8, x28
 498     __ rorv(r3, r29, r4);                              //       rorv    x3, x29, x4
 499 
 500 // FourRegMulOp
 501     __ maddw(r17, r14, r26, r21);                      //       madd    w17, w14, w26, w21
 502     __ msubw(r1, r30, r11, r11);                       //       msub    w1, w30, w11, w11
 503     __ madd(r1, r17, r6, r28);                         //       madd    x1, x17, x6, x28
 504     __ msub(r30, r6, r30, r8);                         //       msub    x30, x6, x30, x8
 505     __ smaddl(r21, r6, r14, r8);                       //       smaddl  x21, w6, w14, x8
 506     __ smsubl(r10, r10, r24, r19);                     //       smsubl  x10, w10, w24, x19
 507     __ umaddl(r20, r18, r14, r24);                     //       umaddl  x20, w18, w14, x24
 508     __ umsubl(r18, r2, r5, r5);                        //       umsubl  x18, w2, w5, x5
 509 
 510 // ThreeRegFloatOp
 511     __ fmuls(v8, v18, v13);                            //       fmul    s8, s18, s13
 512     __ fdivs(v2, v14, v28);                            //       fdiv    s2, s14, s28
 513     __ fadds(v15, v12, v28);                           //       fadd    s15, s12, s28
 514     __ fsubs(v0, v12, v1);                             //       fsub    s0, s12, s1
 515     __ fmuls(v15, v29, v4);                            //       fmul    s15, s29, s4
 516     __ fmuld(v12, v1, v23);                            //       fmul    d12, d1, d23
 517     __ fdivd(v27, v8, v18);                            //       fdiv    d27, d8, d18
 518     __ faddd(v23, v20, v11);                           //       fadd    d23, d20, d11
 519     __ fsubd(v8, v12, v18);                            //       fsub    d8, d12, d18
 520     __ fmuld(v26, v24, v23);                           //       fmul    d26, d24, d23
 521 
 522 // FourRegFloatOp
 523     __ fmadds(v21, v23, v13, v25);                     //       fmadd   s21, s23, s13, s25
 524     __ fmsubs(v22, v10, v1, v14);                      //       fmsub   s22, s10, s1, s14
 525     __ fnmadds(v14, v20, v2, v30);                     //       fnmadd  s14, s20, s2, s30
 526     __ fnmadds(v7, v29, v22, v22);                     //       fnmadd  s7, s29, s22, s22
 527     __ fmaddd(v13, v5, v15, v5);                       //       fmadd   d13, d5, d15, d5
 528     __ fmsubd(v14, v12, v5, v10);                      //       fmsub   d14, d12, d5, d10
 529     __ fnmaddd(v10, v19, v0, v1);                      //       fnmadd  d10, d19, d0, d1
 530     __ fnmaddd(v20, v2, v2, v0);                       //       fnmadd  d20, d2, d2, d0
 531 
 532 // TwoRegFloatOp
 533     __ fmovs(v25, v9);                                 //       fmov    s25, s9
 534     __ fabss(v20, v4);                                 //       fabs    s20, s4
 535     __ fnegs(v3, v27);                                 //       fneg    s3, s27
 536     __ fsqrts(v1, v2);                                 //       fsqrt   s1, s2
 537     __ fcvts(v30, v0);                                 //       fcvt    d30, s0
 538     __ fmovd(v12, v4);                                 //       fmov    d12, d4
 539     __ fabsd(v1, v27);                                 //       fabs    d1, d27
 540     __ fnegd(v8, v22);                                 //       fneg    d8, d22
 541     __ fsqrtd(v11, v11);                               //       fsqrt   d11, d11
 542     __ fcvtd(v22, v28);                                //       fcvt    s22, d28
 543 
 544 // FloatConvertOp
 545     __ fcvtzsw(r28, v22);                              //       fcvtzs  w28, s22
 546     __ fcvtzs(r20, v27);                               //       fcvtzs  x20, s27
 547     __ fcvtzdw(r14, v0);                               //       fcvtzs  w14, d0
 548     __ fcvtzd(r26, v11);                               //       fcvtzs  x26, d11
 549     __ scvtfws(v28, r22);                              //       scvtf   s28, w22
 550     __ scvtfs(v16, r10);                               //       scvtf   s16, x10
 551     __ scvtfwd(v8, r21);                               //       scvtf   d8, w21
 552     __ scvtfd(v21, r28);                               //       scvtf   d21, x28
 553     __ fmovs(r24, v24);                                //       fmov    w24, s24
 554     __ fmovd(r8, v19);                                 //       fmov    x8, d19
 555     __ fmovs(v8, r12);                                 //       fmov    s8, w12
 556     __ fmovd(v6, r7);                                  //       fmov    d6, x7
 557 
 558 // TwoRegFloatOp
 559     __ fcmps(v30, v16);                                //       fcmp    s30, s16
 560     __ fcmpd(v25, v11);                                //       fcmp    d25, d11
 561     __ fcmps(v11, 0.0);                                //       fcmp    s11, #0.0
 562     __ fcmpd(v11, 0.0);                                //       fcmp    d11, #0.0
 563 
 564 // LoadStorePairOp
 565     __ stpw(r29, r12, Address(r17, 128));              //       stp     w29, w12, [x17, #128]
 566     __ ldpw(r22, r18, Address(r14, -96));              //       ldp     w22, w18, [x14, #-96]
 567     __ ldpsw(r11, r16, Address(r1, 64));               //       ldpsw   x11, x16, [x1, #64]
 568     __ stp(r0, r11, Address(r26, 112));                //       stp     x0, x11, [x26, #112]
 569     __ ldp(r7, r1, Address(r26, 16));                  //       ldp     x7, x1, [x26, #16]
 570 
 571 // LoadStorePairOp
 572     __ stpw(r10, r7, Address(__ pre(r24, 0)));         //       stp     w10, w7, [x24, #0]!
 573     __ ldpw(r7, r28, Address(__ pre(r24, -256)));      //       ldp     w7, w28, [x24, #-256]!
 574     __ ldpsw(r25, r28, Address(__ pre(r21, -240)));    //       ldpsw   x25, x28, [x21, #-240]!
 575     __ stp(r20, r18, Address(__ pre(r14, -16)));       //       stp     x20, x18, [x14, #-16]!
 576     __ ldp(r8, r10, Address(__ pre(r13, 80)));         //       ldp     x8, x10, [x13, #80]!
 577 
 578 // LoadStorePairOp
 579     __ stpw(r26, r24, Address(__ post(r2, -128)));     //       stp     w26, w24, [x2], #-128
 580     __ ldpw(r2, r25, Address(__ post(r21, -192)));     //       ldp     w2, w25, [x21], #-192
 581     __ ldpsw(r17, r2, Address(__ post(r21, -144)));    //       ldpsw   x17, x2, [x21], #-144
 582     __ stp(r12, r10, Address(__ post(r11, 96)));       //       stp     x12, x10, [x11], #96
 583     __ ldp(r24, r6, Address(__ post(r17, -32)));       //       ldp     x24, x6, [x17], #-32
 584 
 585 // LoadStorePairOp
 586     __ stnpw(r3, r30, Address(r14, -224));             //       stnp    w3, w30, [x14, #-224]
 587     __ ldnpw(r15, r20, Address(r26, -144));            //       ldnp    w15, w20, [x26, #-144]
 588     __ stnp(r22, r25, Address(r12, -128));             //       stnp    x22, x25, [x12, #-128]
 589     __ ldnp(r27, r22, Address(r17, -176));             //       ldnp    x27, x22, [x17, #-176]
 590 
 591 // FloatImmediateOp
 592     __ fmovd(v0, 2.0);                                 //       fmov d0, #2.0
 593     __ fmovd(v0, 2.125);                               //       fmov d0, #2.125
 594     __ fmovd(v0, 4.0);                                 //       fmov d0, #4.0
 595     __ fmovd(v0, 4.25);                                //       fmov d0, #4.25
 596     __ fmovd(v0, 8.0);                                 //       fmov d0, #8.0
 597     __ fmovd(v0, 8.5);                                 //       fmov d0, #8.5
 598     __ fmovd(v0, 16.0);                                //       fmov d0, #16.0
 599     __ fmovd(v0, 17.0);                                //       fmov d0, #17.0
 600     __ fmovd(v0, 0.125);                               //       fmov d0, #0.125
 601     __ fmovd(v0, 0.1328125);                           //       fmov d0, #0.1328125
 602     __ fmovd(v0, 0.25);                                //       fmov d0, #0.25
 603     __ fmovd(v0, 0.265625);                            //       fmov d0, #0.265625
 604     __ fmovd(v0, 0.5);                                 //       fmov d0, #0.5
 605     __ fmovd(v0, 0.53125);                             //       fmov d0, #0.53125
 606     __ fmovd(v0, 1.0);                                 //       fmov d0, #1.0
 607     __ fmovd(v0, 1.0625);                              //       fmov d0, #1.0625
 608     __ fmovd(v0, -2.0);                                //       fmov d0, #-2.0
 609     __ fmovd(v0, -2.125);                              //       fmov d0, #-2.125
 610     __ fmovd(v0, -4.0);                                //       fmov d0, #-4.0
 611     __ fmovd(v0, -4.25);                               //       fmov d0, #-4.25
 612     __ fmovd(v0, -8.0);                                //       fmov d0, #-8.0
 613     __ fmovd(v0, -8.5);                                //       fmov d0, #-8.5
 614     __ fmovd(v0, -16.0);                               //       fmov d0, #-16.0
 615     __ fmovd(v0, -17.0);                               //       fmov d0, #-17.0
 616     __ fmovd(v0, -0.125);                              //       fmov d0, #-0.125
 617     __ fmovd(v0, -0.1328125);                          //       fmov d0, #-0.1328125
 618     __ fmovd(v0, -0.25);                               //       fmov d0, #-0.25
 619     __ fmovd(v0, -0.265625);                           //       fmov d0, #-0.265625
 620     __ fmovd(v0, -0.5);                                //       fmov d0, #-0.5
 621     __ fmovd(v0, -0.53125);                            //       fmov d0, #-0.53125
 622     __ fmovd(v0, -1.0);                                //       fmov d0, #-1.0
 623     __ fmovd(v0, -1.0625);                             //       fmov d0, #-1.0625
 624 
 625     __ bind(forth);
 626 
 627 /*
 628 aarch64ops.o:     file format elf64-littleaarch64
 629 
 630 
 631 Disassembly of section .text:
 632 
 633 0000000000000000 <back>:
 634    0:   8b0772d3        add     x19, x22, x7, lsl #28
 635    4:   cb4a3570        sub     x16, x11, x10, lsr #13
 636    8:   ab9c09bb        adds    x27, x13, x28, asr #2
 637    c:   eb9aa794        subs    x20, x28, x26, asr #41
 638   10:   0b934e68        add     w8, w19, w19, asr #19
 639   14:   4b0a3924        sub     w4, w9, w10, lsl #14
 640   18:   2b1e3568        adds    w8, w11, w30, lsl #13
 641   1c:   6b132720        subs    w0, w25, w19, lsl #9
 642   20:   8a154c14        and     x20, x0, x21, lsl #19
 643   24:   aa1445d5        orr     x21, x14, x20, lsl #17
 644   28:   ca01cf99        eor     x25, x28, x1, lsl #51
 645   2c:   ea8b3f6a        ands    x10, x27, x11, asr #15
 646   30:   0a8c5cb9        and     w25, w5, w12, asr #23
 647   34:   2a4a11d2        orr     w18, w14, w10, lsr #4
 648   38:   4a855aa4        eor     w4, w21, w5, asr #22
 649   3c:   6a857415        ands    w21, w0, w5, asr #29
 650   40:   8aa697da        bic     x26, x30, x6, asr #37
 651   44:   aa6d7423        orn     x3, x1, x13, lsr #29
 652   48:   ca29bf80        eon     x0, x28, x9, lsl #47
 653   4c:   ea3cb8bd        bics    x29, x5, x28, lsl #46
 654   50:   0a675249        bic     w9, w18, w7, lsr #20
 655   54:   2ab961ba        orn     w26, w13, w25, asr #24
 656   58:   4a331899        eon     w25, w4, w19, lsl #6
 657   5c:   6a646345        bics    w5, w26, w4, lsr #24
 658   60:   11055267        add     w7, w19, #0x154
 659   64:   31064408        adds    w8, w0, #0x191
 660   68:   51028e9d        sub     w29, w20, #0xa3
 661   6c:   710bdee8        subs    w8, w23, #0x2f7
 662   70:   91082d81        add     x1, x12, #0x20b
 663   74:   b106a962        adds    x2, x11, #0x1aa
 664   78:   d10b33ae        sub     x14, x29, #0x2cc
 665   7c:   f10918ab        subs    x11, x5, #0x246
 666   80:   121102d7        and     w23, w22, #0x8000
 667   84:   3204cd44        orr     w4, w10, #0xf0f0f0f0
 668   88:   5204cf00        eor     w0, w24, #0xf0f0f0f0
 669   8c:   72099fb3        ands    w19, w29, #0x7f807f80
 670   90:   92729545        and     x5, x10, #0xfffffffffc000
 671   94:   b20e37cc        orr     x12, x30, #0xfffc0000fffc0000
 672   98:   d27c34be        eor     x30, x5, #0x3fff0
 673   9c:   f27e4efa        ands    x26, x23, #0x3ffffc
 674   a0:   14000000        b       a0 <back+0xa0>
 675   a4:   17ffffd7        b       0 <back>
 676   a8:   1400017f        b       6a4 <forth>
 677   ac:   94000000        bl      ac <back+0xac>
 678   b0:   97ffffd4        bl      0 <back>
 679   b4:   9400017c        bl      6a4 <forth>
 680   b8:   3400000c        cbz     w12, b8 <back+0xb8>
 681   bc:   34fffa2c        cbz     w12, 0 <back>
 682   c0:   34002f2c        cbz     w12, 6a4 <forth>
 683   c4:   35000014        cbnz    w20, c4 <back+0xc4>
 684   c8:   35fff9d4        cbnz    w20, 0 <back>
 685   cc:   35002ed4        cbnz    w20, 6a4 <forth>
 686   d0:   b400000c        cbz     x12, d0 <back+0xd0>
 687   d4:   b4fff96c        cbz     x12, 0 <back>
 688   d8:   b4002e6c        cbz     x12, 6a4 <forth>
 689   dc:   b5000018        cbnz    x24, dc <back+0xdc>
 690   e0:   b5fff918        cbnz    x24, 0 <back>
 691   e4:   b5002e18        cbnz    x24, 6a4 <forth>
 692   e8:   10000006        adr     x6, e8 <back+0xe8>
 693   ec:   10fff8a6        adr     x6, 0 <back>
 694   f0:   10002da6        adr     x6, 6a4 <forth>
 695   f4:   90000015        adrp    x21, 0 <back>
 696   f8:   36080001        tbz     w1, #1, f8 <back+0xf8>
 697   fc:   360ff821        tbz     w1, #1, 0 <back>
 698  100:   36082d21        tbz     w1, #1, 6a4 <forth>
 699  104:   37480008        tbnz    w8, #9, 104 <back+0x104>
 700  108:   374ff7c8        tbnz    w8, #9, 0 <back>
 701  10c:   37482cc8        tbnz    w8, #9, 6a4 <forth>
 702  110:   128b50ec        movn    w12, #0x5a87
 703  114:   52a9ff8b        movz    w11, #0x4ffc, lsl #16
 704  118:   7281d095        movk    w21, #0xe84
 705  11c:   92edfebd        movn    x29, #0x6ff5, lsl #48
 706  120:   d28361e3        movz    x3, #0x1b0f
 707  124:   f2a4cc96        movk    x22, #0x2664, lsl #16
 708  128:   9346590c        sbfx    x12, x8, #6, #17
 709  12c:   33194f33        bfi     w19, w25, #7, #20
 710  130:   531d3d89        ubfiz   w9, w12, #3, #16
 711  134:   9350433c        sbfx    x28, x25, #16, #1
 712  138:   b34464ac        bfxil   x12, x5, #4, #22
 713  13c:   d3462140        ubfx    x0, x10, #6, #3
 714  140:   139a61a4        extr    w4, w13, w26, #24
 715  144:   93d87fd7        extr    x23, x30, x24, #31
 716  148:   54000000        b.eq    148 <back+0x148>
 717  14c:   54fff5a0        b.eq    0 <back>
 718  150:   54002aa0        b.eq    6a4 <forth>
 719  154:   54000001        b.ne    154 <back+0x154>
 720  158:   54fff541        b.ne    0 <back>
 721  15c:   54002a41        b.ne    6a4 <forth>
 722  160:   54000002        b.cs    160 <back+0x160>
 723  164:   54fff4e2        b.cs    0 <back>
 724  168:   540029e2        b.cs    6a4 <forth>
 725  16c:   54000002        b.cs    16c <back+0x16c>
 726  170:   54fff482        b.cs    0 <back>
 727  174:   54002982        b.cs    6a4 <forth>
 728  178:   54000003        b.cc    178 <back+0x178>
 729  17c:   54fff423        b.cc    0 <back>
 730  180:   54002923        b.cc    6a4 <forth>
 731  184:   54000003        b.cc    184 <back+0x184>
 732  188:   54fff3c3        b.cc    0 <back>
 733  18c:   540028c3        b.cc    6a4 <forth>
 734  190:   54000004        b.mi    190 <back+0x190>
 735  194:   54fff364        b.mi    0 <back>
 736  198:   54002864        b.mi    6a4 <forth>
 737  19c:   54000005        b.pl    19c <back+0x19c>
 738  1a0:   54fff305        b.pl    0 <back>
 739  1a4:   54002805        b.pl    6a4 <forth>
 740  1a8:   54000006        b.vs    1a8 <back+0x1a8>
 741  1ac:   54fff2a6        b.vs    0 <back>
 742  1b0:   540027a6        b.vs    6a4 <forth>
 743  1b4:   54000007        b.vc    1b4 <back+0x1b4>
 744  1b8:   54fff247        b.vc    0 <back>
 745  1bc:   54002747        b.vc    6a4 <forth>
 746  1c0:   54000008        b.hi    1c0 <back+0x1c0>
 747  1c4:   54fff1e8        b.hi    0 <back>
 748  1c8:   540026e8        b.hi    6a4 <forth>
 749  1cc:   54000009        b.ls    1cc <back+0x1cc>
 750  1d0:   54fff189        b.ls    0 <back>
 751  1d4:   54002689        b.ls    6a4 <forth>
 752  1d8:   5400000a        b.ge    1d8 <back+0x1d8>
 753  1dc:   54fff12a        b.ge    0 <back>
 754  1e0:   5400262a        b.ge    6a4 <forth>
 755  1e4:   5400000b        b.lt    1e4 <back+0x1e4>
 756  1e8:   54fff0cb        b.lt    0 <back>
 757  1ec:   540025cb        b.lt    6a4 <forth>
 758  1f0:   5400000c        b.gt    1f0 <back+0x1f0>
 759  1f4:   54fff06c        b.gt    0 <back>
 760  1f8:   5400256c        b.gt    6a4 <forth>
 761  1fc:   5400000d        b.le    1fc <back+0x1fc>
 762  200:   54fff00d        b.le    0 <back>
 763  204:   5400250d        b.le    6a4 <forth>
 764  208:   5400000e        b.al    208 <back+0x208>
 765  20c:   54ffefae        b.al    0 <back>
 766  210:   540024ae        b.al    6a4 <forth>
 767  214:   5400000f        b.nv    214 <back+0x214>
 768  218:   54ffef4f        b.nv    0 <back>
 769  21c:   5400244f        b.nv    6a4 <forth>
 770  220:   d4063721        svc     #0x31b9
 771  224:   d4035082        hvc     #0x1a84
 772  228:   d400bfe3        smc     #0x5ff
 773  22c:   d4282fc0        brk     #0x417e
 774  230:   d444c320        hlt     #0x2619
 775  234:   d503201f        nop
 776  238:   d69f03e0        eret
 777  23c:   d6bf03e0        drps
 778  240:   d5033fdf        isb
 779  244:   d5033f9f        dsb     sy
 780  248:   d5033abf        dmb     ishst
 781  24c:   d61f0040        br      x2
 782  250:   d63f00a0        blr     x5
 783  254:   c8147c55        stxr    w20, x21, [x2]
 784  258:   c805fcfd        stlxr   w5, x29, [x7]
 785  25c:   c85f7e05        ldxr    x5, [x16]
 786  260:   c85fffbb        ldaxr   x27, [x29]
 787  264:   c89fffa0        stlr    x0, [x29]
 788  268:   c8dfff95        ldar    x21, [x28]
 789  26c:   88157cf8        stxr    w21, w24, [x7]
 790  270:   8815ff9a        stlxr   w21, w26, [x28]
 791  274:   885f7cd5        ldxr    w21, [x6]
 792  278:   885fffcf        ldaxr   w15, [x30]
 793  27c:   889ffc73        stlr    w19, [x3]
 794  280:   88dffc56        ldar    w22, [x2]
 795  284:   48127c0f        stxrh   w18, w15, [x0]
 796  288:   480bff85        stlxrh  w11, w5, [x28]
 797  28c:   485f7cdd        ldxrh   w29, [x6]
 798  290:   485ffcf2        ldaxrh  w18, [x7]
 799  294:   489fff99        stlrh   w25, [x28]
 800  298:   48dffe62        ldarh   w2, [x19]
 801  29c:   080a7c3e        stxrb   w10, w30, [x1]
 802  2a0:   0814fed5        stlxrb  w20, w21, [x22]
 803  2a4:   085f7c59        ldxrb   w25, [x2]
 804  2a8:   085ffcb8        ldaxrb  w24, [x5]
 805  2ac:   089ffc70        stlrb   w16, [x3]
 806  2b0:   08dfffb6        ldarb   w22, [x29]
 807  2b4:   c87f0a68        ldxp    x8, x2, [x19]
 808  2b8:   c87fcdc7        ldaxp   x7, x19, [x14]
 809  2bc:   c82870bb        stxp    w8, x27, x28, [x5]
 810  2c0:   c825b8c8        stlxp   w5, x8, x14, [x6]
 811  2c4:   887f12d9        ldxp    w25, w4, [x22]
 812  2c8:   887fb9ed        ldaxp   w13, w14, [x15]
 813  2cc:   8834215a        stxp    w20, w26, w8, [x10]
 814  2d0:   8837ca52        stlxp   w23, w18, w18, [x18]
 815  2d4:   f806317e        str     x30, [x11,#99]
 816  2d8:   b81b3337        str     w23, [x25,#-77]
 817  2dc:   39000dc2        strb    w2, [x14,#3]
 818  2e0:   78005149        strh    w9, [x10,#5]
 819  2e4:   f84391f4        ldr     x20, [x15,#57]
 820  2e8:   b85b220c        ldr     w12, [x16,#-78]
 821  2ec:   385fd356        ldrb    w22, [x26,#-3]
 822  2f0:   785d127e        ldrh    w30, [x19,#-47]
 823  2f4:   389f4149        ldrsb   x9, [x10,#-12]
 824  2f8:   79801e3c        ldrsh   x28, [x17,#14]
 825  2fc:   79c014a3        ldrsh   w3, [x5,#10]
 826  300:   b89a5231        ldrsw   x17, [x17,#-91]
 827  304:   fc5ef282        ldr     d2, [x20,#-17]
 828  308:   bc5f60f6        ldr     s22, [x7,#-10]
 829  30c:   fc12125e        str     d30, [x18,#-223]
 830  310:   bc0152cd        str     s13, [x22,#21]
 831  314:   f8190e49        str     x9, [x18,#-112]!
 832  318:   b800befd        str     w29, [x23,#11]!
 833  31c:   381ffd92        strb    w18, [x12,#-1]!
 834  320:   781e9e90        strh    w16, [x20,#-23]!
 835  324:   f8409fa3        ldr     x3, [x29,#9]!
 836  328:   b8413c79        ldr     w25, [x3,#19]!
 837  32c:   385fffa1        ldrb    w1, [x29,#-1]!
 838  330:   785c7fa8        ldrh    w8, [x29,#-57]!
 839  334:   389f3dc5        ldrsb   x5, [x14,#-13]!
 840  338:   78801f6a        ldrsh   x10, [x27,#1]!
 841  33c:   78c19d4b        ldrsh   w11, [x10,#25]!
 842  340:   b89a4ec4        ldrsw   x4, [x22,#-92]!
 843  344:   fc408eeb        ldr     d11, [x23,#8]!
 844  348:   bc436e79        ldr     s25, [x19,#54]!
 845  34c:   fc152ce1        str     d1, [x7,#-174]!
 846  350:   bc036f28        str     s8, [x25,#54]!
 847  354:   f8025565        str     x5, [x11],#37
 848  358:   b80135f8        str     w24, [x15],#19
 849  35c:   381ff74f        strb    w15, [x26],#-1
 850  360:   781fa652        strh    w18, [x18],#-6
 851  364:   f851a447        ldr     x7, [x2],#-230
 852  368:   b85e557b        ldr     w27, [x11],#-27
 853  36c:   385e7472        ldrb    w18, [x3],#-25
 854  370:   785e070a        ldrh    w10, [x24],#-32
 855  374:   38804556        ldrsb   x22, [x10],#4
 856  378:   78819591        ldrsh   x17, [x12],#25
 857  37c:   78dc24e8        ldrsh   w8, [x7],#-62
 858  380:   b89cd6d7        ldrsw   x23, [x22],#-51
 859  384:   fc430738        ldr     d24, [x25],#48
 860  388:   bc5f6595        ldr     s21, [x12],#-10
 861  38c:   fc1225b2        str     d18, [x13],#-222
 862  390:   bc1d7430        str     s16, [x1],#-41
 863  394:   f82fcac2        str     x2, [x22,w15,sxtw]
 864  398:   b83d6a02        str     w2, [x16,x29]
 865  39c:   382e5a54        strb    w20, [x18,w14,uxtw #0]
 866  3a0:   7834fa66        strh    w6, [x19,x20,sxtx #1]
 867  3a4:   f86ecbae        ldr     x14, [x29,w14,sxtw]
 868  3a8:   b86cda90        ldr     w16, [x20,w12,sxtw #2]
 869  3ac:   3860d989        ldrb    w9, [x12,w0,sxtw #0]
 870  3b0:   78637a2c        ldrh    w12, [x17,x3,lsl #1]
 871  3b4:   38a3fa22        ldrsb   x2, [x17,x3,sxtx #0]
 872  3b8:   78b15827        ldrsh   x7, [x1,w17,uxtw #1]
 873  3bc:   78f2d9f9        ldrsh   w25, [x15,w18,sxtw #1]
 874  3c0:   b8ac6ab7        ldrsw   x23, [x21,x12]
 875  3c4:   fc6879a5        ldr     d5, [x13,x8,lsl #3]
 876  3c8:   bc767943        ldr     s3, [x10,x22,lsl #2]
 877  3cc:   fc3bc84e        str     d14, [x2,w27,sxtw]
 878  3d0:   bc3968d4        str     s20, [x6,x25]
 879  3d4:   f91fc0fe        str     x30, [x7,#16256]
 880  3d8:   b91da50f        str     w15, [x8,#7588]
 881  3dc:   391d280b        strb    w11, [x0,#1866]
 882  3e0:   791d2e23        strh    w3, [x17,#3734]
 883  3e4:   f95bc8e2        ldr     x2, [x7,#14224]
 884  3e8:   b95ce525        ldr     w5, [x9,#7396]
 885  3ec:   395ae53c        ldrb    w28, [x9,#1721]
 886  3f0:   795c9282        ldrh    w2, [x20,#3656]
 887  3f4:   399d7dd6        ldrsb   x22, [x14,#1887]
 888  3f8:   799fe008        ldrsh   x8, [x0,#4080]
 889  3fc:   79de9bc0        ldrsh   w0, [x30,#3916]
 890  400:   b99aae78        ldrsw   x24, [x19,#6828]
 891  404:   fd597598        ldr     d24, [x12,#13032]
 892  408:   bd5d1d08        ldr     s8, [x8,#7452]
 893  40c:   fd1f3dea        str     d10, [x15,#15992]
 894  410:   bd1a227a        str     s26, [x19,#6688]
 895  414:   5800148a        ldr     x10, 6a4 <forth>
 896  418:   18000003        ldr     w3, 418 <back+0x418>
 897  41c:   f88092e0        prfm    pldl1keep, [x23,#9]
 898  420:   d8ffdf00        prfm    pldl1keep, 0 <back>
 899  424:   f8a84860        prfm    pldl1keep, [x3,w8,uxtw]
 900  428:   f99d7560        prfm    pldl1keep, [x11,#15080]
 901  42c:   1a1c012d        adc     w13, w9, w28
 902  430:   3a1c027b        adcs    w27, w19, w28
 903  434:   5a060253        sbc     w19, w18, w6
 904  438:   7a03028e        sbcs    w14, w20, w3
 905  43c:   9a0801d0        adc     x16, x14, x8
 906  440:   ba0803a0        adcs    x0, x29, x8
 907  444:   da140308        sbc     x8, x24, x20
 908  448:   fa00038c        sbcs    x12, x28, x0
 909  44c:   0b3010d7        add     w23, w6, w16, uxtb #4
 910  450:   2b37ab39        adds    w25, w25, w23, sxth #2
 911  454:   cb2466da        sub     x26, x22, x4, uxtx #1
 912  458:   6b33efb1        subs    w17, w29, w19, sxtx #3
 913  45c:   8b350fcb        add     x11, x30, w21, uxtb #3
 914  460:   ab208a70        adds    x16, x19, w0, sxtb #2
 915  464:   cb39e52b        sub     x11, x9, x25, sxtx #1
 916  468:   eb2c9291        subs    x17, x20, w12, sxtb #4
 917  46c:   3a4bd1a3        ccmn    w13, w11, #0x3, le
 918  470:   7a4c81a2        ccmp    w13, w12, #0x2, hi
 919  474:   ba42106c        ccmn    x3, x2, #0xc, ne
 920  478:   fa5560e3        ccmp    x7, x21, #0x3, vs
 921  47c:   3a4e3844        ccmn    w2, #0xe, #0x4, cc
 922  480:   7a515a26        ccmp    w17, #0x11, #0x6, pl
 923  484:   ba4c2940        ccmn    x10, #0xc, #0x0, cs
 924  488:   fa52aaae        ccmp    x21, #0x12, #0xe, ge
 925  48c:   1a8cc1b5        csel    w21, w13, w12, gt
 926  490:   1a8f976a        csinc   w10, w27, w15, ls
 927  494:   5a8981a0        csinv   w0, w13, w9, hi
 928  498:   5a9a6492        csneg   w18, w4, w26, vs
 929  49c:   9a8793ac        csel    x12, x29, x7, ls
 930  4a0:   9a9474e6        csinc   x6, x7, x20, vc
 931  4a4:   da83d2b6        csinv   x22, x21, x3, le
 932  4a8:   da9b9593        csneg   x19, x12, x27, ls
 933  4ac:   5ac00200        rbit    w0, w16
 934  4b0:   5ac006f1        rev16   w17, w23
 935  4b4:   5ac009d1        rev     w17, w14
 936  4b8:   5ac013d8        clz     w24, w30
 937  4bc:   5ac016d8        cls     w24, w22
 938  4c0:   dac00223        rbit    x3, x17
 939  4c4:   dac005ac        rev16   x12, x13
 940  4c8:   dac00ac9        rev32   x9, x22
 941  4cc:   dac00c00        rev     x0, x0
 942  4d0:   dac01205        clz     x5, x16
 943  4d4:   dac016d9        cls     x25, x22
 944  4d8:   1ac0089d        udiv    w29, w4, w0
 945  4dc:   1add0fa0        sdiv    w0, w29, w29
 946  4e0:   1ad52225        lsl     w5, w17, w21
 947  4e4:   1ad22529        lsr     w9, w9, w18
 948  4e8:   1ac82b61        asr     w1, w27, w8
 949  4ec:   1acd2e92        ror     w18, w20, w13
 950  4f0:   9acc0b28        udiv    x8, x25, x12
 951  4f4:   9adc0ca7        sdiv    x7, x5, x28
 952  4f8:   9adb2225        lsl     x5, x17, x27
 953  4fc:   9ad42757        lsr     x23, x26, x20
 954  500:   9adc291c        asr     x28, x8, x28
 955  504:   9ac42fa3        ror     x3, x29, x4
 956  508:   1b1a55d1        madd    w17, w14, w26, w21
 957  50c:   1b0bafc1        msub    w1, w30, w11, w11
 958  510:   9b067221        madd    x1, x17, x6, x28
 959  514:   9b1ea0de        msub    x30, x6, x30, x8
 960  518:   9b2e20d5        smaddl  x21, w6, w14, x8
 961  51c:   9b38cd4a        smsubl  x10, w10, w24, x19
 962  520:   9bae6254        umaddl  x20, w18, w14, x24
 963  524:   9ba59452        umsubl  x18, w2, w5, x5
 964  528:   1e2d0a48        fmul    s8, s18, s13
 965  52c:   1e3c19c2        fdiv    s2, s14, s28
 966  530:   1e3c298f        fadd    s15, s12, s28
 967  534:   1e213980        fsub    s0, s12, s1
 968  538:   1e240baf        fmul    s15, s29, s4
 969  53c:   1e77082c        fmul    d12, d1, d23
 970  540:   1e72191b        fdiv    d27, d8, d18
 971  544:   1e6b2a97        fadd    d23, d20, d11
 972  548:   1e723988        fsub    d8, d12, d18
 973  54c:   1e770b1a        fmul    d26, d24, d23
 974  550:   1f0d66f5        fmadd   s21, s23, s13, s25
 975  554:   1f01b956        fmsub   s22, s10, s1, s14
 976  558:   1f227a8e        fnmadd  s14, s20, s2, s30
 977  55c:   1f365ba7        fnmadd  s7, s29, s22, s22
 978  560:   1f4f14ad        fmadd   d13, d5, d15, d5
 979  564:   1f45a98e        fmsub   d14, d12, d5, d10
 980  568:   1f60066a        fnmadd  d10, d19, d0, d1
 981  56c:   1f620054        fnmadd  d20, d2, d2, d0
 982  570:   1e204139        fmov    s25, s9
 983  574:   1e20c094        fabs    s20, s4
 984  578:   1e214363        fneg    s3, s27
 985  57c:   1e21c041        fsqrt   s1, s2
 986  580:   1e22c01e        fcvt    d30, s0
 987  584:   1e60408c        fmov    d12, d4
 988  588:   1e60c361        fabs    d1, d27
 989  58c:   1e6142c8        fneg    d8, d22
 990  590:   1e61c16b        fsqrt   d11, d11
 991  594:   1e624396        fcvt    s22, d28
 992  598:   1e3802dc        fcvtzs  w28, s22
 993  59c:   9e380374        fcvtzs  x20, s27
 994  5a0:   1e78000e        fcvtzs  w14, d0
 995  5a4:   9e78017a        fcvtzs  x26, d11
 996  5a8:   1e2202dc        scvtf   s28, w22
 997  5ac:   9e220150        scvtf   s16, x10
 998  5b0:   1e6202a8        scvtf   d8, w21
 999  5b4:   9e620395        scvtf   d21, x28
1000  5b8:   1e260318        fmov    w24, s24
1001  5bc:   9e660268        fmov    x8, d19
1002  5c0:   1e270188        fmov    s8, w12
1003  5c4:   9e6700e6        fmov    d6, x7
1004  5c8:   1e3023c0        fcmp    s30, s16
1005  5cc:   1e6b2320        fcmp    d25, d11
1006  5d0:   1e202168        fcmp    s11, #0.0
1007  5d4:   1e602168        fcmp    d11, #0.0
1008  5d8:   2910323d        stp     w29, w12, [x17,#128]
1009  5dc:   297449d6        ldp     w22, w18, [x14,#-96]
1010  5e0:   6948402b        ldpsw   x11, x16, [x1,#64]
1011  5e4:   a9072f40        stp     x0, x11, [x26,#112]
1012  5e8:   a9410747        ldp     x7, x1, [x26,#16]
1013  5ec:   29801f0a        stp     w10, w7, [x24,#0]!
1014  5f0:   29e07307        ldp     w7, w28, [x24,#-256]!
1015  5f4:   69e272b9        ldpsw   x25, x28, [x21,#-240]!
1016  5f8:   a9bf49d4        stp     x20, x18, [x14,#-16]!
1017  5fc:   a9c529a8        ldp     x8, x10, [x13,#80]!
1018  600:   28b0605a        stp     w26, w24, [x2],#-128
1019  604:   28e866a2        ldp     w2, w25, [x21],#-192
1020  608:   68ee0ab1        ldpsw   x17, x2, [x21],#-144
1021  60c:   a886296c        stp     x12, x10, [x11],#96
1022  610:   a8fe1a38        ldp     x24, x6, [x17],#-32
1023  614:   282479c3        stnp    w3, w30, [x14,#-224]
1024  618:   286e534f        ldnp    w15, w20, [x26,#-144]
1025  61c:   a8386596        stnp    x22, x25, [x12,#-128]
1026  620:   a8755a3b        ldnp    x27, x22, [x17,#-176]
1027  624:   1e601000        fmov    d0, #2.000000000000000000e+00
1028  628:   1e603000        fmov    d0, #2.125000000000000000e+00
1029  62c:   1e621000        fmov    d0, #4.000000000000000000e+00
1030  630:   1e623000        fmov    d0, #4.250000000000000000e+00
1031  634:   1e641000        fmov    d0, #8.000000000000000000e+00
1032  638:   1e643000        fmov    d0, #8.500000000000000000e+00
1033  63c:   1e661000        fmov    d0, #1.600000000000000000e+01
1034  640:   1e663000        fmov    d0, #1.700000000000000000e+01
1035  644:   1e681000        fmov    d0, #1.250000000000000000e-01
1036  648:   1e683000        fmov    d0, #1.328125000000000000e-01
1037  64c:   1e6a1000        fmov    d0, #2.500000000000000000e-01
1038  650:   1e6a3000        fmov    d0, #2.656250000000000000e-01
1039  654:   1e6c1000        fmov    d0, #5.000000000000000000e-01
1040  658:   1e6c3000        fmov    d0, #5.312500000000000000e-01
1041  65c:   1e6e1000        fmov    d0, #1.000000000000000000e+00
1042  660:   1e6e3000        fmov    d0, #1.062500000000000000e+00
1043  664:   1e701000        fmov    d0, #-2.000000000000000000e+00
1044  668:   1e703000        fmov    d0, #-2.125000000000000000e+00
1045  66c:   1e721000        fmov    d0, #-4.000000000000000000e+00
1046  670:   1e723000        fmov    d0, #-4.250000000000000000e+00
1047  674:   1e741000        fmov    d0, #-8.000000000000000000e+00
1048  678:   1e743000        fmov    d0, #-8.500000000000000000e+00
1049  67c:   1e761000        fmov    d0, #-1.600000000000000000e+01
1050  680:   1e763000        fmov    d0, #-1.700000000000000000e+01
1051  684:   1e781000        fmov    d0, #-1.250000000000000000e-01
1052  688:   1e783000        fmov    d0, #-1.328125000000000000e-01
1053  68c:   1e7a1000        fmov    d0, #-2.500000000000000000e-01
1054  690:   1e7a3000        fmov    d0, #-2.656250000000000000e-01
1055  694:   1e7c1000        fmov    d0, #-5.000000000000000000e-01
1056  698:   1e7c3000        fmov    d0, #-5.312500000000000000e-01
1057  69c:   1e7e1000        fmov    d0, #-1.000000000000000000e+00
1058  6a0:   1e7e3000        fmov    d0, #-1.062500000000000000e+00
1059  */
1060 
1061   static const unsigned int insns[] =
1062   {
1063     0x8b0772d3,     0xcb4a3570,     0xab9c09bb,     0xeb9aa794,
1064     0x0b934e68,     0x4b0a3924,     0x2b1e3568,     0x6b132720,
1065     0x8a154c14,     0xaa1445d5,     0xca01cf99,     0xea8b3f6a,
1066     0x0a8c5cb9,     0x2a4a11d2,     0x4a855aa4,     0x6a857415,
1067     0x8aa697da,     0xaa6d7423,     0xca29bf80,     0xea3cb8bd,
1068     0x0a675249,     0x2ab961ba,     0x4a331899,     0x6a646345,
1069     0x11055267,     0x31064408,     0x51028e9d,     0x710bdee8,
1070     0x91082d81,     0xb106a962,     0xd10b33ae,     0xf10918ab,
1071     0x121102d7,     0x3204cd44,     0x5204cf00,     0x72099fb3,
1072     0x92729545,     0xb20e37cc,     0xd27c34be,     0xf27e4efa,
1073     0x14000000,     0x17ffffd7,     0x1400017f,     0x94000000,
1074     0x97ffffd4,     0x9400017c,     0x3400000c,     0x34fffa2c,
1075     0x34002f2c,     0x35000014,     0x35fff9d4,     0x35002ed4,
1076     0xb400000c,     0xb4fff96c,     0xb4002e6c,     0xb5000018,
1077     0xb5fff918,     0xb5002e18,     0x10000006,     0x10fff8a6,
1078     0x10002da6,     0x90000015,     0x36080001,     0x360ff821,
1079     0x36082d21,     0x37480008,     0x374ff7c8,     0x37482cc8,
1080     0x128b50ec,     0x52a9ff8b,     0x7281d095,     0x92edfebd,
1081     0xd28361e3,     0xf2a4cc96,     0x9346590c,     0x33194f33,
1082     0x531d3d89,     0x9350433c,     0xb34464ac,     0xd3462140,
1083     0x139a61a4,     0x93d87fd7,     0x54000000,     0x54fff5a0,
1084     0x54002aa0,     0x54000001,     0x54fff541,     0x54002a41,
1085     0x54000002,     0x54fff4e2,     0x540029e2,     0x54000002,
1086     0x54fff482,     0x54002982,     0x54000003,     0x54fff423,
1087     0x54002923,     0x54000003,     0x54fff3c3,     0x540028c3,
1088     0x54000004,     0x54fff364,     0x54002864,     0x54000005,
1089     0x54fff305,     0x54002805,     0x54000006,     0x54fff2a6,
1090     0x540027a6,     0x54000007,     0x54fff247,     0x54002747,
1091     0x54000008,     0x54fff1e8,     0x540026e8,     0x54000009,
1092     0x54fff189,     0x54002689,     0x5400000a,     0x54fff12a,
1093     0x5400262a,     0x5400000b,     0x54fff0cb,     0x540025cb,
1094     0x5400000c,     0x54fff06c,     0x5400256c,     0x5400000d,
1095     0x54fff00d,     0x5400250d,     0x5400000e,     0x54ffefae,
1096     0x540024ae,     0x5400000f,     0x54ffef4f,     0x5400244f,
1097     0xd4063721,     0xd4035082,     0xd400bfe3,     0xd4282fc0,
1098     0xd444c320,     0xd503201f,     0xd69f03e0,     0xd6bf03e0,
1099     0xd5033fdf,     0xd5033f9f,     0xd5033abf,     0xd61f0040,
1100     0xd63f00a0,     0xc8147c55,     0xc805fcfd,     0xc85f7e05,
1101     0xc85fffbb,     0xc89fffa0,     0xc8dfff95,     0x88157cf8,
1102     0x8815ff9a,     0x885f7cd5,     0x885fffcf,     0x889ffc73,
1103     0x88dffc56,     0x48127c0f,     0x480bff85,     0x485f7cdd,
1104     0x485ffcf2,     0x489fff99,     0x48dffe62,     0x080a7c3e,
1105     0x0814fed5,     0x085f7c59,     0x085ffcb8,     0x089ffc70,
1106     0x08dfffb6,     0xc87f0a68,     0xc87fcdc7,     0xc82870bb,
1107     0xc825b8c8,     0x887f12d9,     0x887fb9ed,     0x8834215a,
1108     0x8837ca52,     0xf806317e,     0xb81b3337,     0x39000dc2,
1109     0x78005149,     0xf84391f4,     0xb85b220c,     0x385fd356,
1110     0x785d127e,     0x389f4149,     0x79801e3c,     0x79c014a3,
1111     0xb89a5231,     0xfc5ef282,     0xbc5f60f6,     0xfc12125e,
1112     0xbc0152cd,     0xf8190e49,     0xb800befd,     0x381ffd92,
1113     0x781e9e90,     0xf8409fa3,     0xb8413c79,     0x385fffa1,
1114     0x785c7fa8,     0x389f3dc5,     0x78801f6a,     0x78c19d4b,
1115     0xb89a4ec4,     0xfc408eeb,     0xbc436e79,     0xfc152ce1,
1116     0xbc036f28,     0xf8025565,     0xb80135f8,     0x381ff74f,
1117     0x781fa652,     0xf851a447,     0xb85e557b,     0x385e7472,
1118     0x785e070a,     0x38804556,     0x78819591,     0x78dc24e8,
1119     0xb89cd6d7,     0xfc430738,     0xbc5f6595,     0xfc1225b2,
1120     0xbc1d7430,     0xf82fcac2,     0xb83d6a02,     0x382e5a54,
1121     0x7834fa66,     0xf86ecbae,     0xb86cda90,     0x3860d989,
1122     0x78637a2c,     0x38a3fa22,     0x78b15827,     0x78f2d9f9,
1123     0xb8ac6ab7,     0xfc6879a5,     0xbc767943,     0xfc3bc84e,
1124     0xbc3968d4,     0xf91fc0fe,     0xb91da50f,     0x391d280b,
1125     0x791d2e23,     0xf95bc8e2,     0xb95ce525,     0x395ae53c,
1126     0x795c9282,     0x399d7dd6,     0x799fe008,     0x79de9bc0,
1127     0xb99aae78,     0xfd597598,     0xbd5d1d08,     0xfd1f3dea,
1128     0xbd1a227a,     0x5800148a,     0x18000003,     0xf88092e0,
1129     0xd8ffdf00,     0xf8a84860,     0xf99d7560,     0x1a1c012d,
1130     0x3a1c027b,     0x5a060253,     0x7a03028e,     0x9a0801d0,
1131     0xba0803a0,     0xda140308,     0xfa00038c,     0x0b3010d7,
1132     0x2b37ab39,     0xcb2466da,     0x6b33efb1,     0x8b350fcb,
1133     0xab208a70,     0xcb39e52b,     0xeb2c9291,     0x3a4bd1a3,
1134     0x7a4c81a2,     0xba42106c,     0xfa5560e3,     0x3a4e3844,
1135     0x7a515a26,     0xba4c2940,     0xfa52aaae,     0x1a8cc1b5,
1136     0x1a8f976a,     0x5a8981a0,     0x5a9a6492,     0x9a8793ac,
1137     0x9a9474e6,     0xda83d2b6,     0xda9b9593,     0x5ac00200,
1138     0x5ac006f1,     0x5ac009d1,     0x5ac013d8,     0x5ac016d8,
1139     0xdac00223,     0xdac005ac,     0xdac00ac9,     0xdac00c00,
1140     0xdac01205,     0xdac016d9,     0x1ac0089d,     0x1add0fa0,
1141     0x1ad52225,     0x1ad22529,     0x1ac82b61,     0x1acd2e92,
1142     0x9acc0b28,     0x9adc0ca7,     0x9adb2225,     0x9ad42757,
1143     0x9adc291c,     0x9ac42fa3,     0x1b1a55d1,     0x1b0bafc1,
1144     0x9b067221,     0x9b1ea0de,     0x9b2e20d5,     0x9b38cd4a,
1145     0x9bae6254,     0x9ba59452,     0x1e2d0a48,     0x1e3c19c2,
1146     0x1e3c298f,     0x1e213980,     0x1e240baf,     0x1e77082c,
1147     0x1e72191b,     0x1e6b2a97,     0x1e723988,     0x1e770b1a,
1148     0x1f0d66f5,     0x1f01b956,     0x1f227a8e,     0x1f365ba7,
1149     0x1f4f14ad,     0x1f45a98e,     0x1f60066a,     0x1f620054,
1150     0x1e204139,     0x1e20c094,     0x1e214363,     0x1e21c041,
1151     0x1e22c01e,     0x1e60408c,     0x1e60c361,     0x1e6142c8,
1152     0x1e61c16b,     0x1e624396,     0x1e3802dc,     0x9e380374,
1153     0x1e78000e,     0x9e78017a,     0x1e2202dc,     0x9e220150,
1154     0x1e6202a8,     0x9e620395,     0x1e260318,     0x9e660268,
1155     0x1e270188,     0x9e6700e6,     0x1e3023c0,     0x1e6b2320,
1156     0x1e202168,     0x1e602168,     0x2910323d,     0x297449d6,
1157     0x6948402b,     0xa9072f40,     0xa9410747,     0x29801f0a,
1158     0x29e07307,     0x69e272b9,     0xa9bf49d4,     0xa9c529a8,
1159     0x28b0605a,     0x28e866a2,     0x68ee0ab1,     0xa886296c,
1160     0xa8fe1a38,     0x282479c3,     0x286e534f,     0xa8386596,
1161     0xa8755a3b,     0x1e601000,     0x1e603000,     0x1e621000,
1162     0x1e623000,     0x1e641000,     0x1e643000,     0x1e661000,
1163     0x1e663000,     0x1e681000,     0x1e683000,     0x1e6a1000,
1164     0x1e6a3000,     0x1e6c1000,     0x1e6c3000,     0x1e6e1000,
1165     0x1e6e3000,     0x1e701000,     0x1e703000,     0x1e721000,
1166     0x1e723000,     0x1e741000,     0x1e743000,     0x1e761000,
1167     0x1e763000,     0x1e781000,     0x1e783000,     0x1e7a1000,
1168     0x1e7a3000,     0x1e7c1000,     0x1e7c3000,     0x1e7e1000,
1169     0x1e7e3000, 
1170   };
1171 // END  Generated code -- do not edit
1172 
1173   {
1174     bool ok = true;
1175     unsigned int *insns1 = (unsigned int *)entry;
1176     for (unsigned int i = 0; i < sizeof insns / sizeof insns[0]; i++) {
1177       if (insns[i] != insns1[i]) {
1178         ok = false;
1179         printf("Ours:\n");
1180         Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]);
1181         printf("Theirs:\n");
1182         Disassembler::decode((address)&insns[i], (address)&insns[i+1]);
1183         printf("\n");
1184       }
1185     }
1186     assert(ok, "Assembler smoke test failed");
1187   }
1188 
1189 #ifndef PRODUCT
1190 
1191   address PC = __ pc();
1192   __ ld1(v0, __ T16B, Address(r16)); // No offset
1193   __ ld1(v0, __ T16B, __ post(r16, 0)); // Post-index
1194   __ ld1(v0, __ T16B, Address(r16, r17)); // 
1195 
1196 
1197 #endif // PRODUCT
1198 }
1199 
1200 #endif // ASSERT
1201 
1202 #undef __
1203 
1204 void Assembler::emit_data64(jlong data,
1205                             relocInfo::relocType rtype,
1206                             int format) {
1207   if (rtype == relocInfo::none) {
1208     emit_int64(data);
1209   } else {
1210     emit_data64(data, Relocation::spec_simple(rtype), format);
1211   }
1212 }
1213 
1214 void Assembler::emit_data64(jlong data,
1215                             RelocationHolder const& rspec,
1216                             int format) {
1217 
1218   assert(inst_mark() != NULL, "must be inside InstructionMark");
1219   // Do not use AbstractAssembler::relocate, which is not intended for
1220   // embedded words.  Instead, relocate to the enclosing instruction.
1221   code_section()->relocate(inst_mark(), rspec, format);
1222   emit_int64(data);
1223 }
1224 
1225 extern "C" {
1226   void das(uint64_t start, int len) {
1227     ResourceMark rm;
1228     len <<= 2;
1229     if (len < 0)
1230       Disassembler::decode((address)start + len, (address)start);
1231     else
1232       Disassembler::decode((address)start, (address)start + len);
1233   }
1234 
1235   JNIEXPORT void das1(unsigned long insn) {
1236     das(insn, 1);
1237   }
1238 }
1239 
1240 #define gas_assert(ARG1) assert(ARG1, #ARG1)
1241 
1242 #define __ as->
1243 
1244 void Address::lea(MacroAssembler *as, Register r) const {
1245   Relocation* reloc = _rspec.reloc();
1246   relocInfo::relocType rtype = (relocInfo::relocType) reloc->type();
1247 
1248   switch(_mode) {
1249   case base_plus_offset: {
1250     if (_offset == 0 && _base == r) // it's a nop
1251       break;
1252     if (_offset > 0)
1253       __ add(r, _base, _offset);
1254     else
1255       __ sub(r, _base, -_offset);
1256       break;
1257   }
1258   case base_plus_offset_reg: {
1259     __ add(r, _base, _index, _ext.op(), MAX(_ext.shift(), 0));
1260     break;
1261   }
1262   case literal: {
1263     if (rtype == relocInfo::none)
1264       __ mov(r, target());
1265     else
1266       __ movptr(r, (uint64_t)target());
1267     break;
1268   }
1269   case post: {
1270     __ mov(r, _base);
1271     break;
1272   }
1273   default:
1274     ShouldNotReachHere();
1275   }
1276 }
1277 
1278 void Assembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
1279   ShouldNotReachHere();
1280 }
1281 
1282 #undef __
1283 
1284 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
1285 
1286   void Assembler::adr(Register Rd, address adr) {
1287     long offset = adr - pc();
1288     int offset_lo = offset & 3;
1289     offset >>= 2;
1290     starti;
1291     f(0, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1292     rf(Rd, 0);
1293   }
1294 
1295   void Assembler::_adrp(Register Rd, address adr) {
1296     uint64_t pc_page = (uint64_t)pc() >> 12;
1297     uint64_t adr_page = (uint64_t)adr >> 12;
1298     long offset = adr_page - pc_page;
1299     int offset_lo = offset & 3;
1300     offset >>= 2;
1301     starti;
1302     f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1303     rf(Rd, 0);
1304   }
1305 
1306 #undef starti
1307 
1308 Address::Address(address target, relocInfo::relocType rtype) : _mode(literal){
1309   _is_lval = false;
1310   _target = target;
1311   switch (rtype) {
1312   case relocInfo::oop_type:
1313   case relocInfo::metadata_type:
1314     // Oops are a special case. Normally they would be their own section
1315     // but in cases like icBuffer they are literals in the code stream that
1316     // we don't have a section for. We use none so that we get a literal address
1317     // which is always patchable.
1318     break;
1319   case relocInfo::external_word_type:
1320     _rspec = external_word_Relocation::spec(target);
1321     break;
1322   case relocInfo::internal_word_type:
1323     _rspec = internal_word_Relocation::spec(target);
1324     break;
1325   case relocInfo::opt_virtual_call_type:
1326     _rspec = opt_virtual_call_Relocation::spec();
1327     break;
1328   case relocInfo::static_call_type:
1329     _rspec = static_call_Relocation::spec();
1330     break;
1331   case relocInfo::runtime_call_type:
1332     _rspec = runtime_call_Relocation::spec();
1333     break;
1334   case relocInfo::poll_type:
1335   case relocInfo::poll_return_type:
1336     _rspec = Relocation::spec_simple(rtype);
1337     break;
1338   case relocInfo::none:
1339     _rspec = RelocationHolder::none;
1340     break;
1341   default:
1342     ShouldNotReachHere();
1343     break;
1344   }
1345 }
1346 
1347 void Assembler::b(const Address &dest) {
1348   InstructionMark im(this);
1349   code_section()->relocate(inst_mark(), dest.rspec());
1350   b(dest.target());
1351 }
1352 
1353 void Assembler::bl(const Address &dest) {
1354   InstructionMark im(this);
1355   code_section()->relocate(inst_mark(), dest.rspec());
1356   bl(dest.target());
1357 }
1358 
1359 void Assembler::adr(Register r, const Address &dest) {
1360   InstructionMark im(this);
1361   code_section()->relocate(inst_mark(), dest.rspec());
1362   adr(r, dest.target());
1363 }
1364 
1365 void Assembler::br(Condition cc, Label &L) {
1366   if (L.is_bound()) {
1367     br(cc, target(L));
1368   } else {
1369     L.add_patch_at(code(), locator());
1370     br(cc, pc());
1371   }
1372 }
1373 
1374 void Assembler::wrap_label(Label &L,
1375                                  Assembler::uncond_branch_insn insn) {
1376   if (L.is_bound()) {
1377     (this->*insn)(target(L));
1378   } else {
1379     L.add_patch_at(code(), locator());
1380     (this->*insn)(pc());
1381   }
1382 }
1383 
1384 void Assembler::wrap_label(Register r, Label &L,
1385                                  compare_and_branch_insn insn) {
1386   if (L.is_bound()) {
1387     (this->*insn)(r, target(L));
1388   } else {
1389     L.add_patch_at(code(), locator());
1390     (this->*insn)(r, pc());
1391   }
1392 }
1393 
1394 void Assembler::wrap_label(Register r, int bitpos, Label &L,
1395                                  test_and_branch_insn insn) {
1396   if (L.is_bound()) {
1397     (this->*insn)(r, bitpos, target(L));
1398   } else {
1399     L.add_patch_at(code(), locator());
1400     (this->*insn)(r, bitpos, pc());
1401   }
1402 }
1403 
1404 void Assembler::wrap_label(Label &L, prfop op, prefetch_insn insn) {
1405   if (L.is_bound()) {
1406     (this->*insn)(target(L), op);
1407   } else {
1408     L.add_patch_at(code(), locator());
1409     (this->*insn)(pc(), op);
1410   }
1411 }
1412 
1413   // An "all-purpose" add/subtract immediate, per ARM documentation:
1414   // A "programmer-friendly" assembler may accept a negative immediate
1415   // between -(2^24 -1) and -1 inclusive, causing it to convert a
1416   // requested ADD operation to a SUB, or vice versa, and then encode
1417   // the absolute value of the immediate as for uimm24.
1418 void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
1419                                   int negated_op) {
1420   bool sets_flags = op & 1;   // this op sets flags
1421   union {
1422     unsigned u;
1423     int imm;
1424   };
1425   u = uimm;
1426   bool shift = false;
1427   bool neg = imm < 0;
1428   if (neg) {
1429     imm = -imm;
1430     op = negated_op;
1431   }
1432   assert(Rd != sp || imm % 16 == 0, "misaligned stack");
1433   if (imm >= (1 << 11)
1434       && ((imm >> 12) << 12 == imm)) {
1435     imm >>= 12;
1436     shift = true;
1437   }
1438   f(op, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10);
1439 
1440   // add/subtract immediate ops with the S bit set treat r31 as zr;
1441   // with S unset they use sp.
1442   if (sets_flags)
1443     zrf(Rd, 0);
1444   else
1445     srf(Rd, 0);
1446 
1447   srf(Rn, 5);
1448 }
1449 
1450 bool Assembler::operand_valid_for_add_sub_immediate(long imm) {
1451   bool shift = false;
1452   unsigned long uimm = uabs(imm);
1453   if (uimm < (1 << 12))
1454     return true;
1455   if (uimm < (1 << 24)
1456       && ((uimm >> 12) << 12 == uimm)) {
1457     return true;
1458   }
1459   return false;
1460 }
1461 
1462 bool Assembler::operand_valid_for_logical_immediate(bool is32, uint64_t imm) {
1463   return encode_logical_immediate(is32, imm) != 0xffffffff;
1464 }
1465 
1466 static uint64_t doubleTo64Bits(jdouble d) {
1467   union {
1468     jdouble double_value;
1469     uint64_t double_bits;
1470   };
1471 
1472   double_value = d;
1473   return double_bits;
1474 }
1475 
1476 bool Assembler::operand_valid_for_float_immediate(double imm) {
1477   // If imm is all zero bits we can use ZR as the source of a
1478   // floating-point value.
1479   if (doubleTo64Bits(imm) == 0)
1480     return true;
1481 
1482   // Otherwise try to encode imm then convert the encoded value back
1483   // and make sure it's the exact same bit pattern.
1484   unsigned result = encoding_for_fp_immediate(imm);
1485   return doubleTo64Bits(imm) == fp_immediate_for_encoding(result, true);
1486 }
1487 
1488 int AbstractAssembler::code_fill_byte() {
1489   return 0;
1490 }
1491 
1492 // n.b. this is implemented in subclass MacroAssembler
1493 void Assembler::bang_stack_with_offset(int offset) { Unimplemented(); }
1494 
1495 
1496 // and now the routines called by the assembler which encapsulate the
1497 // above encode and decode functions
1498 
1499 uint32_t
1500 asm_util::encode_logical_immediate(bool is32, uint64_t imm)
1501 {
1502   if (is32) {
1503     /* Allow all zeros or all ones in top 32-bits, so that
1504        constant expressions like ~1 are permitted. */
1505     if (imm >> 32 != 0 && imm >> 32 != 0xffffffff)
1506       return 0xffffffff;
1507     /* Replicate the 32 lower bits to the 32 upper bits.  */
1508     imm &= 0xffffffff;
1509     imm |= imm << 32;
1510   }
1511 
1512   return encoding_for_logical_immediate(imm);
1513 }
1514 
1515 unsigned Assembler::pack(double value) {
1516   float val = (float)value;
1517   unsigned result = encoding_for_fp_immediate(val);
1518   guarantee(unpack(result) == value,
1519             "Invalid floating-point immediate operand");
1520   return result;
1521 }
1522 
1523 // Packed operands for  Floating-point Move (immediate)
1524 
1525 static float unpack(unsigned value) {
1526   union {
1527     unsigned ival;
1528     float val;
1529   };
1530   ival = fp_immediate_for_encoding(value, 0);
1531   return val;
1532 }