1 /*
   2  * Copyright (c) 2013, Red Hat Inc.
   3  * Copyright (c) 1997, 2011, Oracle and/or its affiliates.
   4  * All rights reserved.
   5  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   6  *
   7  * This code is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 only, as
   9  * published by the Free Software Foundation.
  10  *
  11  * This code is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * version 2 for more details (a copy is included in the LICENSE file that
  15  * accompanied this code).
  16  *
  17  * You should have received a copy of the GNU General Public License version
  18  * 2 along with this work; if not, write to the Free Software Foundation,
  19  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  20  *
  21  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  22  * or visit www.oracle.com if you need additional information or have any
  23  * questions.
  24  *
  25  */
  26 
  27 #ifndef CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP
  28 #define CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP
  29 
  30 #include "runtime/globals_extension.hpp"
  31 #include "runtime/vm_version.hpp"
  32 
  33 class VM_Version : public Abstract_VM_Version {
  34 public:
  35 protected:
  36   static int _cpu;
  37   static int _model;
  38   static int _model2;
  39   static int _variant;
  40   static int _revision;
  41   static int _stepping;
  42   static int _cpuFeatures;     // features returned by the "cpuid" instruction
  43                                // 0 if this instruction is not available
  44   static const char* _features_str;
  45 
  46   struct PsrInfo {
  47     uint32_t dczid_el0;
  48     uint32_t ctr_el0;
  49   };
  50   static PsrInfo _psr_info;
  51   static void get_processor_features();
  52 
  53 public:
  54   // Initialization
  55   static void initialize();
  56 
  57   // Asserts
  58   static void assert_is_initialized() {
  59   }
  60 
  61   enum {
  62     CPU_ARM       = 'A',
  63     CPU_BROADCOM  = 'B',
  64     CPU_CAVIUM    = 'C',
  65     CPU_DEC       = 'D',
  66     CPU_INFINEON  = 'I',
  67     CPU_MOTOROLA  = 'M',
  68     CPU_NVIDIA    = 'N',
  69     CPU_AMCC      = 'P',
  70     CPU_QUALCOM   = 'Q',
  71     CPU_MARVELL   = 'V',
  72     CPU_INTEL     = 'i',
  73   } cpuFamily;
  74 
  75   enum {
  76     CPU_FP           = (1<<0),
  77     CPU_ASIMD        = (1<<1),
  78     CPU_EVTSTRM      = (1<<2),
  79     CPU_AES          = (1<<3),
  80     CPU_PMULL        = (1<<4),
  81     CPU_SHA1         = (1<<5),
  82     CPU_SHA2         = (1<<6),
  83     CPU_CRC32        = (1<<7),
  84     CPU_LSE          = (1<<8),
  85     CPU_STXR_PREFETCH= (1 << 29),
  86     CPU_A53MAC       = (1 << 30),
  87     CPU_DMB_ATOMICS  = (1 << 31),
  88   } cpuFeatureFlags;
  89 
  90   static const char* cpu_features()           { return _features_str; }
  91   static int cpu_family()                     { return _cpu; }
  92   static int cpu_model()                      { return _model; }
  93   static int cpu_variant()                    { return _variant; }
  94   static int cpu_revision()                   { return _revision; }
  95   static int cpu_cpuFeatures()                { return _cpuFeatures; }
  96   static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); }
  97   static ByteSize ctr_el0_offset()   { return byte_offset_of(PsrInfo, ctr_el0); }
  98   static bool is_zva_enabled() {
  99     // Check the DZP bit (bit 4) of dczid_el0 is zero
 100     // and block size (bit 0~3) is not zero.
 101     return ((_psr_info.dczid_el0 & 0x10) == 0 &&
 102             (_psr_info.dczid_el0 & 0xf) != 0);
 103   }
 104   static int zva_length() {
 105     assert(is_zva_enabled(), "ZVA not available");
 106     return 4 << (_psr_info.dczid_el0 & 0xf);
 107   }
 108   static int icache_line_size() {
 109     return (1 << (_psr_info.ctr_el0 & 0x0f)) * 4;
 110   }
 111   static int dcache_line_size() {
 112     return (1 << ((_psr_info.ctr_el0 >> 16) & 0x0f)) * 4;
 113   }
 114 };
 115 
 116 #endif // CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP