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src/cpu/x86/vm/macroAssembler_x86.cpp

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*** 41,50 **** --- 41,52 ---- #include "utilities/macros.hpp" #if INCLUDE_ALL_GCS #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" #include "gc_implementation/g1/heapRegion.hpp" + #include "shenandoahBarrierSetAssembler_x86.hpp" + #include "gc_implementation/shenandoah/shenandoahHeap.inline.hpp" #endif // INCLUDE_ALL_GCS #ifdef PRODUCT #define BLOCK_COMMENT(str) /* nothing */ #define STOP(error) stop(error)
*** 4130,4140 **** jcc(Assembler::zero, not_weak); // Resolve jweak. movptr(value, Address(value, -JNIHandles::weak_tag_value)); verify_oop(value); #if INCLUDE_ALL_GCS ! if (UseG1GC) { g1_write_barrier_pre(noreg /* obj */, value /* pre_val */, thread /* thread */, tmp /* tmp */, true /* tosca_live */, --- 4132,4142 ---- jcc(Assembler::zero, not_weak); // Resolve jweak. movptr(value, Address(value, -JNIHandles::weak_tag_value)); verify_oop(value); #if INCLUDE_ALL_GCS ! if (UseG1GC || (UseShenandoahGC && ShenandoahSATBBarrier)) { g1_write_barrier_pre(noreg /* obj */, value /* pre_val */, thread /* thread */, tmp /* tmp */, true /* tosca_live */,
*** 4189,4207 **** Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_index())); Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_buf())); ! ! // Is marking active? ! if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { ! cmpl(in_progress, 0); ! } else { ! assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); ! cmpb(in_progress, 0); } - jcc(Assembler::equal, done); // Do we need to load the previous value? if (obj != noreg) { load_heap_oop(pre_val, Address(obj, 0)); } --- 4191,4215 ---- Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_index())); Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + PtrQueue::byte_offset_of_buf())); ! if (UseShenandoahGC) { ! Address gc_state(thread, in_bytes(JavaThread::gc_state_offset())); ! testb(gc_state, ShenandoahHeap::MARKING); ! jcc(Assembler::zero, done); ! } else { ! assert(UseG1GC, "Should be"); ! // Is marking active? ! if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { ! cmpl(in_progress, 0); ! } else { ! assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); ! cmpb(in_progress, 0); ! } ! jcc(Assembler::equal, done); } // Do we need to load the previous value? if (obj != noreg) { load_heap_oop(pre_val, Address(obj, 0)); }
*** 4280,4289 **** --- 4288,4304 ---- Register tmp2) { #ifdef _LP64 assert(thread == r15_thread, "must be"); #endif // _LP64 + if (UseShenandoahGC) { + // No need for this in Shenandoah. + return; + } + + assert(UseG1GC, "expect G1 GC"); + Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + PtrQueue::byte_offset_of_index())); Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + PtrQueue::byte_offset_of_buf()));
*** 4615,4683 **** } void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) { pusha(); // if we are coming from c1, xmm registers may be live - int off = 0; - if (UseSSE == 1) { - subptr(rsp, sizeof(jdouble)*8); - movflt(Address(rsp,off++*sizeof(jdouble)),xmm0); - movflt(Address(rsp,off++*sizeof(jdouble)),xmm1); - movflt(Address(rsp,off++*sizeof(jdouble)),xmm2); - movflt(Address(rsp,off++*sizeof(jdouble)),xmm3); - movflt(Address(rsp,off++*sizeof(jdouble)),xmm4); - movflt(Address(rsp,off++*sizeof(jdouble)),xmm5); - movflt(Address(rsp,off++*sizeof(jdouble)),xmm6); - movflt(Address(rsp,off++*sizeof(jdouble)),xmm7); - } else if (UseSSE >= 2) { - #ifdef COMPILER2 - if (MaxVectorSize > 16) { - assert(UseAVX > 0, "256bit vectors are supported only with AVX"); - // Save upper half of YMM registes - subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); - vextractf128h(Address(rsp, 0),xmm0); - vextractf128h(Address(rsp, 16),xmm1); - vextractf128h(Address(rsp, 32),xmm2); - vextractf128h(Address(rsp, 48),xmm3); - vextractf128h(Address(rsp, 64),xmm4); - vextractf128h(Address(rsp, 80),xmm5); - vextractf128h(Address(rsp, 96),xmm6); - vextractf128h(Address(rsp,112),xmm7); - #ifdef _LP64 - vextractf128h(Address(rsp,128),xmm8); - vextractf128h(Address(rsp,144),xmm9); - vextractf128h(Address(rsp,160),xmm10); - vextractf128h(Address(rsp,176),xmm11); - vextractf128h(Address(rsp,192),xmm12); - vextractf128h(Address(rsp,208),xmm13); - vextractf128h(Address(rsp,224),xmm14); - vextractf128h(Address(rsp,240),xmm15); - #endif - } - #endif - // Save whole 128bit (16 bytes) XMM regiters - subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); - movdqu(Address(rsp,off++*16),xmm0); - movdqu(Address(rsp,off++*16),xmm1); - movdqu(Address(rsp,off++*16),xmm2); - movdqu(Address(rsp,off++*16),xmm3); - movdqu(Address(rsp,off++*16),xmm4); - movdqu(Address(rsp,off++*16),xmm5); - movdqu(Address(rsp,off++*16),xmm6); - movdqu(Address(rsp,off++*16),xmm7); - #ifdef _LP64 - movdqu(Address(rsp,off++*16),xmm8); - movdqu(Address(rsp,off++*16),xmm9); - movdqu(Address(rsp,off++*16),xmm10); - movdqu(Address(rsp,off++*16),xmm11); - movdqu(Address(rsp,off++*16),xmm12); - movdqu(Address(rsp,off++*16),xmm13); - movdqu(Address(rsp,off++*16),xmm14); - movdqu(Address(rsp,off++*16),xmm15); - #endif - } // Preserve registers across runtime call int incoming_argument_and_return_value_offset = -1; if (num_fpu_regs_in_use > 1) { // Must preserve all other FPU regs (could alternatively convert --- 4630,4642 ---- } void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) { pusha(); + save_vector_registers(); + // if we are coming from c1, xmm registers may be live // Preserve registers across runtime call int incoming_argument_and_return_value_offset = -1; if (num_fpu_regs_in_use > 1) { // Must preserve all other FPU regs (could alternatively convert
*** 4739,4749 **** } fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble))); addptr(rsp, sizeof(jdouble) * nb_args); } ! off = 0; if (UseSSE == 1) { movflt(xmm0, Address(rsp,off++*sizeof(jdouble))); movflt(xmm1, Address(rsp,off++*sizeof(jdouble))); movflt(xmm2, Address(rsp,off++*sizeof(jdouble))); movflt(xmm3, Address(rsp,off++*sizeof(jdouble))); --- 4698,4774 ---- } fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble))); addptr(rsp, sizeof(jdouble) * nb_args); } ! restore_vector_registers(); ! popa(); ! } ! ! void MacroAssembler::save_vector_registers() { ! int off = 0; ! if (UseSSE == 1) { ! subptr(rsp, sizeof(jdouble)*8); ! movflt(Address(rsp,off++*sizeof(jdouble)),xmm0); ! movflt(Address(rsp,off++*sizeof(jdouble)),xmm1); ! movflt(Address(rsp,off++*sizeof(jdouble)),xmm2); ! movflt(Address(rsp,off++*sizeof(jdouble)),xmm3); ! movflt(Address(rsp,off++*sizeof(jdouble)),xmm4); ! movflt(Address(rsp,off++*sizeof(jdouble)),xmm5); ! movflt(Address(rsp,off++*sizeof(jdouble)),xmm6); ! movflt(Address(rsp,off++*sizeof(jdouble)),xmm7); ! } else if (UseSSE >= 2) { ! #ifdef COMPILER2 ! if (MaxVectorSize > 16) { ! assert(UseAVX > 0, "256bit vectors are supported only with AVX"); ! // Save upper half of YMM registes ! subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); ! vextractf128h(Address(rsp, 0),xmm0); ! vextractf128h(Address(rsp, 16),xmm1); ! vextractf128h(Address(rsp, 32),xmm2); ! vextractf128h(Address(rsp, 48),xmm3); ! vextractf128h(Address(rsp, 64),xmm4); ! vextractf128h(Address(rsp, 80),xmm5); ! vextractf128h(Address(rsp, 96),xmm6); ! vextractf128h(Address(rsp,112),xmm7); ! #ifdef _LP64 ! vextractf128h(Address(rsp,128),xmm8); ! vextractf128h(Address(rsp,144),xmm9); ! vextractf128h(Address(rsp,160),xmm10); ! vextractf128h(Address(rsp,176),xmm11); ! vextractf128h(Address(rsp,192),xmm12); ! vextractf128h(Address(rsp,208),xmm13); ! vextractf128h(Address(rsp,224),xmm14); ! vextractf128h(Address(rsp,240),xmm15); ! #endif ! } ! #endif ! // Save whole 128bit (16 bytes) XMM regiters ! subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); ! movdqu(Address(rsp,off++*16),xmm0); ! movdqu(Address(rsp,off++*16),xmm1); ! movdqu(Address(rsp,off++*16),xmm2); ! movdqu(Address(rsp,off++*16),xmm3); ! movdqu(Address(rsp,off++*16),xmm4); ! movdqu(Address(rsp,off++*16),xmm5); ! movdqu(Address(rsp,off++*16),xmm6); ! movdqu(Address(rsp,off++*16),xmm7); ! #ifdef _LP64 ! movdqu(Address(rsp,off++*16),xmm8); ! movdqu(Address(rsp,off++*16),xmm9); ! movdqu(Address(rsp,off++*16),xmm10); ! movdqu(Address(rsp,off++*16),xmm11); ! movdqu(Address(rsp,off++*16),xmm12); ! movdqu(Address(rsp,off++*16),xmm13); ! movdqu(Address(rsp,off++*16),xmm14); ! movdqu(Address(rsp,off++*16),xmm15); ! #endif ! } ! } ! ! void MacroAssembler::restore_vector_registers() { ! int off = 0; if (UseSSE == 1) { movflt(xmm0, Address(rsp,off++*sizeof(jdouble))); movflt(xmm1, Address(rsp,off++*sizeof(jdouble))); movflt(xmm2, Address(rsp,off++*sizeof(jdouble))); movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
*** 4796,4806 **** #endif addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); } #endif } - popa(); } static const double pi_4 = 0.7853981633974483; void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { --- 4821,4830 ----
*** 5232,5242 **** call(rax); // Caller pops the arguments (oop, message) and restores rax, r10 BLOCK_COMMENT("} verify_oop"); } - RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset) { intptr_t value = *delayed_value_addr; if (value != 0) --- 5256,5265 ----
*** 5769,5778 **** --- 5792,5807 ---- movl(dst, src); decode_heap_oop(dst); } else #endif movptr(dst, src); + + #if INCLUDE_ALL_GCS + if (UseShenandoahGC) { + ShenandoahBarrierSetAssembler::bsasm()->load_reference_barrier(this, dst); + } + #endif } // Doesn't do verfication, generates fixed size code void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { #ifdef _LP64
*** 5780,5789 **** --- 5809,5824 ---- movl(dst, src); decode_heap_oop_not_null(dst); } else #endif movptr(dst, src); + + #if INCLUDE_ALL_GCS + if (UseShenandoahGC) { + ShenandoahBarrierSetAssembler::bsasm()->load_reference_barrier(this, dst); + } + #endif } void MacroAssembler::store_heap_oop(Address dst, Register src) { #ifdef _LP64 if (UseCompressedOops) {
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