1 /*
   2  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "utilities/macros.hpp"
  30 #include "runtime/rtmLocking.hpp"
  31 
  32 
  33 // MacroAssembler extends Assembler by frequently used macros.
  34 //
  35 // Instructions for which a 'better' code sequence exists depending
  36 // on arguments should also go in here.
  37 
  38 class MacroAssembler: public Assembler {
  39   friend class LIR_Assembler;
  40   friend class Runtime1;      // as_Address()
  41 
  42  protected:
  43 
  44   Address as_Address(AddressLiteral adr);
  45   Address as_Address(ArrayAddress adr);
  46 
  47   // Support for VM calls
  48   //
  49   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  50   // may customize this version by overriding it for its purposes (e.g., to save/restore
  51   // additional registers when doing a VM call).
  52 #ifdef CC_INTERP
  53   // c++ interpreter never wants to use interp_masm version of call_VM
  54   #define VIRTUAL
  55 #else
  56   #define VIRTUAL virtual
  57 #endif
  58 
  59   VIRTUAL void call_VM_leaf_base(
  60     address entry_point,               // the entry point
  61     int     number_of_arguments        // the number of arguments to pop after the call
  62   );
  63 
  64   // This is the base routine called by the different versions of call_VM. The interpreter
  65   // may customize this version by overriding it for its purposes (e.g., to save/restore
  66   // additional registers when doing a VM call).
  67   //
  68   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
  69   // returns the register which contains the thread upon return. If a thread register has been
  70   // specified, the return value will correspond to that register. If no last_java_sp is specified
  71   // (noreg) than rsp will be used instead.
  72   VIRTUAL void call_VM_base(           // returns the register containing the thread upon return
  73     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  74     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  75     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  76     address  entry_point,              // the entry point
  77     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  78     bool     check_exceptions          // whether to check for pending exceptions after return
  79   );
  80 
  81   // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  82   // The implementation is only non-empty for the InterpreterMacroAssembler,
  83   // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  84   virtual void check_and_handle_popframe(Register java_thread);
  85   virtual void check_and_handle_earlyret(Register java_thread);
  86 
  87   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  88 
  89   // helpers for FPU flag access
  90   // tmp is a temporary register, if none is available use noreg
  91   void save_rax   (Register tmp);
  92   void restore_rax(Register tmp);
  93 
  94  public:
  95   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  96 
  97   // Support for NULL-checks
  98   //
  99   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 100   // If the accessed location is M[reg + offset] and the offset is known, provide the
 101   // offset. No explicit code generation is needed if the offset is within a certain
 102   // range (0 <= offset <= page_size).
 103 
 104   void null_check(Register reg, int offset = -1);
 105   static bool needs_explicit_null_check(intptr_t offset);
 106 
 107   // Required platform-specific helpers for Label::patch_instructions.
 108   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 109   void pd_patch_instruction(address branch, address target) {
 110     unsigned char op = branch[0];
 111     assert(op == 0xE8 /* call */ ||
 112         op == 0xE9 /* jmp */ ||
 113         op == 0xEB /* short jmp */ ||
 114         (op & 0xF0) == 0x70 /* short jcc */ ||
 115         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
 116         op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
 117         "Invalid opcode at patch point");
 118 
 119     if (op == 0xEB || (op & 0xF0) == 0x70) {
 120       // short offset operators (jmp and jcc)
 121       char* disp = (char*) &branch[1];
 122       int imm8 = target - (address) &disp[1];
 123       guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
 124       *disp = imm8;
 125     } else {
 126       int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
 127       int imm32 = target - (address) &disp[1];
 128       *disp = imm32;
 129     }
 130   }
 131 
 132   // The following 4 methods return the offset of the appropriate move instruction
 133 
 134   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 135   int load_unsigned_byte(Register dst, Address src);
 136   int load_unsigned_short(Register dst, Address src);
 137 
 138   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 139   int load_signed_byte(Register dst, Address src);
 140   int load_signed_short(Register dst, Address src);
 141 
 142   // Support for sign-extension (hi:lo = extend_sign(lo))
 143   void extend_sign(Register hi, Register lo);
 144 
 145   // Load and store values by size and signed-ness
 146   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 147   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 148 
 149   // Support for inc/dec with optimal instruction selection depending on value
 150 
 151   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
 152   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
 153 
 154   void decrementl(Address dst, int value = 1);
 155   void decrementl(Register reg, int value = 1);
 156 
 157   void decrementq(Register reg, int value = 1);
 158   void decrementq(Address dst, int value = 1);
 159 
 160   void incrementl(Address dst, int value = 1);
 161   void incrementl(Register reg, int value = 1);
 162 
 163   void incrementq(Register reg, int value = 1);
 164   void incrementq(Address dst, int value = 1);
 165 
 166   // Support optimal SSE move instructions.
 167   void movflt(XMMRegister dst, XMMRegister src) {
 168     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
 169     else                       { movss (dst, src); return; }
 170   }
 171   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
 172   void movflt(XMMRegister dst, AddressLiteral src);
 173   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
 174 
 175   void movdbl(XMMRegister dst, XMMRegister src) {
 176     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
 177     else                       { movsd (dst, src); return; }
 178   }
 179 
 180   void movdbl(XMMRegister dst, AddressLiteral src);
 181 
 182   void movdbl(XMMRegister dst, Address src) {
 183     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
 184     else                         { movlpd(dst, src); return; }
 185   }
 186   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
 187 
 188   void incrementl(AddressLiteral dst);
 189   void incrementl(ArrayAddress dst);
 190 
 191   void incrementq(AddressLiteral dst);
 192 
 193   // Alignment
 194   void align(int modulus);
 195 
 196   // A 5 byte nop that is safe for patching (see patch_verified_entry)
 197   void fat_nop();
 198 
 199   // Stack frame creation/removal
 200   void enter();
 201   void leave();
 202 
 203   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 204   // The pointer will be loaded into the thread register.
 205   void get_thread(Register thread);
 206 
 207 
 208   // Support for VM calls
 209   //
 210   // It is imperative that all calls into the VM are handled via the call_VM macros.
 211   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 212   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 213 
 214 
 215   void call_VM(Register oop_result,
 216                address entry_point,
 217                bool check_exceptions = true);
 218   void call_VM(Register oop_result,
 219                address entry_point,
 220                Register arg_1,
 221                bool check_exceptions = true);
 222   void call_VM(Register oop_result,
 223                address entry_point,
 224                Register arg_1, Register arg_2,
 225                bool check_exceptions = true);
 226   void call_VM(Register oop_result,
 227                address entry_point,
 228                Register arg_1, Register arg_2, Register arg_3,
 229                bool check_exceptions = true);
 230 
 231   // Overloadings with last_Java_sp
 232   void call_VM(Register oop_result,
 233                Register last_java_sp,
 234                address entry_point,
 235                int number_of_arguments = 0,
 236                bool check_exceptions = true);
 237   void call_VM(Register oop_result,
 238                Register last_java_sp,
 239                address entry_point,
 240                Register arg_1, bool
 241                check_exceptions = true);
 242   void call_VM(Register oop_result,
 243                Register last_java_sp,
 244                address entry_point,
 245                Register arg_1, Register arg_2,
 246                bool check_exceptions = true);
 247   void call_VM(Register oop_result,
 248                Register last_java_sp,
 249                address entry_point,
 250                Register arg_1, Register arg_2, Register arg_3,
 251                bool check_exceptions = true);
 252 
 253   void get_vm_result  (Register oop_result, Register thread);
 254   void get_vm_result_2(Register metadata_result, Register thread);
 255 
 256   // These always tightly bind to MacroAssembler::call_VM_base
 257   // bypassing the virtual implementation
 258   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 259   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 260   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 261   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 262   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 263 
 264   void call_VM_leaf(address entry_point,
 265                     int number_of_arguments = 0);
 266   void call_VM_leaf(address entry_point,
 267                     Register arg_1);
 268   void call_VM_leaf(address entry_point,
 269                     Register arg_1, Register arg_2);
 270   void call_VM_leaf(address entry_point,
 271                     Register arg_1, Register arg_2, Register arg_3);
 272 
 273   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 274   // bypassing the virtual implementation
 275   void super_call_VM_leaf(address entry_point);
 276   void super_call_VM_leaf(address entry_point, Register arg_1);
 277   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 278   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 279   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 280 
 281   // last Java Frame (fills frame anchor)
 282   void set_last_Java_frame(Register thread,
 283                            Register last_java_sp,
 284                            Register last_java_fp,
 285                            address last_java_pc);
 286 
 287   // thread in the default location (r15_thread on 64bit)
 288   void set_last_Java_frame(Register last_java_sp,
 289                            Register last_java_fp,
 290                            address last_java_pc);
 291 
 292   void reset_last_Java_frame(Register thread, bool clear_fp);
 293 
 294   // thread in the default location (r15_thread on 64bit)
 295   void reset_last_Java_frame(bool clear_fp);
 296 
 297   // Stores
 298   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 299   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 300 
 301   void resolve_jobject(Register value, Register thread, Register tmp);
 302   void clear_jweak_tag(Register possibly_jweak);
 303 
 304 #if INCLUDE_ALL_GCS
 305 
 306   void g1_write_barrier_pre(Register obj,
 307                             Register pre_val,
 308                             Register thread,
 309                             Register tmp,
 310                             bool tosca_live,
 311                             bool expand_call);
 312 
 313   void g1_write_barrier_post(Register store_addr,
 314                              Register new_val,
 315                              Register thread,
 316                              Register tmp,
 317                              Register tmp2);
 318 
 319 #endif // INCLUDE_ALL_GCS
 320 
 321   // split store_check(Register obj) to enhance instruction interleaving
 322   void store_check_part_1(Register obj);
 323   void store_check_part_2(Register obj);
 324 
 325   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 326   void c2bool(Register x);
 327 
 328   // C++ bool manipulation
 329 
 330   void movbool(Register dst, Address src);
 331   void movbool(Address dst, bool boolconst);
 332   void movbool(Address dst, Register src);
 333   void testbool(Register dst);
 334 
 335   // oop manipulations
 336   void load_klass(Register dst, Register src);
 337   void store_klass(Register dst, Register src);
 338 
 339   void load_heap_oop(Register dst, Address src);
 340   void load_heap_oop_not_null(Register dst, Address src);
 341   void store_heap_oop(Address dst, Register src);
 342   void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
 343 
 344   // Used for storing NULL. All other oop constants should be
 345   // stored using routines that take a jobject.
 346   void store_heap_oop_null(Address dst);
 347 
 348   void load_prototype_header(Register dst, Register src);
 349 
 350 #ifdef _LP64
 351   void store_klass_gap(Register dst, Register src);
 352 
 353   // This dummy is to prevent a call to store_heap_oop from
 354   // converting a zero (like NULL) into a Register by giving
 355   // the compiler two choices it can't resolve
 356 
 357   void store_heap_oop(Address dst, void* dummy);
 358 
 359   void encode_heap_oop(Register r);
 360   void decode_heap_oop(Register r);
 361   void encode_heap_oop_not_null(Register r);
 362   void decode_heap_oop_not_null(Register r);
 363   void encode_heap_oop_not_null(Register dst, Register src);
 364   void decode_heap_oop_not_null(Register dst, Register src);
 365 
 366   void set_narrow_oop(Register dst, jobject obj);
 367   void set_narrow_oop(Address dst, jobject obj);
 368   void cmp_narrow_oop(Register dst, jobject obj);
 369   void cmp_narrow_oop(Address dst, jobject obj);
 370 
 371   void encode_klass_not_null(Register r);
 372   void decode_klass_not_null(Register r);
 373   void encode_klass_not_null(Register dst, Register src);
 374   void decode_klass_not_null(Register dst, Register src);
 375   void set_narrow_klass(Register dst, Klass* k);
 376   void set_narrow_klass(Address dst, Klass* k);
 377   void cmp_narrow_klass(Register dst, Klass* k);
 378   void cmp_narrow_klass(Address dst, Klass* k);
 379 
 380   // Returns the byte size of the instructions generated by decode_klass_not_null()
 381   // when compressed klass pointers are being used.
 382   static int instr_size_for_decode_klass_not_null();
 383 
 384   // if heap base register is used - reinit it with the correct value
 385   void reinit_heapbase();
 386 
 387   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 388 
 389 #endif // _LP64
 390 
 391   // Int division/remainder for Java
 392   // (as idivl, but checks for special case as described in JVM spec.)
 393   // returns idivl instruction offset for implicit exception handling
 394   int corrected_idivl(Register reg);
 395 
 396   // Long division/remainder for Java
 397   // (as idivq, but checks for special case as described in JVM spec.)
 398   // returns idivq instruction offset for implicit exception handling
 399   int corrected_idivq(Register reg);
 400 
 401   void int3();
 402 
 403   // Long operation macros for a 32bit cpu
 404   // Long negation for Java
 405   void lneg(Register hi, Register lo);
 406 
 407   // Long multiplication for Java
 408   // (destroys contents of eax, ebx, ecx and edx)
 409   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
 410 
 411   // Long shifts for Java
 412   // (semantics as described in JVM spec.)
 413   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
 414   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
 415 
 416   // Long compare for Java
 417   // (semantics as described in JVM spec.)
 418   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
 419 
 420 
 421   // misc
 422 
 423   // Sign extension
 424   void sign_extend_short(Register reg);
 425   void sign_extend_byte(Register reg);
 426 
 427   // Division by power of 2, rounding towards 0
 428   void division_with_shift(Register reg, int shift_value);
 429 
 430   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
 431   //
 432   // CF (corresponds to C0) if x < y
 433   // PF (corresponds to C2) if unordered
 434   // ZF (corresponds to C3) if x = y
 435   //
 436   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 437   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
 438   void fcmp(Register tmp);
 439   // Variant of the above which allows y to be further down the stack
 440   // and which only pops x and y if specified. If pop_right is
 441   // specified then pop_left must also be specified.
 442   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
 443 
 444   // Floating-point comparison for Java
 445   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
 446   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 447   // (semantics as described in JVM spec.)
 448   void fcmp2int(Register dst, bool unordered_is_less);
 449   // Variant of the above which allows y to be further down the stack
 450   // and which only pops x and y if specified. If pop_right is
 451   // specified then pop_left must also be specified.
 452   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
 453 
 454   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
 455   // tmp is a temporary register, if none is available use noreg
 456   void fremr(Register tmp);
 457 
 458 
 459   // same as fcmp2int, but using SSE2
 460   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 461   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 462 
 463   // Inlined sin/cos generator for Java; must not use CPU instruction
 464   // directly on Intel as it does not have high enough precision
 465   // outside of the range [-pi/4, pi/4]. Extra argument indicate the
 466   // number of FPU stack slots in use; all but the topmost will
 467   // require saving if a slow case is necessary. Assumes argument is
 468   // on FP TOS; result is on FP TOS.  No cpu registers are changed by
 469   // this code.
 470   void trigfunc(char trig, int num_fpu_regs_in_use = 1);
 471 
 472   // branch to L if FPU flag C2 is set/not set
 473   // tmp is a temporary register, if none is available use noreg
 474   void jC2 (Register tmp, Label& L);
 475   void jnC2(Register tmp, Label& L);
 476 
 477   // Pop ST (ffree & fincstp combined)
 478   void fpop();
 479 
 480   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
 481   void push_fTOS();
 482 
 483   // pops double TOS element from CPU stack and pushes on FPU stack
 484   void pop_fTOS();
 485 
 486   void empty_FPU_stack();
 487 
 488   void push_IU_state();
 489   void pop_IU_state();
 490 
 491   void push_FPU_state();
 492   void pop_FPU_state();
 493 
 494   void push_CPU_state();
 495   void pop_CPU_state();
 496 
 497   // Round up to a power of two
 498   void round_to(Register reg, int modulus);
 499 
 500   // Callee saved registers handling
 501   void push_callee_saved_registers();
 502   void pop_callee_saved_registers();
 503 
 504   // allocation
 505   void eden_allocate(
 506     Register obj,                      // result: pointer to object after successful allocation
 507     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 508     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 509     Register t1,                       // temp register
 510     Label&   slow_case                 // continuation point if fast allocation fails
 511   );
 512   void tlab_allocate(
 513     Register obj,                      // result: pointer to object after successful allocation
 514     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 515     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 516     Register t1,                       // temp register
 517     Register t2,                       // temp register
 518     Label&   slow_case                 // continuation point if fast allocation fails
 519   );
 520   Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
 521   void incr_allocated_bytes(Register thread,
 522                             Register var_size_in_bytes, int con_size_in_bytes,
 523                             Register t1 = noreg);
 524 
 525   // interface method calling
 526   void lookup_interface_method(Register recv_klass,
 527                                Register intf_klass,
 528                                RegisterOrConstant itable_index,
 529                                Register method_result,
 530                                Register scan_temp,
 531                                Label& no_such_interface,
 532                                bool return_method = true);
 533 
 534   // virtual method calling
 535   void lookup_virtual_method(Register recv_klass,
 536                              RegisterOrConstant vtable_index,
 537                              Register method_result);
 538 
 539   // Test sub_klass against super_klass, with fast and slow paths.
 540 
 541   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 542   // One of the three labels can be NULL, meaning take the fall-through.
 543   // If super_check_offset is -1, the value is loaded up from super_klass.
 544   // No registers are killed, except temp_reg.
 545   void check_klass_subtype_fast_path(Register sub_klass,
 546                                      Register super_klass,
 547                                      Register temp_reg,
 548                                      Label* L_success,
 549                                      Label* L_failure,
 550                                      Label* L_slow_path,
 551                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 552 
 553   // The rest of the type check; must be wired to a corresponding fast path.
 554   // It does not repeat the fast path logic, so don't use it standalone.
 555   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 556   // Updates the sub's secondary super cache as necessary.
 557   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 558   void check_klass_subtype_slow_path(Register sub_klass,
 559                                      Register super_klass,
 560                                      Register temp_reg,
 561                                      Register temp2_reg,
 562                                      Label* L_success,
 563                                      Label* L_failure,
 564                                      bool set_cond_codes = false);
 565 
 566   // Simplified, combined version, good for typical uses.
 567   // Falls through on failure.
 568   void check_klass_subtype(Register sub_klass,
 569                            Register super_klass,
 570                            Register temp_reg,
 571                            Label& L_success);
 572 
 573   // method handles (JSR 292)
 574   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 575 
 576   //----
 577   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
 578 
 579   // Debugging
 580 
 581   // only if +VerifyOops
 582   // TODO: Make these macros with file and line like sparc version!
 583   void verify_oop(Register reg, const char* s = "broken oop");
 584   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 585 
 586 #if INCLUDE_ALL_GCS
 587   void in_heap_check(Register raddr, Register tmp, Label& done);
 588 #endif
 589 
 590   // TODO: verify method and klass metadata (compare against vptr?)
 591   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 592   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 593 
 594 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 595 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 596 
 597   // only if +VerifyFPU
 598   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 599 
 600   // Verify or restore cpu control state after JNI call
 601   void restore_cpu_control_state_after_jni();
 602 
 603   // prints msg, dumps registers and stops execution
 604   void stop(const char* msg);
 605 
 606   // prints msg and continues
 607   void warn(const char* msg);
 608 
 609   // dumps registers and other state
 610   void print_state();
 611 
 612   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
 613   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 614   static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
 615   static void print_state64(int64_t pc, int64_t regs[]);
 616 
 617   void os_breakpoint();
 618 
 619   void untested()                                { stop("untested"); }
 620 
 621   void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, 1024, "unimplemented: %s", what);  stop(b); }
 622 
 623   void should_not_reach_here()                   { stop("should not reach here"); }
 624 
 625   void print_CPU_state();
 626 
 627   // Stack overflow checking
 628   void bang_stack_with_offset(int offset) {
 629     // stack grows down, caller passes positive offset
 630     assert(offset > 0, "must bang with negative offset");
 631     movl(Address(rsp, (-offset)), rax);
 632   }
 633 
 634   // Writes to stack successive pages until offset reached to check for
 635   // stack overflow + shadow pages.  Also, clobbers tmp
 636   void bang_stack_size(Register size, Register tmp);
 637 
 638   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 639                                                 Register tmp,
 640                                                 int offset);
 641 
 642   // Support for serializing memory accesses between threads
 643   void serialize_memory(Register thread, Register tmp);
 644 
 645   void verify_tlab();
 646 
 647   // Biased locking support
 648   // lock_reg and obj_reg must be loaded up with the appropriate values.
 649   // swap_reg must be rax, and is killed.
 650   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
 651   // be killed; if not supplied, push/pop will be used internally to
 652   // allocate a temporary (inefficient, avoid if possible).
 653   // Optional slow case is for implementations (interpreter and C1) which branch to
 654   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 655   // Returns offset of first potentially-faulting instruction for null
 656   // check info (currently consumed only by C1). If
 657   // swap_reg_contains_mark is true then returns -1 as it is assumed
 658   // the calling code has already passed any potential faults.
 659   int biased_locking_enter(Register lock_reg, Register obj_reg,
 660                            Register swap_reg, Register tmp_reg,
 661                            bool swap_reg_contains_mark,
 662                            Label& done, Label* slow_case = NULL,
 663                            BiasedLockingCounters* counters = NULL);
 664   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 665 #ifdef COMPILER2
 666   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
 667   // See full desription in macroAssembler_x86.cpp.
 668   void fast_lock(Register obj, Register box, Register tmp,
 669                  Register scr, Register cx1, Register cx2,
 670                  BiasedLockingCounters* counters,
 671                  RTMLockingCounters* rtm_counters,
 672                  RTMLockingCounters* stack_rtm_counters,
 673                  Metadata* method_data,
 674                  bool use_rtm, bool profile_rtm);
 675   void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
 676 #if INCLUDE_RTM_OPT
 677   void rtm_counters_update(Register abort_status, Register rtm_counters);
 678   void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
 679   void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
 680                                    RTMLockingCounters* rtm_counters,
 681                                    Metadata* method_data);
 682   void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
 683                      RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
 684   void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
 685   void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
 686   void rtm_stack_locking(Register obj, Register tmp, Register scr,
 687                          Register retry_on_abort_count,
 688                          RTMLockingCounters* stack_rtm_counters,
 689                          Metadata* method_data, bool profile_rtm,
 690                          Label& DONE_LABEL, Label& IsInflated);
 691   void rtm_inflated_locking(Register obj, Register box, Register tmp,
 692                             Register scr, Register retry_on_busy_count,
 693                             Register retry_on_abort_count,
 694                             RTMLockingCounters* rtm_counters,
 695                             Metadata* method_data, bool profile_rtm,
 696                             Label& DONE_LABEL);
 697 #endif
 698 #endif
 699 
 700   Condition negate_condition(Condition cond);
 701 
 702   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
 703   // operands. In general the names are modified to avoid hiding the instruction in Assembler
 704   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
 705   // here in MacroAssembler. The major exception to this rule is call
 706 
 707   // Arithmetics
 708 
 709 
 710   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
 711   void addptr(Address dst, Register src);
 712 
 713   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
 714   void addptr(Register dst, int32_t src);
 715   void addptr(Register dst, Register src);
 716   void addptr(Register dst, RegisterOrConstant src) {
 717     if (src.is_constant()) addptr(dst, (int) src.as_constant());
 718     else                   addptr(dst,       src.as_register());
 719   }
 720 
 721   void andptr(Register dst, int32_t src);
 722   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
 723 
 724   void cmp8(AddressLiteral src1, int imm);
 725 
 726   // renamed to drag out the casting of address to int32_t/intptr_t
 727   void cmp32(Register src1, int32_t imm);
 728 
 729   void cmp32(AddressLiteral src1, int32_t imm);
 730   // compare reg - mem, or reg - &mem
 731   void cmp32(Register src1, AddressLiteral src2);
 732 
 733   void cmp32(Register src1, Address src2);
 734 
 735 #ifndef _LP64
 736   void cmpklass(Address dst, Metadata* obj);
 737   void cmpklass(Register dst, Metadata* obj);
 738   void cmpoop(Address dst, jobject obj);
 739   void cmpoop(Register dst, jobject obj);
 740 #endif // _LP64
 741 
 742   // NOTE src2 must be the lval. This is NOT an mem-mem compare
 743   void cmpptr(Address src1, AddressLiteral src2);
 744 
 745   void cmpptr(Register src1, AddressLiteral src2);
 746 
 747   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 748   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 749   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 750 
 751   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 752   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 753 
 754   // cmp64 to avoild hiding cmpq
 755   void cmp64(Register src1, AddressLiteral src);
 756 
 757   void cmpxchgptr(Register reg, Address adr);
 758 
 759   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
 760 
 761 
 762   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
 763   void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
 764 
 765 
 766   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
 767 
 768   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
 769 
 770   void shlptr(Register dst, int32_t shift);
 771   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
 772 
 773   void shrptr(Register dst, int32_t shift);
 774   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
 775 
 776   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
 777   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
 778 
 779   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 780 
 781   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 782   void subptr(Register dst, int32_t src);
 783   // Force generation of a 4 byte immediate value even if it fits into 8bit
 784   void subptr_imm32(Register dst, int32_t src);
 785   void subptr(Register dst, Register src);
 786   void subptr(Register dst, RegisterOrConstant src) {
 787     if (src.is_constant()) subptr(dst, (int) src.as_constant());
 788     else                   subptr(dst,       src.as_register());
 789   }
 790 
 791   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 792   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 793 
 794   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 795   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 796 
 797   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
 798 
 799 
 800 
 801   // Helper functions for statistics gathering.
 802   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
 803   void cond_inc32(Condition cond, AddressLiteral counter_addr);
 804   // Unconditional atomic increment.
 805   void atomic_incl(Address counter_addr);
 806   void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
 807 #ifdef _LP64
 808   void atomic_incq(Address counter_addr);
 809   void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
 810 #endif
 811   void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
 812   void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
 813 
 814   void lea(Register dst, AddressLiteral adr);
 815   void lea(Address dst, AddressLiteral adr);
 816   void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
 817 
 818   void leal32(Register dst, Address src) { leal(dst, src); }
 819 
 820   // Import other testl() methods from the parent class or else
 821   // they will be hidden by the following overriding declaration.
 822   using Assembler::testl;
 823   void testl(Register dst, AddressLiteral src);
 824 
 825   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 826   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 827   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 828   void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
 829 
 830   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
 831   void testptr(Register src1, Register src2);
 832 
 833   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 834   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 835 
 836   // Calls
 837 
 838   void call(Label& L, relocInfo::relocType rtype);
 839   void call(Register entry);
 840 
 841   // NOTE: this call tranfers to the effective address of entry NOT
 842   // the address contained by entry. This is because this is more natural
 843   // for jumps/calls.
 844   void call(AddressLiteral entry);
 845 
 846   // Emit the CompiledIC call idiom
 847   void ic_call(address entry);
 848 
 849   // Jumps
 850 
 851   // NOTE: these jumps tranfer to the effective address of dst NOT
 852   // the address contained by dst. This is because this is more natural
 853   // for jumps/calls.
 854   void jump(AddressLiteral dst);
 855   void jump_cc(Condition cc, AddressLiteral dst);
 856 
 857   // 32bit can do a case table jump in one instruction but we no longer allow the base
 858   // to be installed in the Address class. This jump will tranfers to the address
 859   // contained in the location described by entry (not the address of entry)
 860   void jump(ArrayAddress entry);
 861 
 862   // Floating
 863 
 864   void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
 865   void andpd(XMMRegister dst, AddressLiteral src);
 866 
 867   void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
 868   void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
 869   void andps(XMMRegister dst, AddressLiteral src);
 870 
 871   void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
 872   void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
 873   void comiss(XMMRegister dst, AddressLiteral src);
 874 
 875   void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
 876   void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
 877   void comisd(XMMRegister dst, AddressLiteral src);
 878 
 879   void fadd_s(Address src)        { Assembler::fadd_s(src); }
 880   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
 881 
 882   void fldcw(Address src) { Assembler::fldcw(src); }
 883   void fldcw(AddressLiteral src);
 884 
 885   void fld_s(int index)   { Assembler::fld_s(index); }
 886   void fld_s(Address src) { Assembler::fld_s(src); }
 887   void fld_s(AddressLiteral src);
 888 
 889   void fld_d(Address src) { Assembler::fld_d(src); }
 890   void fld_d(AddressLiteral src);
 891 
 892   void fld_x(Address src) { Assembler::fld_x(src); }
 893   void fld_x(AddressLiteral src);
 894 
 895   void fmul_s(Address src)        { Assembler::fmul_s(src); }
 896   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
 897 
 898   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
 899   void ldmxcsr(AddressLiteral src);
 900 
 901   // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
 902   // all corner cases and may result in NaN and require fallback to a
 903   // runtime call.
 904   void fast_pow();
 905   void fast_exp();
 906   void increase_precision();
 907   void restore_precision();
 908 
 909   // computes exp(x). Fallback to runtime call included.
 910   void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); }
 911   // computes pow(x,y). Fallback to runtime call included.
 912   void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); }
 913 
 914 private:
 915 
 916   // call runtime as a fallback for trig functions and pow/exp.
 917   void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
 918 
 919   // computes 2^(Ylog2X); Ylog2X in ST(0)
 920   void pow_exp_core_encoding();
 921 
 922   // computes pow(x,y) or exp(x). Fallback to runtime call included.
 923   void pow_or_exp(bool is_exp, int num_fpu_regs_in_use);
 924 
 925   // these are private because users should be doing movflt/movdbl
 926 
 927   void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
 928   void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
 929   void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
 930   void movss(XMMRegister dst, AddressLiteral src);
 931 
 932   void movlpd(XMMRegister dst, Address src)    {Assembler::movlpd(dst, src); }
 933   void movlpd(XMMRegister dst, AddressLiteral src);
 934 
 935 public:
 936 
 937   void addsd(XMMRegister dst, XMMRegister src)    { Assembler::addsd(dst, src); }
 938   void addsd(XMMRegister dst, Address src)        { Assembler::addsd(dst, src); }
 939   void addsd(XMMRegister dst, AddressLiteral src);
 940 
 941   void addss(XMMRegister dst, XMMRegister src)    { Assembler::addss(dst, src); }
 942   void addss(XMMRegister dst, Address src)        { Assembler::addss(dst, src); }
 943   void addss(XMMRegister dst, AddressLiteral src);
 944 
 945   void divsd(XMMRegister dst, XMMRegister src)    { Assembler::divsd(dst, src); }
 946   void divsd(XMMRegister dst, Address src)        { Assembler::divsd(dst, src); }
 947   void divsd(XMMRegister dst, AddressLiteral src);
 948 
 949   void divss(XMMRegister dst, XMMRegister src)    { Assembler::divss(dst, src); }
 950   void divss(XMMRegister dst, Address src)        { Assembler::divss(dst, src); }
 951   void divss(XMMRegister dst, AddressLiteral src);
 952 
 953   // Move Unaligned Double Quadword
 954   void movdqu(Address     dst, XMMRegister src)   { Assembler::movdqu(dst, src); }
 955   void movdqu(XMMRegister dst, Address src)       { Assembler::movdqu(dst, src); }
 956   void movdqu(XMMRegister dst, XMMRegister src)   { Assembler::movdqu(dst, src); }
 957   void movdqu(XMMRegister dst, AddressLiteral src);
 958 
 959   // Move Aligned Double Quadword
 960   void movdqa(XMMRegister dst, Address src)       { Assembler::movdqa(dst, src); }
 961   void movdqa(XMMRegister dst, XMMRegister src)   { Assembler::movdqa(dst, src); }
 962   void movdqa(XMMRegister dst, AddressLiteral src);
 963 
 964   void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
 965   void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
 966   void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
 967   void movsd(XMMRegister dst, AddressLiteral src);
 968 
 969   void mulsd(XMMRegister dst, XMMRegister src)    { Assembler::mulsd(dst, src); }
 970   void mulsd(XMMRegister dst, Address src)        { Assembler::mulsd(dst, src); }
 971   void mulsd(XMMRegister dst, AddressLiteral src);
 972 
 973   void mulss(XMMRegister dst, XMMRegister src)    { Assembler::mulss(dst, src); }
 974   void mulss(XMMRegister dst, Address src)        { Assembler::mulss(dst, src); }
 975   void mulss(XMMRegister dst, AddressLiteral src);
 976 
 977   // Carry-Less Multiplication Quadword
 978   void pclmulldq(XMMRegister dst, XMMRegister src) {
 979     // 0x00 - multiply lower 64 bits [0:63]
 980     Assembler::pclmulqdq(dst, src, 0x00);
 981   }
 982   void pclmulhdq(XMMRegister dst, XMMRegister src) {
 983     // 0x11 - multiply upper 64 bits [64:127]
 984     Assembler::pclmulqdq(dst, src, 0x11);
 985   }
 986 
 987   void sqrtsd(XMMRegister dst, XMMRegister src)    { Assembler::sqrtsd(dst, src); }
 988   void sqrtsd(XMMRegister dst, Address src)        { Assembler::sqrtsd(dst, src); }
 989   void sqrtsd(XMMRegister dst, AddressLiteral src);
 990 
 991   void sqrtss(XMMRegister dst, XMMRegister src)    { Assembler::sqrtss(dst, src); }
 992   void sqrtss(XMMRegister dst, Address src)        { Assembler::sqrtss(dst, src); }
 993   void sqrtss(XMMRegister dst, AddressLiteral src);
 994 
 995   void subsd(XMMRegister dst, XMMRegister src)    { Assembler::subsd(dst, src); }
 996   void subsd(XMMRegister dst, Address src)        { Assembler::subsd(dst, src); }
 997   void subsd(XMMRegister dst, AddressLiteral src);
 998 
 999   void subss(XMMRegister dst, XMMRegister src)    { Assembler::subss(dst, src); }
1000   void subss(XMMRegister dst, Address src)        { Assembler::subss(dst, src); }
1001   void subss(XMMRegister dst, AddressLiteral src);
1002 
1003   void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1004   void ucomiss(XMMRegister dst, Address src)     { Assembler::ucomiss(dst, src); }
1005   void ucomiss(XMMRegister dst, AddressLiteral src);
1006 
1007   void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1008   void ucomisd(XMMRegister dst, Address src)     { Assembler::ucomisd(dst, src); }
1009   void ucomisd(XMMRegister dst, AddressLiteral src);
1010 
1011   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1012   void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
1013   void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
1014   void xorpd(XMMRegister dst, AddressLiteral src);
1015 
1016   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1017   void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
1018   void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
1019   void xorps(XMMRegister dst, AddressLiteral src);
1020 
1021   // Shuffle Bytes
1022   void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1023   void pshufb(XMMRegister dst, Address src)     { Assembler::pshufb(dst, src); }
1024   void pshufb(XMMRegister dst, AddressLiteral src);
1025   // AVX 3-operands instructions
1026 
1027   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1028   void vaddsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddsd(dst, nds, src); }
1029   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1030 
1031   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1032   void vaddss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddss(dst, nds, src); }
1033   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1034 
1035   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
1036   void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256)     { Assembler::vandpd(dst, nds, src, vector256); }
1037   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
1038 
1039   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
1040   void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256)     { Assembler::vandps(dst, nds, src, vector256); }
1041   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
1042 
1043   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1044   void vdivsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivsd(dst, nds, src); }
1045   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1046 
1047   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1048   void vdivss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivss(dst, nds, src); }
1049   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1050 
1051   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1052   void vmulsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulsd(dst, nds, src); }
1053   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1054 
1055   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1056   void vmulss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulss(dst, nds, src); }
1057   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1058 
1059   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1060   void vsubsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubsd(dst, nds, src); }
1061   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1062 
1063   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1064   void vsubss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubss(dst, nds, src); }
1065   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1066 
1067   // AVX Vector instructions
1068 
1069   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
1070   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
1071   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
1072 
1073   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
1074   void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
1075   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
1076 
1077   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1078     if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
1079       Assembler::vpxor(dst, nds, src, vector256);
1080     else
1081       Assembler::vxorpd(dst, nds, src, vector256);
1082   }
1083   void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1084     if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
1085       Assembler::vpxor(dst, nds, src, vector256);
1086     else
1087       Assembler::vxorpd(dst, nds, src, vector256);
1088   }
1089 
1090   // Simple version for AVX2 256bit vectors
1091   void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1092   void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1093 
1094   // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector.
1095   void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1096     if (UseAVX > 1) // vinserti128h is available only in AVX2
1097       Assembler::vinserti128h(dst, nds, src);
1098     else
1099       Assembler::vinsertf128h(dst, nds, src);
1100   }
1101 
1102   // Carry-Less Multiplication Quadword
1103   void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1104     // 0x00 - multiply lower 64 bits [0:63]
1105     Assembler::vpclmulqdq(dst, nds, src, 0x00);
1106   }
1107   void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1108     // 0x11 - multiply upper 64 bits [64:127]
1109     Assembler::vpclmulqdq(dst, nds, src, 0x11);
1110   }
1111 
1112   // Data
1113 
1114   void cmov32( Condition cc, Register dst, Address  src);
1115   void cmov32( Condition cc, Register dst, Register src);
1116 
1117   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1118 
1119   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1120   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1121 
1122   void movoop(Register dst, jobject obj);
1123   void movoop(Address dst, jobject obj);
1124 
1125   void mov_metadata(Register dst, Metadata* obj);
1126   void mov_metadata(Address dst, Metadata* obj);
1127 
1128   void movptr(ArrayAddress dst, Register src);
1129   // can this do an lea?
1130   void movptr(Register dst, ArrayAddress src);
1131 
1132   void movptr(Register dst, Address src);
1133 
1134 #ifdef _LP64
1135   void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1136 #else
1137   void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1138 #endif
1139 
1140   void movptr(Register dst, intptr_t src);
1141   void movptr(Register dst, Register src);
1142   void movptr(Address dst, intptr_t src);
1143 
1144   void movptr(Address dst, Register src);
1145 
1146   void movptr(Register dst, RegisterOrConstant src) {
1147     if (src.is_constant()) movptr(dst, src.as_constant());
1148     else                   movptr(dst, src.as_register());
1149   }
1150 
1151 #ifdef _LP64
1152   // Generally the next two are only used for moving NULL
1153   // Although there are situations in initializing the mark word where
1154   // they could be used. They are dangerous.
1155 
1156   // They only exist on LP64 so that int32_t and intptr_t are not the same
1157   // and we have ambiguous declarations.
1158 
1159   void movptr(Address dst, int32_t imm32);
1160   void movptr(Register dst, int32_t imm32);
1161 #endif // _LP64
1162 
1163   // to avoid hiding movl
1164   void mov32(AddressLiteral dst, Register src);
1165   void mov32(Register dst, AddressLiteral src);
1166 
1167   // to avoid hiding movb
1168   void movbyte(ArrayAddress dst, int src);
1169 
1170   // Import other mov() methods from the parent class or else
1171   // they will be hidden by the following overriding declaration.
1172   using Assembler::movdl;
1173   using Assembler::movq;
1174   void movdl(XMMRegister dst, AddressLiteral src);
1175   void movq(XMMRegister dst, AddressLiteral src);
1176 
1177   // Can push value or effective address
1178   void pushptr(AddressLiteral src);
1179 
1180   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1181   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1182 
1183   void pushoop(jobject obj);
1184   void pushklass(Metadata* obj);
1185 
1186   // sign extend as need a l to ptr sized element
1187   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1188   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1189 
1190   // C2 compiled method's prolog code.
1191   void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1192 
1193   // clear memory of size 'cnt' qwords, starting at 'base'.
1194   void clear_mem(Register base, Register cnt, Register rtmp);
1195 
1196   // IndexOf strings.
1197   // Small strings are loaded through stack if they cross page boundary.
1198   void string_indexof(Register str1, Register str2,
1199                       Register cnt1, Register cnt2,
1200                       int int_cnt2,  Register result,
1201                       XMMRegister vec, Register tmp);
1202 
1203   // IndexOf for constant substrings with size >= 8 elements
1204   // which don't need to be loaded through stack.
1205   void string_indexofC8(Register str1, Register str2,
1206                       Register cnt1, Register cnt2,
1207                       int int_cnt2,  Register result,
1208                       XMMRegister vec, Register tmp);
1209 
1210     // Smallest code: we don't need to load through stack,
1211     // check string tail.
1212 
1213   // Compare strings.
1214   void string_compare(Register str1, Register str2,
1215                       Register cnt1, Register cnt2, Register result,
1216                       XMMRegister vec1);
1217 
1218   // Compare char[] arrays.
1219   void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1220                           Register limit, Register result, Register chr,
1221                           XMMRegister vec1, XMMRegister vec2);
1222 
1223   // Fill primitive arrays
1224   void generate_fill(BasicType t, bool aligned,
1225                      Register to, Register value, Register count,
1226                      Register rtmp, XMMRegister xtmp);
1227 
1228   void encode_iso_array(Register src, Register dst, Register len,
1229                         XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1230                         XMMRegister tmp4, Register tmp5, Register result);
1231 
1232 #ifdef _LP64
1233   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1234   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1235                              Register y, Register y_idx, Register z,
1236                              Register carry, Register product,
1237                              Register idx, Register kdx);
1238   void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1239                               Register yz_idx, Register idx,
1240                               Register carry, Register product, int offset);
1241   void multiply_128_x_128_bmi2_loop(Register y, Register z,
1242                                     Register carry, Register carry2,
1243                                     Register idx, Register jdx,
1244                                     Register yz_idx1, Register yz_idx2,
1245                                     Register tmp, Register tmp3, Register tmp4);
1246   void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1247                                Register yz_idx, Register idx, Register jdx,
1248                                Register carry, Register product,
1249                                Register carry2);
1250   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1251                        Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1252 
1253   void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1254                      Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1255   void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1256                             Register tmp2);
1257   void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1258                        Register rdxReg, Register raxReg);
1259   void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1260   void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1261                        Register tmp3, Register tmp4);
1262   void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1263                      Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1264 
1265   void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1266                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1267                Register raxReg);
1268   void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1269                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1270                Register raxReg);
1271 #endif
1272 
1273   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1274   void update_byte_crc32(Register crc, Register val, Register table);
1275   void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1276   // Fold 128-bit data chunk
1277   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1278   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1279   // Fold 8-bit data
1280   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1281   void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1282 
1283 #undef VIRTUAL
1284 
1285   void save_vector_registers();
1286   void restore_vector_registers();
1287 };
1288 
1289 /**
1290  * class SkipIfEqual:
1291  *
1292  * Instantiating this class will result in assembly code being output that will
1293  * jump around any code emitted between the creation of the instance and it's
1294  * automatic destruction at the end of a scope block, depending on the value of
1295  * the flag passed to the constructor, which will be checked at run-time.
1296  */
1297 class SkipIfEqual {
1298  private:
1299   MacroAssembler* _masm;
1300   Label _label;
1301 
1302  public:
1303    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1304    ~SkipIfEqual();
1305 };
1306 
1307 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP