< prev index next >

src/cpu/x86/vm/x86_32.ad

Print this page




 212 // Dynamic register class that selects between nadx_reg and nadx_reg_no_ebp.
 213 reg_class_dynamic nadx_reg(nadx_reg_no_ebp, nadx_reg_with_ebp, %{ PreserveFramePointer %});
 214 
 215 // Floating point registers.  Notice FPR0 is not a choice.
 216 // FPR0 is not ever allocated; we use clever encodings to fake
 217 // a 2-address instructions out of Intels FP stack.
 218 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
 219 
 220 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
 221                       FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
 222                       FPR7L,FPR7H );
 223 
 224 reg_class fp_flt_reg0( FPR1L );
 225 reg_class fp_dbl_reg0( FPR1L,FPR1H );
 226 reg_class fp_dbl_reg1( FPR2L,FPR2H );
 227 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
 228                           FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
 229 
 230 %}
 231 





 232 
 233 //----------SOURCE BLOCK-------------------------------------------------------
 234 // This is a block of C++ code which provides values, functions, and
 235 // definitions necessary in the rest of the architecture description
 236 source_hpp %{
 237 // Must be visible to the DFA in dfa_x86_32.cpp
 238 extern bool is_operand_hi32_zero(Node* n);
 239 %}
 240 
 241 source %{
 242 #define   RELOC_IMM32    Assembler::imm_operand
 243 #define   RELOC_DISP32   Assembler::disp32_operand
 244 
 245 #define __ _masm.
 246 
 247 // How to find the high register of a Long pair, given the low register
 248 #define   HIGH_FROM_LOW(x) ((x)+2)
 249 
 250 // These masks are used to provide 128-bit aligned bitmasks to the XMM
 251 // instructions, to allow sign-masking or sign-bit flipping.  They allow


7282   ins_pipe( pipe_cmpxchg );
7283 %}
7284 
7285 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7286 
7287 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7288   predicate(VM_Version::supports_cx8());
7289   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7290   effect(KILL cr, KILL oldval);
7291   format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7292             "MOV    $res,0\n\t"
7293             "JNE,s  fail\n\t"
7294             "MOV    $res,1\n"
7295           "fail:" %}
7296   ins_encode( enc_cmpxchg8(mem_ptr),
7297               enc_flags_ne_to_boolean(res) );
7298   ins_pipe( pipe_cmpxchg );
7299 %}
7300 
7301 instruct compareAndSwapP( rRegI res,  pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{

7302   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7303   effect(KILL cr, KILL oldval);
7304   format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7305             "MOV    $res,0\n\t"
7306             "JNE,s  fail\n\t"
7307             "MOV    $res,1\n"
7308           "fail:" %}
7309   ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );






















7310   ins_pipe( pipe_cmpxchg );
7311 %}
7312 
7313 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7314   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7315   effect(KILL cr, KILL oldval);
7316   format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7317             "MOV    $res,0\n\t"
7318             "JNE,s  fail\n\t"
7319             "MOV    $res,1\n"
7320           "fail:" %}
7321   ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7322   ins_pipe( pipe_cmpxchg );
7323 %}
7324 
7325 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7326   predicate(n->as_LoadStore()->result_not_used());
7327   match(Set dummy (GetAndAddI mem add));
7328   effect(KILL cr);
7329   format %{ "ADDL  [$mem],$add" %}




 212 // Dynamic register class that selects between nadx_reg and nadx_reg_no_ebp.
 213 reg_class_dynamic nadx_reg(nadx_reg_no_ebp, nadx_reg_with_ebp, %{ PreserveFramePointer %});
 214 
 215 // Floating point registers.  Notice FPR0 is not a choice.
 216 // FPR0 is not ever allocated; we use clever encodings to fake
 217 // a 2-address instructions out of Intels FP stack.
 218 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
 219 
 220 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
 221                       FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
 222                       FPR7L,FPR7H );
 223 
 224 reg_class fp_flt_reg0( FPR1L );
 225 reg_class fp_dbl_reg0( FPR1L,FPR1H );
 226 reg_class fp_dbl_reg1( FPR2L,FPR2H );
 227 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
 228                           FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
 229 
 230 %}
 231 
 232 source_hpp %{
 233 #if INCLUDE_ALL_GCS
 234 #include "shenandoahBarrierSetAssembler_x86.hpp"
 235 #endif
 236 %}
 237 
 238 //----------SOURCE BLOCK-------------------------------------------------------
 239 // This is a block of C++ code which provides values, functions, and
 240 // definitions necessary in the rest of the architecture description
 241 source_hpp %{
 242 // Must be visible to the DFA in dfa_x86_32.cpp
 243 extern bool is_operand_hi32_zero(Node* n);
 244 %}
 245 
 246 source %{
 247 #define   RELOC_IMM32    Assembler::imm_operand
 248 #define   RELOC_DISP32   Assembler::disp32_operand
 249 
 250 #define __ _masm.
 251 
 252 // How to find the high register of a Long pair, given the low register
 253 #define   HIGH_FROM_LOW(x) ((x)+2)
 254 
 255 // These masks are used to provide 128-bit aligned bitmasks to the XMM
 256 // instructions, to allow sign-masking or sign-bit flipping.  They allow


7287   ins_pipe( pipe_cmpxchg );
7288 %}
7289 
7290 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7291 
7292 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7293   predicate(VM_Version::supports_cx8());
7294   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7295   effect(KILL cr, KILL oldval);
7296   format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7297             "MOV    $res,0\n\t"
7298             "JNE,s  fail\n\t"
7299             "MOV    $res,1\n"
7300           "fail:" %}
7301   ins_encode( enc_cmpxchg8(mem_ptr),
7302               enc_flags_ne_to_boolean(res) );
7303   ins_pipe( pipe_cmpxchg );
7304 %}
7305 
7306 instruct compareAndSwapP( rRegI res,  pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7307   predicate(!UseShenandoahGC || !ShenandoahCASBarrier || n->in(3)->in(1)->bottom_type() == TypePtr::NULL_PTR);
7308   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7309   effect(KILL cr, KILL oldval);
7310   format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7311             "MOV    $res,0\n\t"
7312             "JNE,s  fail\n\t"
7313             "MOV    $res,1\n"
7314           "fail:" %}
7315   ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7316   ins_pipe( pipe_cmpxchg );
7317 %}
7318 
7319 instruct compareAndSwapP_shenandoah(rRegI res,
7320                                     memory mem_ptr,
7321                                     eRegP tmp1, eRegP tmp2,
7322                                     eAXRegP oldval, eCXRegP newval,
7323                                     eFlagsReg cr)
7324 %{
7325   predicate(UseShenandoahGC && ShenandoahCASBarrier && n->in(3)->in(1)->bottom_type() != TypePtr::NULL_PTR);
7326   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7327   effect(TEMP tmp1, TEMP tmp2, KILL cr, KILL oldval);
7328 
7329   format %{ "shenandoah_cas_oop $mem_ptr,$newval" %}
7330 
7331   ins_encode %{
7332     ShenandoahBarrierSetAssembler::bsasm()->cmpxchg_oop(&_masm,
7333       $res$$Register, $mem_ptr$$Address, $oldval$$Register, $newval$$Register,
7334       false, // swap
7335       $tmp1$$Register, $tmp2$$Register
7336     );
7337   %}
7338   ins_pipe( pipe_cmpxchg );
7339 %}
7340 
7341 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7342   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7343   effect(KILL cr, KILL oldval);
7344   format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7345             "MOV    $res,0\n\t"
7346             "JNE,s  fail\n\t"
7347             "MOV    $res,1\n"
7348           "fail:" %}
7349   ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7350   ins_pipe( pipe_cmpxchg );
7351 %}
7352 
7353 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7354   predicate(n->as_LoadStore()->result_not_used());
7355   match(Set dummy (GetAndAddI mem add));
7356   effect(KILL cr);
7357   format %{ "ADDL  [$mem],$add" %}


< prev index next >