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src/share/vm/c1/c1_LIR.cpp

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*** 65,75 **** return FrameMap::nr2floatreg(fpu_regnrHi()); } #endif ! #ifdef ARM FloatRegister LIR_OprDesc::as_float_reg() const { return as_FloatRegister(fpu_regnr()); } --- 65,75 ---- return FrameMap::nr2floatreg(fpu_regnrHi()); } #endif ! #if defined(ARM) || defined (TARGET_ARCH_aarch64) FloatRegister LIR_OprDesc::as_float_reg() const { return as_FloatRegister(fpu_regnr()); }
*** 147,157 **** --- 147,161 ---- assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); assert(disp() == 0 || index()->is_illegal(), "can't have both"); #endif #ifdef _LP64 assert(base()->is_cpu_register(), "wrong base operand"); + #ifndef TARGET_ARCH_aarch64 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); + #else + assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand"); + #endif assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, "wrong type for addresses"); #else assert(base()->is_single_cpu(), "wrong base operand"); assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
*** 554,564 **** LIR_OpConvert* opConvert = (LIR_OpConvert*)op; assert(opConvert->_info == NULL, "must be"); if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); if (opConvert->_result->is_valid()) do_output(opConvert->_result); ! #ifdef PPC if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); #endif do_stub(opConvert->_stub); --- 558,568 ---- LIR_OpConvert* opConvert = (LIR_OpConvert*)op; assert(opConvert->_info == NULL, "must be"); if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); if (opConvert->_result->is_valid()) do_output(opConvert->_result); ! #if defined(PPC) || defined(TARGET_ARCH_aarch64) if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); #endif do_stub(opConvert->_stub);
*** 1572,1582 **** } else if (is_single_cpu()) { out->print("%s", as_register()->name()); } else if (is_double_cpu()) { out->print("%s", as_register_hi()->name()); out->print("%s", as_register_lo()->name()); ! #if defined(X86) } else if (is_single_xmm()) { out->print("%s", as_xmm_float_reg()->name()); } else if (is_double_xmm()) { out->print("%s", as_xmm_double_reg()->name()); } else if (is_single_fpu()) { --- 1576,1591 ---- } else if (is_single_cpu()) { out->print("%s", as_register()->name()); } else if (is_double_cpu()) { out->print("%s", as_register_hi()->name()); out->print("%s", as_register_lo()->name()); ! #if defined(AARCH64) ! } else if (is_single_fpu()) { ! out->print("fpu%d", fpu_regnr()); ! } else if (is_double_fpu()) { ! out->print("fpu%d", fpu_regnrLo()); ! #elif defined(X86) } else if (is_single_xmm()) { out->print("%s", as_xmm_float_reg()->name()); } else if (is_double_xmm()) { out->print("%s", as_xmm_double_reg()->name()); } else if (is_single_fpu()) {
*** 1969,1979 **** // LIR_OpConvert void LIR_OpConvert::print_instr(outputStream* out) const { print_bytecode(out, bytecode()); in_opr()->print(out); out->print(" "); result_opr()->print(out); out->print(" "); ! #ifdef PPC if(tmp1()->is_valid()) { tmp1()->print(out); out->print(" "); tmp2()->print(out); out->print(" "); } #endif --- 1978,1988 ---- // LIR_OpConvert void LIR_OpConvert::print_instr(outputStream* out) const { print_bytecode(out, bytecode()); in_opr()->print(out); out->print(" "); result_opr()->print(out); out->print(" "); ! #if defined(PPC) || defined(TARGET_ARCH_aarch64) if(tmp1()->is_valid()) { tmp1()->print(out); out->print(" "); tmp2()->print(out); out->print(" "); } #endif
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