< prev index next >

src/share/vm/c1/c1_LIR.hpp

Print this page

        

*** 444,460 **** } #endif return as_register(); } ! #ifdef X86 XMMRegister as_xmm_float_reg() const; XMMRegister as_xmm_double_reg() const; // for compatibility with RInfo int fpu () const { return lo_reg_half(); } ! #endif // X86 ! #if defined(SPARC) || defined(ARM) || defined(PPC) FloatRegister as_float_reg () const; FloatRegister as_double_reg () const; #endif jint as_jint() const { return as_constant_ptr()->as_jint(); } --- 444,460 ---- } #endif return as_register(); } ! #if defined(X86) XMMRegister as_xmm_float_reg() const; XMMRegister as_xmm_double_reg() const; // for compatibility with RInfo int fpu () const { return lo_reg_half(); } ! #endif ! #if defined(SPARC) || defined(ARM) || defined(PPC) || defined(AARCH64) FloatRegister as_float_reg () const; FloatRegister as_double_reg () const; #endif jint as_jint() const { return as_constant_ptr()->as_jint(); }
*** 540,550 **** , _index(LIR_OprDesc::illegalOpr()) , _scale(times_1) , _type(type) , _disp(0) { verify(); } ! #if defined(X86) || defined(ARM) LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type): _base(base) , _index(index) , _scale(scale) , _type(type) --- 540,550 ---- , _index(LIR_OprDesc::illegalOpr()) , _scale(times_1) , _type(type) , _disp(0) { verify(); } ! #if defined(X86) || defined(ARM) || defined(AARCH64) LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type): _base(base) , _index(index) , _scale(scale) , _type(type)
*** 623,633 **** static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); } ! #elif defined(X86) static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | (reg << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); } --- 623,633 ---- static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); } ! #elif defined(X86) || defined(AARCH64) static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) | (reg << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); }
*** 1472,1482 **** friend class LIR_OpVisitState; private: Bytecodes::Code _bytecode; ConversionStub* _stub; ! #ifdef PPC LIR_Opr _tmp1; LIR_Opr _tmp2; #endif public: --- 1472,1482 ---- friend class LIR_OpVisitState; private: Bytecodes::Code _bytecode; ConversionStub* _stub; ! #if defined(PPC) || defined(TARGET_ARCH_aarch64) LIR_Opr _tmp1; LIR_Opr _tmp2; #endif public:
*** 1487,1497 **** , _tmp1(LIR_OprDesc::illegalOpr()) , _tmp2(LIR_OprDesc::illegalOpr()) #endif , _bytecode(code) {} ! #ifdef PPC LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub ,LIR_Opr tmp1, LIR_Opr tmp2) : LIR_Op1(lir_convert, opr, result) , _stub(stub) , _tmp1(tmp1) --- 1487,1497 ---- , _tmp1(LIR_OprDesc::illegalOpr()) , _tmp2(LIR_OprDesc::illegalOpr()) #endif , _bytecode(code) {} ! #if defined(PPC) || defined(TARGET_ARCH_aarch64) LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub ,LIR_Opr tmp1, LIR_Opr tmp2) : LIR_Op1(lir_convert, opr, result) , _stub(stub) , _tmp1(tmp1)
*** 1499,1509 **** , _bytecode(code) {} #endif Bytecodes::Code bytecode() const { return _bytecode; } ConversionStub* stub() const { return _stub; } ! #ifdef PPC LIR_Opr tmp1() const { return _tmp1; } LIR_Opr tmp2() const { return _tmp2; } #endif virtual void emit_code(LIR_Assembler* masm); --- 1499,1509 ---- , _bytecode(code) {} #endif Bytecodes::Code bytecode() const { return _bytecode; } ConversionStub* stub() const { return _stub; } ! #if defined(PPC) || defined(TARGET_ARCH_aarch64) LIR_Opr tmp1() const { return _tmp1; } LIR_Opr tmp2() const { return _tmp2; } #endif virtual void emit_code(LIR_Assembler* masm);
*** 2142,2152 **** --- 2142,2159 ---- void safepoint(LIR_Opr tmp, CodeEmitInfo* info) { append(new LIR_Op1(lir_safepoint, tmp, info)); } #ifdef PPC void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_OpConvert(code, left, dst, NULL, tmp1, tmp2)); } #endif + #if defined (TARGET_ARCH_aarch64) + void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, + ConversionStub* stub = NULL, LIR_Opr tmp1 = LIR_OprDesc::illegalOpr()) { + append(new LIR_OpConvert(code, left, dst, stub, tmp1, LIR_OprDesc::illegalOpr())); + } + #else void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); } + #endif void logical_and (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_and, left, right, dst)); } void logical_or (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_or, left, right, dst)); } void logical_xor (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_xor, left, right, dst)); }
< prev index next >