src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp

*** 41,50 ****
--- 41,53 ----
  #include "oops/objArrayKlass.hpp"
  #include "runtime/sharedRuntime.hpp"
  #include "vmreg_aarch64.inline.hpp"
  
  
+ #if INCLUDE_ALL_GCS
+ #include "shenandoahBarrierSetAssembler_aarch64.hpp"
+ #endif
  
  #ifndef PRODUCT
  #define COMMENT(x)   do { __ block_comment(x); } while (0)
  #else
  #define COMMENT(x)
*** 1610,1642 ****
    __ cset(rscratch1, Assembler::NE);
    __ membar(__ AnyAny);
  }
  
  
  void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
    assert(VM_Version::supports_cx8(), "wrong machine");
    Register addr = as_reg(op->addr());
    Register newval = as_reg(op->new_value());
    Register cmpval = as_reg(op->cmp_value());
    Label succeed, fail, around;
  
    if (op->code() == lir_cas_obj) {
      if (UseCompressedOops) {
!       Register t1 = op->tmp1()->as_register();
!       assert(op->tmp1()->is_valid(), "must be");
!       __ encode_heap_oop(t1, cmpval);
!       cmpval = t1;
!       __ encode_heap_oop(rscratch2, newval);
!       newval = rscratch2;
!       casw(addr, newval, cmpval);
      } else {
!       casl(addr, newval, cmpval);
      }
    } else if (op->code() == lir_cas_int) {
      casw(addr, newval, cmpval);
    } else {
      casl(addr, newval, cmpval);
    }
  }
  
  
  void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
--- 1613,1671 ----
    __ cset(rscratch1, Assembler::NE);
    __ membar(__ AnyAny);
  }
  
  
+ // Return 1 in rscratch1 if the CAS fails.
  void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
    assert(VM_Version::supports_cx8(), "wrong machine");
    Register addr = as_reg(op->addr());
    Register newval = as_reg(op->new_value());
    Register cmpval = as_reg(op->cmp_value());
    Label succeed, fail, around;
+   Register res = op->result_opr()->as_register();
  
    if (op->code() == lir_cas_obj) {
+     assert(op->tmp1()->is_valid(), "must be");
+     Register t1 = op->tmp1()->as_register();
      if (UseCompressedOops) {
! #if INCLUDE_ALL_GCS
!       if (UseShenandoahGC && ShenandoahCASBarrier) {
!         __ encode_heap_oop(t1, cmpval);
!         cmpval = t1;
!         assert(op->tmp2()->is_valid(), "must be");
!         Register t2 = op->tmp2()->as_register();
!         __ encode_heap_oop(t2, newval);
!         newval = t2;
!         ShenandoahBarrierSetAssembler::bsasm()->cmpxchg_oop(_masm, addr, cmpval, newval, /*acquire*/ false, /*release*/ true, /*weak*/ false, /*is_cae*/ false, res);
!       } else
! #endif
!       {
!         __ encode_heap_oop(t1, cmpval);
!         cmpval = t1;
!         __ encode_heap_oop(rscratch2, newval);
!         newval = rscratch2;
!         casw(addr, newval, cmpval);
!         __ eorw (res, r8, 1);
!       }
      } else {
! #if INCLUDE_ALL_GCS
!       if (UseShenandoahGC && ShenandoahCASBarrier) {
!         ShenandoahBarrierSetAssembler::bsasm()->cmpxchg_oop(_masm, addr, cmpval, newval, /*acquire*/ false, /*release*/ true, /*weak*/ false, /*is_cae*/ false, res);
!       } else
! #endif
!       {
!         casl(addr, newval, cmpval);
!         __ eorw (res, r8, 1);
!       }
      }
    } else if (op->code() == lir_cas_int) {
      casw(addr, newval, cmpval);
+     __ eorw (res, r8, 1);
    } else {
      casl(addr, newval, cmpval);
+     __ eorw (res, r8, 1);
    }
  }
  
  
  void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
*** 2877,2887 ****
      __ fnegd(dest->as_double_reg(), left->as_double_reg());
    }
  }
  
  
! void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
    __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
  }
  
  
  void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
--- 2906,2923 ----
      __ fnegd(dest->as_double_reg(), left->as_double_reg());
    }
  }
  
  
! void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
! #if INCLUDE_ALL_GCS
!   if (UseShenandoahGC && patch_code != lir_patch_none) {
!     deoptimize_trap(info);
!     return;
!   }
! #endif
! 
    __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
  }
  
  
  void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {