src/cpu/aarch64/vm/templateTable_aarch64.cpp

@@ -36,10 +36,13 @@
 #include "oops/oop.inline.hpp"
 #include "prims/methodHandles.hpp"
 #include "runtime/sharedRuntime.hpp"
 #include "runtime/stubRoutines.hpp"
 #include "runtime/synchronizer.hpp"
+#if INCLUDE_ALL_GCS
+#include "shenandoahBarrierSetAssembler_aarch64.hpp"
+#endif
 
 #ifndef CC_INTERP
 
 #define __ _masm->
 

@@ -184,10 +187,39 @@
                                    r1 /* tmp2 */);
         }
 
       }
       break;
+    case BarrierSet::ShenandoahBarrierSet:
+      {
+        // flatten object address if needed
+        if (obj.index() == noreg && obj.offset() == 0) {
+          if (obj.base() != r3) {
+            __ mov(r3, obj.base());
+          }
+        } else {
+          __ lea(r3, obj);
+        }
+        if (ShenandoahSATBBarrier) {
+          __ g1_write_barrier_pre(r3 /* obj */,
+                                  r1 /* pre_val */,
+                                  rthread /* thread */,
+                                  r10  /* tmp */,
+                                  val != noreg /* tosca_live */,
+                                  false /* expand_call */);
+        }
+        if (val == noreg) {
+          __ store_heap_oop_null(Address(r3, 0));
+        } else {
+          if (ShenandoahStoreValEnqueueBarrier) {
+            ShenandoahBarrierSetAssembler::bsasm()->storeval_barrier(_masm, val, r10);
+          }
+          __ store_heap_oop(Address(r3, 0), val);
+        }
+
+      }
+      break;
 #endif // INCLUDE_ALL_GCS
     case BarrierSet::CardTableModRef:
     case BarrierSet::CardTableExtension:
       {
         if (val == noreg) {