src/cpu/x86/vm/c1_LIRGenerator_x86.cpp

@@ -41,10 +41,14 @@
 #define __ gen()->lir(__FILE__, __LINE__)->
 #else
 #define __ gen()->lir()->
 #endif
 
+#if INCLUDE_ALL_GCS
+#include "gc_implementation/shenandoah/c1/shenandoahBarrierSetC1.hpp"
+#endif
+
 // Item will be loaded into a byte register; Intel only
 void LIRItem::load_byte_item() {
   load_item();
   LIR_Opr res = result();
 

@@ -784,12 +788,23 @@
     pre_barrier(addr, LIR_OprFact::illegalOpr /* pre_val */,
                 true /* do_load */, false /* patch */, NULL);
   }
 
   LIR_Opr ill = LIR_OprFact::illegalOpr;  // for convenience
-  if (type == objectType)
+  if (type == objectType) {
+#if INCLUDE_ALL_GCS
+    if (UseShenandoahGC && ShenandoahCASBarrier) {
+      LIR_Opr result = rlock_result(x);
+      __ cas_obj(addr, cmp.result(), val.result(), new_register(T_OBJECT), new_register(T_OBJECT), result);
+      // Shenandoah C1 barrier would do all result management itself, shortcut here.
+      return;
+    } else
+#endif
+    {
     __ cas_obj(addr, cmp.result(), val.result(), ill, ill);
+    }
+  }
   else if (type == intType)
     __ cas_int(addr, cmp.result(), val.result(), ill, ill);
   else if (type == longType)
     __ cas_long(addr, cmp.result(), val.result(), ill, ill);
   else {

@@ -1483,10 +1498,18 @@
       // Do the pre-write barrier, if any.
       pre_barrier(LIR_OprFact::address(addr), LIR_OprFact::illegalOpr /* pre_val */,
                   true /* do_load */, false /* patch */, NULL);
     }
     __ xchg(LIR_OprFact::address(addr), dst, dst, LIR_OprFact::illegalOpr);
+
+#if INCLUDE_ALL_GCS
+    if (UseShenandoahGC && is_obj) {
+      LIR_Opr tmp = ShenandoahBarrierSet::barrier_set()->bsc1()->load_reference_barrier(this, dst, LIR_OprFact::addressConst(0));
+      __ move(tmp, dst);
+    }
+#endif
+
     if (is_obj) {
       // Seems to be a precise address
       post_barrier(LIR_OprFact::address(addr), data);
     }
   }