1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc_interface/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/cardTableModRefBS.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "prims/methodHandles.hpp"
35 #include "runtime/biasedLocking.hpp"
36 #include "runtime/interfaceSupport.hpp"
37 #include "runtime/objectMonitor.hpp"
38 #include "runtime/os.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/stubRoutines.hpp"
41 #include "utilities/macros.hpp"
42 #if INCLUDE_ALL_GCS
43 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
44 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
45 #include "gc_implementation/g1/heapRegion.hpp"
46 #endif // INCLUDE_ALL_GCS
47
48 #ifdef PRODUCT
49 #define BLOCK_COMMENT(str) /* nothing */
50 #define STOP(error) stop(error)
51 #else
52 #define BLOCK_COMMENT(str) block_comment(str)
53 #define STOP(error) block_comment(error); stop(error)
54 #endif
55
56 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
57
58 PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC
59
60 #ifdef ASSERT
61 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
62 #endif
63
64 static Assembler::Condition reverse[] = {
65 Assembler::noOverflow /* overflow = 0x0 */ ,
66 Assembler::overflow /* noOverflow = 0x1 */ ,
67 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
68 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
69 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
70 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
71 Assembler::above /* belowEqual = 0x6 */ ,
72 Assembler::belowEqual /* above = 0x7 */ ,
73 Assembler::positive /* negative = 0x8 */ ,
74 Assembler::negative /* positive = 0x9 */ ,
75 Assembler::noParity /* parity = 0xa */ ,
76 Assembler::parity /* noParity = 0xb */ ,
77 Assembler::greaterEqual /* less = 0xc */ ,
78 Assembler::less /* greaterEqual = 0xd */ ,
79 Assembler::greater /* lessEqual = 0xe */ ,
80 Assembler::lessEqual /* greater = 0xf, */
81
82 };
83
84
85 // Implementation of MacroAssembler
86
87 // First all the versions that have distinct versions depending on 32/64 bit
88 // Unless the difference is trivial (1 line or so).
89
90 #ifndef _LP64
91
92 // 32bit versions
93
94 Address MacroAssembler::as_Address(AddressLiteral adr) {
95 return Address(adr.target(), adr.rspec());
96 }
97
98 Address MacroAssembler::as_Address(ArrayAddress adr) {
99 return Address::make_array(adr);
100 }
101
102 void MacroAssembler::call_VM_leaf_base(address entry_point,
103 int number_of_arguments) {
104 call(RuntimeAddress(entry_point));
105 increment(rsp, number_of_arguments * wordSize);
106 }
107
108 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
109 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
110 }
111
112 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
114 }
115
116 void MacroAssembler::cmpoop(Address src1, jobject obj) {
117 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
118 }
119
120 void MacroAssembler::cmpoop(Register src1, jobject obj) {
121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
122 }
123
124 void MacroAssembler::extend_sign(Register hi, Register lo) {
125 // According to Intel Doc. AP-526, "Integer Divide", p.18.
126 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
127 cdql();
128 } else {
129 movl(hi, lo);
130 sarl(hi, 31);
131 }
132 }
133
134 void MacroAssembler::jC2(Register tmp, Label& L) {
135 // set parity bit if FPU flag C2 is set (via rax)
136 save_rax(tmp);
137 fwait(); fnstsw_ax();
138 sahf();
139 restore_rax(tmp);
140 // branch
141 jcc(Assembler::parity, L);
142 }
143
144 void MacroAssembler::jnC2(Register tmp, Label& L) {
145 // set parity bit if FPU flag C2 is set (via rax)
146 save_rax(tmp);
147 fwait(); fnstsw_ax();
148 sahf();
149 restore_rax(tmp);
150 // branch
151 jcc(Assembler::noParity, L);
152 }
153
154 // 32bit can do a case table jump in one instruction but we no longer allow the base
155 // to be installed in the Address class
156 void MacroAssembler::jump(ArrayAddress entry) {
157 jmp(as_Address(entry));
158 }
159
160 // Note: y_lo will be destroyed
161 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
162 // Long compare for Java (semantics as described in JVM spec.)
163 Label high, low, done;
164
165 cmpl(x_hi, y_hi);
166 jcc(Assembler::less, low);
167 jcc(Assembler::greater, high);
168 // x_hi is the return register
169 xorl(x_hi, x_hi);
170 cmpl(x_lo, y_lo);
171 jcc(Assembler::below, low);
172 jcc(Assembler::equal, done);
173
174 bind(high);
175 xorl(x_hi, x_hi);
176 increment(x_hi);
177 jmp(done);
178
179 bind(low);
180 xorl(x_hi, x_hi);
181 decrementl(x_hi);
182
183 bind(done);
184 }
185
186 void MacroAssembler::lea(Register dst, AddressLiteral src) {
187 mov_literal32(dst, (int32_t)src.target(), src.rspec());
188 }
189
190 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
191 // leal(dst, as_Address(adr));
192 // see note in movl as to why we must use a move
193 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
194 }
195
196 void MacroAssembler::leave() {
197 mov(rsp, rbp);
198 pop(rbp);
199 }
200
201 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
202 // Multiplication of two Java long values stored on the stack
203 // as illustrated below. Result is in rdx:rax.
204 //
205 // rsp ---> [ ?? ] \ \
206 // .... | y_rsp_offset |
207 // [ y_lo ] / (in bytes) | x_rsp_offset
208 // [ y_hi ] | (in bytes)
209 // .... |
210 // [ x_lo ] /
211 // [ x_hi ]
212 // ....
213 //
214 // Basic idea: lo(result) = lo(x_lo * y_lo)
215 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
216 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
217 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
218 Label quick;
219 // load x_hi, y_hi and check if quick
220 // multiplication is possible
221 movl(rbx, x_hi);
222 movl(rcx, y_hi);
223 movl(rax, rbx);
224 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
225 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
226 // do full multiplication
227 // 1st step
228 mull(y_lo); // x_hi * y_lo
229 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
230 // 2nd step
231 movl(rax, x_lo);
232 mull(rcx); // x_lo * y_hi
233 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
234 // 3rd step
235 bind(quick); // note: rbx, = 0 if quick multiply!
236 movl(rax, x_lo);
237 mull(y_lo); // x_lo * y_lo
238 addl(rdx, rbx); // correct hi(x_lo * y_lo)
239 }
240
241 void MacroAssembler::lneg(Register hi, Register lo) {
242 negl(lo);
243 adcl(hi, 0);
244 negl(hi);
245 }
246
247 void MacroAssembler::lshl(Register hi, Register lo) {
248 // Java shift left long support (semantics as described in JVM spec., p.305)
249 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
250 // shift value is in rcx !
251 assert(hi != rcx, "must not use rcx");
252 assert(lo != rcx, "must not use rcx");
253 const Register s = rcx; // shift count
254 const int n = BitsPerWord;
255 Label L;
256 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
257 cmpl(s, n); // if (s < n)
258 jcc(Assembler::less, L); // else (s >= n)
259 movl(hi, lo); // x := x << n
260 xorl(lo, lo);
261 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
262 bind(L); // s (mod n) < n
263 shldl(hi, lo); // x := x << s
264 shll(lo);
265 }
266
267
268 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
269 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
270 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
271 assert(hi != rcx, "must not use rcx");
272 assert(lo != rcx, "must not use rcx");
273 const Register s = rcx; // shift count
274 const int n = BitsPerWord;
275 Label L;
276 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
277 cmpl(s, n); // if (s < n)
278 jcc(Assembler::less, L); // else (s >= n)
279 movl(lo, hi); // x := x >> n
280 if (sign_extension) sarl(hi, 31);
281 else xorl(hi, hi);
282 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
283 bind(L); // s (mod n) < n
284 shrdl(lo, hi); // x := x >> s
285 if (sign_extension) sarl(hi);
286 else shrl(hi);
287 }
288
289 void MacroAssembler::movoop(Register dst, jobject obj) {
290 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
291 }
292
293 void MacroAssembler::movoop(Address dst, jobject obj) {
294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
295 }
296
297 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
298 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
299 }
300
301 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
303 }
304
305 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
306 // scratch register is not used,
307 // it is defined to match parameters of 64-bit version of this method.
308 if (src.is_lval()) {
309 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
310 } else {
311 movl(dst, as_Address(src));
312 }
313 }
314
315 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
316 movl(as_Address(dst), src);
317 }
318
319 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
320 movl(dst, as_Address(src));
321 }
322
323 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
324 void MacroAssembler::movptr(Address dst, intptr_t src) {
325 movl(dst, src);
326 }
327
328
329 void MacroAssembler::pop_callee_saved_registers() {
330 pop(rcx);
331 pop(rdx);
332 pop(rdi);
333 pop(rsi);
334 }
335
336 void MacroAssembler::pop_fTOS() {
337 fld_d(Address(rsp, 0));
338 addl(rsp, 2 * wordSize);
339 }
340
341 void MacroAssembler::push_callee_saved_registers() {
342 push(rsi);
343 push(rdi);
344 push(rdx);
345 push(rcx);
346 }
347
348 void MacroAssembler::push_fTOS() {
349 subl(rsp, 2 * wordSize);
350 fstp_d(Address(rsp, 0));
351 }
352
353
354 void MacroAssembler::pushoop(jobject obj) {
355 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
356 }
357
358 void MacroAssembler::pushklass(Metadata* obj) {
359 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
360 }
361
362 void MacroAssembler::pushptr(AddressLiteral src) {
363 if (src.is_lval()) {
364 push_literal32((int32_t)src.target(), src.rspec());
365 } else {
366 pushl(as_Address(src));
367 }
368 }
369
370 void MacroAssembler::set_word_if_not_zero(Register dst) {
371 xorl(dst, dst);
372 set_byte_if_not_zero(dst);
373 }
374
375 static void pass_arg0(MacroAssembler* masm, Register arg) {
376 masm->push(arg);
377 }
378
379 static void pass_arg1(MacroAssembler* masm, Register arg) {
380 masm->push(arg);
381 }
382
383 static void pass_arg2(MacroAssembler* masm, Register arg) {
384 masm->push(arg);
385 }
386
387 static void pass_arg3(MacroAssembler* masm, Register arg) {
388 masm->push(arg);
389 }
390
391 #ifndef PRODUCT
392 extern "C" void findpc(intptr_t x);
393 #endif
394
395 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
396 // In order to get locks to work, we need to fake a in_VM state
397 JavaThread* thread = JavaThread::current();
398 JavaThreadState saved_state = thread->thread_state();
399 thread->set_thread_state(_thread_in_vm);
400 if (ShowMessageBoxOnError) {
401 JavaThread* thread = JavaThread::current();
402 JavaThreadState saved_state = thread->thread_state();
403 thread->set_thread_state(_thread_in_vm);
404 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
405 ttyLocker ttyl;
406 BytecodeCounter::print();
407 }
408 // To see where a verify_oop failed, get $ebx+40/X for this frame.
409 // This is the value of eip which points to where verify_oop will return.
410 if (os::message_box(msg, "Execution stopped, print registers?")) {
411 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
412 BREAKPOINT;
413 }
414 } else {
415 ttyLocker ttyl;
416 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
417 }
418 // Don't assert holding the ttyLock
419 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
420 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
421 }
422
423 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
424 ttyLocker ttyl;
425 FlagSetting fs(Debugging, true);
426 tty->print_cr("eip = 0x%08x", eip);
427 #ifndef PRODUCT
428 if ((WizardMode || Verbose) && PrintMiscellaneous) {
429 tty->cr();
430 findpc(eip);
431 tty->cr();
432 }
433 #endif
434 #define PRINT_REG(rax) \
435 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
436 PRINT_REG(rax);
437 PRINT_REG(rbx);
438 PRINT_REG(rcx);
439 PRINT_REG(rdx);
440 PRINT_REG(rdi);
441 PRINT_REG(rsi);
442 PRINT_REG(rbp);
443 PRINT_REG(rsp);
444 #undef PRINT_REG
445 // Print some words near top of staack.
446 int* dump_sp = (int*) rsp;
447 for (int col1 = 0; col1 < 8; col1++) {
448 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
449 os::print_location(tty, *dump_sp++);
450 }
451 for (int row = 0; row < 16; row++) {
452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
453 for (int col = 0; col < 8; col++) {
454 tty->print(" 0x%08x", *dump_sp++);
455 }
456 tty->cr();
457 }
458 // Print some instructions around pc:
459 Disassembler::decode((address)eip-64, (address)eip);
460 tty->print_cr("--------");
461 Disassembler::decode((address)eip, (address)eip+32);
462 }
463
464 void MacroAssembler::stop(const char* msg) {
465 ExternalAddress message((address)msg);
466 // push address of message
467 pushptr(message.addr());
468 { Label L; call(L, relocInfo::none); bind(L); } // push eip
469 pusha(); // push registers
470 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
471 hlt();
472 }
473
474 void MacroAssembler::warn(const char* msg) {
475 push_CPU_state();
476
477 ExternalAddress message((address) msg);
478 // push address of message
479 pushptr(message.addr());
480
481 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
482 addl(rsp, wordSize); // discard argument
483 pop_CPU_state();
484 }
485
486 void MacroAssembler::print_state() {
487 { Label L; call(L, relocInfo::none); bind(L); } // push eip
488 pusha(); // push registers
489
490 push_CPU_state();
491 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
492 pop_CPU_state();
493
494 popa();
495 addl(rsp, wordSize);
496 }
497
498 #else // _LP64
499
500 // 64 bit versions
501
502 Address MacroAssembler::as_Address(AddressLiteral adr) {
503 // amd64 always does this as a pc-rel
504 // we can be absolute or disp based on the instruction type
505 // jmp/call are displacements others are absolute
506 assert(!adr.is_lval(), "must be rval");
507 assert(reachable(adr), "must be");
508 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
509
510 }
511
512 Address MacroAssembler::as_Address(ArrayAddress adr) {
513 AddressLiteral base = adr.base();
514 lea(rscratch1, base);
515 Address index = adr.index();
516 assert(index._disp == 0, "must not have disp"); // maybe it can?
517 Address array(rscratch1, index._index, index._scale, index._disp);
518 return array;
519 }
520
521 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
522 Label L, E;
523
524 #ifdef _WIN64
525 // Windows always allocates space for it's register args
526 assert(num_args <= 4, "only register arguments supported");
527 subq(rsp, frame::arg_reg_save_area_bytes);
528 #endif
529
530 // Align stack if necessary
531 testl(rsp, 15);
532 jcc(Assembler::zero, L);
533
534 subq(rsp, 8);
535 {
536 call(RuntimeAddress(entry_point));
537 }
538 addq(rsp, 8);
539 jmp(E);
540
541 bind(L);
542 {
543 call(RuntimeAddress(entry_point));
544 }
545
546 bind(E);
547
548 #ifdef _WIN64
549 // restore stack pointer
550 addq(rsp, frame::arg_reg_save_area_bytes);
551 #endif
552
553 }
554
555 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
556 assert(!src2.is_lval(), "should use cmpptr");
557
558 if (reachable(src2)) {
559 cmpq(src1, as_Address(src2));
560 } else {
561 lea(rscratch1, src2);
562 Assembler::cmpq(src1, Address(rscratch1, 0));
563 }
564 }
565
566 int MacroAssembler::corrected_idivq(Register reg) {
567 // Full implementation of Java ldiv and lrem; checks for special
568 // case as described in JVM spec., p.243 & p.271. The function
569 // returns the (pc) offset of the idivl instruction - may be needed
570 // for implicit exceptions.
571 //
572 // normal case special case
573 //
574 // input : rax: dividend min_long
575 // reg: divisor (may not be eax/edx) -1
576 //
577 // output: rax: quotient (= rax idiv reg) min_long
578 // rdx: remainder (= rax irem reg) 0
579 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
580 static const int64_t min_long = 0x8000000000000000;
581 Label normal_case, special_case;
582
583 // check for special case
584 cmp64(rax, ExternalAddress((address) &min_long));
585 jcc(Assembler::notEqual, normal_case);
586 xorl(rdx, rdx); // prepare rdx for possible special case (where
587 // remainder = 0)
588 cmpq(reg, -1);
589 jcc(Assembler::equal, special_case);
590
591 // handle normal case
592 bind(normal_case);
593 cdqq();
594 int idivq_offset = offset();
595 idivq(reg);
596
597 // normal and special case exit
598 bind(special_case);
599
600 return idivq_offset;
601 }
602
603 void MacroAssembler::decrementq(Register reg, int value) {
604 if (value == min_jint) { subq(reg, value); return; }
605 if (value < 0) { incrementq(reg, -value); return; }
606 if (value == 0) { ; return; }
607 if (value == 1 && UseIncDec) { decq(reg) ; return; }
608 /* else */ { subq(reg, value) ; return; }
609 }
610
611 void MacroAssembler::decrementq(Address dst, int value) {
612 if (value == min_jint) { subq(dst, value); return; }
613 if (value < 0) { incrementq(dst, -value); return; }
614 if (value == 0) { ; return; }
615 if (value == 1 && UseIncDec) { decq(dst) ; return; }
616 /* else */ { subq(dst, value) ; return; }
617 }
618
619 void MacroAssembler::incrementq(AddressLiteral dst) {
620 if (reachable(dst)) {
621 incrementq(as_Address(dst));
622 } else {
623 lea(rscratch1, dst);
624 incrementq(Address(rscratch1, 0));
625 }
626 }
627
628 void MacroAssembler::incrementq(Register reg, int value) {
629 if (value == min_jint) { addq(reg, value); return; }
630 if (value < 0) { decrementq(reg, -value); return; }
631 if (value == 0) { ; return; }
632 if (value == 1 && UseIncDec) { incq(reg) ; return; }
633 /* else */ { addq(reg, value) ; return; }
634 }
635
636 void MacroAssembler::incrementq(Address dst, int value) {
637 if (value == min_jint) { addq(dst, value); return; }
638 if (value < 0) { decrementq(dst, -value); return; }
639 if (value == 0) { ; return; }
640 if (value == 1 && UseIncDec) { incq(dst) ; return; }
641 /* else */ { addq(dst, value) ; return; }
642 }
643
644 // 32bit can do a case table jump in one instruction but we no longer allow the base
645 // to be installed in the Address class
646 void MacroAssembler::jump(ArrayAddress entry) {
647 lea(rscratch1, entry.base());
648 Address dispatch = entry.index();
649 assert(dispatch._base == noreg, "must be");
650 dispatch._base = rscratch1;
651 jmp(dispatch);
652 }
653
654 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
655 ShouldNotReachHere(); // 64bit doesn't use two regs
656 cmpq(x_lo, y_lo);
657 }
658
659 void MacroAssembler::lea(Register dst, AddressLiteral src) {
660 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
661 }
662
663 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
664 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
665 movptr(dst, rscratch1);
666 }
667
668 void MacroAssembler::leave() {
669 // %%% is this really better? Why not on 32bit too?
670 emit_int8((unsigned char)0xC9); // LEAVE
671 }
672
673 void MacroAssembler::lneg(Register hi, Register lo) {
674 ShouldNotReachHere(); // 64bit doesn't use two regs
675 negq(lo);
676 }
677
678 void MacroAssembler::movoop(Register dst, jobject obj) {
679 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
680 }
681
682 void MacroAssembler::movoop(Address dst, jobject obj) {
683 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
684 movq(dst, rscratch1);
685 }
686
687 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
688 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
689 }
690
691 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
692 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
693 movq(dst, rscratch1);
694 }
695
696 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
697 if (src.is_lval()) {
698 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
699 } else {
700 if (reachable(src)) {
701 movq(dst, as_Address(src));
702 } else {
703 lea(scratch, src);
704 movq(dst, Address(scratch, 0));
705 }
706 }
707 }
708
709 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
710 movq(as_Address(dst), src);
711 }
712
713 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
714 movq(dst, as_Address(src));
715 }
716
717 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
718 void MacroAssembler::movptr(Address dst, intptr_t src) {
719 mov64(rscratch1, src);
720 movq(dst, rscratch1);
721 }
722
723 // These are mostly for initializing NULL
724 void MacroAssembler::movptr(Address dst, int32_t src) {
725 movslq(dst, src);
726 }
727
728 void MacroAssembler::movptr(Register dst, int32_t src) {
729 mov64(dst, (intptr_t)src);
730 }
731
732 void MacroAssembler::pushoop(jobject obj) {
733 movoop(rscratch1, obj);
734 push(rscratch1);
735 }
736
737 void MacroAssembler::pushklass(Metadata* obj) {
738 mov_metadata(rscratch1, obj);
739 push(rscratch1);
740 }
741
742 void MacroAssembler::pushptr(AddressLiteral src) {
743 lea(rscratch1, src);
744 if (src.is_lval()) {
745 push(rscratch1);
746 } else {
747 pushq(Address(rscratch1, 0));
748 }
749 }
750
751 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
752 // we must set sp to zero to clear frame
753 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
754 // must clear fp, so that compiled frames are not confused; it is
755 // possible that we need it only for debugging
756 if (clear_fp) {
757 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
758 }
759
760 // Always clear the pc because it could have been set by make_walkable()
761 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
762 }
763
764 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
765 Register last_java_fp,
766 address last_java_pc) {
767 // determine last_java_sp register
768 if (!last_java_sp->is_valid()) {
769 last_java_sp = rsp;
770 }
771
772 // last_java_fp is optional
773 if (last_java_fp->is_valid()) {
774 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
775 last_java_fp);
776 }
777
778 // last_java_pc is optional
779 if (last_java_pc != NULL) {
780 Address java_pc(r15_thread,
781 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
782 lea(rscratch1, InternalAddress(last_java_pc));
783 movptr(java_pc, rscratch1);
784 }
785
786 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
787 }
788
789 static void pass_arg0(MacroAssembler* masm, Register arg) {
790 if (c_rarg0 != arg ) {
791 masm->mov(c_rarg0, arg);
792 }
793 }
794
795 static void pass_arg1(MacroAssembler* masm, Register arg) {
796 if (c_rarg1 != arg ) {
797 masm->mov(c_rarg1, arg);
798 }
799 }
800
801 static void pass_arg2(MacroAssembler* masm, Register arg) {
802 if (c_rarg2 != arg ) {
803 masm->mov(c_rarg2, arg);
804 }
805 }
806
807 static void pass_arg3(MacroAssembler* masm, Register arg) {
808 if (c_rarg3 != arg ) {
809 masm->mov(c_rarg3, arg);
810 }
811 }
812
813 void MacroAssembler::stop(const char* msg) {
814 address rip = pc();
815 pusha(); // get regs on stack
816 lea(c_rarg0, ExternalAddress((address) msg));
817 lea(c_rarg1, InternalAddress(rip));
818 movq(c_rarg2, rsp); // pass pointer to regs array
819 andq(rsp, -16); // align stack as required by ABI
820 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
821 hlt();
822 }
823
824 void MacroAssembler::warn(const char* msg) {
825 push(rbp);
826 movq(rbp, rsp);
827 andq(rsp, -16); // align stack as required by push_CPU_state and call
828 push_CPU_state(); // keeps alignment at 16 bytes
829 lea(c_rarg0, ExternalAddress((address) msg));
830 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
831 pop_CPU_state();
832 mov(rsp, rbp);
833 pop(rbp);
834 }
835
836 void MacroAssembler::print_state() {
837 address rip = pc();
838 pusha(); // get regs on stack
839 push(rbp);
840 movq(rbp, rsp);
841 andq(rsp, -16); // align stack as required by push_CPU_state and call
842 push_CPU_state(); // keeps alignment at 16 bytes
843
844 lea(c_rarg0, InternalAddress(rip));
845 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
846 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
847
848 pop_CPU_state();
849 mov(rsp, rbp);
850 pop(rbp);
851 popa();
852 }
853
854 #ifndef PRODUCT
855 extern "C" void findpc(intptr_t x);
856 #endif
857
858 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
859 // In order to get locks to work, we need to fake a in_VM state
860 if (ShowMessageBoxOnError) {
861 JavaThread* thread = JavaThread::current();
862 JavaThreadState saved_state = thread->thread_state();
863 thread->set_thread_state(_thread_in_vm);
864 #ifndef PRODUCT
865 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
866 ttyLocker ttyl;
867 BytecodeCounter::print();
868 }
869 #endif
870 // To see where a verify_oop failed, get $ebx+40/X for this frame.
871 // XXX correct this offset for amd64
872 // This is the value of eip which points to where verify_oop will return.
873 if (os::message_box(msg, "Execution stopped, print registers?")) {
874 print_state64(pc, regs);
875 BREAKPOINT;
876 assert(false, "start up GDB");
877 }
878 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
879 } else {
880 ttyLocker ttyl;
881 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
882 msg);
883 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
884 }
885 }
886
887 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
888 ttyLocker ttyl;
889 FlagSetting fs(Debugging, true);
890 tty->print_cr("rip = 0x%016lx", pc);
891 #ifndef PRODUCT
892 tty->cr();
893 findpc(pc);
894 tty->cr();
895 #endif
896 #define PRINT_REG(rax, value) \
897 { tty->print("%s = ", #rax); os::print_location(tty, value); }
898 PRINT_REG(rax, regs[15]);
899 PRINT_REG(rbx, regs[12]);
900 PRINT_REG(rcx, regs[14]);
901 PRINT_REG(rdx, regs[13]);
902 PRINT_REG(rdi, regs[8]);
903 PRINT_REG(rsi, regs[9]);
904 PRINT_REG(rbp, regs[10]);
905 PRINT_REG(rsp, regs[11]);
906 PRINT_REG(r8 , regs[7]);
907 PRINT_REG(r9 , regs[6]);
908 PRINT_REG(r10, regs[5]);
909 PRINT_REG(r11, regs[4]);
910 PRINT_REG(r12, regs[3]);
911 PRINT_REG(r13, regs[2]);
912 PRINT_REG(r14, regs[1]);
913 PRINT_REG(r15, regs[0]);
914 #undef PRINT_REG
915 // Print some words near top of staack.
916 int64_t* rsp = (int64_t*) regs[11];
917 int64_t* dump_sp = rsp;
918 for (int col1 = 0; col1 < 8; col1++) {
919 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
920 os::print_location(tty, *dump_sp++);
921 }
922 for (int row = 0; row < 25; row++) {
923 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
924 for (int col = 0; col < 4; col++) {
925 tty->print(" 0x%016lx", *dump_sp++);
926 }
927 tty->cr();
928 }
929 // Print some instructions around pc:
930 Disassembler::decode((address)pc-64, (address)pc);
931 tty->print_cr("--------");
932 Disassembler::decode((address)pc, (address)pc+32);
933 }
934
935 #endif // _LP64
936
937 // Now versions that are common to 32/64 bit
938
939 void MacroAssembler::addptr(Register dst, int32_t imm32) {
940 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
941 }
942
943 void MacroAssembler::addptr(Register dst, Register src) {
944 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
945 }
946
947 void MacroAssembler::addptr(Address dst, Register src) {
948 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
949 }
950
951 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
952 if (reachable(src)) {
953 Assembler::addsd(dst, as_Address(src));
954 } else {
955 lea(rscratch1, src);
956 Assembler::addsd(dst, Address(rscratch1, 0));
957 }
958 }
959
960 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
961 if (reachable(src)) {
962 addss(dst, as_Address(src));
963 } else {
964 lea(rscratch1, src);
965 addss(dst, Address(rscratch1, 0));
966 }
967 }
968
969 void MacroAssembler::align(int modulus) {
970 if (offset() % modulus != 0) {
971 nop(modulus - (offset() % modulus));
972 }
973 }
974
975 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
976 // Used in sign-masking with aligned address.
977 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
978 if (reachable(src)) {
979 Assembler::andpd(dst, as_Address(src));
980 } else {
981 lea(rscratch1, src);
982 Assembler::andpd(dst, Address(rscratch1, 0));
983 }
984 }
985
986 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
987 // Used in sign-masking with aligned address.
988 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
989 if (reachable(src)) {
990 Assembler::andps(dst, as_Address(src));
991 } else {
992 lea(rscratch1, src);
993 Assembler::andps(dst, Address(rscratch1, 0));
994 }
995 }
996
997 void MacroAssembler::andptr(Register dst, int32_t imm32) {
998 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
999 }
1000
1001 void MacroAssembler::atomic_incl(Address counter_addr) {
1002 if (os::is_MP())
1003 lock();
1004 incrementl(counter_addr);
1005 }
1006
1007 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1008 if (reachable(counter_addr)) {
1009 atomic_incl(as_Address(counter_addr));
1010 } else {
1011 lea(scr, counter_addr);
1012 atomic_incl(Address(scr, 0));
1013 }
1014 }
1015
1016 #ifdef _LP64
1017 void MacroAssembler::atomic_incq(Address counter_addr) {
1018 if (os::is_MP())
1019 lock();
1020 incrementq(counter_addr);
1021 }
1022
1023 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1024 if (reachable(counter_addr)) {
1025 atomic_incq(as_Address(counter_addr));
1026 } else {
1027 lea(scr, counter_addr);
1028 atomic_incq(Address(scr, 0));
1029 }
1030 }
1031 #endif
1032
1033 // Writes to stack successive pages until offset reached to check for
1034 // stack overflow + shadow pages. This clobbers tmp.
1035 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1036 movptr(tmp, rsp);
1037 // Bang stack for total size given plus shadow page size.
1038 // Bang one page at a time because large size can bang beyond yellow and
1039 // red zones.
1040 Label loop;
1041 bind(loop);
1042 movl(Address(tmp, (-os::vm_page_size())), size );
1043 subptr(tmp, os::vm_page_size());
1044 subl(size, os::vm_page_size());
1045 jcc(Assembler::greater, loop);
1046
1047 // Bang down shadow pages too.
1048 // At this point, (tmp-0) is the last address touched, so don't
1049 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1050 // was post-decremented.) Skip this address by starting at i=1, and
1051 // touch a few more pages below. N.B. It is important to touch all
1052 // the way down to and including i=StackShadowPages.
1053 for (int i = 1; i < StackShadowPages; i++) {
1054 // this could be any sized move but this is can be a debugging crumb
1055 // so the bigger the better.
1056 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1057 }
1058 }
1059
1060 int MacroAssembler::biased_locking_enter(Register lock_reg,
1061 Register obj_reg,
1062 Register swap_reg,
1063 Register tmp_reg,
1064 bool swap_reg_contains_mark,
1065 Label& done,
1066 Label* slow_case,
1067 BiasedLockingCounters* counters) {
1068 assert(UseBiasedLocking, "why call this otherwise?");
1069 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1070 LP64_ONLY( assert(tmp_reg != noreg, "tmp_reg must be supplied"); )
1071 bool need_tmp_reg = false;
1072 if (tmp_reg == noreg) {
1073 need_tmp_reg = true;
1074 tmp_reg = lock_reg;
1075 assert_different_registers(lock_reg, obj_reg, swap_reg);
1076 } else {
1077 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1078 }
1079 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1080 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1081 Address saved_mark_addr(lock_reg, 0);
1082
1083 if (PrintBiasedLockingStatistics && counters == NULL) {
1084 counters = BiasedLocking::counters();
1085 }
1086 // Biased locking
1087 // See whether the lock is currently biased toward our thread and
1088 // whether the epoch is still valid
1089 // Note that the runtime guarantees sufficient alignment of JavaThread
1090 // pointers to allow age to be placed into low bits
1091 // First check to see whether biasing is even enabled for this object
1092 Label cas_label;
1093 int null_check_offset = -1;
1094 if (!swap_reg_contains_mark) {
1095 null_check_offset = offset();
1096 movptr(swap_reg, mark_addr);
1097 }
1098 if (need_tmp_reg) {
1099 push(tmp_reg);
1100 }
1101 movptr(tmp_reg, swap_reg);
1102 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1103 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1104 if (need_tmp_reg) {
1105 pop(tmp_reg);
1106 }
1107 jcc(Assembler::notEqual, cas_label);
1108 // The bias pattern is present in the object's header. Need to check
1109 // whether the bias owner and the epoch are both still current.
1110 #ifndef _LP64
1111 // Note that because there is no current thread register on x86_32 we
1112 // need to store off the mark word we read out of the object to
1113 // avoid reloading it and needing to recheck invariants below. This
1114 // store is unfortunate but it makes the overall code shorter and
1115 // simpler.
1116 movptr(saved_mark_addr, swap_reg);
1117 #endif
1118 if (need_tmp_reg) {
1119 push(tmp_reg);
1120 }
1121 if (swap_reg_contains_mark) {
1122 null_check_offset = offset();
1123 }
1124 load_prototype_header(tmp_reg, obj_reg);
1125 #ifdef _LP64
1126 orptr(tmp_reg, r15_thread);
1127 xorptr(tmp_reg, swap_reg);
1128 Register header_reg = tmp_reg;
1129 #else
1130 xorptr(tmp_reg, swap_reg);
1131 get_thread(swap_reg);
1132 xorptr(swap_reg, tmp_reg);
1133 Register header_reg = swap_reg;
1134 #endif
1135 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1136 if (need_tmp_reg) {
1137 pop(tmp_reg);
1138 }
1139 if (counters != NULL) {
1140 cond_inc32(Assembler::zero,
1141 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1142 }
1143 jcc(Assembler::equal, done);
1144
1145 Label try_revoke_bias;
1146 Label try_rebias;
1147
1148 // At this point we know that the header has the bias pattern and
1149 // that we are not the bias owner in the current epoch. We need to
1150 // figure out more details about the state of the header in order to
1151 // know what operations can be legally performed on the object's
1152 // header.
1153
1154 // If the low three bits in the xor result aren't clear, that means
1155 // the prototype header is no longer biased and we have to revoke
1156 // the bias on this object.
1157 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1158 jccb(Assembler::notZero, try_revoke_bias);
1159
1160 // Biasing is still enabled for this data type. See whether the
1161 // epoch of the current bias is still valid, meaning that the epoch
1162 // bits of the mark word are equal to the epoch bits of the
1163 // prototype header. (Note that the prototype header's epoch bits
1164 // only change at a safepoint.) If not, attempt to rebias the object
1165 // toward the current thread. Note that we must be absolutely sure
1166 // that the current epoch is invalid in order to do this because
1167 // otherwise the manipulations it performs on the mark word are
1168 // illegal.
1169 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1170 jccb(Assembler::notZero, try_rebias);
1171
1172 // The epoch of the current bias is still valid but we know nothing
1173 // about the owner; it might be set or it might be clear. Try to
1174 // acquire the bias of the object using an atomic operation. If this
1175 // fails we will go in to the runtime to revoke the object's bias.
1176 // Note that we first construct the presumed unbiased header so we
1177 // don't accidentally blow away another thread's valid bias.
1178 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1179 andptr(swap_reg,
1180 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1181 if (need_tmp_reg) {
1182 push(tmp_reg);
1183 }
1184 #ifdef _LP64
1185 movptr(tmp_reg, swap_reg);
1186 orptr(tmp_reg, r15_thread);
1187 #else
1188 get_thread(tmp_reg);
1189 orptr(tmp_reg, swap_reg);
1190 #endif
1191 if (os::is_MP()) {
1192 lock();
1193 }
1194 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1195 if (need_tmp_reg) {
1196 pop(tmp_reg);
1197 }
1198 // If the biasing toward our thread failed, this means that
1199 // another thread succeeded in biasing it toward itself and we
1200 // need to revoke that bias. The revocation will occur in the
1201 // interpreter runtime in the slow case.
1202 if (counters != NULL) {
1203 cond_inc32(Assembler::zero,
1204 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1205 }
1206 if (slow_case != NULL) {
1207 jcc(Assembler::notZero, *slow_case);
1208 }
1209 jmp(done);
1210
1211 bind(try_rebias);
1212 // At this point we know the epoch has expired, meaning that the
1213 // current "bias owner", if any, is actually invalid. Under these
1214 // circumstances _only_, we are allowed to use the current header's
1215 // value as the comparison value when doing the cas to acquire the
1216 // bias in the current epoch. In other words, we allow transfer of
1217 // the bias from one thread to another directly in this situation.
1218 //
1219 // FIXME: due to a lack of registers we currently blow away the age
1220 // bits in this situation. Should attempt to preserve them.
1221 if (need_tmp_reg) {
1222 push(tmp_reg);
1223 }
1224 load_prototype_header(tmp_reg, obj_reg);
1225 #ifdef _LP64
1226 orptr(tmp_reg, r15_thread);
1227 #else
1228 get_thread(swap_reg);
1229 orptr(tmp_reg, swap_reg);
1230 movptr(swap_reg, saved_mark_addr);
1231 #endif
1232 if (os::is_MP()) {
1233 lock();
1234 }
1235 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1236 if (need_tmp_reg) {
1237 pop(tmp_reg);
1238 }
1239 // If the biasing toward our thread failed, then another thread
1240 // succeeded in biasing it toward itself and we need to revoke that
1241 // bias. The revocation will occur in the runtime in the slow case.
1242 if (counters != NULL) {
1243 cond_inc32(Assembler::zero,
1244 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1245 }
1246 if (slow_case != NULL) {
1247 jcc(Assembler::notZero, *slow_case);
1248 }
1249 jmp(done);
1250
1251 bind(try_revoke_bias);
1252 // The prototype mark in the klass doesn't have the bias bit set any
1253 // more, indicating that objects of this data type are not supposed
1254 // to be biased any more. We are going to try to reset the mark of
1255 // this object to the prototype value and fall through to the
1256 // CAS-based locking scheme. Note that if our CAS fails, it means
1257 // that another thread raced us for the privilege of revoking the
1258 // bias of this particular object, so it's okay to continue in the
1259 // normal locking code.
1260 //
1261 // FIXME: due to a lack of registers we currently blow away the age
1262 // bits in this situation. Should attempt to preserve them.
1263 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1264 if (need_tmp_reg) {
1265 push(tmp_reg);
1266 }
1267 load_prototype_header(tmp_reg, obj_reg);
1268 if (os::is_MP()) {
1269 lock();
1270 }
1271 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1272 if (need_tmp_reg) {
1273 pop(tmp_reg);
1274 }
1275 // Fall through to the normal CAS-based lock, because no matter what
1276 // the result of the above CAS, some thread must have succeeded in
1277 // removing the bias bit from the object's header.
1278 if (counters != NULL) {
1279 cond_inc32(Assembler::zero,
1280 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1281 }
1282
1283 bind(cas_label);
1284
1285 return null_check_offset;
1286 }
1287
1288 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1289 assert(UseBiasedLocking, "why call this otherwise?");
1290
1291 // Check for biased locking unlock case, which is a no-op
1292 // Note: we do not have to check the thread ID for two reasons.
1293 // First, the interpreter checks for IllegalMonitorStateException at
1294 // a higher level. Second, if the bias was revoked while we held the
1295 // lock, the object could not be rebiased toward another thread, so
1296 // the bias bit would be clear.
1297 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1298 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1299 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1300 jcc(Assembler::equal, done);
1301 }
1302
1303 #ifdef COMPILER2
1304
1305 #if INCLUDE_RTM_OPT
1306
1307 // Update rtm_counters based on abort status
1308 // input: abort_status
1309 // rtm_counters (RTMLockingCounters*)
1310 // flags are killed
1311 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1312
1313 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1314 if (PrintPreciseRTMLockingStatistics) {
1315 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1316 Label check_abort;
1317 testl(abort_status, (1<<i));
1318 jccb(Assembler::equal, check_abort);
1319 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1320 bind(check_abort);
1321 }
1322 }
1323 }
1324
1325 // Branch if (random & (count-1) != 0), count is 2^n
1326 // tmp, scr and flags are killed
1327 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1328 assert(tmp == rax, "");
1329 assert(scr == rdx, "");
1330 rdtsc(); // modifies EDX:EAX
1331 andptr(tmp, count-1);
1332 jccb(Assembler::notZero, brLabel);
1333 }
1334
1335 // Perform abort ratio calculation, set no_rtm bit if high ratio
1336 // input: rtm_counters_Reg (RTMLockingCounters* address)
1337 // tmpReg, rtm_counters_Reg and flags are killed
1338 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1339 Register rtm_counters_Reg,
1340 RTMLockingCounters* rtm_counters,
1341 Metadata* method_data) {
1342 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1343
1344 if (RTMLockingCalculationDelay > 0) {
1345 // Delay calculation
1346 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1347 testptr(tmpReg, tmpReg);
1348 jccb(Assembler::equal, L_done);
1349 }
1350 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1351 // Aborted transactions = abort_count * 100
1352 // All transactions = total_count * RTMTotalCountIncrRate
1353 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1354
1355 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1356 cmpptr(tmpReg, RTMAbortThreshold);
1357 jccb(Assembler::below, L_check_always_rtm2);
1358 imulptr(tmpReg, tmpReg, 100);
1359
1360 Register scrReg = rtm_counters_Reg;
1361 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1362 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1363 imulptr(scrReg, scrReg, RTMAbortRatio);
1364 cmpptr(tmpReg, scrReg);
1365 jccb(Assembler::below, L_check_always_rtm1);
1366 if (method_data != NULL) {
1367 // set rtm_state to "no rtm" in MDO
1368 mov_metadata(tmpReg, method_data);
1369 if (os::is_MP()) {
1370 lock();
1371 }
1372 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1373 }
1374 jmpb(L_done);
1375 bind(L_check_always_rtm1);
1376 // Reload RTMLockingCounters* address
1377 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1378 bind(L_check_always_rtm2);
1379 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1380 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1381 jccb(Assembler::below, L_done);
1382 if (method_data != NULL) {
1383 // set rtm_state to "always rtm" in MDO
1384 mov_metadata(tmpReg, method_data);
1385 if (os::is_MP()) {
1386 lock();
1387 }
1388 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1389 }
1390 bind(L_done);
1391 }
1392
1393 // Update counters and perform abort ratio calculation
1394 // input: abort_status_Reg
1395 // rtm_counters_Reg, flags are killed
1396 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1397 Register rtm_counters_Reg,
1398 RTMLockingCounters* rtm_counters,
1399 Metadata* method_data,
1400 bool profile_rtm) {
1401
1402 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1403 // update rtm counters based on rax value at abort
1404 // reads abort_status_Reg, updates flags
1405 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1406 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1407 if (profile_rtm) {
1408 // Save abort status because abort_status_Reg is used by following code.
1409 if (RTMRetryCount > 0) {
1410 push(abort_status_Reg);
1411 }
1412 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1413 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1414 // restore abort status
1415 if (RTMRetryCount > 0) {
1416 pop(abort_status_Reg);
1417 }
1418 }
1419 }
1420
1421 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1422 // inputs: retry_count_Reg
1423 // : abort_status_Reg
1424 // output: retry_count_Reg decremented by 1
1425 // flags are killed
1426 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1427 Label doneRetry;
1428 assert(abort_status_Reg == rax, "");
1429 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1430 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1431 // if reason is in 0x6 and retry count != 0 then retry
1432 andptr(abort_status_Reg, 0x6);
1433 jccb(Assembler::zero, doneRetry);
1434 testl(retry_count_Reg, retry_count_Reg);
1435 jccb(Assembler::zero, doneRetry);
1436 pause();
1437 decrementl(retry_count_Reg);
1438 jmp(retryLabel);
1439 bind(doneRetry);
1440 }
1441
1442 // Spin and retry if lock is busy,
1443 // inputs: box_Reg (monitor address)
1444 // : retry_count_Reg
1445 // output: retry_count_Reg decremented by 1
1446 // : clear z flag if retry count exceeded
1447 // tmp_Reg, scr_Reg, flags are killed
1448 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1449 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1450 Label SpinLoop, SpinExit, doneRetry;
1451 // Clean monitor_value bit to get valid pointer
1452 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
1453
1454 testl(retry_count_Reg, retry_count_Reg);
1455 jccb(Assembler::zero, doneRetry);
1456 decrementl(retry_count_Reg);
1457 movptr(scr_Reg, RTMSpinLoopCount);
1458
1459 bind(SpinLoop);
1460 pause();
1461 decrementl(scr_Reg);
1462 jccb(Assembler::lessEqual, SpinExit);
1463 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1464 testptr(tmp_Reg, tmp_Reg);
1465 jccb(Assembler::notZero, SpinLoop);
1466
1467 bind(SpinExit);
1468 jmp(retryLabel);
1469 bind(doneRetry);
1470 incrementl(retry_count_Reg); // clear z flag
1471 }
1472
1473 // Use RTM for normal stack locks
1474 // Input: objReg (object to lock)
1475 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1476 Register retry_on_abort_count_Reg,
1477 RTMLockingCounters* stack_rtm_counters,
1478 Metadata* method_data, bool profile_rtm,
1479 Label& DONE_LABEL, Label& IsInflated) {
1480 assert(UseRTMForStackLocks, "why call this otherwise?");
1481 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1482 assert(tmpReg == rax, "");
1483 assert(scrReg == rdx, "");
1484 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1485
1486 if (RTMRetryCount > 0) {
1487 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1488 bind(L_rtm_retry);
1489 }
1490 movptr(tmpReg, Address(objReg, 0));
1491 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1492 jcc(Assembler::notZero, IsInflated);
1493
1494 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1495 Label L_noincrement;
1496 if (RTMTotalCountIncrRate > 1) {
1497 // tmpReg, scrReg and flags are killed
1498 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1499 }
1500 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1501 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1502 bind(L_noincrement);
1503 }
1504 xbegin(L_on_abort);
1505 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1506 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1507 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1508 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1509
1510 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1511 if (UseRTMXendForLockBusy) {
1512 xend();
1513 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1514 jmp(L_decrement_retry);
1515 }
1516 else {
1517 xabort(0);
1518 }
1519 bind(L_on_abort);
1520 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1521 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1522 }
1523 bind(L_decrement_retry);
1524 if (RTMRetryCount > 0) {
1525 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1526 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1527 }
1528 }
1529
1530 // Use RTM for inflating locks
1531 // inputs: objReg (object to lock)
1532 // boxReg (on-stack box address (displaced header location) - KILLED)
1533 // tmpReg (ObjectMonitor address + 2(monitor_value))
1534 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1535 Register scrReg, Register retry_on_busy_count_Reg,
1536 Register retry_on_abort_count_Reg,
1537 RTMLockingCounters* rtm_counters,
1538 Metadata* method_data, bool profile_rtm,
1539 Label& DONE_LABEL) {
1540 assert(UseRTMLocking, "why call this otherwise?");
1541 assert(tmpReg == rax, "");
1542 assert(scrReg == rdx, "");
1543 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1544 // Clean monitor_value bit to get valid pointer
1545 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
1546
1547 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1548 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1549 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1550
1551 if (RTMRetryCount > 0) {
1552 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1553 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1554 bind(L_rtm_retry);
1555 }
1556 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1557 Label L_noincrement;
1558 if (RTMTotalCountIncrRate > 1) {
1559 // tmpReg, scrReg and flags are killed
1560 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1561 }
1562 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1563 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1564 bind(L_noincrement);
1565 }
1566 xbegin(L_on_abort);
1567 movptr(tmpReg, Address(objReg, 0));
1568 movptr(tmpReg, Address(tmpReg, owner_offset));
1569 testptr(tmpReg, tmpReg);
1570 jcc(Assembler::zero, DONE_LABEL);
1571 if (UseRTMXendForLockBusy) {
1572 xend();
1573 jmp(L_decrement_retry);
1574 }
1575 else {
1576 xabort(0);
1577 }
1578 bind(L_on_abort);
1579 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1580 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1581 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1582 }
1583 if (RTMRetryCount > 0) {
1584 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1585 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1586 }
1587
1588 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1589 testptr(tmpReg, tmpReg) ;
1590 jccb(Assembler::notZero, L_decrement_retry) ;
1591
1592 // Appears unlocked - try to swing _owner from null to non-null.
1593 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1594 #ifdef _LP64
1595 Register threadReg = r15_thread;
1596 #else
1597 get_thread(scrReg);
1598 Register threadReg = scrReg;
1599 #endif
1600 if (os::is_MP()) {
1601 lock();
1602 }
1603 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1604
1605 if (RTMRetryCount > 0) {
1606 // success done else retry
1607 jccb(Assembler::equal, DONE_LABEL) ;
1608 bind(L_decrement_retry);
1609 // Spin and retry if lock is busy.
1610 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1611 }
1612 else {
1613 bind(L_decrement_retry);
1614 }
1615 }
1616
1617 #endif // INCLUDE_RTM_OPT
1618
1619 // Fast_Lock and Fast_Unlock used by C2
1620
1621 // Because the transitions from emitted code to the runtime
1622 // monitorenter/exit helper stubs are so slow it's critical that
1623 // we inline both the stack-locking fast-path and the inflated fast path.
1624 //
1625 // See also: cmpFastLock and cmpFastUnlock.
1626 //
1627 // What follows is a specialized inline transliteration of the code
1628 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1629 // another option would be to emit TrySlowEnter and TrySlowExit methods
1630 // at startup-time. These methods would accept arguments as
1631 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1632 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1633 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1634 // In practice, however, the # of lock sites is bounded and is usually small.
1635 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1636 // if the processor uses simple bimodal branch predictors keyed by EIP
1637 // Since the helper routines would be called from multiple synchronization
1638 // sites.
1639 //
1640 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1641 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1642 // to those specialized methods. That'd give us a mostly platform-independent
1643 // implementation that the JITs could optimize and inline at their pleasure.
1644 // Done correctly, the only time we'd need to cross to native could would be
1645 // to park() or unpark() threads. We'd also need a few more unsafe operators
1646 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1647 // (b) explicit barriers or fence operations.
1648 //
1649 // TODO:
1650 //
1651 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1652 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1653 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1654 // the lock operators would typically be faster than reifying Self.
1655 //
1656 // * Ideally I'd define the primitives as:
1657 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1658 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1659 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1660 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1661 // Furthermore the register assignments are overconstrained, possibly resulting in
1662 // sub-optimal code near the synchronization site.
1663 //
1664 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1665 // Alternately, use a better sp-proximity test.
1666 //
1667 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1668 // Either one is sufficient to uniquely identify a thread.
1669 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1670 //
1671 // * Intrinsify notify() and notifyAll() for the common cases where the
1672 // object is locked by the calling thread but the waitlist is empty.
1673 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1674 //
1675 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1676 // But beware of excessive branch density on AMD Opterons.
1677 //
1678 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1679 // or failure of the fast-path. If the fast-path fails then we pass
1680 // control to the slow-path, typically in C. In Fast_Lock and
1681 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1682 // will emit a conditional branch immediately after the node.
1683 // So we have branches to branches and lots of ICC.ZF games.
1684 // Instead, it might be better to have C2 pass a "FailureLabel"
1685 // into Fast_Lock and Fast_Unlock. In the case of success, control
1686 // will drop through the node. ICC.ZF is undefined at exit.
1687 // In the case of failure, the node will branch directly to the
1688 // FailureLabel
1689
1690
1691 // obj: object to lock
1692 // box: on-stack box address (displaced header location) - KILLED
1693 // rax,: tmp -- KILLED
1694 // scr: tmp -- KILLED
1695 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1696 Register scrReg, Register cx1Reg, Register cx2Reg,
1697 BiasedLockingCounters* counters,
1698 RTMLockingCounters* rtm_counters,
1699 RTMLockingCounters* stack_rtm_counters,
1700 Metadata* method_data,
1701 bool use_rtm, bool profile_rtm) {
1702 // Ensure the register assignents are disjoint
1703 assert(tmpReg == rax, "");
1704
1705 if (use_rtm) {
1706 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1707 } else {
1708 assert(cx1Reg == noreg, "");
1709 assert(cx2Reg == noreg, "");
1710 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1711 }
1712
1713 if (counters != NULL) {
1714 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1715 }
1716 if (EmitSync & 1) {
1717 // set box->dhw = unused_mark (3)
1718 // Force all sync thru slow-path: slow_enter() and slow_exit()
1719 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1720 cmpptr (rsp, (int32_t)NULL_WORD);
1721 } else
1722 if (EmitSync & 2) {
1723 Label DONE_LABEL ;
1724 if (UseBiasedLocking) {
1725 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
1726 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1727 }
1728
1729 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1730 orptr (tmpReg, 0x1);
1731 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1732 if (os::is_MP()) {
1733 lock();
1734 }
1735 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1736 jccb(Assembler::equal, DONE_LABEL);
1737 // Recursive locking
1738 subptr(tmpReg, rsp);
1739 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1740 movptr(Address(boxReg, 0), tmpReg);
1741 bind(DONE_LABEL);
1742 } else {
1743 // Possible cases that we'll encounter in fast_lock
1744 // ------------------------------------------------
1745 // * Inflated
1746 // -- unlocked
1747 // -- Locked
1748 // = by self
1749 // = by other
1750 // * biased
1751 // -- by Self
1752 // -- by other
1753 // * neutral
1754 // * stack-locked
1755 // -- by self
1756 // = sp-proximity test hits
1757 // = sp-proximity test generates false-negative
1758 // -- by other
1759 //
1760
1761 Label IsInflated, DONE_LABEL;
1762
1763 // it's stack-locked, biased or neutral
1764 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1765 // order to reduce the number of conditional branches in the most common cases.
1766 // Beware -- there's a subtle invariant that fetch of the markword
1767 // at [FETCH], below, will never observe a biased encoding (*101b).
1768 // If this invariant is not held we risk exclusion (safety) failure.
1769 if (UseBiasedLocking && !UseOptoBiasInlining) {
1770 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1771 }
1772
1773 #if INCLUDE_RTM_OPT
1774 if (UseRTMForStackLocks && use_rtm) {
1775 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1776 stack_rtm_counters, method_data, profile_rtm,
1777 DONE_LABEL, IsInflated);
1778 }
1779 #endif // INCLUDE_RTM_OPT
1780
1781 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1782 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1783 jccb(Assembler::notZero, IsInflated);
1784
1785 // Attempt stack-locking ...
1786 orptr (tmpReg, markOopDesc::unlocked_value);
1787 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1788 if (os::is_MP()) {
1789 lock();
1790 }
1791 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1792 if (counters != NULL) {
1793 cond_inc32(Assembler::equal,
1794 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1795 }
1796 jcc(Assembler::equal, DONE_LABEL); // Success
1797
1798 // Recursive locking.
1799 // The object is stack-locked: markword contains stack pointer to BasicLock.
1800 // Locked by current thread if difference with current SP is less than one page.
1801 subptr(tmpReg, rsp);
1802 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1803 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1804 movptr(Address(boxReg, 0), tmpReg);
1805 if (counters != NULL) {
1806 cond_inc32(Assembler::equal,
1807 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1808 }
1809 jmp(DONE_LABEL);
1810
1811 bind(IsInflated);
1812 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + 2(monitor_value)
1813
1814 #if INCLUDE_RTM_OPT
1815 // Use the same RTM locking code in 32- and 64-bit VM.
1816 if (use_rtm) {
1817 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1818 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1819 } else {
1820 #endif // INCLUDE_RTM_OPT
1821
1822 #ifndef _LP64
1823 // The object is inflated.
1824 //
1825 // TODO-FIXME: eliminate the ugly use of manifest constants:
1826 // Use markOopDesc::monitor_value instead of "2".
1827 // use markOop::unused_mark() instead of "3".
1828 // The tmpReg value is an objectMonitor reference ORed with
1829 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
1830 // objectmonitor pointer by masking off the "2" bit or we can just
1831 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
1832 // field offsets with "-2" to compensate for and annul the low-order tag bit.
1833 //
1834 // I use the latter as it avoids AGI stalls.
1835 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
1836 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
1837 //
1838 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
1839
1840 // boxReg refers to the on-stack BasicLock in the current frame.
1841 // We'd like to write:
1842 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
1843 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1844 // additional latency as we have another ST in the store buffer that must drain.
1845
1846 if (EmitSync & 8192) {
1847 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1848 get_thread (scrReg);
1849 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1850 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1851 if (os::is_MP()) {
1852 lock();
1853 }
1854 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1855 } else
1856 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1857 movptr(scrReg, boxReg);
1858 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1859
1860 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1861 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1862 // prefetchw [eax + Offset(_owner)-2]
1863 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
1864 }
1865
1866 if ((EmitSync & 64) == 0) {
1867 // Optimistic form: consider XORL tmpReg,tmpReg
1868 movptr(tmpReg, NULL_WORD);
1869 } else {
1870 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1871 // Test-And-CAS instead of CAS
1872 movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); // rax, = m->_owner
1873 testptr(tmpReg, tmpReg); // Locked ?
1874 jccb (Assembler::notZero, DONE_LABEL);
1875 }
1876
1877 // Appears unlocked - try to swing _owner from null to non-null.
1878 // Ideally, I'd manifest "Self" with get_thread and then attempt
1879 // to CAS the register containing Self into m->Owner.
1880 // But we don't have enough registers, so instead we can either try to CAS
1881 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1882 // we later store "Self" into m->Owner. Transiently storing a stack address
1883 // (rsp or the address of the box) into m->owner is harmless.
1884 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1885 if (os::is_MP()) {
1886 lock();
1887 }
1888 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1889 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1890 jccb (Assembler::notZero, DONE_LABEL);
1891 get_thread (scrReg); // beware: clobbers ICCs
1892 movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg);
1893 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1894
1895 // If the CAS fails we can either retry or pass control to the slow-path.
1896 // We use the latter tactic.
1897 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1898 // If the CAS was successful ...
1899 // Self has acquired the lock
1900 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1901 // Intentional fall-through into DONE_LABEL ...
1902 } else {
1903 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1904 movptr(boxReg, tmpReg);
1905
1906 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1907 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1908 // prefetchw [eax + Offset(_owner)-2]
1909 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
1910 }
1911
1912 if ((EmitSync & 64) == 0) {
1913 // Optimistic form
1914 xorptr (tmpReg, tmpReg);
1915 } else {
1916 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1917 movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); // rax, = m->_owner
1918 testptr(tmpReg, tmpReg); // Locked ?
1919 jccb (Assembler::notZero, DONE_LABEL);
1920 }
1921
1922 // Appears unlocked - try to swing _owner from null to non-null.
1923 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1924 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1925 get_thread (scrReg);
1926 if (os::is_MP()) {
1927 lock();
1928 }
1929 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1930
1931 // If the CAS fails we can either retry or pass control to the slow-path.
1932 // We use the latter tactic.
1933 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1934 // If the CAS was successful ...
1935 // Self has acquired the lock
1936 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1937 // Intentional fall-through into DONE_LABEL ...
1938 }
1939 #else // _LP64
1940 // It's inflated
1941
1942 // TODO: someday avoid the ST-before-CAS penalty by
1943 // relocating (deferring) the following ST.
1944 // We should also think about trying a CAS without having
1945 // fetched _owner. If the CAS is successful we may
1946 // avoid an RTO->RTS upgrade on the $line.
1947
1948 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1949 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1950
1951 movptr (boxReg, tmpReg);
1952 movptr (tmpReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1953 testptr(tmpReg, tmpReg);
1954 jccb (Assembler::notZero, DONE_LABEL);
1955
1956 // It's inflated and appears unlocked
1957 if (os::is_MP()) {
1958 lock();
1959 }
1960 cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1961 // Intentional fall-through into DONE_LABEL ...
1962 #endif // _LP64
1963
1964 #if INCLUDE_RTM_OPT
1965 } // use_rtm()
1966 #endif
1967 // DONE_LABEL is a hot target - we'd really like to place it at the
1968 // start of cache line by padding with NOPs.
1969 // See the AMD and Intel software optimization manuals for the
1970 // most efficient "long" NOP encodings.
1971 // Unfortunately none of our alignment mechanisms suffice.
1972 bind(DONE_LABEL);
1973
1974 // At DONE_LABEL the icc ZFlag is set as follows ...
1975 // Fast_Unlock uses the same protocol.
1976 // ZFlag == 1 -> Success
1977 // ZFlag == 0 -> Failure - force control through the slow-path
1978 }
1979 }
1980
1981 // obj: object to unlock
1982 // box: box address (displaced header location), killed. Must be EAX.
1983 // tmp: killed, cannot be obj nor box.
1984 //
1985 // Some commentary on balanced locking:
1986 //
1987 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1988 // Methods that don't have provably balanced locking are forced to run in the
1989 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1990 // The interpreter provides two properties:
1991 // I1: At return-time the interpreter automatically and quietly unlocks any
1992 // objects acquired the current activation (frame). Recall that the
1993 // interpreter maintains an on-stack list of locks currently held by
1994 // a frame.
1995 // I2: If a method attempts to unlock an object that is not held by the
1996 // the frame the interpreter throws IMSX.
1997 //
1998 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1999 // B() doesn't have provably balanced locking so it runs in the interpreter.
2000 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
2001 // is still locked by A().
2002 //
2003 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
2004 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
2005 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
2006 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
2007
2008 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
2009 assert(boxReg == rax, "");
2010 assert_different_registers(objReg, boxReg, tmpReg);
2011
2012 if (EmitSync & 4) {
2013 // Disable - inhibit all inlining. Force control through the slow-path
2014 cmpptr (rsp, 0);
2015 } else
2016 if (EmitSync & 8) {
2017 Label DONE_LABEL;
2018 if (UseBiasedLocking) {
2019 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2020 }
2021 // Classic stack-locking code ...
2022 // Check whether the displaced header is 0
2023 //(=> recursive unlock)
2024 movptr(tmpReg, Address(boxReg, 0));
2025 testptr(tmpReg, tmpReg);
2026 jccb(Assembler::zero, DONE_LABEL);
2027 // If not recursive lock, reset the header to displaced header
2028 if (os::is_MP()) {
2029 lock();
2030 }
2031 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2032 bind(DONE_LABEL);
2033 } else {
2034 Label DONE_LABEL, Stacked, CheckSucc;
2035
2036 // Critically, the biased locking test must have precedence over
2037 // and appear before the (box->dhw == 0) recursive stack-lock test.
2038 if (UseBiasedLocking && !UseOptoBiasInlining) {
2039 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2040 }
2041
2042 #if INCLUDE_RTM_OPT
2043 if (UseRTMForStackLocks && use_rtm) {
2044 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
2045 Label L_regular_unlock;
2046 movptr(tmpReg, Address(objReg, 0)); // fetch markword
2047 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2048 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
2049 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
2050 xend(); // otherwise end...
2051 jmp(DONE_LABEL); // ... and we're done
2052 bind(L_regular_unlock);
2053 }
2054 #endif
2055
2056 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2057 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2058 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
2059 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2060 jccb (Assembler::zero, Stacked);
2061
2062 // It's inflated.
2063 #if INCLUDE_RTM_OPT
2064 if (use_rtm) {
2065 Label L_regular_inflated_unlock;
2066 // Clean monitor_value bit to get valid pointer
2067 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
2068 movptr(boxReg, Address(tmpReg, owner_offset));
2069 testptr(boxReg, boxReg);
2070 jccb(Assembler::notZero, L_regular_inflated_unlock);
2071 xend();
2072 jmpb(DONE_LABEL);
2073 bind(L_regular_inflated_unlock);
2074 }
2075 #endif
2076
2077 // Despite our balanced locking property we still check that m->_owner == Self
2078 // as java routines or native JNI code called by this thread might
2079 // have released the lock.
2080 // Refer to the comments in synchronizer.cpp for how we might encode extra
2081 // state in _succ so we can avoid fetching EntryList|cxq.
2082 //
2083 // I'd like to add more cases in fast_lock() and fast_unlock() --
2084 // such as recursive enter and exit -- but we have to be wary of
2085 // I$ bloat, T$ effects and BP$ effects.
2086 //
2087 // If there's no contention try a 1-0 exit. That is, exit without
2088 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2089 // we detect and recover from the race that the 1-0 exit admits.
2090 //
2091 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2092 // before it STs null into _owner, releasing the lock. Updates
2093 // to data protected by the critical section must be visible before
2094 // we drop the lock (and thus before any other thread could acquire
2095 // the lock and observe the fields protected by the lock).
2096 // IA32's memory-model is SPO, so STs are ordered with respect to
2097 // each other and there's no need for an explicit barrier (fence).
2098 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2099 #ifndef _LP64
2100 get_thread (boxReg);
2101 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2102 // prefetchw [ebx + Offset(_owner)-2]
2103 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2104 }
2105
2106 // Note that we could employ various encoding schemes to reduce
2107 // the number of loads below (currently 4) to just 2 or 3.
2108 // Refer to the comments in synchronizer.cpp.
2109 // In practice the chain of fetches doesn't seem to impact performance, however.
2110 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2111 // Attempt to reduce branch density - AMD's branch predictor.
2112 xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2113 orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2114 orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2115 orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2116 jccb (Assembler::notZero, DONE_LABEL);
2117 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2118 jmpb (DONE_LABEL);
2119 } else {
2120 xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2121 orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2122 jccb (Assembler::notZero, DONE_LABEL);
2123 movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2124 orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2125 jccb (Assembler::notZero, CheckSucc);
2126 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2127 jmpb (DONE_LABEL);
2128 }
2129
2130 // The Following code fragment (EmitSync & 65536) improves the performance of
2131 // contended applications and contended synchronization microbenchmarks.
2132 // Unfortunately the emission of the code - even though not executed - causes regressions
2133 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2134 // with an equal number of never-executed NOPs results in the same regression.
2135 // We leave it off by default.
2136
2137 if ((EmitSync & 65536) != 0) {
2138 Label LSuccess, LGoSlowPath ;
2139
2140 bind (CheckSucc);
2141
2142 // Optional pre-test ... it's safe to elide this
2143 if ((EmitSync & 16) == 0) {
2144 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2145 jccb (Assembler::zero, LGoSlowPath);
2146 }
2147
2148 // We have a classic Dekker-style idiom:
2149 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2150 // There are a number of ways to implement the barrier:
2151 // (1) lock:andl &m->_owner, 0
2152 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2153 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2154 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2155 // (2) If supported, an explicit MFENCE is appealing.
2156 // In older IA32 processors MFENCE is slower than lock:add or xchg
2157 // particularly if the write-buffer is full as might be the case if
2158 // if stores closely precede the fence or fence-equivalent instruction.
2159 // In more modern implementations MFENCE appears faster, however.
2160 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2161 // The $lines underlying the top-of-stack should be in M-state.
2162 // The locked add instruction is serializing, of course.
2163 // (4) Use xchg, which is serializing
2164 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2165 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2166 // The integer condition codes will tell us if succ was 0.
2167 // Since _succ and _owner should reside in the same $line and
2168 // we just stored into _owner, it's likely that the $line
2169 // remains in M-state for the lock:orl.
2170 //
2171 // We currently use (3), although it's likely that switching to (2)
2172 // is correct for the future.
2173
2174 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2175 if (os::is_MP()) {
2176 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
2177 mfence();
2178 } else {
2179 lock (); addptr(Address(rsp, 0), 0);
2180 }
2181 }
2182 // Ratify _succ remains non-null
2183 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0);
2184 jccb (Assembler::notZero, LSuccess);
2185
2186 xorptr(boxReg, boxReg); // box is really EAX
2187 if (os::is_MP()) { lock(); }
2188 cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2189 jccb (Assembler::notEqual, LSuccess);
2190 // Since we're low on registers we installed rsp as a placeholding in _owner.
2191 // Now install Self over rsp. This is safe as we're transitioning from
2192 // non-null to non=null
2193 get_thread (boxReg);
2194 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg);
2195 // Intentional fall-through into LGoSlowPath ...
2196
2197 bind (LGoSlowPath);
2198 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2199 jmpb (DONE_LABEL);
2200
2201 bind (LSuccess);
2202 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2203 jmpb (DONE_LABEL);
2204 }
2205
2206 bind (Stacked);
2207 // It's not inflated and it's not recursively stack-locked and it's not biased.
2208 // It must be stack-locked.
2209 // Try to reset the header to displaced header.
2210 // The "box" value on the stack is stable, so we can reload
2211 // and be assured we observe the same value as above.
2212 movptr(tmpReg, Address(boxReg, 0));
2213 if (os::is_MP()) {
2214 lock();
2215 }
2216 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2217 // Intention fall-thru into DONE_LABEL
2218
2219 // DONE_LABEL is a hot target - we'd really like to place it at the
2220 // start of cache line by padding with NOPs.
2221 // See the AMD and Intel software optimization manuals for the
2222 // most efficient "long" NOP encodings.
2223 // Unfortunately none of our alignment mechanisms suffice.
2224 if ((EmitSync & 65536) == 0) {
2225 bind (CheckSucc);
2226 }
2227 #else // _LP64
2228 // It's inflated
2229 movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2230 xorptr(boxReg, r15_thread);
2231 orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2232 jccb (Assembler::notZero, DONE_LABEL);
2233 movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2234 orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2235 jccb (Assembler::notZero, CheckSucc);
2236 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD);
2237 jmpb (DONE_LABEL);
2238
2239 if ((EmitSync & 65536) == 0) {
2240 Label LSuccess, LGoSlowPath ;
2241 bind (CheckSucc);
2242 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2243 jccb (Assembler::zero, LGoSlowPath);
2244
2245 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
2246 // the explicit ST;MEMBAR combination, but masm doesn't currently support
2247 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
2248 // are all faster when the write buffer is populated.
2249 movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD);
2250 if (os::is_MP()) {
2251 lock (); addl (Address(rsp, 0), 0);
2252 }
2253 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2254 jccb (Assembler::notZero, LSuccess);
2255
2256 movptr (boxReg, (int32_t)NULL_WORD); // box is really EAX
2257 if (os::is_MP()) { lock(); }
2258 cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2259 jccb (Assembler::notEqual, LSuccess);
2260 // Intentional fall-through into slow-path
2261
2262 bind (LGoSlowPath);
2263 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2264 jmpb (DONE_LABEL);
2265
2266 bind (LSuccess);
2267 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2268 jmpb (DONE_LABEL);
2269 }
2270
2271 bind (Stacked);
2272 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2273 if (os::is_MP()) { lock(); }
2274 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2275
2276 if (EmitSync & 65536) {
2277 bind (CheckSucc);
2278 }
2279 #endif
2280 bind(DONE_LABEL);
2281 // Avoid branch to branch on AMD processors
2282 if (EmitSync & 32768) {
2283 nop();
2284 }
2285 }
2286 }
2287 #endif // COMPILER2
2288
2289 void MacroAssembler::c2bool(Register x) {
2290 // implements x == 0 ? 0 : 1
2291 // note: must only look at least-significant byte of x
2292 // since C-style booleans are stored in one byte
2293 // only! (was bug)
2294 andl(x, 0xFF);
2295 setb(Assembler::notZero, x);
2296 }
2297
2298 // Wouldn't need if AddressLiteral version had new name
2299 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2300 Assembler::call(L, rtype);
2301 }
2302
2303 void MacroAssembler::call(Register entry) {
2304 Assembler::call(entry);
2305 }
2306
2307 void MacroAssembler::call(AddressLiteral entry) {
2308 if (reachable(entry)) {
2309 Assembler::call_literal(entry.target(), entry.rspec());
2310 } else {
2311 lea(rscratch1, entry);
2312 Assembler::call(rscratch1);
2313 }
2314 }
2315
2316 void MacroAssembler::ic_call(address entry) {
2317 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2318 movptr(rax, (intptr_t)Universe::non_oop_word());
2319 call(AddressLiteral(entry, rh));
2320 }
2321
2322 // Implementation of call_VM versions
2323
2324 void MacroAssembler::call_VM(Register oop_result,
2325 address entry_point,
2326 bool check_exceptions) {
2327 Label C, E;
2328 call(C, relocInfo::none);
2329 jmp(E);
2330
2331 bind(C);
2332 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2333 ret(0);
2334
2335 bind(E);
2336 }
2337
2338 void MacroAssembler::call_VM(Register oop_result,
2339 address entry_point,
2340 Register arg_1,
2341 bool check_exceptions) {
2342 Label C, E;
2343 call(C, relocInfo::none);
2344 jmp(E);
2345
2346 bind(C);
2347 pass_arg1(this, arg_1);
2348 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2349 ret(0);
2350
2351 bind(E);
2352 }
2353
2354 void MacroAssembler::call_VM(Register oop_result,
2355 address entry_point,
2356 Register arg_1,
2357 Register arg_2,
2358 bool check_exceptions) {
2359 Label C, E;
2360 call(C, relocInfo::none);
2361 jmp(E);
2362
2363 bind(C);
2364
2365 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2366
2367 pass_arg2(this, arg_2);
2368 pass_arg1(this, arg_1);
2369 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2370 ret(0);
2371
2372 bind(E);
2373 }
2374
2375 void MacroAssembler::call_VM(Register oop_result,
2376 address entry_point,
2377 Register arg_1,
2378 Register arg_2,
2379 Register arg_3,
2380 bool check_exceptions) {
2381 Label C, E;
2382 call(C, relocInfo::none);
2383 jmp(E);
2384
2385 bind(C);
2386
2387 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2388 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2389 pass_arg3(this, arg_3);
2390
2391 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2392 pass_arg2(this, arg_2);
2393
2394 pass_arg1(this, arg_1);
2395 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2396 ret(0);
2397
2398 bind(E);
2399 }
2400
2401 void MacroAssembler::call_VM(Register oop_result,
2402 Register last_java_sp,
2403 address entry_point,
2404 int number_of_arguments,
2405 bool check_exceptions) {
2406 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2407 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2408 }
2409
2410 void MacroAssembler::call_VM(Register oop_result,
2411 Register last_java_sp,
2412 address entry_point,
2413 Register arg_1,
2414 bool check_exceptions) {
2415 pass_arg1(this, arg_1);
2416 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2417 }
2418
2419 void MacroAssembler::call_VM(Register oop_result,
2420 Register last_java_sp,
2421 address entry_point,
2422 Register arg_1,
2423 Register arg_2,
2424 bool check_exceptions) {
2425
2426 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2427 pass_arg2(this, arg_2);
2428 pass_arg1(this, arg_1);
2429 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2430 }
2431
2432 void MacroAssembler::call_VM(Register oop_result,
2433 Register last_java_sp,
2434 address entry_point,
2435 Register arg_1,
2436 Register arg_2,
2437 Register arg_3,
2438 bool check_exceptions) {
2439 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2440 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2441 pass_arg3(this, arg_3);
2442 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2443 pass_arg2(this, arg_2);
2444 pass_arg1(this, arg_1);
2445 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2446 }
2447
2448 void MacroAssembler::super_call_VM(Register oop_result,
2449 Register last_java_sp,
2450 address entry_point,
2451 int number_of_arguments,
2452 bool check_exceptions) {
2453 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2454 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2455 }
2456
2457 void MacroAssembler::super_call_VM(Register oop_result,
2458 Register last_java_sp,
2459 address entry_point,
2460 Register arg_1,
2461 bool check_exceptions) {
2462 pass_arg1(this, arg_1);
2463 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2464 }
2465
2466 void MacroAssembler::super_call_VM(Register oop_result,
2467 Register last_java_sp,
2468 address entry_point,
2469 Register arg_1,
2470 Register arg_2,
2471 bool check_exceptions) {
2472
2473 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2474 pass_arg2(this, arg_2);
2475 pass_arg1(this, arg_1);
2476 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2477 }
2478
2479 void MacroAssembler::super_call_VM(Register oop_result,
2480 Register last_java_sp,
2481 address entry_point,
2482 Register arg_1,
2483 Register arg_2,
2484 Register arg_3,
2485 bool check_exceptions) {
2486 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2487 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2488 pass_arg3(this, arg_3);
2489 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2490 pass_arg2(this, arg_2);
2491 pass_arg1(this, arg_1);
2492 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2493 }
2494
2495 void MacroAssembler::call_VM_base(Register oop_result,
2496 Register java_thread,
2497 Register last_java_sp,
2498 address entry_point,
2499 int number_of_arguments,
2500 bool check_exceptions) {
2501 // determine java_thread register
2502 if (!java_thread->is_valid()) {
2503 #ifdef _LP64
2504 java_thread = r15_thread;
2505 #else
2506 java_thread = rdi;
2507 get_thread(java_thread);
2508 #endif // LP64
2509 }
2510 // determine last_java_sp register
2511 if (!last_java_sp->is_valid()) {
2512 last_java_sp = rsp;
2513 }
2514 // debugging support
2515 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2516 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2517 #ifdef ASSERT
2518 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2519 // r12 is the heapbase.
2520 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2521 #endif // ASSERT
2522
2523 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2524 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2525
2526 // push java thread (becomes first argument of C function)
2527
2528 NOT_LP64(push(java_thread); number_of_arguments++);
2529 LP64_ONLY(mov(c_rarg0, r15_thread));
2530
2531 // set last Java frame before call
2532 assert(last_java_sp != rbp, "can't use ebp/rbp");
2533
2534 // Only interpreter should have to set fp
2535 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2536
2537 // do the call, remove parameters
2538 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2539
2540 // restore the thread (cannot use the pushed argument since arguments
2541 // may be overwritten by C code generated by an optimizing compiler);
2542 // however can use the register value directly if it is callee saved.
2543 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2544 // rdi & rsi (also r15) are callee saved -> nothing to do
2545 #ifdef ASSERT
2546 guarantee(java_thread != rax, "change this code");
2547 push(rax);
2548 { Label L;
2549 get_thread(rax);
2550 cmpptr(java_thread, rax);
2551 jcc(Assembler::equal, L);
2552 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2553 bind(L);
2554 }
2555 pop(rax);
2556 #endif
2557 } else {
2558 get_thread(java_thread);
2559 }
2560 // reset last Java frame
2561 // Only interpreter should have to clear fp
2562 reset_last_Java_frame(java_thread, true);
2563
2564 #ifndef CC_INTERP
2565 // C++ interp handles this in the interpreter
2566 check_and_handle_popframe(java_thread);
2567 check_and_handle_earlyret(java_thread);
2568 #endif /* CC_INTERP */
2569
2570 if (check_exceptions) {
2571 // check for pending exceptions (java_thread is set upon return)
2572 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2573 #ifndef _LP64
2574 jump_cc(Assembler::notEqual,
2575 RuntimeAddress(StubRoutines::forward_exception_entry()));
2576 #else
2577 // This used to conditionally jump to forward_exception however it is
2578 // possible if we relocate that the branch will not reach. So we must jump
2579 // around so we can always reach
2580
2581 Label ok;
2582 jcc(Assembler::equal, ok);
2583 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2584 bind(ok);
2585 #endif // LP64
2586 }
2587
2588 // get oop result if there is one and reset the value in the thread
2589 if (oop_result->is_valid()) {
2590 get_vm_result(oop_result, java_thread);
2591 }
2592 }
2593
2594 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2595
2596 // Calculate the value for last_Java_sp
2597 // somewhat subtle. call_VM does an intermediate call
2598 // which places a return address on the stack just under the
2599 // stack pointer as the user finsihed with it. This allows
2600 // use to retrieve last_Java_pc from last_Java_sp[-1].
2601 // On 32bit we then have to push additional args on the stack to accomplish
2602 // the actual requested call. On 64bit call_VM only can use register args
2603 // so the only extra space is the return address that call_VM created.
2604 // This hopefully explains the calculations here.
2605
2606 #ifdef _LP64
2607 // We've pushed one address, correct last_Java_sp
2608 lea(rax, Address(rsp, wordSize));
2609 #else
2610 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2611 #endif // LP64
2612
2613 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2614
2615 }
2616
2617 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2618 call_VM_leaf_base(entry_point, number_of_arguments);
2619 }
2620
2621 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2622 pass_arg0(this, arg_0);
2623 call_VM_leaf(entry_point, 1);
2624 }
2625
2626 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2627
2628 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2629 pass_arg1(this, arg_1);
2630 pass_arg0(this, arg_0);
2631 call_VM_leaf(entry_point, 2);
2632 }
2633
2634 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2635 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2636 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2637 pass_arg2(this, arg_2);
2638 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2639 pass_arg1(this, arg_1);
2640 pass_arg0(this, arg_0);
2641 call_VM_leaf(entry_point, 3);
2642 }
2643
2644 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2645 pass_arg0(this, arg_0);
2646 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2647 }
2648
2649 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2650
2651 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2652 pass_arg1(this, arg_1);
2653 pass_arg0(this, arg_0);
2654 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2655 }
2656
2657 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2658 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2659 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2660 pass_arg2(this, arg_2);
2661 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2662 pass_arg1(this, arg_1);
2663 pass_arg0(this, arg_0);
2664 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2665 }
2666
2667 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2668 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2669 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2670 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2671 pass_arg3(this, arg_3);
2672 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2673 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2674 pass_arg2(this, arg_2);
2675 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2676 pass_arg1(this, arg_1);
2677 pass_arg0(this, arg_0);
2678 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2679 }
2680
2681 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2682 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2683 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2684 verify_oop(oop_result, "broken oop in call_VM_base");
2685 }
2686
2687 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2688 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2689 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2690 }
2691
2692 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2693 }
2694
2695 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2696 }
2697
2698 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2699 if (reachable(src1)) {
2700 cmpl(as_Address(src1), imm);
2701 } else {
2702 lea(rscratch1, src1);
2703 cmpl(Address(rscratch1, 0), imm);
2704 }
2705 }
2706
2707 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2708 assert(!src2.is_lval(), "use cmpptr");
2709 if (reachable(src2)) {
2710 cmpl(src1, as_Address(src2));
2711 } else {
2712 lea(rscratch1, src2);
2713 cmpl(src1, Address(rscratch1, 0));
2714 }
2715 }
2716
2717 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2718 Assembler::cmpl(src1, imm);
2719 }
2720
2721 void MacroAssembler::cmp32(Register src1, Address src2) {
2722 Assembler::cmpl(src1, src2);
2723 }
2724
2725 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2726 ucomisd(opr1, opr2);
2727
2728 Label L;
2729 if (unordered_is_less) {
2730 movl(dst, -1);
2731 jcc(Assembler::parity, L);
2732 jcc(Assembler::below , L);
2733 movl(dst, 0);
2734 jcc(Assembler::equal , L);
2735 increment(dst);
2736 } else { // unordered is greater
2737 movl(dst, 1);
2738 jcc(Assembler::parity, L);
2739 jcc(Assembler::above , L);
2740 movl(dst, 0);
2741 jcc(Assembler::equal , L);
2742 decrementl(dst);
2743 }
2744 bind(L);
2745 }
2746
2747 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2748 ucomiss(opr1, opr2);
2749
2750 Label L;
2751 if (unordered_is_less) {
2752 movl(dst, -1);
2753 jcc(Assembler::parity, L);
2754 jcc(Assembler::below , L);
2755 movl(dst, 0);
2756 jcc(Assembler::equal , L);
2757 increment(dst);
2758 } else { // unordered is greater
2759 movl(dst, 1);
2760 jcc(Assembler::parity, L);
2761 jcc(Assembler::above , L);
2762 movl(dst, 0);
2763 jcc(Assembler::equal , L);
2764 decrementl(dst);
2765 }
2766 bind(L);
2767 }
2768
2769
2770 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2771 if (reachable(src1)) {
2772 cmpb(as_Address(src1), imm);
2773 } else {
2774 lea(rscratch1, src1);
2775 cmpb(Address(rscratch1, 0), imm);
2776 }
2777 }
2778
2779 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2780 #ifdef _LP64
2781 if (src2.is_lval()) {
2782 movptr(rscratch1, src2);
2783 Assembler::cmpq(src1, rscratch1);
2784 } else if (reachable(src2)) {
2785 cmpq(src1, as_Address(src2));
2786 } else {
2787 lea(rscratch1, src2);
2788 Assembler::cmpq(src1, Address(rscratch1, 0));
2789 }
2790 #else
2791 if (src2.is_lval()) {
2792 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2793 } else {
2794 cmpl(src1, as_Address(src2));
2795 }
2796 #endif // _LP64
2797 }
2798
2799 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2800 assert(src2.is_lval(), "not a mem-mem compare");
2801 #ifdef _LP64
2802 // moves src2's literal address
2803 movptr(rscratch1, src2);
2804 Assembler::cmpq(src1, rscratch1);
2805 #else
2806 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2807 #endif // _LP64
2808 }
2809
2810 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2811 if (reachable(adr)) {
2812 if (os::is_MP())
2813 lock();
2814 cmpxchgptr(reg, as_Address(adr));
2815 } else {
2816 lea(rscratch1, adr);
2817 if (os::is_MP())
2818 lock();
2819 cmpxchgptr(reg, Address(rscratch1, 0));
2820 }
2821 }
2822
2823 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2824 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2825 }
2826
2827 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2828 if (reachable(src)) {
2829 Assembler::comisd(dst, as_Address(src));
2830 } else {
2831 lea(rscratch1, src);
2832 Assembler::comisd(dst, Address(rscratch1, 0));
2833 }
2834 }
2835
2836 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2837 if (reachable(src)) {
2838 Assembler::comiss(dst, as_Address(src));
2839 } else {
2840 lea(rscratch1, src);
2841 Assembler::comiss(dst, Address(rscratch1, 0));
2842 }
2843 }
2844
2845
2846 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2847 Condition negated_cond = negate_condition(cond);
2848 Label L;
2849 jcc(negated_cond, L);
2850 pushf(); // Preserve flags
2851 atomic_incl(counter_addr);
2852 popf();
2853 bind(L);
2854 }
2855
2856 int MacroAssembler::corrected_idivl(Register reg) {
2857 // Full implementation of Java idiv and irem; checks for
2858 // special case as described in JVM spec., p.243 & p.271.
2859 // The function returns the (pc) offset of the idivl
2860 // instruction - may be needed for implicit exceptions.
2861 //
2862 // normal case special case
2863 //
2864 // input : rax,: dividend min_int
2865 // reg: divisor (may not be rax,/rdx) -1
2866 //
2867 // output: rax,: quotient (= rax, idiv reg) min_int
2868 // rdx: remainder (= rax, irem reg) 0
2869 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2870 const int min_int = 0x80000000;
2871 Label normal_case, special_case;
2872
2873 // check for special case
2874 cmpl(rax, min_int);
2875 jcc(Assembler::notEqual, normal_case);
2876 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2877 cmpl(reg, -1);
2878 jcc(Assembler::equal, special_case);
2879
2880 // handle normal case
2881 bind(normal_case);
2882 cdql();
2883 int idivl_offset = offset();
2884 idivl(reg);
2885
2886 // normal and special case exit
2887 bind(special_case);
2888
2889 return idivl_offset;
2890 }
2891
2892
2893
2894 void MacroAssembler::decrementl(Register reg, int value) {
2895 if (value == min_jint) {subl(reg, value) ; return; }
2896 if (value < 0) { incrementl(reg, -value); return; }
2897 if (value == 0) { ; return; }
2898 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2899 /* else */ { subl(reg, value) ; return; }
2900 }
2901
2902 void MacroAssembler::decrementl(Address dst, int value) {
2903 if (value == min_jint) {subl(dst, value) ; return; }
2904 if (value < 0) { incrementl(dst, -value); return; }
2905 if (value == 0) { ; return; }
2906 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2907 /* else */ { subl(dst, value) ; return; }
2908 }
2909
2910 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2911 assert (shift_value > 0, "illegal shift value");
2912 Label _is_positive;
2913 testl (reg, reg);
2914 jcc (Assembler::positive, _is_positive);
2915 int offset = (1 << shift_value) - 1 ;
2916
2917 if (offset == 1) {
2918 incrementl(reg);
2919 } else {
2920 addl(reg, offset);
2921 }
2922
2923 bind (_is_positive);
2924 sarl(reg, shift_value);
2925 }
2926
2927 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2928 if (reachable(src)) {
2929 Assembler::divsd(dst, as_Address(src));
2930 } else {
2931 lea(rscratch1, src);
2932 Assembler::divsd(dst, Address(rscratch1, 0));
2933 }
2934 }
2935
2936 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2937 if (reachable(src)) {
2938 Assembler::divss(dst, as_Address(src));
2939 } else {
2940 lea(rscratch1, src);
2941 Assembler::divss(dst, Address(rscratch1, 0));
2942 }
2943 }
2944
2945 // !defined(COMPILER2) is because of stupid core builds
2946 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
2947 void MacroAssembler::empty_FPU_stack() {
2948 if (VM_Version::supports_mmx()) {
2949 emms();
2950 } else {
2951 for (int i = 8; i-- > 0; ) ffree(i);
2952 }
2953 }
2954 #endif // !LP64 || C1 || !C2
2955
2956
2957 // Defines obj, preserves var_size_in_bytes
2958 void MacroAssembler::eden_allocate(Register obj,
2959 Register var_size_in_bytes,
2960 int con_size_in_bytes,
2961 Register t1,
2962 Label& slow_case) {
2963 assert(obj == rax, "obj must be in rax, for cmpxchg");
2964 assert_different_registers(obj, var_size_in_bytes, t1);
2965 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
2966 jmp(slow_case);
2967 } else {
2968 Register end = t1;
2969 Label retry;
2970 bind(retry);
2971 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2972 movptr(obj, heap_top);
2973 if (var_size_in_bytes == noreg) {
2974 lea(end, Address(obj, con_size_in_bytes));
2975 } else {
2976 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2977 }
2978 // if end < obj then we wrapped around => object too long => slow case
2979 cmpptr(end, obj);
2980 jcc(Assembler::below, slow_case);
2981 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2982 jcc(Assembler::above, slow_case);
2983 // Compare obj with the top addr, and if still equal, store the new top addr in
2984 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2985 // it otherwise. Use lock prefix for atomicity on MPs.
2986 locked_cmpxchgptr(end, heap_top);
2987 jcc(Assembler::notEqual, retry);
2988 }
2989 }
2990
2991 void MacroAssembler::enter() {
2992 push(rbp);
2993 mov(rbp, rsp);
2994 }
2995
2996 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2997 void MacroAssembler::fat_nop() {
2998 if (UseAddressNop) {
2999 addr_nop_5();
3000 } else {
3001 emit_int8(0x26); // es:
3002 emit_int8(0x2e); // cs:
3003 emit_int8(0x64); // fs:
3004 emit_int8(0x65); // gs:
3005 emit_int8((unsigned char)0x90);
3006 }
3007 }
3008
3009 void MacroAssembler::fcmp(Register tmp) {
3010 fcmp(tmp, 1, true, true);
3011 }
3012
3013 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
3014 assert(!pop_right || pop_left, "usage error");
3015 if (VM_Version::supports_cmov()) {
3016 assert(tmp == noreg, "unneeded temp");
3017 if (pop_left) {
3018 fucomip(index);
3019 } else {
3020 fucomi(index);
3021 }
3022 if (pop_right) {
3023 fpop();
3024 }
3025 } else {
3026 assert(tmp != noreg, "need temp");
3027 if (pop_left) {
3028 if (pop_right) {
3029 fcompp();
3030 } else {
3031 fcomp(index);
3032 }
3033 } else {
3034 fcom(index);
3035 }
3036 // convert FPU condition into eflags condition via rax,
3037 save_rax(tmp);
3038 fwait(); fnstsw_ax();
3039 sahf();
3040 restore_rax(tmp);
3041 }
3042 // condition codes set as follows:
3043 //
3044 // CF (corresponds to C0) if x < y
3045 // PF (corresponds to C2) if unordered
3046 // ZF (corresponds to C3) if x = y
3047 }
3048
3049 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3050 fcmp2int(dst, unordered_is_less, 1, true, true);
3051 }
3052
3053 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3054 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3055 Label L;
3056 if (unordered_is_less) {
3057 movl(dst, -1);
3058 jcc(Assembler::parity, L);
3059 jcc(Assembler::below , L);
3060 movl(dst, 0);
3061 jcc(Assembler::equal , L);
3062 increment(dst);
3063 } else { // unordered is greater
3064 movl(dst, 1);
3065 jcc(Assembler::parity, L);
3066 jcc(Assembler::above , L);
3067 movl(dst, 0);
3068 jcc(Assembler::equal , L);
3069 decrementl(dst);
3070 }
3071 bind(L);
3072 }
3073
3074 void MacroAssembler::fld_d(AddressLiteral src) {
3075 fld_d(as_Address(src));
3076 }
3077
3078 void MacroAssembler::fld_s(AddressLiteral src) {
3079 fld_s(as_Address(src));
3080 }
3081
3082 void MacroAssembler::fld_x(AddressLiteral src) {
3083 Assembler::fld_x(as_Address(src));
3084 }
3085
3086 void MacroAssembler::fldcw(AddressLiteral src) {
3087 Assembler::fldcw(as_Address(src));
3088 }
3089
3090 void MacroAssembler::pow_exp_core_encoding() {
3091 // kills rax, rcx, rdx
3092 subptr(rsp,sizeof(jdouble));
3093 // computes 2^X. Stack: X ...
3094 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
3095 // keep it on the thread's stack to compute 2^int(X) later
3096 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
3097 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
3098 fld_s(0); // Stack: X X ...
3099 frndint(); // Stack: int(X) X ...
3100 fsuba(1); // Stack: int(X) X-int(X) ...
3101 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ...
3102 f2xm1(); // Stack: 2^(X-int(X))-1 ...
3103 fld1(); // Stack: 1 2^(X-int(X))-1 ...
3104 faddp(1); // Stack: 2^(X-int(X))
3105 // computes 2^(int(X)): add exponent bias (1023) to int(X), then
3106 // shift int(X)+1023 to exponent position.
3107 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
3108 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
3109 // values so detect them and set result to NaN.
3110 movl(rax,Address(rsp,0));
3111 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
3112 addl(rax, 1023);
3113 movl(rdx,rax);
3114 shll(rax,20);
3115 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
3116 addl(rdx,1);
3117 // Check that 1 < int(X)+1023+1 < 2048
3118 // in 3 steps:
3119 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
3120 // 2- (int(X)+1023+1)&-2048 != 0
3121 // 3- (int(X)+1023+1)&-2048 != 1
3122 // Do 2- first because addl just updated the flags.
3123 cmov32(Assembler::equal,rax,rcx);
3124 cmpl(rdx,1);
3125 cmov32(Assembler::equal,rax,rcx);
3126 testl(rdx,rcx);
3127 cmov32(Assembler::notEqual,rax,rcx);
3128 movl(Address(rsp,4),rax);
3129 movl(Address(rsp,0),0);
3130 fmul_d(Address(rsp,0)); // Stack: 2^X ...
3131 addptr(rsp,sizeof(jdouble));
3132 }
3133
3134 void MacroAssembler::increase_precision() {
3135 subptr(rsp, BytesPerWord);
3136 fnstcw(Address(rsp, 0));
3137 movl(rax, Address(rsp, 0));
3138 orl(rax, 0x300);
3139 push(rax);
3140 fldcw(Address(rsp, 0));
3141 pop(rax);
3142 }
3143
3144 void MacroAssembler::restore_precision() {
3145 fldcw(Address(rsp, 0));
3146 addptr(rsp, BytesPerWord);
3147 }
3148
3149 void MacroAssembler::fast_pow() {
3150 // computes X^Y = 2^(Y * log2(X))
3151 // if fast computation is not possible, result is NaN. Requires
3152 // fallback from user of this macro.
3153 // increase precision for intermediate steps of the computation
3154 BLOCK_COMMENT("fast_pow {");
3155 increase_precision();
3156 fyl2x(); // Stack: (Y*log2(X)) ...
3157 pow_exp_core_encoding(); // Stack: exp(X) ...
3158 restore_precision();
3159 BLOCK_COMMENT("} fast_pow");
3160 }
3161
3162 void MacroAssembler::fast_exp() {
3163 // computes exp(X) = 2^(X * log2(e))
3164 // if fast computation is not possible, result is NaN. Requires
3165 // fallback from user of this macro.
3166 // increase precision for intermediate steps of the computation
3167 increase_precision();
3168 fldl2e(); // Stack: log2(e) X ...
3169 fmulp(1); // Stack: (X*log2(e)) ...
3170 pow_exp_core_encoding(); // Stack: exp(X) ...
3171 restore_precision();
3172 }
3173
3174 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) {
3175 // kills rax, rcx, rdx
3176 // pow and exp needs 2 extra registers on the fpu stack.
3177 Label slow_case, done;
3178 Register tmp = noreg;
3179 if (!VM_Version::supports_cmov()) {
3180 // fcmp needs a temporary so preserve rdx,
3181 tmp = rdx;
3182 }
3183 Register tmp2 = rax;
3184 Register tmp3 = rcx;
3185
3186 if (is_exp) {
3187 // Stack: X
3188 fld_s(0); // duplicate argument for runtime call. Stack: X X
3189 fast_exp(); // Stack: exp(X) X
3190 fcmp(tmp, 0, false, false); // Stack: exp(X) X
3191 // exp(X) not equal to itself: exp(X) is NaN go to slow case.
3192 jcc(Assembler::parity, slow_case);
3193 // get rid of duplicate argument. Stack: exp(X)
3194 if (num_fpu_regs_in_use > 0) {
3195 fxch();
3196 fpop();
3197 } else {
3198 ffree(1);
3199 }
3200 jmp(done);
3201 } else {
3202 // Stack: X Y
3203 Label x_negative, y_not_2;
3204
3205 static double two = 2.0;
3206 ExternalAddress two_addr((address)&two);
3207
3208 // constant maybe too far on 64 bit
3209 lea(tmp2, two_addr);
3210 fld_d(Address(tmp2, 0)); // Stack: 2 X Y
3211 fcmp(tmp, 2, true, false); // Stack: X Y
3212 jcc(Assembler::parity, y_not_2);
3213 jcc(Assembler::notEqual, y_not_2);
3214
3215 fxch(); fpop(); // Stack: X
3216 fmul(0); // Stack: X*X
3217
3218 jmp(done);
3219
3220 bind(y_not_2);
3221
3222 fldz(); // Stack: 0 X Y
3223 fcmp(tmp, 1, true, false); // Stack: X Y
3224 jcc(Assembler::above, x_negative);
3225
3226 // X >= 0
3227
3228 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3229 fld_s(1); // Stack: X Y X Y
3230 fast_pow(); // Stack: X^Y X Y
3231 fcmp(tmp, 0, false, false); // Stack: X^Y X Y
3232 // X^Y not equal to itself: X^Y is NaN go to slow case.
3233 jcc(Assembler::parity, slow_case);
3234 // get rid of duplicate arguments. Stack: X^Y
3235 if (num_fpu_regs_in_use > 0) {
3236 fxch(); fpop();
3237 fxch(); fpop();
3238 } else {
3239 ffree(2);
3240 ffree(1);
3241 }
3242 jmp(done);
3243
3244 // X <= 0
3245 bind(x_negative);
3246
3247 fld_s(1); // Stack: Y X Y
3248 frndint(); // Stack: int(Y) X Y
3249 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
3250 jcc(Assembler::notEqual, slow_case);
3251
3252 subptr(rsp, 8);
3253
3254 // For X^Y, when X < 0, Y has to be an integer and the final
3255 // result depends on whether it's odd or even. We just checked
3256 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit
3257 // integer to test its parity. If int(Y) is huge and doesn't fit
3258 // in the 64 bit integer range, the integer indefinite value will
3259 // end up in the gp registers. Huge numbers are all even, the
3260 // integer indefinite number is even so it's fine.
3261
3262 #ifdef ASSERT
3263 // Let's check we don't end up with an integer indefinite number
3264 // when not expected. First test for huge numbers: check whether
3265 // int(Y)+1 == int(Y) which is true for very large numbers and
3266 // those are all even. A 64 bit integer is guaranteed to not
3267 // overflow for numbers where y+1 != y (when precision is set to
3268 // double precision).
3269 Label y_not_huge;
3270
3271 fld1(); // Stack: 1 int(Y) X Y
3272 fadd(1); // Stack: 1+int(Y) int(Y) X Y
3273
3274 #ifdef _LP64
3275 // trip to memory to force the precision down from double extended
3276 // precision
3277 fstp_d(Address(rsp, 0));
3278 fld_d(Address(rsp, 0));
3279 #endif
3280
3281 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y
3282 #endif
3283
3284 // move int(Y) as 64 bit integer to thread's stack
3285 fistp_d(Address(rsp,0)); // Stack: X Y
3286
3287 #ifdef ASSERT
3288 jcc(Assembler::notEqual, y_not_huge);
3289
3290 // Y is huge so we know it's even. It may not fit in a 64 bit
3291 // integer and we don't want the debug code below to see the
3292 // integer indefinite value so overwrite int(Y) on the thread's
3293 // stack with 0.
3294 movl(Address(rsp, 0), 0);
3295 movl(Address(rsp, 4), 0);
3296
3297 bind(y_not_huge);
3298 #endif
3299
3300 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3301 fld_s(1); // Stack: X Y X Y
3302 fabs(); // Stack: abs(X) Y X Y
3303 fast_pow(); // Stack: abs(X)^Y X Y
3304 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
3305 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
3306
3307 pop(tmp2);
3308 NOT_LP64(pop(tmp3));
3309 jcc(Assembler::parity, slow_case);
3310
3311 #ifdef ASSERT
3312 // Check that int(Y) is not integer indefinite value (int
3313 // overflow). Shouldn't happen because for values that would
3314 // overflow, 1+int(Y)==Y which was tested earlier.
3315 #ifndef _LP64
3316 {
3317 Label integer;
3318 testl(tmp2, tmp2);
3319 jcc(Assembler::notZero, integer);
3320 cmpl(tmp3, 0x80000000);
3321 jcc(Assembler::notZero, integer);
3322 STOP("integer indefinite value shouldn't be seen here");
3323 bind(integer);
3324 }
3325 #else
3326 {
3327 Label integer;
3328 mov(tmp3, tmp2); // preserve tmp2 for parity check below
3329 shlq(tmp3, 1);
3330 jcc(Assembler::carryClear, integer);
3331 jcc(Assembler::notZero, integer);
3332 STOP("integer indefinite value shouldn't be seen here");
3333 bind(integer);
3334 }
3335 #endif
3336 #endif
3337
3338 // get rid of duplicate arguments. Stack: X^Y
3339 if (num_fpu_regs_in_use > 0) {
3340 fxch(); fpop();
3341 fxch(); fpop();
3342 } else {
3343 ffree(2);
3344 ffree(1);
3345 }
3346
3347 testl(tmp2, 1);
3348 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
3349 // X <= 0, Y even: X^Y = -abs(X)^Y
3350
3351 fchs(); // Stack: -abs(X)^Y Y
3352 jmp(done);
3353 }
3354
3355 // slow case: runtime call
3356 bind(slow_case);
3357
3358 fpop(); // pop incorrect result or int(Y)
3359
3360 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow),
3361 is_exp ? 1 : 2, num_fpu_regs_in_use);
3362
3363 // Come here with result in F-TOS
3364 bind(done);
3365 }
3366
3367 void MacroAssembler::fpop() {
3368 ffree();
3369 fincstp();
3370 }
3371
3372 void MacroAssembler::fremr(Register tmp) {
3373 save_rax(tmp);
3374 { Label L;
3375 bind(L);
3376 fprem();
3377 fwait(); fnstsw_ax();
3378 #ifdef _LP64
3379 testl(rax, 0x400);
3380 jcc(Assembler::notEqual, L);
3381 #else
3382 sahf();
3383 jcc(Assembler::parity, L);
3384 #endif // _LP64
3385 }
3386 restore_rax(tmp);
3387 // Result is in ST0.
3388 // Note: fxch & fpop to get rid of ST1
3389 // (otherwise FPU stack could overflow eventually)
3390 fxch(1);
3391 fpop();
3392 }
3393
3394
3395 void MacroAssembler::incrementl(AddressLiteral dst) {
3396 if (reachable(dst)) {
3397 incrementl(as_Address(dst));
3398 } else {
3399 lea(rscratch1, dst);
3400 incrementl(Address(rscratch1, 0));
3401 }
3402 }
3403
3404 void MacroAssembler::incrementl(ArrayAddress dst) {
3405 incrementl(as_Address(dst));
3406 }
3407
3408 void MacroAssembler::incrementl(Register reg, int value) {
3409 if (value == min_jint) {addl(reg, value) ; return; }
3410 if (value < 0) { decrementl(reg, -value); return; }
3411 if (value == 0) { ; return; }
3412 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3413 /* else */ { addl(reg, value) ; return; }
3414 }
3415
3416 void MacroAssembler::incrementl(Address dst, int value) {
3417 if (value == min_jint) {addl(dst, value) ; return; }
3418 if (value < 0) { decrementl(dst, -value); return; }
3419 if (value == 0) { ; return; }
3420 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3421 /* else */ { addl(dst, value) ; return; }
3422 }
3423
3424 void MacroAssembler::jump(AddressLiteral dst) {
3425 if (reachable(dst)) {
3426 jmp_literal(dst.target(), dst.rspec());
3427 } else {
3428 lea(rscratch1, dst);
3429 jmp(rscratch1);
3430 }
3431 }
3432
3433 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3434 if (reachable(dst)) {
3435 InstructionMark im(this);
3436 relocate(dst.reloc());
3437 const int short_size = 2;
3438 const int long_size = 6;
3439 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3440 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3441 // 0111 tttn #8-bit disp
3442 emit_int8(0x70 | cc);
3443 emit_int8((offs - short_size) & 0xFF);
3444 } else {
3445 // 0000 1111 1000 tttn #32-bit disp
3446 emit_int8(0x0F);
3447 emit_int8((unsigned char)(0x80 | cc));
3448 emit_int32(offs - long_size);
3449 }
3450 } else {
3451 #ifdef ASSERT
3452 warning("reversing conditional branch");
3453 #endif /* ASSERT */
3454 Label skip;
3455 jccb(reverse[cc], skip);
3456 lea(rscratch1, dst);
3457 Assembler::jmp(rscratch1);
3458 bind(skip);
3459 }
3460 }
3461
3462 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3463 if (reachable(src)) {
3464 Assembler::ldmxcsr(as_Address(src));
3465 } else {
3466 lea(rscratch1, src);
3467 Assembler::ldmxcsr(Address(rscratch1, 0));
3468 }
3469 }
3470
3471 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3472 int off;
3473 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3474 off = offset();
3475 movsbl(dst, src); // movsxb
3476 } else {
3477 off = load_unsigned_byte(dst, src);
3478 shll(dst, 24);
3479 sarl(dst, 24);
3480 }
3481 return off;
3482 }
3483
3484 // Note: load_signed_short used to be called load_signed_word.
3485 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3486 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3487 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3488 int MacroAssembler::load_signed_short(Register dst, Address src) {
3489 int off;
3490 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3491 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3492 // version but this is what 64bit has always done. This seems to imply
3493 // that users are only using 32bits worth.
3494 off = offset();
3495 movswl(dst, src); // movsxw
3496 } else {
3497 off = load_unsigned_short(dst, src);
3498 shll(dst, 16);
3499 sarl(dst, 16);
3500 }
3501 return off;
3502 }
3503
3504 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3505 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3506 // and "3.9 Partial Register Penalties", p. 22).
3507 int off;
3508 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3509 off = offset();
3510 movzbl(dst, src); // movzxb
3511 } else {
3512 xorl(dst, dst);
3513 off = offset();
3514 movb(dst, src);
3515 }
3516 return off;
3517 }
3518
3519 // Note: load_unsigned_short used to be called load_unsigned_word.
3520 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3521 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3522 // and "3.9 Partial Register Penalties", p. 22).
3523 int off;
3524 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3525 off = offset();
3526 movzwl(dst, src); // movzxw
3527 } else {
3528 xorl(dst, dst);
3529 off = offset();
3530 movw(dst, src);
3531 }
3532 return off;
3533 }
3534
3535 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3536 switch (size_in_bytes) {
3537 #ifndef _LP64
3538 case 8:
3539 assert(dst2 != noreg, "second dest register required");
3540 movl(dst, src);
3541 movl(dst2, src.plus_disp(BytesPerInt));
3542 break;
3543 #else
3544 case 8: movq(dst, src); break;
3545 #endif
3546 case 4: movl(dst, src); break;
3547 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3548 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3549 default: ShouldNotReachHere();
3550 }
3551 }
3552
3553 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3554 switch (size_in_bytes) {
3555 #ifndef _LP64
3556 case 8:
3557 assert(src2 != noreg, "second source register required");
3558 movl(dst, src);
3559 movl(dst.plus_disp(BytesPerInt), src2);
3560 break;
3561 #else
3562 case 8: movq(dst, src); break;
3563 #endif
3564 case 4: movl(dst, src); break;
3565 case 2: movw(dst, src); break;
3566 case 1: movb(dst, src); break;
3567 default: ShouldNotReachHere();
3568 }
3569 }
3570
3571 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3572 if (reachable(dst)) {
3573 movl(as_Address(dst), src);
3574 } else {
3575 lea(rscratch1, dst);
3576 movl(Address(rscratch1, 0), src);
3577 }
3578 }
3579
3580 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3581 if (reachable(src)) {
3582 movl(dst, as_Address(src));
3583 } else {
3584 lea(rscratch1, src);
3585 movl(dst, Address(rscratch1, 0));
3586 }
3587 }
3588
3589 // C++ bool manipulation
3590
3591 void MacroAssembler::movbool(Register dst, Address src) {
3592 if(sizeof(bool) == 1)
3593 movb(dst, src);
3594 else if(sizeof(bool) == 2)
3595 movw(dst, src);
3596 else if(sizeof(bool) == 4)
3597 movl(dst, src);
3598 else
3599 // unsupported
3600 ShouldNotReachHere();
3601 }
3602
3603 void MacroAssembler::movbool(Address dst, bool boolconst) {
3604 if(sizeof(bool) == 1)
3605 movb(dst, (int) boolconst);
3606 else if(sizeof(bool) == 2)
3607 movw(dst, (int) boolconst);
3608 else if(sizeof(bool) == 4)
3609 movl(dst, (int) boolconst);
3610 else
3611 // unsupported
3612 ShouldNotReachHere();
3613 }
3614
3615 void MacroAssembler::movbool(Address dst, Register src) {
3616 if(sizeof(bool) == 1)
3617 movb(dst, src);
3618 else if(sizeof(bool) == 2)
3619 movw(dst, src);
3620 else if(sizeof(bool) == 4)
3621 movl(dst, src);
3622 else
3623 // unsupported
3624 ShouldNotReachHere();
3625 }
3626
3627 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3628 movb(as_Address(dst), src);
3629 }
3630
3631 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3632 if (reachable(src)) {
3633 movdl(dst, as_Address(src));
3634 } else {
3635 lea(rscratch1, src);
3636 movdl(dst, Address(rscratch1, 0));
3637 }
3638 }
3639
3640 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3641 if (reachable(src)) {
3642 movq(dst, as_Address(src));
3643 } else {
3644 lea(rscratch1, src);
3645 movq(dst, Address(rscratch1, 0));
3646 }
3647 }
3648
3649 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3650 if (reachable(src)) {
3651 if (UseXmmLoadAndClearUpper) {
3652 movsd (dst, as_Address(src));
3653 } else {
3654 movlpd(dst, as_Address(src));
3655 }
3656 } else {
3657 lea(rscratch1, src);
3658 if (UseXmmLoadAndClearUpper) {
3659 movsd (dst, Address(rscratch1, 0));
3660 } else {
3661 movlpd(dst, Address(rscratch1, 0));
3662 }
3663 }
3664 }
3665
3666 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3667 if (reachable(src)) {
3668 movss(dst, as_Address(src));
3669 } else {
3670 lea(rscratch1, src);
3671 movss(dst, Address(rscratch1, 0));
3672 }
3673 }
3674
3675 void MacroAssembler::movptr(Register dst, Register src) {
3676 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3677 }
3678
3679 void MacroAssembler::movptr(Register dst, Address src) {
3680 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3681 }
3682
3683 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3684 void MacroAssembler::movptr(Register dst, intptr_t src) {
3685 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3686 }
3687
3688 void MacroAssembler::movptr(Address dst, Register src) {
3689 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3690 }
3691
3692 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3693 if (reachable(src)) {
3694 Assembler::movdqu(dst, as_Address(src));
3695 } else {
3696 lea(rscratch1, src);
3697 Assembler::movdqu(dst, Address(rscratch1, 0));
3698 }
3699 }
3700
3701 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3702 if (reachable(src)) {
3703 Assembler::movdqa(dst, as_Address(src));
3704 } else {
3705 lea(rscratch1, src);
3706 Assembler::movdqa(dst, Address(rscratch1, 0));
3707 }
3708 }
3709
3710 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3711 if (reachable(src)) {
3712 Assembler::movsd(dst, as_Address(src));
3713 } else {
3714 lea(rscratch1, src);
3715 Assembler::movsd(dst, Address(rscratch1, 0));
3716 }
3717 }
3718
3719 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3720 if (reachable(src)) {
3721 Assembler::movss(dst, as_Address(src));
3722 } else {
3723 lea(rscratch1, src);
3724 Assembler::movss(dst, Address(rscratch1, 0));
3725 }
3726 }
3727
3728 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3729 if (reachable(src)) {
3730 Assembler::mulsd(dst, as_Address(src));
3731 } else {
3732 lea(rscratch1, src);
3733 Assembler::mulsd(dst, Address(rscratch1, 0));
3734 }
3735 }
3736
3737 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3738 if (reachable(src)) {
3739 Assembler::mulss(dst, as_Address(src));
3740 } else {
3741 lea(rscratch1, src);
3742 Assembler::mulss(dst, Address(rscratch1, 0));
3743 }
3744 }
3745
3746 void MacroAssembler::null_check(Register reg, int offset) {
3747 if (needs_explicit_null_check(offset)) {
3748 // provoke OS NULL exception if reg = NULL by
3749 // accessing M[reg] w/o changing any (non-CC) registers
3750 // NOTE: cmpl is plenty here to provoke a segv
3751 cmpptr(rax, Address(reg, 0));
3752 // Note: should probably use testl(rax, Address(reg, 0));
3753 // may be shorter code (however, this version of
3754 // testl needs to be implemented first)
3755 } else {
3756 // nothing to do, (later) access of M[reg + offset]
3757 // will provoke OS NULL exception if reg = NULL
3758 }
3759 }
3760
3761 void MacroAssembler::os_breakpoint() {
3762 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3763 // (e.g., MSVC can't call ps() otherwise)
3764 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3765 }
3766
3767 void MacroAssembler::pop_CPU_state() {
3768 pop_FPU_state();
3769 pop_IU_state();
3770 }
3771
3772 void MacroAssembler::pop_FPU_state() {
3773 NOT_LP64(frstor(Address(rsp, 0));)
3774 LP64_ONLY(fxrstor(Address(rsp, 0));)
3775 addptr(rsp, FPUStateSizeInWords * wordSize);
3776 }
3777
3778 void MacroAssembler::pop_IU_state() {
3779 popa();
3780 LP64_ONLY(addq(rsp, 8));
3781 popf();
3782 }
3783
3784 // Save Integer and Float state
3785 // Warning: Stack must be 16 byte aligned (64bit)
3786 void MacroAssembler::push_CPU_state() {
3787 push_IU_state();
3788 push_FPU_state();
3789 }
3790
3791 void MacroAssembler::push_FPU_state() {
3792 subptr(rsp, FPUStateSizeInWords * wordSize);
3793 #ifndef _LP64
3794 fnsave(Address(rsp, 0));
3795 fwait();
3796 #else
3797 fxsave(Address(rsp, 0));
3798 #endif // LP64
3799 }
3800
3801 void MacroAssembler::push_IU_state() {
3802 // Push flags first because pusha kills them
3803 pushf();
3804 // Make sure rsp stays 16-byte aligned
3805 LP64_ONLY(subq(rsp, 8));
3806 pusha();
3807 }
3808
3809 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) {
3810 // determine java_thread register
3811 if (!java_thread->is_valid()) {
3812 java_thread = rdi;
3813 get_thread(java_thread);
3814 }
3815 // we must set sp to zero to clear frame
3816 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3817 if (clear_fp) {
3818 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3819 }
3820
3821 // Always clear the pc because it could have been set by make_walkable()
3822 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3823
3824 }
3825
3826 void MacroAssembler::restore_rax(Register tmp) {
3827 if (tmp == noreg) pop(rax);
3828 else if (tmp != rax) mov(rax, tmp);
3829 }
3830
3831 void MacroAssembler::round_to(Register reg, int modulus) {
3832 addptr(reg, modulus - 1);
3833 andptr(reg, -modulus);
3834 }
3835
3836 void MacroAssembler::save_rax(Register tmp) {
3837 if (tmp == noreg) push(rax);
3838 else if (tmp != rax) mov(tmp, rax);
3839 }
3840
3841 // Write serialization page so VM thread can do a pseudo remote membar.
3842 // We use the current thread pointer to calculate a thread specific
3843 // offset to write to within the page. This minimizes bus traffic
3844 // due to cache line collision.
3845 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3846 movl(tmp, thread);
3847 shrl(tmp, os::get_serialize_page_shift_count());
3848 andl(tmp, (os::vm_page_size() - sizeof(int)));
3849
3850 Address index(noreg, tmp, Address::times_1);
3851 ExternalAddress page(os::get_memory_serialize_page());
3852
3853 // Size of store must match masking code above
3854 movl(as_Address(ArrayAddress(page, index)), tmp);
3855 }
3856
3857 // Calls to C land
3858 //
3859 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3860 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3861 // has to be reset to 0. This is required to allow proper stack traversal.
3862 void MacroAssembler::set_last_Java_frame(Register java_thread,
3863 Register last_java_sp,
3864 Register last_java_fp,
3865 address last_java_pc) {
3866 // determine java_thread register
3867 if (!java_thread->is_valid()) {
3868 java_thread = rdi;
3869 get_thread(java_thread);
3870 }
3871 // determine last_java_sp register
3872 if (!last_java_sp->is_valid()) {
3873 last_java_sp = rsp;
3874 }
3875
3876 // last_java_fp is optional
3877
3878 if (last_java_fp->is_valid()) {
3879 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3880 }
3881
3882 // last_java_pc is optional
3883
3884 if (last_java_pc != NULL) {
3885 lea(Address(java_thread,
3886 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3887 InternalAddress(last_java_pc));
3888
3889 }
3890 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3891 }
3892
3893 void MacroAssembler::shlptr(Register dst, int imm8) {
3894 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3895 }
3896
3897 void MacroAssembler::shrptr(Register dst, int imm8) {
3898 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3899 }
3900
3901 void MacroAssembler::sign_extend_byte(Register reg) {
3902 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3903 movsbl(reg, reg); // movsxb
3904 } else {
3905 shll(reg, 24);
3906 sarl(reg, 24);
3907 }
3908 }
3909
3910 void MacroAssembler::sign_extend_short(Register reg) {
3911 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3912 movswl(reg, reg); // movsxw
3913 } else {
3914 shll(reg, 16);
3915 sarl(reg, 16);
3916 }
3917 }
3918
3919 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3920 assert(reachable(src), "Address should be reachable");
3921 testl(dst, as_Address(src));
3922 }
3923
3924 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3925 if (reachable(src)) {
3926 Assembler::sqrtsd(dst, as_Address(src));
3927 } else {
3928 lea(rscratch1, src);
3929 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3930 }
3931 }
3932
3933 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3934 if (reachable(src)) {
3935 Assembler::sqrtss(dst, as_Address(src));
3936 } else {
3937 lea(rscratch1, src);
3938 Assembler::sqrtss(dst, Address(rscratch1, 0));
3939 }
3940 }
3941
3942 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3943 if (reachable(src)) {
3944 Assembler::subsd(dst, as_Address(src));
3945 } else {
3946 lea(rscratch1, src);
3947 Assembler::subsd(dst, Address(rscratch1, 0));
3948 }
3949 }
3950
3951 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3952 if (reachable(src)) {
3953 Assembler::subss(dst, as_Address(src));
3954 } else {
3955 lea(rscratch1, src);
3956 Assembler::subss(dst, Address(rscratch1, 0));
3957 }
3958 }
3959
3960 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3961 if (reachable(src)) {
3962 Assembler::ucomisd(dst, as_Address(src));
3963 } else {
3964 lea(rscratch1, src);
3965 Assembler::ucomisd(dst, Address(rscratch1, 0));
3966 }
3967 }
3968
3969 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3970 if (reachable(src)) {
3971 Assembler::ucomiss(dst, as_Address(src));
3972 } else {
3973 lea(rscratch1, src);
3974 Assembler::ucomiss(dst, Address(rscratch1, 0));
3975 }
3976 }
3977
3978 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3979 // Used in sign-bit flipping with aligned address.
3980 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3981 if (reachable(src)) {
3982 Assembler::xorpd(dst, as_Address(src));
3983 } else {
3984 lea(rscratch1, src);
3985 Assembler::xorpd(dst, Address(rscratch1, 0));
3986 }
3987 }
3988
3989 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
3990 // Used in sign-bit flipping with aligned address.
3991 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3992 if (reachable(src)) {
3993 Assembler::xorps(dst, as_Address(src));
3994 } else {
3995 lea(rscratch1, src);
3996 Assembler::xorps(dst, Address(rscratch1, 0));
3997 }
3998 }
3999
4000 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4001 // Used in sign-bit flipping with aligned address.
4002 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4003 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4004 if (reachable(src)) {
4005 Assembler::pshufb(dst, as_Address(src));
4006 } else {
4007 lea(rscratch1, src);
4008 Assembler::pshufb(dst, Address(rscratch1, 0));
4009 }
4010 }
4011
4012 // AVX 3-operands instructions
4013
4014 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4015 if (reachable(src)) {
4016 vaddsd(dst, nds, as_Address(src));
4017 } else {
4018 lea(rscratch1, src);
4019 vaddsd(dst, nds, Address(rscratch1, 0));
4020 }
4021 }
4022
4023 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4024 if (reachable(src)) {
4025 vaddss(dst, nds, as_Address(src));
4026 } else {
4027 lea(rscratch1, src);
4028 vaddss(dst, nds, Address(rscratch1, 0));
4029 }
4030 }
4031
4032 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4033 if (reachable(src)) {
4034 vandpd(dst, nds, as_Address(src), vector256);
4035 } else {
4036 lea(rscratch1, src);
4037 vandpd(dst, nds, Address(rscratch1, 0), vector256);
4038 }
4039 }
4040
4041 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4042 if (reachable(src)) {
4043 vandps(dst, nds, as_Address(src), vector256);
4044 } else {
4045 lea(rscratch1, src);
4046 vandps(dst, nds, Address(rscratch1, 0), vector256);
4047 }
4048 }
4049
4050 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4051 if (reachable(src)) {
4052 vdivsd(dst, nds, as_Address(src));
4053 } else {
4054 lea(rscratch1, src);
4055 vdivsd(dst, nds, Address(rscratch1, 0));
4056 }
4057 }
4058
4059 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4060 if (reachable(src)) {
4061 vdivss(dst, nds, as_Address(src));
4062 } else {
4063 lea(rscratch1, src);
4064 vdivss(dst, nds, Address(rscratch1, 0));
4065 }
4066 }
4067
4068 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4069 if (reachable(src)) {
4070 vmulsd(dst, nds, as_Address(src));
4071 } else {
4072 lea(rscratch1, src);
4073 vmulsd(dst, nds, Address(rscratch1, 0));
4074 }
4075 }
4076
4077 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4078 if (reachable(src)) {
4079 vmulss(dst, nds, as_Address(src));
4080 } else {
4081 lea(rscratch1, src);
4082 vmulss(dst, nds, Address(rscratch1, 0));
4083 }
4084 }
4085
4086 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4087 if (reachable(src)) {
4088 vsubsd(dst, nds, as_Address(src));
4089 } else {
4090 lea(rscratch1, src);
4091 vsubsd(dst, nds, Address(rscratch1, 0));
4092 }
4093 }
4094
4095 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4096 if (reachable(src)) {
4097 vsubss(dst, nds, as_Address(src));
4098 } else {
4099 lea(rscratch1, src);
4100 vsubss(dst, nds, Address(rscratch1, 0));
4101 }
4102 }
4103
4104 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4105 if (reachable(src)) {
4106 vxorpd(dst, nds, as_Address(src), vector256);
4107 } else {
4108 lea(rscratch1, src);
4109 vxorpd(dst, nds, Address(rscratch1, 0), vector256);
4110 }
4111 }
4112
4113 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4114 if (reachable(src)) {
4115 vxorps(dst, nds, as_Address(src), vector256);
4116 } else {
4117 lea(rscratch1, src);
4118 vxorps(dst, nds, Address(rscratch1, 0), vector256);
4119 }
4120 }
4121
4122 void MacroAssembler::resolve_jobject(Register value,
4123 Register thread,
4124 Register tmp) {
4125 assert_different_registers(value, thread, tmp);
4126 Label done, not_weak;
4127 testptr(value, value);
4128 jcc(Assembler::zero, done); // Use NULL as-is.
4129 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
4130 jcc(Assembler::zero, not_weak);
4131 // Resolve jweak.
4132 movptr(value, Address(value, -JNIHandles::weak_tag_value));
4133 verify_oop(value);
4134 #if INCLUDE_ALL_GCS
4135 if (UseG1GC) {
4136 g1_write_barrier_pre(noreg /* obj */,
4137 value /* pre_val */,
4138 thread /* thread */,
4139 tmp /* tmp */,
4140 true /* tosca_live */,
4141 true /* expand_call */);
4142 }
4143 #endif // INCLUDE_ALL_GCS
4144 jmp(done);
4145 bind(not_weak);
4146 // Resolve (untagged) jobject.
4147 movptr(value, Address(value, 0));
4148 verify_oop(value);
4149 bind(done);
4150 }
4151
4152 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
4153 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
4154 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
4155 // The inverted mask is sign-extended
4156 andptr(possibly_jweak, inverted_jweak_mask);
4157 }
4158
4159 //////////////////////////////////////////////////////////////////////////////////
4160 #if INCLUDE_ALL_GCS
4161
4162 void MacroAssembler::g1_write_barrier_pre(Register obj,
4163 Register pre_val,
4164 Register thread,
4165 Register tmp,
4166 bool tosca_live,
4167 bool expand_call) {
4168
4169 // If expand_call is true then we expand the call_VM_leaf macro
4170 // directly to skip generating the check by
4171 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
4172
4173 #ifdef _LP64
4174 assert(thread == r15_thread, "must be");
4175 #endif // _LP64
4176
4177 Label done;
4178 Label runtime;
4179
4180 assert(pre_val != noreg, "check this code");
4181
4182 if (obj != noreg) {
4183 assert_different_registers(obj, pre_val, tmp);
4184 assert(pre_val != rax, "check this code");
4185 }
4186
4187 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4188 PtrQueue::byte_offset_of_active()));
4189 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4190 PtrQueue::byte_offset_of_index()));
4191 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4192 PtrQueue::byte_offset_of_buf()));
4193
4194
4195 // Is marking active?
4196 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4197 cmpl(in_progress, 0);
4198 } else {
4199 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
4200 cmpb(in_progress, 0);
4201 }
4202 jcc(Assembler::equal, done);
4203
4204 // Do we need to load the previous value?
4205 if (obj != noreg) {
4206 load_heap_oop(pre_val, Address(obj, 0));
4207 }
4208
4209 // Is the previous value null?
4210 cmpptr(pre_val, (int32_t) NULL_WORD);
4211 jcc(Assembler::equal, done);
4212
4213 // Can we store original value in the thread's buffer?
4214 // Is index == 0?
4215 // (The index field is typed as size_t.)
4216
4217 movptr(tmp, index); // tmp := *index_adr
4218 cmpptr(tmp, 0); // tmp == 0?
4219 jcc(Assembler::equal, runtime); // If yes, goto runtime
4220
4221 subptr(tmp, wordSize); // tmp := tmp - wordSize
4222 movptr(index, tmp); // *index_adr := tmp
4223 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
4224
4225 // Record the previous value
4226 movptr(Address(tmp, 0), pre_val);
4227 jmp(done);
4228
4229 bind(runtime);
4230 // save the live input values
4231 if(tosca_live) push(rax);
4232
4233 if (obj != noreg && obj != rax)
4234 push(obj);
4235
4236 if (pre_val != rax)
4237 push(pre_val);
4238
4239 // Calling the runtime using the regular call_VM_leaf mechanism generates
4240 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
4241 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
4242 //
4243 // If we care generating the pre-barrier without a frame (e.g. in the
4244 // intrinsified Reference.get() routine) then ebp might be pointing to
4245 // the caller frame and so this check will most likely fail at runtime.
4246 //
4247 // Expanding the call directly bypasses the generation of the check.
4248 // So when we do not have have a full interpreter frame on the stack
4249 // expand_call should be passed true.
4250
4251 NOT_LP64( push(thread); )
4252
4253 if (expand_call) {
4254 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
4255 pass_arg1(this, thread);
4256 pass_arg0(this, pre_val);
4257 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
4258 } else {
4259 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
4260 }
4261
4262 NOT_LP64( pop(thread); )
4263
4264 // save the live input values
4265 if (pre_val != rax)
4266 pop(pre_val);
4267
4268 if (obj != noreg && obj != rax)
4269 pop(obj);
4270
4271 if(tosca_live) pop(rax);
4272
4273 bind(done);
4274 }
4275
4276 void MacroAssembler::g1_write_barrier_post(Register store_addr,
4277 Register new_val,
4278 Register thread,
4279 Register tmp,
4280 Register tmp2) {
4281 #ifdef _LP64
4282 assert(thread == r15_thread, "must be");
4283 #endif // _LP64
4284
4285 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4286 PtrQueue::byte_offset_of_index()));
4287 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4288 PtrQueue::byte_offset_of_buf()));
4289
4290 BarrierSet* bs = Universe::heap()->barrier_set();
4291 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
4292 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4293
4294 Label done;
4295 Label runtime;
4296
4297 // Does store cross heap regions?
4298
4299 movptr(tmp, store_addr);
4300 xorptr(tmp, new_val);
4301 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
4302 jcc(Assembler::equal, done);
4303
4304 // crosses regions, storing NULL?
4305
4306 cmpptr(new_val, (int32_t) NULL_WORD);
4307 jcc(Assembler::equal, done);
4308
4309 // storing region crossing non-NULL, is card already dirty?
4310
4311 const Register card_addr = tmp;
4312 const Register cardtable = tmp2;
4313
4314 movptr(card_addr, store_addr);
4315 shrptr(card_addr, CardTableModRefBS::card_shift);
4316 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
4317 // a valid address and therefore is not properly handled by the relocation code.
4318 movptr(cardtable, (intptr_t)ct->byte_map_base);
4319 addptr(card_addr, cardtable);
4320
4321 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
4322 jcc(Assembler::equal, done);
4323
4324 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4325 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4326 jcc(Assembler::equal, done);
4327
4328
4329 // storing a region crossing, non-NULL oop, card is clean.
4330 // dirty card and log.
4331
4332 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4333
4334 cmpl(queue_index, 0);
4335 jcc(Assembler::equal, runtime);
4336 subl(queue_index, wordSize);
4337 movptr(tmp2, buffer);
4338 #ifdef _LP64
4339 movslq(rscratch1, queue_index);
4340 addq(tmp2, rscratch1);
4341 movq(Address(tmp2, 0), card_addr);
4342 #else
4343 addl(tmp2, queue_index);
4344 movl(Address(tmp2, 0), card_addr);
4345 #endif
4346 jmp(done);
4347
4348 bind(runtime);
4349 // save the live input values
4350 push(store_addr);
4351 push(new_val);
4352 #ifdef _LP64
4353 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
4354 #else
4355 push(thread);
4356 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
4357 pop(thread);
4358 #endif
4359 pop(new_val);
4360 pop(store_addr);
4361
4362 bind(done);
4363 }
4364
4365 #endif // INCLUDE_ALL_GCS
4366 //////////////////////////////////////////////////////////////////////////////////
4367
4368
4369 void MacroAssembler::store_check(Register obj) {
4370 // Does a store check for the oop in register obj. The content of
4371 // register obj is destroyed afterwards.
4372 store_check_part_1(obj);
4373 store_check_part_2(obj);
4374 }
4375
4376 void MacroAssembler::store_check(Register obj, Address dst) {
4377 store_check(obj);
4378 }
4379
4380
4381 // split the store check operation so that other instructions can be scheduled inbetween
4382 void MacroAssembler::store_check_part_1(Register obj) {
4383 BarrierSet* bs = Universe::heap()->barrier_set();
4384 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4385 shrptr(obj, CardTableModRefBS::card_shift);
4386 }
4387
4388 void MacroAssembler::store_check_part_2(Register obj) {
4389 BarrierSet* bs = Universe::heap()->barrier_set();
4390 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4391 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
4392 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4393
4394 // The calculation for byte_map_base is as follows:
4395 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
4396 // So this essentially converts an address to a displacement and it will
4397 // never need to be relocated. On 64bit however the value may be too
4398 // large for a 32bit displacement.
4399 intptr_t disp = (intptr_t) ct->byte_map_base;
4400 if (is_simm32(disp)) {
4401 Address cardtable(noreg, obj, Address::times_1, disp);
4402 movb(cardtable, 0);
4403 } else {
4404 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
4405 // displacement and done in a single instruction given favorable mapping and a
4406 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
4407 // entry and that entry is not properly handled by the relocation code.
4408 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
4409 Address index(noreg, obj, Address::times_1);
4410 movb(as_Address(ArrayAddress(cardtable, index)), 0);
4411 }
4412 }
4413
4414 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4415 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4416 }
4417
4418 // Force generation of a 4 byte immediate value even if it fits into 8bit
4419 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4420 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4421 }
4422
4423 void MacroAssembler::subptr(Register dst, Register src) {
4424 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4425 }
4426
4427 // C++ bool manipulation
4428 void MacroAssembler::testbool(Register dst) {
4429 if(sizeof(bool) == 1)
4430 testb(dst, 0xff);
4431 else if(sizeof(bool) == 2) {
4432 // testw implementation needed for two byte bools
4433 ShouldNotReachHere();
4434 } else if(sizeof(bool) == 4)
4435 testl(dst, dst);
4436 else
4437 // unsupported
4438 ShouldNotReachHere();
4439 }
4440
4441 void MacroAssembler::testptr(Register dst, Register src) {
4442 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4443 }
4444
4445 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4446 void MacroAssembler::tlab_allocate(Register obj,
4447 Register var_size_in_bytes,
4448 int con_size_in_bytes,
4449 Register t1,
4450 Register t2,
4451 Label& slow_case) {
4452 assert_different_registers(obj, t1, t2);
4453 assert_different_registers(obj, var_size_in_bytes, t1);
4454 Register end = t2;
4455 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
4456
4457 verify_tlab();
4458
4459 NOT_LP64(get_thread(thread));
4460
4461 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
4462 if (var_size_in_bytes == noreg) {
4463 lea(end, Address(obj, con_size_in_bytes));
4464 } else {
4465 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
4466 }
4467 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
4468 jcc(Assembler::above, slow_case);
4469
4470 // update the tlab top pointer
4471 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
4472
4473 // recover var_size_in_bytes if necessary
4474 if (var_size_in_bytes == end) {
4475 subptr(var_size_in_bytes, obj);
4476 }
4477 verify_tlab();
4478 }
4479
4480 // Preserves rbx, and rdx.
4481 Register MacroAssembler::tlab_refill(Label& retry,
4482 Label& try_eden,
4483 Label& slow_case) {
4484 Register top = rax;
4485 Register t1 = rcx;
4486 Register t2 = rsi;
4487 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
4488 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
4489 Label do_refill, discard_tlab;
4490
4491 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
4492 // No allocation in the shared eden.
4493 jmp(slow_case);
4494 }
4495
4496 NOT_LP64(get_thread(thread_reg));
4497
4498 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4499 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4500
4501 // calculate amount of free space
4502 subptr(t1, top);
4503 shrptr(t1, LogHeapWordSize);
4504
4505 // Retain tlab and allocate object in shared space if
4506 // the amount free in the tlab is too large to discard.
4507 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
4508 jcc(Assembler::lessEqual, discard_tlab);
4509
4510 // Retain
4511 // %%% yuck as movptr...
4512 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
4513 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
4514 if (TLABStats) {
4515 // increment number of slow_allocations
4516 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
4517 }
4518 jmp(try_eden);
4519
4520 bind(discard_tlab);
4521 if (TLABStats) {
4522 // increment number of refills
4523 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
4524 // accumulate wastage -- t1 is amount free in tlab
4525 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
4526 }
4527
4528 // if tlab is currently allocated (top or end != null) then
4529 // fill [top, end + alignment_reserve) with array object
4530 testptr(top, top);
4531 jcc(Assembler::zero, do_refill);
4532
4533 // set up the mark word
4534 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
4535 // set the length to the remaining space
4536 subptr(t1, typeArrayOopDesc::header_size(T_INT));
4537 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
4538 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
4539 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
4540 // set klass to intArrayKlass
4541 // dubious reloc why not an oop reloc?
4542 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
4543 // store klass last. concurrent gcs assumes klass length is valid if
4544 // klass field is not null.
4545 store_klass(top, t1);
4546
4547 movptr(t1, top);
4548 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4549 incr_allocated_bytes(thread_reg, t1, 0);
4550
4551 // refill the tlab with an eden allocation
4552 bind(do_refill);
4553 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4554 shlptr(t1, LogHeapWordSize);
4555 // allocate new tlab, address returned in top
4556 eden_allocate(top, t1, 0, t2, slow_case);
4557
4558 // Check that t1 was preserved in eden_allocate.
4559 #ifdef ASSERT
4560 if (UseTLAB) {
4561 Label ok;
4562 Register tsize = rsi;
4563 assert_different_registers(tsize, thread_reg, t1);
4564 push(tsize);
4565 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4566 shlptr(tsize, LogHeapWordSize);
4567 cmpptr(t1, tsize);
4568 jcc(Assembler::equal, ok);
4569 STOP("assert(t1 != tlab size)");
4570 should_not_reach_here();
4571
4572 bind(ok);
4573 pop(tsize);
4574 }
4575 #endif
4576 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
4577 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
4578 addptr(top, t1);
4579 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
4580 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
4581 verify_tlab();
4582 jmp(retry);
4583
4584 return thread_reg; // for use by caller
4585 }
4586
4587 void MacroAssembler::incr_allocated_bytes(Register thread,
4588 Register var_size_in_bytes,
4589 int con_size_in_bytes,
4590 Register t1) {
4591 if (!thread->is_valid()) {
4592 #ifdef _LP64
4593 thread = r15_thread;
4594 #else
4595 assert(t1->is_valid(), "need temp reg");
4596 thread = t1;
4597 get_thread(thread);
4598 #endif
4599 }
4600
4601 #ifdef _LP64
4602 if (var_size_in_bytes->is_valid()) {
4603 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4604 } else {
4605 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4606 }
4607 #else
4608 if (var_size_in_bytes->is_valid()) {
4609 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4610 } else {
4611 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4612 }
4613 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
4614 #endif
4615 }
4616
4617 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
4618 pusha();
4619
4620 // if we are coming from c1, xmm registers may be live
4621 int off = 0;
4622 if (UseSSE == 1) {
4623 subptr(rsp, sizeof(jdouble)*8);
4624 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0);
4625 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1);
4626 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2);
4627 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3);
4628 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4);
4629 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5);
4630 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6);
4631 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7);
4632 } else if (UseSSE >= 2) {
4633 #ifdef COMPILER2
4634 if (MaxVectorSize > 16) {
4635 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
4636 // Save upper half of YMM registes
4637 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4638 vextractf128h(Address(rsp, 0),xmm0);
4639 vextractf128h(Address(rsp, 16),xmm1);
4640 vextractf128h(Address(rsp, 32),xmm2);
4641 vextractf128h(Address(rsp, 48),xmm3);
4642 vextractf128h(Address(rsp, 64),xmm4);
4643 vextractf128h(Address(rsp, 80),xmm5);
4644 vextractf128h(Address(rsp, 96),xmm6);
4645 vextractf128h(Address(rsp,112),xmm7);
4646 #ifdef _LP64
4647 vextractf128h(Address(rsp,128),xmm8);
4648 vextractf128h(Address(rsp,144),xmm9);
4649 vextractf128h(Address(rsp,160),xmm10);
4650 vextractf128h(Address(rsp,176),xmm11);
4651 vextractf128h(Address(rsp,192),xmm12);
4652 vextractf128h(Address(rsp,208),xmm13);
4653 vextractf128h(Address(rsp,224),xmm14);
4654 vextractf128h(Address(rsp,240),xmm15);
4655 #endif
4656 }
4657 #endif
4658 // Save whole 128bit (16 bytes) XMM regiters
4659 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4660 movdqu(Address(rsp,off++*16),xmm0);
4661 movdqu(Address(rsp,off++*16),xmm1);
4662 movdqu(Address(rsp,off++*16),xmm2);
4663 movdqu(Address(rsp,off++*16),xmm3);
4664 movdqu(Address(rsp,off++*16),xmm4);
4665 movdqu(Address(rsp,off++*16),xmm5);
4666 movdqu(Address(rsp,off++*16),xmm6);
4667 movdqu(Address(rsp,off++*16),xmm7);
4668 #ifdef _LP64
4669 movdqu(Address(rsp,off++*16),xmm8);
4670 movdqu(Address(rsp,off++*16),xmm9);
4671 movdqu(Address(rsp,off++*16),xmm10);
4672 movdqu(Address(rsp,off++*16),xmm11);
4673 movdqu(Address(rsp,off++*16),xmm12);
4674 movdqu(Address(rsp,off++*16),xmm13);
4675 movdqu(Address(rsp,off++*16),xmm14);
4676 movdqu(Address(rsp,off++*16),xmm15);
4677 #endif
4678 }
4679
4680 // Preserve registers across runtime call
4681 int incoming_argument_and_return_value_offset = -1;
4682 if (num_fpu_regs_in_use > 1) {
4683 // Must preserve all other FPU regs (could alternatively convert
4684 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
4685 // FPU state, but can not trust C compiler)
4686 NEEDS_CLEANUP;
4687 // NOTE that in this case we also push the incoming argument(s) to
4688 // the stack and restore it later; we also use this stack slot to
4689 // hold the return value from dsin, dcos etc.
4690 for (int i = 0; i < num_fpu_regs_in_use; i++) {
4691 subptr(rsp, sizeof(jdouble));
4692 fstp_d(Address(rsp, 0));
4693 }
4694 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
4695 for (int i = nb_args-1; i >= 0; i--) {
4696 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
4697 }
4698 }
4699
4700 subptr(rsp, nb_args*sizeof(jdouble));
4701 for (int i = 0; i < nb_args; i++) {
4702 fstp_d(Address(rsp, i*sizeof(jdouble)));
4703 }
4704
4705 #ifdef _LP64
4706 if (nb_args > 0) {
4707 movdbl(xmm0, Address(rsp, 0));
4708 }
4709 if (nb_args > 1) {
4710 movdbl(xmm1, Address(rsp, sizeof(jdouble)));
4711 }
4712 assert(nb_args <= 2, "unsupported number of args");
4713 #endif // _LP64
4714
4715 // NOTE: we must not use call_VM_leaf here because that requires a
4716 // complete interpreter frame in debug mode -- same bug as 4387334
4717 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
4718 // do proper 64bit abi
4719
4720 NEEDS_CLEANUP;
4721 // Need to add stack banging before this runtime call if it needs to
4722 // be taken; however, there is no generic stack banging routine at
4723 // the MacroAssembler level
4724
4725 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
4726
4727 #ifdef _LP64
4728 movsd(Address(rsp, 0), xmm0);
4729 fld_d(Address(rsp, 0));
4730 #endif // _LP64
4731 addptr(rsp, sizeof(jdouble) * nb_args);
4732 if (num_fpu_regs_in_use > 1) {
4733 // Must save return value to stack and then restore entire FPU
4734 // stack except incoming arguments
4735 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
4736 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
4737 fld_d(Address(rsp, 0));
4738 addptr(rsp, sizeof(jdouble));
4739 }
4740 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
4741 addptr(rsp, sizeof(jdouble) * nb_args);
4742 }
4743
4744 off = 0;
4745 if (UseSSE == 1) {
4746 movflt(xmm0, Address(rsp,off++*sizeof(jdouble)));
4747 movflt(xmm1, Address(rsp,off++*sizeof(jdouble)));
4748 movflt(xmm2, Address(rsp,off++*sizeof(jdouble)));
4749 movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
4750 movflt(xmm4, Address(rsp,off++*sizeof(jdouble)));
4751 movflt(xmm5, Address(rsp,off++*sizeof(jdouble)));
4752 movflt(xmm6, Address(rsp,off++*sizeof(jdouble)));
4753 movflt(xmm7, Address(rsp,off++*sizeof(jdouble)));
4754 addptr(rsp, sizeof(jdouble)*8);
4755 } else if (UseSSE >= 2) {
4756 // Restore whole 128bit (16 bytes) XMM regiters
4757 movdqu(xmm0, Address(rsp,off++*16));
4758 movdqu(xmm1, Address(rsp,off++*16));
4759 movdqu(xmm2, Address(rsp,off++*16));
4760 movdqu(xmm3, Address(rsp,off++*16));
4761 movdqu(xmm4, Address(rsp,off++*16));
4762 movdqu(xmm5, Address(rsp,off++*16));
4763 movdqu(xmm6, Address(rsp,off++*16));
4764 movdqu(xmm7, Address(rsp,off++*16));
4765 #ifdef _LP64
4766 movdqu(xmm8, Address(rsp,off++*16));
4767 movdqu(xmm9, Address(rsp,off++*16));
4768 movdqu(xmm10, Address(rsp,off++*16));
4769 movdqu(xmm11, Address(rsp,off++*16));
4770 movdqu(xmm12, Address(rsp,off++*16));
4771 movdqu(xmm13, Address(rsp,off++*16));
4772 movdqu(xmm14, Address(rsp,off++*16));
4773 movdqu(xmm15, Address(rsp,off++*16));
4774 #endif
4775 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4776 #ifdef COMPILER2
4777 if (MaxVectorSize > 16) {
4778 // Restore upper half of YMM registes.
4779 vinsertf128h(xmm0, Address(rsp, 0));
4780 vinsertf128h(xmm1, Address(rsp, 16));
4781 vinsertf128h(xmm2, Address(rsp, 32));
4782 vinsertf128h(xmm3, Address(rsp, 48));
4783 vinsertf128h(xmm4, Address(rsp, 64));
4784 vinsertf128h(xmm5, Address(rsp, 80));
4785 vinsertf128h(xmm6, Address(rsp, 96));
4786 vinsertf128h(xmm7, Address(rsp,112));
4787 #ifdef _LP64
4788 vinsertf128h(xmm8, Address(rsp,128));
4789 vinsertf128h(xmm9, Address(rsp,144));
4790 vinsertf128h(xmm10, Address(rsp,160));
4791 vinsertf128h(xmm11, Address(rsp,176));
4792 vinsertf128h(xmm12, Address(rsp,192));
4793 vinsertf128h(xmm13, Address(rsp,208));
4794 vinsertf128h(xmm14, Address(rsp,224));
4795 vinsertf128h(xmm15, Address(rsp,240));
4796 #endif
4797 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4798 }
4799 #endif
4800 }
4801 popa();
4802 }
4803
4804 static const double pi_4 = 0.7853981633974483;
4805
4806 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
4807 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
4808 // was attempted in this code; unfortunately it appears that the
4809 // switch to 80-bit precision and back causes this to be
4810 // unprofitable compared with simply performing a runtime call if
4811 // the argument is out of the (-pi/4, pi/4) range.
4812
4813 Register tmp = noreg;
4814 if (!VM_Version::supports_cmov()) {
4815 // fcmp needs a temporary so preserve rbx,
4816 tmp = rbx;
4817 push(tmp);
4818 }
4819
4820 Label slow_case, done;
4821
4822 ExternalAddress pi4_adr = (address)&pi_4;
4823 if (reachable(pi4_adr)) {
4824 // x ?<= pi/4
4825 fld_d(pi4_adr);
4826 fld_s(1); // Stack: X PI/4 X
4827 fabs(); // Stack: |X| PI/4 X
4828 fcmp(tmp);
4829 jcc(Assembler::above, slow_case);
4830
4831 // fastest case: -pi/4 <= x <= pi/4
4832 switch(trig) {
4833 case 's':
4834 fsin();
4835 break;
4836 case 'c':
4837 fcos();
4838 break;
4839 case 't':
4840 ftan();
4841 break;
4842 default:
4843 assert(false, "bad intrinsic");
4844 break;
4845 }
4846 jmp(done);
4847 }
4848
4849 // slow case: runtime call
4850 bind(slow_case);
4851
4852 switch(trig) {
4853 case 's':
4854 {
4855 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
4856 }
4857 break;
4858 case 'c':
4859 {
4860 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
4861 }
4862 break;
4863 case 't':
4864 {
4865 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
4866 }
4867 break;
4868 default:
4869 assert(false, "bad intrinsic");
4870 break;
4871 }
4872
4873 // Come here with result in F-TOS
4874 bind(done);
4875
4876 if (tmp != noreg) {
4877 pop(tmp);
4878 }
4879 }
4880
4881
4882 // Look up the method for a megamorphic invokeinterface call.
4883 // The target method is determined by <intf_klass, itable_index>.
4884 // The receiver klass is in recv_klass.
4885 // On success, the result will be in method_result, and execution falls through.
4886 // On failure, execution transfers to the given label.
4887 void MacroAssembler::lookup_interface_method(Register recv_klass,
4888 Register intf_klass,
4889 RegisterOrConstant itable_index,
4890 Register method_result,
4891 Register scan_temp,
4892 Label& L_no_such_interface,
4893 bool return_method) {
4894 assert_different_registers(recv_klass, intf_klass, scan_temp);
4895 assert_different_registers(method_result, intf_klass, scan_temp);
4896 assert(recv_klass != method_result || !return_method,
4897 "recv_klass can be destroyed when method isn't needed");
4898
4899 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4900 "caller must use same register for non-constant itable index as for method");
4901
4902 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4903 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
4904 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4905 int scan_step = itableOffsetEntry::size() * wordSize;
4906 int vte_size = vtableEntry::size() * wordSize;
4907 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4908 assert(vte_size == wordSize, "else adjust times_vte_scale");
4909
4910 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
4911
4912 // %%% Could store the aligned, prescaled offset in the klassoop.
4913 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4914 if (HeapWordsPerLong > 1) {
4915 // Round up to align_object_offset boundary
4916 // see code for InstanceKlass::start_of_itable!
4917 round_to(scan_temp, BytesPerLong);
4918 }
4919
4920 if (return_method) {
4921 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4922 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4923 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4924 }
4925
4926 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4927 // if (scan->interface() == intf) {
4928 // result = (klass + scan->offset() + itable_index);
4929 // }
4930 // }
4931 Label search, found_method;
4932
4933 for (int peel = 1; peel >= 0; peel--) {
4934 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4935 cmpptr(intf_klass, method_result);
4936
4937 if (peel) {
4938 jccb(Assembler::equal, found_method);
4939 } else {
4940 jccb(Assembler::notEqual, search);
4941 // (invert the test to fall through to found_method...)
4942 }
4943
4944 if (!peel) break;
4945
4946 bind(search);
4947
4948 // Check that the previous entry is non-null. A null entry means that
4949 // the receiver class doesn't implement the interface, and wasn't the
4950 // same as when the caller was compiled.
4951 testptr(method_result, method_result);
4952 jcc(Assembler::zero, L_no_such_interface);
4953 addptr(scan_temp, scan_step);
4954 }
4955
4956 bind(found_method);
4957
4958 if (return_method) {
4959 // Got a hit.
4960 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4961 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4962 }
4963 }
4964
4965
4966 // virtual method calling
4967 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4968 RegisterOrConstant vtable_index,
4969 Register method_result) {
4970 const int base = InstanceKlass::vtable_start_offset() * wordSize;
4971 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4972 Address vtable_entry_addr(recv_klass,
4973 vtable_index, Address::times_ptr,
4974 base + vtableEntry::method_offset_in_bytes());
4975 movptr(method_result, vtable_entry_addr);
4976 }
4977
4978
4979 void MacroAssembler::check_klass_subtype(Register sub_klass,
4980 Register super_klass,
4981 Register temp_reg,
4982 Label& L_success) {
4983 Label L_failure;
4984 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4985 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4986 bind(L_failure);
4987 }
4988
4989
4990 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4991 Register super_klass,
4992 Register temp_reg,
4993 Label* L_success,
4994 Label* L_failure,
4995 Label* L_slow_path,
4996 RegisterOrConstant super_check_offset) {
4997 assert_different_registers(sub_klass, super_klass, temp_reg);
4998 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4999 if (super_check_offset.is_register()) {
5000 assert_different_registers(sub_klass, super_klass,
5001 super_check_offset.as_register());
5002 } else if (must_load_sco) {
5003 assert(temp_reg != noreg, "supply either a temp or a register offset");
5004 }
5005
5006 Label L_fallthrough;
5007 int label_nulls = 0;
5008 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5009 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5010 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5011 assert(label_nulls <= 1, "at most one NULL in the batch");
5012
5013 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5014 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5015 Address super_check_offset_addr(super_klass, sco_offset);
5016
5017 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5018 // range of a jccb. If this routine grows larger, reconsider at
5019 // least some of these.
5020 #define local_jcc(assembler_cond, label) \
5021 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5022 else jcc( assembler_cond, label) /*omit semi*/
5023
5024 // Hacked jmp, which may only be used just before L_fallthrough.
5025 #define final_jmp(label) \
5026 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5027 else jmp(label) /*omit semi*/
5028
5029 // If the pointers are equal, we are done (e.g., String[] elements).
5030 // This self-check enables sharing of secondary supertype arrays among
5031 // non-primary types such as array-of-interface. Otherwise, each such
5032 // type would need its own customized SSA.
5033 // We move this check to the front of the fast path because many
5034 // type checks are in fact trivially successful in this manner,
5035 // so we get a nicely predicted branch right at the start of the check.
5036 cmpptr(sub_klass, super_klass);
5037 local_jcc(Assembler::equal, *L_success);
5038
5039 // Check the supertype display:
5040 if (must_load_sco) {
5041 // Positive movl does right thing on LP64.
5042 movl(temp_reg, super_check_offset_addr);
5043 super_check_offset = RegisterOrConstant(temp_reg);
5044 }
5045 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5046 cmpptr(super_klass, super_check_addr); // load displayed supertype
5047
5048 // This check has worked decisively for primary supers.
5049 // Secondary supers are sought in the super_cache ('super_cache_addr').
5050 // (Secondary supers are interfaces and very deeply nested subtypes.)
5051 // This works in the same check above because of a tricky aliasing
5052 // between the super_cache and the primary super display elements.
5053 // (The 'super_check_addr' can address either, as the case requires.)
5054 // Note that the cache is updated below if it does not help us find
5055 // what we need immediately.
5056 // So if it was a primary super, we can just fail immediately.
5057 // Otherwise, it's the slow path for us (no success at this point).
5058
5059 if (super_check_offset.is_register()) {
5060 local_jcc(Assembler::equal, *L_success);
5061 cmpl(super_check_offset.as_register(), sc_offset);
5062 if (L_failure == &L_fallthrough) {
5063 local_jcc(Assembler::equal, *L_slow_path);
5064 } else {
5065 local_jcc(Assembler::notEqual, *L_failure);
5066 final_jmp(*L_slow_path);
5067 }
5068 } else if (super_check_offset.as_constant() == sc_offset) {
5069 // Need a slow path; fast failure is impossible.
5070 if (L_slow_path == &L_fallthrough) {
5071 local_jcc(Assembler::equal, *L_success);
5072 } else {
5073 local_jcc(Assembler::notEqual, *L_slow_path);
5074 final_jmp(*L_success);
5075 }
5076 } else {
5077 // No slow path; it's a fast decision.
5078 if (L_failure == &L_fallthrough) {
5079 local_jcc(Assembler::equal, *L_success);
5080 } else {
5081 local_jcc(Assembler::notEqual, *L_failure);
5082 final_jmp(*L_success);
5083 }
5084 }
5085
5086 bind(L_fallthrough);
5087
5088 #undef local_jcc
5089 #undef final_jmp
5090 }
5091
5092
5093 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5094 Register super_klass,
5095 Register temp_reg,
5096 Register temp2_reg,
5097 Label* L_success,
5098 Label* L_failure,
5099 bool set_cond_codes) {
5100 assert_different_registers(sub_klass, super_klass, temp_reg);
5101 if (temp2_reg != noreg)
5102 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5103 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5104
5105 Label L_fallthrough;
5106 int label_nulls = 0;
5107 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5108 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5109 assert(label_nulls <= 1, "at most one NULL in the batch");
5110
5111 // a couple of useful fields in sub_klass:
5112 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5113 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5114 Address secondary_supers_addr(sub_klass, ss_offset);
5115 Address super_cache_addr( sub_klass, sc_offset);
5116
5117 // Do a linear scan of the secondary super-klass chain.
5118 // This code is rarely used, so simplicity is a virtue here.
5119 // The repne_scan instruction uses fixed registers, which we must spill.
5120 // Don't worry too much about pre-existing connections with the input regs.
5121
5122 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5123 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5124
5125 // Get super_klass value into rax (even if it was in rdi or rcx).
5126 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5127 if (super_klass != rax || UseCompressedOops) {
5128 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5129 mov(rax, super_klass);
5130 }
5131 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5132 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5133
5134 #ifndef PRODUCT
5135 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5136 ExternalAddress pst_counter_addr((address) pst_counter);
5137 NOT_LP64( incrementl(pst_counter_addr) );
5138 LP64_ONLY( lea(rcx, pst_counter_addr) );
5139 LP64_ONLY( incrementl(Address(rcx, 0)) );
5140 #endif //PRODUCT
5141
5142 // We will consult the secondary-super array.
5143 movptr(rdi, secondary_supers_addr);
5144 // Load the array length. (Positive movl does right thing on LP64.)
5145 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5146 // Skip to start of data.
5147 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5148
5149 // Scan RCX words at [RDI] for an occurrence of RAX.
5150 // Set NZ/Z based on last compare.
5151 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5152 // not change flags (only scas instruction which is repeated sets flags).
5153 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5154
5155 testptr(rax,rax); // Set Z = 0
5156 repne_scan();
5157
5158 // Unspill the temp. registers:
5159 if (pushed_rdi) pop(rdi);
5160 if (pushed_rcx) pop(rcx);
5161 if (pushed_rax) pop(rax);
5162
5163 if (set_cond_codes) {
5164 // Special hack for the AD files: rdi is guaranteed non-zero.
5165 assert(!pushed_rdi, "rdi must be left non-NULL");
5166 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5167 }
5168
5169 if (L_failure == &L_fallthrough)
5170 jccb(Assembler::notEqual, *L_failure);
5171 else jcc(Assembler::notEqual, *L_failure);
5172
5173 // Success. Cache the super we found and proceed in triumph.
5174 movptr(super_cache_addr, super_klass);
5175
5176 if (L_success != &L_fallthrough) {
5177 jmp(*L_success);
5178 }
5179
5180 #undef IS_A_TEMP
5181
5182 bind(L_fallthrough);
5183 }
5184
5185
5186 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5187 if (VM_Version::supports_cmov()) {
5188 cmovl(cc, dst, src);
5189 } else {
5190 Label L;
5191 jccb(negate_condition(cc), L);
5192 movl(dst, src);
5193 bind(L);
5194 }
5195 }
5196
5197 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5198 if (VM_Version::supports_cmov()) {
5199 cmovl(cc, dst, src);
5200 } else {
5201 Label L;
5202 jccb(negate_condition(cc), L);
5203 movl(dst, src);
5204 bind(L);
5205 }
5206 }
5207
5208 void MacroAssembler::verify_oop(Register reg, const char* s) {
5209 if (!VerifyOops) return;
5210
5211 // Pass register number to verify_oop_subroutine
5212 const char* b = NULL;
5213 {
5214 ResourceMark rm;
5215 stringStream ss;
5216 ss.print("verify_oop: %s: %s", reg->name(), s);
5217 b = code_string(ss.as_string());
5218 }
5219 BLOCK_COMMENT("verify_oop {");
5220 #ifdef _LP64
5221 push(rscratch1); // save r10, trashed by movptr()
5222 #endif
5223 push(rax); // save rax,
5224 push(reg); // pass register argument
5225 ExternalAddress buffer((address) b);
5226 // avoid using pushptr, as it modifies scratch registers
5227 // and our contract is not to modify anything
5228 movptr(rax, buffer.addr());
5229 push(rax);
5230 // call indirectly to solve generation ordering problem
5231 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5232 call(rax);
5233 // Caller pops the arguments (oop, message) and restores rax, r10
5234 BLOCK_COMMENT("} verify_oop");
5235 }
5236
5237
5238 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5239 Register tmp,
5240 int offset) {
5241 intptr_t value = *delayed_value_addr;
5242 if (value != 0)
5243 return RegisterOrConstant(value + offset);
5244
5245 // load indirectly to solve generation ordering problem
5246 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5247
5248 #ifdef ASSERT
5249 { Label L;
5250 testptr(tmp, tmp);
5251 if (WizardMode) {
5252 const char* buf = NULL;
5253 {
5254 ResourceMark rm;
5255 stringStream ss;
5256 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
5257 buf = code_string(ss.as_string());
5258 }
5259 jcc(Assembler::notZero, L);
5260 STOP(buf);
5261 } else {
5262 jccb(Assembler::notZero, L);
5263 hlt();
5264 }
5265 bind(L);
5266 }
5267 #endif
5268
5269 if (offset != 0)
5270 addptr(tmp, offset);
5271
5272 return RegisterOrConstant(tmp);
5273 }
5274
5275
5276 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5277 int extra_slot_offset) {
5278 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5279 int stackElementSize = Interpreter::stackElementSize;
5280 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5281 #ifdef ASSERT
5282 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5283 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5284 #endif
5285 Register scale_reg = noreg;
5286 Address::ScaleFactor scale_factor = Address::no_scale;
5287 if (arg_slot.is_constant()) {
5288 offset += arg_slot.as_constant() * stackElementSize;
5289 } else {
5290 scale_reg = arg_slot.as_register();
5291 scale_factor = Address::times(stackElementSize);
5292 }
5293 offset += wordSize; // return PC is on stack
5294 return Address(rsp, scale_reg, scale_factor, offset);
5295 }
5296
5297
5298 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5299 if (!VerifyOops) return;
5300
5301 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5302 // Pass register number to verify_oop_subroutine
5303 const char* b = NULL;
5304 {
5305 ResourceMark rm;
5306 stringStream ss;
5307 ss.print("verify_oop_addr: %s", s);
5308 b = code_string(ss.as_string());
5309 }
5310 #ifdef _LP64
5311 push(rscratch1); // save r10, trashed by movptr()
5312 #endif
5313 push(rax); // save rax,
5314 // addr may contain rsp so we will have to adjust it based on the push
5315 // we just did (and on 64 bit we do two pushes)
5316 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5317 // stores rax into addr which is backwards of what was intended.
5318 if (addr.uses(rsp)) {
5319 lea(rax, addr);
5320 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5321 } else {
5322 pushptr(addr);
5323 }
5324
5325 ExternalAddress buffer((address) b);
5326 // pass msg argument
5327 // avoid using pushptr, as it modifies scratch registers
5328 // and our contract is not to modify anything
5329 movptr(rax, buffer.addr());
5330 push(rax);
5331
5332 // call indirectly to solve generation ordering problem
5333 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5334 call(rax);
5335 // Caller pops the arguments (addr, message) and restores rax, r10.
5336 }
5337
5338 void MacroAssembler::verify_tlab() {
5339 #ifdef ASSERT
5340 if (UseTLAB && VerifyOops) {
5341 Label next, ok;
5342 Register t1 = rsi;
5343 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5344
5345 push(t1);
5346 NOT_LP64(push(thread_reg));
5347 NOT_LP64(get_thread(thread_reg));
5348
5349 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5350 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5351 jcc(Assembler::aboveEqual, next);
5352 STOP("assert(top >= start)");
5353 should_not_reach_here();
5354
5355 bind(next);
5356 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5357 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5358 jcc(Assembler::aboveEqual, ok);
5359 STOP("assert(top <= end)");
5360 should_not_reach_here();
5361
5362 bind(ok);
5363 NOT_LP64(pop(thread_reg));
5364 pop(t1);
5365 }
5366 #endif
5367 }
5368
5369 class ControlWord {
5370 public:
5371 int32_t _value;
5372
5373 int rounding_control() const { return (_value >> 10) & 3 ; }
5374 int precision_control() const { return (_value >> 8) & 3 ; }
5375 bool precision() const { return ((_value >> 5) & 1) != 0; }
5376 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5377 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5378 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5379 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5380 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5381
5382 void print() const {
5383 // rounding control
5384 const char* rc;
5385 switch (rounding_control()) {
5386 case 0: rc = "round near"; break;
5387 case 1: rc = "round down"; break;
5388 case 2: rc = "round up "; break;
5389 case 3: rc = "chop "; break;
5390 };
5391 // precision control
5392 const char* pc;
5393 switch (precision_control()) {
5394 case 0: pc = "24 bits "; break;
5395 case 1: pc = "reserved"; break;
5396 case 2: pc = "53 bits "; break;
5397 case 3: pc = "64 bits "; break;
5398 };
5399 // flags
5400 char f[9];
5401 f[0] = ' ';
5402 f[1] = ' ';
5403 f[2] = (precision ()) ? 'P' : 'p';
5404 f[3] = (underflow ()) ? 'U' : 'u';
5405 f[4] = (overflow ()) ? 'O' : 'o';
5406 f[5] = (zero_divide ()) ? 'Z' : 'z';
5407 f[6] = (denormalized()) ? 'D' : 'd';
5408 f[7] = (invalid ()) ? 'I' : 'i';
5409 f[8] = '\x0';
5410 // output
5411 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5412 }
5413
5414 };
5415
5416 class StatusWord {
5417 public:
5418 int32_t _value;
5419
5420 bool busy() const { return ((_value >> 15) & 1) != 0; }
5421 bool C3() const { return ((_value >> 14) & 1) != 0; }
5422 bool C2() const { return ((_value >> 10) & 1) != 0; }
5423 bool C1() const { return ((_value >> 9) & 1) != 0; }
5424 bool C0() const { return ((_value >> 8) & 1) != 0; }
5425 int top() const { return (_value >> 11) & 7 ; }
5426 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5427 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5428 bool precision() const { return ((_value >> 5) & 1) != 0; }
5429 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5430 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5431 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5432 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5433 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5434
5435 void print() const {
5436 // condition codes
5437 char c[5];
5438 c[0] = (C3()) ? '3' : '-';
5439 c[1] = (C2()) ? '2' : '-';
5440 c[2] = (C1()) ? '1' : '-';
5441 c[3] = (C0()) ? '0' : '-';
5442 c[4] = '\x0';
5443 // flags
5444 char f[9];
5445 f[0] = (error_status()) ? 'E' : '-';
5446 f[1] = (stack_fault ()) ? 'S' : '-';
5447 f[2] = (precision ()) ? 'P' : '-';
5448 f[3] = (underflow ()) ? 'U' : '-';
5449 f[4] = (overflow ()) ? 'O' : '-';
5450 f[5] = (zero_divide ()) ? 'Z' : '-';
5451 f[6] = (denormalized()) ? 'D' : '-';
5452 f[7] = (invalid ()) ? 'I' : '-';
5453 f[8] = '\x0';
5454 // output
5455 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5456 }
5457
5458 };
5459
5460 class TagWord {
5461 public:
5462 int32_t _value;
5463
5464 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5465
5466 void print() const {
5467 printf("%04x", _value & 0xFFFF);
5468 }
5469
5470 };
5471
5472 class FPU_Register {
5473 public:
5474 int32_t _m0;
5475 int32_t _m1;
5476 int16_t _ex;
5477
5478 bool is_indefinite() const {
5479 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5480 }
5481
5482 void print() const {
5483 char sign = (_ex < 0) ? '-' : '+';
5484 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5485 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5486 };
5487
5488 };
5489
5490 class FPU_State {
5491 public:
5492 enum {
5493 register_size = 10,
5494 number_of_registers = 8,
5495 register_mask = 7
5496 };
5497
5498 ControlWord _control_word;
5499 StatusWord _status_word;
5500 TagWord _tag_word;
5501 int32_t _error_offset;
5502 int32_t _error_selector;
5503 int32_t _data_offset;
5504 int32_t _data_selector;
5505 int8_t _register[register_size * number_of_registers];
5506
5507 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5508 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5509
5510 const char* tag_as_string(int tag) const {
5511 switch (tag) {
5512 case 0: return "valid";
5513 case 1: return "zero";
5514 case 2: return "special";
5515 case 3: return "empty";
5516 }
5517 ShouldNotReachHere();
5518 return NULL;
5519 }
5520
5521 void print() const {
5522 // print computation registers
5523 { int t = _status_word.top();
5524 for (int i = 0; i < number_of_registers; i++) {
5525 int j = (i - t) & register_mask;
5526 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5527 st(j)->print();
5528 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5529 }
5530 }
5531 printf("\n");
5532 // print control registers
5533 printf("ctrl = "); _control_word.print(); printf("\n");
5534 printf("stat = "); _status_word .print(); printf("\n");
5535 printf("tags = "); _tag_word .print(); printf("\n");
5536 }
5537
5538 };
5539
5540 class Flag_Register {
5541 public:
5542 int32_t _value;
5543
5544 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5545 bool direction() const { return ((_value >> 10) & 1) != 0; }
5546 bool sign() const { return ((_value >> 7) & 1) != 0; }
5547 bool zero() const { return ((_value >> 6) & 1) != 0; }
5548 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5549 bool parity() const { return ((_value >> 2) & 1) != 0; }
5550 bool carry() const { return ((_value >> 0) & 1) != 0; }
5551
5552 void print() const {
5553 // flags
5554 char f[8];
5555 f[0] = (overflow ()) ? 'O' : '-';
5556 f[1] = (direction ()) ? 'D' : '-';
5557 f[2] = (sign ()) ? 'S' : '-';
5558 f[3] = (zero ()) ? 'Z' : '-';
5559 f[4] = (auxiliary_carry()) ? 'A' : '-';
5560 f[5] = (parity ()) ? 'P' : '-';
5561 f[6] = (carry ()) ? 'C' : '-';
5562 f[7] = '\x0';
5563 // output
5564 printf("%08x flags = %s", _value, f);
5565 }
5566
5567 };
5568
5569 class IU_Register {
5570 public:
5571 int32_t _value;
5572
5573 void print() const {
5574 printf("%08x %11d", _value, _value);
5575 }
5576
5577 };
5578
5579 class IU_State {
5580 public:
5581 Flag_Register _eflags;
5582 IU_Register _rdi;
5583 IU_Register _rsi;
5584 IU_Register _rbp;
5585 IU_Register _rsp;
5586 IU_Register _rbx;
5587 IU_Register _rdx;
5588 IU_Register _rcx;
5589 IU_Register _rax;
5590
5591 void print() const {
5592 // computation registers
5593 printf("rax, = "); _rax.print(); printf("\n");
5594 printf("rbx, = "); _rbx.print(); printf("\n");
5595 printf("rcx = "); _rcx.print(); printf("\n");
5596 printf("rdx = "); _rdx.print(); printf("\n");
5597 printf("rdi = "); _rdi.print(); printf("\n");
5598 printf("rsi = "); _rsi.print(); printf("\n");
5599 printf("rbp, = "); _rbp.print(); printf("\n");
5600 printf("rsp = "); _rsp.print(); printf("\n");
5601 printf("\n");
5602 // control registers
5603 printf("flgs = "); _eflags.print(); printf("\n");
5604 }
5605 };
5606
5607
5608 class CPU_State {
5609 public:
5610 FPU_State _fpu_state;
5611 IU_State _iu_state;
5612
5613 void print() const {
5614 printf("--------------------------------------------------\n");
5615 _iu_state .print();
5616 printf("\n");
5617 _fpu_state.print();
5618 printf("--------------------------------------------------\n");
5619 }
5620
5621 };
5622
5623
5624 static void _print_CPU_state(CPU_State* state) {
5625 state->print();
5626 };
5627
5628
5629 void MacroAssembler::print_CPU_state() {
5630 push_CPU_state();
5631 push(rsp); // pass CPU state
5632 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5633 addptr(rsp, wordSize); // discard argument
5634 pop_CPU_state();
5635 }
5636
5637
5638 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5639 static int counter = 0;
5640 FPU_State* fs = &state->_fpu_state;
5641 counter++;
5642 // For leaf calls, only verify that the top few elements remain empty.
5643 // We only need 1 empty at the top for C2 code.
5644 if( stack_depth < 0 ) {
5645 if( fs->tag_for_st(7) != 3 ) {
5646 printf("FPR7 not empty\n");
5647 state->print();
5648 assert(false, "error");
5649 return false;
5650 }
5651 return true; // All other stack states do not matter
5652 }
5653
5654 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5655 "bad FPU control word");
5656
5657 // compute stack depth
5658 int i = 0;
5659 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5660 int d = i;
5661 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5662 // verify findings
5663 if (i != FPU_State::number_of_registers) {
5664 // stack not contiguous
5665 printf("%s: stack not contiguous at ST%d\n", s, i);
5666 state->print();
5667 assert(false, "error");
5668 return false;
5669 }
5670 // check if computed stack depth corresponds to expected stack depth
5671 if (stack_depth < 0) {
5672 // expected stack depth is -stack_depth or less
5673 if (d > -stack_depth) {
5674 // too many elements on the stack
5675 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5676 state->print();
5677 assert(false, "error");
5678 return false;
5679 }
5680 } else {
5681 // expected stack depth is stack_depth
5682 if (d != stack_depth) {
5683 // wrong stack depth
5684 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5685 state->print();
5686 assert(false, "error");
5687 return false;
5688 }
5689 }
5690 // everything is cool
5691 return true;
5692 }
5693
5694
5695 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5696 if (!VerifyFPU) return;
5697 push_CPU_state();
5698 push(rsp); // pass CPU state
5699 ExternalAddress msg((address) s);
5700 // pass message string s
5701 pushptr(msg.addr());
5702 push(stack_depth); // pass stack depth
5703 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5704 addptr(rsp, 3 * wordSize); // discard arguments
5705 // check for error
5706 { Label L;
5707 testl(rax, rax);
5708 jcc(Assembler::notZero, L);
5709 int3(); // break if error condition
5710 bind(L);
5711 }
5712 pop_CPU_state();
5713 }
5714
5715 void MacroAssembler::restore_cpu_control_state_after_jni() {
5716 // Either restore the MXCSR register after returning from the JNI Call
5717 // or verify that it wasn't changed (with -Xcheck:jni flag).
5718 if (VM_Version::supports_sse()) {
5719 if (RestoreMXCSROnJNICalls) {
5720 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5721 } else if (CheckJNICalls) {
5722 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5723 }
5724 }
5725 if (VM_Version::supports_avx()) {
5726 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5727 vzeroupper();
5728 }
5729
5730 #ifndef _LP64
5731 // Either restore the x87 floating pointer control word after returning
5732 // from the JNI call or verify that it wasn't changed.
5733 if (CheckJNICalls) {
5734 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5735 }
5736 #endif // _LP64
5737 }
5738
5739
5740 void MacroAssembler::load_klass(Register dst, Register src) {
5741 #ifdef _LP64
5742 if (UseCompressedClassPointers) {
5743 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5744 decode_klass_not_null(dst);
5745 } else
5746 #endif
5747 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5748 }
5749
5750 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5751 load_klass(dst, src);
5752 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5753 }
5754
5755 void MacroAssembler::store_klass(Register dst, Register src) {
5756 #ifdef _LP64
5757 if (UseCompressedClassPointers) {
5758 encode_klass_not_null(src);
5759 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5760 } else
5761 #endif
5762 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5763 }
5764
5765 void MacroAssembler::load_heap_oop(Register dst, Address src) {
5766 #ifdef _LP64
5767 // FIXME: Must change all places where we try to load the klass.
5768 if (UseCompressedOops) {
5769 movl(dst, src);
5770 decode_heap_oop(dst);
5771 } else
5772 #endif
5773 movptr(dst, src);
5774 }
5775
5776 // Doesn't do verfication, generates fixed size code
5777 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
5778 #ifdef _LP64
5779 if (UseCompressedOops) {
5780 movl(dst, src);
5781 decode_heap_oop_not_null(dst);
5782 } else
5783 #endif
5784 movptr(dst, src);
5785 }
5786
5787 void MacroAssembler::store_heap_oop(Address dst, Register src) {
5788 #ifdef _LP64
5789 if (UseCompressedOops) {
5790 assert(!dst.uses(src), "not enough registers");
5791 encode_heap_oop(src);
5792 movl(dst, src);
5793 } else
5794 #endif
5795 movptr(dst, src);
5796 }
5797
5798 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
5799 assert_different_registers(src1, tmp);
5800 #ifdef _LP64
5801 if (UseCompressedOops) {
5802 bool did_push = false;
5803 if (tmp == noreg) {
5804 tmp = rax;
5805 push(tmp);
5806 did_push = true;
5807 assert(!src2.uses(rsp), "can't push");
5808 }
5809 load_heap_oop(tmp, src2);
5810 cmpptr(src1, tmp);
5811 if (did_push) pop(tmp);
5812 } else
5813 #endif
5814 cmpptr(src1, src2);
5815 }
5816
5817 // Used for storing NULLs.
5818 void MacroAssembler::store_heap_oop_null(Address dst) {
5819 #ifdef _LP64
5820 if (UseCompressedOops) {
5821 movl(dst, (int32_t)NULL_WORD);
5822 } else {
5823 movslq(dst, (int32_t)NULL_WORD);
5824 }
5825 #else
5826 movl(dst, (int32_t)NULL_WORD);
5827 #endif
5828 }
5829
5830 #ifdef _LP64
5831 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5832 if (UseCompressedClassPointers) {
5833 // Store to klass gap in destination
5834 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5835 }
5836 }
5837
5838 #ifdef ASSERT
5839 void MacroAssembler::verify_heapbase(const char* msg) {
5840 assert (UseCompressedOops, "should be compressed");
5841 assert (Universe::heap() != NULL, "java heap should be initialized");
5842 if (CheckCompressedOops) {
5843 Label ok;
5844 push(rscratch1); // cmpptr trashes rscratch1
5845 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5846 jcc(Assembler::equal, ok);
5847 STOP(msg);
5848 bind(ok);
5849 pop(rscratch1);
5850 }
5851 }
5852 #endif
5853
5854 // Algorithm must match oop.inline.hpp encode_heap_oop.
5855 void MacroAssembler::encode_heap_oop(Register r) {
5856 #ifdef ASSERT
5857 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5858 #endif
5859 verify_oop(r, "broken oop in encode_heap_oop");
5860 if (Universe::narrow_oop_base() == NULL) {
5861 if (Universe::narrow_oop_shift() != 0) {
5862 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5863 shrq(r, LogMinObjAlignmentInBytes);
5864 }
5865 return;
5866 }
5867 testq(r, r);
5868 cmovq(Assembler::equal, r, r12_heapbase);
5869 subq(r, r12_heapbase);
5870 shrq(r, LogMinObjAlignmentInBytes);
5871 }
5872
5873 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5874 #ifdef ASSERT
5875 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5876 if (CheckCompressedOops) {
5877 Label ok;
5878 testq(r, r);
5879 jcc(Assembler::notEqual, ok);
5880 STOP("null oop passed to encode_heap_oop_not_null");
5881 bind(ok);
5882 }
5883 #endif
5884 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5885 if (Universe::narrow_oop_base() != NULL) {
5886 subq(r, r12_heapbase);
5887 }
5888 if (Universe::narrow_oop_shift() != 0) {
5889 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5890 shrq(r, LogMinObjAlignmentInBytes);
5891 }
5892 }
5893
5894 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5895 #ifdef ASSERT
5896 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5897 if (CheckCompressedOops) {
5898 Label ok;
5899 testq(src, src);
5900 jcc(Assembler::notEqual, ok);
5901 STOP("null oop passed to encode_heap_oop_not_null2");
5902 bind(ok);
5903 }
5904 #endif
5905 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5906 if (dst != src) {
5907 movq(dst, src);
5908 }
5909 if (Universe::narrow_oop_base() != NULL) {
5910 subq(dst, r12_heapbase);
5911 }
5912 if (Universe::narrow_oop_shift() != 0) {
5913 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5914 shrq(dst, LogMinObjAlignmentInBytes);
5915 }
5916 }
5917
5918 void MacroAssembler::decode_heap_oop(Register r) {
5919 #ifdef ASSERT
5920 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5921 #endif
5922 if (Universe::narrow_oop_base() == NULL) {
5923 if (Universe::narrow_oop_shift() != 0) {
5924 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5925 shlq(r, LogMinObjAlignmentInBytes);
5926 }
5927 } else {
5928 Label done;
5929 shlq(r, LogMinObjAlignmentInBytes);
5930 jccb(Assembler::equal, done);
5931 addq(r, r12_heapbase);
5932 bind(done);
5933 }
5934 verify_oop(r, "broken oop in decode_heap_oop");
5935 }
5936
5937 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5938 // Note: it will change flags
5939 assert (UseCompressedOops, "should only be used for compressed headers");
5940 assert (Universe::heap() != NULL, "java heap should be initialized");
5941 // Cannot assert, unverified entry point counts instructions (see .ad file)
5942 // vtableStubs also counts instructions in pd_code_size_limit.
5943 // Also do not verify_oop as this is called by verify_oop.
5944 if (Universe::narrow_oop_shift() != 0) {
5945 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5946 shlq(r, LogMinObjAlignmentInBytes);
5947 if (Universe::narrow_oop_base() != NULL) {
5948 addq(r, r12_heapbase);
5949 }
5950 } else {
5951 assert (Universe::narrow_oop_base() == NULL, "sanity");
5952 }
5953 }
5954
5955 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5956 // Note: it will change flags
5957 assert (UseCompressedOops, "should only be used for compressed headers");
5958 assert (Universe::heap() != NULL, "java heap should be initialized");
5959 // Cannot assert, unverified entry point counts instructions (see .ad file)
5960 // vtableStubs also counts instructions in pd_code_size_limit.
5961 // Also do not verify_oop as this is called by verify_oop.
5962 if (Universe::narrow_oop_shift() != 0) {
5963 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5964 if (LogMinObjAlignmentInBytes == Address::times_8) {
5965 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5966 } else {
5967 if (dst != src) {
5968 movq(dst, src);
5969 }
5970 shlq(dst, LogMinObjAlignmentInBytes);
5971 if (Universe::narrow_oop_base() != NULL) {
5972 addq(dst, r12_heapbase);
5973 }
5974 }
5975 } else {
5976 assert (Universe::narrow_oop_base() == NULL, "sanity");
5977 if (dst != src) {
5978 movq(dst, src);
5979 }
5980 }
5981 }
5982
5983 void MacroAssembler::encode_klass_not_null(Register r) {
5984 if (Universe::narrow_klass_base() != NULL) {
5985 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5986 assert(r != r12_heapbase, "Encoding a klass in r12");
5987 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5988 subq(r, r12_heapbase);
5989 }
5990 if (Universe::narrow_klass_shift() != 0) {
5991 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5992 shrq(r, LogKlassAlignmentInBytes);
5993 }
5994 if (Universe::narrow_klass_base() != NULL) {
5995 reinit_heapbase();
5996 }
5997 }
5998
5999 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6000 if (dst == src) {
6001 encode_klass_not_null(src);
6002 } else {
6003 if (Universe::narrow_klass_base() != NULL) {
6004 mov64(dst, (int64_t)Universe::narrow_klass_base());
6005 negq(dst);
6006 addq(dst, src);
6007 } else {
6008 movptr(dst, src);
6009 }
6010 if (Universe::narrow_klass_shift() != 0) {
6011 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6012 shrq(dst, LogKlassAlignmentInBytes);
6013 }
6014 }
6015 }
6016
6017 // Function instr_size_for_decode_klass_not_null() counts the instructions
6018 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6019 // when (Universe::heap() != NULL). Hence, if the instructions they
6020 // generate change, then this method needs to be updated.
6021 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6022 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6023 if (Universe::narrow_klass_base() != NULL) {
6024 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6025 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6026 } else {
6027 // longest load decode klass function, mov64, leaq
6028 return 16;
6029 }
6030 }
6031
6032 // !!! If the instructions that get generated here change then function
6033 // instr_size_for_decode_klass_not_null() needs to get updated.
6034 void MacroAssembler::decode_klass_not_null(Register r) {
6035 // Note: it will change flags
6036 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6037 assert(r != r12_heapbase, "Decoding a klass in r12");
6038 // Cannot assert, unverified entry point counts instructions (see .ad file)
6039 // vtableStubs also counts instructions in pd_code_size_limit.
6040 // Also do not verify_oop as this is called by verify_oop.
6041 if (Universe::narrow_klass_shift() != 0) {
6042 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6043 shlq(r, LogKlassAlignmentInBytes);
6044 }
6045 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6046 if (Universe::narrow_klass_base() != NULL) {
6047 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6048 addq(r, r12_heapbase);
6049 reinit_heapbase();
6050 }
6051 }
6052
6053 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6054 // Note: it will change flags
6055 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6056 if (dst == src) {
6057 decode_klass_not_null(dst);
6058 } else {
6059 // Cannot assert, unverified entry point counts instructions (see .ad file)
6060 // vtableStubs also counts instructions in pd_code_size_limit.
6061 // Also do not verify_oop as this is called by verify_oop.
6062 mov64(dst, (int64_t)Universe::narrow_klass_base());
6063 if (Universe::narrow_klass_shift() != 0) {
6064 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6065 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6066 leaq(dst, Address(dst, src, Address::times_8, 0));
6067 } else {
6068 addq(dst, src);
6069 }
6070 }
6071 }
6072
6073 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6074 assert (UseCompressedOops, "should only be used for compressed headers");
6075 assert (Universe::heap() != NULL, "java heap should be initialized");
6076 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6077 int oop_index = oop_recorder()->find_index(obj);
6078 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6079 mov_narrow_oop(dst, oop_index, rspec);
6080 }
6081
6082 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6083 assert (UseCompressedOops, "should only be used for compressed headers");
6084 assert (Universe::heap() != NULL, "java heap should be initialized");
6085 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6086 int oop_index = oop_recorder()->find_index(obj);
6087 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6088 mov_narrow_oop(dst, oop_index, rspec);
6089 }
6090
6091 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6092 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6093 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6094 int klass_index = oop_recorder()->find_index(k);
6095 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6096 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6097 }
6098
6099 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6100 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6101 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6102 int klass_index = oop_recorder()->find_index(k);
6103 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6104 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6105 }
6106
6107 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6108 assert (UseCompressedOops, "should only be used for compressed headers");
6109 assert (Universe::heap() != NULL, "java heap should be initialized");
6110 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6111 int oop_index = oop_recorder()->find_index(obj);
6112 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6113 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6114 }
6115
6116 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6117 assert (UseCompressedOops, "should only be used for compressed headers");
6118 assert (Universe::heap() != NULL, "java heap should be initialized");
6119 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6120 int oop_index = oop_recorder()->find_index(obj);
6121 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6122 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6123 }
6124
6125 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6126 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6127 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6128 int klass_index = oop_recorder()->find_index(k);
6129 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6130 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6131 }
6132
6133 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6134 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6135 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6136 int klass_index = oop_recorder()->find_index(k);
6137 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6138 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6139 }
6140
6141 void MacroAssembler::reinit_heapbase() {
6142 if (UseCompressedOops || UseCompressedClassPointers) {
6143 if (Universe::heap() != NULL) {
6144 if (Universe::narrow_oop_base() == NULL) {
6145 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6146 } else {
6147 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6148 }
6149 } else {
6150 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6151 }
6152 }
6153 }
6154
6155 #endif // _LP64
6156
6157
6158 // C2 compiled method's prolog code.
6159 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6160
6161 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6162 // NativeJump::patch_verified_entry will be able to patch out the entry
6163 // code safely. The push to verify stack depth is ok at 5 bytes,
6164 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6165 // stack bang then we must use the 6 byte frame allocation even if
6166 // we have no frame. :-(
6167 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6168
6169 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6170 // Remove word for return addr
6171 framesize -= wordSize;
6172 stack_bang_size -= wordSize;
6173
6174 // Calls to C2R adapters often do not accept exceptional returns.
6175 // We require that their callers must bang for them. But be careful, because
6176 // some VM calls (such as call site linkage) can use several kilobytes of
6177 // stack. But the stack safety zone should account for that.
6178 // See bugs 4446381, 4468289, 4497237.
6179 if (stack_bang_size > 0) {
6180 generate_stack_overflow_check(stack_bang_size);
6181
6182 // We always push rbp, so that on return to interpreter rbp, will be
6183 // restored correctly and we can correct the stack.
6184 push(rbp);
6185 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6186 if (PreserveFramePointer) {
6187 mov(rbp, rsp);
6188 }
6189 // Remove word for ebp
6190 framesize -= wordSize;
6191
6192 // Create frame
6193 if (framesize) {
6194 subptr(rsp, framesize);
6195 }
6196 } else {
6197 // Create frame (force generation of a 4 byte immediate value)
6198 subptr_imm32(rsp, framesize);
6199
6200 // Save RBP register now.
6201 framesize -= wordSize;
6202 movptr(Address(rsp, framesize), rbp);
6203 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6204 if (PreserveFramePointer) {
6205 movptr(rbp, rsp);
6206 if (framesize > 0) {
6207 addptr(rbp, framesize);
6208 }
6209 }
6210 }
6211
6212 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6213 framesize -= wordSize;
6214 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6215 }
6216
6217 #ifndef _LP64
6218 // If method sets FPU control word do it now
6219 if (fp_mode_24b) {
6220 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6221 }
6222 if (UseSSE >= 2 && VerifyFPU) {
6223 verify_FPU(0, "FPU stack must be clean on entry");
6224 }
6225 #endif
6226
6227 #ifdef ASSERT
6228 if (VerifyStackAtCalls) {
6229 Label L;
6230 push(rax);
6231 mov(rax, rsp);
6232 andptr(rax, StackAlignmentInBytes-1);
6233 cmpptr(rax, StackAlignmentInBytes-wordSize);
6234 pop(rax);
6235 jcc(Assembler::equal, L);
6236 STOP("Stack is not properly aligned!");
6237 bind(L);
6238 }
6239 #endif
6240
6241 }
6242
6243 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) {
6244 // cnt - number of qwords (8-byte words).
6245 // base - start address, qword aligned.
6246 assert(base==rdi, "base register must be edi for rep stos");
6247 assert(tmp==rax, "tmp register must be eax for rep stos");
6248 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6249
6250 xorptr(tmp, tmp);
6251 if (UseFastStosb) {
6252 shlptr(cnt,3); // convert to number of bytes
6253 rep_stosb();
6254 } else {
6255 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM
6256 rep_stos();
6257 }
6258 }
6259
6260 // IndexOf for constant substrings with size >= 8 chars
6261 // which don't need to be loaded through stack.
6262 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6263 Register cnt1, Register cnt2,
6264 int int_cnt2, Register result,
6265 XMMRegister vec, Register tmp) {
6266 ShortBranchVerifier sbv(this);
6267 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6268
6269 // This method uses pcmpestri inxtruction with bound registers
6270 // inputs:
6271 // xmm - substring
6272 // rax - substring length (elements count)
6273 // mem - scanned string
6274 // rdx - string length (elements count)
6275 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6276 // outputs:
6277 // rcx - matched index in string
6278 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6279
6280 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6281 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6282 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6283
6284 // Note, inline_string_indexOf() generates checks:
6285 // if (substr.count > string.count) return -1;
6286 // if (substr.count == 0) return 0;
6287 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
6288
6289 // Load substring.
6290 movdqu(vec, Address(str2, 0));
6291 movl(cnt2, int_cnt2);
6292 movptr(result, str1); // string addr
6293
6294 if (int_cnt2 > 8) {
6295 jmpb(SCAN_TO_SUBSTR);
6296
6297 // Reload substr for rescan, this code
6298 // is executed only for large substrings (> 8 chars)
6299 bind(RELOAD_SUBSTR);
6300 movdqu(vec, Address(str2, 0));
6301 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6302
6303 bind(RELOAD_STR);
6304 // We came here after the beginning of the substring was
6305 // matched but the rest of it was not so we need to search
6306 // again. Start from the next element after the previous match.
6307
6308 // cnt2 is number of substring reminding elements and
6309 // cnt1 is number of string reminding elements when cmp failed.
6310 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6311 subl(cnt1, cnt2);
6312 addl(cnt1, int_cnt2);
6313 movl(cnt2, int_cnt2); // Now restore cnt2
6314
6315 decrementl(cnt1); // Shift to next element
6316 cmpl(cnt1, cnt2);
6317 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6318
6319 addptr(result, 2);
6320
6321 } // (int_cnt2 > 8)
6322
6323 // Scan string for start of substr in 16-byte vectors
6324 bind(SCAN_TO_SUBSTR);
6325 pcmpestri(vec, Address(result, 0), 0x0d);
6326 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6327 subl(cnt1, 8);
6328 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6329 cmpl(cnt1, cnt2);
6330 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6331 addptr(result, 16);
6332 jmpb(SCAN_TO_SUBSTR);
6333
6334 // Found a potential substr
6335 bind(FOUND_CANDIDATE);
6336 // Matched whole vector if first element matched (tmp(rcx) == 0).
6337 if (int_cnt2 == 8) {
6338 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6339 } else { // int_cnt2 > 8
6340 jccb(Assembler::overflow, FOUND_SUBSTR);
6341 }
6342 // After pcmpestri tmp(rcx) contains matched element index
6343 // Compute start addr of substr
6344 lea(result, Address(result, tmp, Address::times_2));
6345
6346 // Make sure string is still long enough
6347 subl(cnt1, tmp);
6348 cmpl(cnt1, cnt2);
6349 if (int_cnt2 == 8) {
6350 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6351 } else { // int_cnt2 > 8
6352 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6353 }
6354 // Left less then substring.
6355
6356 bind(RET_NOT_FOUND);
6357 movl(result, -1);
6358 jmpb(EXIT);
6359
6360 if (int_cnt2 > 8) {
6361 // This code is optimized for the case when whole substring
6362 // is matched if its head is matched.
6363 bind(MATCH_SUBSTR_HEAD);
6364 pcmpestri(vec, Address(result, 0), 0x0d);
6365 // Reload only string if does not match
6366 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
6367
6368 Label CONT_SCAN_SUBSTR;
6369 // Compare the rest of substring (> 8 chars).
6370 bind(FOUND_SUBSTR);
6371 // First 8 chars are already matched.
6372 negptr(cnt2);
6373 addptr(cnt2, 8);
6374
6375 bind(SCAN_SUBSTR);
6376 subl(cnt1, 8);
6377 cmpl(cnt2, -8); // Do not read beyond substring
6378 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6379 // Back-up strings to avoid reading beyond substring:
6380 // cnt1 = cnt1 - cnt2 + 8
6381 addl(cnt1, cnt2); // cnt2 is negative
6382 addl(cnt1, 8);
6383 movl(cnt2, 8); negptr(cnt2);
6384 bind(CONT_SCAN_SUBSTR);
6385 if (int_cnt2 < (int)G) {
6386 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
6387 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
6388 } else {
6389 // calculate index in register to avoid integer overflow (int_cnt2*2)
6390 movl(tmp, int_cnt2);
6391 addptr(tmp, cnt2);
6392 movdqu(vec, Address(str2, tmp, Address::times_2, 0));
6393 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
6394 }
6395 // Need to reload strings pointers if not matched whole vector
6396 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6397 addptr(cnt2, 8);
6398 jcc(Assembler::negative, SCAN_SUBSTR);
6399 // Fall through if found full substring
6400
6401 } // (int_cnt2 > 8)
6402
6403 bind(RET_FOUND);
6404 // Found result if we matched full small substring.
6405 // Compute substr offset
6406 subptr(result, str1);
6407 shrl(result, 1); // index
6408 bind(EXIT);
6409
6410 } // string_indexofC8
6411
6412 // Small strings are loaded through stack if they cross page boundary.
6413 void MacroAssembler::string_indexof(Register str1, Register str2,
6414 Register cnt1, Register cnt2,
6415 int int_cnt2, Register result,
6416 XMMRegister vec, Register tmp) {
6417 ShortBranchVerifier sbv(this);
6418 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6419 //
6420 // int_cnt2 is length of small (< 8 chars) constant substring
6421 // or (-1) for non constant substring in which case its length
6422 // is in cnt2 register.
6423 //
6424 // Note, inline_string_indexOf() generates checks:
6425 // if (substr.count > string.count) return -1;
6426 // if (substr.count == 0) return 0;
6427 //
6428 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
6429
6430 // This method uses pcmpestri inxtruction with bound registers
6431 // inputs:
6432 // xmm - substring
6433 // rax - substring length (elements count)
6434 // mem - scanned string
6435 // rdx - string length (elements count)
6436 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6437 // outputs:
6438 // rcx - matched index in string
6439 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6440
6441 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6442 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6443 FOUND_CANDIDATE;
6444
6445 { //========================================================
6446 // We don't know where these strings are located
6447 // and we can't read beyond them. Load them through stack.
6448 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6449
6450 movptr(tmp, rsp); // save old SP
6451
6452 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6453 if (int_cnt2 == 1) { // One char
6454 load_unsigned_short(result, Address(str2, 0));
6455 movdl(vec, result); // move 32 bits
6456 } else if (int_cnt2 == 2) { // Two chars
6457 movdl(vec, Address(str2, 0)); // move 32 bits
6458 } else if (int_cnt2 == 4) { // Four chars
6459 movq(vec, Address(str2, 0)); // move 64 bits
6460 } else { // cnt2 = { 3, 5, 6, 7 }
6461 // Array header size is 12 bytes in 32-bit VM
6462 // + 6 bytes for 3 chars == 18 bytes,
6463 // enough space to load vec and shift.
6464 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6465 movdqu(vec, Address(str2, (int_cnt2*2)-16));
6466 psrldq(vec, 16-(int_cnt2*2));
6467 }
6468 } else { // not constant substring
6469 cmpl(cnt2, 8);
6470 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6471
6472 // We can read beyond string if srt+16 does not cross page boundary
6473 // since heaps are aligned and mapped by pages.
6474 assert(os::vm_page_size() < (int)G, "default page should be small");
6475 movl(result, str2); // We need only low 32 bits
6476 andl(result, (os::vm_page_size()-1));
6477 cmpl(result, (os::vm_page_size()-16));
6478 jccb(Assembler::belowEqual, CHECK_STR);
6479
6480 // Move small strings to stack to allow load 16 bytes into vec.
6481 subptr(rsp, 16);
6482 int stk_offset = wordSize-2;
6483 push(cnt2);
6484
6485 bind(COPY_SUBSTR);
6486 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
6487 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6488 decrement(cnt2);
6489 jccb(Assembler::notZero, COPY_SUBSTR);
6490
6491 pop(cnt2);
6492 movptr(str2, rsp); // New substring address
6493 } // non constant
6494
6495 bind(CHECK_STR);
6496 cmpl(cnt1, 8);
6497 jccb(Assembler::aboveEqual, BIG_STRINGS);
6498
6499 // Check cross page boundary.
6500 movl(result, str1); // We need only low 32 bits
6501 andl(result, (os::vm_page_size()-1));
6502 cmpl(result, (os::vm_page_size()-16));
6503 jccb(Assembler::belowEqual, BIG_STRINGS);
6504
6505 subptr(rsp, 16);
6506 int stk_offset = -2;
6507 if (int_cnt2 < 0) { // not constant
6508 push(cnt2);
6509 stk_offset += wordSize;
6510 }
6511 movl(cnt2, cnt1);
6512
6513 bind(COPY_STR);
6514 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
6515 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6516 decrement(cnt2);
6517 jccb(Assembler::notZero, COPY_STR);
6518
6519 if (int_cnt2 < 0) { // not constant
6520 pop(cnt2);
6521 }
6522 movptr(str1, rsp); // New string address
6523
6524 bind(BIG_STRINGS);
6525 // Load substring.
6526 if (int_cnt2 < 0) { // -1
6527 movdqu(vec, Address(str2, 0));
6528 push(cnt2); // substr count
6529 push(str2); // substr addr
6530 push(str1); // string addr
6531 } else {
6532 // Small (< 8 chars) constant substrings are loaded already.
6533 movl(cnt2, int_cnt2);
6534 }
6535 push(tmp); // original SP
6536
6537 } // Finished loading
6538
6539 //========================================================
6540 // Start search
6541 //
6542
6543 movptr(result, str1); // string addr
6544
6545 if (int_cnt2 < 0) { // Only for non constant substring
6546 jmpb(SCAN_TO_SUBSTR);
6547
6548 // SP saved at sp+0
6549 // String saved at sp+1*wordSize
6550 // Substr saved at sp+2*wordSize
6551 // Substr count saved at sp+3*wordSize
6552
6553 // Reload substr for rescan, this code
6554 // is executed only for large substrings (> 8 chars)
6555 bind(RELOAD_SUBSTR);
6556 movptr(str2, Address(rsp, 2*wordSize));
6557 movl(cnt2, Address(rsp, 3*wordSize));
6558 movdqu(vec, Address(str2, 0));
6559 // We came here after the beginning of the substring was
6560 // matched but the rest of it was not so we need to search
6561 // again. Start from the next element after the previous match.
6562 subptr(str1, result); // Restore counter
6563 shrl(str1, 1);
6564 addl(cnt1, str1);
6565 decrementl(cnt1); // Shift to next element
6566 cmpl(cnt1, cnt2);
6567 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6568
6569 addptr(result, 2);
6570 } // non constant
6571
6572 // Scan string for start of substr in 16-byte vectors
6573 bind(SCAN_TO_SUBSTR);
6574 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6575 pcmpestri(vec, Address(result, 0), 0x0d);
6576 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6577 subl(cnt1, 8);
6578 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6579 cmpl(cnt1, cnt2);
6580 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6581 addptr(result, 16);
6582
6583 bind(ADJUST_STR);
6584 cmpl(cnt1, 8); // Do not read beyond string
6585 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6586 // Back-up string to avoid reading beyond string.
6587 lea(result, Address(result, cnt1, Address::times_2, -16));
6588 movl(cnt1, 8);
6589 jmpb(SCAN_TO_SUBSTR);
6590
6591 // Found a potential substr
6592 bind(FOUND_CANDIDATE);
6593 // After pcmpestri tmp(rcx) contains matched element index
6594
6595 // Make sure string is still long enough
6596 subl(cnt1, tmp);
6597 cmpl(cnt1, cnt2);
6598 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6599 // Left less then substring.
6600
6601 bind(RET_NOT_FOUND);
6602 movl(result, -1);
6603 jmpb(CLEANUP);
6604
6605 bind(FOUND_SUBSTR);
6606 // Compute start addr of substr
6607 lea(result, Address(result, tmp, Address::times_2));
6608
6609 if (int_cnt2 > 0) { // Constant substring
6610 // Repeat search for small substring (< 8 chars)
6611 // from new point without reloading substring.
6612 // Have to check that we don't read beyond string.
6613 cmpl(tmp, 8-int_cnt2);
6614 jccb(Assembler::greater, ADJUST_STR);
6615 // Fall through if matched whole substring.
6616 } else { // non constant
6617 assert(int_cnt2 == -1, "should be != 0");
6618
6619 addl(tmp, cnt2);
6620 // Found result if we matched whole substring.
6621 cmpl(tmp, 8);
6622 jccb(Assembler::lessEqual, RET_FOUND);
6623
6624 // Repeat search for small substring (<= 8 chars)
6625 // from new point 'str1' without reloading substring.
6626 cmpl(cnt2, 8);
6627 // Have to check that we don't read beyond string.
6628 jccb(Assembler::lessEqual, ADJUST_STR);
6629
6630 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6631 // Compare the rest of substring (> 8 chars).
6632 movptr(str1, result);
6633
6634 cmpl(tmp, cnt2);
6635 // First 8 chars are already matched.
6636 jccb(Assembler::equal, CHECK_NEXT);
6637
6638 bind(SCAN_SUBSTR);
6639 pcmpestri(vec, Address(str1, 0), 0x0d);
6640 // Need to reload strings pointers if not matched whole vector
6641 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6642
6643 bind(CHECK_NEXT);
6644 subl(cnt2, 8);
6645 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6646 addptr(str1, 16);
6647 addptr(str2, 16);
6648 subl(cnt1, 8);
6649 cmpl(cnt2, 8); // Do not read beyond substring
6650 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6651 // Back-up strings to avoid reading beyond substring.
6652 lea(str2, Address(str2, cnt2, Address::times_2, -16));
6653 lea(str1, Address(str1, cnt2, Address::times_2, -16));
6654 subl(cnt1, cnt2);
6655 movl(cnt2, 8);
6656 addl(cnt1, 8);
6657 bind(CONT_SCAN_SUBSTR);
6658 movdqu(vec, Address(str2, 0));
6659 jmpb(SCAN_SUBSTR);
6660
6661 bind(RET_FOUND_LONG);
6662 movptr(str1, Address(rsp, wordSize));
6663 } // non constant
6664
6665 bind(RET_FOUND);
6666 // Compute substr offset
6667 subptr(result, str1);
6668 shrl(result, 1); // index
6669
6670 bind(CLEANUP);
6671 pop(rsp); // restore SP
6672
6673 } // string_indexof
6674
6675 // Compare strings.
6676 void MacroAssembler::string_compare(Register str1, Register str2,
6677 Register cnt1, Register cnt2, Register result,
6678 XMMRegister vec1) {
6679 ShortBranchVerifier sbv(this);
6680 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6681
6682 // Compute the minimum of the string lengths and the
6683 // difference of the string lengths (stack).
6684 // Do the conditional move stuff
6685 movl(result, cnt1);
6686 subl(cnt1, cnt2);
6687 push(cnt1);
6688 cmov32(Assembler::lessEqual, cnt2, result);
6689
6690 // Is the minimum length zero?
6691 testl(cnt2, cnt2);
6692 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6693
6694 // Compare first characters
6695 load_unsigned_short(result, Address(str1, 0));
6696 load_unsigned_short(cnt1, Address(str2, 0));
6697 subl(result, cnt1);
6698 jcc(Assembler::notZero, POP_LABEL);
6699 cmpl(cnt2, 1);
6700 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6701
6702 // Check if the strings start at the same location.
6703 cmpptr(str1, str2);
6704 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6705
6706 Address::ScaleFactor scale = Address::times_2;
6707 int stride = 8;
6708
6709 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6710 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6711 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6712 Label COMPARE_TAIL_LONG;
6713 int pcmpmask = 0x19;
6714
6715 // Setup to compare 16-chars (32-bytes) vectors,
6716 // start from first character again because it has aligned address.
6717 int stride2 = 16;
6718 int adr_stride = stride << scale;
6719 int adr_stride2 = stride2 << scale;
6720
6721 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6722 // rax and rdx are used by pcmpestri as elements counters
6723 movl(result, cnt2);
6724 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6725 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6726
6727 // fast path : compare first 2 8-char vectors.
6728 bind(COMPARE_16_CHARS);
6729 movdqu(vec1, Address(str1, 0));
6730 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6731 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6732
6733 movdqu(vec1, Address(str1, adr_stride));
6734 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6735 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6736 addl(cnt1, stride);
6737
6738 // Compare the characters at index in cnt1
6739 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character
6740 load_unsigned_short(result, Address(str1, cnt1, scale));
6741 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6742 subl(result, cnt2);
6743 jmp(POP_LABEL);
6744
6745 // Setup the registers to start vector comparison loop
6746 bind(COMPARE_WIDE_VECTORS);
6747 lea(str1, Address(str1, result, scale));
6748 lea(str2, Address(str2, result, scale));
6749 subl(result, stride2);
6750 subl(cnt2, stride2);
6751 jccb(Assembler::zero, COMPARE_WIDE_TAIL);
6752 negptr(result);
6753
6754 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6755 bind(COMPARE_WIDE_VECTORS_LOOP);
6756 vmovdqu(vec1, Address(str1, result, scale));
6757 vpxor(vec1, Address(str2, result, scale));
6758 vptest(vec1, vec1);
6759 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
6760 addptr(result, stride2);
6761 subl(cnt2, stride2);
6762 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6763 // clean upper bits of YMM registers
6764 vpxor(vec1, vec1);
6765
6766 // compare wide vectors tail
6767 bind(COMPARE_WIDE_TAIL);
6768 testptr(result, result);
6769 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6770
6771 movl(result, stride2);
6772 movl(cnt2, result);
6773 negptr(result);
6774 jmpb(COMPARE_WIDE_VECTORS_LOOP);
6775
6776 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6777 bind(VECTOR_NOT_EQUAL);
6778 // clean upper bits of YMM registers
6779 vpxor(vec1, vec1);
6780 lea(str1, Address(str1, result, scale));
6781 lea(str2, Address(str2, result, scale));
6782 jmp(COMPARE_16_CHARS);
6783
6784 // Compare tail chars, length between 1 to 15 chars
6785 bind(COMPARE_TAIL_LONG);
6786 movl(cnt2, result);
6787 cmpl(cnt2, stride);
6788 jccb(Assembler::less, COMPARE_SMALL_STR);
6789
6790 movdqu(vec1, Address(str1, 0));
6791 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6792 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6793 subptr(cnt2, stride);
6794 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6795 lea(str1, Address(str1, result, scale));
6796 lea(str2, Address(str2, result, scale));
6797 negptr(cnt2);
6798 jmpb(WHILE_HEAD_LABEL);
6799
6800 bind(COMPARE_SMALL_STR);
6801 } else if (UseSSE42Intrinsics) {
6802 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6803 int pcmpmask = 0x19;
6804 // Setup to compare 8-char (16-byte) vectors,
6805 // start from first character again because it has aligned address.
6806 movl(result, cnt2);
6807 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6808 jccb(Assembler::zero, COMPARE_TAIL);
6809
6810 lea(str1, Address(str1, result, scale));
6811 lea(str2, Address(str2, result, scale));
6812 negptr(result);
6813
6814 // pcmpestri
6815 // inputs:
6816 // vec1- substring
6817 // rax - negative string length (elements count)
6818 // mem - scaned string
6819 // rdx - string length (elements count)
6820 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6821 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6822 // outputs:
6823 // rcx - first mismatched element index
6824 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6825
6826 bind(COMPARE_WIDE_VECTORS);
6827 movdqu(vec1, Address(str1, result, scale));
6828 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6829 // After pcmpestri cnt1(rcx) contains mismatched element index
6830
6831 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6832 addptr(result, stride);
6833 subptr(cnt2, stride);
6834 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6835
6836 // compare wide vectors tail
6837 testptr(result, result);
6838 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6839
6840 movl(cnt2, stride);
6841 movl(result, stride);
6842 negptr(result);
6843 movdqu(vec1, Address(str1, result, scale));
6844 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6845 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6846
6847 // Mismatched characters in the vectors
6848 bind(VECTOR_NOT_EQUAL);
6849 addptr(cnt1, result);
6850 load_unsigned_short(result, Address(str1, cnt1, scale));
6851 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6852 subl(result, cnt2);
6853 jmpb(POP_LABEL);
6854
6855 bind(COMPARE_TAIL); // limit is zero
6856 movl(cnt2, result);
6857 // Fallthru to tail compare
6858 }
6859 // Shift str2 and str1 to the end of the arrays, negate min
6860 lea(str1, Address(str1, cnt2, scale));
6861 lea(str2, Address(str2, cnt2, scale));
6862 decrementl(cnt2); // first character was compared already
6863 negptr(cnt2);
6864
6865 // Compare the rest of the elements
6866 bind(WHILE_HEAD_LABEL);
6867 load_unsigned_short(result, Address(str1, cnt2, scale, 0));
6868 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
6869 subl(result, cnt1);
6870 jccb(Assembler::notZero, POP_LABEL);
6871 increment(cnt2);
6872 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6873
6874 // Strings are equal up to min length. Return the length difference.
6875 bind(LENGTH_DIFF_LABEL);
6876 pop(result);
6877 jmpb(DONE_LABEL);
6878
6879 // Discard the stored length difference
6880 bind(POP_LABEL);
6881 pop(cnt1);
6882
6883 // That's it
6884 bind(DONE_LABEL);
6885 }
6886
6887 // Compare char[] arrays aligned to 4 bytes or substrings.
6888 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
6889 Register limit, Register result, Register chr,
6890 XMMRegister vec1, XMMRegister vec2) {
6891 ShortBranchVerifier sbv(this);
6892 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
6893
6894 int length_offset = arrayOopDesc::length_offset_in_bytes();
6895 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
6896
6897 // Check the input args
6898 cmpptr(ary1, ary2);
6899 jcc(Assembler::equal, TRUE_LABEL);
6900
6901 if (is_array_equ) {
6902 // Need additional checks for arrays_equals.
6903 testptr(ary1, ary1);
6904 jcc(Assembler::zero, FALSE_LABEL);
6905 testptr(ary2, ary2);
6906 jcc(Assembler::zero, FALSE_LABEL);
6907
6908 // Check the lengths
6909 movl(limit, Address(ary1, length_offset));
6910 cmpl(limit, Address(ary2, length_offset));
6911 jcc(Assembler::notEqual, FALSE_LABEL);
6912 }
6913
6914 // count == 0
6915 testl(limit, limit);
6916 jcc(Assembler::zero, TRUE_LABEL);
6917
6918 if (is_array_equ) {
6919 // Load array address
6920 lea(ary1, Address(ary1, base_offset));
6921 lea(ary2, Address(ary2, base_offset));
6922 }
6923
6924 shll(limit, 1); // byte count != 0
6925 movl(result, limit); // copy
6926
6927 if (UseAVX >= 2) {
6928 // With AVX2, use 32-byte vector compare
6929 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6930
6931 // Compare 32-byte vectors
6932 andl(result, 0x0000001e); // tail count (in bytes)
6933 andl(limit, 0xffffffe0); // vector count (in bytes)
6934 jccb(Assembler::zero, COMPARE_TAIL);
6935
6936 lea(ary1, Address(ary1, limit, Address::times_1));
6937 lea(ary2, Address(ary2, limit, Address::times_1));
6938 negptr(limit);
6939
6940 bind(COMPARE_WIDE_VECTORS);
6941 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
6942 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
6943 vpxor(vec1, vec2);
6944
6945 vptest(vec1, vec1);
6946 jccb(Assembler::notZero, FALSE_LABEL);
6947 addptr(limit, 32);
6948 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6949
6950 testl(result, result);
6951 jccb(Assembler::zero, TRUE_LABEL);
6952
6953 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6954 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
6955 vpxor(vec1, vec2);
6956
6957 vptest(vec1, vec1);
6958 jccb(Assembler::notZero, FALSE_LABEL);
6959 jmpb(TRUE_LABEL);
6960
6961 bind(COMPARE_TAIL); // limit is zero
6962 movl(limit, result);
6963 // Fallthru to tail compare
6964 } else if (UseSSE42Intrinsics) {
6965 // With SSE4.2, use double quad vector compare
6966 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6967
6968 // Compare 16-byte vectors
6969 andl(result, 0x0000000e); // tail count (in bytes)
6970 andl(limit, 0xfffffff0); // vector count (in bytes)
6971 jccb(Assembler::zero, COMPARE_TAIL);
6972
6973 lea(ary1, Address(ary1, limit, Address::times_1));
6974 lea(ary2, Address(ary2, limit, Address::times_1));
6975 negptr(limit);
6976
6977 bind(COMPARE_WIDE_VECTORS);
6978 movdqu(vec1, Address(ary1, limit, Address::times_1));
6979 movdqu(vec2, Address(ary2, limit, Address::times_1));
6980 pxor(vec1, vec2);
6981
6982 ptest(vec1, vec1);
6983 jccb(Assembler::notZero, FALSE_LABEL);
6984 addptr(limit, 16);
6985 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6986
6987 testl(result, result);
6988 jccb(Assembler::zero, TRUE_LABEL);
6989
6990 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
6991 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
6992 pxor(vec1, vec2);
6993
6994 ptest(vec1, vec1);
6995 jccb(Assembler::notZero, FALSE_LABEL);
6996 jmpb(TRUE_LABEL);
6997
6998 bind(COMPARE_TAIL); // limit is zero
6999 movl(limit, result);
7000 // Fallthru to tail compare
7001 }
7002
7003 // Compare 4-byte vectors
7004 andl(limit, 0xfffffffc); // vector count (in bytes)
7005 jccb(Assembler::zero, COMPARE_CHAR);
7006
7007 lea(ary1, Address(ary1, limit, Address::times_1));
7008 lea(ary2, Address(ary2, limit, Address::times_1));
7009 negptr(limit);
7010
7011 bind(COMPARE_VECTORS);
7012 movl(chr, Address(ary1, limit, Address::times_1));
7013 cmpl(chr, Address(ary2, limit, Address::times_1));
7014 jccb(Assembler::notEqual, FALSE_LABEL);
7015 addptr(limit, 4);
7016 jcc(Assembler::notZero, COMPARE_VECTORS);
7017
7018 // Compare trailing char (final 2 bytes), if any
7019 bind(COMPARE_CHAR);
7020 testl(result, 0x2); // tail char
7021 jccb(Assembler::zero, TRUE_LABEL);
7022 load_unsigned_short(chr, Address(ary1, 0));
7023 load_unsigned_short(limit, Address(ary2, 0));
7024 cmpl(chr, limit);
7025 jccb(Assembler::notEqual, FALSE_LABEL);
7026
7027 bind(TRUE_LABEL);
7028 movl(result, 1); // return true
7029 jmpb(DONE);
7030
7031 bind(FALSE_LABEL);
7032 xorl(result, result); // return false
7033
7034 // That's it
7035 bind(DONE);
7036 if (UseAVX >= 2) {
7037 // clean upper bits of YMM registers
7038 vpxor(vec1, vec1);
7039 vpxor(vec2, vec2);
7040 }
7041 }
7042
7043 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7044 Register to, Register value, Register count,
7045 Register rtmp, XMMRegister xtmp) {
7046 ShortBranchVerifier sbv(this);
7047 assert_different_registers(to, value, count, rtmp);
7048 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
7049 Label L_fill_2_bytes, L_fill_4_bytes;
7050
7051 int shift = -1;
7052 switch (t) {
7053 case T_BYTE:
7054 shift = 2;
7055 break;
7056 case T_SHORT:
7057 shift = 1;
7058 break;
7059 case T_INT:
7060 shift = 0;
7061 break;
7062 default: ShouldNotReachHere();
7063 }
7064
7065 if (t == T_BYTE) {
7066 andl(value, 0xff);
7067 movl(rtmp, value);
7068 shll(rtmp, 8);
7069 orl(value, rtmp);
7070 }
7071 if (t == T_SHORT) {
7072 andl(value, 0xffff);
7073 }
7074 if (t == T_BYTE || t == T_SHORT) {
7075 movl(rtmp, value);
7076 shll(rtmp, 16);
7077 orl(value, rtmp);
7078 }
7079
7080 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7081 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7082 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7083 // align source address at 4 bytes address boundary
7084 if (t == T_BYTE) {
7085 // One byte misalignment happens only for byte arrays
7086 testptr(to, 1);
7087 jccb(Assembler::zero, L_skip_align1);
7088 movb(Address(to, 0), value);
7089 increment(to);
7090 decrement(count);
7091 BIND(L_skip_align1);
7092 }
7093 // Two bytes misalignment happens only for byte and short (char) arrays
7094 testptr(to, 2);
7095 jccb(Assembler::zero, L_skip_align2);
7096 movw(Address(to, 0), value);
7097 addptr(to, 2);
7098 subl(count, 1<<(shift-1));
7099 BIND(L_skip_align2);
7100 }
7101 if (UseSSE < 2) {
7102 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7103 // Fill 32-byte chunks
7104 subl(count, 8 << shift);
7105 jcc(Assembler::less, L_check_fill_8_bytes);
7106 align(16);
7107
7108 BIND(L_fill_32_bytes_loop);
7109
7110 for (int i = 0; i < 32; i += 4) {
7111 movl(Address(to, i), value);
7112 }
7113
7114 addptr(to, 32);
7115 subl(count, 8 << shift);
7116 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7117 BIND(L_check_fill_8_bytes);
7118 addl(count, 8 << shift);
7119 jccb(Assembler::zero, L_exit);
7120 jmpb(L_fill_8_bytes);
7121
7122 //
7123 // length is too short, just fill qwords
7124 //
7125 BIND(L_fill_8_bytes_loop);
7126 movl(Address(to, 0), value);
7127 movl(Address(to, 4), value);
7128 addptr(to, 8);
7129 BIND(L_fill_8_bytes);
7130 subl(count, 1 << (shift + 1));
7131 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7132 // fall through to fill 4 bytes
7133 } else {
7134 Label L_fill_32_bytes;
7135 if (!UseUnalignedLoadStores) {
7136 // align to 8 bytes, we know we are 4 byte aligned to start
7137 testptr(to, 4);
7138 jccb(Assembler::zero, L_fill_32_bytes);
7139 movl(Address(to, 0), value);
7140 addptr(to, 4);
7141 subl(count, 1<<shift);
7142 }
7143 BIND(L_fill_32_bytes);
7144 {
7145 assert( UseSSE >= 2, "supported cpu only" );
7146 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7147 movdl(xtmp, value);
7148 if (UseAVX >= 2 && UseUnalignedLoadStores) {
7149 // Fill 64-byte chunks
7150 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7151 vpbroadcastd(xtmp, xtmp);
7152
7153 subl(count, 16 << shift);
7154 jcc(Assembler::less, L_check_fill_32_bytes);
7155 align(16);
7156
7157 BIND(L_fill_64_bytes_loop);
7158 vmovdqu(Address(to, 0), xtmp);
7159 vmovdqu(Address(to, 32), xtmp);
7160 addptr(to, 64);
7161 subl(count, 16 << shift);
7162 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7163
7164 BIND(L_check_fill_32_bytes);
7165 addl(count, 8 << shift);
7166 jccb(Assembler::less, L_check_fill_8_bytes);
7167 vmovdqu(Address(to, 0), xtmp);
7168 addptr(to, 32);
7169 subl(count, 8 << shift);
7170
7171 BIND(L_check_fill_8_bytes);
7172 // clean upper bits of YMM registers
7173 movdl(xtmp, value);
7174 pshufd(xtmp, xtmp, 0);
7175 } else {
7176 // Fill 32-byte chunks
7177 pshufd(xtmp, xtmp, 0);
7178
7179 subl(count, 8 << shift);
7180 jcc(Assembler::less, L_check_fill_8_bytes);
7181 align(16);
7182
7183 BIND(L_fill_32_bytes_loop);
7184
7185 if (UseUnalignedLoadStores) {
7186 movdqu(Address(to, 0), xtmp);
7187 movdqu(Address(to, 16), xtmp);
7188 } else {
7189 movq(Address(to, 0), xtmp);
7190 movq(Address(to, 8), xtmp);
7191 movq(Address(to, 16), xtmp);
7192 movq(Address(to, 24), xtmp);
7193 }
7194
7195 addptr(to, 32);
7196 subl(count, 8 << shift);
7197 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7198
7199 BIND(L_check_fill_8_bytes);
7200 }
7201 addl(count, 8 << shift);
7202 jccb(Assembler::zero, L_exit);
7203 jmpb(L_fill_8_bytes);
7204
7205 //
7206 // length is too short, just fill qwords
7207 //
7208 BIND(L_fill_8_bytes_loop);
7209 movq(Address(to, 0), xtmp);
7210 addptr(to, 8);
7211 BIND(L_fill_8_bytes);
7212 subl(count, 1 << (shift + 1));
7213 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7214 }
7215 }
7216 // fill trailing 4 bytes
7217 BIND(L_fill_4_bytes);
7218 testl(count, 1<<shift);
7219 jccb(Assembler::zero, L_fill_2_bytes);
7220 movl(Address(to, 0), value);
7221 if (t == T_BYTE || t == T_SHORT) {
7222 addptr(to, 4);
7223 BIND(L_fill_2_bytes);
7224 // fill trailing 2 bytes
7225 testl(count, 1<<(shift-1));
7226 jccb(Assembler::zero, L_fill_byte);
7227 movw(Address(to, 0), value);
7228 if (t == T_BYTE) {
7229 addptr(to, 2);
7230 BIND(L_fill_byte);
7231 // fill trailing byte
7232 testl(count, 1);
7233 jccb(Assembler::zero, L_exit);
7234 movb(Address(to, 0), value);
7235 } else {
7236 BIND(L_fill_byte);
7237 }
7238 } else {
7239 BIND(L_fill_2_bytes);
7240 }
7241 BIND(L_exit);
7242 }
7243
7244 // encode char[] to byte[] in ISO_8859_1
7245 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7246 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7247 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7248 Register tmp5, Register result) {
7249 // rsi: src
7250 // rdi: dst
7251 // rdx: len
7252 // rcx: tmp5
7253 // rax: result
7254 ShortBranchVerifier sbv(this);
7255 assert_different_registers(src, dst, len, tmp5, result);
7256 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7257
7258 // set result
7259 xorl(result, result);
7260 // check for zero length
7261 testl(len, len);
7262 jcc(Assembler::zero, L_done);
7263 movl(result, len);
7264
7265 // Setup pointers
7266 lea(src, Address(src, len, Address::times_2)); // char[]
7267 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7268 negptr(len);
7269
7270 if (UseSSE42Intrinsics || UseAVX >= 2) {
7271 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
7272 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7273
7274 if (UseAVX >= 2) {
7275 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7276 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7277 movdl(tmp1Reg, tmp5);
7278 vpbroadcastd(tmp1Reg, tmp1Reg);
7279 jmpb(L_chars_32_check);
7280
7281 bind(L_copy_32_chars);
7282 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7283 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7284 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7285 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7286 jccb(Assembler::notZero, L_copy_32_chars_exit);
7287 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7288 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector256 */ true);
7289 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7290
7291 bind(L_chars_32_check);
7292 addptr(len, 32);
7293 jccb(Assembler::lessEqual, L_copy_32_chars);
7294
7295 bind(L_copy_32_chars_exit);
7296 subptr(len, 16);
7297 jccb(Assembler::greater, L_copy_16_chars_exit);
7298
7299 } else if (UseSSE42Intrinsics) {
7300 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7301 movdl(tmp1Reg, tmp5);
7302 pshufd(tmp1Reg, tmp1Reg, 0);
7303 jmpb(L_chars_16_check);
7304 }
7305
7306 bind(L_copy_16_chars);
7307 if (UseAVX >= 2) {
7308 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7309 vptest(tmp2Reg, tmp1Reg);
7310 jccb(Assembler::notZero, L_copy_16_chars_exit);
7311 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector256 */ true);
7312 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector256 */ true);
7313 } else {
7314 if (UseAVX > 0) {
7315 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7316 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7317 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ false);
7318 } else {
7319 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7320 por(tmp2Reg, tmp3Reg);
7321 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7322 por(tmp2Reg, tmp4Reg);
7323 }
7324 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7325 jccb(Assembler::notZero, L_copy_16_chars_exit);
7326 packuswb(tmp3Reg, tmp4Reg);
7327 }
7328 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7329
7330 bind(L_chars_16_check);
7331 addptr(len, 16);
7332 jccb(Assembler::lessEqual, L_copy_16_chars);
7333
7334 bind(L_copy_16_chars_exit);
7335 if (UseAVX >= 2) {
7336 // clean upper bits of YMM registers
7337 vpxor(tmp2Reg, tmp2Reg);
7338 vpxor(tmp3Reg, tmp3Reg);
7339 vpxor(tmp4Reg, tmp4Reg);
7340 movdl(tmp1Reg, tmp5);
7341 pshufd(tmp1Reg, tmp1Reg, 0);
7342 }
7343 subptr(len, 8);
7344 jccb(Assembler::greater, L_copy_8_chars_exit);
7345
7346 bind(L_copy_8_chars);
7347 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7348 ptest(tmp3Reg, tmp1Reg);
7349 jccb(Assembler::notZero, L_copy_8_chars_exit);
7350 packuswb(tmp3Reg, tmp1Reg);
7351 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7352 addptr(len, 8);
7353 jccb(Assembler::lessEqual, L_copy_8_chars);
7354
7355 bind(L_copy_8_chars_exit);
7356 subptr(len, 8);
7357 jccb(Assembler::zero, L_done);
7358 }
7359
7360 bind(L_copy_1_char);
7361 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7362 testl(tmp5, 0xff00); // check if Unicode char
7363 jccb(Assembler::notZero, L_copy_1_char_exit);
7364 movb(Address(dst, len, Address::times_1, 0), tmp5);
7365 addptr(len, 1);
7366 jccb(Assembler::less, L_copy_1_char);
7367
7368 bind(L_copy_1_char_exit);
7369 addptr(result, len); // len is negative count of not processed elements
7370 bind(L_done);
7371 }
7372
7373 #ifdef _LP64
7374 /**
7375 * Helper for multiply_to_len().
7376 */
7377 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7378 addq(dest_lo, src1);
7379 adcq(dest_hi, 0);
7380 addq(dest_lo, src2);
7381 adcq(dest_hi, 0);
7382 }
7383
7384 /**
7385 * Multiply 64 bit by 64 bit first loop.
7386 */
7387 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7388 Register y, Register y_idx, Register z,
7389 Register carry, Register product,
7390 Register idx, Register kdx) {
7391 //
7392 // jlong carry, x[], y[], z[];
7393 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7394 // huge_128 product = y[idx] * x[xstart] + carry;
7395 // z[kdx] = (jlong)product;
7396 // carry = (jlong)(product >>> 64);
7397 // }
7398 // z[xstart] = carry;
7399 //
7400
7401 Label L_first_loop, L_first_loop_exit;
7402 Label L_one_x, L_one_y, L_multiply;
7403
7404 decrementl(xstart);
7405 jcc(Assembler::negative, L_one_x);
7406
7407 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7408 rorq(x_xstart, 32); // convert big-endian to little-endian
7409
7410 bind(L_first_loop);
7411 decrementl(idx);
7412 jcc(Assembler::negative, L_first_loop_exit);
7413 decrementl(idx);
7414 jcc(Assembler::negative, L_one_y);
7415 movq(y_idx, Address(y, idx, Address::times_4, 0));
7416 rorq(y_idx, 32); // convert big-endian to little-endian
7417 bind(L_multiply);
7418 movq(product, x_xstart);
7419 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7420 addq(product, carry);
7421 adcq(rdx, 0);
7422 subl(kdx, 2);
7423 movl(Address(z, kdx, Address::times_4, 4), product);
7424 shrq(product, 32);
7425 movl(Address(z, kdx, Address::times_4, 0), product);
7426 movq(carry, rdx);
7427 jmp(L_first_loop);
7428
7429 bind(L_one_y);
7430 movl(y_idx, Address(y, 0));
7431 jmp(L_multiply);
7432
7433 bind(L_one_x);
7434 movl(x_xstart, Address(x, 0));
7435 jmp(L_first_loop);
7436
7437 bind(L_first_loop_exit);
7438 }
7439
7440 /**
7441 * Multiply 64 bit by 64 bit and add 128 bit.
7442 */
7443 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7444 Register yz_idx, Register idx,
7445 Register carry, Register product, int offset) {
7446 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7447 // z[kdx] = (jlong)product;
7448
7449 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7450 rorq(yz_idx, 32); // convert big-endian to little-endian
7451 movq(product, x_xstart);
7452 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7453 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7454 rorq(yz_idx, 32); // convert big-endian to little-endian
7455
7456 add2_with_carry(rdx, product, carry, yz_idx);
7457
7458 movl(Address(z, idx, Address::times_4, offset+4), product);
7459 shrq(product, 32);
7460 movl(Address(z, idx, Address::times_4, offset), product);
7461
7462 }
7463
7464 /**
7465 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7466 */
7467 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7468 Register yz_idx, Register idx, Register jdx,
7469 Register carry, Register product,
7470 Register carry2) {
7471 // jlong carry, x[], y[], z[];
7472 // int kdx = ystart+1;
7473 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7474 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7475 // z[kdx+idx+1] = (jlong)product;
7476 // jlong carry2 = (jlong)(product >>> 64);
7477 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7478 // z[kdx+idx] = (jlong)product;
7479 // carry = (jlong)(product >>> 64);
7480 // }
7481 // idx += 2;
7482 // if (idx > 0) {
7483 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7484 // z[kdx+idx] = (jlong)product;
7485 // carry = (jlong)(product >>> 64);
7486 // }
7487 //
7488
7489 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7490
7491 movl(jdx, idx);
7492 andl(jdx, 0xFFFFFFFC);
7493 shrl(jdx, 2);
7494
7495 bind(L_third_loop);
7496 subl(jdx, 1);
7497 jcc(Assembler::negative, L_third_loop_exit);
7498 subl(idx, 4);
7499
7500 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7501 movq(carry2, rdx);
7502
7503 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7504 movq(carry, rdx);
7505 jmp(L_third_loop);
7506
7507 bind (L_third_loop_exit);
7508
7509 andl (idx, 0x3);
7510 jcc(Assembler::zero, L_post_third_loop_done);
7511
7512 Label L_check_1;
7513 subl(idx, 2);
7514 jcc(Assembler::negative, L_check_1);
7515
7516 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7517 movq(carry, rdx);
7518
7519 bind (L_check_1);
7520 addl (idx, 0x2);
7521 andl (idx, 0x1);
7522 subl(idx, 1);
7523 jcc(Assembler::negative, L_post_third_loop_done);
7524
7525 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7526 movq(product, x_xstart);
7527 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7528 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7529
7530 add2_with_carry(rdx, product, yz_idx, carry);
7531
7532 movl(Address(z, idx, Address::times_4, 0), product);
7533 shrq(product, 32);
7534
7535 shlq(rdx, 32);
7536 orq(product, rdx);
7537 movq(carry, product);
7538
7539 bind(L_post_third_loop_done);
7540 }
7541
7542 /**
7543 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7544 *
7545 */
7546 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7547 Register carry, Register carry2,
7548 Register idx, Register jdx,
7549 Register yz_idx1, Register yz_idx2,
7550 Register tmp, Register tmp3, Register tmp4) {
7551 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7552
7553 // jlong carry, x[], y[], z[];
7554 // int kdx = ystart+1;
7555 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7556 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7557 // jlong carry2 = (jlong)(tmp3 >>> 64);
7558 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7559 // carry = (jlong)(tmp4 >>> 64);
7560 // z[kdx+idx+1] = (jlong)tmp3;
7561 // z[kdx+idx] = (jlong)tmp4;
7562 // }
7563 // idx += 2;
7564 // if (idx > 0) {
7565 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7566 // z[kdx+idx] = (jlong)yz_idx1;
7567 // carry = (jlong)(yz_idx1 >>> 64);
7568 // }
7569 //
7570
7571 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7572
7573 movl(jdx, idx);
7574 andl(jdx, 0xFFFFFFFC);
7575 shrl(jdx, 2);
7576
7577 bind(L_third_loop);
7578 subl(jdx, 1);
7579 jcc(Assembler::negative, L_third_loop_exit);
7580 subl(idx, 4);
7581
7582 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7583 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7584 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7585 rorxq(yz_idx2, yz_idx2, 32);
7586
7587 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7588 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7589
7590 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7591 rorxq(yz_idx1, yz_idx1, 32);
7592 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7593 rorxq(yz_idx2, yz_idx2, 32);
7594
7595 if (VM_Version::supports_adx()) {
7596 adcxq(tmp3, carry);
7597 adoxq(tmp3, yz_idx1);
7598
7599 adcxq(tmp4, tmp);
7600 adoxq(tmp4, yz_idx2);
7601
7602 movl(carry, 0); // does not affect flags
7603 adcxq(carry2, carry);
7604 adoxq(carry2, carry);
7605 } else {
7606 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7607 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7608 }
7609 movq(carry, carry2);
7610
7611 movl(Address(z, idx, Address::times_4, 12), tmp3);
7612 shrq(tmp3, 32);
7613 movl(Address(z, idx, Address::times_4, 8), tmp3);
7614
7615 movl(Address(z, idx, Address::times_4, 4), tmp4);
7616 shrq(tmp4, 32);
7617 movl(Address(z, idx, Address::times_4, 0), tmp4);
7618
7619 jmp(L_third_loop);
7620
7621 bind (L_third_loop_exit);
7622
7623 andl (idx, 0x3);
7624 jcc(Assembler::zero, L_post_third_loop_done);
7625
7626 Label L_check_1;
7627 subl(idx, 2);
7628 jcc(Assembler::negative, L_check_1);
7629
7630 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7631 rorxq(yz_idx1, yz_idx1, 32);
7632 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7633 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7634 rorxq(yz_idx2, yz_idx2, 32);
7635
7636 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7637
7638 movl(Address(z, idx, Address::times_4, 4), tmp3);
7639 shrq(tmp3, 32);
7640 movl(Address(z, idx, Address::times_4, 0), tmp3);
7641 movq(carry, tmp4);
7642
7643 bind (L_check_1);
7644 addl (idx, 0x2);
7645 andl (idx, 0x1);
7646 subl(idx, 1);
7647 jcc(Assembler::negative, L_post_third_loop_done);
7648 movl(tmp4, Address(y, idx, Address::times_4, 0));
7649 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7650 movl(tmp4, Address(z, idx, Address::times_4, 0));
7651
7652 add2_with_carry(carry2, tmp3, tmp4, carry);
7653
7654 movl(Address(z, idx, Address::times_4, 0), tmp3);
7655 shrq(tmp3, 32);
7656
7657 shlq(carry2, 32);
7658 orq(tmp3, carry2);
7659 movq(carry, tmp3);
7660
7661 bind(L_post_third_loop_done);
7662 }
7663
7664 /**
7665 * Code for BigInteger::multiplyToLen() instrinsic.
7666 *
7667 * rdi: x
7668 * rax: xlen
7669 * rsi: y
7670 * rcx: ylen
7671 * r8: z
7672 * r11: zlen
7673 * r12: tmp1
7674 * r13: tmp2
7675 * r14: tmp3
7676 * r15: tmp4
7677 * rbx: tmp5
7678 *
7679 */
7680 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7681 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7682 ShortBranchVerifier sbv(this);
7683 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7684
7685 push(tmp1);
7686 push(tmp2);
7687 push(tmp3);
7688 push(tmp4);
7689 push(tmp5);
7690
7691 push(xlen);
7692 push(zlen);
7693
7694 const Register idx = tmp1;
7695 const Register kdx = tmp2;
7696 const Register xstart = tmp3;
7697
7698 const Register y_idx = tmp4;
7699 const Register carry = tmp5;
7700 const Register product = xlen;
7701 const Register x_xstart = zlen; // reuse register
7702
7703 // First Loop.
7704 //
7705 // final static long LONG_MASK = 0xffffffffL;
7706 // int xstart = xlen - 1;
7707 // int ystart = ylen - 1;
7708 // long carry = 0;
7709 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7710 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7711 // z[kdx] = (int)product;
7712 // carry = product >>> 32;
7713 // }
7714 // z[xstart] = (int)carry;
7715 //
7716
7717 movl(idx, ylen); // idx = ylen;
7718 movl(kdx, zlen); // kdx = xlen+ylen;
7719 xorq(carry, carry); // carry = 0;
7720
7721 Label L_done;
7722
7723 movl(xstart, xlen);
7724 decrementl(xstart);
7725 jcc(Assembler::negative, L_done);
7726
7727 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7728
7729 Label L_second_loop;
7730 testl(kdx, kdx);
7731 jcc(Assembler::zero, L_second_loop);
7732
7733 Label L_carry;
7734 subl(kdx, 1);
7735 jcc(Assembler::zero, L_carry);
7736
7737 movl(Address(z, kdx, Address::times_4, 0), carry);
7738 shrq(carry, 32);
7739 subl(kdx, 1);
7740
7741 bind(L_carry);
7742 movl(Address(z, kdx, Address::times_4, 0), carry);
7743
7744 // Second and third (nested) loops.
7745 //
7746 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7747 // carry = 0;
7748 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7749 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7750 // (z[k] & LONG_MASK) + carry;
7751 // z[k] = (int)product;
7752 // carry = product >>> 32;
7753 // }
7754 // z[i] = (int)carry;
7755 // }
7756 //
7757 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7758
7759 const Register jdx = tmp1;
7760
7761 bind(L_second_loop);
7762 xorl(carry, carry); // carry = 0;
7763 movl(jdx, ylen); // j = ystart+1
7764
7765 subl(xstart, 1); // i = xstart-1;
7766 jcc(Assembler::negative, L_done);
7767
7768 push (z);
7769
7770 Label L_last_x;
7771 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7772 subl(xstart, 1); // i = xstart-1;
7773 jcc(Assembler::negative, L_last_x);
7774
7775 if (UseBMI2Instructions) {
7776 movq(rdx, Address(x, xstart, Address::times_4, 0));
7777 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7778 } else {
7779 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7780 rorq(x_xstart, 32); // convert big-endian to little-endian
7781 }
7782
7783 Label L_third_loop_prologue;
7784 bind(L_third_loop_prologue);
7785
7786 push (x);
7787 push (xstart);
7788 push (ylen);
7789
7790
7791 if (UseBMI2Instructions) {
7792 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7793 } else { // !UseBMI2Instructions
7794 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7795 }
7796
7797 pop(ylen);
7798 pop(xlen);
7799 pop(x);
7800 pop(z);
7801
7802 movl(tmp3, xlen);
7803 addl(tmp3, 1);
7804 movl(Address(z, tmp3, Address::times_4, 0), carry);
7805 subl(tmp3, 1);
7806 jccb(Assembler::negative, L_done);
7807
7808 shrq(carry, 32);
7809 movl(Address(z, tmp3, Address::times_4, 0), carry);
7810 jmp(L_second_loop);
7811
7812 // Next infrequent code is moved outside loops.
7813 bind(L_last_x);
7814 if (UseBMI2Instructions) {
7815 movl(rdx, Address(x, 0));
7816 } else {
7817 movl(x_xstart, Address(x, 0));
7818 }
7819 jmp(L_third_loop_prologue);
7820
7821 bind(L_done);
7822
7823 pop(zlen);
7824 pop(xlen);
7825
7826 pop(tmp5);
7827 pop(tmp4);
7828 pop(tmp3);
7829 pop(tmp2);
7830 pop(tmp1);
7831 }
7832
7833 //Helper functions for square_to_len()
7834
7835 /**
7836 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7837 * Preserves x and z and modifies rest of the registers.
7838 */
7839
7840 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7841 // Perform square and right shift by 1
7842 // Handle odd xlen case first, then for even xlen do the following
7843 // jlong carry = 0;
7844 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7845 // huge_128 product = x[j:j+1] * x[j:j+1];
7846 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7847 // z[i+2:i+3] = (jlong)(product >>> 1);
7848 // carry = (jlong)product;
7849 // }
7850
7851 xorq(tmp5, tmp5); // carry
7852 xorq(rdxReg, rdxReg);
7853 xorl(tmp1, tmp1); // index for x
7854 xorl(tmp4, tmp4); // index for z
7855
7856 Label L_first_loop, L_first_loop_exit;
7857
7858 testl(xlen, 1);
7859 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7860
7861 // Square and right shift by 1 the odd element using 32 bit multiply
7862 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7863 imulq(raxReg, raxReg);
7864 shrq(raxReg, 1);
7865 adcq(tmp5, 0);
7866 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7867 incrementl(tmp1);
7868 addl(tmp4, 2);
7869
7870 // Square and right shift by 1 the rest using 64 bit multiply
7871 bind(L_first_loop);
7872 cmpptr(tmp1, xlen);
7873 jccb(Assembler::equal, L_first_loop_exit);
7874
7875 // Square
7876 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7877 rorq(raxReg, 32); // convert big-endian to little-endian
7878 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7879
7880 // Right shift by 1 and save carry
7881 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7882 rcrq(rdxReg, 1);
7883 rcrq(raxReg, 1);
7884 adcq(tmp5, 0);
7885
7886 // Store result in z
7887 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7888 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7889
7890 // Update indices for x and z
7891 addl(tmp1, 2);
7892 addl(tmp4, 4);
7893 jmp(L_first_loop);
7894
7895 bind(L_first_loop_exit);
7896 }
7897
7898
7899 /**
7900 * Perform the following multiply add operation using BMI2 instructions
7901 * carry:sum = sum + op1*op2 + carry
7902 * op2 should be in rdx
7903 * op2 is preserved, all other registers are modified
7904 */
7905 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7906 // assert op2 is rdx
7907 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7908 addq(sum, carry);
7909 adcq(tmp2, 0);
7910 addq(sum, op1);
7911 adcq(tmp2, 0);
7912 movq(carry, tmp2);
7913 }
7914
7915 /**
7916 * Perform the following multiply add operation:
7917 * carry:sum = sum + op1*op2 + carry
7918 * Preserves op1, op2 and modifies rest of registers
7919 */
7920 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7921 // rdx:rax = op1 * op2
7922 movq(raxReg, op2);
7923 mulq(op1);
7924
7925 // rdx:rax = sum + carry + rdx:rax
7926 addq(sum, carry);
7927 adcq(rdxReg, 0);
7928 addq(sum, raxReg);
7929 adcq(rdxReg, 0);
7930
7931 // carry:sum = rdx:sum
7932 movq(carry, rdxReg);
7933 }
7934
7935 /**
7936 * Add 64 bit long carry into z[] with carry propogation.
7937 * Preserves z and carry register values and modifies rest of registers.
7938 *
7939 */
7940 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7941 Label L_fourth_loop, L_fourth_loop_exit;
7942
7943 movl(tmp1, 1);
7944 subl(zlen, 2);
7945 addq(Address(z, zlen, Address::times_4, 0), carry);
7946
7947 bind(L_fourth_loop);
7948 jccb(Assembler::carryClear, L_fourth_loop_exit);
7949 subl(zlen, 2);
7950 jccb(Assembler::negative, L_fourth_loop_exit);
7951 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7952 jmp(L_fourth_loop);
7953 bind(L_fourth_loop_exit);
7954 }
7955
7956 /**
7957 * Shift z[] left by 1 bit.
7958 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7959 *
7960 */
7961 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7962
7963 Label L_fifth_loop, L_fifth_loop_exit;
7964
7965 // Fifth loop
7966 // Perform primitiveLeftShift(z, zlen, 1)
7967
7968 const Register prev_carry = tmp1;
7969 const Register new_carry = tmp4;
7970 const Register value = tmp2;
7971 const Register zidx = tmp3;
7972
7973 // int zidx, carry;
7974 // long value;
7975 // carry = 0;
7976 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7977 // (carry:value) = (z[i] << 1) | carry ;
7978 // z[i] = value;
7979 // }
7980
7981 movl(zidx, zlen);
7982 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7983
7984 bind(L_fifth_loop);
7985 decl(zidx); // Use decl to preserve carry flag
7986 decl(zidx);
7987 jccb(Assembler::negative, L_fifth_loop_exit);
7988
7989 if (UseBMI2Instructions) {
7990 movq(value, Address(z, zidx, Address::times_4, 0));
7991 rclq(value, 1);
7992 rorxq(value, value, 32);
7993 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7994 }
7995 else {
7996 // clear new_carry
7997 xorl(new_carry, new_carry);
7998
7999 // Shift z[i] by 1, or in previous carry and save new carry
8000 movq(value, Address(z, zidx, Address::times_4, 0));
8001 shlq(value, 1);
8002 adcl(new_carry, 0);
8003
8004 orq(value, prev_carry);
8005 rorq(value, 0x20);
8006 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8007
8008 // Set previous carry = new carry
8009 movl(prev_carry, new_carry);
8010 }
8011 jmp(L_fifth_loop);
8012
8013 bind(L_fifth_loop_exit);
8014 }
8015
8016
8017 /**
8018 * Code for BigInteger::squareToLen() intrinsic
8019 *
8020 * rdi: x
8021 * rsi: len
8022 * r8: z
8023 * rcx: zlen
8024 * r12: tmp1
8025 * r13: tmp2
8026 * r14: tmp3
8027 * r15: tmp4
8028 * rbx: tmp5
8029 *
8030 */
8031 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8032
8033 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
8034 push(tmp1);
8035 push(tmp2);
8036 push(tmp3);
8037 push(tmp4);
8038 push(tmp5);
8039
8040 // First loop
8041 // Store the squares, right shifted one bit (i.e., divided by 2).
8042 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8043
8044 // Add in off-diagonal sums.
8045 //
8046 // Second, third (nested) and fourth loops.
8047 // zlen +=2;
8048 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8049 // carry = 0;
8050 // long op2 = x[xidx:xidx+1];
8051 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8052 // k -= 2;
8053 // long op1 = x[j:j+1];
8054 // long sum = z[k:k+1];
8055 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8056 // z[k:k+1] = sum;
8057 // }
8058 // add_one_64(z, k, carry, tmp_regs);
8059 // }
8060
8061 const Register carry = tmp5;
8062 const Register sum = tmp3;
8063 const Register op1 = tmp4;
8064 Register op2 = tmp2;
8065
8066 push(zlen);
8067 push(len);
8068 addl(zlen,2);
8069 bind(L_second_loop);
8070 xorq(carry, carry);
8071 subl(zlen, 4);
8072 subl(len, 2);
8073 push(zlen);
8074 push(len);
8075 cmpl(len, 0);
8076 jccb(Assembler::lessEqual, L_second_loop_exit);
8077
8078 // Multiply an array by one 64 bit long.
8079 if (UseBMI2Instructions) {
8080 op2 = rdxReg;
8081 movq(op2, Address(x, len, Address::times_4, 0));
8082 rorxq(op2, op2, 32);
8083 }
8084 else {
8085 movq(op2, Address(x, len, Address::times_4, 0));
8086 rorq(op2, 32);
8087 }
8088
8089 bind(L_third_loop);
8090 decrementl(len);
8091 jccb(Assembler::negative, L_third_loop_exit);
8092 decrementl(len);
8093 jccb(Assembler::negative, L_last_x);
8094
8095 movq(op1, Address(x, len, Address::times_4, 0));
8096 rorq(op1, 32);
8097
8098 bind(L_multiply);
8099 subl(zlen, 2);
8100 movq(sum, Address(z, zlen, Address::times_4, 0));
8101
8102 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8103 if (UseBMI2Instructions) {
8104 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8105 }
8106 else {
8107 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8108 }
8109
8110 movq(Address(z, zlen, Address::times_4, 0), sum);
8111
8112 jmp(L_third_loop);
8113 bind(L_third_loop_exit);
8114
8115 // Fourth loop
8116 // Add 64 bit long carry into z with carry propogation.
8117 // Uses offsetted zlen.
8118 add_one_64(z, zlen, carry, tmp1);
8119
8120 pop(len);
8121 pop(zlen);
8122 jmp(L_second_loop);
8123
8124 // Next infrequent code is moved outside loops.
8125 bind(L_last_x);
8126 movl(op1, Address(x, 0));
8127 jmp(L_multiply);
8128
8129 bind(L_second_loop_exit);
8130 pop(len);
8131 pop(zlen);
8132 pop(len);
8133 pop(zlen);
8134
8135 // Fifth loop
8136 // Shift z left 1 bit.
8137 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8138
8139 // z[zlen-1] |= x[len-1] & 1;
8140 movl(tmp3, Address(x, len, Address::times_4, -4));
8141 andl(tmp3, 1);
8142 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8143
8144 pop(tmp5);
8145 pop(tmp4);
8146 pop(tmp3);
8147 pop(tmp2);
8148 pop(tmp1);
8149 }
8150
8151 /**
8152 * Helper function for mul_add()
8153 * Multiply the in[] by int k and add to out[] starting at offset offs using
8154 * 128 bit by 32 bit multiply and return the carry in tmp5.
8155 * Only quad int aligned length of in[] is operated on in this function.
8156 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8157 * This function preserves out, in and k registers.
8158 * len and offset point to the appropriate index in "in" & "out" correspondingly
8159 * tmp5 has the carry.
8160 * other registers are temporary and are modified.
8161 *
8162 */
8163 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8164 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8165 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8166
8167 Label L_first_loop, L_first_loop_exit;
8168
8169 movl(tmp1, len);
8170 shrl(tmp1, 2);
8171
8172 bind(L_first_loop);
8173 subl(tmp1, 1);
8174 jccb(Assembler::negative, L_first_loop_exit);
8175
8176 subl(len, 4);
8177 subl(offset, 4);
8178
8179 Register op2 = tmp2;
8180 const Register sum = tmp3;
8181 const Register op1 = tmp4;
8182 const Register carry = tmp5;
8183
8184 if (UseBMI2Instructions) {
8185 op2 = rdxReg;
8186 }
8187
8188 movq(op1, Address(in, len, Address::times_4, 8));
8189 rorq(op1, 32);
8190 movq(sum, Address(out, offset, Address::times_4, 8));
8191 rorq(sum, 32);
8192 if (UseBMI2Instructions) {
8193 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8194 }
8195 else {
8196 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8197 }
8198 // Store back in big endian from little endian
8199 rorq(sum, 0x20);
8200 movq(Address(out, offset, Address::times_4, 8), sum);
8201
8202 movq(op1, Address(in, len, Address::times_4, 0));
8203 rorq(op1, 32);
8204 movq(sum, Address(out, offset, Address::times_4, 0));
8205 rorq(sum, 32);
8206 if (UseBMI2Instructions) {
8207 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8208 }
8209 else {
8210 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8211 }
8212 // Store back in big endian from little endian
8213 rorq(sum, 0x20);
8214 movq(Address(out, offset, Address::times_4, 0), sum);
8215
8216 jmp(L_first_loop);
8217 bind(L_first_loop_exit);
8218 }
8219
8220 /**
8221 * Code for BigInteger::mulAdd() intrinsic
8222 *
8223 * rdi: out
8224 * rsi: in
8225 * r11: offs (out.length - offset)
8226 * rcx: len
8227 * r8: k
8228 * r12: tmp1
8229 * r13: tmp2
8230 * r14: tmp3
8231 * r15: tmp4
8232 * rbx: tmp5
8233 * Multiply the in[] by word k and add to out[], return the carry in rax
8234 */
8235 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8236 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8237 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8238
8239 Label L_carry, L_last_in, L_done;
8240
8241 // carry = 0;
8242 // for (int j=len-1; j >= 0; j--) {
8243 // long product = (in[j] & LONG_MASK) * kLong +
8244 // (out[offs] & LONG_MASK) + carry;
8245 // out[offs--] = (int)product;
8246 // carry = product >>> 32;
8247 // }
8248 //
8249 push(tmp1);
8250 push(tmp2);
8251 push(tmp3);
8252 push(tmp4);
8253 push(tmp5);
8254
8255 Register op2 = tmp2;
8256 const Register sum = tmp3;
8257 const Register op1 = tmp4;
8258 const Register carry = tmp5;
8259
8260 if (UseBMI2Instructions) {
8261 op2 = rdxReg;
8262 movl(op2, k);
8263 }
8264 else {
8265 movl(op2, k);
8266 }
8267
8268 xorq(carry, carry);
8269
8270 //First loop
8271
8272 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8273 //The carry is in tmp5
8274 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8275
8276 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8277 decrementl(len);
8278 jccb(Assembler::negative, L_carry);
8279 decrementl(len);
8280 jccb(Assembler::negative, L_last_in);
8281
8282 movq(op1, Address(in, len, Address::times_4, 0));
8283 rorq(op1, 32);
8284
8285 subl(offs, 2);
8286 movq(sum, Address(out, offs, Address::times_4, 0));
8287 rorq(sum, 32);
8288
8289 if (UseBMI2Instructions) {
8290 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8291 }
8292 else {
8293 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8294 }
8295
8296 // Store back in big endian from little endian
8297 rorq(sum, 0x20);
8298 movq(Address(out, offs, Address::times_4, 0), sum);
8299
8300 testl(len, len);
8301 jccb(Assembler::zero, L_carry);
8302
8303 //Multiply the last in[] entry, if any
8304 bind(L_last_in);
8305 movl(op1, Address(in, 0));
8306 movl(sum, Address(out, offs, Address::times_4, -4));
8307
8308 movl(raxReg, k);
8309 mull(op1); //tmp4 * eax -> edx:eax
8310 addl(sum, carry);
8311 adcl(rdxReg, 0);
8312 addl(sum, raxReg);
8313 adcl(rdxReg, 0);
8314 movl(carry, rdxReg);
8315
8316 movl(Address(out, offs, Address::times_4, -4), sum);
8317
8318 bind(L_carry);
8319 //return tmp5/carry as carry in rax
8320 movl(rax, carry);
8321
8322 bind(L_done);
8323 pop(tmp5);
8324 pop(tmp4);
8325 pop(tmp3);
8326 pop(tmp2);
8327 pop(tmp1);
8328 }
8329 #endif
8330
8331 /**
8332 * Emits code to update CRC-32 with a byte value according to constants in table
8333 *
8334 * @param [in,out]crc Register containing the crc.
8335 * @param [in]val Register containing the byte to fold into the CRC.
8336 * @param [in]table Register containing the table of crc constants.
8337 *
8338 * uint32_t crc;
8339 * val = crc_table[(val ^ crc) & 0xFF];
8340 * crc = val ^ (crc >> 8);
8341 *
8342 */
8343 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8344 xorl(val, crc);
8345 andl(val, 0xFF);
8346 shrl(crc, 8); // unsigned shift
8347 xorl(crc, Address(table, val, Address::times_4, 0));
8348 }
8349
8350 /**
8351 * Fold 128-bit data chunk
8352 */
8353 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8354 if (UseAVX > 0) {
8355 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8356 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8357 vpxor(xcrc, xcrc, Address(buf, offset), false /* vector256 */);
8358 pxor(xcrc, xtmp);
8359 } else {
8360 movdqa(xtmp, xcrc);
8361 pclmulhdq(xtmp, xK); // [123:64]
8362 pclmulldq(xcrc, xK); // [63:0]
8363 pxor(xcrc, xtmp);
8364 movdqu(xtmp, Address(buf, offset));
8365 pxor(xcrc, xtmp);
8366 }
8367 }
8368
8369 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8370 if (UseAVX > 0) {
8371 vpclmulhdq(xtmp, xK, xcrc);
8372 vpclmulldq(xcrc, xK, xcrc);
8373 pxor(xcrc, xbuf);
8374 pxor(xcrc, xtmp);
8375 } else {
8376 movdqa(xtmp, xcrc);
8377 pclmulhdq(xtmp, xK);
8378 pclmulldq(xcrc, xK);
8379 pxor(xcrc, xbuf);
8380 pxor(xcrc, xtmp);
8381 }
8382 }
8383
8384 /**
8385 * 8-bit folds to compute 32-bit CRC
8386 *
8387 * uint64_t xcrc;
8388 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8389 */
8390 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8391 movdl(tmp, xcrc);
8392 andl(tmp, 0xFF);
8393 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8394 psrldq(xcrc, 1); // unsigned shift one byte
8395 pxor(xcrc, xtmp);
8396 }
8397
8398 /**
8399 * uint32_t crc;
8400 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8401 */
8402 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8403 movl(tmp, crc);
8404 andl(tmp, 0xFF);
8405 shrl(crc, 8);
8406 xorl(crc, Address(table, tmp, Address::times_4, 0));
8407 }
8408
8409 /**
8410 * @param crc register containing existing CRC (32-bit)
8411 * @param buf register pointing to input byte buffer (byte*)
8412 * @param len register containing number of bytes
8413 * @param table register that will contain address of CRC table
8414 * @param tmp scratch register
8415 */
8416 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8417 assert_different_registers(crc, buf, len, table, tmp, rax);
8418
8419 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8420 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8421
8422 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8423 notl(crc); // ~crc
8424 cmpl(len, 16);
8425 jcc(Assembler::less, L_tail);
8426
8427 // Align buffer to 16 bytes
8428 movl(tmp, buf);
8429 andl(tmp, 0xF);
8430 jccb(Assembler::zero, L_aligned);
8431 subl(tmp, 16);
8432 addl(len, tmp);
8433
8434 align(4);
8435 BIND(L_align_loop);
8436 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8437 update_byte_crc32(crc, rax, table);
8438 increment(buf);
8439 incrementl(tmp);
8440 jccb(Assembler::less, L_align_loop);
8441
8442 BIND(L_aligned);
8443 movl(tmp, len); // save
8444 shrl(len, 4);
8445 jcc(Assembler::zero, L_tail_restore);
8446
8447 // Fold crc into first bytes of vector
8448 movdqa(xmm1, Address(buf, 0));
8449 movdl(rax, xmm1);
8450 xorl(crc, rax);
8451 pinsrd(xmm1, crc, 0);
8452 addptr(buf, 16);
8453 subl(len, 4); // len > 0
8454 jcc(Assembler::less, L_fold_tail);
8455
8456 movdqa(xmm2, Address(buf, 0));
8457 movdqa(xmm3, Address(buf, 16));
8458 movdqa(xmm4, Address(buf, 32));
8459 addptr(buf, 48);
8460 subl(len, 3);
8461 jcc(Assembler::lessEqual, L_fold_512b);
8462
8463 // Fold total 512 bits of polynomial on each iteration,
8464 // 128 bits per each of 4 parallel streams.
8465 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8466
8467 align(32);
8468 BIND(L_fold_512b_loop);
8469 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8470 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8471 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8472 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8473 addptr(buf, 64);
8474 subl(len, 4);
8475 jcc(Assembler::greater, L_fold_512b_loop);
8476
8477 // Fold 512 bits to 128 bits.
8478 BIND(L_fold_512b);
8479 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8480 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8481 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8482 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8483
8484 // Fold the rest of 128 bits data chunks
8485 BIND(L_fold_tail);
8486 addl(len, 3);
8487 jccb(Assembler::lessEqual, L_fold_128b);
8488 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8489
8490 BIND(L_fold_tail_loop);
8491 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8492 addptr(buf, 16);
8493 decrementl(len);
8494 jccb(Assembler::greater, L_fold_tail_loop);
8495
8496 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8497 BIND(L_fold_128b);
8498 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
8499 if (UseAVX > 0) {
8500 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8501 vpand(xmm3, xmm0, xmm2, false /* vector256 */);
8502 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8503 } else {
8504 movdqa(xmm2, xmm0);
8505 pclmulqdq(xmm2, xmm1, 0x1);
8506 movdqa(xmm3, xmm0);
8507 pand(xmm3, xmm2);
8508 pclmulqdq(xmm0, xmm3, 0x1);
8509 }
8510 psrldq(xmm1, 8);
8511 psrldq(xmm2, 4);
8512 pxor(xmm0, xmm1);
8513 pxor(xmm0, xmm2);
8514
8515 // 8 8-bit folds to compute 32-bit CRC.
8516 for (int j = 0; j < 4; j++) {
8517 fold_8bit_crc32(xmm0, table, xmm1, rax);
8518 }
8519 movdl(crc, xmm0); // mov 32 bits to general register
8520 for (int j = 0; j < 4; j++) {
8521 fold_8bit_crc32(crc, table, rax);
8522 }
8523
8524 BIND(L_tail_restore);
8525 movl(len, tmp); // restore
8526 BIND(L_tail);
8527 andl(len, 0xf);
8528 jccb(Assembler::zero, L_exit);
8529
8530 // Fold the rest of bytes
8531 align(4);
8532 BIND(L_tail_loop);
8533 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8534 update_byte_crc32(crc, rax, table);
8535 increment(buf);
8536 decrementl(len);
8537 jccb(Assembler::greater, L_tail_loop);
8538
8539 BIND(L_exit);
8540 notl(crc); // ~c
8541 }
8542
8543 #undef BIND
8544 #undef BLOCK_COMMENT
8545
8546
8547 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
8548 switch (cond) {
8549 // Note some conditions are synonyms for others
8550 case Assembler::zero: return Assembler::notZero;
8551 case Assembler::notZero: return Assembler::zero;
8552 case Assembler::less: return Assembler::greaterEqual;
8553 case Assembler::lessEqual: return Assembler::greater;
8554 case Assembler::greater: return Assembler::lessEqual;
8555 case Assembler::greaterEqual: return Assembler::less;
8556 case Assembler::below: return Assembler::aboveEqual;
8557 case Assembler::belowEqual: return Assembler::above;
8558 case Assembler::above: return Assembler::belowEqual;
8559 case Assembler::aboveEqual: return Assembler::below;
8560 case Assembler::overflow: return Assembler::noOverflow;
8561 case Assembler::noOverflow: return Assembler::overflow;
8562 case Assembler::negative: return Assembler::positive;
8563 case Assembler::positive: return Assembler::negative;
8564 case Assembler::parity: return Assembler::noParity;
8565 case Assembler::noParity: return Assembler::parity;
8566 }
8567 ShouldNotReachHere(); return Assembler::overflow;
8568 }
8569
8570 SkipIfEqual::SkipIfEqual(
8571 MacroAssembler* masm, const bool* flag_addr, bool value) {
8572 _masm = masm;
8573 _masm->cmp8(ExternalAddress((address)flag_addr), value);
8574 _masm->jcc(Assembler::equal, _label);
8575 }
8576
8577 SkipIfEqual::~SkipIfEqual() {
8578 _masm->bind(_label);
8579 }