1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
300 switch (instr_0) {
301 case instruction_operandsize_prefix:
302
303 fatal("should have skipped instruction_operandsize_prefix");
304 break;
305
306 case instruction_extended_prefix:
307 fatal("should have skipped instruction_extended_prefix");
308 break;
309
310 case instruction_code_mem2reg_movslq: // 0x63
311 case instruction_code_mem2reg_movzxb: // 0xB6
312 case instruction_code_mem2reg_movsxb: // 0xBE
313 case instruction_code_mem2reg_movzxw: // 0xB7
314 case instruction_code_mem2reg_movsxw: // 0xBF
315 case instruction_code_reg2mem: // 0x89 (q/l)
316 case instruction_code_mem2reg: // 0x8B (q/l)
317 case instruction_code_reg2memb: // 0x88
318 case instruction_code_mem2regb: // 0x8a
319
320 case instruction_code_float_s: // 0xd9 fld_s a
321 case instruction_code_float_d: // 0xdd fld_d a
322
323 case instruction_code_xmm_load: // 0x10
324 case instruction_code_xmm_store: // 0x11
325 case instruction_code_xmm_lpd: // 0x12
326 {
327 // If there is an SIB then instruction is longer than expected
328 u_char mod_rm = *(u_char*)(instruction_address() + 1);
329 if ((mod_rm & 7) == 0x4) {
330 ret++;
331 }
332 }
333 case instruction_code_xor:
334 fatal("should have skipped xor lead in");
335 break;
336
337 default:
338 fatal("not a NativeMovRegMem");
339 }
370 u_char test_byte = *(u_char*)instruction_address();
371 switch (test_byte) {
372 case instruction_code_reg2memb: // 0x88 movb a, r
373 case instruction_code_reg2mem: // 0x89 movl a, r (can be movq in 64bit)
374 case instruction_code_mem2regb: // 0x8a movb r, a
375 case instruction_code_mem2reg: // 0x8b movl r, a (can be movq in 64bit)
376 break;
377
378 case instruction_code_mem2reg_movslq: // 0x63 movsql r, a
379 case instruction_code_mem2reg_movzxb: // 0xb6 movzbl r, a (movzxb)
380 case instruction_code_mem2reg_movzxw: // 0xb7 movzwl r, a (movzxw)
381 case instruction_code_mem2reg_movsxb: // 0xbe movsbl r, a (movsxb)
382 case instruction_code_mem2reg_movsxw: // 0xbf movswl r, a (movsxw)
383 break;
384
385 case instruction_code_float_s: // 0xd9 fld_s a
386 case instruction_code_float_d: // 0xdd fld_d a
387 case instruction_code_xmm_load: // 0x10 movsd xmm, a
388 case instruction_code_xmm_store: // 0x11 movsd a, xmm
389 case instruction_code_xmm_lpd: // 0x12 movlpd xmm, a
390 break;
391
392 default:
393 fatal ("not a mov [reg+offs], reg instruction");
394 }
395 }
396
397
398 void NativeMovRegMem::print() {
399 tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset());
400 }
401
402 //-------------------------------------------------------------------
403
404 void NativeLoadAddress::verify() {
405 // make sure code pattern is actually a mov [reg+offset], reg instruction
406 u_char test_byte = *(u_char*)instruction_address();
407 #ifdef _LP64
408 if ( (test_byte == instruction_prefix_wide ||
409 test_byte == instruction_prefix_wide_extended) ) {
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1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
300 switch (instr_0) {
301 case instruction_operandsize_prefix:
302
303 fatal("should have skipped instruction_operandsize_prefix");
304 break;
305
306 case instruction_extended_prefix:
307 fatal("should have skipped instruction_extended_prefix");
308 break;
309
310 case instruction_code_mem2reg_movslq: // 0x63
311 case instruction_code_mem2reg_movzxb: // 0xB6
312 case instruction_code_mem2reg_movsxb: // 0xBE
313 case instruction_code_mem2reg_movzxw: // 0xB7
314 case instruction_code_mem2reg_movsxw: // 0xBF
315 case instruction_code_reg2mem: // 0x89 (q/l)
316 case instruction_code_mem2reg: // 0x8B (q/l)
317 case instruction_code_reg2memb: // 0x88
318 case instruction_code_mem2regb: // 0x8a
319
320 case instruction_code_lea: // 0x8d
321
322 case instruction_code_float_s: // 0xd9 fld_s a
323 case instruction_code_float_d: // 0xdd fld_d a
324
325 case instruction_code_xmm_load: // 0x10
326 case instruction_code_xmm_store: // 0x11
327 case instruction_code_xmm_lpd: // 0x12
328 {
329 // If there is an SIB then instruction is longer than expected
330 u_char mod_rm = *(u_char*)(instruction_address() + 1);
331 if ((mod_rm & 7) == 0x4) {
332 ret++;
333 }
334 }
335 case instruction_code_xor:
336 fatal("should have skipped xor lead in");
337 break;
338
339 default:
340 fatal("not a NativeMovRegMem");
341 }
372 u_char test_byte = *(u_char*)instruction_address();
373 switch (test_byte) {
374 case instruction_code_reg2memb: // 0x88 movb a, r
375 case instruction_code_reg2mem: // 0x89 movl a, r (can be movq in 64bit)
376 case instruction_code_mem2regb: // 0x8a movb r, a
377 case instruction_code_mem2reg: // 0x8b movl r, a (can be movq in 64bit)
378 break;
379
380 case instruction_code_mem2reg_movslq: // 0x63 movsql r, a
381 case instruction_code_mem2reg_movzxb: // 0xb6 movzbl r, a (movzxb)
382 case instruction_code_mem2reg_movzxw: // 0xb7 movzwl r, a (movzxw)
383 case instruction_code_mem2reg_movsxb: // 0xbe movsbl r, a (movsxb)
384 case instruction_code_mem2reg_movsxw: // 0xbf movswl r, a (movsxw)
385 break;
386
387 case instruction_code_float_s: // 0xd9 fld_s a
388 case instruction_code_float_d: // 0xdd fld_d a
389 case instruction_code_xmm_load: // 0x10 movsd xmm, a
390 case instruction_code_xmm_store: // 0x11 movsd a, xmm
391 case instruction_code_xmm_lpd: // 0x12 movlpd xmm, a
392 break;
393
394 case instruction_code_lea: // 0x8d lea r, a
395 break;
396
397 default:
398 fatal ("not a mov [reg+offs], reg instruction");
399 }
400 }
401
402
403 void NativeMovRegMem::print() {
404 tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset());
405 }
406
407 //-------------------------------------------------------------------
408
409 void NativeLoadAddress::verify() {
410 // make sure code pattern is actually a mov [reg+offset], reg instruction
411 u_char test_byte = *(u_char*)instruction_address();
412 #ifdef _LP64
413 if ( (test_byte == instruction_prefix_wide ||
414 test_byte == instruction_prefix_wide_extended) ) {
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