1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_NATIVEINST_X86_HPP
26 #define CPU_X86_VM_NATIVEINST_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "memory/allocation.hpp"
30 #include "runtime/icache.hpp"
31 #include "runtime/os.hpp"
32 #include "utilities/top.hpp"
33
34 // We have interfaces for the following instructions:
35 // - NativeInstruction
36 // - - NativeCall
37 // - - NativeMovConstReg
38 // - - NativeMovConstRegPatching
39 // - - NativeMovRegMem
40 // - - NativeMovRegMemPatching
41 // - - NativeJump
42 // - - NativeIllegalOpCode
43 // - - NativeGeneralJump
44 // - - NativeReturn
45 // - - NativeReturnX (return with argument)
46 // - - NativePushConst
47 // - - NativeTstRegMem
48
49 // The base class for different kinds of native instruction abstractions.
50 // Provides the primitive operations to manipulate code relative to this.
51
52 class NativeInstruction VALUE_OBJ_CLASS_SPEC {
53 friend class Relocation;
54
55 public:
56 enum Intel_specific_constants {
57 nop_instruction_code = 0x90,
58 nop_instruction_size = 1
59 };
60
61 bool is_nop() { return ubyte_at(0) == nop_instruction_code; }
62 bool is_dtrace_trap();
63 inline bool is_call();
64 inline bool is_illegal();
65 inline bool is_return();
66 inline bool is_jump();
67 inline bool is_cond_jump();
68 inline bool is_safepoint_poll();
69 inline bool is_mov_literal64();
70
71 protected:
72 address addr_at(int offset) const { return address(this) + offset; }
73
74 s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); }
75 u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); }
76
77 jint int_at(int offset) const { return *(jint*) addr_at(offset); }
78
79 intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); }
80
81 oop oop_at (int offset) const { return *(oop*) addr_at(offset); }
82
83
84 void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; wrote(offset); }
85 void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; wrote(offset); }
86 void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; wrote(offset); }
87 void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; wrote(offset); }
88
89 // This doesn't really do anything on Intel, but it is the place where
90 // cache invalidation belongs, generically:
91 void wrote(int offset);
92
93 public:
94
95 // unit test stuff
96 static void test() {} // override for testing
97
98 inline friend NativeInstruction* nativeInstruction_at(address address);
99 };
100
101 inline NativeInstruction* nativeInstruction_at(address address) {
102 NativeInstruction* inst = (NativeInstruction*)address;
103 #ifdef ASSERT
104 //inst->verify();
105 #endif
106 return inst;
107 }
108
109 inline NativeCall* nativeCall_at(address address);
110 // The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off
111 // instructions (used to manipulate inline caches, primitive & dll calls, etc.).
112
113 class NativeCall: public NativeInstruction {
114 public:
115 enum Intel_specific_constants {
116 instruction_code = 0xE8,
117 instruction_size = 5,
118 instruction_offset = 0,
119 displacement_offset = 1,
120 return_address_offset = 5
121 };
122
123 enum { cache_line_size = BytesPerWord }; // conservative estimate!
124
125 address instruction_address() const { return addr_at(instruction_offset); }
126 address next_instruction_address() const { return addr_at(return_address_offset); }
127 int displacement() const { return (jint) int_at(displacement_offset); }
128 address displacement_address() const { return addr_at(displacement_offset); }
129 address return_address() const { return addr_at(return_address_offset); }
130 address destination() const;
131 void set_destination(address dest) {
132 #ifdef AMD64
133 assert((labs((intptr_t) dest - (intptr_t) return_address()) &
134 0xFFFFFFFF00000000) == 0,
135 "must be 32bit offset");
136 #endif // AMD64
137 set_int_at(displacement_offset, dest - return_address());
138 }
139 void set_destination_mt_safe(address dest);
140
141 void verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); }
142 void verify();
143 void print();
144
145 // Creation
146 inline friend NativeCall* nativeCall_at(address address);
147 inline friend NativeCall* nativeCall_before(address return_address);
148
149 static bool is_call_at(address instr) {
150 return ((*instr) & 0xFF) == NativeCall::instruction_code;
151 }
152
153 static bool is_call_before(address return_address) {
154 return is_call_at(return_address - NativeCall::return_address_offset);
155 }
156
157 static bool is_call_to(address instr, address target) {
158 return nativeInstruction_at(instr)->is_call() &&
159 nativeCall_at(instr)->destination() == target;
160 }
161
162 // MT-safe patching of a call instruction.
163 static void insert(address code_pos, address entry);
164
165 static void replace_mt_safe(address instr_addr, address code_buffer);
166 };
167
168 inline NativeCall* nativeCall_at(address address) {
169 NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset);
170 #ifdef ASSERT
171 call->verify();
172 #endif
173 return call;
174 }
175
176 inline NativeCall* nativeCall_before(address return_address) {
177 NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset);
178 #ifdef ASSERT
179 call->verify();
180 #endif
181 return call;
182 }
183
184 // An interface for accessing/manipulating native mov reg, imm32 instructions.
185 // (used to manipulate inlined 32bit data dll calls, etc.)
186 class NativeMovConstReg: public NativeInstruction {
187 #ifdef AMD64
188 static const bool has_rex = true;
189 static const int rex_size = 1;
190 #else
191 static const bool has_rex = false;
192 static const int rex_size = 0;
193 #endif // AMD64
194 public:
195 enum Intel_specific_constants {
196 instruction_code = 0xB8,
197 instruction_size = 1 + rex_size + wordSize,
198 instruction_offset = 0,
199 data_offset = 1 + rex_size,
200 next_instruction_offset = instruction_size,
201 register_mask = 0x07
202 };
203
204 address instruction_address() const { return addr_at(instruction_offset); }
205 address next_instruction_address() const { return addr_at(next_instruction_offset); }
206 intptr_t data() const { return ptr_at(data_offset); }
207 void set_data(intptr_t x) { set_ptr_at(data_offset, x); }
208
209 void verify();
210 void print();
211
212 // unit test stuff
213 static void test() {}
214
215 // Creation
216 inline friend NativeMovConstReg* nativeMovConstReg_at(address address);
217 inline friend NativeMovConstReg* nativeMovConstReg_before(address address);
218 };
219
220 inline NativeMovConstReg* nativeMovConstReg_at(address address) {
221 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset);
222 #ifdef ASSERT
223 test->verify();
224 #endif
225 return test;
226 }
227
228 inline NativeMovConstReg* nativeMovConstReg_before(address address) {
229 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset);
230 #ifdef ASSERT
231 test->verify();
232 #endif
233 return test;
234 }
235
236 class NativeMovConstRegPatching: public NativeMovConstReg {
237 private:
238 friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
239 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset);
240 #ifdef ASSERT
241 test->verify();
242 #endif
243 return test;
244 }
245 };
246
247 // An interface for accessing/manipulating native moves of the form:
248 // mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem)
249 // mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg
250 // mov[s/z]x[w/b/q] [reg + offset], reg
251 // fld_s [reg+offset]
252 // fld_d [reg+offset]
253 // fstp_s [reg + offset]
254 // fstp_d [reg + offset]
255 // mov_literal64 scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch)
256 //
257 // Warning: These routines must be able to handle any instruction sequences
258 // that are generated as a result of the load/store byte,word,long
259 // macros. For example: The load_unsigned_byte instruction generates
260 // an xor reg,reg inst prior to generating the movb instruction. This
261 // class must skip the xor instruction.
262
263 class NativeMovRegMem: public NativeInstruction {
264 public:
265 enum Intel_specific_constants {
266 instruction_prefix_wide_lo = Assembler::REX,
267 instruction_prefix_wide_hi = Assembler::REX_WRXB,
268 instruction_code_xor = 0x33,
269 instruction_extended_prefix = 0x0F,
270 instruction_code_mem2reg_movslq = 0x63,
271 instruction_code_mem2reg_movzxb = 0xB6,
272 instruction_code_mem2reg_movsxb = 0xBE,
273 instruction_code_mem2reg_movzxw = 0xB7,
274 instruction_code_mem2reg_movsxw = 0xBF,
275 instruction_operandsize_prefix = 0x66,
276 instruction_code_reg2mem = 0x89,
277 instruction_code_mem2reg = 0x8b,
278 instruction_code_reg2memb = 0x88,
279 instruction_code_mem2regb = 0x8a,
280 instruction_code_float_s = 0xd9,
281 instruction_code_float_d = 0xdd,
282 instruction_code_long_volatile = 0xdf,
283 instruction_code_xmm_ss_prefix = 0xf3,
284 instruction_code_xmm_sd_prefix = 0xf2,
285 instruction_code_xmm_code = 0x0f,
286 instruction_code_xmm_load = 0x10,
287 instruction_code_xmm_store = 0x11,
288 instruction_code_xmm_lpd = 0x12,
289
290 instruction_code_lea = 0x8d,
291
292 instruction_VEX_prefix_2bytes = Assembler::VEX_2bytes,
293 instruction_VEX_prefix_3bytes = Assembler::VEX_3bytes,
294
295 instruction_size = 4,
296 instruction_offset = 0,
297 data_offset = 2,
298 next_instruction_offset = 4
299 };
300
301 // helper
302 int instruction_start() const;
303
304 address instruction_address() const;
305
306 address next_instruction_address() const;
307
308 int offset() const;
309
310 void set_offset(int x);
311
312 void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); }
313
314 void verify();
315 void print ();
316
317 // unit test stuff
318 static void test() {}
319
320 private:
321 inline friend NativeMovRegMem* nativeMovRegMem_at (address address);
322 };
323
324 inline NativeMovRegMem* nativeMovRegMem_at (address address) {
325 NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset);
326 #ifdef ASSERT
327 test->verify();
328 #endif
329 return test;
330 }
331
332 class NativeMovRegMemPatching: public NativeMovRegMem {
333 private:
334 friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {
335 NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset);
336 #ifdef ASSERT
337 test->verify();
338 #endif
339 return test;
340 }
341 };
342
343
344
345 // An interface for accessing/manipulating native leal instruction of form:
346 // leal reg, [reg + offset]
347
348 class NativeLoadAddress: public NativeMovRegMem {
349 #ifdef AMD64
350 static const bool has_rex = true;
351 static const int rex_size = 1;
352 #else
353 static const bool has_rex = false;
354 static const int rex_size = 0;
355 #endif // AMD64
356 public:
357 enum Intel_specific_constants {
358 instruction_prefix_wide = Assembler::REX_W,
359 instruction_prefix_wide_extended = Assembler::REX_WB,
360 lea_instruction_code = 0x8D,
361 mov64_instruction_code = 0xB8
362 };
363
364 void verify();
365 void print ();
366
367 // unit test stuff
368 static void test() {}
369
370 private:
371 friend NativeLoadAddress* nativeLoadAddress_at (address address) {
372 NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset);
373 #ifdef ASSERT
374 test->verify();
375 #endif
376 return test;
377 }
378 };
379
380 // jump rel32off
381
382 class NativeJump: public NativeInstruction {
383 public:
384 enum Intel_specific_constants {
385 instruction_code = 0xe9,
386 instruction_size = 5,
387 instruction_offset = 0,
388 data_offset = 1,
389 next_instruction_offset = 5
390 };
391
392 address instruction_address() const { return addr_at(instruction_offset); }
393 address next_instruction_address() const { return addr_at(next_instruction_offset); }
394 address jump_destination() const {
395 address dest = (int_at(data_offset)+next_instruction_address());
396 // 32bit used to encode unresolved jmp as jmp -1
397 // 64bit can't produce this so it used jump to self.
398 // Now 32bit and 64bit use jump to self as the unresolved address
399 // which the inline cache code (and relocs) know about
400
401 // return -1 if jump to self
402 dest = (dest == (address) this) ? (address) -1 : dest;
403 return dest;
404 }
405
406 void set_jump_destination(address dest) {
407 intptr_t val = dest - next_instruction_address();
408 if (dest == (address) -1) {
409 val = -5; // jump to self
410 }
411 #ifdef AMD64
412 assert((labs(val) & 0xFFFFFFFF00000000) == 0 || dest == (address)-1, "must be 32bit offset or -1");
413 #endif // AMD64
414 set_int_at(data_offset, (jint)val);
415 }
416
417 // Creation
418 inline friend NativeJump* nativeJump_at(address address);
419
420 void verify();
421
422 // Unit testing stuff
423 static void test() {}
424
425 // Insertion of native jump instruction
426 static void insert(address code_pos, address entry);
427 // MT-safe insertion of native jump at verified method entry
428 static void check_verified_entry_alignment(address entry, address verified_entry);
429 static void patch_verified_entry(address entry, address verified_entry, address dest);
430 };
431
432 inline NativeJump* nativeJump_at(address address) {
433 NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset);
434 #ifdef ASSERT
435 jump->verify();
436 #endif
437 return jump;
438 }
439
440 // Handles all kinds of jump on Intel. Long/far, conditional/unconditional
441 class NativeGeneralJump: public NativeInstruction {
442 public:
443 enum Intel_specific_constants {
444 // Constants does not apply, since the lengths and offsets depends on the actual jump
445 // used
446 // Instruction codes:
447 // Unconditional jumps: 0xE9 (rel32off), 0xEB (rel8off)
448 // Conditional jumps: 0x0F8x (rel32off), 0x7x (rel8off)
449 unconditional_long_jump = 0xe9,
450 unconditional_short_jump = 0xeb,
451 instruction_size = 5
452 };
453
454 address instruction_address() const { return addr_at(0); }
455 address jump_destination() const;
456
457 // Creation
458 inline friend NativeGeneralJump* nativeGeneralJump_at(address address);
459
460 // Insertion of native general jump instruction
461 static void insert_unconditional(address code_pos, address entry);
462 static void replace_mt_safe(address instr_addr, address code_buffer);
463
464 void verify();
465 };
466
467 inline NativeGeneralJump* nativeGeneralJump_at(address address) {
468 NativeGeneralJump* jump = (NativeGeneralJump*)(address);
469 debug_only(jump->verify();)
470 return jump;
471 }
472
473 class NativePopReg : public NativeInstruction {
474 public:
475 enum Intel_specific_constants {
476 instruction_code = 0x58,
477 instruction_size = 1,
478 instruction_offset = 0,
479 data_offset = 1,
480 next_instruction_offset = 1
481 };
482
483 // Insert a pop instruction
484 static void insert(address code_pos, Register reg);
485 };
486
487
488 class NativeIllegalInstruction: public NativeInstruction {
489 public:
490 enum Intel_specific_constants {
491 instruction_code = 0x0B0F, // Real byte order is: 0x0F, 0x0B
492 instruction_size = 2,
493 instruction_offset = 0,
494 next_instruction_offset = 2
495 };
496
497 // Insert illegal opcode as specific address
498 static void insert(address code_pos);
499 };
500
501 // return instruction that does not pop values of the stack
502 class NativeReturn: public NativeInstruction {
503 public:
504 enum Intel_specific_constants {
505 instruction_code = 0xC3,
506 instruction_size = 1,
507 instruction_offset = 0,
508 next_instruction_offset = 1
509 };
510 };
511
512 // return instruction that does pop values of the stack
513 class NativeReturnX: public NativeInstruction {
514 public:
515 enum Intel_specific_constants {
516 instruction_code = 0xC2,
517 instruction_size = 2,
518 instruction_offset = 0,
519 next_instruction_offset = 2
520 };
521 };
522
523 // Simple test vs memory
524 class NativeTstRegMem: public NativeInstruction {
525 public:
526 enum Intel_specific_constants {
527 instruction_rex_prefix_mask = 0xF0,
528 instruction_rex_prefix = Assembler::REX,
529 instruction_code_memXregl = 0x85,
530 modrm_mask = 0x38, // select reg from the ModRM byte
531 modrm_reg = 0x00 // rax
532 };
533 };
534
535 inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; }
536 inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; }
537 inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code ||
538 ubyte_at(0) == NativeReturnX::instruction_code; }
539 inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code ||
540 ubyte_at(0) == 0xEB; /* short jump */ }
541 inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ ||
542 (ubyte_at(0) & 0xF0) == 0x70; /* short jump */ }
543 inline bool NativeInstruction::is_safepoint_poll() {
544 #ifdef AMD64
545 if (Assembler::is_polling_page_far()) {
546 // two cases, depending on the choice of the base register in the address.
547 if (((ubyte_at(0) & NativeTstRegMem::instruction_rex_prefix_mask) == NativeTstRegMem::instruction_rex_prefix &&
548 ubyte_at(1) == NativeTstRegMem::instruction_code_memXregl &&
549 (ubyte_at(2) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) ||
550 ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
551 (ubyte_at(1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) {
552 return true;
553 } else {
554 return false;
555 }
556 } else {
557 if (ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
558 ubyte_at(1) == 0x05) { // 00 rax 101
559 address fault = addr_at(6) + int_at(2);
560 return os::is_poll_address(fault);
561 } else {
562 return false;
563 }
564 }
565 #else
566 return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg ||
567 ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) &&
568 (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */
569 (os::is_poll_address((address)int_at(2)));
570 #endif // AMD64
571 }
572
573 inline bool NativeInstruction::is_mov_literal64() {
574 #ifdef AMD64
575 return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) &&
576 (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8);
577 #else
578 return false;
579 #endif // AMD64
580 }
581
582 #endif // CPU_X86_VM_NATIVEINST_X86_HPP