1 /*
2 * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "code/debugInfoRec.hpp"
29 #include "code/icBuffer.hpp"
30 #include "code/vtableStubs.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "oops/compiledICHolder.hpp"
33 #include "prims/jvmtiRedefineClassesTrace.hpp"
34 #include "runtime/sharedRuntime.hpp"
35 #include "runtime/vframeArray.hpp"
36 #include "vmreg_x86.inline.hpp"
37 #ifdef COMPILER1
38 #include "c1/c1_Runtime1.hpp"
39 #endif
40 #ifdef COMPILER2
41 #include "opto/runtime.hpp"
42 #endif
43
44 #define __ masm->
45
46 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
47
48 class RegisterSaver {
49 // Capture info about frame layout
50 #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off
51 enum layout {
52 fpu_state_off = 0,
53 fpu_state_end = fpu_state_off+FPUStateSizeInWords,
54 st0_off, st0H_off,
55 st1_off, st1H_off,
56 st2_off, st2H_off,
57 st3_off, st3H_off,
58 st4_off, st4H_off,
59 st5_off, st5H_off,
60 st6_off, st6H_off,
61 st7_off, st7H_off,
62 xmm_off,
63 DEF_XMM_OFFS(0),
64 DEF_XMM_OFFS(1),
65 DEF_XMM_OFFS(2),
66 DEF_XMM_OFFS(3),
67 DEF_XMM_OFFS(4),
68 DEF_XMM_OFFS(5),
69 DEF_XMM_OFFS(6),
70 DEF_XMM_OFFS(7),
71 flags_off = xmm7_off + 16/BytesPerInt + 1, // 16-byte stack alignment fill word
72 rdi_off,
73 rsi_off,
74 ignore_off, // extra copy of rbp,
75 rsp_off,
76 rbx_off,
77 rdx_off,
78 rcx_off,
79 rax_off,
80 // The frame sender code expects that rbp will be in the "natural" place and
81 // will override any oopMap setting for it. We must therefore force the layout
82 // so that it agrees with the frame sender code.
83 rbp_off,
84 return_off, // slot for return address
85 reg_save_size };
86 enum { FPU_regs_live = flags_off - fpu_state_end };
87
88 public:
89
90 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words,
91 int* total_frame_words, bool verify_fpu = true, bool save_vectors = false);
92 static void restore_live_registers(MacroAssembler* masm, bool restore_vectors = false);
93
94 static int rax_offset() { return rax_off; }
95 static int rbx_offset() { return rbx_off; }
96
97 // Offsets into the register save area
98 // Used by deoptimization when it is managing result register
99 // values on its own
100
101 static int raxOffset(void) { return rax_off; }
102 static int rdxOffset(void) { return rdx_off; }
103 static int rbxOffset(void) { return rbx_off; }
104 static int xmm0Offset(void) { return xmm0_off; }
105 // This really returns a slot in the fp save area, which one is not important
106 static int fpResultOffset(void) { return st0_off; }
107
108 // During deoptimization only the result register need to be restored
109 // all the other values have already been extracted.
110
111 static void restore_result_registers(MacroAssembler* masm);
112
113 };
114
115 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words,
116 int* total_frame_words, bool verify_fpu, bool save_vectors) {
117 int vect_words = 0;
118 #ifdef COMPILER2
119 if (save_vectors) {
120 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
121 assert(MaxVectorSize == 32, "only 256bit vectors are supported now");
122 // Save upper half of YMM registes
123 vect_words = 8 * 16 / wordSize;
124 additional_frame_words += vect_words;
125 }
126 #else
127 assert(!save_vectors, "vectors are generated only by C2");
128 #endif
129 int frame_size_in_bytes = (reg_save_size + additional_frame_words) * wordSize;
130 int frame_words = frame_size_in_bytes / wordSize;
131 *total_frame_words = frame_words;
132
133 assert(FPUStateSizeInWords == 27, "update stack layout");
134
135 // save registers, fpu state, and flags
136 // We assume caller has already has return address slot on the stack
137 // We push epb twice in this sequence because we want the real rbp,
138 // to be under the return like a normal enter and we want to use pusha
139 // We push by hand instead of pusing push
140 __ enter();
141 __ pusha();
142 __ pushf();
143 __ subptr(rsp,FPU_regs_live*wordSize); // Push FPU registers space
144 __ push_FPU_state(); // Save FPU state & init
145
146 if (verify_fpu) {
147 // Some stubs may have non standard FPU control word settings so
148 // only check and reset the value when it required to be the
149 // standard value. The safepoint blob in particular can be used
150 // in methods which are using the 24 bit control word for
151 // optimized float math.
152
153 #ifdef ASSERT
154 // Make sure the control word has the expected value
155 Label ok;
156 __ cmpw(Address(rsp, 0), StubRoutines::fpu_cntrl_wrd_std());
157 __ jccb(Assembler::equal, ok);
158 __ stop("corrupted control word detected");
159 __ bind(ok);
160 #endif
161
162 // Reset the control word to guard against exceptions being unmasked
163 // since fstp_d can cause FPU stack underflow exceptions. Write it
164 // into the on stack copy and then reload that to make sure that the
165 // current and future values are correct.
166 __ movw(Address(rsp, 0), StubRoutines::fpu_cntrl_wrd_std());
167 }
168
169 __ frstor(Address(rsp, 0));
170 if (!verify_fpu) {
171 // Set the control word so that exceptions are masked for the
172 // following code.
173 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
174 }
175
176 // Save the FPU registers in de-opt-able form
177
178 __ fstp_d(Address(rsp, st0_off*wordSize)); // st(0)
179 __ fstp_d(Address(rsp, st1_off*wordSize)); // st(1)
180 __ fstp_d(Address(rsp, st2_off*wordSize)); // st(2)
181 __ fstp_d(Address(rsp, st3_off*wordSize)); // st(3)
182 __ fstp_d(Address(rsp, st4_off*wordSize)); // st(4)
183 __ fstp_d(Address(rsp, st5_off*wordSize)); // st(5)
184 __ fstp_d(Address(rsp, st6_off*wordSize)); // st(6)
185 __ fstp_d(Address(rsp, st7_off*wordSize)); // st(7)
186
187 if( UseSSE == 1 ) { // Save the XMM state
188 __ movflt(Address(rsp,xmm0_off*wordSize),xmm0);
189 __ movflt(Address(rsp,xmm1_off*wordSize),xmm1);
190 __ movflt(Address(rsp,xmm2_off*wordSize),xmm2);
191 __ movflt(Address(rsp,xmm3_off*wordSize),xmm3);
192 __ movflt(Address(rsp,xmm4_off*wordSize),xmm4);
193 __ movflt(Address(rsp,xmm5_off*wordSize),xmm5);
194 __ movflt(Address(rsp,xmm6_off*wordSize),xmm6);
195 __ movflt(Address(rsp,xmm7_off*wordSize),xmm7);
196 } else if( UseSSE >= 2 ) {
197 // Save whole 128bit (16 bytes) XMM regiters
198 __ movdqu(Address(rsp,xmm0_off*wordSize),xmm0);
199 __ movdqu(Address(rsp,xmm1_off*wordSize),xmm1);
200 __ movdqu(Address(rsp,xmm2_off*wordSize),xmm2);
201 __ movdqu(Address(rsp,xmm3_off*wordSize),xmm3);
202 __ movdqu(Address(rsp,xmm4_off*wordSize),xmm4);
203 __ movdqu(Address(rsp,xmm5_off*wordSize),xmm5);
204 __ movdqu(Address(rsp,xmm6_off*wordSize),xmm6);
205 __ movdqu(Address(rsp,xmm7_off*wordSize),xmm7);
206 }
207
208 if (vect_words > 0) {
209 assert(vect_words*wordSize == 128, "");
210 __ subptr(rsp, 128); // Save upper half of YMM registes
211 __ vextractf128h(Address(rsp, 0),xmm0);
212 __ vextractf128h(Address(rsp, 16),xmm1);
213 __ vextractf128h(Address(rsp, 32),xmm2);
214 __ vextractf128h(Address(rsp, 48),xmm3);
215 __ vextractf128h(Address(rsp, 64),xmm4);
216 __ vextractf128h(Address(rsp, 80),xmm5);
217 __ vextractf128h(Address(rsp, 96),xmm6);
218 __ vextractf128h(Address(rsp,112),xmm7);
219 }
220
221 // Set an oopmap for the call site. This oopmap will map all
222 // oop-registers and debug-info registers as callee-saved. This
223 // will allow deoptimization at this safepoint to find all possible
224 // debug-info recordings, as well as let GC find all oops.
225
226 OopMapSet *oop_maps = new OopMapSet();
227 OopMap* map = new OopMap( frame_words, 0 );
228
229 #define STACK_OFFSET(x) VMRegImpl::stack2reg((x) + additional_frame_words)
230
231 map->set_callee_saved(STACK_OFFSET( rax_off), rax->as_VMReg());
232 map->set_callee_saved(STACK_OFFSET( rcx_off), rcx->as_VMReg());
233 map->set_callee_saved(STACK_OFFSET( rdx_off), rdx->as_VMReg());
234 map->set_callee_saved(STACK_OFFSET( rbx_off), rbx->as_VMReg());
235 // rbp, location is known implicitly, no oopMap
236 map->set_callee_saved(STACK_OFFSET( rsi_off), rsi->as_VMReg());
237 map->set_callee_saved(STACK_OFFSET( rdi_off), rdi->as_VMReg());
238 map->set_callee_saved(STACK_OFFSET(st0_off), as_FloatRegister(0)->as_VMReg());
239 map->set_callee_saved(STACK_OFFSET(st1_off), as_FloatRegister(1)->as_VMReg());
240 map->set_callee_saved(STACK_OFFSET(st2_off), as_FloatRegister(2)->as_VMReg());
241 map->set_callee_saved(STACK_OFFSET(st3_off), as_FloatRegister(3)->as_VMReg());
242 map->set_callee_saved(STACK_OFFSET(st4_off), as_FloatRegister(4)->as_VMReg());
243 map->set_callee_saved(STACK_OFFSET(st5_off), as_FloatRegister(5)->as_VMReg());
244 map->set_callee_saved(STACK_OFFSET(st6_off), as_FloatRegister(6)->as_VMReg());
245 map->set_callee_saved(STACK_OFFSET(st7_off), as_FloatRegister(7)->as_VMReg());
246 map->set_callee_saved(STACK_OFFSET(xmm0_off), xmm0->as_VMReg());
247 map->set_callee_saved(STACK_OFFSET(xmm1_off), xmm1->as_VMReg());
248 map->set_callee_saved(STACK_OFFSET(xmm2_off), xmm2->as_VMReg());
249 map->set_callee_saved(STACK_OFFSET(xmm3_off), xmm3->as_VMReg());
250 map->set_callee_saved(STACK_OFFSET(xmm4_off), xmm4->as_VMReg());
251 map->set_callee_saved(STACK_OFFSET(xmm5_off), xmm5->as_VMReg());
252 map->set_callee_saved(STACK_OFFSET(xmm6_off), xmm6->as_VMReg());
253 map->set_callee_saved(STACK_OFFSET(xmm7_off), xmm7->as_VMReg());
254 // %%% This is really a waste but we'll keep things as they were for now
255 if (true) {
256 #define NEXTREG(x) (x)->as_VMReg()->next()
257 map->set_callee_saved(STACK_OFFSET(st0H_off), NEXTREG(as_FloatRegister(0)));
258 map->set_callee_saved(STACK_OFFSET(st1H_off), NEXTREG(as_FloatRegister(1)));
259 map->set_callee_saved(STACK_OFFSET(st2H_off), NEXTREG(as_FloatRegister(2)));
260 map->set_callee_saved(STACK_OFFSET(st3H_off), NEXTREG(as_FloatRegister(3)));
261 map->set_callee_saved(STACK_OFFSET(st4H_off), NEXTREG(as_FloatRegister(4)));
262 map->set_callee_saved(STACK_OFFSET(st5H_off), NEXTREG(as_FloatRegister(5)));
263 map->set_callee_saved(STACK_OFFSET(st6H_off), NEXTREG(as_FloatRegister(6)));
264 map->set_callee_saved(STACK_OFFSET(st7H_off), NEXTREG(as_FloatRegister(7)));
265 map->set_callee_saved(STACK_OFFSET(xmm0H_off), NEXTREG(xmm0));
266 map->set_callee_saved(STACK_OFFSET(xmm1H_off), NEXTREG(xmm1));
267 map->set_callee_saved(STACK_OFFSET(xmm2H_off), NEXTREG(xmm2));
268 map->set_callee_saved(STACK_OFFSET(xmm3H_off), NEXTREG(xmm3));
269 map->set_callee_saved(STACK_OFFSET(xmm4H_off), NEXTREG(xmm4));
270 map->set_callee_saved(STACK_OFFSET(xmm5H_off), NEXTREG(xmm5));
271 map->set_callee_saved(STACK_OFFSET(xmm6H_off), NEXTREG(xmm6));
272 map->set_callee_saved(STACK_OFFSET(xmm7H_off), NEXTREG(xmm7));
273 #undef NEXTREG
274 #undef STACK_OFFSET
275 }
276
277 return map;
278
279 }
280
281 void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) {
282 // Recover XMM & FPU state
283 int additional_frame_bytes = 0;
284 #ifdef COMPILER2
285 if (restore_vectors) {
286 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
287 assert(MaxVectorSize == 32, "only 256bit vectors are supported now");
288 additional_frame_bytes = 128;
289 }
290 #else
291 assert(!restore_vectors, "vectors are generated only by C2");
292 #endif
293 if (UseSSE == 1) {
294 assert(additional_frame_bytes == 0, "");
295 __ movflt(xmm0,Address(rsp,xmm0_off*wordSize));
296 __ movflt(xmm1,Address(rsp,xmm1_off*wordSize));
297 __ movflt(xmm2,Address(rsp,xmm2_off*wordSize));
298 __ movflt(xmm3,Address(rsp,xmm3_off*wordSize));
299 __ movflt(xmm4,Address(rsp,xmm4_off*wordSize));
300 __ movflt(xmm5,Address(rsp,xmm5_off*wordSize));
301 __ movflt(xmm6,Address(rsp,xmm6_off*wordSize));
302 __ movflt(xmm7,Address(rsp,xmm7_off*wordSize));
303 } else if (UseSSE >= 2) {
304 #define STACK_ADDRESS(x) Address(rsp,(x)*wordSize + additional_frame_bytes)
305 __ movdqu(xmm0,STACK_ADDRESS(xmm0_off));
306 __ movdqu(xmm1,STACK_ADDRESS(xmm1_off));
307 __ movdqu(xmm2,STACK_ADDRESS(xmm2_off));
308 __ movdqu(xmm3,STACK_ADDRESS(xmm3_off));
309 __ movdqu(xmm4,STACK_ADDRESS(xmm4_off));
310 __ movdqu(xmm5,STACK_ADDRESS(xmm5_off));
311 __ movdqu(xmm6,STACK_ADDRESS(xmm6_off));
312 __ movdqu(xmm7,STACK_ADDRESS(xmm7_off));
313 #undef STACK_ADDRESS
314 }
315 if (restore_vectors) {
316 // Restore upper half of YMM registes.
317 assert(additional_frame_bytes == 128, "");
318 __ vinsertf128h(xmm0, Address(rsp, 0));
319 __ vinsertf128h(xmm1, Address(rsp, 16));
320 __ vinsertf128h(xmm2, Address(rsp, 32));
321 __ vinsertf128h(xmm3, Address(rsp, 48));
322 __ vinsertf128h(xmm4, Address(rsp, 64));
323 __ vinsertf128h(xmm5, Address(rsp, 80));
324 __ vinsertf128h(xmm6, Address(rsp, 96));
325 __ vinsertf128h(xmm7, Address(rsp,112));
326 __ addptr(rsp, additional_frame_bytes);
327 }
328 __ pop_FPU_state();
329 __ addptr(rsp, FPU_regs_live*wordSize); // Pop FPU registers
330
331 __ popf();
332 __ popa();
333 // Get the rbp, described implicitly by the frame sender code (no oopMap)
334 __ pop(rbp);
335
336 }
337
338 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
339
340 // Just restore result register. Only used by deoptimization. By
341 // now any callee save register that needs to be restore to a c2
342 // caller of the deoptee has been extracted into the vframeArray
343 // and will be stuffed into the c2i adapter we create for later
344 // restoration so only result registers need to be restored here.
345 //
346
347 __ frstor(Address(rsp, 0)); // Restore fpu state
348
349 // Recover XMM & FPU state
350 if( UseSSE == 1 ) {
351 __ movflt(xmm0, Address(rsp, xmm0_off*wordSize));
352 } else if( UseSSE >= 2 ) {
353 __ movdbl(xmm0, Address(rsp, xmm0_off*wordSize));
354 }
355 __ movptr(rax, Address(rsp, rax_off*wordSize));
356 __ movptr(rdx, Address(rsp, rdx_off*wordSize));
357 // Pop all of the register save are off the stack except the return address
358 __ addptr(rsp, return_off * wordSize);
359 }
360
361 // Is vector's size (in bytes) bigger than a size saved by default?
362 // 16 bytes XMM registers are saved by default using SSE2 movdqu instructions.
363 // Note, MaxVectorSize == 0 with UseSSE < 2 and vectors are not generated.
364 bool SharedRuntime::is_wide_vector(int size) {
365 return size > 16;
366 }
367
368 // The java_calling_convention describes stack locations as ideal slots on
369 // a frame with no abi restrictions. Since we must observe abi restrictions
370 // (like the placement of the register window) the slots must be biased by
371 // the following value.
372 static int reg2offset_in(VMReg r) {
373 // Account for saved rbp, and return address
374 // This should really be in_preserve_stack_slots
375 return (r->reg2stack() + 2) * VMRegImpl::stack_slot_size;
376 }
377
378 static int reg2offset_out(VMReg r) {
379 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
380 }
381
382 // ---------------------------------------------------------------------------
383 // Read the array of BasicTypes from a signature, and compute where the
384 // arguments should go. Values in the VMRegPair regs array refer to 4-byte
385 // quantities. Values less than SharedInfo::stack0 are registers, those above
386 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer
387 // as framesizes are fixed.
388 // VMRegImpl::stack0 refers to the first slot 0(sp).
389 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
390 // up to RegisterImpl::number_of_registers) are the 32-bit
391 // integer registers.
392
393 // Pass first two oop/int args in registers ECX and EDX.
394 // Pass first two float/double args in registers XMM0 and XMM1.
395 // Doubles have precedence, so if you pass a mix of floats and doubles
396 // the doubles will grab the registers before the floats will.
397
398 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
399 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
400 // units regardless of build. Of course for i486 there is no 64 bit build
401
402
403 // ---------------------------------------------------------------------------
404 // The compiled Java calling convention.
405 // Pass first two oop/int args in registers ECX and EDX.
406 // Pass first two float/double args in registers XMM0 and XMM1.
407 // Doubles have precedence, so if you pass a mix of floats and doubles
408 // the doubles will grab the registers before the floats will.
409 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
410 VMRegPair *regs,
411 int total_args_passed,
412 int is_outgoing) {
413 uint stack = 0; // Starting stack position for args on stack
414
415
416 // Pass first two oop/int args in registers ECX and EDX.
417 uint reg_arg0 = 9999;
418 uint reg_arg1 = 9999;
419
420 // Pass first two float/double args in registers XMM0 and XMM1.
421 // Doubles have precedence, so if you pass a mix of floats and doubles
422 // the doubles will grab the registers before the floats will.
423 // CNC - TURNED OFF FOR non-SSE.
424 // On Intel we have to round all doubles (and most floats) at
425 // call sites by storing to the stack in any case.
426 // UseSSE=0 ==> Don't Use ==> 9999+0
427 // UseSSE=1 ==> Floats only ==> 9999+1
428 // UseSSE>=2 ==> Floats or doubles ==> 9999+2
429 enum { fltarg_dontuse = 9999+0, fltarg_float_only = 9999+1, fltarg_flt_dbl = 9999+2 };
430 uint fargs = (UseSSE>=2) ? 2 : UseSSE;
431 uint freg_arg0 = 9999+fargs;
432 uint freg_arg1 = 9999+fargs;
433
434 // Pass doubles & longs aligned on the stack. First count stack slots for doubles
435 int i;
436 for( i = 0; i < total_args_passed; i++) {
437 if( sig_bt[i] == T_DOUBLE ) {
438 // first 2 doubles go in registers
439 if( freg_arg0 == fltarg_flt_dbl ) freg_arg0 = i;
440 else if( freg_arg1 == fltarg_flt_dbl ) freg_arg1 = i;
441 else // Else double is passed low on the stack to be aligned.
442 stack += 2;
443 } else if( sig_bt[i] == T_LONG ) {
444 stack += 2;
445 }
446 }
447 int dstack = 0; // Separate counter for placing doubles
448
449 // Now pick where all else goes.
450 for( i = 0; i < total_args_passed; i++) {
451 // From the type and the argument number (count) compute the location
452 switch( sig_bt[i] ) {
453 case T_SHORT:
454 case T_CHAR:
455 case T_BYTE:
456 case T_BOOLEAN:
457 case T_INT:
458 case T_ARRAY:
459 case T_OBJECT:
460 case T_ADDRESS:
461 if( reg_arg0 == 9999 ) {
462 reg_arg0 = i;
463 regs[i].set1(rcx->as_VMReg());
464 } else if( reg_arg1 == 9999 ) {
465 reg_arg1 = i;
466 regs[i].set1(rdx->as_VMReg());
467 } else {
468 regs[i].set1(VMRegImpl::stack2reg(stack++));
469 }
470 break;
471 case T_FLOAT:
472 if( freg_arg0 == fltarg_flt_dbl || freg_arg0 == fltarg_float_only ) {
473 freg_arg0 = i;
474 regs[i].set1(xmm0->as_VMReg());
475 } else if( freg_arg1 == fltarg_flt_dbl || freg_arg1 == fltarg_float_only ) {
476 freg_arg1 = i;
477 regs[i].set1(xmm1->as_VMReg());
478 } else {
479 regs[i].set1(VMRegImpl::stack2reg(stack++));
480 }
481 break;
482 case T_LONG:
483 assert(sig_bt[i+1] == T_VOID, "missing Half" );
484 regs[i].set2(VMRegImpl::stack2reg(dstack));
485 dstack += 2;
486 break;
487 case T_DOUBLE:
488 assert(sig_bt[i+1] == T_VOID, "missing Half" );
489 if( freg_arg0 == (uint)i ) {
490 regs[i].set2(xmm0->as_VMReg());
491 } else if( freg_arg1 == (uint)i ) {
492 regs[i].set2(xmm1->as_VMReg());
493 } else {
494 regs[i].set2(VMRegImpl::stack2reg(dstack));
495 dstack += 2;
496 }
497 break;
498 case T_VOID: regs[i].set_bad(); break;
499 break;
500 default:
501 ShouldNotReachHere();
502 break;
503 }
504 }
505
506 // return value can be odd number of VMRegImpl stack slots make multiple of 2
507 return round_to(stack, 2);
508 }
509
510 // Patch the callers callsite with entry to compiled code if it exists.
511 static void patch_callers_callsite(MacroAssembler *masm) {
512 Label L;
513 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
514 __ jcc(Assembler::equal, L);
515 // Schedule the branch target address early.
516 // Call into the VM to patch the caller, then jump to compiled callee
517 // rax, isn't live so capture return address while we easily can
518 __ movptr(rax, Address(rsp, 0));
519 __ pusha();
520 __ pushf();
521
522 if (UseSSE == 1) {
523 __ subptr(rsp, 2*wordSize);
524 __ movflt(Address(rsp, 0), xmm0);
525 __ movflt(Address(rsp, wordSize), xmm1);
526 }
527 if (UseSSE >= 2) {
528 __ subptr(rsp, 4*wordSize);
529 __ movdbl(Address(rsp, 0), xmm0);
530 __ movdbl(Address(rsp, 2*wordSize), xmm1);
531 }
532 #ifdef COMPILER2
533 // C2 may leave the stack dirty if not in SSE2+ mode
534 if (UseSSE >= 2) {
535 __ verify_FPU(0, "c2i transition should have clean FPU stack");
536 } else {
537 __ empty_FPU_stack();
538 }
539 #endif /* COMPILER2 */
540
541 // VM needs caller's callsite
542 __ push(rax);
543 // VM needs target method
544 __ push(rbx);
545 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
546 __ addptr(rsp, 2*wordSize);
547
548 if (UseSSE == 1) {
549 __ movflt(xmm0, Address(rsp, 0));
550 __ movflt(xmm1, Address(rsp, wordSize));
551 __ addptr(rsp, 2*wordSize);
552 }
553 if (UseSSE >= 2) {
554 __ movdbl(xmm0, Address(rsp, 0));
555 __ movdbl(xmm1, Address(rsp, 2*wordSize));
556 __ addptr(rsp, 4*wordSize);
557 }
558
559 __ popf();
560 __ popa();
561 __ bind(L);
562 }
563
564
565 static void move_c2i_double(MacroAssembler *masm, XMMRegister r, int st_off) {
566 int next_off = st_off - Interpreter::stackElementSize;
567 __ movdbl(Address(rsp, next_off), r);
568 }
569
570 static void gen_c2i_adapter(MacroAssembler *masm,
571 int total_args_passed,
572 int comp_args_on_stack,
573 const BasicType *sig_bt,
574 const VMRegPair *regs,
575 Label& skip_fixup) {
576 // Before we get into the guts of the C2I adapter, see if we should be here
577 // at all. We've come from compiled code and are attempting to jump to the
578 // interpreter, which means the caller made a static call to get here
579 // (vcalls always get a compiled target if there is one). Check for a
580 // compiled target. If there is one, we need to patch the caller's call.
581 patch_callers_callsite(masm);
582
583 __ bind(skip_fixup);
584
585 #ifdef COMPILER2
586 // C2 may leave the stack dirty if not in SSE2+ mode
587 if (UseSSE >= 2) {
588 __ verify_FPU(0, "c2i transition should have clean FPU stack");
589 } else {
590 __ empty_FPU_stack();
591 }
592 #endif /* COMPILER2 */
593
594 // Since all args are passed on the stack, total_args_passed * interpreter_
595 // stack_element_size is the
596 // space we need.
597 int extraspace = total_args_passed * Interpreter::stackElementSize;
598
599 // Get return address
600 __ pop(rax);
601
602 // set senderSP value
603 __ movptr(rsi, rsp);
604
605 __ subptr(rsp, extraspace);
606
607 // Now write the args into the outgoing interpreter space
608 for (int i = 0; i < total_args_passed; i++) {
609 if (sig_bt[i] == T_VOID) {
610 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
611 continue;
612 }
613
614 // st_off points to lowest address on stack.
615 int st_off = ((total_args_passed - 1) - i) * Interpreter::stackElementSize;
616 int next_off = st_off - Interpreter::stackElementSize;
617
618 // Say 4 args:
619 // i st_off
620 // 0 12 T_LONG
621 // 1 8 T_VOID
622 // 2 4 T_OBJECT
623 // 3 0 T_BOOL
624 VMReg r_1 = regs[i].first();
625 VMReg r_2 = regs[i].second();
626 if (!r_1->is_valid()) {
627 assert(!r_2->is_valid(), "");
628 continue;
629 }
630
631 if (r_1->is_stack()) {
632 // memory to memory use fpu stack top
633 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
634
635 if (!r_2->is_valid()) {
636 __ movl(rdi, Address(rsp, ld_off));
637 __ movptr(Address(rsp, st_off), rdi);
638 } else {
639
640 // ld_off == LSW, ld_off+VMRegImpl::stack_slot_size == MSW
641 // st_off == MSW, st_off-wordSize == LSW
642
643 __ movptr(rdi, Address(rsp, ld_off));
644 __ movptr(Address(rsp, next_off), rdi);
645 #ifndef _LP64
646 __ movptr(rdi, Address(rsp, ld_off + wordSize));
647 __ movptr(Address(rsp, st_off), rdi);
648 #else
649 #ifdef ASSERT
650 // Overwrite the unused slot with known junk
651 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
652 __ movptr(Address(rsp, st_off), rax);
653 #endif /* ASSERT */
654 #endif // _LP64
655 }
656 } else if (r_1->is_Register()) {
657 Register r = r_1->as_Register();
658 if (!r_2->is_valid()) {
659 __ movl(Address(rsp, st_off), r);
660 } else {
661 // long/double in gpr
662 NOT_LP64(ShouldNotReachHere());
663 // Two VMRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
664 // T_DOUBLE and T_LONG use two slots in the interpreter
665 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
666 // long/double in gpr
667 #ifdef ASSERT
668 // Overwrite the unused slot with known junk
669 LP64_ONLY(__ mov64(rax, CONST64(0xdeadffffdeadaaab)));
670 __ movptr(Address(rsp, st_off), rax);
671 #endif /* ASSERT */
672 __ movptr(Address(rsp, next_off), r);
673 } else {
674 __ movptr(Address(rsp, st_off), r);
675 }
676 }
677 } else {
678 assert(r_1->is_XMMRegister(), "");
679 if (!r_2->is_valid()) {
680 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
681 } else {
682 assert(sig_bt[i] == T_DOUBLE || sig_bt[i] == T_LONG, "wrong type");
683 move_c2i_double(masm, r_1->as_XMMRegister(), st_off);
684 }
685 }
686 }
687
688 // Schedule the branch target address early.
689 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
690 // And repush original return address
691 __ push(rax);
692 __ jmp(rcx);
693 }
694
695
696 static void move_i2c_double(MacroAssembler *masm, XMMRegister r, Register saved_sp, int ld_off) {
697 int next_val_off = ld_off - Interpreter::stackElementSize;
698 __ movdbl(r, Address(saved_sp, next_val_off));
699 }
700
701 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg,
702 address code_start, address code_end,
703 Label& L_ok) {
704 Label L_fail;
705 __ lea(temp_reg, ExternalAddress(code_start));
706 __ cmpptr(pc_reg, temp_reg);
707 __ jcc(Assembler::belowEqual, L_fail);
708 __ lea(temp_reg, ExternalAddress(code_end));
709 __ cmpptr(pc_reg, temp_reg);
710 __ jcc(Assembler::below, L_ok);
711 __ bind(L_fail);
712 }
713
714 static void gen_i2c_adapter(MacroAssembler *masm,
715 int total_args_passed,
716 int comp_args_on_stack,
717 const BasicType *sig_bt,
718 const VMRegPair *regs) {
719
720 // Note: rsi contains the senderSP on entry. We must preserve it since
721 // we may do a i2c -> c2i transition if we lose a race where compiled
722 // code goes non-entrant while we get args ready.
723
724 // Adapters can be frameless because they do not require the caller
725 // to perform additional cleanup work, such as correcting the stack pointer.
726 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
727 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
728 // even if a callee has modified the stack pointer.
729 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
730 // routinely repairs its caller's stack pointer (from sender_sp, which is set
731 // up via the senderSP register).
732 // In other words, if *either* the caller or callee is interpreted, we can
733 // get the stack pointer repaired after a call.
734 // This is why c2i and i2c adapters cannot be indefinitely composed.
735 // In particular, if a c2i adapter were to somehow call an i2c adapter,
736 // both caller and callee would be compiled methods, and neither would
737 // clean up the stack pointer changes performed by the two adapters.
738 // If this happens, control eventually transfers back to the compiled
739 // caller, but with an uncorrected stack, causing delayed havoc.
740
741 // Pick up the return address
742 __ movptr(rax, Address(rsp, 0));
743
744 if (VerifyAdapterCalls &&
745 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) {
746 // So, let's test for cascading c2i/i2c adapters right now.
747 // assert(Interpreter::contains($return_addr) ||
748 // StubRoutines::contains($return_addr),
749 // "i2c adapter must return to an interpreter frame");
750 __ block_comment("verify_i2c { ");
751 Label L_ok;
752 if (Interpreter::code() != NULL)
753 range_check(masm, rax, rdi,
754 Interpreter::code()->code_start(), Interpreter::code()->code_end(),
755 L_ok);
756 if (StubRoutines::code1() != NULL)
757 range_check(masm, rax, rdi,
758 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
759 L_ok);
760 if (StubRoutines::code2() != NULL)
761 range_check(masm, rax, rdi,
762 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
763 L_ok);
764 const char* msg = "i2c adapter must return to an interpreter frame";
765 __ block_comment(msg);
766 __ stop(msg);
767 __ bind(L_ok);
768 __ block_comment("} verify_i2ce ");
769 }
770
771 // Must preserve original SP for loading incoming arguments because
772 // we need to align the outgoing SP for compiled code.
773 __ movptr(rdi, rsp);
774
775 // Cut-out for having no stack args. Since up to 2 int/oop args are passed
776 // in registers, we will occasionally have no stack args.
777 int comp_words_on_stack = 0;
778 if (comp_args_on_stack) {
779 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
780 // registers are below. By subtracting stack0, we either get a negative
781 // number (all values in registers) or the maximum stack slot accessed.
782 // int comp_args_on_stack = VMRegImpl::reg2stack(max_arg);
783 // Convert 4-byte stack slots to words.
784 comp_words_on_stack = round_to(comp_args_on_stack*4, wordSize)>>LogBytesPerWord;
785 // Round up to miminum stack alignment, in wordSize
786 comp_words_on_stack = round_to(comp_words_on_stack, 2);
787 __ subptr(rsp, comp_words_on_stack * wordSize);
788 }
789
790 // Align the outgoing SP
791 __ andptr(rsp, -(StackAlignmentInBytes));
792
793 // push the return address on the stack (note that pushing, rather
794 // than storing it, yields the correct frame alignment for the callee)
795 __ push(rax);
796
797 // Put saved SP in another register
798 const Register saved_sp = rax;
799 __ movptr(saved_sp, rdi);
800
801
802 // Will jump to the compiled code just as if compiled code was doing it.
803 // Pre-load the register-jump target early, to schedule it better.
804 __ movptr(rdi, Address(rbx, in_bytes(Method::from_compiled_offset())));
805
806 // Now generate the shuffle code. Pick up all register args and move the
807 // rest through the floating point stack top.
808 for (int i = 0; i < total_args_passed; i++) {
809 if (sig_bt[i] == T_VOID) {
810 // Longs and doubles are passed in native word order, but misaligned
811 // in the 32-bit build.
812 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
813 continue;
814 }
815
816 // Pick up 0, 1 or 2 words from SP+offset.
817
818 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
819 "scrambled load targets?");
820 // Load in argument order going down.
821 int ld_off = (total_args_passed - i) * Interpreter::stackElementSize;
822 // Point to interpreter value (vs. tag)
823 int next_off = ld_off - Interpreter::stackElementSize;
824 //
825 //
826 //
827 VMReg r_1 = regs[i].first();
828 VMReg r_2 = regs[i].second();
829 if (!r_1->is_valid()) {
830 assert(!r_2->is_valid(), "");
831 continue;
832 }
833 if (r_1->is_stack()) {
834 // Convert stack slot to an SP offset (+ wordSize to account for return address )
835 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
836
837 // We can use rsi as a temp here because compiled code doesn't need rsi as an input
838 // and if we end up going thru a c2i because of a miss a reasonable value of rsi
839 // we be generated.
840 if (!r_2->is_valid()) {
841 // __ fld_s(Address(saved_sp, ld_off));
842 // __ fstp_s(Address(rsp, st_off));
843 __ movl(rsi, Address(saved_sp, ld_off));
844 __ movptr(Address(rsp, st_off), rsi);
845 } else {
846 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
847 // are accessed as negative so LSW is at LOW address
848
849 // ld_off is MSW so get LSW
850 // st_off is LSW (i.e. reg.first())
851 // __ fld_d(Address(saved_sp, next_off));
852 // __ fstp_d(Address(rsp, st_off));
853 //
854 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
855 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
856 // So we must adjust where to pick up the data to match the interpreter.
857 //
858 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
859 // are accessed as negative so LSW is at LOW address
860
861 // ld_off is MSW so get LSW
862 const int offset = (NOT_LP64(true ||) sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
863 next_off : ld_off;
864 __ movptr(rsi, Address(saved_sp, offset));
865 __ movptr(Address(rsp, st_off), rsi);
866 #ifndef _LP64
867 __ movptr(rsi, Address(saved_sp, ld_off));
868 __ movptr(Address(rsp, st_off + wordSize), rsi);
869 #endif // _LP64
870 }
871 } else if (r_1->is_Register()) { // Register argument
872 Register r = r_1->as_Register();
873 assert(r != rax, "must be different");
874 if (r_2->is_valid()) {
875 //
876 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
877 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
878 // So we must adjust where to pick up the data to match the interpreter.
879
880 const int offset = (NOT_LP64(true ||) sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
881 next_off : ld_off;
882
883 // this can be a misaligned move
884 __ movptr(r, Address(saved_sp, offset));
885 #ifndef _LP64
886 assert(r_2->as_Register() != rax, "need another temporary register");
887 // Remember r_1 is low address (and LSB on x86)
888 // So r_2 gets loaded from high address regardless of the platform
889 __ movptr(r_2->as_Register(), Address(saved_sp, ld_off));
890 #endif // _LP64
891 } else {
892 __ movl(r, Address(saved_sp, ld_off));
893 }
894 } else {
895 assert(r_1->is_XMMRegister(), "");
896 if (!r_2->is_valid()) {
897 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
898 } else {
899 move_i2c_double(masm, r_1->as_XMMRegister(), saved_sp, ld_off);
900 }
901 }
902 }
903
904 // 6243940 We might end up in handle_wrong_method if
905 // the callee is deoptimized as we race thru here. If that
906 // happens we don't want to take a safepoint because the
907 // caller frame will look interpreted and arguments are now
908 // "compiled" so it is much better to make this transition
909 // invisible to the stack walking code. Unfortunately if
910 // we try and find the callee by normal means a safepoint
911 // is possible. So we stash the desired callee in the thread
912 // and the vm will find there should this case occur.
913
914 __ get_thread(rax);
915 __ movptr(Address(rax, JavaThread::callee_target_offset()), rbx);
916
917 // move Method* to rax, in case we end up in an c2i adapter.
918 // the c2i adapters expect Method* in rax, (c2) because c2's
919 // resolve stubs return the result (the method) in rax,.
920 // I'd love to fix this.
921 __ mov(rax, rbx);
922
923 __ jmp(rdi);
924 }
925
926 // ---------------------------------------------------------------
927 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
928 int total_args_passed,
929 int comp_args_on_stack,
930 const BasicType *sig_bt,
931 const VMRegPair *regs,
932 AdapterFingerPrint* fingerprint) {
933 address i2c_entry = __ pc();
934
935 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
936
937 // -------------------------------------------------------------------------
938 // Generate a C2I adapter. On entry we know rbx, holds the Method* during calls
939 // to the interpreter. The args start out packed in the compiled layout. They
940 // need to be unpacked into the interpreter layout. This will almost always
941 // require some stack space. We grow the current (compiled) stack, then repack
942 // the args. We finally end in a jump to the generic interpreter entry point.
943 // On exit from the interpreter, the interpreter will restore our SP (lest the
944 // compiled code, which relys solely on SP and not EBP, get sick).
945
946 address c2i_unverified_entry = __ pc();
947 Label skip_fixup;
948
949 Register holder = rax;
950 Register receiver = rcx;
951 Register temp = rbx;
952
953 {
954
955 Label missed;
956 __ movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
957 __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset()));
958 __ movptr(rbx, Address(holder, CompiledICHolder::holder_metadata_offset()));
959 __ jcc(Assembler::notEqual, missed);
960 // Method might have been compiled since the call site was patched to
961 // interpreted if that is the case treat it as a miss so we can get
962 // the call site corrected.
963 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
964 __ jcc(Assembler::equal, skip_fixup);
965
966 __ bind(missed);
967 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
968 }
969
970 address c2i_entry = __ pc();
971
972 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
973
974 __ flush();
975 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
976 }
977
978 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
979 VMRegPair *regs,
980 VMRegPair *regs2,
981 int total_args_passed) {
982 assert(regs2 == NULL, "not needed on x86");
983 // We return the amount of VMRegImpl stack slots we need to reserve for all
984 // the arguments NOT counting out_preserve_stack_slots.
985
986 uint stack = 0; // All arguments on stack
987
988 for( int i = 0; i < total_args_passed; i++) {
989 // From the type and the argument number (count) compute the location
990 switch( sig_bt[i] ) {
991 case T_BOOLEAN:
992 case T_CHAR:
993 case T_FLOAT:
994 case T_BYTE:
995 case T_SHORT:
996 case T_INT:
997 case T_OBJECT:
998 case T_ARRAY:
999 case T_ADDRESS:
1000 case T_METADATA:
1001 regs[i].set1(VMRegImpl::stack2reg(stack++));
1002 break;
1003 case T_LONG:
1004 case T_DOUBLE: // The stack numbering is reversed from Java
1005 // Since C arguments do not get reversed, the ordering for
1006 // doubles on the stack must be opposite the Java convention
1007 assert(sig_bt[i+1] == T_VOID, "missing Half" );
1008 regs[i].set2(VMRegImpl::stack2reg(stack));
1009 stack += 2;
1010 break;
1011 case T_VOID: regs[i].set_bad(); break;
1012 default:
1013 ShouldNotReachHere();
1014 break;
1015 }
1016 }
1017 return stack;
1018 }
1019
1020 // A simple move of integer like type
1021 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1022 if (src.first()->is_stack()) {
1023 if (dst.first()->is_stack()) {
1024 // stack to stack
1025 // __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1026 // __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1027 __ movl2ptr(rax, Address(rbp, reg2offset_in(src.first())));
1028 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1029 } else {
1030 // stack to reg
1031 __ movl2ptr(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1032 }
1033 } else if (dst.first()->is_stack()) {
1034 // reg to stack
1035 // no need to sign extend on 64bit
1036 __ movptr(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1037 } else {
1038 if (dst.first() != src.first()) {
1039 __ mov(dst.first()->as_Register(), src.first()->as_Register());
1040 }
1041 }
1042 }
1043
1044 // An oop arg. Must pass a handle not the oop itself
1045 static void object_move(MacroAssembler* masm,
1046 OopMap* map,
1047 int oop_handle_offset,
1048 int framesize_in_slots,
1049 VMRegPair src,
1050 VMRegPair dst,
1051 bool is_receiver,
1052 int* receiver_offset) {
1053
1054 // Because of the calling conventions we know that src can be a
1055 // register or a stack location. dst can only be a stack location.
1056
1057 assert(dst.first()->is_stack(), "must be stack");
1058 // must pass a handle. First figure out the location we use as a handle
1059
1060 if (src.first()->is_stack()) {
1061 // Oop is already on the stack as an argument
1062 Register rHandle = rax;
1063 Label nil;
1064 __ xorptr(rHandle, rHandle);
1065 __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
1066 __ jcc(Assembler::equal, nil);
1067 __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1068 __ bind(nil);
1069 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1070
1071 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1072 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1073 if (is_receiver) {
1074 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1075 }
1076 } else {
1077 // Oop is in an a register we must store it to the space we reserve
1078 // on the stack for oop_handles
1079 const Register rOop = src.first()->as_Register();
1080 const Register rHandle = rax;
1081 int oop_slot = (rOop == rcx ? 0 : 1) * VMRegImpl::slots_per_word + oop_handle_offset;
1082 int offset = oop_slot*VMRegImpl::stack_slot_size;
1083 Label skip;
1084 __ movptr(Address(rsp, offset), rOop);
1085 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1086 __ xorptr(rHandle, rHandle);
1087 __ cmpptr(rOop, (int32_t)NULL_WORD);
1088 __ jcc(Assembler::equal, skip);
1089 __ lea(rHandle, Address(rsp, offset));
1090 __ bind(skip);
1091 // Store the handle parameter
1092 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1093 if (is_receiver) {
1094 *receiver_offset = offset;
1095 }
1096 }
1097 }
1098
1099 // A float arg may have to do float reg int reg conversion
1100 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1101 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1102
1103 // Because of the calling convention we know that src is either a stack location
1104 // or an xmm register. dst can only be a stack location.
1105
1106 assert(dst.first()->is_stack() && ( src.first()->is_stack() || src.first()->is_XMMRegister()), "bad parameters");
1107
1108 if (src.first()->is_stack()) {
1109 __ movl(rax, Address(rbp, reg2offset_in(src.first())));
1110 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1111 } else {
1112 // reg to stack
1113 __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1114 }
1115 }
1116
1117 // A long move
1118 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1119
1120 // The only legal possibility for a long_move VMRegPair is:
1121 // 1: two stack slots (possibly unaligned)
1122 // as neither the java or C calling convention will use registers
1123 // for longs.
1124
1125 if (src.first()->is_stack() && dst.first()->is_stack()) {
1126 assert(src.second()->is_stack() && dst.second()->is_stack(), "must be all stack");
1127 __ movptr(rax, Address(rbp, reg2offset_in(src.first())));
1128 NOT_LP64(__ movptr(rbx, Address(rbp, reg2offset_in(src.second()))));
1129 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1130 NOT_LP64(__ movptr(Address(rsp, reg2offset_out(dst.second())), rbx));
1131 } else {
1132 ShouldNotReachHere();
1133 }
1134 }
1135
1136 // A double move
1137 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1138
1139 // The only legal possibilities for a double_move VMRegPair are:
1140 // The painful thing here is that like long_move a VMRegPair might be
1141
1142 // Because of the calling convention we know that src is either
1143 // 1: a single physical register (xmm registers only)
1144 // 2: two stack slots (possibly unaligned)
1145 // dst can only be a pair of stack slots.
1146
1147 assert(dst.first()->is_stack() && (src.first()->is_XMMRegister() || src.first()->is_stack()), "bad args");
1148
1149 if (src.first()->is_stack()) {
1150 // source is all stack
1151 __ movptr(rax, Address(rbp, reg2offset_in(src.first())));
1152 NOT_LP64(__ movptr(rbx, Address(rbp, reg2offset_in(src.second()))));
1153 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1154 NOT_LP64(__ movptr(Address(rsp, reg2offset_out(dst.second())), rbx));
1155 } else {
1156 // reg to stack
1157 // No worries about stack alignment
1158 __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1159 }
1160 }
1161
1162
1163 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1164 // We always ignore the frame_slots arg and just use the space just below frame pointer
1165 // which by this time is free to use
1166 switch (ret_type) {
1167 case T_FLOAT:
1168 __ fstp_s(Address(rbp, -wordSize));
1169 break;
1170 case T_DOUBLE:
1171 __ fstp_d(Address(rbp, -2*wordSize));
1172 break;
1173 case T_VOID: break;
1174 case T_LONG:
1175 __ movptr(Address(rbp, -wordSize), rax);
1176 NOT_LP64(__ movptr(Address(rbp, -2*wordSize), rdx));
1177 break;
1178 default: {
1179 __ movptr(Address(rbp, -wordSize), rax);
1180 }
1181 }
1182 }
1183
1184 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1185 // We always ignore the frame_slots arg and just use the space just below frame pointer
1186 // which by this time is free to use
1187 switch (ret_type) {
1188 case T_FLOAT:
1189 __ fld_s(Address(rbp, -wordSize));
1190 break;
1191 case T_DOUBLE:
1192 __ fld_d(Address(rbp, -2*wordSize));
1193 break;
1194 case T_LONG:
1195 __ movptr(rax, Address(rbp, -wordSize));
1196 NOT_LP64(__ movptr(rdx, Address(rbp, -2*wordSize)));
1197 break;
1198 case T_VOID: break;
1199 default: {
1200 __ movptr(rax, Address(rbp, -wordSize));
1201 }
1202 }
1203 }
1204
1205
1206 static void save_or_restore_arguments(MacroAssembler* masm,
1207 const int stack_slots,
1208 const int total_in_args,
1209 const int arg_save_area,
1210 OopMap* map,
1211 VMRegPair* in_regs,
1212 BasicType* in_sig_bt) {
1213 // if map is non-NULL then the code should store the values,
1214 // otherwise it should load them.
1215 int handle_index = 0;
1216 // Save down double word first
1217 for ( int i = 0; i < total_in_args; i++) {
1218 if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) {
1219 int slot = handle_index * VMRegImpl::slots_per_word + arg_save_area;
1220 int offset = slot * VMRegImpl::stack_slot_size;
1221 handle_index += 2;
1222 assert(handle_index <= stack_slots, "overflow");
1223 if (map != NULL) {
1224 __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1225 } else {
1226 __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1227 }
1228 }
1229 if (in_regs[i].first()->is_Register() && in_sig_bt[i] == T_LONG) {
1230 int slot = handle_index * VMRegImpl::slots_per_word + arg_save_area;
1231 int offset = slot * VMRegImpl::stack_slot_size;
1232 handle_index += 2;
1233 assert(handle_index <= stack_slots, "overflow");
1234 if (map != NULL) {
1235 __ movl(Address(rsp, offset), in_regs[i].first()->as_Register());
1236 if (in_regs[i].second()->is_Register()) {
1237 __ movl(Address(rsp, offset + 4), in_regs[i].second()->as_Register());
1238 }
1239 } else {
1240 __ movl(in_regs[i].first()->as_Register(), Address(rsp, offset));
1241 if (in_regs[i].second()->is_Register()) {
1242 __ movl(in_regs[i].second()->as_Register(), Address(rsp, offset + 4));
1243 }
1244 }
1245 }
1246 }
1247 // Save or restore single word registers
1248 for ( int i = 0; i < total_in_args; i++) {
1249 if (in_regs[i].first()->is_Register()) {
1250 int slot = handle_index++ * VMRegImpl::slots_per_word + arg_save_area;
1251 int offset = slot * VMRegImpl::stack_slot_size;
1252 assert(handle_index <= stack_slots, "overflow");
1253 if (in_sig_bt[i] == T_ARRAY && map != NULL) {
1254 map->set_oop(VMRegImpl::stack2reg(slot));;
1255 }
1256
1257 // Value is in an input register pass we must flush it to the stack
1258 const Register reg = in_regs[i].first()->as_Register();
1259 switch (in_sig_bt[i]) {
1260 case T_ARRAY:
1261 if (map != NULL) {
1262 __ movptr(Address(rsp, offset), reg);
1263 } else {
1264 __ movptr(reg, Address(rsp, offset));
1265 }
1266 break;
1267 case T_BOOLEAN:
1268 case T_CHAR:
1269 case T_BYTE:
1270 case T_SHORT:
1271 case T_INT:
1272 if (map != NULL) {
1273 __ movl(Address(rsp, offset), reg);
1274 } else {
1275 __ movl(reg, Address(rsp, offset));
1276 }
1277 break;
1278 case T_OBJECT:
1279 default: ShouldNotReachHere();
1280 }
1281 } else if (in_regs[i].first()->is_XMMRegister()) {
1282 if (in_sig_bt[i] == T_FLOAT) {
1283 int slot = handle_index++ * VMRegImpl::slots_per_word + arg_save_area;
1284 int offset = slot * VMRegImpl::stack_slot_size;
1285 assert(handle_index <= stack_slots, "overflow");
1286 if (map != NULL) {
1287 __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1288 } else {
1289 __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1290 }
1291 }
1292 } else if (in_regs[i].first()->is_stack()) {
1293 if (in_sig_bt[i] == T_ARRAY && map != NULL) {
1294 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1295 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
1296 }
1297 }
1298 }
1299 }
1300
1301 // Registers need to be saved for runtime call
1302 static Register caller_saved_registers[] = {
1303 rcx, rdx, rsi, rdi
1304 };
1305
1306 // Save caller saved registers except r1 and r2
1307 static void save_registers_except(MacroAssembler* masm, Register r1, Register r2) {
1308 int reg_len = (int)(sizeof(caller_saved_registers) / sizeof(Register));
1309 for (int index = 0; index < reg_len; index ++) {
1310 Register this_reg = caller_saved_registers[index];
1311 if (this_reg != r1 && this_reg != r2) {
1312 __ push(this_reg);
1313 }
1314 }
1315 }
1316
1317 // Restore caller saved registers except r1 and r2
1318 static void restore_registers_except(MacroAssembler* masm, Register r1, Register r2) {
1319 int reg_len = (int)(sizeof(caller_saved_registers) / sizeof(Register));
1320 for (int index = reg_len - 1; index >= 0; index --) {
1321 Register this_reg = caller_saved_registers[index];
1322 if (this_reg != r1 && this_reg != r2) {
1323 __ pop(this_reg);
1324 }
1325 }
1326 }
1327
1328 // Pin object, return pinned object or null in rax
1329 static void gen_pin_object(MacroAssembler* masm,
1330 Register thread, VMRegPair reg) {
1331 __ block_comment("gen_pin_object {");
1332
1333 Label is_null;
1334 Register tmp_reg = rax;
1335 VMRegPair tmp(tmp_reg->as_VMReg());
1336 if (reg.first()->is_stack()) {
1337 // Load the arg up from the stack
1338 simple_move32(masm, reg, tmp);
1339 reg = tmp;
1340 } else {
1341 __ movl(tmp_reg, reg.first()->as_Register());
1342 }
1343 __ testptr(reg.first()->as_Register(), reg.first()->as_Register());
1344 __ jccb(Assembler::equal, is_null);
1345
1346 // Save registers that may be used by runtime call
1347 Register arg = reg.first()->is_Register() ? reg.first()->as_Register() : noreg;
1348 save_registers_except(masm, arg, thread);
1349
1350 __ call_VM_leaf(
1351 CAST_FROM_FN_PTR(address, SharedRuntime::pin_object),
1352 thread, reg.first()->as_Register());
1353
1354 // Restore saved registers
1355 restore_registers_except(masm, arg, thread);
1356
1357 __ bind(is_null);
1358 __ block_comment("} gen_pin_object");
1359 }
1360
1361 // Unpin object
1362 static void gen_unpin_object(MacroAssembler* masm,
1363 Register thread, VMRegPair reg) {
1364 __ block_comment("gen_unpin_object {");
1365 Label is_null;
1366
1367 // temp register
1368 __ push(rax);
1369 Register tmp_reg = rax;
1370 VMRegPair tmp(tmp_reg->as_VMReg());
1371
1372 simple_move32(masm, reg, tmp);
1373
1374 __ testptr(rax, rax);
1375 __ jccb(Assembler::equal, is_null);
1376
1377 // Save registers that may be used by runtime call
1378 Register arg = reg.first()->is_Register() ? reg.first()->as_Register() : noreg;
1379 save_registers_except(masm, arg, thread);
1380
1381 __ call_VM_leaf(
1382 CAST_FROM_FN_PTR(address, SharedRuntime::unpin_object),
1383 thread, rax);
1384
1385 // Restore saved registers
1386 restore_registers_except(masm, arg, thread);
1387 __ bind(is_null);
1388 __ pop(rax);
1389 __ block_comment("} gen_unpin_object");
1390 }
1391
1392 // Check GC_locker::needs_gc and enter the runtime if it's true. This
1393 // keeps a new JNI critical region from starting until a GC has been
1394 // forced. Save down any oops in registers and describe them in an
1395 // OopMap.
1396 static void check_needs_gc_for_critical_native(MacroAssembler* masm,
1397 Register thread,
1398 int stack_slots,
1399 int total_c_args,
1400 int total_in_args,
1401 int arg_save_area,
1402 OopMapSet* oop_maps,
1403 VMRegPair* in_regs,
1404 BasicType* in_sig_bt) {
1405 __ block_comment("check GC_locker::needs_gc");
1406 Label cont;
1407 __ cmp8(ExternalAddress((address)GC_locker::needs_gc_address()), false);
1408 __ jcc(Assembler::equal, cont);
1409
1410 // Save down any incoming oops and call into the runtime to halt for a GC
1411
1412 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1413
1414 save_or_restore_arguments(masm, stack_slots, total_in_args,
1415 arg_save_area, map, in_regs, in_sig_bt);
1416
1417 address the_pc = __ pc();
1418 oop_maps->add_gc_map( __ offset(), map);
1419 __ set_last_Java_frame(thread, rsp, noreg, the_pc);
1420
1421 __ block_comment("block_for_jni_critical");
1422 __ push(thread);
1423 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical)));
1424 __ increment(rsp, wordSize);
1425
1426 __ get_thread(thread);
1427 __ reset_last_Java_frame(thread, false);
1428
1429 save_or_restore_arguments(masm, stack_slots, total_in_args,
1430 arg_save_area, NULL, in_regs, in_sig_bt);
1431
1432 __ bind(cont);
1433 #ifdef ASSERT
1434 if (StressCriticalJNINatives) {
1435 // Stress register saving
1436 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1437 save_or_restore_arguments(masm, stack_slots, total_in_args,
1438 arg_save_area, map, in_regs, in_sig_bt);
1439 // Destroy argument registers
1440 for (int i = 0; i < total_in_args - 1; i++) {
1441 if (in_regs[i].first()->is_Register()) {
1442 const Register reg = in_regs[i].first()->as_Register();
1443 __ xorptr(reg, reg);
1444 } else if (in_regs[i].first()->is_XMMRegister()) {
1445 __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister());
1446 } else if (in_regs[i].first()->is_FloatRegister()) {
1447 ShouldNotReachHere();
1448 } else if (in_regs[i].first()->is_stack()) {
1449 // Nothing to do
1450 } else {
1451 ShouldNotReachHere();
1452 }
1453 if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) {
1454 i++;
1455 }
1456 }
1457
1458 save_or_restore_arguments(masm, stack_slots, total_in_args,
1459 arg_save_area, NULL, in_regs, in_sig_bt);
1460 }
1461 #endif
1462 }
1463
1464 // Unpack an array argument into a pointer to the body and the length
1465 // if the array is non-null, otherwise pass 0 for both.
1466 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
1467 Register tmp_reg = rax;
1468 assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg,
1469 "possible collision");
1470 assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg,
1471 "possible collision");
1472
1473 // Pass the length, ptr pair
1474 Label is_null, done;
1475 VMRegPair tmp(tmp_reg->as_VMReg());
1476 if (reg.first()->is_stack()) {
1477 // Load the arg up from the stack
1478 simple_move32(masm, reg, tmp);
1479 reg = tmp;
1480 }
1481 __ testptr(reg.first()->as_Register(), reg.first()->as_Register());
1482 __ jccb(Assembler::equal, is_null);
1483 __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1484 simple_move32(masm, tmp, body_arg);
1485 // load the length relative to the body.
1486 __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() -
1487 arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1488 simple_move32(masm, tmp, length_arg);
1489 __ jmpb(done);
1490 __ bind(is_null);
1491 // Pass zeros
1492 __ xorptr(tmp_reg, tmp_reg);
1493 simple_move32(masm, tmp, body_arg);
1494 simple_move32(masm, tmp, length_arg);
1495 __ bind(done);
1496 }
1497
1498 static void verify_oop_args(MacroAssembler* masm,
1499 methodHandle method,
1500 const BasicType* sig_bt,
1501 const VMRegPair* regs) {
1502 Register temp_reg = rbx; // not part of any compiled calling seq
1503 if (VerifyOops) {
1504 for (int i = 0; i < method->size_of_parameters(); i++) {
1505 if (sig_bt[i] == T_OBJECT ||
1506 sig_bt[i] == T_ARRAY) {
1507 VMReg r = regs[i].first();
1508 assert(r->is_valid(), "bad oop arg");
1509 if (r->is_stack()) {
1510 __ movptr(temp_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1511 __ verify_oop(temp_reg);
1512 } else {
1513 __ verify_oop(r->as_Register());
1514 }
1515 }
1516 }
1517 }
1518 }
1519
1520 static void gen_special_dispatch(MacroAssembler* masm,
1521 methodHandle method,
1522 const BasicType* sig_bt,
1523 const VMRegPair* regs) {
1524 verify_oop_args(masm, method, sig_bt, regs);
1525 vmIntrinsics::ID iid = method->intrinsic_id();
1526
1527 // Now write the args into the outgoing interpreter space
1528 bool has_receiver = false;
1529 Register receiver_reg = noreg;
1530 int member_arg_pos = -1;
1531 Register member_reg = noreg;
1532 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid);
1533 if (ref_kind != 0) {
1534 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument
1535 member_reg = rbx; // known to be free at this point
1536 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
1537 } else if (iid == vmIntrinsics::_invokeBasic) {
1538 has_receiver = true;
1539 } else {
1540 fatal(err_msg_res("unexpected intrinsic id %d", iid));
1541 }
1542
1543 if (member_reg != noreg) {
1544 // Load the member_arg into register, if necessary.
1545 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs);
1546 VMReg r = regs[member_arg_pos].first();
1547 if (r->is_stack()) {
1548 __ movptr(member_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1549 } else {
1550 // no data motion is needed
1551 member_reg = r->as_Register();
1552 }
1553 }
1554
1555 if (has_receiver) {
1556 // Make sure the receiver is loaded into a register.
1557 assert(method->size_of_parameters() > 0, "oob");
1558 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
1559 VMReg r = regs[0].first();
1560 assert(r->is_valid(), "bad receiver arg");
1561 if (r->is_stack()) {
1562 // Porting note: This assumes that compiled calling conventions always
1563 // pass the receiver oop in a register. If this is not true on some
1564 // platform, pick a temp and load the receiver from stack.
1565 fatal("receiver always in a register");
1566 receiver_reg = rcx; // known to be free at this point
1567 __ movptr(receiver_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1568 } else {
1569 // no data motion is needed
1570 receiver_reg = r->as_Register();
1571 }
1572 }
1573
1574 // Figure out which address we are really jumping to:
1575 MethodHandles::generate_method_handle_dispatch(masm, iid,
1576 receiver_reg, member_reg, /*for_compiler_entry:*/ true);
1577 }
1578
1579 // ---------------------------------------------------------------------------
1580 // Generate a native wrapper for a given method. The method takes arguments
1581 // in the Java compiled code convention, marshals them to the native
1582 // convention (handlizes oops, etc), transitions to native, makes the call,
1583 // returns to java state (possibly blocking), unhandlizes any result and
1584 // returns.
1585 //
1586 // Critical native functions are a shorthand for the use of
1587 // GetPrimtiveArrayCritical and disallow the use of any other JNI
1588 // functions. The wrapper is expected to unpack the arguments before
1589 // passing them to the callee and perform checks before and after the
1590 // native call to ensure that they GC_locker
1591 // lock_critical/unlock_critical semantics are followed. Some other
1592 // parts of JNI setup are skipped like the tear down of the JNI handle
1593 // block and the check for pending exceptions it's impossible for them
1594 // to be thrown.
1595 //
1596 // They are roughly structured like this:
1597 // if (GC_locker::needs_gc())
1598 // SharedRuntime::block_for_jni_critical();
1599 // tranistion to thread_in_native
1600 // unpack arrray arguments and call native entry point
1601 // check for safepoint in progress
1602 // check if any thread suspend flags are set
1603 // call into JVM and possible unlock the JNI critical
1604 // if a GC was suppressed while in the critical native.
1605 // transition back to thread_in_Java
1606 // return to caller
1607 //
1608 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
1609 methodHandle method,
1610 int compile_id,
1611 BasicType* in_sig_bt,
1612 VMRegPair* in_regs,
1613 BasicType ret_type) {
1614 if (method->is_method_handle_intrinsic()) {
1615 vmIntrinsics::ID iid = method->intrinsic_id();
1616 intptr_t start = (intptr_t)__ pc();
1617 int vep_offset = ((intptr_t)__ pc()) - start;
1618 gen_special_dispatch(masm,
1619 method,
1620 in_sig_bt,
1621 in_regs);
1622 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
1623 __ flush();
1624 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually
1625 return nmethod::new_native_nmethod(method,
1626 compile_id,
1627 masm->code(),
1628 vep_offset,
1629 frame_complete,
1630 stack_slots / VMRegImpl::slots_per_word,
1631 in_ByteSize(-1),
1632 in_ByteSize(-1),
1633 (OopMapSet*)NULL);
1634 }
1635 bool is_critical_native = true;
1636 address native_func = method->critical_native_function();
1637 if (native_func == NULL) {
1638 native_func = method->native_function();
1639 is_critical_native = false;
1640 }
1641 assert(native_func != NULL, "must have function");
1642
1643 // An OopMap for lock (and class if static)
1644 OopMapSet *oop_maps = new OopMapSet();
1645
1646 // We have received a description of where all the java arg are located
1647 // on entry to the wrapper. We need to convert these args to where
1648 // the jni function will expect them. To figure out where they go
1649 // we convert the java signature to a C signature by inserting
1650 // the hidden arguments as arg[0] and possibly arg[1] (static method)
1651
1652 const int total_in_args = method->size_of_parameters();
1653 int total_c_args = total_in_args;
1654 if (!is_critical_native) {
1655 total_c_args += 1;
1656 if (method->is_static()) {
1657 total_c_args++;
1658 }
1659 } else {
1660 for (int i = 0; i < total_in_args; i++) {
1661 if (in_sig_bt[i] == T_ARRAY) {
1662 total_c_args++;
1663 }
1664 }
1665 }
1666
1667 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1668 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
1669 BasicType* in_elem_bt = NULL;
1670
1671 int argc = 0;
1672 if (!is_critical_native) {
1673 out_sig_bt[argc++] = T_ADDRESS;
1674 if (method->is_static()) {
1675 out_sig_bt[argc++] = T_OBJECT;
1676 }
1677
1678 for (int i = 0; i < total_in_args ; i++ ) {
1679 out_sig_bt[argc++] = in_sig_bt[i];
1680 }
1681 } else {
1682 Thread* THREAD = Thread::current();
1683 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
1684 SignatureStream ss(method->signature());
1685 for (int i = 0; i < total_in_args ; i++ ) {
1686 if (in_sig_bt[i] == T_ARRAY) {
1687 // Arrays are passed as int, elem* pair
1688 out_sig_bt[argc++] = T_INT;
1689 out_sig_bt[argc++] = T_ADDRESS;
1690 Symbol* atype = ss.as_symbol(CHECK_NULL);
1691 const char* at = atype->as_C_string();
1692 if (strlen(at) == 2) {
1693 assert(at[0] == '[', "must be");
1694 switch (at[1]) {
1695 case 'B': in_elem_bt[i] = T_BYTE; break;
1696 case 'C': in_elem_bt[i] = T_CHAR; break;
1697 case 'D': in_elem_bt[i] = T_DOUBLE; break;
1698 case 'F': in_elem_bt[i] = T_FLOAT; break;
1699 case 'I': in_elem_bt[i] = T_INT; break;
1700 case 'J': in_elem_bt[i] = T_LONG; break;
1701 case 'S': in_elem_bt[i] = T_SHORT; break;
1702 case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
1703 default: ShouldNotReachHere();
1704 }
1705 }
1706 } else {
1707 out_sig_bt[argc++] = in_sig_bt[i];
1708 in_elem_bt[i] = T_VOID;
1709 }
1710 if (in_sig_bt[i] != T_VOID) {
1711 assert(in_sig_bt[i] == ss.type(), "must match");
1712 ss.next();
1713 }
1714 }
1715 }
1716
1717 // Now figure out where the args must be stored and how much stack space
1718 // they require.
1719 int out_arg_slots;
1720 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args);
1721
1722 // Compute framesize for the wrapper. We need to handlize all oops in
1723 // registers a max of 2 on x86.
1724
1725 // Calculate the total number of stack slots we will need.
1726
1727 // First count the abi requirement plus all of the outgoing args
1728 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
1729
1730 // Now the space for the inbound oop handle area
1731 int total_save_slots = 2 * VMRegImpl::slots_per_word; // 2 arguments passed in registers
1732 if (is_critical_native) {
1733 // Critical natives may have to call out so they need a save area
1734 // for register arguments.
1735 int double_slots = 0;
1736 int single_slots = 0;
1737 for ( int i = 0; i < total_in_args; i++) {
1738 if (in_regs[i].first()->is_Register()) {
1739 const Register reg = in_regs[i].first()->as_Register();
1740 switch (in_sig_bt[i]) {
1741 case T_ARRAY: // critical array (uses 2 slots on LP64)
1742 case T_BOOLEAN:
1743 case T_BYTE:
1744 case T_SHORT:
1745 case T_CHAR:
1746 case T_INT: single_slots++; break;
1747 case T_LONG: double_slots++; break;
1748 default: ShouldNotReachHere();
1749 }
1750 } else if (in_regs[i].first()->is_XMMRegister()) {
1751 switch (in_sig_bt[i]) {
1752 case T_FLOAT: single_slots++; break;
1753 case T_DOUBLE: double_slots++; break;
1754 default: ShouldNotReachHere();
1755 }
1756 } else if (in_regs[i].first()->is_FloatRegister()) {
1757 ShouldNotReachHere();
1758 }
1759 }
1760 total_save_slots = double_slots * 2 + single_slots;
1761 // align the save area
1762 if (double_slots != 0) {
1763 stack_slots = round_to(stack_slots, 2);
1764 }
1765 }
1766
1767 int oop_handle_offset = stack_slots;
1768 stack_slots += total_save_slots;
1769
1770 // Now any space we need for handlizing a klass if static method
1771
1772 int klass_slot_offset = 0;
1773 int klass_offset = -1;
1774 int lock_slot_offset = 0;
1775 bool is_static = false;
1776
1777 if (method->is_static()) {
1778 klass_slot_offset = stack_slots;
1779 stack_slots += VMRegImpl::slots_per_word;
1780 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
1781 is_static = true;
1782 }
1783
1784 // Plus a lock if needed
1785
1786 if (method->is_synchronized()) {
1787 lock_slot_offset = stack_slots;
1788 stack_slots += VMRegImpl::slots_per_word;
1789 }
1790
1791 // Now a place (+2) to save return values or temp during shuffling
1792 // + 2 for return address (which we own) and saved rbp,
1793 stack_slots += 4;
1794
1795 // Ok The space we have allocated will look like:
1796 //
1797 //
1798 // FP-> | |
1799 // |---------------------|
1800 // | 2 slots for moves |
1801 // |---------------------|
1802 // | lock box (if sync) |
1803 // |---------------------| <- lock_slot_offset (-lock_slot_rbp_offset)
1804 // | klass (if static) |
1805 // |---------------------| <- klass_slot_offset
1806 // | oopHandle area |
1807 // |---------------------| <- oop_handle_offset (a max of 2 registers)
1808 // | outbound memory |
1809 // | based arguments |
1810 // | |
1811 // |---------------------|
1812 // | |
1813 // SP-> | out_preserved_slots |
1814 //
1815 //
1816 // ****************************************************************************
1817 // WARNING - on Windows Java Natives use pascal calling convention and pop the
1818 // arguments off of the stack after the jni call. Before the call we can use
1819 // instructions that are SP relative. After the jni call we switch to FP
1820 // relative instructions instead of re-adjusting the stack on windows.
1821 // ****************************************************************************
1822
1823
1824 // Now compute actual number of stack words we need rounding to make
1825 // stack properly aligned.
1826 stack_slots = round_to(stack_slots, StackAlignmentInSlots);
1827
1828 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
1829
1830 intptr_t start = (intptr_t)__ pc();
1831
1832 // First thing make an ic check to see if we should even be here
1833
1834 // We are free to use all registers as temps without saving them and
1835 // restoring them except rbp. rbp is the only callee save register
1836 // as far as the interpreter and the compiler(s) are concerned.
1837
1838
1839 const Register ic_reg = rax;
1840 const Register receiver = rcx;
1841 Label hit;
1842 Label exception_pending;
1843
1844 __ verify_oop(receiver);
1845 __ cmpptr(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
1846 __ jcc(Assembler::equal, hit);
1847
1848 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1849
1850 // verified entry must be aligned for code patching.
1851 // and the first 5 bytes must be in the same cache line
1852 // if we align at 8 then we will be sure 5 bytes are in the same line
1853 __ align(8);
1854
1855 __ bind(hit);
1856
1857 int vep_offset = ((intptr_t)__ pc()) - start;
1858
1859 #ifdef COMPILER1
1860 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
1861 // Object.hashCode can pull the hashCode from the header word
1862 // instead of doing a full VM transition once it's been computed.
1863 // Since hashCode is usually polymorphic at call sites we can't do
1864 // this optimization at the call site without a lot of work.
1865 Label slowCase;
1866 Register receiver = rcx;
1867 Register result = rax;
1868 __ movptr(result, Address(receiver, oopDesc::mark_offset_in_bytes()));
1869
1870 // check if locked
1871 __ testptr(result, markOopDesc::unlocked_value);
1872 __ jcc (Assembler::zero, slowCase);
1873
1874 if (UseBiasedLocking) {
1875 // Check if biased and fall through to runtime if so
1876 __ testptr(result, markOopDesc::biased_lock_bit_in_place);
1877 __ jcc (Assembler::notZero, slowCase);
1878 }
1879
1880 // get hash
1881 __ andptr(result, markOopDesc::hash_mask_in_place);
1882 // test if hashCode exists
1883 __ jcc (Assembler::zero, slowCase);
1884 __ shrptr(result, markOopDesc::hash_shift);
1885 __ ret(0);
1886 __ bind (slowCase);
1887 }
1888 #endif // COMPILER1
1889
1890 // The instruction at the verified entry point must be 5 bytes or longer
1891 // because it can be patched on the fly by make_non_entrant. The stack bang
1892 // instruction fits that requirement.
1893
1894 // Generate stack overflow check
1895
1896 if (UseStackBanging) {
1897 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
1898 } else {
1899 // need a 5 byte instruction to allow MT safe patching to non-entrant
1900 __ fat_nop();
1901 }
1902
1903 // Generate a new frame for the wrapper.
1904 __ enter();
1905 // -2 because return address is already present and so is saved rbp
1906 __ subptr(rsp, stack_size - 2*wordSize);
1907
1908 // Frame is now completed as far as size and linkage.
1909 int frame_complete = ((intptr_t)__ pc()) - start;
1910
1911 if (UseRTMLocking) {
1912 // Abort RTM transaction before calling JNI
1913 // because critical section will be large and will be
1914 // aborted anyway. Also nmethod could be deoptimized.
1915 __ xabort(0);
1916 }
1917
1918 // Calculate the difference between rsp and rbp,. We need to know it
1919 // after the native call because on windows Java Natives will pop
1920 // the arguments and it is painful to do rsp relative addressing
1921 // in a platform independent way. So after the call we switch to
1922 // rbp, relative addressing.
1923
1924 int fp_adjustment = stack_size - 2*wordSize;
1925
1926 #ifdef COMPILER2
1927 // C2 may leave the stack dirty if not in SSE2+ mode
1928 if (UseSSE >= 2) {
1929 __ verify_FPU(0, "c2i transition should have clean FPU stack");
1930 } else {
1931 __ empty_FPU_stack();
1932 }
1933 #endif /* COMPILER2 */
1934
1935 // Compute the rbp, offset for any slots used after the jni call
1936
1937 int lock_slot_rbp_offset = (lock_slot_offset*VMRegImpl::stack_slot_size) - fp_adjustment;
1938
1939 // We use rdi as a thread pointer because it is callee save and
1940 // if we load it once it is usable thru the entire wrapper
1941 const Register thread = rdi;
1942
1943 // We use rsi as the oop handle for the receiver/klass
1944 // It is callee save so it survives the call to native
1945
1946 const Register oop_handle_reg = rsi;
1947
1948 __ get_thread(thread);
1949
1950 if (is_critical_native && !Universe::heap()->supports_object_pinning()) {
1951 check_needs_gc_for_critical_native(masm, thread, stack_slots, total_c_args, total_in_args,
1952 oop_handle_offset, oop_maps, in_regs, in_sig_bt);
1953 }
1954
1955 //
1956 // We immediately shuffle the arguments so that any vm call we have to
1957 // make from here on out (sync slow path, jvmti, etc.) we will have
1958 // captured the oops from our caller and have a valid oopMap for
1959 // them.
1960
1961 // -----------------
1962 // The Grand Shuffle
1963 //
1964 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
1965 // and, if static, the class mirror instead of a receiver. This pretty much
1966 // guarantees that register layout will not match (and x86 doesn't use reg
1967 // parms though amd does). Since the native abi doesn't use register args
1968 // and the java conventions does we don't have to worry about collisions.
1969 // All of our moved are reg->stack or stack->stack.
1970 // We ignore the extra arguments during the shuffle and handle them at the
1971 // last moment. The shuffle is described by the two calling convention
1972 // vectors we have in our possession. We simply walk the java vector to
1973 // get the source locations and the c vector to get the destinations.
1974
1975 int c_arg = is_critical_native ? 0 : (method->is_static() ? 2 : 1 );
1976
1977 // Record rsp-based slot for receiver on stack for non-static methods
1978 int receiver_offset = -1;
1979
1980 // This is a trick. We double the stack slots so we can claim
1981 // the oops in the caller's frame. Since we are sure to have
1982 // more args than the caller doubling is enough to make
1983 // sure we can capture all the incoming oop args from the
1984 // caller.
1985 //
1986 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1987
1988 // Inbound arguments that need to be pinned for critical natives
1989 GrowableArray<int> pinned_args(total_in_args);
1990 // Current stack slot for storing register based array argument
1991 int pinned_slot = oop_handle_offset;
1992
1993 // Mark location of rbp,
1994 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, rbp->as_VMReg());
1995
1996 // We know that we only have args in at most two integer registers (rcx, rdx). So rax, rbx
1997 // Are free to temporaries if we have to do stack to steck moves.
1998 // All inbound args are referenced based on rbp, and all outbound args via rsp.
1999
2000 for (int i = 0; i < total_in_args ; i++, c_arg++ ) {
2001 switch (in_sig_bt[i]) {
2002 case T_ARRAY:
2003 if (is_critical_native) {
2004 VMRegPair in_arg = in_regs[i];
2005 if (Universe::heap()->supports_object_pinning()) {
2006 // gen_pin_object handles save and restore
2007 // of any clobbered registers
2008 gen_pin_object(masm, thread, in_arg);
2009 pinned_args.append(i);
2010
2011 // rax has pinned array
2012 VMRegPair result_reg(rax->as_VMReg());
2013 if (!in_arg.first()->is_stack()) {
2014 assert(pinned_slot <= stack_slots, "overflow");
2015 simple_move32(masm, result_reg, VMRegImpl::stack2reg(pinned_slot));
2016 pinned_slot += VMRegImpl::slots_per_word;
2017 } else {
2018 // Write back pinned value, it will be used to unpin this argument
2019 __ movptr(Address(rbp, reg2offset_in(in_arg.first())), result_reg.first()->as_Register());
2020 }
2021 // We have the array in register, use it
2022 in_arg = result_reg;
2023 }
2024
2025 unpack_array_argument(masm, in_arg, in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]);
2026 c_arg++;
2027 break;
2028 }
2029 case T_OBJECT:
2030 assert(!is_critical_native, "no oop arguments");
2031 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
2032 ((i == 0) && (!is_static)),
2033 &receiver_offset);
2034 break;
2035 case T_VOID:
2036 break;
2037
2038 case T_FLOAT:
2039 float_move(masm, in_regs[i], out_regs[c_arg]);
2040 break;
2041
2042 case T_DOUBLE:
2043 assert( i + 1 < total_in_args &&
2044 in_sig_bt[i + 1] == T_VOID &&
2045 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2046 double_move(masm, in_regs[i], out_regs[c_arg]);
2047 break;
2048
2049 case T_LONG :
2050 long_move(masm, in_regs[i], out_regs[c_arg]);
2051 break;
2052
2053 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2054
2055 default:
2056 simple_move32(masm, in_regs[i], out_regs[c_arg]);
2057 }
2058 }
2059
2060 // Pre-load a static method's oop into rsi. Used both by locking code and
2061 // the normal JNI call code.
2062 if (method->is_static() && !is_critical_native) {
2063
2064 // load opp into a register
2065 __ movoop(oop_handle_reg, JNIHandles::make_local(method->method_holder()->java_mirror()));
2066
2067 // Now handlize the static class mirror it's known not-null.
2068 __ movptr(Address(rsp, klass_offset), oop_handle_reg);
2069 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
2070
2071 // Now get the handle
2072 __ lea(oop_handle_reg, Address(rsp, klass_offset));
2073 // store the klass handle as second argument
2074 __ movptr(Address(rsp, wordSize), oop_handle_reg);
2075 }
2076
2077 // Change state to native (we save the return address in the thread, since it might not
2078 // be pushed on the stack when we do a a stack traversal). It is enough that the pc()
2079 // points into the right code segment. It does not have to be the correct return pc.
2080 // We use the same pc/oopMap repeatedly when we call out
2081
2082 intptr_t the_pc = (intptr_t) __ pc();
2083 oop_maps->add_gc_map(the_pc - start, map);
2084
2085 __ set_last_Java_frame(thread, rsp, noreg, (address)the_pc);
2086
2087
2088 // We have all of the arguments setup at this point. We must not touch any register
2089 // argument registers at this point (what if we save/restore them there are no oop?
2090
2091 {
2092 SkipIfEqual skip_if(masm, &DTraceMethodProbes, 0);
2093 __ mov_metadata(rax, method());
2094 __ call_VM_leaf(
2095 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
2096 thread, rax);
2097 }
2098
2099 // RedefineClasses() tracing support for obsolete method entry
2100 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
2101 __ mov_metadata(rax, method());
2102 __ call_VM_leaf(
2103 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
2104 thread, rax);
2105 }
2106
2107 // These are register definitions we need for locking/unlocking
2108 const Register swap_reg = rax; // Must use rax, for cmpxchg instruction
2109 const Register obj_reg = rcx; // Will contain the oop
2110 const Register lock_reg = rdx; // Address of compiler lock object (BasicLock)
2111
2112 Label slow_path_lock;
2113 Label lock_done;
2114
2115 // Lock a synchronized method
2116 if (method->is_synchronized()) {
2117 assert(!is_critical_native, "unhandled");
2118
2119
2120 const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
2121
2122 // Get the handle (the 2nd argument)
2123 __ movptr(oop_handle_reg, Address(rsp, wordSize));
2124
2125 // Get address of the box
2126
2127 __ lea(lock_reg, Address(rbp, lock_slot_rbp_offset));
2128
2129 // Load the oop from the handle
2130 __ movptr(obj_reg, Address(oop_handle_reg, 0));
2131
2132 if (UseBiasedLocking) {
2133 // Note that oop_handle_reg is trashed during this call
2134 __ biased_locking_enter(lock_reg, obj_reg, swap_reg, oop_handle_reg, false, lock_done, &slow_path_lock);
2135 }
2136
2137 // Load immediate 1 into swap_reg %rax,
2138 __ movptr(swap_reg, 1);
2139
2140 // Load (object->mark() | 1) into swap_reg %rax,
2141 __ orptr(swap_reg, Address(obj_reg, 0));
2142
2143 // Save (object->mark() | 1) into BasicLock's displaced header
2144 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2145
2146 if (os::is_MP()) {
2147 __ lock();
2148 }
2149
2150 // src -> dest iff dest == rax, else rax, <- dest
2151 // *obj_reg = lock_reg iff *obj_reg == rax, else rax, = *(obj_reg)
2152 __ cmpxchgptr(lock_reg, Address(obj_reg, 0));
2153 __ jcc(Assembler::equal, lock_done);
2154
2155 // Test if the oopMark is an obvious stack pointer, i.e.,
2156 // 1) (mark & 3) == 0, and
2157 // 2) rsp <= mark < mark + os::pagesize()
2158 // These 3 tests can be done by evaluating the following
2159 // expression: ((mark - rsp) & (3 - os::vm_page_size())),
2160 // assuming both stack pointer and pagesize have their
2161 // least significant 2 bits clear.
2162 // NOTE: the oopMark is in swap_reg %rax, as the result of cmpxchg
2163
2164 __ subptr(swap_reg, rsp);
2165 __ andptr(swap_reg, 3 - os::vm_page_size());
2166
2167 // Save the test result, for recursive case, the result is zero
2168 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2169 __ jcc(Assembler::notEqual, slow_path_lock);
2170 // Slow path will re-enter here
2171 __ bind(lock_done);
2172
2173 if (UseBiasedLocking) {
2174 // Re-fetch oop_handle_reg as we trashed it above
2175 __ movptr(oop_handle_reg, Address(rsp, wordSize));
2176 }
2177 }
2178
2179
2180 // Finally just about ready to make the JNI call
2181
2182
2183 // get JNIEnv* which is first argument to native
2184 if (!is_critical_native) {
2185 __ lea(rdx, Address(thread, in_bytes(JavaThread::jni_environment_offset())));
2186 __ movptr(Address(rsp, 0), rdx);
2187 }
2188
2189 // Now set thread in native
2190 __ movl(Address(thread, JavaThread::thread_state_offset()), _thread_in_native);
2191
2192 __ call(RuntimeAddress(native_func));
2193
2194 // Verify or restore cpu control state after JNI call
2195 __ restore_cpu_control_state_after_jni();
2196
2197 // WARNING - on Windows Java Natives use pascal calling convention and pop the
2198 // arguments off of the stack. We could just re-adjust the stack pointer here
2199 // and continue to do SP relative addressing but we instead switch to FP
2200 // relative addressing.
2201
2202 // Unpack native results.
2203 switch (ret_type) {
2204 case T_BOOLEAN: __ c2bool(rax); break;
2205 case T_CHAR : __ andptr(rax, 0xFFFF); break;
2206 case T_BYTE : __ sign_extend_byte (rax); break;
2207 case T_SHORT : __ sign_extend_short(rax); break;
2208 case T_INT : /* nothing to do */ break;
2209 case T_DOUBLE :
2210 case T_FLOAT :
2211 // Result is in st0 we'll save as needed
2212 break;
2213 case T_ARRAY: // Really a handle
2214 case T_OBJECT: // Really a handle
2215 break; // can't de-handlize until after safepoint check
2216 case T_VOID: break;
2217 case T_LONG: break;
2218 default : ShouldNotReachHere();
2219 }
2220
2221 // unpin pinned arguments
2222 pinned_slot = oop_handle_offset;
2223 if (pinned_args.length() > 0) {
2224 // save return value that may be overwritten otherwise.
2225 save_native_result(masm, ret_type, stack_slots);
2226 for (int index = 0; index < pinned_args.length(); index ++) {
2227 int i = pinned_args.at(index);
2228 assert(pinned_slot <= stack_slots, "overflow");
2229 if (!in_regs[i].first()->is_stack()) {
2230 int offset = pinned_slot * VMRegImpl::stack_slot_size;
2231 __ movl(in_regs[i].first()->as_Register(), Address(rsp, offset));
2232 pinned_slot += VMRegImpl::slots_per_word;
2233 }
2234 // gen_pin_object handles save and restore
2235 // of any other clobbered registers
2236 gen_unpin_object(masm, thread, in_regs[i]);
2237 }
2238 restore_native_result(masm, ret_type, stack_slots);
2239 }
2240
2241 // Switch thread to "native transition" state before reading the synchronization state.
2242 // This additional state is necessary because reading and testing the synchronization
2243 // state is not atomic w.r.t. GC, as this scenario demonstrates:
2244 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2245 // VM thread changes sync state to synchronizing and suspends threads for GC.
2246 // Thread A is resumed to finish this native method, but doesn't block here since it
2247 // didn't see any synchronization is progress, and escapes.
2248 __ movl(Address(thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
2249
2250 if(os::is_MP()) {
2251 if (UseMembar) {
2252 // Force this write out before the read below
2253 __ membar(Assembler::Membar_mask_bits(
2254 Assembler::LoadLoad | Assembler::LoadStore |
2255 Assembler::StoreLoad | Assembler::StoreStore));
2256 } else {
2257 // Write serialization page so VM thread can do a pseudo remote membar.
2258 // We use the current thread pointer to calculate a thread specific
2259 // offset to write to within the page. This minimizes bus traffic
2260 // due to cache line collision.
2261 __ serialize_memory(thread, rcx);
2262 }
2263 }
2264
2265 if (AlwaysRestoreFPU) {
2266 // Make sure the control word is correct.
2267 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
2268 }
2269
2270 Label after_transition;
2271
2272 // check for safepoint operation in progress and/or pending suspend requests
2273 { Label Continue;
2274
2275 __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()),
2276 SafepointSynchronize::_not_synchronized);
2277
2278 Label L;
2279 __ jcc(Assembler::notEqual, L);
2280 __ cmpl(Address(thread, JavaThread::suspend_flags_offset()), 0);
2281 __ jcc(Assembler::equal, Continue);
2282 __ bind(L);
2283
2284 // Don't use call_VM as it will see a possible pending exception and forward it
2285 // and never return here preventing us from clearing _last_native_pc down below.
2286 // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
2287 // preserved and correspond to the bcp/locals pointers. So we do a runtime call
2288 // by hand.
2289 //
2290 save_native_result(masm, ret_type, stack_slots);
2291 __ push(thread);
2292 if (!is_critical_native) {
2293 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address,
2294 JavaThread::check_special_condition_for_native_trans)));
2295 } else {
2296 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address,
2297 JavaThread::check_special_condition_for_native_trans_and_transition)));
2298 }
2299 __ increment(rsp, wordSize);
2300 // Restore any method result value
2301 restore_native_result(masm, ret_type, stack_slots);
2302
2303 if (is_critical_native) {
2304 // The call above performed the transition to thread_in_Java so
2305 // skip the transition logic below.
2306 __ jmpb(after_transition);
2307 }
2308
2309 __ bind(Continue);
2310 }
2311
2312 // change thread state
2313 __ movl(Address(thread, JavaThread::thread_state_offset()), _thread_in_Java);
2314 __ bind(after_transition);
2315
2316 Label reguard;
2317 Label reguard_done;
2318 __ cmpl(Address(thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled);
2319 __ jcc(Assembler::equal, reguard);
2320
2321 // slow path reguard re-enters here
2322 __ bind(reguard_done);
2323
2324 // Handle possible exception (will unlock if necessary)
2325
2326 // native result if any is live
2327
2328 // Unlock
2329 Label slow_path_unlock;
2330 Label unlock_done;
2331 if (method->is_synchronized()) {
2332
2333 Label done;
2334
2335 // Get locked oop from the handle we passed to jni
2336 __ movptr(obj_reg, Address(oop_handle_reg, 0));
2337
2338 if (UseBiasedLocking) {
2339 __ biased_locking_exit(obj_reg, rbx, done);
2340 }
2341
2342 // Simple recursive lock?
2343
2344 __ cmpptr(Address(rbp, lock_slot_rbp_offset), (int32_t)NULL_WORD);
2345 __ jcc(Assembler::equal, done);
2346
2347 // Must save rax, if if it is live now because cmpxchg must use it
2348 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2349 save_native_result(masm, ret_type, stack_slots);
2350 }
2351
2352 // get old displaced header
2353 __ movptr(rbx, Address(rbp, lock_slot_rbp_offset));
2354
2355 // get address of the stack lock
2356 __ lea(rax, Address(rbp, lock_slot_rbp_offset));
2357
2358 // Atomic swap old header if oop still contains the stack lock
2359 if (os::is_MP()) {
2360 __ lock();
2361 }
2362
2363 // src -> dest iff dest == rax, else rax, <- dest
2364 // *obj_reg = rbx, iff *obj_reg == rax, else rax, = *(obj_reg)
2365 __ cmpxchgptr(rbx, Address(obj_reg, 0));
2366 __ jcc(Assembler::notEqual, slow_path_unlock);
2367
2368 // slow path re-enters here
2369 __ bind(unlock_done);
2370 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2371 restore_native_result(masm, ret_type, stack_slots);
2372 }
2373
2374 __ bind(done);
2375
2376 }
2377
2378 {
2379 SkipIfEqual skip_if(masm, &DTraceMethodProbes, 0);
2380 // Tell dtrace about this method exit
2381 save_native_result(masm, ret_type, stack_slots);
2382 __ mov_metadata(rax, method());
2383 __ call_VM_leaf(
2384 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
2385 thread, rax);
2386 restore_native_result(masm, ret_type, stack_slots);
2387 }
2388
2389 // We can finally stop using that last_Java_frame we setup ages ago
2390
2391 __ reset_last_Java_frame(thread, false);
2392
2393 // Unbox oop result, e.g. JNIHandles::resolve value.
2394 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
2395 __ resolve_jobject(rax /* value */,
2396 thread /* thread */,
2397 rcx /* tmp */);
2398 }
2399
2400 if (!is_critical_native) {
2401 // reset handle block
2402 __ movptr(rcx, Address(thread, JavaThread::active_handles_offset()));
2403 __ movl(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), NULL_WORD);
2404
2405 // Any exception pending?
2406 __ cmpptr(Address(thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2407 __ jcc(Assembler::notEqual, exception_pending);
2408 }
2409
2410 // no exception, we're almost done
2411
2412 // check that only result value is on FPU stack
2413 __ verify_FPU(ret_type == T_FLOAT || ret_type == T_DOUBLE ? 1 : 0, "native_wrapper normal exit");
2414
2415 // Fixup floating pointer results so that result looks like a return from a compiled method
2416 if (ret_type == T_FLOAT) {
2417 if (UseSSE >= 1) {
2418 // Pop st0 and store as float and reload into xmm register
2419 __ fstp_s(Address(rbp, -4));
2420 __ movflt(xmm0, Address(rbp, -4));
2421 }
2422 } else if (ret_type == T_DOUBLE) {
2423 if (UseSSE >= 2) {
2424 // Pop st0 and store as double and reload into xmm register
2425 __ fstp_d(Address(rbp, -8));
2426 __ movdbl(xmm0, Address(rbp, -8));
2427 }
2428 }
2429
2430 // Return
2431
2432 __ leave();
2433 __ ret(0);
2434
2435 // Unexpected paths are out of line and go here
2436
2437 // Slow path locking & unlocking
2438 if (method->is_synchronized()) {
2439
2440 // BEGIN Slow path lock
2441
2442 __ bind(slow_path_lock);
2443
2444 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM
2445 // args are (oop obj, BasicLock* lock, JavaThread* thread)
2446 __ push(thread);
2447 __ push(lock_reg);
2448 __ push(obj_reg);
2449 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C)));
2450 __ addptr(rsp, 3*wordSize);
2451
2452 #ifdef ASSERT
2453 { Label L;
2454 __ cmpptr(Address(thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
2455 __ jcc(Assembler::equal, L);
2456 __ stop("no pending exception allowed on exit from monitorenter");
2457 __ bind(L);
2458 }
2459 #endif
2460 __ jmp(lock_done);
2461
2462 // END Slow path lock
2463
2464 // BEGIN Slow path unlock
2465 __ bind(slow_path_unlock);
2466
2467 // Slow path unlock
2468
2469 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2470 save_native_result(masm, ret_type, stack_slots);
2471 }
2472 // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
2473
2474 __ pushptr(Address(thread, in_bytes(Thread::pending_exception_offset())));
2475 __ movptr(Address(thread, in_bytes(Thread::pending_exception_offset())), NULL_WORD);
2476
2477
2478 // should be a peal
2479 // +wordSize because of the push above
2480 __ lea(rax, Address(rbp, lock_slot_rbp_offset));
2481 __ push(rax);
2482
2483 __ push(obj_reg);
2484 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
2485 __ addptr(rsp, 2*wordSize);
2486 #ifdef ASSERT
2487 {
2488 Label L;
2489 __ cmpptr(Address(thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2490 __ jcc(Assembler::equal, L);
2491 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
2492 __ bind(L);
2493 }
2494 #endif /* ASSERT */
2495
2496 __ popptr(Address(thread, in_bytes(Thread::pending_exception_offset())));
2497
2498 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2499 restore_native_result(masm, ret_type, stack_slots);
2500 }
2501 __ jmp(unlock_done);
2502 // END Slow path unlock
2503
2504 }
2505
2506 // SLOW PATH Reguard the stack if needed
2507
2508 __ bind(reguard);
2509 save_native_result(masm, ret_type, stack_slots);
2510 {
2511 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
2512 }
2513 restore_native_result(masm, ret_type, stack_slots);
2514 __ jmp(reguard_done);
2515
2516
2517 // BEGIN EXCEPTION PROCESSING
2518
2519 if (!is_critical_native) {
2520 // Forward the exception
2521 __ bind(exception_pending);
2522
2523 // remove possible return value from FPU register stack
2524 __ empty_FPU_stack();
2525
2526 // pop our frame
2527 __ leave();
2528 // and forward the exception
2529 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2530 }
2531
2532 __ flush();
2533
2534 nmethod *nm = nmethod::new_native_nmethod(method,
2535 compile_id,
2536 masm->code(),
2537 vep_offset,
2538 frame_complete,
2539 stack_slots / VMRegImpl::slots_per_word,
2540 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
2541 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size),
2542 oop_maps);
2543
2544 if (is_critical_native) {
2545 nm->set_lazy_critical_native(true);
2546 }
2547
2548 return nm;
2549
2550 }
2551
2552 #ifdef HAVE_DTRACE_H
2553 // ---------------------------------------------------------------------------
2554 // Generate a dtrace nmethod for a given signature. The method takes arguments
2555 // in the Java compiled code convention, marshals them to the native
2556 // abi and then leaves nops at the position you would expect to call a native
2557 // function. When the probe is enabled the nops are replaced with a trap
2558 // instruction that dtrace inserts and the trace will cause a notification
2559 // to dtrace.
2560 //
2561 // The probes are only able to take primitive types and java/lang/String as
2562 // arguments. No other java types are allowed. Strings are converted to utf8
2563 // strings so that from dtrace point of view java strings are converted to C
2564 // strings. There is an arbitrary fixed limit on the total space that a method
2565 // can use for converting the strings. (256 chars per string in the signature).
2566 // So any java string larger then this is truncated.
2567
2568 nmethod *SharedRuntime::generate_dtrace_nmethod(
2569 MacroAssembler *masm, methodHandle method) {
2570
2571 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
2572 // be single threaded in this method.
2573 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
2574
2575 // Fill in the signature array, for the calling-convention call.
2576 int total_args_passed = method->size_of_parameters();
2577
2578 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
2579 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
2580
2581 // The signature we are going to use for the trap that dtrace will see
2582 // java/lang/String is converted. We drop "this" and any other object
2583 // is converted to NULL. (A one-slot java/lang/Long object reference
2584 // is converted to a two-slot long, which is why we double the allocation).
2585 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
2586 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
2587
2588 int i=0;
2589 int total_strings = 0;
2590 int first_arg_to_pass = 0;
2591 int total_c_args = 0;
2592
2593 if( !method->is_static() ) { // Pass in receiver first
2594 in_sig_bt[i++] = T_OBJECT;
2595 first_arg_to_pass = 1;
2596 }
2597
2598 // We need to convert the java args to where a native (non-jni) function
2599 // would expect them. To figure out where they go we convert the java
2600 // signature to a C signature.
2601
2602 SignatureStream ss(method->signature());
2603 for ( ; !ss.at_return_type(); ss.next()) {
2604 BasicType bt = ss.type();
2605 in_sig_bt[i++] = bt; // Collect remaining bits of signature
2606 out_sig_bt[total_c_args++] = bt;
2607 if( bt == T_OBJECT) {
2608 Symbol* s = ss.as_symbol_or_null(); // symbol is created
2609 if (s == vmSymbols::java_lang_String()) {
2610 total_strings++;
2611 out_sig_bt[total_c_args-1] = T_ADDRESS;
2612 } else if (s == vmSymbols::java_lang_Boolean() ||
2613 s == vmSymbols::java_lang_Character() ||
2614 s == vmSymbols::java_lang_Byte() ||
2615 s == vmSymbols::java_lang_Short() ||
2616 s == vmSymbols::java_lang_Integer() ||
2617 s == vmSymbols::java_lang_Float()) {
2618 out_sig_bt[total_c_args-1] = T_INT;
2619 } else if (s == vmSymbols::java_lang_Long() ||
2620 s == vmSymbols::java_lang_Double()) {
2621 out_sig_bt[total_c_args-1] = T_LONG;
2622 out_sig_bt[total_c_args++] = T_VOID;
2623 }
2624 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
2625 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
2626 out_sig_bt[total_c_args++] = T_VOID;
2627 }
2628 }
2629
2630 assert(i==total_args_passed, "validly parsed signature");
2631
2632 // Now get the compiled-Java layout as input arguments
2633 int comp_args_on_stack;
2634 comp_args_on_stack = SharedRuntime::java_calling_convention(
2635 in_sig_bt, in_regs, total_args_passed, false);
2636
2637 // Now figure out where the args must be stored and how much stack space
2638 // they require (neglecting out_preserve_stack_slots).
2639
2640 int out_arg_slots;
2641 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args);
2642
2643 // Calculate the total number of stack slots we will need.
2644
2645 // First count the abi requirement plus all of the outgoing args
2646 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2647
2648 // Now space for the string(s) we must convert
2649
2650 int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1);
2651 for (i = 0; i < total_strings ; i++) {
2652 string_locs[i] = stack_slots;
2653 stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size;
2654 }
2655
2656 // + 2 for return address (which we own) and saved rbp,
2657
2658 stack_slots += 2;
2659
2660 // Ok The space we have allocated will look like:
2661 //
2662 //
2663 // FP-> | |
2664 // |---------------------|
2665 // | string[n] |
2666 // |---------------------| <- string_locs[n]
2667 // | string[n-1] |
2668 // |---------------------| <- string_locs[n-1]
2669 // | ... |
2670 // | ... |
2671 // |---------------------| <- string_locs[1]
2672 // | string[0] |
2673 // |---------------------| <- string_locs[0]
2674 // | outbound memory |
2675 // | based arguments |
2676 // | |
2677 // |---------------------|
2678 // | |
2679 // SP-> | out_preserved_slots |
2680 //
2681 //
2682
2683 // Now compute actual number of stack words we need rounding to make
2684 // stack properly aligned.
2685 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
2686
2687 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2688
2689 intptr_t start = (intptr_t)__ pc();
2690
2691 // First thing make an ic check to see if we should even be here
2692
2693 // We are free to use all registers as temps without saving them and
2694 // restoring them except rbp. rbp, is the only callee save register
2695 // as far as the interpreter and the compiler(s) are concerned.
2696
2697 const Register ic_reg = rax;
2698 const Register receiver = rcx;
2699 Label hit;
2700 Label exception_pending;
2701
2702
2703 __ verify_oop(receiver);
2704 __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
2705 __ jcc(Assembler::equal, hit);
2706
2707 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
2708
2709 // verified entry must be aligned for code patching.
2710 // and the first 5 bytes must be in the same cache line
2711 // if we align at 8 then we will be sure 5 bytes are in the same line
2712 __ align(8);
2713
2714 __ bind(hit);
2715
2716 int vep_offset = ((intptr_t)__ pc()) - start;
2717
2718
2719 // The instruction at the verified entry point must be 5 bytes or longer
2720 // because it can be patched on the fly by make_non_entrant. The stack bang
2721 // instruction fits that requirement.
2722
2723 // Generate stack overflow check
2724
2725
2726 if (UseStackBanging) {
2727 if (stack_size <= StackShadowPages*os::vm_page_size()) {
2728 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
2729 } else {
2730 __ movl(rax, stack_size);
2731 __ bang_stack_size(rax, rbx);
2732 }
2733 } else {
2734 // need a 5 byte instruction to allow MT safe patching to non-entrant
2735 __ fat_nop();
2736 }
2737
2738 assert(((int)__ pc() - start - vep_offset) >= 5,
2739 "valid size for make_non_entrant");
2740
2741 // Generate a new frame for the wrapper.
2742 __ enter();
2743
2744 // -2 because return address is already present and so is saved rbp,
2745 if (stack_size - 2*wordSize != 0) {
2746 __ subl(rsp, stack_size - 2*wordSize);
2747 }
2748
2749 // Frame is now completed as far a size and linkage.
2750
2751 int frame_complete = ((intptr_t)__ pc()) - start;
2752
2753 // First thing we do store all the args as if we are doing the call.
2754 // Since the C calling convention is stack based that ensures that
2755 // all the Java register args are stored before we need to convert any
2756 // string we might have.
2757
2758 int sid = 0;
2759 int c_arg, j_arg;
2760 int string_reg = 0;
2761
2762 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2763 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2764
2765 VMRegPair src = in_regs[j_arg];
2766 VMRegPair dst = out_regs[c_arg];
2767 assert(dst.first()->is_stack() || in_sig_bt[j_arg] == T_VOID,
2768 "stack based abi assumed");
2769
2770 switch (in_sig_bt[j_arg]) {
2771
2772 case T_ARRAY:
2773 case T_OBJECT:
2774 if (out_sig_bt[c_arg] == T_ADDRESS) {
2775 // Any register based arg for a java string after the first
2776 // will be destroyed by the call to get_utf so we store
2777 // the original value in the location the utf string address
2778 // will eventually be stored.
2779 if (src.first()->is_reg()) {
2780 if (string_reg++ != 0) {
2781 simple_move32(masm, src, dst);
2782 }
2783 }
2784 } else if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2785 // need to unbox a one-word value
2786 Register in_reg = rax;
2787 if ( src.first()->is_reg() ) {
2788 in_reg = src.first()->as_Register();
2789 } else {
2790 simple_move32(masm, src, in_reg->as_VMReg());
2791 }
2792 Label skipUnbox;
2793 __ movl(Address(rsp, reg2offset_out(dst.first())), NULL_WORD);
2794 if ( out_sig_bt[c_arg] == T_LONG ) {
2795 __ movl(Address(rsp, reg2offset_out(dst.second())), NULL_WORD);
2796 }
2797 __ testl(in_reg, in_reg);
2798 __ jcc(Assembler::zero, skipUnbox);
2799 assert(dst.first()->is_stack() &&
2800 (!dst.second()->is_valid() || dst.second()->is_stack()),
2801 "value(s) must go into stack slots");
2802
2803 BasicType bt = out_sig_bt[c_arg];
2804 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2805 if ( bt == T_LONG ) {
2806 __ movl(rbx, Address(in_reg,
2807 box_offset + VMRegImpl::stack_slot_size));
2808 __ movl(Address(rsp, reg2offset_out(dst.second())), rbx);
2809 }
2810 __ movl(in_reg, Address(in_reg, box_offset));
2811 __ movl(Address(rsp, reg2offset_out(dst.first())), in_reg);
2812 __ bind(skipUnbox);
2813 } else {
2814 // Convert the arg to NULL
2815 __ movl(Address(rsp, reg2offset_out(dst.first())), NULL_WORD);
2816 }
2817 if (out_sig_bt[c_arg] == T_LONG) {
2818 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2819 ++c_arg; // Move over the T_VOID To keep the loop indices in sync
2820 }
2821 break;
2822
2823 case T_VOID:
2824 break;
2825
2826 case T_FLOAT:
2827 float_move(masm, src, dst);
2828 break;
2829
2830 case T_DOUBLE:
2831 assert( j_arg + 1 < total_args_passed &&
2832 in_sig_bt[j_arg + 1] == T_VOID, "bad arg list");
2833 double_move(masm, src, dst);
2834 break;
2835
2836 case T_LONG :
2837 long_move(masm, src, dst);
2838 break;
2839
2840 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2841
2842 default:
2843 simple_move32(masm, src, dst);
2844 }
2845 }
2846
2847 // Now we must convert any string we have to utf8
2848 //
2849
2850 for (sid = 0, j_arg = first_arg_to_pass, c_arg = 0 ;
2851 sid < total_strings ; j_arg++, c_arg++ ) {
2852
2853 if (out_sig_bt[c_arg] == T_ADDRESS) {
2854
2855 Address utf8_addr = Address(
2856 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
2857 __ leal(rax, utf8_addr);
2858
2859 // The first string we find might still be in the original java arg
2860 // register
2861 VMReg orig_loc = in_regs[j_arg].first();
2862 Register string_oop;
2863
2864 // This is where the argument will eventually reside
2865 Address dest = Address(rsp, reg2offset_out(out_regs[c_arg].first()));
2866
2867 if (sid == 1 && orig_loc->is_reg()) {
2868 string_oop = orig_loc->as_Register();
2869 assert(string_oop != rax, "smashed arg");
2870 } else {
2871
2872 if (orig_loc->is_reg()) {
2873 // Get the copy of the jls object
2874 __ movl(rcx, dest);
2875 } else {
2876 // arg is still in the original location
2877 __ movl(rcx, Address(rbp, reg2offset_in(orig_loc)));
2878 }
2879 string_oop = rcx;
2880
2881 }
2882 Label nullString;
2883 __ movl(dest, NULL_WORD);
2884 __ testl(string_oop, string_oop);
2885 __ jcc(Assembler::zero, nullString);
2886
2887 // Now we can store the address of the utf string as the argument
2888 __ movl(dest, rax);
2889
2890 // And do the conversion
2891 __ call_VM_leaf(CAST_FROM_FN_PTR(
2892 address, SharedRuntime::get_utf), string_oop, rax);
2893 __ bind(nullString);
2894 }
2895
2896 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
2897 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2898 ++c_arg; // Move over the T_VOID To keep the loop indices in sync
2899 }
2900 }
2901
2902
2903 // Ok now we are done. Need to place the nop that dtrace wants in order to
2904 // patch in the trap
2905
2906 int patch_offset = ((intptr_t)__ pc()) - start;
2907
2908 __ nop();
2909
2910
2911 // Return
2912
2913 __ leave();
2914 __ ret(0);
2915
2916 __ flush();
2917
2918 nmethod *nm = nmethod::new_dtrace_nmethod(
2919 method, masm->code(), vep_offset, patch_offset, frame_complete,
2920 stack_slots / VMRegImpl::slots_per_word);
2921 return nm;
2922
2923 }
2924
2925 #endif // HAVE_DTRACE_H
2926
2927 // this function returns the adjust size (in number of words) to a c2i adapter
2928 // activation for use during deoptimization
2929 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) {
2930 return (callee_locals - callee_parameters) * Interpreter::stackElementWords;
2931 }
2932
2933
2934 uint SharedRuntime::out_preserve_stack_slots() {
2935 return 0;
2936 }
2937
2938 //------------------------------generate_deopt_blob----------------------------
2939 void SharedRuntime::generate_deopt_blob() {
2940 // allocate space for the code
2941 ResourceMark rm;
2942 // setup code generation tools
2943 CodeBuffer buffer("deopt_blob", 1024, 1024);
2944 MacroAssembler* masm = new MacroAssembler(&buffer);
2945 int frame_size_in_words;
2946 OopMap* map = NULL;
2947 // Account for the extra args we place on the stack
2948 // by the time we call fetch_unroll_info
2949 const int additional_words = 2; // deopt kind, thread
2950
2951 OopMapSet *oop_maps = new OopMapSet();
2952
2953 // -------------
2954 // This code enters when returning to a de-optimized nmethod. A return
2955 // address has been pushed on the the stack, and return values are in
2956 // registers.
2957 // If we are doing a normal deopt then we were called from the patched
2958 // nmethod from the point we returned to the nmethod. So the return
2959 // address on the stack is wrong by NativeCall::instruction_size
2960 // We will adjust the value to it looks like we have the original return
2961 // address on the stack (like when we eagerly deoptimized).
2962 // In the case of an exception pending with deoptimized then we enter
2963 // with a return address on the stack that points after the call we patched
2964 // into the exception handler. We have the following register state:
2965 // rax,: exception
2966 // rbx,: exception handler
2967 // rdx: throwing pc
2968 // So in this case we simply jam rdx into the useless return address and
2969 // the stack looks just like we want.
2970 //
2971 // At this point we need to de-opt. We save the argument return
2972 // registers. We call the first C routine, fetch_unroll_info(). This
2973 // routine captures the return values and returns a structure which
2974 // describes the current frame size and the sizes of all replacement frames.
2975 // The current frame is compiled code and may contain many inlined
2976 // functions, each with their own JVM state. We pop the current frame, then
2977 // push all the new frames. Then we call the C routine unpack_frames() to
2978 // populate these frames. Finally unpack_frames() returns us the new target
2979 // address. Notice that callee-save registers are BLOWN here; they have
2980 // already been captured in the vframeArray at the time the return PC was
2981 // patched.
2982 address start = __ pc();
2983 Label cont;
2984
2985 // Prolog for non exception case!
2986
2987 // Save everything in sight.
2988
2989 map = RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, false);
2990 // Normal deoptimization
2991 __ push(Deoptimization::Unpack_deopt);
2992 __ jmp(cont);
2993
2994 int reexecute_offset = __ pc() - start;
2995
2996 // Reexecute case
2997 // return address is the pc describes what bci to do re-execute at
2998
2999 // No need to update map as each call to save_live_registers will produce identical oopmap
3000 (void) RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, false);
3001
3002 __ push(Deoptimization::Unpack_reexecute);
3003 __ jmp(cont);
3004
3005 int exception_offset = __ pc() - start;
3006
3007 // Prolog for exception case
3008
3009 // all registers are dead at this entry point, except for rax, and
3010 // rdx which contain the exception oop and exception pc
3011 // respectively. Set them in TLS and fall thru to the
3012 // unpack_with_exception_in_tls entry point.
3013
3014 __ get_thread(rdi);
3015 __ movptr(Address(rdi, JavaThread::exception_pc_offset()), rdx);
3016 __ movptr(Address(rdi, JavaThread::exception_oop_offset()), rax);
3017
3018 int exception_in_tls_offset = __ pc() - start;
3019
3020 // new implementation because exception oop is now passed in JavaThread
3021
3022 // Prolog for exception case
3023 // All registers must be preserved because they might be used by LinearScan
3024 // Exceptiop oop and throwing PC are passed in JavaThread
3025 // tos: stack at point of call to method that threw the exception (i.e. only
3026 // args are on the stack, no return address)
3027
3028 // make room on stack for the return address
3029 // It will be patched later with the throwing pc. The correct value is not
3030 // available now because loading it from memory would destroy registers.
3031 __ push(0);
3032
3033 // Save everything in sight.
3034
3035 // No need to update map as each call to save_live_registers will produce identical oopmap
3036 (void) RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, false);
3037
3038 // Now it is safe to overwrite any register
3039
3040 // store the correct deoptimization type
3041 __ push(Deoptimization::Unpack_exception);
3042
3043 // load throwing pc from JavaThread and patch it as the return address
3044 // of the current frame. Then clear the field in JavaThread
3045 __ get_thread(rdi);
3046 __ movptr(rdx, Address(rdi, JavaThread::exception_pc_offset()));
3047 __ movptr(Address(rbp, wordSize), rdx);
3048 __ movptr(Address(rdi, JavaThread::exception_pc_offset()), NULL_WORD);
3049
3050 #ifdef ASSERT
3051 // verify that there is really an exception oop in JavaThread
3052 __ movptr(rax, Address(rdi, JavaThread::exception_oop_offset()));
3053 __ verify_oop(rax);
3054
3055 // verify that there is no pending exception
3056 Label no_pending_exception;
3057 __ movptr(rax, Address(rdi, Thread::pending_exception_offset()));
3058 __ testptr(rax, rax);
3059 __ jcc(Assembler::zero, no_pending_exception);
3060 __ stop("must not have pending exception here");
3061 __ bind(no_pending_exception);
3062 #endif
3063
3064 __ bind(cont);
3065
3066 // Compiled code leaves the floating point stack dirty, empty it.
3067 __ empty_FPU_stack();
3068
3069
3070 // Call C code. Need thread and this frame, but NOT official VM entry
3071 // crud. We cannot block on this call, no GC can happen.
3072 __ get_thread(rcx);
3073 __ push(rcx);
3074 // fetch_unroll_info needs to call last_java_frame()
3075 __ set_last_Java_frame(rcx, noreg, noreg, NULL);
3076
3077 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info)));
3078
3079 // Need to have an oopmap that tells fetch_unroll_info where to
3080 // find any register it might need.
3081
3082 oop_maps->add_gc_map( __ pc()-start, map);
3083
3084 // Discard arg to fetch_unroll_info
3085 __ pop(rcx);
3086
3087 __ get_thread(rcx);
3088 __ reset_last_Java_frame(rcx, false);
3089
3090 // Load UnrollBlock into EDI
3091 __ mov(rdi, rax);
3092
3093 // Move the unpack kind to a safe place in the UnrollBlock because
3094 // we are very short of registers
3095
3096 Address unpack_kind(rdi, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes());
3097 // retrieve the deopt kind from where we left it.
3098 __ pop(rax);
3099 __ movl(unpack_kind, rax); // save the unpack_kind value
3100
3101 Label noException;
3102 __ cmpl(rax, Deoptimization::Unpack_exception); // Was exception pending?
3103 __ jcc(Assembler::notEqual, noException);
3104 __ movptr(rax, Address(rcx, JavaThread::exception_oop_offset()));
3105 __ movptr(rdx, Address(rcx, JavaThread::exception_pc_offset()));
3106 __ movptr(Address(rcx, JavaThread::exception_oop_offset()), NULL_WORD);
3107 __ movptr(Address(rcx, JavaThread::exception_pc_offset()), NULL_WORD);
3108
3109 __ verify_oop(rax);
3110
3111 // Overwrite the result registers with the exception results.
3112 __ movptr(Address(rsp, RegisterSaver::raxOffset()*wordSize), rax);
3113 __ movptr(Address(rsp, RegisterSaver::rdxOffset()*wordSize), rdx);
3114
3115 __ bind(noException);
3116
3117 // Stack is back to only having register save data on the stack.
3118 // Now restore the result registers. Everything else is either dead or captured
3119 // in the vframeArray.
3120
3121 RegisterSaver::restore_result_registers(masm);
3122
3123 // Non standard control word may be leaked out through a safepoint blob, and we can
3124 // deopt at a poll point with the non standard control word. However, we should make
3125 // sure the control word is correct after restore_result_registers.
3126 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
3127
3128 // All of the register save area has been popped of the stack. Only the
3129 // return address remains.
3130
3131 // Pop all the frames we must move/replace.
3132 //
3133 // Frame picture (youngest to oldest)
3134 // 1: self-frame (no frame link)
3135 // 2: deopting frame (no frame link)
3136 // 3: caller of deopting frame (could be compiled/interpreted).
3137 //
3138 // Note: by leaving the return address of self-frame on the stack
3139 // and using the size of frame 2 to adjust the stack
3140 // when we are done the return to frame 3 will still be on the stack.
3141
3142 // Pop deoptimized frame
3143 __ addptr(rsp, Address(rdi,Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
3144
3145 // sp should be pointing at the return address to the caller (3)
3146
3147 // Pick up the initial fp we should save
3148 // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved)
3149 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3150
3151 #ifdef ASSERT
3152 // Compilers generate code that bang the stack by as much as the
3153 // interpreter would need. So this stack banging should never
3154 // trigger a fault. Verify that it does not on non product builds.
3155 if (UseStackBanging) {
3156 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3157 __ bang_stack_size(rbx, rcx);
3158 }
3159 #endif
3160
3161 // Load array of frame pcs into ECX
3162 __ movptr(rcx,Address(rdi,Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3163
3164 __ pop(rsi); // trash the old pc
3165
3166 // Load array of frame sizes into ESI
3167 __ movptr(rsi,Address(rdi,Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
3168
3169 Address counter(rdi, Deoptimization::UnrollBlock::counter_temp_offset_in_bytes());
3170
3171 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
3172 __ movl(counter, rbx);
3173
3174 // Now adjust the caller's stack to make up for the extra locals
3175 // but record the original sp so that we can save it in the skeletal interpreter
3176 // frame and the stack walking of interpreter_sender will get the unextended sp
3177 // value and not the "real" sp value.
3178
3179 Address sp_temp(rdi, Deoptimization::UnrollBlock::sender_sp_temp_offset_in_bytes());
3180 __ movptr(sp_temp, rsp);
3181 __ movl2ptr(rbx, Address(rdi, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()));
3182 __ subptr(rsp, rbx);
3183
3184 // Push interpreter frames in a loop
3185 Label loop;
3186 __ bind(loop);
3187 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3188 #ifdef CC_INTERP
3189 __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and
3190 #ifdef ASSERT
3191 __ push(0xDEADDEAD); // Make a recognizable pattern
3192 __ push(0xDEADDEAD);
3193 #else /* ASSERT */
3194 __ subptr(rsp, 2*wordSize); // skip the "static long no_param"
3195 #endif /* ASSERT */
3196 #else /* CC_INTERP */
3197 __ subptr(rbx, 2*wordSize); // we'll push pc and rbp, by hand
3198 #endif /* CC_INTERP */
3199 __ pushptr(Address(rcx, 0)); // save return address
3200 __ enter(); // save old & set new rbp,
3201 __ subptr(rsp, rbx); // Prolog!
3202 __ movptr(rbx, sp_temp); // sender's sp
3203 #ifdef CC_INTERP
3204 __ movptr(Address(rbp,
3205 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
3206 rbx); // Make it walkable
3207 #else /* CC_INTERP */
3208 // This value is corrected by layout_activation_impl
3209 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD);
3210 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), rbx); // Make it walkable
3211 #endif /* CC_INTERP */
3212 __ movptr(sp_temp, rsp); // pass to next frame
3213 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3214 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3215 __ decrementl(counter); // decrement counter
3216 __ jcc(Assembler::notZero, loop);
3217 __ pushptr(Address(rcx, 0)); // save final return address
3218
3219 // Re-push self-frame
3220 __ enter(); // save old & set new rbp,
3221
3222 // Return address and rbp, are in place
3223 // We'll push additional args later. Just allocate a full sized
3224 // register save area
3225 __ subptr(rsp, (frame_size_in_words-additional_words - 2) * wordSize);
3226
3227 // Restore frame locals after moving the frame
3228 __ movptr(Address(rsp, RegisterSaver::raxOffset()*wordSize), rax);
3229 __ movptr(Address(rsp, RegisterSaver::rdxOffset()*wordSize), rdx);
3230 __ fstp_d(Address(rsp, RegisterSaver::fpResultOffset()*wordSize)); // Pop float stack and store in local
3231 if( UseSSE>=2 ) __ movdbl(Address(rsp, RegisterSaver::xmm0Offset()*wordSize), xmm0);
3232 if( UseSSE==1 ) __ movflt(Address(rsp, RegisterSaver::xmm0Offset()*wordSize), xmm0);
3233
3234 // Set up the args to unpack_frame
3235
3236 __ pushl(unpack_kind); // get the unpack_kind value
3237 __ get_thread(rcx);
3238 __ push(rcx);
3239
3240 // set last_Java_sp, last_Java_fp
3241 __ set_last_Java_frame(rcx, noreg, rbp, NULL);
3242
3243 // Call C code. Need thread but NOT official VM entry
3244 // crud. We cannot block on this call, no GC can happen. Call should
3245 // restore return values to their stack-slots with the new SP.
3246 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3247 // Set an oopmap for the call site
3248 oop_maps->add_gc_map( __ pc()-start, new OopMap( frame_size_in_words, 0 ));
3249
3250 // rax, contains the return result type
3251 __ push(rax);
3252
3253 __ get_thread(rcx);
3254 __ reset_last_Java_frame(rcx, false);
3255
3256 // Collect return values
3257 __ movptr(rax,Address(rsp, (RegisterSaver::raxOffset() + additional_words + 1)*wordSize));
3258 __ movptr(rdx,Address(rsp, (RegisterSaver::rdxOffset() + additional_words + 1)*wordSize));
3259
3260 // Clear floating point stack before returning to interpreter
3261 __ empty_FPU_stack();
3262
3263 // Check if we should push the float or double return value.
3264 Label results_done, yes_double_value;
3265 __ cmpl(Address(rsp, 0), T_DOUBLE);
3266 __ jcc (Assembler::zero, yes_double_value);
3267 __ cmpl(Address(rsp, 0), T_FLOAT);
3268 __ jcc (Assembler::notZero, results_done);
3269
3270 // return float value as expected by interpreter
3271 if( UseSSE>=1 ) __ movflt(xmm0, Address(rsp, (RegisterSaver::xmm0Offset() + additional_words + 1)*wordSize));
3272 else __ fld_d(Address(rsp, (RegisterSaver::fpResultOffset() + additional_words + 1)*wordSize));
3273 __ jmp(results_done);
3274
3275 // return double value as expected by interpreter
3276 __ bind(yes_double_value);
3277 if( UseSSE>=2 ) __ movdbl(xmm0, Address(rsp, (RegisterSaver::xmm0Offset() + additional_words + 1)*wordSize));
3278 else __ fld_d(Address(rsp, (RegisterSaver::fpResultOffset() + additional_words + 1)*wordSize));
3279
3280 __ bind(results_done);
3281
3282 // Pop self-frame.
3283 __ leave(); // Epilog!
3284
3285 // Jump to interpreter
3286 __ ret(0);
3287
3288 // -------------
3289 // make sure all code is generated
3290 masm->flush();
3291
3292 _deopt_blob = DeoptimizationBlob::create( &buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words);
3293 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
3294 }
3295
3296
3297 #ifdef COMPILER2
3298 //------------------------------generate_uncommon_trap_blob--------------------
3299 void SharedRuntime::generate_uncommon_trap_blob() {
3300 // allocate space for the code
3301 ResourceMark rm;
3302 // setup code generation tools
3303 CodeBuffer buffer("uncommon_trap_blob", 512, 512);
3304 MacroAssembler* masm = new MacroAssembler(&buffer);
3305
3306 enum frame_layout {
3307 arg0_off, // thread sp + 0 // Arg location for
3308 arg1_off, // unloaded_class_index sp + 1 // calling C
3309 // The frame sender code expects that rbp will be in the "natural" place and
3310 // will override any oopMap setting for it. We must therefore force the layout
3311 // so that it agrees with the frame sender code.
3312 rbp_off, // callee saved register sp + 2
3313 return_off, // slot for return address sp + 3
3314 framesize
3315 };
3316
3317 address start = __ pc();
3318
3319 if (UseRTMLocking) {
3320 // Abort RTM transaction before possible nmethod deoptimization.
3321 __ xabort(0);
3322 }
3323
3324 // Push self-frame.
3325 __ subptr(rsp, return_off*wordSize); // Epilog!
3326
3327 // rbp, is an implicitly saved callee saved register (i.e. the calling
3328 // convention will save restore it in prolog/epilog) Other than that
3329 // there are no callee save registers no that adapter frames are gone.
3330 __ movptr(Address(rsp, rbp_off*wordSize), rbp);
3331
3332 // Clear the floating point exception stack
3333 __ empty_FPU_stack();
3334
3335 // set last_Java_sp
3336 __ get_thread(rdx);
3337 __ set_last_Java_frame(rdx, noreg, noreg, NULL);
3338
3339 // Call C code. Need thread but NOT official VM entry
3340 // crud. We cannot block on this call, no GC can happen. Call should
3341 // capture callee-saved registers as well as return values.
3342 __ movptr(Address(rsp, arg0_off*wordSize), rdx);
3343 // argument already in ECX
3344 __ movl(Address(rsp, arg1_off*wordSize),rcx);
3345 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
3346
3347 // Set an oopmap for the call site
3348 OopMapSet *oop_maps = new OopMapSet();
3349 OopMap* map = new OopMap( framesize, 0 );
3350 // No oopMap for rbp, it is known implicitly
3351
3352 oop_maps->add_gc_map( __ pc()-start, map);
3353
3354 __ get_thread(rcx);
3355
3356 __ reset_last_Java_frame(rcx, false);
3357
3358 // Load UnrollBlock into EDI
3359 __ movptr(rdi, rax);
3360
3361 // Pop all the frames we must move/replace.
3362 //
3363 // Frame picture (youngest to oldest)
3364 // 1: self-frame (no frame link)
3365 // 2: deopting frame (no frame link)
3366 // 3: caller of deopting frame (could be compiled/interpreted).
3367
3368 // Pop self-frame. We have no frame, and must rely only on EAX and ESP.
3369 __ addptr(rsp,(framesize-1)*wordSize); // Epilog!
3370
3371 // Pop deoptimized frame
3372 __ movl2ptr(rcx, Address(rdi,Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
3373 __ addptr(rsp, rcx);
3374
3375 // sp should be pointing at the return address to the caller (3)
3376
3377 // Pick up the initial fp we should save
3378 // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved)
3379 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3380
3381 #ifdef ASSERT
3382 // Compilers generate code that bang the stack by as much as the
3383 // interpreter would need. So this stack banging should never
3384 // trigger a fault. Verify that it does not on non product builds.
3385 if (UseStackBanging) {
3386 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3387 __ bang_stack_size(rbx, rcx);
3388 }
3389 #endif
3390
3391 // Load array of frame pcs into ECX
3392 __ movl(rcx,Address(rdi,Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3393
3394 __ pop(rsi); // trash the pc
3395
3396 // Load array of frame sizes into ESI
3397 __ movptr(rsi,Address(rdi,Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
3398
3399 Address counter(rdi, Deoptimization::UnrollBlock::counter_temp_offset_in_bytes());
3400
3401 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
3402 __ movl(counter, rbx);
3403
3404 // Now adjust the caller's stack to make up for the extra locals
3405 // but record the original sp so that we can save it in the skeletal interpreter
3406 // frame and the stack walking of interpreter_sender will get the unextended sp
3407 // value and not the "real" sp value.
3408
3409 Address sp_temp(rdi, Deoptimization::UnrollBlock::sender_sp_temp_offset_in_bytes());
3410 __ movptr(sp_temp, rsp);
3411 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()));
3412 __ subptr(rsp, rbx);
3413
3414 // Push interpreter frames in a loop
3415 Label loop;
3416 __ bind(loop);
3417 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3418 #ifdef CC_INTERP
3419 __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and
3420 #ifdef ASSERT
3421 __ push(0xDEADDEAD); // Make a recognizable pattern
3422 __ push(0xDEADDEAD); // (parm to RecursiveInterpreter...)
3423 #else /* ASSERT */
3424 __ subptr(rsp, 2*wordSize); // skip the "static long no_param"
3425 #endif /* ASSERT */
3426 #else /* CC_INTERP */
3427 __ subptr(rbx, 2*wordSize); // we'll push pc and rbp, by hand
3428 #endif /* CC_INTERP */
3429 __ pushptr(Address(rcx, 0)); // save return address
3430 __ enter(); // save old & set new rbp,
3431 __ subptr(rsp, rbx); // Prolog!
3432 __ movptr(rbx, sp_temp); // sender's sp
3433 #ifdef CC_INTERP
3434 __ movptr(Address(rbp,
3435 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
3436 rbx); // Make it walkable
3437 #else /* CC_INTERP */
3438 // This value is corrected by layout_activation_impl
3439 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), NULL_WORD );
3440 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), rbx); // Make it walkable
3441 #endif /* CC_INTERP */
3442 __ movptr(sp_temp, rsp); // pass to next frame
3443 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3444 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3445 __ decrementl(counter); // decrement counter
3446 __ jcc(Assembler::notZero, loop);
3447 __ pushptr(Address(rcx, 0)); // save final return address
3448
3449 // Re-push self-frame
3450 __ enter(); // save old & set new rbp,
3451 __ subptr(rsp, (framesize-2) * wordSize); // Prolog!
3452
3453
3454 // set last_Java_sp, last_Java_fp
3455 __ get_thread(rdi);
3456 __ set_last_Java_frame(rdi, noreg, rbp, NULL);
3457
3458 // Call C code. Need thread but NOT official VM entry
3459 // crud. We cannot block on this call, no GC can happen. Call should
3460 // restore return values to their stack-slots with the new SP.
3461 __ movptr(Address(rsp,arg0_off*wordSize),rdi);
3462 __ movl(Address(rsp,arg1_off*wordSize), Deoptimization::Unpack_uncommon_trap);
3463 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3464 // Set an oopmap for the call site
3465 oop_maps->add_gc_map( __ pc()-start, new OopMap( framesize, 0 ) );
3466
3467 __ get_thread(rdi);
3468 __ reset_last_Java_frame(rdi, true);
3469
3470 // Pop self-frame.
3471 __ leave(); // Epilog!
3472
3473 // Jump to interpreter
3474 __ ret(0);
3475
3476 // -------------
3477 // make sure all code is generated
3478 masm->flush();
3479
3480 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps, framesize);
3481 }
3482 #endif // COMPILER2
3483
3484 //------------------------------generate_handler_blob------
3485 //
3486 // Generate a special Compile2Runtime blob that saves all registers,
3487 // setup oopmap, and calls safepoint code to stop the compiled code for
3488 // a safepoint.
3489 //
3490 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) {
3491
3492 // Account for thread arg in our frame
3493 const int additional_words = 1;
3494 int frame_size_in_words;
3495
3496 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3497
3498 ResourceMark rm;
3499 OopMapSet *oop_maps = new OopMapSet();
3500 OopMap* map;
3501
3502 // allocate space for the code
3503 // setup code generation tools
3504 CodeBuffer buffer("handler_blob", 1024, 512);
3505 MacroAssembler* masm = new MacroAssembler(&buffer);
3506
3507 const Register java_thread = rdi; // callee-saved for VC++
3508 address start = __ pc();
3509 address call_pc = NULL;
3510 bool cause_return = (poll_type == POLL_AT_RETURN);
3511 bool save_vectors = (poll_type == POLL_AT_VECTOR_LOOP);
3512
3513 if (UseRTMLocking) {
3514 // Abort RTM transaction before calling runtime
3515 // because critical section will be large and will be
3516 // aborted anyway. Also nmethod could be deoptimized.
3517 __ xabort(0);
3518 }
3519
3520 // If cause_return is true we are at a poll_return and there is
3521 // the return address on the stack to the caller on the nmethod
3522 // that is safepoint. We can leave this return on the stack and
3523 // effectively complete the return and safepoint in the caller.
3524 // Otherwise we push space for a return address that the safepoint
3525 // handler will install later to make the stack walking sensible.
3526 if (!cause_return)
3527 __ push(rbx); // Make room for return address (or push it again)
3528
3529 map = RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, false, save_vectors);
3530
3531 // The following is basically a call_VM. However, we need the precise
3532 // address of the call in order to generate an oopmap. Hence, we do all the
3533 // work ourselves.
3534
3535 // Push thread argument and setup last_Java_sp
3536 __ get_thread(java_thread);
3537 __ push(java_thread);
3538 __ set_last_Java_frame(java_thread, noreg, noreg, NULL);
3539
3540 // if this was not a poll_return then we need to correct the return address now.
3541 if (!cause_return) {
3542 __ movptr(rax, Address(java_thread, JavaThread::saved_exception_pc_offset()));
3543 __ movptr(Address(rbp, wordSize), rax);
3544 }
3545
3546 // do the call
3547 __ call(RuntimeAddress(call_ptr));
3548
3549 // Set an oopmap for the call site. This oopmap will map all
3550 // oop-registers and debug-info registers as callee-saved. This
3551 // will allow deoptimization at this safepoint to find all possible
3552 // debug-info recordings, as well as let GC find all oops.
3553
3554 oop_maps->add_gc_map( __ pc() - start, map);
3555
3556 // Discard arg
3557 __ pop(rcx);
3558
3559 Label noException;
3560
3561 // Clear last_Java_sp again
3562 __ get_thread(java_thread);
3563 __ reset_last_Java_frame(java_thread, false);
3564
3565 __ cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3566 __ jcc(Assembler::equal, noException);
3567
3568 // Exception pending
3569 RegisterSaver::restore_live_registers(masm, save_vectors);
3570
3571 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3572
3573 __ bind(noException);
3574
3575 // Normal exit, register restoring and exit
3576 RegisterSaver::restore_live_registers(masm, save_vectors);
3577
3578 __ ret(0);
3579
3580 // make sure all code is generated
3581 masm->flush();
3582
3583 // Fill-out other meta info
3584 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words);
3585 }
3586
3587 //
3588 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3589 //
3590 // Generate a stub that calls into vm to find out the proper destination
3591 // of a java call. All the argument registers are live at this point
3592 // but since this is generic code we don't know what they are and the caller
3593 // must do any gc of the args.
3594 //
3595 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) {
3596 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3597
3598 // allocate space for the code
3599 ResourceMark rm;
3600
3601 CodeBuffer buffer(name, 1000, 512);
3602 MacroAssembler* masm = new MacroAssembler(&buffer);
3603
3604 int frame_size_words;
3605 enum frame_layout {
3606 thread_off,
3607 extra_words };
3608
3609 OopMapSet *oop_maps = new OopMapSet();
3610 OopMap* map = NULL;
3611
3612 int start = __ offset();
3613
3614 map = RegisterSaver::save_live_registers(masm, extra_words, &frame_size_words);
3615
3616 int frame_complete = __ offset();
3617
3618 const Register thread = rdi;
3619 __ get_thread(rdi);
3620
3621 __ push(thread);
3622 __ set_last_Java_frame(thread, noreg, rbp, NULL);
3623
3624 __ call(RuntimeAddress(destination));
3625
3626
3627 // Set an oopmap for the call site.
3628 // We need this not only for callee-saved registers, but also for volatile
3629 // registers that the compiler might be keeping live across a safepoint.
3630
3631 oop_maps->add_gc_map( __ offset() - start, map);
3632
3633 // rax, contains the address we are going to jump to assuming no exception got installed
3634
3635 __ addptr(rsp, wordSize);
3636
3637 // clear last_Java_sp
3638 __ reset_last_Java_frame(thread, true);
3639 // check for pending exceptions
3640 Label pending;
3641 __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3642 __ jcc(Assembler::notEqual, pending);
3643
3644 // get the returned Method*
3645 __ get_vm_result_2(rbx, thread);
3646 __ movptr(Address(rsp, RegisterSaver::rbx_offset() * wordSize), rbx);
3647
3648 __ movptr(Address(rsp, RegisterSaver::rax_offset() * wordSize), rax);
3649
3650 RegisterSaver::restore_live_registers(masm);
3651
3652 // We are back the the original state on entry and ready to go.
3653
3654 __ jmp(rax);
3655
3656 // Pending exception after the safepoint
3657
3658 __ bind(pending);
3659
3660 RegisterSaver::restore_live_registers(masm);
3661
3662 // exception pending => remove activation and forward to exception handler
3663
3664 __ get_thread(thread);
3665 __ movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
3666 __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
3667 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3668
3669 // -------------
3670 // make sure all code is generated
3671 masm->flush();
3672
3673 // return the blob
3674 // frame_size_words or bytes??
3675 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
3676 }