1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/addnode.hpp"
28 #include "opto/callnode.hpp"
29 #include "opto/connode.hpp"
30 #include "opto/idealGraphPrinter.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/memnode.hpp"
33 #include "opto/opcodes.hpp"
34 #include "opto/regmask.hpp"
35 #include "opto/rootnode.hpp"
36 #include "opto/runtime.hpp"
37 #include "opto/type.hpp"
38 #include "opto/vectornode.hpp"
39 #include "runtime/atomic.hpp"
40 #include "runtime/os.hpp"
41 #if defined AD_MD_HPP
42 # include AD_MD_HPP
43 #elif defined TARGET_ARCH_MODEL_x86_32
44 # include "adfiles/ad_x86_32.hpp"
45 #elif defined TARGET_ARCH_MODEL_x86_64
46 # include "adfiles/ad_x86_64.hpp"
47 #elif defined TARGET_ARCH_MODEL_aarch64
48 # include "adfiles/ad_aarch64.hpp"
49 #elif defined TARGET_ARCH_MODEL_sparc
50 # include "adfiles/ad_sparc.hpp"
51 #elif defined TARGET_ARCH_MODEL_zero
52 # include "adfiles/ad_zero.hpp"
53 #elif defined TARGET_ARCH_MODEL_ppc_64
54 # include "adfiles/ad_ppc_64.hpp"
55 #endif
56 #if INCLUDE_ALL_GCS
57 #include "gc_implementation/shenandoah/c2/shenandoahSupport.hpp"
58 #endif
59
60 OptoReg::Name OptoReg::c_frame_pointer;
61
62 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
63 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
64 RegMask Matcher::STACK_ONLY_mask;
65 RegMask Matcher::c_frame_ptr_mask;
66 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
67 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
68
69 //---------------------------Matcher-------------------------------------------
70 Matcher::Matcher()
71 : PhaseTransform( Phase::Ins_Select ),
72 #ifdef ASSERT
73 _old2new_map(C->comp_arena()),
74 _new2old_map(C->comp_arena()),
75 #endif
76 _shared_nodes(C->comp_arena()),
77 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
78 _swallowed(swallowed),
79 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
80 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
81 _must_clone(must_clone),
82 _register_save_policy(register_save_policy),
83 _c_reg_save_policy(c_reg_save_policy),
84 _register_save_type(register_save_type),
85 _ruleName(ruleName),
86 _allocation_started(false),
87 _states_arena(Chunk::medium_size, mtCompiler),
88 _visited(&_states_arena),
89 _shared(&_states_arena),
90 _dontcare(&_states_arena) {
91 C->set_matcher(this);
92
93 idealreg2spillmask [Op_RegI] = NULL;
94 idealreg2spillmask [Op_RegN] = NULL;
95 idealreg2spillmask [Op_RegL] = NULL;
96 idealreg2spillmask [Op_RegF] = NULL;
97 idealreg2spillmask [Op_RegD] = NULL;
98 idealreg2spillmask [Op_RegP] = NULL;
99 idealreg2spillmask [Op_VecS] = NULL;
100 idealreg2spillmask [Op_VecD] = NULL;
101 idealreg2spillmask [Op_VecX] = NULL;
102 idealreg2spillmask [Op_VecY] = NULL;
103 idealreg2spillmask [Op_RegFlags] = NULL;
104
105 idealreg2debugmask [Op_RegI] = NULL;
106 idealreg2debugmask [Op_RegN] = NULL;
107 idealreg2debugmask [Op_RegL] = NULL;
108 idealreg2debugmask [Op_RegF] = NULL;
109 idealreg2debugmask [Op_RegD] = NULL;
110 idealreg2debugmask [Op_RegP] = NULL;
111 idealreg2debugmask [Op_VecS] = NULL;
112 idealreg2debugmask [Op_VecD] = NULL;
113 idealreg2debugmask [Op_VecX] = NULL;
114 idealreg2debugmask [Op_VecY] = NULL;
115 idealreg2debugmask [Op_RegFlags] = NULL;
116
117 idealreg2mhdebugmask[Op_RegI] = NULL;
118 idealreg2mhdebugmask[Op_RegN] = NULL;
119 idealreg2mhdebugmask[Op_RegL] = NULL;
120 idealreg2mhdebugmask[Op_RegF] = NULL;
121 idealreg2mhdebugmask[Op_RegD] = NULL;
122 idealreg2mhdebugmask[Op_RegP] = NULL;
123 idealreg2mhdebugmask[Op_VecS] = NULL;
124 idealreg2mhdebugmask[Op_VecD] = NULL;
125 idealreg2mhdebugmask[Op_VecX] = NULL;
126 idealreg2mhdebugmask[Op_VecY] = NULL;
127 idealreg2mhdebugmask[Op_RegFlags] = NULL;
128
129 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
130 }
131
132 //------------------------------warp_incoming_stk_arg------------------------
133 // This warps a VMReg into an OptoReg::Name
134 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
135 OptoReg::Name warped;
136 if( reg->is_stack() ) { // Stack slot argument?
137 warped = OptoReg::add(_old_SP, reg->reg2stack() );
138 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
139 if( warped >= _in_arg_limit )
140 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
141 if (!RegMask::can_represent_arg(warped)) {
142 // the compiler cannot represent this method's calling sequence
143 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
144 return OptoReg::Bad;
145 }
146 return warped;
147 }
148 return OptoReg::as_OptoReg(reg);
149 }
150
151 //---------------------------compute_old_SP------------------------------------
152 OptoReg::Name Compile::compute_old_SP() {
153 int fixed = fixed_slots();
154 int preserve = in_preserve_stack_slots();
155 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
156 }
157
158
159
160 #ifdef ASSERT
161 void Matcher::verify_new_nodes_only(Node* xroot) {
162 // Make sure that the new graph only references new nodes
163 ResourceMark rm;
164 Unique_Node_List worklist;
165 VectorSet visited(Thread::current()->resource_area());
166 worklist.push(xroot);
167 while (worklist.size() > 0) {
168 Node* n = worklist.pop();
169 visited <<= n->_idx;
170 assert(C->node_arena()->contains(n), "dead node");
171 for (uint j = 0; j < n->req(); j++) {
172 Node* in = n->in(j);
173 if (in != NULL) {
174 assert(C->node_arena()->contains(in), "dead node");
175 if (!visited.test(in->_idx)) {
176 worklist.push(in);
177 }
178 }
179 }
180 }
181 }
182 #endif
183
184
185 //---------------------------match---------------------------------------------
186 void Matcher::match( ) {
187 if( MaxLabelRootDepth < 100 ) { // Too small?
188 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
189 MaxLabelRootDepth = 100;
190 }
191 // One-time initialization of some register masks.
192 init_spill_mask( C->root()->in(1) );
193 _return_addr_mask = return_addr();
194 #ifdef _LP64
195 // Pointers take 2 slots in 64-bit land
196 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
197 #endif
198
199 // Map a Java-signature return type into return register-value
200 // machine registers for 0, 1 and 2 returned values.
201 const TypeTuple *range = C->tf()->range();
202 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
203 // Get ideal-register return type
204 uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
205 // Get machine return register
206 uint sop = C->start()->Opcode();
207 OptoRegPair regs = return_value(ireg, false);
208
209 // And mask for same
210 _return_value_mask = RegMask(regs.first());
211 if( OptoReg::is_valid(regs.second()) )
212 _return_value_mask.Insert(regs.second());
213 }
214
215 // ---------------
216 // Frame Layout
217
218 // Need the method signature to determine the incoming argument types,
219 // because the types determine which registers the incoming arguments are
220 // in, and this affects the matched code.
221 const TypeTuple *domain = C->tf()->domain();
222 uint argcnt = domain->cnt() - TypeFunc::Parms;
223 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
224 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
225 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
226 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
227 uint i;
228 for( i = 0; i<argcnt; i++ ) {
229 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
230 }
231
232 // Pass array of ideal registers and length to USER code (from the AD file)
233 // that will convert this to an array of register numbers.
234 const StartNode *start = C->start();
235 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
236 #ifdef ASSERT
237 // Sanity check users' calling convention. Real handy while trying to
238 // get the initial port correct.
239 { for (uint i = 0; i<argcnt; i++) {
240 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
241 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
242 _parm_regs[i].set_bad();
243 continue;
244 }
245 VMReg parm_reg = vm_parm_regs[i].first();
246 assert(parm_reg->is_valid(), "invalid arg?");
247 if (parm_reg->is_reg()) {
248 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
249 assert(can_be_java_arg(opto_parm_reg) ||
250 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
251 opto_parm_reg == inline_cache_reg(),
252 "parameters in register must be preserved by runtime stubs");
253 }
254 for (uint j = 0; j < i; j++) {
255 assert(parm_reg != vm_parm_regs[j].first(),
256 "calling conv. must produce distinct regs");
257 }
258 }
259 }
260 #endif
261
262 // Do some initial frame layout.
263
264 // Compute the old incoming SP (may be called FP) as
265 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
266 _old_SP = C->compute_old_SP();
267 assert( is_even(_old_SP), "must be even" );
268
269 // Compute highest incoming stack argument as
270 // _old_SP + out_preserve_stack_slots + incoming argument size.
271 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
272 assert( is_even(_in_arg_limit), "out_preserve must be even" );
273 for( i = 0; i < argcnt; i++ ) {
274 // Permit args to have no register
275 _calling_convention_mask[i].Clear();
276 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
277 continue;
278 }
279 // calling_convention returns stack arguments as a count of
280 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
281 // the allocators point of view, taking into account all the
282 // preserve area, locks & pad2.
283
284 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
285 if( OptoReg::is_valid(reg1))
286 _calling_convention_mask[i].Insert(reg1);
287
288 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
289 if( OptoReg::is_valid(reg2))
290 _calling_convention_mask[i].Insert(reg2);
291
292 // Saved biased stack-slot register number
293 _parm_regs[i].set_pair(reg2, reg1);
294 }
295
296 // Finally, make sure the incoming arguments take up an even number of
297 // words, in case the arguments or locals need to contain doubleword stack
298 // slots. The rest of the system assumes that stack slot pairs (in
299 // particular, in the spill area) which look aligned will in fact be
300 // aligned relative to the stack pointer in the target machine. Double
301 // stack slots will always be allocated aligned.
302 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
303
304 // Compute highest outgoing stack argument as
305 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
306 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
307 assert( is_even(_out_arg_limit), "out_preserve must be even" );
308
309 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
310 // the compiler cannot represent this method's calling sequence
311 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
312 }
313
314 if (C->failing()) return; // bailed out on incoming arg failure
315
316 // ---------------
317 // Collect roots of matcher trees. Every node for which
318 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
319 // can be a valid interior of some tree.
320 find_shared( C->root() );
321 find_shared( C->top() );
322
323 C->print_method(PHASE_BEFORE_MATCHING);
324
325 // Create new ideal node ConP #NULL even if it does exist in old space
326 // to avoid false sharing if the corresponding mach node is not used.
327 // The corresponding mach node is only used in rare cases for derived
328 // pointers.
329 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR);
330
331 // Swap out to old-space; emptying new-space
332 Arena *old = C->node_arena()->move_contents(C->old_arena());
333
334 // Save debug and profile information for nodes in old space:
335 _old_node_note_array = C->node_note_array();
336 if (_old_node_note_array != NULL) {
337 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
338 (C->comp_arena(), _old_node_note_array->length(),
339 0, NULL));
340 }
341
342 // Pre-size the new_node table to avoid the need for range checks.
343 grow_new_node_array(C->unique());
344
345 // Reset node counter so MachNodes start with _idx at 0
346 int live_nodes = C->live_nodes();
347 C->set_unique(0);
348 C->reset_dead_node_list();
349
350 // Recursively match trees from old space into new space.
351 // Correct leaves of new-space Nodes; they point to old-space.
352 _visited.Clear(); // Clear visit bits for xform call
353 C->set_cached_top_node(xform( C->top(), live_nodes));
354 if (!C->failing()) {
355 Node* xroot = xform( C->root(), 1 );
356 if (xroot == NULL) {
357 Matcher::soft_match_failure(); // recursive matching process failed
358 C->record_method_not_compilable("instruction match failed");
359 } else {
360 // During matching shared constants were attached to C->root()
361 // because xroot wasn't available yet, so transfer the uses to
362 // the xroot.
363 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
364 Node* n = C->root()->fast_out(j);
365 if (C->node_arena()->contains(n)) {
366 assert(n->in(0) == C->root(), "should be control user");
367 n->set_req(0, xroot);
368 --j;
369 --jmax;
370 }
371 }
372
373 // Generate new mach node for ConP #NULL
374 assert(new_ideal_null != NULL, "sanity");
375 _mach_null = match_tree(new_ideal_null);
376 // Don't set control, it will confuse GCM since there are no uses.
377 // The control will be set when this node is used first time
378 // in find_base_for_derived().
379 assert(_mach_null != NULL, "");
380
381 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
382
383 #ifdef ASSERT
384 verify_new_nodes_only(xroot);
385 #endif
386 }
387 }
388 if (C->top() == NULL || C->root() == NULL) {
389 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
390 }
391 if (C->failing()) {
392 // delete old;
393 old->destruct_contents();
394 return;
395 }
396 assert( C->top(), "" );
397 assert( C->root(), "" );
398 validate_null_checks();
399
400 // Now smoke old-space
401 NOT_DEBUG( old->destruct_contents() );
402
403 // ------------------------
404 // Set up save-on-entry registers
405 Fixup_Save_On_Entry( );
406 }
407
408
409 //------------------------------Fixup_Save_On_Entry----------------------------
410 // The stated purpose of this routine is to take care of save-on-entry
411 // registers. However, the overall goal of the Match phase is to convert into
412 // machine-specific instructions which have RegMasks to guide allocation.
413 // So what this procedure really does is put a valid RegMask on each input
414 // to the machine-specific variations of all Return, TailCall and Halt
415 // instructions. It also adds edgs to define the save-on-entry values (and of
416 // course gives them a mask).
417
418 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
419 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
420 // Do all the pre-defined register masks
421 rms[TypeFunc::Control ] = RegMask::Empty;
422 rms[TypeFunc::I_O ] = RegMask::Empty;
423 rms[TypeFunc::Memory ] = RegMask::Empty;
424 rms[TypeFunc::ReturnAdr] = ret_adr;
425 rms[TypeFunc::FramePtr ] = fp;
426 return rms;
427 }
428
429 //---------------------------init_first_stack_mask-----------------------------
430 // Create the initial stack mask used by values spilling to the stack.
431 // Disallow any debug info in outgoing argument areas by setting the
432 // initial mask accordingly.
433 void Matcher::init_first_stack_mask() {
434
435 // Allocate storage for spill masks as masks for the appropriate load type.
436 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4));
437
438 idealreg2spillmask [Op_RegN] = &rms[0];
439 idealreg2spillmask [Op_RegI] = &rms[1];
440 idealreg2spillmask [Op_RegL] = &rms[2];
441 idealreg2spillmask [Op_RegF] = &rms[3];
442 idealreg2spillmask [Op_RegD] = &rms[4];
443 idealreg2spillmask [Op_RegP] = &rms[5];
444
445 idealreg2debugmask [Op_RegN] = &rms[6];
446 idealreg2debugmask [Op_RegI] = &rms[7];
447 idealreg2debugmask [Op_RegL] = &rms[8];
448 idealreg2debugmask [Op_RegF] = &rms[9];
449 idealreg2debugmask [Op_RegD] = &rms[10];
450 idealreg2debugmask [Op_RegP] = &rms[11];
451
452 idealreg2mhdebugmask[Op_RegN] = &rms[12];
453 idealreg2mhdebugmask[Op_RegI] = &rms[13];
454 idealreg2mhdebugmask[Op_RegL] = &rms[14];
455 idealreg2mhdebugmask[Op_RegF] = &rms[15];
456 idealreg2mhdebugmask[Op_RegD] = &rms[16];
457 idealreg2mhdebugmask[Op_RegP] = &rms[17];
458
459 idealreg2spillmask [Op_VecS] = &rms[18];
460 idealreg2spillmask [Op_VecD] = &rms[19];
461 idealreg2spillmask [Op_VecX] = &rms[20];
462 idealreg2spillmask [Op_VecY] = &rms[21];
463
464 OptoReg::Name i;
465
466 // At first, start with the empty mask
467 C->FIRST_STACK_mask().Clear();
468
469 // Add in the incoming argument area
470 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
471 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
472 C->FIRST_STACK_mask().Insert(i);
473 }
474 // Add in all bits past the outgoing argument area
475 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
476 "must be able to represent all call arguments in reg mask");
477 OptoReg::Name init = _out_arg_limit;
478 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
479 C->FIRST_STACK_mask().Insert(i);
480 }
481 // Finally, set the "infinite stack" bit.
482 C->FIRST_STACK_mask().set_AllStack();
483
484 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
485 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
486 // Keep spill masks aligned.
487 aligned_stack_mask.clear_to_pairs();
488 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
489
490 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
491 #ifdef _LP64
492 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
493 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
494 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
495 #else
496 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
497 #endif
498 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
499 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
500 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
501 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
502 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
503 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
504 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
505 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
506
507 if (Matcher::vector_size_supported(T_BYTE,4)) {
508 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
509 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
510 }
511 if (Matcher::vector_size_supported(T_FLOAT,2)) {
512 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
513 // RA guarantees such alignment since it is needed for Double and Long values.
514 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
515 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
516 }
517 if (Matcher::vector_size_supported(T_FLOAT,4)) {
518 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
519 //
520 // RA can use input arguments stack slots for spills but until RA
521 // we don't know frame size and offset of input arg stack slots.
522 //
523 // Exclude last input arg stack slots to avoid spilling vectors there
524 // otherwise vector spills could stomp over stack slots in caller frame.
525 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
526 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
527 aligned_stack_mask.Remove(in);
528 in = OptoReg::add(in, -1);
529 }
530 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
531 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
532 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
533 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
534 }
535 if (Matcher::vector_size_supported(T_FLOAT,8)) {
536 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
537 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
538 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
539 aligned_stack_mask.Remove(in);
540 in = OptoReg::add(in, -1);
541 }
542 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
543 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
544 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
545 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
546 }
547 if (UseFPUForSpilling) {
548 // This mask logic assumes that the spill operations are
549 // symmetric and that the registers involved are the same size.
550 // On sparc for instance we may have to use 64 bit moves will
551 // kill 2 registers when used with F0-F31.
552 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
553 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
554 #ifdef _LP64
555 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
556 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
557 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
558 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
559 #else
560 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
561 #ifdef ARM
562 // ARM has support for moving 64bit values between a pair of
563 // integer registers and a double register
564 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
565 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
566 #endif
567 #endif
568 }
569
570 // Make up debug masks. Any spill slot plus callee-save registers.
571 // Caller-save registers are assumed to be trashable by the various
572 // inline-cache fixup routines.
573 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
574 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
575 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
576 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
577 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
578 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
579
580 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
581 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
582 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
583 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
584 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
585 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
586
587 // Prevent stub compilations from attempting to reference
588 // callee-saved registers from debug info
589 bool exclude_soe = !Compile::current()->is_method_compilation();
590
591 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
592 // registers the caller has to save do not work
593 if( _register_save_policy[i] == 'C' ||
594 _register_save_policy[i] == 'A' ||
595 (_register_save_policy[i] == 'E' && exclude_soe) ) {
596 idealreg2debugmask [Op_RegN]->Remove(i);
597 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
598 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
599 idealreg2debugmask [Op_RegF]->Remove(i); // masks
600 idealreg2debugmask [Op_RegD]->Remove(i);
601 idealreg2debugmask [Op_RegP]->Remove(i);
602
603 idealreg2mhdebugmask[Op_RegN]->Remove(i);
604 idealreg2mhdebugmask[Op_RegI]->Remove(i);
605 idealreg2mhdebugmask[Op_RegL]->Remove(i);
606 idealreg2mhdebugmask[Op_RegF]->Remove(i);
607 idealreg2mhdebugmask[Op_RegD]->Remove(i);
608 idealreg2mhdebugmask[Op_RegP]->Remove(i);
609 }
610 }
611
612 // Subtract the register we use to save the SP for MethodHandle
613 // invokes to from the debug mask.
614 const RegMask save_mask = method_handle_invoke_SP_save_mask();
615 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
616 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
617 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
618 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
619 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
620 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
621 }
622
623 //---------------------------is_save_on_entry----------------------------------
624 bool Matcher::is_save_on_entry( int reg ) {
625 return
626 _register_save_policy[reg] == 'E' ||
627 _register_save_policy[reg] == 'A' || // Save-on-entry register?
628 // Also save argument registers in the trampolining stubs
629 (C->save_argument_registers() && is_spillable_arg(reg));
630 }
631
632 //---------------------------Fixup_Save_On_Entry-------------------------------
633 void Matcher::Fixup_Save_On_Entry( ) {
634 init_first_stack_mask();
635
636 Node *root = C->root(); // Short name for root
637 // Count number of save-on-entry registers.
638 uint soe_cnt = number_of_saved_registers();
639 uint i;
640
641 // Find the procedure Start Node
642 StartNode *start = C->start();
643 assert( start, "Expect a start node" );
644
645 // Save argument registers in the trampolining stubs
646 if( C->save_argument_registers() )
647 for( i = 0; i < _last_Mach_Reg; i++ )
648 if( is_spillable_arg(i) )
649 soe_cnt++;
650
651 // Input RegMask array shared by all Returns.
652 // The type for doubles and longs has a count of 2, but
653 // there is only 1 returned value
654 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
655 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
656 // Returns have 0 or 1 returned values depending on call signature.
657 // Return register is specified by return_value in the AD file.
658 if (ret_edge_cnt > TypeFunc::Parms)
659 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
660
661 // Input RegMask array shared by all Rethrows.
662 uint reth_edge_cnt = TypeFunc::Parms+1;
663 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
664 // Rethrow takes exception oop only, but in the argument 0 slot.
665 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
666 #ifdef _LP64
667 // Need two slots for ptrs in 64-bit land
668 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
669 #endif
670
671 // Input RegMask array shared by all TailCalls
672 uint tail_call_edge_cnt = TypeFunc::Parms+2;
673 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
674
675 // Input RegMask array shared by all TailJumps
676 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
677 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
678
679 // TailCalls have 2 returned values (target & moop), whose masks come
680 // from the usual MachNode/MachOper mechanism. Find a sample
681 // TailCall to extract these masks and put the correct masks into
682 // the tail_call_rms array.
683 for( i=1; i < root->req(); i++ ) {
684 MachReturnNode *m = root->in(i)->as_MachReturn();
685 if( m->ideal_Opcode() == Op_TailCall ) {
686 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
687 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
688 break;
689 }
690 }
691
692 // TailJumps have 2 returned values (target & ex_oop), whose masks come
693 // from the usual MachNode/MachOper mechanism. Find a sample
694 // TailJump to extract these masks and put the correct masks into
695 // the tail_jump_rms array.
696 for( i=1; i < root->req(); i++ ) {
697 MachReturnNode *m = root->in(i)->as_MachReturn();
698 if( m->ideal_Opcode() == Op_TailJump ) {
699 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
700 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
701 break;
702 }
703 }
704
705 // Input RegMask array shared by all Halts
706 uint halt_edge_cnt = TypeFunc::Parms;
707 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
708
709 // Capture the return input masks into each exit flavor
710 for( i=1; i < root->req(); i++ ) {
711 MachReturnNode *exit = root->in(i)->as_MachReturn();
712 switch( exit->ideal_Opcode() ) {
713 case Op_Return : exit->_in_rms = ret_rms; break;
714 case Op_Rethrow : exit->_in_rms = reth_rms; break;
715 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
716 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
717 case Op_Halt : exit->_in_rms = halt_rms; break;
718 default : ShouldNotReachHere();
719 }
720 }
721
722 // Next unused projection number from Start.
723 int proj_cnt = C->tf()->domain()->cnt();
724
725 // Do all the save-on-entry registers. Make projections from Start for
726 // them, and give them a use at the exit points. To the allocator, they
727 // look like incoming register arguments.
728 for( i = 0; i < _last_Mach_Reg; i++ ) {
729 if( is_save_on_entry(i) ) {
730
731 // Add the save-on-entry to the mask array
732 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
733 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
734 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
735 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
736 // Halts need the SOE registers, but only in the stack as debug info.
737 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
738 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
739
740 Node *mproj;
741
742 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
743 // into a single RegD.
744 if( (i&1) == 0 &&
745 _register_save_type[i ] == Op_RegF &&
746 _register_save_type[i+1] == Op_RegF &&
747 is_save_on_entry(i+1) ) {
748 // Add other bit for double
749 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
750 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
751 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
752 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
753 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
754 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
755 proj_cnt += 2; // Skip 2 for doubles
756 }
757 else if( (i&1) == 1 && // Else check for high half of double
758 _register_save_type[i-1] == Op_RegF &&
759 _register_save_type[i ] == Op_RegF &&
760 is_save_on_entry(i-1) ) {
761 ret_rms [ ret_edge_cnt] = RegMask::Empty;
762 reth_rms [ reth_edge_cnt] = RegMask::Empty;
763 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
764 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
765 halt_rms [ halt_edge_cnt] = RegMask::Empty;
766 mproj = C->top();
767 }
768 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
769 // into a single RegL.
770 else if( (i&1) == 0 &&
771 _register_save_type[i ] == Op_RegI &&
772 _register_save_type[i+1] == Op_RegI &&
773 is_save_on_entry(i+1) ) {
774 // Add other bit for long
775 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
776 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
777 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
778 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
779 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
780 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
781 proj_cnt += 2; // Skip 2 for longs
782 }
783 else if( (i&1) == 1 && // Else check for high half of long
784 _register_save_type[i-1] == Op_RegI &&
785 _register_save_type[i ] == Op_RegI &&
786 is_save_on_entry(i-1) ) {
787 ret_rms [ ret_edge_cnt] = RegMask::Empty;
788 reth_rms [ reth_edge_cnt] = RegMask::Empty;
789 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
790 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
791 halt_rms [ halt_edge_cnt] = RegMask::Empty;
792 mproj = C->top();
793 } else {
794 // Make a projection for it off the Start
795 mproj = new (C) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
796 }
797
798 ret_edge_cnt ++;
799 reth_edge_cnt ++;
800 tail_call_edge_cnt ++;
801 tail_jump_edge_cnt ++;
802 halt_edge_cnt ++;
803
804 // Add a use of the SOE register to all exit paths
805 for( uint j=1; j < root->req(); j++ )
806 root->in(j)->add_req(mproj);
807 } // End of if a save-on-entry register
808 } // End of for all machine registers
809 }
810
811 //------------------------------init_spill_mask--------------------------------
812 void Matcher::init_spill_mask( Node *ret ) {
813 if( idealreg2regmask[Op_RegI] ) return; // One time only init
814
815 OptoReg::c_frame_pointer = c_frame_pointer();
816 c_frame_ptr_mask = c_frame_pointer();
817 #ifdef _LP64
818 // pointers are twice as big
819 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
820 #endif
821
822 // Start at OptoReg::stack0()
823 STACK_ONLY_mask.Clear();
824 OptoReg::Name init = OptoReg::stack2reg(0);
825 // STACK_ONLY_mask is all stack bits
826 OptoReg::Name i;
827 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
828 STACK_ONLY_mask.Insert(i);
829 // Also set the "infinite stack" bit.
830 STACK_ONLY_mask.set_AllStack();
831
832 // Copy the register names over into the shared world
833 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
834 // SharedInfo::regName[i] = regName[i];
835 // Handy RegMasks per machine register
836 mreg2regmask[i].Insert(i);
837 }
838
839 // Grab the Frame Pointer
840 Node *fp = ret->in(TypeFunc::FramePtr);
841 Node *mem = ret->in(TypeFunc::Memory);
842 const TypePtr* atp = TypePtr::BOTTOM;
843 // Share frame pointer while making spill ops
844 set_shared(fp);
845
846 // Compute generic short-offset Loads
847 #ifdef _LP64
848 MachNode *spillCP = match_tree(new (C) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
849 #endif
850 MachNode *spillI = match_tree(new (C) LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
851 MachNode *spillL = match_tree(new (C) LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest,false));
852 MachNode *spillF = match_tree(new (C) LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
853 MachNode *spillD = match_tree(new (C) LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
854 MachNode *spillP = match_tree(new (C) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
855 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
856 spillD != NULL && spillP != NULL, "");
857 // Get the ADLC notion of the right regmask, for each basic type.
858 #ifdef _LP64
859 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
860 #endif
861 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
862 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
863 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
864 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
865 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
866
867 // Vector regmasks.
868 if (Matcher::vector_size_supported(T_BYTE,4)) {
869 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
870 MachNode *spillVectS = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
871 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
872 }
873 if (Matcher::vector_size_supported(T_FLOAT,2)) {
874 MachNode *spillVectD = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
875 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
876 }
877 if (Matcher::vector_size_supported(T_FLOAT,4)) {
878 MachNode *spillVectX = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
879 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
880 }
881 if (Matcher::vector_size_supported(T_FLOAT,8)) {
882 MachNode *spillVectY = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
883 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
884 }
885 }
886
887 #ifdef ASSERT
888 static void match_alias_type(Compile* C, Node* n, Node* m) {
889 if (!VerifyAliases) return; // do not go looking for trouble by default
890 const TypePtr* nat = n->adr_type();
891 const TypePtr* mat = m->adr_type();
892 int nidx = C->get_alias_index(nat);
893 int midx = C->get_alias_index(mat);
894 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
895 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
896 for (uint i = 1; i < n->req(); i++) {
897 Node* n1 = n->in(i);
898 const TypePtr* n1at = n1->adr_type();
899 if (n1at != NULL) {
900 nat = n1at;
901 nidx = C->get_alias_index(n1at);
902 }
903 }
904 }
905 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
906 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
907 switch (n->Opcode()) {
908 case Op_PrefetchRead:
909 case Op_PrefetchWrite:
910 case Op_PrefetchAllocation:
911 nidx = Compile::AliasIdxRaw;
912 nat = TypeRawPtr::BOTTOM;
913 break;
914 }
915 }
916 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
917 switch (n->Opcode()) {
918 case Op_ClearArray:
919 midx = Compile::AliasIdxRaw;
920 mat = TypeRawPtr::BOTTOM;
921 break;
922 }
923 }
924 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
925 switch (n->Opcode()) {
926 case Op_Return:
927 case Op_Rethrow:
928 case Op_Halt:
929 case Op_TailCall:
930 case Op_TailJump:
931 nidx = Compile::AliasIdxBot;
932 nat = TypePtr::BOTTOM;
933 break;
934 }
935 }
936 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
937 switch (n->Opcode()) {
938 case Op_StrComp:
939 case Op_StrEquals:
940 case Op_StrIndexOf:
941 case Op_AryEq:
942 case Op_MemBarVolatile:
943 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
944 case Op_EncodeISOArray:
945 nidx = Compile::AliasIdxTop;
946 nat = NULL;
947 break;
948 }
949 }
950 if (nidx != midx) {
951 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
952 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
953 n->dump();
954 m->dump();
955 }
956 assert(C->subsume_loads() && C->must_alias(nat, midx),
957 "must not lose alias info when matching");
958 }
959 }
960 #endif
961
962
963 //------------------------------MStack-----------------------------------------
964 // State and MStack class used in xform() and find_shared() iterative methods.
965 enum Node_State { Pre_Visit, // node has to be pre-visited
966 Visit, // visit node
967 Post_Visit, // post-visit node
968 Alt_Post_Visit // alternative post-visit path
969 };
970
971 class MStack: public Node_Stack {
972 public:
973 MStack(int size) : Node_Stack(size) { }
974
975 void push(Node *n, Node_State ns) {
976 Node_Stack::push(n, (uint)ns);
977 }
978 void push(Node *n, Node_State ns, Node *parent, int indx) {
979 ++_inode_top;
980 if ((_inode_top + 1) >= _inode_max) grow();
981 _inode_top->node = parent;
982 _inode_top->indx = (uint)indx;
983 ++_inode_top;
984 _inode_top->node = n;
985 _inode_top->indx = (uint)ns;
986 }
987 Node *parent() {
988 pop();
989 return node();
990 }
991 Node_State state() const {
992 return (Node_State)index();
993 }
994 void set_state(Node_State ns) {
995 set_index((uint)ns);
996 }
997 };
998
999
1000 //------------------------------xform------------------------------------------
1001 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1002 // Node in new-space. Given a new-space Node, recursively walk his children.
1003 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1004 Node *Matcher::xform( Node *n, int max_stack ) {
1005 // Use one stack to keep both: child's node/state and parent's node/index
1006 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1007 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
1008
1009 while (mstack.is_nonempty()) {
1010 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1011 if (C->failing()) return NULL;
1012 n = mstack.node(); // Leave node on stack
1013 Node_State nstate = mstack.state();
1014 if (nstate == Visit) {
1015 mstack.set_state(Post_Visit);
1016 Node *oldn = n;
1017 // Old-space or new-space check
1018 if (!C->node_arena()->contains(n)) {
1019 // Old space!
1020 Node* m;
1021 if (has_new_node(n)) { // Not yet Label/Reduced
1022 m = new_node(n);
1023 } else {
1024 if (!is_dontcare(n)) { // Matcher can match this guy
1025 // Calls match special. They match alone with no children.
1026 // Their children, the incoming arguments, match normally.
1027 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1028 if (C->failing()) return NULL;
1029 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1030 if (n->is_MemBar() && UseShenandoahGC) {
1031 m->as_MachMemBar()->set_adr_type(n->adr_type());
1032 }
1033 } else { // Nothing the matcher cares about
1034 if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) { // Projections?
1035 // Convert to machine-dependent projection
1036 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1037 #ifdef ASSERT
1038 _new2old_map.map(m->_idx, n);
1039 #endif
1040 if (m->in(0) != NULL) // m might be top
1041 collect_null_checks(m, n);
1042 } else { // Else just a regular 'ol guy
1043 m = n->clone(); // So just clone into new-space
1044 #ifdef ASSERT
1045 _new2old_map.map(m->_idx, n);
1046 #endif
1047 // Def-Use edges will be added incrementally as Uses
1048 // of this node are matched.
1049 assert(m->outcnt() == 0, "no Uses of this clone yet");
1050 }
1051 }
1052
1053 set_new_node(n, m); // Map old to new
1054 if (_old_node_note_array != NULL) {
1055 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1056 n->_idx);
1057 C->set_node_notes_at(m->_idx, nn);
1058 }
1059 debug_only(match_alias_type(C, n, m));
1060 }
1061 n = m; // n is now a new-space node
1062 mstack.set_node(n);
1063 }
1064
1065 // New space!
1066 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1067
1068 int i;
1069 // Put precedence edges on stack first (match them last).
1070 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1071 Node *m = oldn->in(i);
1072 if (m == NULL) break;
1073 // set -1 to call add_prec() instead of set_req() during Step1
1074 mstack.push(m, Visit, n, -1);
1075 }
1076
1077 // Handle precedence edges for interior nodes
1078 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1079 Node *m = n->in(i);
1080 if (m == NULL || C->node_arena()->contains(m)) continue;
1081 n->rm_prec(i);
1082 // set -1 to call add_prec() instead of set_req() during Step1
1083 mstack.push(m, Visit, n, -1);
1084 }
1085
1086 // For constant debug info, I'd rather have unmatched constants.
1087 int cnt = n->req();
1088 JVMState* jvms = n->jvms();
1089 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1090
1091 // Now do only debug info. Clone constants rather than matching.
1092 // Constants are represented directly in the debug info without
1093 // the need for executable machine instructions.
1094 // Monitor boxes are also represented directly.
1095 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1096 Node *m = n->in(i); // Get input
1097 int op = m->Opcode();
1098 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1099 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1100 op == Op_ConF || op == Op_ConD || op == Op_ConL
1101 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1102 ) {
1103 m = m->clone();
1104 #ifdef ASSERT
1105 _new2old_map.map(m->_idx, n);
1106 #endif
1107 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1108 mstack.push(m->in(0), Visit, m, 0);
1109 } else {
1110 mstack.push(m, Visit, n, i);
1111 }
1112 }
1113
1114 // And now walk his children, and convert his inputs to new-space.
1115 for( ; i >= 0; --i ) { // For all normal inputs do
1116 Node *m = n->in(i); // Get input
1117 if(m != NULL)
1118 mstack.push(m, Visit, n, i);
1119 }
1120
1121 }
1122 else if (nstate == Post_Visit) {
1123 // Set xformed input
1124 Node *p = mstack.parent();
1125 if (p != NULL) { // root doesn't have parent
1126 int i = (int)mstack.index();
1127 if (i >= 0)
1128 p->set_req(i, n); // required input
1129 else if (i == -1)
1130 p->add_prec(n); // precedence input
1131 else
1132 ShouldNotReachHere();
1133 }
1134 mstack.pop(); // remove processed node from stack
1135 }
1136 else {
1137 ShouldNotReachHere();
1138 }
1139 } // while (mstack.is_nonempty())
1140 return n; // Return new-space Node
1141 }
1142
1143 //------------------------------warp_outgoing_stk_arg------------------------
1144 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1145 // Convert outgoing argument location to a pre-biased stack offset
1146 if (reg->is_stack()) {
1147 OptoReg::Name warped = reg->reg2stack();
1148 // Adjust the stack slot offset to be the register number used
1149 // by the allocator.
1150 warped = OptoReg::add(begin_out_arg_area, warped);
1151 // Keep track of the largest numbered stack slot used for an arg.
1152 // Largest used slot per call-site indicates the amount of stack
1153 // that is killed by the call.
1154 if( warped >= out_arg_limit_per_call )
1155 out_arg_limit_per_call = OptoReg::add(warped,1);
1156 if (!RegMask::can_represent_arg(warped)) {
1157 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1158 return OptoReg::Bad;
1159 }
1160 return warped;
1161 }
1162 return OptoReg::as_OptoReg(reg);
1163 }
1164
1165
1166 //------------------------------match_sfpt-------------------------------------
1167 // Helper function to match call instructions. Calls match special.
1168 // They match alone with no children. Their children, the incoming
1169 // arguments, match normally.
1170 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1171 MachSafePointNode *msfpt = NULL;
1172 MachCallNode *mcall = NULL;
1173 uint cnt;
1174 // Split out case for SafePoint vs Call
1175 CallNode *call;
1176 const TypeTuple *domain;
1177 ciMethod* method = NULL;
1178 bool is_method_handle_invoke = false; // for special kill effects
1179 if( sfpt->is_Call() ) {
1180 call = sfpt->as_Call();
1181 domain = call->tf()->domain();
1182 cnt = domain->cnt();
1183
1184 // Match just the call, nothing else
1185 MachNode *m = match_tree(call);
1186 if (C->failing()) return NULL;
1187 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1188
1189 // Copy data from the Ideal SafePoint to the machine version
1190 mcall = m->as_MachCall();
1191
1192 mcall->set_tf( call->tf());
1193 mcall->set_entry_point(call->entry_point());
1194 mcall->set_cnt( call->cnt());
1195
1196 if( mcall->is_MachCallJava() ) {
1197 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1198 const CallJavaNode *call_java = call->as_CallJava();
1199 method = call_java->method();
1200 mcall_java->_method = method;
1201 mcall_java->_bci = call_java->_bci;
1202 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1203 is_method_handle_invoke = call_java->is_method_handle_invoke();
1204 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1205 if (is_method_handle_invoke) {
1206 C->set_has_method_handle_invokes(true);
1207 }
1208 if( mcall_java->is_MachCallStaticJava() )
1209 mcall_java->as_MachCallStaticJava()->_name =
1210 call_java->as_CallStaticJava()->_name;
1211 if( mcall_java->is_MachCallDynamicJava() )
1212 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1213 call_java->as_CallDynamicJava()->_vtable_index;
1214 }
1215 else if( mcall->is_MachCallRuntime() ) {
1216 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1217 }
1218 msfpt = mcall;
1219 }
1220 // This is a non-call safepoint
1221 else {
1222 call = NULL;
1223 domain = NULL;
1224 MachNode *mn = match_tree(sfpt);
1225 if (C->failing()) return NULL;
1226 msfpt = mn->as_MachSafePoint();
1227 cnt = TypeFunc::Parms;
1228 }
1229
1230 // Advertise the correct memory effects (for anti-dependence computation).
1231 msfpt->set_adr_type(sfpt->adr_type());
1232
1233 // Allocate a private array of RegMasks. These RegMasks are not shared.
1234 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1235 // Empty them all.
1236 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1237
1238 // Do all the pre-defined non-Empty register masks
1239 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1240 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1241
1242 // Place first outgoing argument can possibly be put.
1243 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1244 assert( is_even(begin_out_arg_area), "" );
1245 // Compute max outgoing register number per call site.
1246 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1247 // Calls to C may hammer extra stack slots above and beyond any arguments.
1248 // These are usually backing store for register arguments for varargs.
1249 if( call != NULL && call->is_CallRuntime() )
1250 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1251
1252
1253 // Do the normal argument list (parameters) register masks
1254 int argcnt = cnt - TypeFunc::Parms;
1255 if( argcnt > 0 ) { // Skip it all if we have no args
1256 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1257 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1258 int i;
1259 for( i = 0; i < argcnt; i++ ) {
1260 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1261 }
1262 // V-call to pick proper calling convention
1263 call->calling_convention( sig_bt, parm_regs, argcnt );
1264
1265 #ifdef ASSERT
1266 // Sanity check users' calling convention. Really handy during
1267 // the initial porting effort. Fairly expensive otherwise.
1268 { for (int i = 0; i<argcnt; i++) {
1269 if( !parm_regs[i].first()->is_valid() &&
1270 !parm_regs[i].second()->is_valid() ) continue;
1271 VMReg reg1 = parm_regs[i].first();
1272 VMReg reg2 = parm_regs[i].second();
1273 for (int j = 0; j < i; j++) {
1274 if( !parm_regs[j].first()->is_valid() &&
1275 !parm_regs[j].second()->is_valid() ) continue;
1276 VMReg reg3 = parm_regs[j].first();
1277 VMReg reg4 = parm_regs[j].second();
1278 if( !reg1->is_valid() ) {
1279 assert( !reg2->is_valid(), "valid halvsies" );
1280 } else if( !reg3->is_valid() ) {
1281 assert( !reg4->is_valid(), "valid halvsies" );
1282 } else {
1283 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1284 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1285 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1286 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1287 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1288 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1289 }
1290 }
1291 }
1292 }
1293 #endif
1294
1295 // Visit each argument. Compute its outgoing register mask.
1296 // Return results now can have 2 bits returned.
1297 // Compute max over all outgoing arguments both per call-site
1298 // and over the entire method.
1299 for( i = 0; i < argcnt; i++ ) {
1300 // Address of incoming argument mask to fill in
1301 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1302 if( !parm_regs[i].first()->is_valid() &&
1303 !parm_regs[i].second()->is_valid() ) {
1304 continue; // Avoid Halves
1305 }
1306 // Grab first register, adjust stack slots and insert in mask.
1307 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1308 if (OptoReg::is_valid(reg1))
1309 rm->Insert( reg1 );
1310 // Grab second register (if any), adjust stack slots and insert in mask.
1311 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1312 if (OptoReg::is_valid(reg2))
1313 rm->Insert( reg2 );
1314 } // End of for all arguments
1315
1316 // Compute number of stack slots needed to restore stack in case of
1317 // Pascal-style argument popping.
1318 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1319 }
1320
1321 // Compute the max stack slot killed by any call. These will not be
1322 // available for debug info, and will be used to adjust FIRST_STACK_mask
1323 // after all call sites have been visited.
1324 if( _out_arg_limit < out_arg_limit_per_call)
1325 _out_arg_limit = out_arg_limit_per_call;
1326
1327 if (mcall) {
1328 // Kill the outgoing argument area, including any non-argument holes and
1329 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1330 // Since the max-per-method covers the max-per-call-site and debug info
1331 // is excluded on the max-per-method basis, debug info cannot land in
1332 // this killed area.
1333 uint r_cnt = mcall->tf()->range()->cnt();
1334 MachProjNode *proj = new (C) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1335 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1336 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1337 } else {
1338 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1339 proj->_rout.Insert(OptoReg::Name(i));
1340 }
1341 if (proj->_rout.is_NotEmpty()) {
1342 push_projection(proj);
1343 }
1344 }
1345 // Transfer the safepoint information from the call to the mcall
1346 // Move the JVMState list
1347 msfpt->set_jvms(sfpt->jvms());
1348 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1349 jvms->set_map(sfpt);
1350 }
1351
1352 // Debug inputs begin just after the last incoming parameter
1353 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1354 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1355
1356 // Move the OopMap
1357 msfpt->_oop_map = sfpt->_oop_map;
1358
1359 // Add additional edges.
1360 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1361 // For these calls we can not add MachConstantBase in expand(), as the
1362 // ins are not complete then.
1363 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1364 if (msfpt->jvms() &&
1365 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1366 // We added an edge before jvms, so we must adapt the position of the ins.
1367 msfpt->jvms()->adapt_position(+1);
1368 }
1369 }
1370
1371 // Registers killed by the call are set in the local scheduling pass
1372 // of Global Code Motion.
1373 return msfpt;
1374 }
1375
1376 //---------------------------match_tree----------------------------------------
1377 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1378 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1379 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1380 // a Load's result RegMask for memoization in idealreg2regmask[]
1381 MachNode *Matcher::match_tree( const Node *n ) {
1382 assert( n->Opcode() != Op_Phi, "cannot match" );
1383 assert( !n->is_block_start(), "cannot match" );
1384 // Set the mark for all locally allocated State objects.
1385 // When this call returns, the _states_arena arena will be reset
1386 // freeing all State objects.
1387 ResourceMark rm( &_states_arena );
1388
1389 LabelRootDepth = 0;
1390
1391 // StoreNodes require their Memory input to match any LoadNodes
1392 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1393 #ifdef ASSERT
1394 Node* save_mem_node = _mem_node;
1395 _mem_node = n->is_Store() ? (Node*)n : NULL;
1396 #endif
1397 // State object for root node of match tree
1398 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1399 State *s = new (&_states_arena) State;
1400 s->_kids[0] = NULL;
1401 s->_kids[1] = NULL;
1402 s->_leaf = (Node*)n;
1403 // Label the input tree, allocating labels from top-level arena
1404 Label_Root( n, s, n->in(0), mem );
1405 if (C->failing()) return NULL;
1406
1407 // The minimum cost match for the whole tree is found at the root State
1408 uint mincost = max_juint;
1409 uint cost = max_juint;
1410 uint i;
1411 for( i = 0; i < NUM_OPERANDS; i++ ) {
1412 if( s->valid(i) && // valid entry and
1413 s->_cost[i] < cost && // low cost and
1414 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1415 cost = s->_cost[mincost=i];
1416 }
1417 if (mincost == max_juint) {
1418 #ifndef PRODUCT
1419 tty->print("No matching rule for:");
1420 s->dump();
1421 #endif
1422 Matcher::soft_match_failure();
1423 return NULL;
1424 }
1425 // Reduce input tree based upon the state labels to machine Nodes
1426 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1427 #ifdef ASSERT
1428 _old2new_map.map(n->_idx, m);
1429 _new2old_map.map(m->_idx, (Node*)n);
1430 #endif
1431
1432 // Add any Matcher-ignored edges
1433 uint cnt = n->req();
1434 uint start = 1;
1435 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1436 if( n->is_AddP() ) {
1437 assert( mem == (Node*)1, "" );
1438 start = AddPNode::Base+1;
1439 }
1440 for( i = start; i < cnt; i++ ) {
1441 if( !n->match_edge(i) ) {
1442 if( i < m->req() )
1443 m->ins_req( i, n->in(i) );
1444 else
1445 m->add_req( n->in(i) );
1446 }
1447 }
1448
1449 debug_only( _mem_node = save_mem_node; )
1450 return m;
1451 }
1452
1453
1454 //------------------------------match_into_reg---------------------------------
1455 // Choose to either match this Node in a register or part of the current
1456 // match tree. Return true for requiring a register and false for matching
1457 // as part of the current match tree.
1458 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1459
1460 const Type *t = m->bottom_type();
1461
1462 if (t->singleton()) {
1463 // Never force constants into registers. Allow them to match as
1464 // constants or registers. Copies of the same value will share
1465 // the same register. See find_shared_node.
1466 return false;
1467 } else { // Not a constant
1468 // Stop recursion if they have different Controls.
1469 Node* m_control = m->in(0);
1470 // Control of load's memory can post-dominates load's control.
1471 // So use it since load can't float above its memory.
1472 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1473 if (control && m_control && control != m_control && control != mem_control) {
1474
1475 // Actually, we can live with the most conservative control we
1476 // find, if it post-dominates the others. This allows us to
1477 // pick up load/op/store trees where the load can float a little
1478 // above the store.
1479 Node *x = control;
1480 const uint max_scan = 6; // Arbitrary scan cutoff
1481 uint j;
1482 for (j=0; j<max_scan; j++) {
1483 if (x->is_Region()) // Bail out at merge points
1484 return true;
1485 x = x->in(0);
1486 if (x == m_control) // Does 'control' post-dominate
1487 break; // m->in(0)? If so, we can use it
1488 if (x == mem_control) // Does 'control' post-dominate
1489 break; // mem_control? If so, we can use it
1490 }
1491 if (j == max_scan) // No post-domination before scan end?
1492 return true; // Then break the match tree up
1493 }
1494 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1495 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1496 // These are commonly used in address expressions and can
1497 // efficiently fold into them on X64 in some cases.
1498 return false;
1499 }
1500 }
1501
1502 // Not forceable cloning. If shared, put it into a register.
1503 return shared;
1504 }
1505
1506
1507 //------------------------------Instruction Selection--------------------------
1508 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1509 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1510 // things the Matcher does not match (e.g., Memory), and things with different
1511 // Controls (hence forced into different blocks). We pass in the Control
1512 // selected for this entire State tree.
1513
1514 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1515 // Store and the Load must have identical Memories (as well as identical
1516 // pointers). Since the Matcher does not have anything for Memory (and
1517 // does not handle DAGs), I have to match the Memory input myself. If the
1518 // Tree root is a Store, I require all Loads to have the identical memory.
1519 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1520 // Since Label_Root is a recursive function, its possible that we might run
1521 // out of stack space. See bugs 6272980 & 6227033 for more info.
1522 LabelRootDepth++;
1523 if (LabelRootDepth > MaxLabelRootDepth) {
1524 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1525 return NULL;
1526 }
1527 uint care = 0; // Edges matcher cares about
1528 uint cnt = n->req();
1529 uint i = 0;
1530
1531 // Examine children for memory state
1532 // Can only subsume a child into your match-tree if that child's memory state
1533 // is not modified along the path to another input.
1534 // It is unsafe even if the other inputs are separate roots.
1535 Node *input_mem = NULL;
1536 for( i = 1; i < cnt; i++ ) {
1537 if( !n->match_edge(i) ) continue;
1538 Node *m = n->in(i); // Get ith input
1539 assert( m, "expect non-null children" );
1540 if( m->is_Load() ) {
1541 if( input_mem == NULL ) {
1542 input_mem = m->in(MemNode::Memory);
1543 } else if( input_mem != m->in(MemNode::Memory) ) {
1544 input_mem = NodeSentinel;
1545 }
1546 }
1547 }
1548
1549 for( i = 1; i < cnt; i++ ){// For my children
1550 if( !n->match_edge(i) ) continue;
1551 Node *m = n->in(i); // Get ith input
1552 // Allocate states out of a private arena
1553 State *s = new (&_states_arena) State;
1554 svec->_kids[care++] = s;
1555 assert( care <= 2, "binary only for now" );
1556
1557 // Recursively label the State tree.
1558 s->_kids[0] = NULL;
1559 s->_kids[1] = NULL;
1560 s->_leaf = m;
1561
1562 // Check for leaves of the State Tree; things that cannot be a part of
1563 // the current tree. If it finds any, that value is matched as a
1564 // register operand. If not, then the normal matching is used.
1565 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1566 //
1567 // Stop recursion if this is LoadNode and the root of this tree is a
1568 // StoreNode and the load & store have different memories.
1569 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1570 // Can NOT include the match of a subtree when its memory state
1571 // is used by any of the other subtrees
1572 (input_mem == NodeSentinel) ) {
1573 #ifndef PRODUCT
1574 // Print when we exclude matching due to different memory states at input-loads
1575 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1576 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1577 tty->print_cr("invalid input_mem");
1578 }
1579 #endif
1580 // Switch to a register-only opcode; this value must be in a register
1581 // and cannot be subsumed as part of a larger instruction.
1582 s->DFA( m->ideal_reg(), m );
1583
1584 } else {
1585 // If match tree has no control and we do, adopt it for entire tree
1586 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1587 control = m->in(0); // Pick up control
1588 // Else match as a normal part of the match tree.
1589 control = Label_Root(m,s,control,mem);
1590 if (C->failing()) return NULL;
1591 }
1592 }
1593
1594
1595 // Call DFA to match this node, and return
1596 svec->DFA( n->Opcode(), n );
1597
1598 #ifdef ASSERT
1599 uint x;
1600 for( x = 0; x < _LAST_MACH_OPER; x++ )
1601 if( svec->valid(x) )
1602 break;
1603
1604 if (x >= _LAST_MACH_OPER) {
1605 n->dump();
1606 svec->dump();
1607 assert( false, "bad AD file" );
1608 }
1609 #endif
1610 return control;
1611 }
1612
1613
1614 // Con nodes reduced using the same rule can share their MachNode
1615 // which reduces the number of copies of a constant in the final
1616 // program. The register allocator is free to split uses later to
1617 // split live ranges.
1618 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1619 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1620
1621 // See if this Con has already been reduced using this rule.
1622 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1623 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1624 if (last != NULL && rule == last->rule()) {
1625 // Don't expect control change for DecodeN
1626 if (leaf->is_DecodeNarrowPtr())
1627 return last;
1628 // Get the new space root.
1629 Node* xroot = new_node(C->root());
1630 if (xroot == NULL) {
1631 // This shouldn't happen give the order of matching.
1632 return NULL;
1633 }
1634
1635 // Shared constants need to have their control be root so they
1636 // can be scheduled properly.
1637 Node* control = last->in(0);
1638 if (control != xroot) {
1639 if (control == NULL || control == C->root()) {
1640 last->set_req(0, xroot);
1641 } else {
1642 assert(false, "unexpected control");
1643 return NULL;
1644 }
1645 }
1646 return last;
1647 }
1648 return NULL;
1649 }
1650
1651
1652 //------------------------------ReduceInst-------------------------------------
1653 // Reduce a State tree (with given Control) into a tree of MachNodes.
1654 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1655 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1656 // Each MachNode has a number of complicated MachOper operands; each
1657 // MachOper also covers a further tree of Ideal Nodes.
1658
1659 // The root of the Ideal match tree is always an instruction, so we enter
1660 // the recursion here. After building the MachNode, we need to recurse
1661 // the tree checking for these cases:
1662 // (1) Child is an instruction -
1663 // Build the instruction (recursively), add it as an edge.
1664 // Build a simple operand (register) to hold the result of the instruction.
1665 // (2) Child is an interior part of an instruction -
1666 // Skip over it (do nothing)
1667 // (3) Child is the start of a operand -
1668 // Build the operand, place it inside the instruction
1669 // Call ReduceOper.
1670 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1671 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1672
1673 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1674 if (shared_node != NULL) {
1675 return shared_node;
1676 }
1677
1678 // Build the object to represent this state & prepare for recursive calls
1679 MachNode *mach = s->MachNodeGenerator( rule, C );
1680 guarantee(mach != NULL, "Missing MachNode");
1681 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1682 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1683 Node *leaf = s->_leaf;
1684 // Check for instruction or instruction chain rule
1685 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1686 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1687 "duplicating node that's already been matched");
1688 // Instruction
1689 mach->add_req( leaf->in(0) ); // Set initial control
1690 // Reduce interior of complex instruction
1691 ReduceInst_Interior( s, rule, mem, mach, 1 );
1692 } else {
1693 // Instruction chain rules are data-dependent on their inputs
1694 mach->add_req(0); // Set initial control to none
1695 ReduceInst_Chain_Rule( s, rule, mem, mach );
1696 }
1697
1698 // If a Memory was used, insert a Memory edge
1699 if( mem != (Node*)1 ) {
1700 mach->ins_req(MemNode::Memory,mem);
1701 #ifdef ASSERT
1702 // Verify adr type after matching memory operation
1703 const MachOper* oper = mach->memory_operand();
1704 if (oper != NULL && oper != (MachOper*)-1) {
1705 // It has a unique memory operand. Find corresponding ideal mem node.
1706 Node* m = NULL;
1707 if (leaf->is_Mem()) {
1708 m = leaf;
1709 } else {
1710 m = _mem_node;
1711 assert(m != NULL && m->is_Mem(), "expecting memory node");
1712 }
1713 const Type* mach_at = mach->adr_type();
1714 // DecodeN node consumed by an address may have different type
1715 // then its input. Don't compare types for such case.
1716 if (m->adr_type() != mach_at &&
1717 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1718 m->in(MemNode::Address)->is_AddP() &&
1719 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1720 m->in(MemNode::Address)->is_AddP() &&
1721 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1722 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1723 mach_at = m->adr_type();
1724 }
1725 if (m->adr_type() != mach_at) {
1726 m->dump();
1727 tty->print_cr("mach:");
1728 mach->dump(1);
1729 }
1730 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1731 }
1732 #endif
1733 }
1734
1735 // If the _leaf is an AddP, insert the base edge
1736 if (leaf->is_AddP()) {
1737 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1738 }
1739
1740 uint number_of_projections_prior = number_of_projections();
1741
1742 // Perform any 1-to-many expansions required
1743 MachNode *ex = mach->Expand(s, _projection_list, mem);
1744 if (ex != mach) {
1745 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1746 if( ex->in(1)->is_Con() )
1747 ex->in(1)->set_req(0, C->root());
1748 // Remove old node from the graph
1749 for( uint i=0; i<mach->req(); i++ ) {
1750 mach->set_req(i,NULL);
1751 }
1752 #ifdef ASSERT
1753 _new2old_map.map(ex->_idx, s->_leaf);
1754 #endif
1755 }
1756
1757 // PhaseChaitin::fixup_spills will sometimes generate spill code
1758 // via the matcher. By the time, nodes have been wired into the CFG,
1759 // and any further nodes generated by expand rules will be left hanging
1760 // in space, and will not get emitted as output code. Catch this.
1761 // Also, catch any new register allocation constraints ("projections")
1762 // generated belatedly during spill code generation.
1763 if (_allocation_started) {
1764 guarantee(ex == mach, "no expand rules during spill generation");
1765 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1766 }
1767
1768 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1769 // Record the con for sharing
1770 _shared_nodes.map(leaf->_idx, ex);
1771 }
1772
1773 return ex;
1774 }
1775
1776 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1777 for (uint i = n->req(); i < n->len(); i++) {
1778 if (n->in(i) != NULL) {
1779 mach->add_prec(n->in(i));
1780 }
1781 }
1782 }
1783
1784 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1785 // 'op' is what I am expecting to receive
1786 int op = _leftOp[rule];
1787 // Operand type to catch childs result
1788 // This is what my child will give me.
1789 int opnd_class_instance = s->_rule[op];
1790 // Choose between operand class or not.
1791 // This is what I will receive.
1792 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1793 // New rule for child. Chase operand classes to get the actual rule.
1794 int newrule = s->_rule[catch_op];
1795
1796 if( newrule < NUM_OPERANDS ) {
1797 // Chain from operand or operand class, may be output of shared node
1798 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1799 "Bad AD file: Instruction chain rule must chain from operand");
1800 // Insert operand into array of operands for this instruction
1801 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1802
1803 ReduceOper( s, newrule, mem, mach );
1804 } else {
1805 // Chain from the result of an instruction
1806 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1807 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1808 Node *mem1 = (Node*)1;
1809 debug_only(Node *save_mem_node = _mem_node;)
1810 mach->add_req( ReduceInst(s, newrule, mem1) );
1811 debug_only(_mem_node = save_mem_node;)
1812 }
1813 return;
1814 }
1815
1816
1817 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1818 handle_precedence_edges(s->_leaf, mach);
1819
1820 if( s->_leaf->is_Load() ) {
1821 Node *mem2 = s->_leaf->in(MemNode::Memory);
1822 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1823 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1824 mem = mem2;
1825 }
1826 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1827 if( mach->in(0) == NULL )
1828 mach->set_req(0, s->_leaf->in(0));
1829 }
1830
1831 // Now recursively walk the state tree & add operand list.
1832 for( uint i=0; i<2; i++ ) { // binary tree
1833 State *newstate = s->_kids[i];
1834 if( newstate == NULL ) break; // Might only have 1 child
1835 // 'op' is what I am expecting to receive
1836 int op;
1837 if( i == 0 ) {
1838 op = _leftOp[rule];
1839 } else {
1840 op = _rightOp[rule];
1841 }
1842 // Operand type to catch childs result
1843 // This is what my child will give me.
1844 int opnd_class_instance = newstate->_rule[op];
1845 // Choose between operand class or not.
1846 // This is what I will receive.
1847 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1848 // New rule for child. Chase operand classes to get the actual rule.
1849 int newrule = newstate->_rule[catch_op];
1850
1851 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1852 // Operand/operandClass
1853 // Insert operand into array of operands for this instruction
1854 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1855 ReduceOper( newstate, newrule, mem, mach );
1856
1857 } else { // Child is internal operand or new instruction
1858 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1859 // internal operand --> call ReduceInst_Interior
1860 // Interior of complex instruction. Do nothing but recurse.
1861 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1862 } else {
1863 // instruction --> call build operand( ) to catch result
1864 // --> ReduceInst( newrule )
1865 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1866 Node *mem1 = (Node*)1;
1867 debug_only(Node *save_mem_node = _mem_node;)
1868 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1869 debug_only(_mem_node = save_mem_node;)
1870 }
1871 }
1872 assert( mach->_opnds[num_opnds-1], "" );
1873 }
1874 return num_opnds;
1875 }
1876
1877 // This routine walks the interior of possible complex operands.
1878 // At each point we check our children in the match tree:
1879 // (1) No children -
1880 // We are a leaf; add _leaf field as an input to the MachNode
1881 // (2) Child is an internal operand -
1882 // Skip over it ( do nothing )
1883 // (3) Child is an instruction -
1884 // Call ReduceInst recursively and
1885 // and instruction as an input to the MachNode
1886 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1887 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1888 State *kid = s->_kids[0];
1889 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1890
1891 // Leaf? And not subsumed?
1892 if( kid == NULL && !_swallowed[rule] ) {
1893 mach->add_req( s->_leaf ); // Add leaf pointer
1894 return; // Bail out
1895 }
1896
1897 if( s->_leaf->is_Load() ) {
1898 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1899 mem = s->_leaf->in(MemNode::Memory);
1900 debug_only(_mem_node = s->_leaf;)
1901 }
1902
1903 handle_precedence_edges(s->_leaf, mach);
1904
1905 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1906 if( !mach->in(0) )
1907 mach->set_req(0,s->_leaf->in(0));
1908 else {
1909 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1910 }
1911 }
1912
1913 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1914 int newrule;
1915 if( i == 0)
1916 newrule = kid->_rule[_leftOp[rule]];
1917 else
1918 newrule = kid->_rule[_rightOp[rule]];
1919
1920 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1921 // Internal operand; recurse but do nothing else
1922 ReduceOper( kid, newrule, mem, mach );
1923
1924 } else { // Child is a new instruction
1925 // Reduce the instruction, and add a direct pointer from this
1926 // machine instruction to the newly reduced one.
1927 Node *mem1 = (Node*)1;
1928 debug_only(Node *save_mem_node = _mem_node;)
1929 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1930 debug_only(_mem_node = save_mem_node;)
1931 }
1932 }
1933 }
1934
1935
1936 // -------------------------------------------------------------------------
1937 // Java-Java calling convention
1938 // (what you use when Java calls Java)
1939
1940 //------------------------------find_receiver----------------------------------
1941 // For a given signature, return the OptoReg for parameter 0.
1942 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1943 VMRegPair regs;
1944 BasicType sig_bt = T_OBJECT;
1945 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1946 // Return argument 0 register. In the LP64 build pointers
1947 // take 2 registers, but the VM wants only the 'main' name.
1948 return OptoReg::as_OptoReg(regs.first());
1949 }
1950
1951 // This function identifies sub-graphs in which a 'load' node is
1952 // input to two different nodes, and such that it can be matched
1953 // with BMI instructions like blsi, blsr, etc.
1954 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1955 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1956 // refers to the same node.
1957 #ifdef X86
1958 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1959 // This is a temporary solution until we make DAGs expressible in ADL.
1960 template<typename ConType>
1961 class FusedPatternMatcher {
1962 Node* _op1_node;
1963 Node* _mop_node;
1964 int _con_op;
1965
1966 static int match_next(Node* n, int next_op, int next_op_idx) {
1967 if (n->in(1) == NULL || n->in(2) == NULL) {
1968 return -1;
1969 }
1970
1971 if (next_op_idx == -1) { // n is commutative, try rotations
1972 if (n->in(1)->Opcode() == next_op) {
1973 return 1;
1974 } else if (n->in(2)->Opcode() == next_op) {
1975 return 2;
1976 }
1977 } else {
1978 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1979 if (n->in(next_op_idx)->Opcode() == next_op) {
1980 return next_op_idx;
1981 }
1982 }
1983 return -1;
1984 }
1985 public:
1986 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1987 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1988
1989 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1990 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1991 typename ConType::NativeType con_value) {
1992 if (_op1_node->Opcode() != op1) {
1993 return false;
1994 }
1995 if (_mop_node->outcnt() > 2) {
1996 return false;
1997 }
1998 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1999 if (op1_op2_idx == -1) {
2000 return false;
2001 }
2002 // Memory operation must be the other edge
2003 int op1_mop_idx = (op1_op2_idx & 1) + 1;
2004
2005 // Check that the mop node is really what we want
2006 if (_op1_node->in(op1_mop_idx) == _mop_node) {
2007 Node *op2_node = _op1_node->in(op1_op2_idx);
2008 if (op2_node->outcnt() > 1) {
2009 return false;
2010 }
2011 assert(op2_node->Opcode() == op2, "Should be");
2012 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
2013 if (op2_con_idx == -1) {
2014 return false;
2015 }
2016 // Memory operation must be the other edge
2017 int op2_mop_idx = (op2_con_idx & 1) + 1;
2018 // Check that the memory operation is the same node
2019 if (op2_node->in(op2_mop_idx) == _mop_node) {
2020 // Now check the constant
2021 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
2022 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
2023 return true;
2024 }
2025 }
2026 }
2027 return false;
2028 }
2029 };
2030
2031
2032 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2033 if (n != NULL && m != NULL) {
2034 if (m->Opcode() == Op_LoadI) {
2035 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2036 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2037 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2038 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2039 } else if (m->Opcode() == Op_LoadL) {
2040 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2041 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2042 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2043 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2044 }
2045 }
2046 return false;
2047 }
2048 #endif // X86
2049
2050 // A method-klass-holder may be passed in the inline_cache_reg
2051 // and then expanded into the inline_cache_reg and a method_oop register
2052 // defined in ad_<arch>.cpp
2053
2054
2055 //------------------------------find_shared------------------------------------
2056 // Set bits if Node is shared or otherwise a root
2057 void Matcher::find_shared( Node *n ) {
2058 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2059 MStack mstack(C->live_nodes() * 2);
2060 // Mark nodes as address_visited if they are inputs to an address expression
2061 VectorSet address_visited(Thread::current()->resource_area());
2062 mstack.push(n, Visit); // Don't need to pre-visit root node
2063 while (mstack.is_nonempty()) {
2064 n = mstack.node(); // Leave node on stack
2065 Node_State nstate = mstack.state();
2066 uint nop = n->Opcode();
2067 if (nstate == Pre_Visit) {
2068 if (address_visited.test(n->_idx)) { // Visited in address already?
2069 // Flag as visited and shared now.
2070 set_visited(n);
2071 }
2072 if (is_visited(n)) { // Visited already?
2073 // Node is shared and has no reason to clone. Flag it as shared.
2074 // This causes it to match into a register for the sharing.
2075 set_shared(n); // Flag as shared and
2076 if (n->is_DecodeNarrowPtr()) {
2077 // Oop field/array element loads must be shared but since
2078 // they are shared through a DecodeN they may appear to have
2079 // a single use so force sharing here.
2080 set_shared(n->in(1));
2081 }
2082 mstack.pop(); // remove node from stack
2083 continue;
2084 }
2085 nstate = Visit; // Not already visited; so visit now
2086 }
2087 if (nstate == Visit) {
2088 mstack.set_state(Post_Visit);
2089 set_visited(n); // Flag as visited now
2090 bool mem_op = false;
2091
2092 switch( nop ) { // Handle some opcodes special
2093 case Op_Phi: // Treat Phis as shared roots
2094 case Op_Parm:
2095 case Op_Proj: // All handled specially during matching
2096 case Op_SafePointScalarObject:
2097 set_shared(n);
2098 set_dontcare(n);
2099 break;
2100 case Op_If:
2101 case Op_CountedLoopEnd:
2102 mstack.set_state(Alt_Post_Visit); // Alternative way
2103 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2104 // with matching cmp/branch in 1 instruction. The Matcher needs the
2105 // Bool and CmpX side-by-side, because it can only get at constants
2106 // that are at the leaves of Match trees, and the Bool's condition acts
2107 // as a constant here.
2108 mstack.push(n->in(1), Visit); // Clone the Bool
2109 mstack.push(n->in(0), Pre_Visit); // Visit control input
2110 continue; // while (mstack.is_nonempty())
2111 case Op_ConvI2D: // These forms efficiently match with a prior
2112 case Op_ConvI2F: // Load but not a following Store
2113 if( n->in(1)->is_Load() && // Prior load
2114 n->outcnt() == 1 && // Not already shared
2115 n->unique_out()->is_Store() ) // Following store
2116 set_shared(n); // Force it to be a root
2117 break;
2118 case Op_ReverseBytesI:
2119 case Op_ReverseBytesL:
2120 if( n->in(1)->is_Load() && // Prior load
2121 n->outcnt() == 1 ) // Not already shared
2122 set_shared(n); // Force it to be a root
2123 break;
2124 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2125 case Op_IfFalse:
2126 case Op_IfTrue:
2127 case Op_MachProj:
2128 case Op_MergeMem:
2129 case Op_Catch:
2130 case Op_CatchProj:
2131 case Op_CProj:
2132 case Op_JumpProj:
2133 case Op_JProj:
2134 case Op_NeverBranch:
2135 set_dontcare(n);
2136 break;
2137 case Op_Jump:
2138 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2139 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2140 continue; // while (mstack.is_nonempty())
2141 case Op_StrComp:
2142 case Op_StrEquals:
2143 case Op_StrIndexOf:
2144 case Op_AryEq:
2145 case Op_EncodeISOArray:
2146 set_shared(n); // Force result into register (it will be anyways)
2147 break;
2148 case Op_ConP: { // Convert pointers above the centerline to NUL
2149 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2150 const TypePtr* tp = tn->type()->is_ptr();
2151 if (tp->_ptr == TypePtr::AnyNull) {
2152 tn->set_type(TypePtr::NULL_PTR);
2153 }
2154 break;
2155 }
2156 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2157 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2158 const TypePtr* tp = tn->type()->make_ptr();
2159 if (tp && tp->_ptr == TypePtr::AnyNull) {
2160 tn->set_type(TypeNarrowOop::NULL_PTR);
2161 }
2162 break;
2163 }
2164 case Op_Binary: // These are introduced in the Post_Visit state.
2165 ShouldNotReachHere();
2166 break;
2167 case Op_ClearArray:
2168 case Op_SafePoint:
2169 mem_op = true;
2170 break;
2171 default:
2172 if( n->is_Store() ) {
2173 // Do match stores, despite no ideal reg
2174 mem_op = true;
2175 break;
2176 }
2177 if( n->is_Mem() ) { // Loads and LoadStores
2178 mem_op = true;
2179 // Loads must be root of match tree due to prior load conflict
2180 if( C->subsume_loads() == false )
2181 set_shared(n);
2182 }
2183 // Fall into default case
2184 if( !n->ideal_reg() )
2185 set_dontcare(n); // Unmatchable Nodes
2186 } // end_switch
2187
2188 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2189 Node *m = n->in(i); // Get ith input
2190 if (m == NULL) continue; // Ignore NULLs
2191 uint mop = m->Opcode();
2192
2193 // Must clone all producers of flags, or we will not match correctly.
2194 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2195 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2196 // are also there, so we may match a float-branch to int-flags and
2197 // expect the allocator to haul the flags from the int-side to the
2198 // fp-side. No can do.
2199 if( _must_clone[mop] ) {
2200 mstack.push(m, Visit);
2201 continue; // for(int i = ...)
2202 }
2203
2204 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2205 #ifdef X86
2206 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2207 mstack.push(m, Visit);
2208 continue;
2209 }
2210 #endif
2211
2212 // Clone addressing expressions as they are "free" in memory access instructions
2213 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
2214 // Some inputs for address expression are not put on stack
2215 // to avoid marking them as shared and forcing them into register
2216 // if they are used only in address expressions.
2217 // But they should be marked as shared if there are other uses
2218 // besides address expressions.
2219
2220 Node *off = m->in(AddPNode::Offset);
2221 if( off->is_Con() &&
2222 // When there are other uses besides address expressions
2223 // put it on stack and mark as shared.
2224 !is_visited(m) ) {
2225 address_visited.test_set(m->_idx); // Flag as address_visited
2226 Node *adr = m->in(AddPNode::Address);
2227
2228 // Intel, ARM and friends can handle 2 adds in addressing mode
2229 if( clone_shift_expressions && adr->is_AddP() &&
2230 // AtomicAdd is not an addressing expression.
2231 // Cheap to find it by looking for screwy base.
2232 !adr->in(AddPNode::Base)->is_top() &&
2233 // Are there other uses besides address expressions?
2234 !is_visited(adr) ) {
2235 address_visited.set(adr->_idx); // Flag as address_visited
2236 Node *shift = adr->in(AddPNode::Offset);
2237 // Check for shift by small constant as well
2238 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2239 shift->in(2)->get_int() <= 3 &&
2240 // Are there other uses besides address expressions?
2241 !is_visited(shift) ) {
2242 address_visited.set(shift->_idx); // Flag as address_visited
2243 mstack.push(shift->in(2), Visit);
2244 Node *conv = shift->in(1);
2245 #ifdef _LP64
2246 // Allow Matcher to match the rule which bypass
2247 // ConvI2L operation for an array index on LP64
2248 // if the index value is positive.
2249 if( conv->Opcode() == Op_ConvI2L &&
2250 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2251 // Are there other uses besides address expressions?
2252 !is_visited(conv) ) {
2253 address_visited.set(conv->_idx); // Flag as address_visited
2254 mstack.push(conv->in(1), Pre_Visit);
2255 } else
2256 #endif
2257 mstack.push(conv, Pre_Visit);
2258 } else {
2259 mstack.push(shift, Pre_Visit);
2260 }
2261 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2262 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2263 } else { // Sparc, Alpha, PPC and friends
2264 mstack.push(adr, Pre_Visit);
2265 }
2266
2267 // Clone X+offset as it also folds into most addressing expressions
2268 mstack.push(off, Visit);
2269 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2270 continue; // for(int i = ...)
2271 } // if( off->is_Con() )
2272 } // if( mem_op &&
2273 mstack.push(m, Pre_Visit);
2274 } // for(int i = ...)
2275 }
2276 else if (nstate == Alt_Post_Visit) {
2277 mstack.pop(); // Remove node from stack
2278 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2279 // shared and all users of the Bool need to move the Cmp in parallel.
2280 // This leaves both the Bool and the If pointing at the Cmp. To
2281 // prevent the Matcher from trying to Match the Cmp along both paths
2282 // BoolNode::match_edge always returns a zero.
2283
2284 // We reorder the Op_If in a pre-order manner, so we can visit without
2285 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2286 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2287 }
2288 else if (nstate == Post_Visit) {
2289 mstack.pop(); // Remove node from stack
2290
2291 // Now hack a few special opcodes
2292 switch( n->Opcode() ) { // Handle some opcodes special
2293 case Op_StorePConditional:
2294 case Op_StoreIConditional:
2295 case Op_StoreLConditional:
2296 case Op_CompareAndSwapI:
2297 case Op_CompareAndSwapL:
2298 case Op_CompareAndSwapP:
2299 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2300 Node *newval = n->in(MemNode::ValueIn );
2301 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2302 Node *pair = new (C) BinaryNode( oldval, newval );
2303 n->set_req(MemNode::ValueIn,pair);
2304 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2305 break;
2306 }
2307 case Op_CMoveD: // Convert trinary to binary-tree
2308 case Op_CMoveF:
2309 case Op_CMoveI:
2310 case Op_CMoveL:
2311 case Op_CMoveN:
2312 case Op_CMoveP: {
2313 // Restructure into a binary tree for Matching. It's possible that
2314 // we could move this code up next to the graph reshaping for IfNodes
2315 // or vice-versa, but I do not want to debug this for Ladybird.
2316 // 10/2/2000 CNC.
2317 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(1)->in(1));
2318 n->set_req(1,pair1);
2319 Node *pair2 = new (C) BinaryNode(n->in(2),n->in(3));
2320 n->set_req(2,pair2);
2321 n->del_req(3);
2322 break;
2323 }
2324 case Op_LoopLimit: {
2325 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(2));
2326 n->set_req(1,pair1);
2327 n->set_req(2,n->in(3));
2328 n->del_req(3);
2329 break;
2330 }
2331 case Op_StrEquals: {
2332 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2333 n->set_req(2,pair1);
2334 n->set_req(3,n->in(4));
2335 n->del_req(4);
2336 break;
2337 }
2338 case Op_StrComp:
2339 case Op_StrIndexOf: {
2340 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2341 n->set_req(2,pair1);
2342 Node *pair2 = new (C) BinaryNode(n->in(4),n->in(5));
2343 n->set_req(3,pair2);
2344 n->del_req(5);
2345 n->del_req(4);
2346 break;
2347 }
2348 case Op_EncodeISOArray: {
2349 // Restructure into a binary tree for Matching.
2350 Node* pair = new (C) BinaryNode(n->in(3), n->in(4));
2351 n->set_req(3, pair);
2352 n->del_req(4);
2353 break;
2354 }
2355 default:
2356 break;
2357 }
2358 }
2359 else {
2360 ShouldNotReachHere();
2361 }
2362 } // end of while (mstack.is_nonempty())
2363 }
2364
2365 #ifdef ASSERT
2366 // machine-independent root to machine-dependent root
2367 void Matcher::dump_old2new_map() {
2368 _old2new_map.dump();
2369 }
2370 #endif
2371
2372 //---------------------------collect_null_checks-------------------------------
2373 // Find null checks in the ideal graph; write a machine-specific node for
2374 // it. Used by later implicit-null-check handling. Actually collects
2375 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2376 // value being tested.
2377 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2378 Node *iff = proj->in(0);
2379 if( iff->Opcode() == Op_If ) {
2380 // During matching If's have Bool & Cmp side-by-side
2381 BoolNode *b = iff->in(1)->as_Bool();
2382 Node *cmp = iff->in(2);
2383 int opc = cmp->Opcode();
2384 if (opc != Op_CmpP && opc != Op_CmpN) return;
2385
2386 const Type* ct = cmp->in(2)->bottom_type();
2387 if (ct == TypePtr::NULL_PTR ||
2388 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2389
2390 bool push_it = false;
2391 if( proj->Opcode() == Op_IfTrue ) {
2392 extern int all_null_checks_found;
2393 all_null_checks_found++;
2394 if( b->_test._test == BoolTest::ne ) {
2395 push_it = true;
2396 }
2397 } else {
2398 assert( proj->Opcode() == Op_IfFalse, "" );
2399 if( b->_test._test == BoolTest::eq ) {
2400 push_it = true;
2401 }
2402 }
2403 if( push_it ) {
2404 _null_check_tests.push(proj);
2405 Node* val = cmp->in(1);
2406 #ifdef _LP64
2407 if (val->bottom_type()->isa_narrowoop() &&
2408 !Matcher::narrow_oop_use_complex_address()) {
2409 //
2410 // Look for DecodeN node which should be pinned to orig_proj.
2411 // On platforms (Sparc) which can not handle 2 adds
2412 // in addressing mode we have to keep a DecodeN node and
2413 // use it to do implicit NULL check in address.
2414 //
2415 // DecodeN node was pinned to non-null path (orig_proj) during
2416 // CastPP transformation in final_graph_reshaping_impl().
2417 //
2418 uint cnt = orig_proj->outcnt();
2419 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2420 Node* d = orig_proj->raw_out(i);
2421 if (d->is_DecodeN() && d->in(1) == val) {
2422 val = d;
2423 val->set_req(0, NULL); // Unpin now.
2424 // Mark this as special case to distinguish from
2425 // a regular case: CmpP(DecodeN, NULL).
2426 val = (Node*)(((intptr_t)val) | 1);
2427 break;
2428 }
2429 }
2430 }
2431 #endif
2432 _null_check_tests.push(val);
2433 }
2434 }
2435 }
2436 }
2437
2438 //---------------------------validate_null_checks------------------------------
2439 // Its possible that the value being NULL checked is not the root of a match
2440 // tree. If so, I cannot use the value in an implicit null check.
2441 void Matcher::validate_null_checks( ) {
2442 uint cnt = _null_check_tests.size();
2443 for( uint i=0; i < cnt; i+=2 ) {
2444 Node *test = _null_check_tests[i];
2445 Node *val = _null_check_tests[i+1];
2446 bool is_decoden = ((intptr_t)val) & 1;
2447 val = (Node*)(((intptr_t)val) & ~1);
2448 if (has_new_node(val)) {
2449 Node* new_val = new_node(val);
2450 if (is_decoden) {
2451 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2452 // Note: new_val may have a control edge if
2453 // the original ideal node DecodeN was matched before
2454 // it was unpinned in Matcher::collect_null_checks().
2455 // Unpin the mach node and mark it.
2456 new_val->set_req(0, NULL);
2457 new_val = (Node*)(((intptr_t)new_val) | 1);
2458 }
2459 // Is a match-tree root, so replace with the matched value
2460 _null_check_tests.map(i+1, new_val);
2461 } else {
2462 // Yank from candidate list
2463 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2464 _null_check_tests.map(i,_null_check_tests[--cnt]);
2465 _null_check_tests.pop();
2466 _null_check_tests.pop();
2467 i-=2;
2468 }
2469 }
2470 }
2471
2472 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2473 // atomic instruction acting as a store_load barrier without any
2474 // intervening volatile load, and thus we don't need a barrier here.
2475 // We retain the Node to act as a compiler ordering barrier.
2476 bool Matcher::post_store_load_barrier(const Node* vmb) {
2477 Compile* C = Compile::current();
2478 assert(vmb->is_MemBar(), "");
2479 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2480 const MemBarNode* membar = vmb->as_MemBar();
2481
2482 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2483 Node* ctrl = NULL;
2484 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2485 Node* p = membar->fast_out(i);
2486 assert(p->is_Proj(), "only projections here");
2487 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2488 !C->node_arena()->contains(p)) { // Unmatched old-space only
2489 ctrl = p;
2490 break;
2491 }
2492 }
2493 assert((ctrl != NULL), "missing control projection");
2494
2495 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2496 Node *x = ctrl->fast_out(j);
2497 int xop = x->Opcode();
2498
2499 // We don't need current barrier if we see another or a lock
2500 // before seeing volatile load.
2501 //
2502 // Op_Fastunlock previously appeared in the Op_* list below.
2503 // With the advent of 1-0 lock operations we're no longer guaranteed
2504 // that a monitor exit operation contains a serializing instruction.
2505
2506 if (xop == Op_MemBarVolatile ||
2507 xop == Op_CompareAndSwapL ||
2508 xop == Op_CompareAndSwapP ||
2509 xop == Op_CompareAndSwapN ||
2510 xop == Op_CompareAndSwapI) {
2511 return true;
2512 }
2513
2514 // Op_FastLock previously appeared in the Op_* list above.
2515 // With biased locking we're no longer guaranteed that a monitor
2516 // enter operation contains a serializing instruction.
2517 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2518 return true;
2519 }
2520
2521 if (x->is_MemBar()) {
2522 // We must retain this membar if there is an upcoming volatile
2523 // load, which will be followed by acquire membar.
2524 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2525 return false;
2526 } else {
2527 // For other kinds of barriers, check by pretending we
2528 // are them, and seeing if we can be removed.
2529 return post_store_load_barrier(x->as_MemBar());
2530 }
2531 }
2532
2533 // probably not necessary to check for these
2534 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2535 return false;
2536 }
2537 }
2538 return false;
2539 }
2540
2541 // Check whether node n is a branch to an uncommon trap that we could
2542 // optimize as test with very high branch costs in case of going to
2543 // the uncommon trap. The code must be able to be recompiled to use
2544 // a cheaper test.
2545 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2546 // Don't do it for natives, adapters, or runtime stubs
2547 Compile *C = Compile::current();
2548 if (!C->is_method_compilation()) return false;
2549
2550 assert(n->is_If(), "You should only call this on if nodes.");
2551 IfNode *ifn = n->as_If();
2552
2553 Node *ifFalse = NULL;
2554 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2555 if (ifn->fast_out(i)->is_IfFalse()) {
2556 ifFalse = ifn->fast_out(i);
2557 break;
2558 }
2559 }
2560 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2561
2562 Node *reg = ifFalse;
2563 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2564 // Alternatively use visited set? Seems too expensive.
2565 while (reg != NULL && cnt > 0) {
2566 CallNode *call = NULL;
2567 RegionNode *nxt_reg = NULL;
2568 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2569 Node *o = reg->fast_out(i);
2570 if (o->is_Call()) {
2571 call = o->as_Call();
2572 }
2573 if (o->is_Region()) {
2574 nxt_reg = o->as_Region();
2575 }
2576 }
2577
2578 if (call &&
2579 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2580 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2581 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2582 jint tr_con = trtype->is_int()->get_con();
2583 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2584 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2585 assert((int)reason < (int)BitsPerInt, "recode bit map");
2586
2587 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2588 && action != Deoptimization::Action_none) {
2589 // This uncommon trap is sure to recompile, eventually.
2590 // When that happens, C->too_many_traps will prevent
2591 // this transformation from happening again.
2592 return true;
2593 }
2594 }
2595 }
2596
2597 reg = nxt_reg;
2598 cnt--;
2599 }
2600
2601 return false;
2602 }
2603
2604 //=============================================================================
2605 //---------------------------State---------------------------------------------
2606 State::State(void) {
2607 #ifdef ASSERT
2608 _id = 0;
2609 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2610 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2611 //memset(_cost, -1, sizeof(_cost));
2612 //memset(_rule, -1, sizeof(_rule));
2613 #endif
2614 memset(_valid, 0, sizeof(_valid));
2615 }
2616
2617 #ifdef ASSERT
2618 State::~State() {
2619 _id = 99;
2620 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2621 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2622 memset(_cost, -3, sizeof(_cost));
2623 memset(_rule, -3, sizeof(_rule));
2624 }
2625 #endif
2626
2627 #ifndef PRODUCT
2628 //---------------------------dump----------------------------------------------
2629 void State::dump() {
2630 tty->print("\n");
2631 dump(0);
2632 }
2633
2634 void State::dump(int depth) {
2635 for( int j = 0; j < depth; j++ )
2636 tty->print(" ");
2637 tty->print("--N: ");
2638 _leaf->dump();
2639 uint i;
2640 for( i = 0; i < _LAST_MACH_OPER; i++ )
2641 // Check for valid entry
2642 if( valid(i) ) {
2643 for( int j = 0; j < depth; j++ )
2644 tty->print(" ");
2645 assert(_cost[i] != max_juint, "cost must be a valid value");
2646 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2647 tty->print_cr("%s %d %s",
2648 ruleName[i], _cost[i], ruleName[_rule[i]] );
2649 }
2650 tty->cr();
2651
2652 for( i=0; i<2; i++ )
2653 if( _kids[i] )
2654 _kids[i]->dump(depth+1);
2655 }
2656 #endif