1 /*
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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5 * This code is free software; you can redistribute it and/or modify it
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 */
24
25 #ifndef SHARE_VM_OPTO_MATCHER_HPP
26 #define SHARE_VM_OPTO_MATCHER_HPP
27
28 #include "libadt/vectset.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "opto/node.hpp"
31 #include "opto/phaseX.hpp"
32 #include "opto/regmask.hpp"
33
34 class Compile;
35 class Node;
36 class MachNode;
37 class MachTypeNode;
38 class MachOper;
39
40 //---------------------------Matcher-------------------------------------------
41 class Matcher : public PhaseTransform {
42 friend class VMStructs;
43 // Private arena of State objects
44 ResourceArea _states_arena;
45
46 VectorSet _visited; // Visit bits
47
48 // Used to control the Label pass
49 VectorSet _shared; // Shared Ideal Node
50 VectorSet _dontcare; // Nothing the matcher cares about
51
52 // Private methods which perform the actual matching and reduction
53 // Walks the label tree, generating machine nodes
54 MachNode *ReduceInst( State *s, int rule, Node *&mem);
55 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach);
56 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds);
57 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach );
58
59 // If this node already matched using "rule", return the MachNode for it.
60 MachNode* find_shared_node(Node* n, uint rule);
61
62 // Convert a dense opcode number to an expanded rule number
63 const int *_reduceOp;
64 const int *_leftOp;
65 const int *_rightOp;
66
67 // Map dense opcode number to info on when rule is swallowed constant.
68 const bool *_swallowed;
69
70 // Map dense rule number to determine if this is an instruction chain rule
71 const uint _begin_inst_chain_rule;
72 const uint _end_inst_chain_rule;
73
74 // We want to clone constants and possible CmpI-variants.
75 // If we do not clone CmpI, then we can have many instances of
76 // condition codes alive at once. This is OK on some chips and
77 // bad on others. Hence the machine-dependent table lookup.
78 const char *_must_clone;
79
80 // Find shared Nodes, or Nodes that otherwise are Matcher roots
81 void find_shared( Node *n );
82 #ifdef X86
83 bool is_bmi_pattern(Node *n, Node *m);
84 #endif
85
86 // Debug and profile information for nodes in old space:
87 GrowableArray<Node_Notes*>* _old_node_note_array;
88
89 // Node labeling iterator for instruction selection
90 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem );
91
92 Node *transform( Node *dummy );
93
94 Node_List _projection_list; // For Machine nodes killing many values
95
96 Node_Array _shared_nodes;
97
98 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots
99 debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal
100
101 // Accessors for the inherited field PhaseTransform::_nodes:
102 void grow_new_node_array(uint idx_limit) {
103 _nodes.map(idx_limit-1, NULL);
104 }
105 bool has_new_node(const Node* n) const {
106 return _nodes.at(n->_idx) != NULL;
107 }
108 Node* new_node(const Node* n) const {
109 assert(has_new_node(n), "set before get");
110 return _nodes.at(n->_idx);
111 }
112 void set_new_node(const Node* n, Node *nn) {
113 assert(!has_new_node(n), "set only once");
114 _nodes.map(n->_idx, nn);
115 }
116
117 #ifdef ASSERT
118 // Make sure only new nodes are reachable from this node
119 void verify_new_nodes_only(Node* root);
120
121 Node* _mem_node; // Ideal memory node consumed by mach node
122 #endif
123
124 // Mach node for ConP #NULL
125 MachNode* _mach_null;
126
127 void handle_precedence_edges(Node* n, MachNode *mach);
128
129 public:
130 int LabelRootDepth;
131 // Convert ideal machine register to a register mask for spill-loads
132 static const RegMask *idealreg2regmask[];
133 RegMask *idealreg2spillmask [_last_machine_leaf];
134 RegMask *idealreg2debugmask [_last_machine_leaf];
135 RegMask *idealreg2mhdebugmask[_last_machine_leaf];
136 void init_spill_mask( Node *ret );
137 // Convert machine register number to register mask
138 static uint mreg2regmask_max;
139 static RegMask mreg2regmask[];
140 static RegMask STACK_ONLY_mask;
141
142 MachNode* mach_null() const { return _mach_null; }
143
144 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; }
145 void set_shared( Node *n ) { _shared.set(n->_idx); }
146 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; }
147 void set_visited( Node *n ) { _visited.set(n->_idx); }
148 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; }
149 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); }
150
151 // Mode bit to tell DFA and expand rules whether we are running after
152 // (or during) register selection. Usually, the matcher runs before,
153 // but it will also get called to generate post-allocation spill code.
154 // In this situation, it is a deadly error to attempt to allocate more
155 // temporary registers.
156 bool _allocation_started;
157
158 // Machine register names
159 static const char *regName[];
160 // Machine register encodings
161 static const unsigned char _regEncode[];
162 // Machine Node names
163 const char **_ruleName;
164 // Rules that are cheaper to rematerialize than to spill
165 static const uint _begin_rematerialize;
166 static const uint _end_rematerialize;
167
168 // An array of chars, from 0 to _last_Mach_Reg.
169 // No Save = 'N' (for register windows)
170 // Save on Entry = 'E'
171 // Save on Call = 'C'
172 // Always Save = 'A' (same as SOE + SOC)
173 const char *_register_save_policy;
174 const char *_c_reg_save_policy;
175 // Convert a machine register to a machine register type, so-as to
176 // properly match spill code.
177 const int *_register_save_type;
178 // Maps from machine register to boolean; true if machine register can
179 // be holding a call argument in some signature.
180 static bool can_be_java_arg( int reg );
181 // Maps from machine register to boolean; true if machine register holds
182 // a spillable argument.
183 static bool is_spillable_arg( int reg );
184
185 // List of IfFalse or IfTrue Nodes that indicate a taken null test.
186 // List is valid in the post-matching space.
187 Node_List _null_check_tests;
188 void collect_null_checks( Node *proj, Node *orig_proj );
189 void validate_null_checks( );
190
191 Matcher();
192
193 // Get a projection node at position pos
194 Node* get_projection(uint pos) {
195 return _projection_list[pos];
196 }
197
198 // Push a projection node onto the projection list
199 void push_projection(Node* node) {
200 _projection_list.push(node);
201 }
202
203 Node* pop_projection() {
204 return _projection_list.pop();
205 }
206
207 // Number of nodes in the projection list
208 uint number_of_projections() const {
209 return _projection_list.size();
210 }
211
212 // Select instructions for entire method
213 void match();
214
215 // Helper for match
216 OptoReg::Name warp_incoming_stk_arg( VMReg reg );
217
218 // Transform, then walk. Does implicit DCE while walking.
219 // Name changed from "transform" to avoid it being virtual.
220 Node *xform( Node *old_space_node, int Nodes );
221
222 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce.
223 MachNode *match_tree( const Node *n );
224 MachNode *match_sfpt( SafePointNode *sfpt );
225 // Helper for match_sfpt
226 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call );
227
228 // Initialize first stack mask and related masks.
229 void init_first_stack_mask();
230
231 // If we should save-on-entry this register
232 bool is_save_on_entry( int reg );
233
234 // Fixup the save-on-entry registers
235 void Fixup_Save_On_Entry( );
236
237 // --- Frame handling ---
238
239 // Register number of the stack slot corresponding to the incoming SP.
240 // Per the Big Picture in the AD file, it is:
241 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2.
242 OptoReg::Name _old_SP;
243
244 // Register number of the stack slot corresponding to the highest incoming
245 // argument on the stack. Per the Big Picture in the AD file, it is:
246 // _old_SP + out_preserve_stack_slots + incoming argument size.
247 OptoReg::Name _in_arg_limit;
248
249 // Register number of the stack slot corresponding to the new SP.
250 // Per the Big Picture in the AD file, it is:
251 // _in_arg_limit + pad0
252 OptoReg::Name _new_SP;
253
254 // Register number of the stack slot corresponding to the highest outgoing
255 // argument on the stack. Per the Big Picture in the AD file, it is:
256 // _new_SP + max outgoing arguments of all calls
257 OptoReg::Name _out_arg_limit;
258
259 OptoRegPair *_parm_regs; // Array of machine registers per argument
260 RegMask *_calling_convention_mask; // Array of RegMasks per argument
261
262 // Does matcher have a match rule for this ideal node?
263 static const bool has_match_rule(int opcode);
264 static const bool _hasMatchRule[_last_opcode];
265
266 // Does matcher have a match rule for this ideal node and is the
267 // predicate (if there is one) true?
268 // NOTE: If this function is used more commonly in the future, ADLC
269 // should generate this one.
270 static const bool match_rule_supported(int opcode);
271
272 // Used to determine if we have fast l2f conversion
273 // USII has it, USIII doesn't
274 static const bool convL2FSupported(void);
275
276 // Vector width in bytes
277 static const int vector_width_in_bytes(BasicType bt);
278
279 // Limits on vector size (number of elements).
280 static const int max_vector_size(const BasicType bt);
281 static const int min_vector_size(const BasicType bt);
282 static const bool vector_size_supported(const BasicType bt, int size) {
283 return (Matcher::max_vector_size(bt) >= size &&
284 Matcher::min_vector_size(bt) <= size);
285 }
286
287 // Vector ideal reg
288 static const uint vector_ideal_reg(int len);
289 static const uint vector_shift_count_ideal_reg(int len);
290
291 // CPU supports misaligned vectors store/load.
292 static const bool misaligned_vectors_ok();
293
294 // Should original key array reference be passed to AES stubs
295 static const bool pass_original_key_for_aes();
296
297 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.)
298 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI).
299 // Depends on the details of 64-bit constant generation on the CPU.
300 static const bool isSimpleConstant64(jlong con);
301
302 // These calls are all generated by the ADLC
303
304 // TRUE - grows up, FALSE - grows down (Intel)
305 virtual bool stack_direction() const;
306
307 // Java-Java calling convention
308 // (what you use when Java calls Java)
309
310 // Alignment of stack in bytes, standard Intel word alignment is 4.
311 // Sparc probably wants at least double-word (8).
312 static uint stack_alignment_in_bytes();
313 // Alignment of stack, measured in stack slots.
314 // The size of stack slots is defined by VMRegImpl::stack_slot_size.
315 static uint stack_alignment_in_slots() {
316 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size);
317 }
318
319 // Array mapping arguments to registers. Argument 0 is usually the 'this'
320 // pointer. Registers can include stack-slots and regular registers.
321 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing );
322
323 // Convert a sig into a calling convention register layout
324 // and find interesting things about it.
325 static OptoReg::Name find_receiver( bool is_outgoing );
326 // Return address register. On Intel it is a stack-slot. On PowerPC
327 // it is the Link register. On Sparc it is r31?
328 virtual OptoReg::Name return_addr() const;
329 RegMask _return_addr_mask;
330 // Return value register. On Intel it is EAX. On Sparc i0/o0.
331 static OptoRegPair return_value(uint ideal_reg, bool is_outgoing);
332 static OptoRegPair c_return_value(uint ideal_reg, bool is_outgoing);
333 RegMask _return_value_mask;
334 // Inline Cache Register
335 static OptoReg::Name inline_cache_reg();
336 static int inline_cache_reg_encode();
337
338 // Register for DIVI projection of divmodI
339 static RegMask divI_proj_mask();
340 // Register for MODI projection of divmodI
341 static RegMask modI_proj_mask();
342
343 // Register for DIVL projection of divmodL
344 static RegMask divL_proj_mask();
345 // Register for MODL projection of divmodL
346 static RegMask modL_proj_mask();
347
348 // Use hardware DIV instruction when it is faster than
349 // a code which use multiply for division by constant.
350 static bool use_asm_for_ldiv_by_con( jlong divisor );
351
352 static const RegMask method_handle_invoke_SP_save_mask();
353
354 // Java-Interpreter calling convention
355 // (what you use when calling between compiled-Java and Interpreted-Java
356
357 // Number of callee-save + always-save registers
358 // Ignores frame pointer and "special" registers
359 static int number_of_saved_registers();
360
361 // The Method-klass-holder may be passed in the inline_cache_reg
362 // and then expanded into the inline_cache_reg and a method_oop register
363
364 static OptoReg::Name interpreter_method_oop_reg();
365 static int interpreter_method_oop_reg_encode();
366
367 static OptoReg::Name compiler_method_oop_reg();
368 static const RegMask &compiler_method_oop_reg_mask();
369 static int compiler_method_oop_reg_encode();
370
371 // Interpreter's Frame Pointer Register
372 static OptoReg::Name interpreter_frame_pointer_reg();
373
374 // Java-Native calling convention
375 // (what you use when intercalling between Java and C++ code)
376
377 // Array mapping arguments to registers. Argument 0 is usually the 'this'
378 // pointer. Registers can include stack-slots and regular registers.
379 static void c_calling_convention( BasicType*, VMRegPair *, uint );
380 // Frame pointer. The frame pointer is kept at the base of the stack
381 // and so is probably the stack pointer for most machines. On Intel
382 // it is ESP. On the PowerPC it is R1. On Sparc it is SP.
383 OptoReg::Name c_frame_pointer() const;
384 static RegMask c_frame_ptr_mask;
385
386 // !!!!! Special stuff for building ScopeDescs
387 virtual int regnum_to_fpu_offset(int regnum);
388
389 // Is this branch offset small enough to be addressed by a short branch?
390 bool is_short_branch_offset(int rule, int br_size, int offset);
391
392 // Optional scaling for the parameter to the ClearArray/CopyArray node.
393 static const bool init_array_count_is_in_bytes;
394
395 // Threshold small size (in bytes) for a ClearArray/CopyArray node.
396 // Anything this size or smaller may get converted to discrete scalar stores.
397 static const int init_array_short_size;
398
399 // Some hardware needs 2 CMOV's for longs.
400 static const int long_cmove_cost();
401
402 // Some hardware have expensive CMOV for float and double.
403 static const int float_cmove_cost();
404
405 // Should the Matcher clone shifts on addressing modes, expecting them to
406 // be subsumed into complex addressing expressions or compute them into
407 // registers? True for Intel but false for most RISCs
408 static const bool clone_shift_expressions;
409
410 static bool narrow_oop_use_complex_address();
411 static bool narrow_klass_use_complex_address();
412
413 // Generate implicit null check for narrow oops if it can fold
414 // into address expression (x64).
415 //
416 // [R12 + narrow_oop_reg<<3 + offset] // fold into address expression
417 // NullCheck narrow_oop_reg
418 //
419 // When narrow oops can't fold into address expression (Sparc) and
420 // base is not null use decode_not_null and normal implicit null check.
421 // Note, decode_not_null node can be used here since it is referenced
422 // only on non null path but it requires special handling, see
423 // collect_null_checks():
424 //
425 // decode_not_null narrow_oop_reg, oop_reg // 'shift' and 'add base'
426 // [oop_reg + offset]
427 // NullCheck oop_reg
428 //
429 // With Zero base and when narrow oops can not fold into address
430 // expression use normal implicit null check since only shift
431 // is needed to decode narrow oop.
432 //
433 // decode narrow_oop_reg, oop_reg // only 'shift'
434 // [oop_reg + offset]
435 // NullCheck oop_reg
436 //
437 inline static bool gen_narrow_oop_implicit_null_checks() {
438 return Universe::narrow_oop_use_implicit_null_checks() &&
439 (narrow_oop_use_complex_address() ||
440 Universe::narrow_oop_base() != NULL);
441 }
442
443 // Is it better to copy float constants, or load them directly from memory?
444 // Intel can load a float constant from a direct address, requiring no
445 // extra registers. Most RISCs will have to materialize an address into a
446 // register first, so they may as well materialize the constant immediately.
447 static const bool rematerialize_float_constants;
448
449 // If CPU can load and store mis-aligned doubles directly then no fixup is
450 // needed. Else we split the double into 2 integer pieces and move it
451 // piece-by-piece. Only happens when passing doubles into C code or when
452 // calling i2c adapters as the Java calling convention forces doubles to be
453 // aligned.
454 static const bool misaligned_doubles_ok;
455
456 // Does the CPU require postalloc expand (see block.cpp for description of
457 // postalloc expand)?
458 static const bool require_postalloc_expand;
459
460 // Perform a platform dependent implicit null fixup. This is needed
461 // on windows95 to take care of some unusual register constraints.
462 void pd_implicit_null_fixup(MachNode *load, uint idx);
463
464 // Advertise here if the CPU requires explicit rounding operations
465 // to implement the UseStrictFP mode.
466 static const bool strict_fp_requires_explicit_rounding;
467
468 // Are floats conerted to double when stored to stack during deoptimization?
469 static bool float_in_double();
470 // Do ints take an entire long register or just half?
471 static const bool int_in_long;
472
473 // Do the processor's shift instructions only use the low 5/6 bits
474 // of the count for 32/64 bit ints? If not we need to do the masking
475 // ourselves.
476 static const bool need_masked_shift_count;
477
478 // This routine is run whenever a graph fails to match.
479 // If it returns, the compiler should bailout to interpreter without error.
480 // In non-product mode, SoftMatchFailure is false to detect non-canonical
481 // graphs. Print a message and exit.
482 static void soft_match_failure() {
483 if( SoftMatchFailure ) return;
484 else { fatal("SoftMatchFailure is not allowed except in product"); }
485 }
486
487 // Check for a following volatile memory barrier without an
488 // intervening load and thus we don't need a barrier here. We
489 // retain the Node to act as a compiler ordering barrier.
490 static bool post_store_load_barrier(const Node* mb);
491
492 // Does n lead to an uncommon trap that can cause deoptimization?
493 static bool branches_to_uncommon_trap(const Node *n);
494
495 #ifdef ASSERT
496 void dump_old2new_map(); // machine-independent to machine-dependent
497
498 Node* find_old_node(Node* new_node) {
499 return _new2old_map[new_node->_idx];
500 }
501 #endif
502 };
503
504 #endif // SHARE_VM_OPTO_MATCHER_HPP