src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.hpp

*** 33,13 ***
--- 33,17 ---
  class LIR_Assembler;
  class ShenandoahPreBarrierStub;
  class ShenandoahLoadReferenceBarrierStub;
  class StubAssembler;
  #endif
+ #ifdef COMPILER2
+ class MachNode;
+ #endif // COMPILER2
  class StubCodeGenerator;
  
  class ShenandoahBarrierSetAssembler: public BarrierSetAssembler {
+   friend class ShenandoahCASBarrierSlowStub;
  private:
  
    void satb_write_barrier_pre(MacroAssembler* masm,
                                Register obj,
                                Register pre_val,

*** 86,8 ***
--- 90,16 ---
                          Address dst, Register val, Register tmp1, Register tmp2, Register tmp3);
    virtual void try_resolve_jobject_in_native(MacroAssembler* masm, Register jni_env,
                                               Register obj, Register tmp, Label& slowpath);
    void cmpxchg_oop(MacroAssembler* masm, Register addr, Register expected, Register new_val,
                     bool acquire, bool release, bool is_cae, Register result);
+ #ifdef COMPILER2
+ 
+   void load_ref_barrier_c2(const MachNode* node, MacroAssembler* masm, Register obj, Register addr, Register tmp, bool narrow, bool maybe_null);
+   void satb_barrier_c2(const MachNode* node, MacroAssembler* masm, Register obj, Register pre_val);
+   void card_barrier_c2(const MachNode* node, MacroAssembler* masm, Register addr, Register tmp);
+   void cmpxchg_oop_c2(const MachNode* node, MacroAssembler* masm, Register addr, Register expected, Register new_val, Register result,
+                       bool acquire, bool release, bool weak, bool is_cae);
+ #endif
  };
  
  #endif // CPU_AARCH64_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_AARCH64_HPP