1 /*
 2  * Copyright (c) 2026, Oracle and/or its affiliates. All rights reserved.
 3  * Copyright (c) 2018, 2021, Red Hat, Inc. All rights reserved.
 4  * Copyright Amazon.com Inc. or its affiliates. All Rights Reserved.
 5  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 6  *
 7  * This code is free software; you can redistribute it and/or modify it
 8  * under the terms of the GNU General Public License version 2 only, as
 9  * published by the Free Software Foundation.
10  *
11  * This code is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14  * version 2 for more details (a copy is included in the LICENSE file that
15  * accompanied this code).
16  *
17  * You should have received a copy of the GNU General Public License version
18  * 2 along with this work; if not, write to the Free Software Foundation,
19  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20  *
21  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22  * or visit www.oracle.com if you need additional information or have any
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25  */
26 
27 #ifndef CPU_AARCH64_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_AARCH64_HPP
28 #define CPU_AARCH64_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_AARCH64_HPP
29 
30 #include "asm/macroAssembler.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
33 #ifdef COMPILER1
34 class LIR_Assembler;
35 class ShenandoahPreBarrierStub;
36 class ShenandoahLoadReferenceBarrierStub;
37 class StubAssembler;
38 #endif
39 #ifdef COMPILER2
40 class MachNode;
41 #endif // COMPILER2
42 class StubCodeGenerator;
43 
44 class ShenandoahBarrierSetAssembler: public BarrierSetAssembler {
45 private:
46 
47   void satb_barrier(MacroAssembler* masm,
48                     Register obj,
49                     Register pre_val,
50                     Register thread,
51                     Register tmp1,
52                     Register tmp2);
53 
54   void card_barrier(MacroAssembler* masm, Register obj);
55 
56   void resolve_forward_pointer(MacroAssembler* masm, Register dst, Register tmp = noreg);
57   void resolve_forward_pointer_not_null(MacroAssembler* masm, Register dst, Register tmp = noreg);
58   void load_reference_barrier(MacroAssembler* masm, Register dst, Address load_addr, DecoratorSet decorators);
59 
60   void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators,
61                                         Register start, Register count,
62                                         Register scratch);
63 
64 public:
65   virtual NMethodPatchingType nmethod_patching_type() { return NMethodPatchingType::conc_instruction_and_data_patch; }
66 
67   virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop,
68                                   Register src, Register dst, Register count, RegSet saved_regs);
69   virtual void arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop,
70                                   Register start, Register count, Register tmp);
71   virtual void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
72                        Register dst, Address src, Register tmp1, Register tmp2);
73   virtual void store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
74                         Address dst, Register val, Register tmp1, Register tmp2, Register tmp3);
75   virtual void try_resolve_jobject_in_native(MacroAssembler* masm, Register jni_env,
76                                              Register obj, Register tmp, Label& slowpath);
77   virtual void try_peek_weak_handle_in_nmethod(MacroAssembler* masm, Register weak_handle, Register obj,
78                                                Register tmp, Label& slow_path);
79   void cmpxchg_oop(MacroAssembler* masm, Register addr, Register expected, Register new_val,
80                    bool acquire, bool release, bool is_cae, Register result);
81 
82 #ifdef COMPILER1
83   void gen_pre_barrier_stub(LIR_Assembler* ce, ShenandoahPreBarrierStub* stub);
84   void gen_load_reference_barrier_stub(LIR_Assembler* ce, ShenandoahLoadReferenceBarrierStub* stub);
85   void generate_c1_pre_barrier_runtime_stub(StubAssembler* sasm);
86   void generate_c1_load_reference_barrier_runtime_stub(StubAssembler* sasm, DecoratorSet decorators);
87 #endif
88 
89 #ifdef COMPILER2
90   // Entry points from Matcher
91   void load_c2(const MachNode* node, MacroAssembler* masm, Register dst, Address addr, Register tmp1, Register tmp2, bool is_narrow, bool is_acquire);
92   void store_c2(const MachNode* node, MacroAssembler* masm, Address dst, bool dst_narrow, Register src, bool src_narrow, Register tmp1, Register tmp2, Register tmp3, bool is_volatile);
93   void compare_and_set_c2(const MachNode* node, MacroAssembler* masm, Register res, Register addr, Register oldval,
94       Register newval, Register tmp1, Register tmp2, Register tmp3, bool exchange, bool narrow, bool weak, bool acquire);
95   void get_and_set_c2(const MachNode* node, MacroAssembler* masm, Register preval, Register newval, Register addr, Register tmp1, Register tmp2, Register tmp3, bool acquire);
96 #endif
97 };
98 
99 #endif // CPU_AARCH64_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_AARCH64_HPP