1 /*
2 * Copyright (c) 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2018, 2019, Red Hat, Inc. All rights reserved.
4 * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #ifndef CPU_RISCV_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_RISCV_HPP
28 #define CPU_RISCV_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_RISCV_HPP
29
30 #include "asm/macroAssembler.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
33
34 #ifdef COMPILER1
35 class LIR_Assembler;
36 class ShenandoahPreBarrierStub;
37 class ShenandoahLoadReferenceBarrierStub;
38 class StubAssembler;
39 #endif
40 class StubCodeGenerator;
41
42 class ShenandoahBarrierSetAssembler: public BarrierSetAssembler {
43 private:
44
45 void satb_barrier(MacroAssembler* masm,
46 Register obj,
47 Register pre_val,
48 Register thread,
49 Register tmp1,
50 Register tmp2,
51 bool tosca_live,
52 bool expand_call);
53
54 void card_barrier(MacroAssembler* masm, Register obj);
55
56 void resolve_forward_pointer(MacroAssembler* masm, Register dst, Register tmp = noreg);
57 void resolve_forward_pointer_not_null(MacroAssembler* masm, Register dst, Register tmp = noreg);
58 void load_reference_barrier(MacroAssembler* masm, Register dst, Address load_addr, DecoratorSet decorators);
59
60 void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators,
61 Register start, Register count,
62 Register tmp);
63
64 public:
65
66 virtual NMethodPatchingType nmethod_patching_type() { return NMethodPatchingType::conc_instruction_and_data_patch; }
67
68 #ifdef COMPILER1
69 void gen_pre_barrier_stub(LIR_Assembler* ce, ShenandoahPreBarrierStub* stub);
70 void gen_load_reference_barrier_stub(LIR_Assembler* ce, ShenandoahLoadReferenceBarrierStub* stub);
71 void generate_c1_pre_barrier_runtime_stub(StubAssembler* sasm);
72 void generate_c1_load_reference_barrier_runtime_stub(StubAssembler* sasm, DecoratorSet decorators);
73 #endif
74
75 virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop,
76 Register src, Register dst, Register count, RegSet saved_regs);
77
78 virtual void arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop,
79 Register start, Register count, Register tmp);
80
81 virtual void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
82 Register dst, Address src, Register tmp1, Register tmp2);
83 virtual void store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
84 Address dst, Register val, Register tmp1, Register tmp2, Register tmp3);
85
86 virtual void try_resolve_jobject_in_native(MacroAssembler* masm, Register jni_env,
87 Register obj, Register tmp, Label& slowpath);
88 #ifdef COMPILER2
89 virtual void try_resolve_weak_handle_in_c2(MacroAssembler* masm, Register obj, Register tmp, Label& slow_path);
90 #endif
91 void cmpxchg_oop(MacroAssembler* masm, Register addr, Register expected, Register new_val,
92 Assembler::Aqrl acquire, Assembler::Aqrl release, bool is_cae, Register result);
93 };
94
95 #endif // CPU_RISCV_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_RISCV_HPP