1 /*
 2  * Copyright (c) 2026, Oracle and/or its affiliates. All rights reserved.
 3  * Copyright (c) 2018, 2021, Red Hat, Inc. All rights reserved.
 4  * Copyright Amazon.com Inc. or its affiliates. All Rights Reserved.
 5  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 6  *
 7  * This code is free software; you can redistribute it and/or modify it
 8  * under the terms of the GNU General Public License version 2 only, as
 9  * published by the Free Software Foundation.
10  *
11  * This code is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14  * version 2 for more details (a copy is included in the LICENSE file that
15  * accompanied this code).
16  *
17  * You should have received a copy of the GNU General Public License version
18  * 2 along with this work; if not, write to the Free Software Foundation,
19  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20  *
21  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22  * or visit www.oracle.com if you need additional information or have any
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24  *
25  */
26 
27 #ifndef CPU_X86_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_X86_HPP
28 #define CPU_X86_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_X86_HPP
29 
30 #include "asm/macroAssembler.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
33 
34 #ifdef COMPILER1
35 class LIR_Assembler;
36 class ShenandoahPreBarrierStub;
37 class ShenandoahLoadReferenceBarrierStub;
38 class StubAssembler;
39 #endif
40 class StubCodeGenerator;
41 
42 class ShenandoahBarrierSetAssembler: public BarrierSetAssembler {
43 private:
44 
45   void satb_barrier(MacroAssembler* masm,
46                     Register obj,
47                     Register pre_val,
48                     Register tmp,
49                     bool tosca_live,
50                     bool expand_call);
51 
52   void card_barrier(MacroAssembler* masm, Register obj);
53 
54   void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators,
55                                         Register addr, Register count,
56                                         Register tmp);
57 
58 public:
59 #ifdef COMPILER1
60   void gen_pre_barrier_stub(LIR_Assembler* ce, ShenandoahPreBarrierStub* stub);
61   void gen_load_reference_barrier_stub(LIR_Assembler* ce, ShenandoahLoadReferenceBarrierStub* stub);
62   void generate_c1_pre_barrier_runtime_stub(StubAssembler* sasm);
63   void generate_c1_load_reference_barrier_runtime_stub(StubAssembler* sasm, DecoratorSet decorators);
64 #endif
65 
66   void load_reference_barrier(MacroAssembler* masm, Register dst, Address src, DecoratorSet decorators);
67 
68   void cmpxchg_oop(MacroAssembler* masm,
69                    Register res, Address addr, Register oldval, Register newval,
70                    bool exchange, Register tmp1, Register tmp2);
71   virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
72                                   Register src, Register dst, Register count);
73   virtual void arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
74                                   Register src, Register dst, Register count);
75   virtual void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
76                        Register dst, Address src, Register tmp1);
77   virtual void store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
78                         Address dst, Register val, Register tmp1, Register tmp2, Register tmp3);
79   virtual void try_resolve_jobject_in_native(MacroAssembler* masm, Register jni_env,
80                                              Register obj, Register tmp, Label& slowpath);
81 #ifdef COMPILER2
82   virtual void try_resolve_weak_handle_in_c2(MacroAssembler* masm, Register obj, Label& slowpath);
83 #endif // COMPILER2
84 };
85 
86 #endif // CPU_X86_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_X86_HPP