1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef SHARE_OPTO_MACHNODE_HPP
26 #define SHARE_OPTO_MACHNODE_HPP
27
28 #include "opto/c2_MacroAssembler.hpp"
29 #include "opto/callnode.hpp"
30 #include "opto/constantTable.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/multnode.hpp"
33 #include "opto/node.hpp"
34 #include "opto/regmask.hpp"
35 #include "utilities/growableArray.hpp"
36
37 class BufferBlob;
38 class JVMState;
39 class MachCallDynamicJavaNode;
40 class MachCallJavaNode;
41 class MachCallLeafNode;
42 class MachCallNode;
43 class MachCallRuntimeNode;
44 class MachCallStaticJavaNode;
45 class MachEpilogNode;
46 class MachIfNode;
47 class MachNullCheckNode;
48 class MachOper;
49 class MachProjNode;
50 class MachPrologNode;
51 class MachReturnNode;
52 class MachSafePointNode;
53 class MachSpillCopyNode;
54 class Matcher;
55 class PhaseRegAlloc;
56 class RegMask;
57 class State;
58
59 //---------------------------MachOper------------------------------------------
60 class MachOper : public ResourceObj {
61 public:
62 // Allocate right next to the MachNodes in the same arena
63 void *operator new(size_t x) throw() {
64 Compile* C = Compile::current();
65 return C->node_arena()->AmallocWords(x);
66 }
67
68 // Opcode
69 virtual uint opcode() const = 0;
70
71 // Number of input edges.
72 // Generally at least 1
73 virtual uint num_edges() const { return 1; }
74 // Array of Register masks
75 virtual const RegMask *in_RegMask(int index) const;
76
77 // Methods to output the encoding of the operand
78
79 // Negate conditional branches. Error for non-branch Nodes
80 virtual void negate();
81
82 // Return the value requested
83 // result register lookup, corresponding to int_format
84 virtual int reg(PhaseRegAlloc *ra_, const Node *node) const;
85 // input register lookup, corresponding to ext_format
86 virtual int reg(PhaseRegAlloc *ra_, const Node *node, int idx) const;
87
88 // helpers for MacroAssembler generation from ADLC
89 Register as_Register(PhaseRegAlloc *ra_, const Node *node) const {
90 return ::as_Register(reg(ra_, node));
91 }
92 Register as_Register(PhaseRegAlloc *ra_, const Node *node, int idx) const {
93 return ::as_Register(reg(ra_, node, idx));
94 }
95 FloatRegister as_FloatRegister(PhaseRegAlloc *ra_, const Node *node) const {
96 return ::as_FloatRegister(reg(ra_, node));
97 }
98 FloatRegister as_FloatRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
99 return ::as_FloatRegister(reg(ra_, node, idx));
100 }
101
102 #if defined(AMD64)
103 KRegister as_KRegister(PhaseRegAlloc *ra_, const Node *node) const {
104 return ::as_KRegister(reg(ra_, node));
105 }
106 KRegister as_KRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
107 return ::as_KRegister(reg(ra_, node, idx));
108 }
109 XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node) const {
110 return ::as_XMMRegister(reg(ra_, node));
111 }
112 XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
113 return ::as_XMMRegister(reg(ra_, node, idx));
114 }
115 #endif
116 // CondRegister reg converter
117 #if defined(PPC64)
118 ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node) const {
119 return ::as_ConditionRegister(reg(ra_, node));
120 }
121 ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
122 return ::as_ConditionRegister(reg(ra_, node, idx));
123 }
124 VectorRegister as_VectorRegister(PhaseRegAlloc *ra_, const Node *node) const {
125 return ::as_VectorRegister(reg(ra_, node));
126 }
127 VectorRegister as_VectorRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
128 return ::as_VectorRegister(reg(ra_, node, idx));
129 }
130 VectorSRegister as_VectorSRegister(PhaseRegAlloc *ra_, const Node *node) const {
131 return ::as_VectorSRegister(reg(ra_, node));
132 }
133 VectorSRegister as_VectorSRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
134 return ::as_VectorSRegister(reg(ra_, node, idx));
135 }
136 #endif
137 #if defined(S390)
138 VectorRegister as_VectorRegister(PhaseRegAlloc *ra_, const Node *node) const {
139 return ::as_VectorRegister(reg(ra_, node));
140 }
141 VectorRegister as_VectorRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
142 return ::as_VectorRegister(reg(ra_, node, idx));
143 }
144 #endif
145 #if defined(AARCH64)
146 PRegister as_PRegister(PhaseRegAlloc* ra_, const Node* node) const {
147 return ::as_PRegister(reg(ra_, node));
148 }
149 PRegister as_PRegister(PhaseRegAlloc* ra_, const Node* node, int idx) const {
150 return ::as_PRegister(reg(ra_, node, idx));
151 }
152 #endif
153
154 virtual intptr_t constant() const;
155 virtual relocInfo::relocType constant_reloc() const;
156 virtual jdouble constantD() const;
157 virtual jfloat constantF() const;
158 virtual jlong constantL() const;
159 virtual jshort constantH() const;
160 virtual TypeOopPtr *oop() const;
161 virtual int ccode() const;
162 // A zero, default, indicates this value is not needed.
163 // May need to lookup the base register, as done in int_ and ext_format
164 virtual int base (PhaseRegAlloc *ra_, const Node *node, int idx) const;
165 virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const;
166 virtual int scale() const;
167 // Parameters needed to support MEMORY_INTERFACE access to stackSlot
168 virtual int disp (PhaseRegAlloc *ra_, const Node *node, int idx) const;
169 // Check for PC-Relative displacement
170 virtual relocInfo::relocType disp_reloc() const;
171 virtual int constant_disp() const; // usu. 0, may return Type::OffsetBot
172 virtual int base_position() const; // base edge position, or -1
173 virtual int index_position() const; // index edge position, or -1
174
175 // Access the TypeKlassPtr of operands with a base==RegI and disp==RegP
176 // Only returns non-null value for x86_32.ad's indOffset32X
177 virtual const TypePtr *disp_as_type() const { return nullptr; }
178
179 // Return the label
180 virtual Label *label() const;
181
182 // Return the method's address
183 virtual intptr_t method() const;
184
185 // Hash and compare over operands are currently identical
186 virtual uint hash() const;
187 virtual bool cmp( const MachOper &oper ) const;
188
189 // Virtual clone, since I do not know how big the MachOper is.
190 virtual MachOper *clone() const = 0;
191
192 // Return ideal Type from simple operands. Fail for complex operands.
193 virtual const Type *type() const;
194
195 // Set an integer offset if we have one, or error otherwise
196 virtual void set_con( jint c0 ) { ShouldNotReachHere(); }
197
198 #ifndef PRODUCT
199 // Return name of operand
200 virtual const char *Name() const { return "???";}
201
202 // Methods to output the text version of the operand
203 virtual void int_format(PhaseRegAlloc *,const MachNode *node, outputStream *st) const = 0;
204 virtual void ext_format(PhaseRegAlloc *,const MachNode *node,int idx, outputStream *st) const=0;
205
206 virtual void dump_spec(outputStream *st) const; // Print per-operand info
207
208 // Check whether o is a valid oper.
209 static bool notAnOper(const MachOper *o) {
210 if (o == nullptr) return true;
211 if (((intptr_t)o & 1) != 0) return true;
212 if (*(address*)o == badAddress) return true; // kill by Node::destruct
213 return false;
214 }
215 #endif // !PRODUCT
216 };
217
218 //------------------------------MachNode---------------------------------------
219 // Base type for all machine specific nodes. All node classes generated by the
220 // ADLC inherit from this class.
221 class MachNode : public Node {
222 public:
223 MachNode() : Node((uint)0), _barrier(0), _num_opnds(0), _opnds(nullptr) {
224 init_class_id(Class_Mach);
225 }
226 // Required boilerplate
227 virtual uint size_of() const { return sizeof(MachNode); }
228 virtual int Opcode() const; // Always equal to MachNode
229 virtual uint rule() const = 0; // Machine-specific opcode
230 // Number of inputs which come before the first operand.
231 // Generally at least 1, to skip the Control input
232 virtual uint oper_input_base() const { return 1; }
233 // Position of constant base node in node's inputs. -1 if
234 // no constant base node input.
235 virtual uint mach_constant_base_node_input() const { return (uint)-1; }
236
237 uint8_t barrier_data() const { return _barrier; }
238 void set_barrier_data(uint8_t data) { _barrier = data; }
239
240 void set_memory_order(MemNode::MemOrd mo) { _mo = mo; }
241 MemNode::MemOrd memory_order() const { return _mo; }
242
243 void set_trailing_membar(Node* n) {
244 if (n->is_Store()) {
245 _has_trailing_membar = n->as_Store()->trailing_membar() != nullptr;
246 } else if (n->is_LoadStore()) {
247 _has_trailing_membar = n->as_LoadStore()->trailing_membar() != nullptr;
248 } else {
249 _has_trailing_membar = false;
250 }
251 }
252
253 bool has_trailing_membar() const { return _has_trailing_membar; }
254
255 // Copy index, inputs, and operands to a new version of the instruction.
256 // Called from cisc_version() and short_branch_version().
257 void fill_new_machnode(MachNode *n) const;
258
259 // Return an equivalent instruction using memory for cisc_operand position
260 virtual MachNode *cisc_version(int offset);
261 // Modify this instruction's register mask to use stack version for cisc_operand
262 virtual void use_cisc_RegMask();
263
264 // Support for short branches
265 bool may_be_short_branch() const { return (flags() & Flag_may_be_short_branch) != 0; }
266
267 // Avoid back to back some instructions on some CPUs.
268 enum AvoidBackToBackFlag { AVOID_NONE = 0,
269 AVOID_BEFORE = Flag_avoid_back_to_back_before,
270 AVOID_AFTER = Flag_avoid_back_to_back_after,
271 AVOID_BEFORE_AND_AFTER = AVOID_BEFORE | AVOID_AFTER };
272
273 bool avoid_back_to_back(AvoidBackToBackFlag flag_value) const {
274 return (flags() & flag_value) == flag_value;
275 }
276
277 // instruction implemented with a call
278 bool has_call() const { return (flags() & Flag_has_call) != 0; }
279
280 // First index in _in[] corresponding to operand, or -1 if there is none
281 int operand_index(uint operand) const;
282 int operand_index(const MachOper *oper) const;
283 int operand_index(Node* m) const;
284 int operand_num_edges(uint operand) const;
285
286 // Register class input is expected in
287 virtual const RegMask &in_RegMask(uint) const;
288
289 // cisc-spillable instructions redefine for use by in_RegMask
290 virtual const RegMask *cisc_RegMask() const { return nullptr; }
291
292 // If this instruction is a 2-address instruction, then return the
293 // index of the input which must match the output. Not necessary
294 // for instructions which bind the input and output register to the
295 // same singleton register (e.g., Intel IDIV which binds AX to be
296 // both an input and an output). It is necessary when the input and
297 // output have choices - but they must use the same choice.
298 virtual uint two_adr( ) const { return 0; }
299
300 // The GC might require some barrier metadata for machine code emission.
301 uint8_t _barrier;
302
303 MemNode::MemOrd _mo;
304
305 bool _has_trailing_membar;
306
307
308 // Array of complex operand pointers. Each corresponds to zero or
309 // more leafs. Must be set by MachNode constructor to point to an
310 // internal array of MachOpers. The MachOper array is sized by
311 // specific MachNodes described in the ADL.
312 uint16_t _num_opnds;
313 MachOper **_opnds;
314 uint16_t num_opnds() const { return _num_opnds; }
315
316 // Emit bytes using C2_MacroAssembler
317 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
318 // Expand node after register allocation.
319 // Node is replaced by several nodes in the postalloc expand phase.
320 // Corresponding methods are generated for nodes if they specify
321 // postalloc_expand. See block.cpp for more documentation.
322 virtual bool requires_postalloc_expand() const { return false; }
323 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
324 // Size of instruction in bytes
325 virtual uint size(PhaseRegAlloc *ra_) const;
326 // Helper function that computes size by emitting code
327 virtual uint emit_size(PhaseRegAlloc *ra_) const;
328
329 // Return the alignment required (in units of relocInfo::addr_unit())
330 // for this instruction (must be a power of 2)
331 int pd_alignment_required() const;
332 virtual int alignment_required() const { return pd_alignment_required(); }
333
334 // Return the padding (in bytes) to be emitted before this
335 // instruction to properly align it.
336 virtual int compute_padding(int current_offset) const;
337
338 // Return number of relocatable values contained in this instruction
339 virtual int reloc() const { return 0; }
340
341 // Return number of words used for double constants in this instruction
342 virtual int ins_num_consts() const { return 0; }
343
344 // Hash and compare over operands. Used to do GVN on machine Nodes.
345 virtual uint hash() const;
346 virtual bool cmp( const Node &n ) const;
347
348 // Expand method for MachNode, replaces nodes representing pseudo
349 // instructions with a set of nodes which represent real machine
350 // instructions and compute the same value.
351 virtual MachNode *Expand( State *, Node_List &proj_list, Node* mem ) { return this; }
352
353 // Bottom_type call; value comes from operand0
354 virtual const class Type *bottom_type() const { return _opnds[0]->type(); }
355 virtual uint ideal_reg() const {
356 const Type *t = _opnds[0]->type();
357 if (t == TypeInt::CC) {
358 return Op_RegFlags;
359 } else {
360 return t->ideal_reg();
361 }
362 }
363
364 // If this is a memory op, return the base pointer and fixed offset.
365 // If there are no such, return null. If there are multiple addresses
366 // or the address is indeterminate (rare cases) then return (Node*)-1,
367 // which serves as node bottom.
368 // If the offset is not statically determined, set it to Type::OffsetBot.
369 // This method is free to ignore stack slots if that helps.
370 #define TYPE_PTR_SENTINAL ((const TypePtr*)-1)
371 // Passing TYPE_PTR_SENTINAL as adr_type asks for computation of the adr_type if possible
372 const Node* get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const;
373
374 // Helper for get_base_and_disp: find the base and index input nodes.
375 // Returns the MachOper as determined by memory_operand(), for use, if
376 // needed by the caller. If (MachOper *)-1 is returned, base and index
377 // are set to NodeSentinel. If null is returned, base and
378 // index are set to null.
379 const MachOper* memory_inputs(Node* &base, Node* &index) const;
380
381 // Helper for memory_inputs: Which operand carries the necessary info?
382 // By default, returns null, which means there is no such operand.
383 // If it returns (MachOper*)-1, this means there are multiple memories.
384 virtual const MachOper* memory_operand() const { return nullptr; }
385
386 // Call "get_base_and_disp" to decide which category of memory is used here.
387 virtual const class TypePtr *adr_type() const;
388
389 // Apply peephole rule(s) to this instruction
390 virtual int peephole(Block *block, int block_index, PhaseCFG* cfg_, PhaseRegAlloc *ra_);
391
392 // Top-level ideal Opcode matched
393 virtual int ideal_Opcode() const { return Op_Node; }
394
395 // Adds the label for the case
396 virtual void add_case_label( int switch_val, Label* blockLabel);
397
398 // Set the absolute address for methods
399 virtual void method_set( intptr_t addr );
400
401 // Should we clone rather than spill this instruction?
402 bool rematerialize() const;
403
404 bool is_CAS(bool maybe_volatile) const;
405
406 // Get the pipeline info
407 static const Pipeline *pipeline_class();
408 virtual const Pipeline *pipeline() const;
409
410 // Returns true if this node is a check that can be implemented with a trap.
411 virtual bool is_TrapBasedCheckNode() const { return false; }
412
413 // Whether this node is expanded during code emission into a sequence of
414 // instructions and the first instruction can perform an implicit null check.
415 virtual bool is_late_expanded_null_check_candidate() const {
416 return false;
417 }
418
419 void set_removed() { add_flag(Flag_is_removed_by_peephole); }
420 bool get_removed() { return (flags() & Flag_is_removed_by_peephole) != 0; }
421
422 #ifndef PRODUCT
423 virtual const char *Name() const = 0; // Machine-specific name
424 virtual void dump_spec(outputStream *st) const; // Print per-node info
425 void dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual
426 #endif
427 };
428
429 //------------------------------MachIdealNode----------------------------
430 // Machine specific versions of nodes that must be defined by user.
431 // These are not converted by matcher from ideal nodes to machine nodes
432 // but are inserted into the code by the compiler.
433 class MachIdealNode : public MachNode {
434 public:
435 MachIdealNode( ) {}
436
437 // Define the following defaults for non-matched machine nodes
438 virtual uint oper_input_base() const { return 0; }
439 virtual uint rule() const { return 9999999; }
440 virtual const class Type *bottom_type() const { return _opnds == nullptr ? Type::CONTROL : MachNode::bottom_type(); }
441 };
442
443 //------------------------------MachTypeNode----------------------------
444 // Machine Nodes that need to retain a known Type.
445 class MachTypeNode : public MachNode {
446 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
447 public:
448 MachTypeNode( ) {}
449 const Type *_bottom_type;
450
451 virtual const class Type *bottom_type() const { return _bottom_type; }
452 #ifndef PRODUCT
453 virtual void dump_spec(outputStream *st) const;
454 #endif
455 };
456
457 //------------------------------MachBreakpointNode----------------------------
458 // Machine breakpoint or interrupt Node
459 class MachBreakpointNode : public MachIdealNode {
460 public:
461 MachBreakpointNode( ) {}
462 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
463 virtual uint size(PhaseRegAlloc *ra_) const;
464
465 #ifndef PRODUCT
466 virtual const char *Name() const { return "Breakpoint"; }
467 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
468 #endif
469 };
470
471 //------------------------------MachConstantBaseNode--------------------------
472 // Machine node that represents the base address of the constant table.
473 class MachConstantBaseNode : public MachIdealNode {
474 public:
475 static const RegMask& _out_RegMask; // We need the out_RegMask statically in MachConstantNode::in_RegMask().
476
477 public:
478 MachConstantBaseNode() : MachIdealNode() {
479 init_class_id(Class_MachConstantBase);
480 }
481 virtual const class Type* bottom_type() const { return TypeRawPtr::NOTNULL; }
482 virtual uint ideal_reg() const { return Op_RegP; }
483 virtual uint oper_input_base() const { return 1; }
484
485 virtual bool requires_postalloc_expand() const;
486 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
487
488 virtual void emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const;
489 virtual uint size(PhaseRegAlloc* ra_) const;
490
491 static const RegMask& static_out_RegMask() { return _out_RegMask; }
492 virtual const RegMask& out_RegMask() const { return static_out_RegMask(); }
493
494 #ifndef PRODUCT
495 virtual const char* Name() const { return "MachConstantBaseNode"; }
496 virtual void format(PhaseRegAlloc*, outputStream* st) const;
497 #endif
498 };
499
500 //------------------------------MachConstantNode-------------------------------
501 // Machine node that holds a constant which is stored in the constant table.
502 class MachConstantNode : public MachTypeNode {
503 protected:
504 ConstantTable::Constant _constant; // This node's constant.
505
506 public:
507 MachConstantNode() : MachTypeNode() {
508 init_class_id(Class_MachConstant);
509 }
510
511 virtual void eval_constant(Compile* C) {
512 #ifdef ASSERT
513 tty->print("missing MachConstantNode eval_constant function: ");
514 dump();
515 #endif
516 ShouldNotCallThis();
517 }
518
519 virtual const RegMask &in_RegMask(uint idx) const {
520 if (idx == mach_constant_base_node_input())
521 return MachConstantBaseNode::static_out_RegMask();
522 return MachNode::in_RegMask(idx);
523 }
524
525 // Input edge of MachConstantBaseNode.
526 virtual uint mach_constant_base_node_input() const { return req() - 1; }
527
528 int constant_offset();
529 int constant_offset() const { return ((MachConstantNode*) this)->constant_offset(); }
530 // Unchecked version to avoid assertions in debug output.
531 int constant_offset_unchecked() const;
532 virtual uint size_of() const { return sizeof(MachConstantNode); }
533 };
534
535 //------------------------------MachUEPNode-----------------------------------
536 // Machine Unvalidated Entry Point Node
537 class MachUEPNode : public MachIdealNode {
538 public:
539 MachUEPNode( ) {}
540 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
541 virtual uint size(PhaseRegAlloc *ra_) const;
542
543 #ifndef PRODUCT
544 virtual const char *Name() const { return "Unvalidated-Entry-Point"; }
545 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
546 #endif
547 };
548
549 //------------------------------MachPrologNode--------------------------------
550 // Machine function Prolog Node
551 class MachPrologNode : public MachIdealNode {
552 public:
553 MachPrologNode( ) {}
554 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
555 virtual uint size(PhaseRegAlloc *ra_) const;
556 virtual int reloc() const;
557
558 #ifndef PRODUCT
559 virtual const char *Name() const { return "Prolog"; }
560 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
561 #endif
562 };
563
564 //------------------------------MachEpilogNode--------------------------------
565 // Machine function Epilog Node
566 class MachEpilogNode : public MachIdealNode {
567 private:
568 bool _do_polling;
569 public:
570 MachEpilogNode(bool do_poll = false) : _do_polling(do_poll) {}
571 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
572 virtual uint size(PhaseRegAlloc *ra_) const;
573 virtual int reloc() const;
574 virtual const Pipeline *pipeline() const;
575 virtual uint size_of() const { return sizeof(MachEpilogNode); }
576 bool do_polling() const { return _do_polling; }
577
578 #ifndef PRODUCT
579 virtual const char *Name() const { return "Epilog"; }
580 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
581 #endif
582 };
583
584 //------------------------------MachNopNode-----------------------------------
585 // Machine function Nop Node
586 class MachNopNode : public MachIdealNode {
587 private:
588 int _count;
589 public:
590 MachNopNode( ) : _count(1) {}
591 MachNopNode( int count ) : _count(count) {}
592 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
593 virtual uint size(PhaseRegAlloc *ra_) const;
594
595 virtual const class Type *bottom_type() const { return Type::CONTROL; }
596
597 virtual int ideal_Opcode() const { return Op_Con; } // bogus; see output.cpp
598 virtual const Pipeline *pipeline() const;
599 virtual uint size_of() const { return sizeof(MachNopNode); }
600 #ifndef PRODUCT
601 virtual const char *Name() const { return "Nop"; }
602 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
603 virtual void dump_spec(outputStream *st) const { } // No per-operand info
604 #endif
605 };
606
607 //------------------------------MachSpillCopyNode------------------------------
608 // Machine SpillCopy Node. Copies 1 or 2 words from any location to any
609 // location (stack or register).
610 class MachSpillCopyNode : public MachIdealNode {
611 public:
612 enum SpillType {
613 TwoAddress, // Inserted when coalescing of a two-address-instruction node and its input fails
614 PhiInput, // Inserted when coalescing of a phi node and its input fails
615 DebugUse, // Inserted as debug info spills to safepoints in non-frequent blocks
616 LoopPhiInput, // Pre-split compares of loop-phis
617 Definition, // An lrg marked as spilled will be spilled to memory right after its definition,
618 // if in high pressure region or the lrg is bound
619 RegToReg, // A register to register move
620 RegToMem, // A register to memory move
621 MemToReg, // A memory to register move
622 PhiLocationDifferToInputLocation, // When coalescing phi nodes in PhaseChaitin::Split(), a move spill is inserted if
623 // the phi and its input resides at different locations (i.e. reg or mem)
624 BasePointerToMem, // Spill base pointer to memory at safepoint
625 InputToRematerialization, // When rematerializing a node we stretch the inputs live ranges, and they might be
626 // stretched beyond a new definition point, therefore we split out new copies instead
627 CallUse, // Spill use at a call
628 Bound // An lrg marked as spill that is bound and needs to be spilled at a use
629 };
630 private:
631 const RegMask *_in; // RegMask for input
632 const RegMask *_out; // RegMask for output
633 const Type *_type;
634 const SpillType _spill_type;
635 public:
636 MachSpillCopyNode(SpillType spill_type, Node *n, const RegMask &in, const RegMask &out ) :
637 MachIdealNode(), _in(&in), _out(&out), _type(n->bottom_type()), _spill_type(spill_type) {
638 init_class_id(Class_MachSpillCopy);
639 init_flags(Flag_is_Copy);
640 add_req(nullptr);
641 add_req(n);
642 }
643 virtual uint size_of() const { return sizeof(*this); }
644 void set_out_RegMask(const RegMask &out) { _out = &out; }
645 void set_in_RegMask(const RegMask &in) { _in = ∈ }
646 virtual const RegMask &out_RegMask() const { return *_out; }
647 virtual const RegMask &in_RegMask(uint) const { return *_in; }
648 virtual const class Type *bottom_type() const { return _type; }
649 virtual uint ideal_reg() const { return _type->ideal_reg(); }
650 virtual uint oper_input_base() const { return 1; }
651 uint implementation( C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const;
652
653 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
654 virtual uint size(PhaseRegAlloc *ra_) const;
655
656
657 #ifndef PRODUCT
658 static const char *spill_type(SpillType st) {
659 switch (st) {
660 case TwoAddress:
661 return "TwoAddressSpillCopy";
662 case PhiInput:
663 return "PhiInputSpillCopy";
664 case DebugUse:
665 return "DebugUseSpillCopy";
666 case LoopPhiInput:
667 return "LoopPhiInputSpillCopy";
668 case Definition:
669 return "DefinitionSpillCopy";
670 case RegToReg:
671 return "RegToRegSpillCopy";
672 case RegToMem:
673 return "RegToMemSpillCopy";
674 case MemToReg:
675 return "MemToRegSpillCopy";
676 case PhiLocationDifferToInputLocation:
677 return "PhiLocationDifferToInputLocationSpillCopy";
678 case BasePointerToMem:
679 return "BasePointerToMemSpillCopy";
680 case InputToRematerialization:
681 return "InputToRematerializationSpillCopy";
682 case CallUse:
683 return "CallUseSpillCopy";
684 case Bound:
685 return "BoundSpillCopy";
686 default:
687 assert(false, "Must have valid spill type");
688 return "MachSpillCopy";
689 }
690 }
691
692 virtual const char *Name() const {
693 return spill_type(_spill_type);
694 }
695
696 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
697 #endif
698 };
699
700 // MachMergeNode is similar to a PhiNode in a sense it merges multiple values,
701 // however it doesn't have a control input and is more like a MergeMem.
702 // It is inserted after the register allocation is done to ensure that nodes use single
703 // definition of a multidef lrg in a block.
704 class MachMergeNode : public MachIdealNode {
705 public:
706 MachMergeNode(Node *n1) {
707 init_class_id(Class_MachMerge);
708 add_req(nullptr);
709 add_req(n1);
710 }
711 virtual const RegMask &out_RegMask() const { return in(1)->out_RegMask(); }
712 virtual const RegMask &in_RegMask(uint idx) const { return in(1)->in_RegMask(idx); }
713 virtual const class Type *bottom_type() const { return in(1)->bottom_type(); }
714 virtual uint ideal_reg() const { return bottom_type()->ideal_reg(); }
715 virtual uint oper_input_base() const { return 1; }
716 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const { }
717 virtual uint size(PhaseRegAlloc *ra_) const { return 0; }
718 #ifndef PRODUCT
719 virtual const char *Name() const { return "MachMerge"; }
720 #endif
721 };
722
723 //------------------------------MachBranchNode--------------------------------
724 // Abstract machine branch Node
725 class MachBranchNode : public MachIdealNode {
726 public:
727 MachBranchNode() : MachIdealNode() {
728 init_class_id(Class_MachBranch);
729 }
730 virtual void label_set(Label* label, uint block_num) = 0;
731 virtual void save_label(Label** label, uint* block_num) = 0;
732
733 // Support for short branches
734 virtual MachNode *short_branch_version() { return nullptr; }
735
736 virtual bool pinned() const { return true; };
737 };
738
739 //------------------------------MachNullChkNode--------------------------------
740 // Machine-dependent null-pointer-check Node. Points a real MachNode that is
741 // also some kind of memory op. Turns the indicated MachNode into a
742 // conditional branch with good latency on the ptr-not-null path and awful
743 // latency on the pointer-is-null path.
744
745 class MachNullCheckNode : public MachBranchNode {
746 public:
747 const uint _vidx; // Index of memop being tested
748 MachNullCheckNode( Node *ctrl, Node *memop, uint vidx ) : MachBranchNode(), _vidx(vidx) {
749 init_class_id(Class_MachNullCheck);
750 add_req(ctrl);
751 add_req(memop);
752 }
753 virtual int Opcode() const;
754 virtual uint size_of() const { return sizeof(*this); }
755
756 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
757 virtual void label_set(Label* label, uint block_num);
758 virtual void save_label(Label** label, uint* block_num);
759 virtual void negate() { }
760 virtual const class Type *bottom_type() const { return TypeTuple::IFBOTH; }
761 virtual uint ideal_reg() const { return NotAMachineReg; }
762 virtual const RegMask &in_RegMask(uint) const;
763 virtual const RegMask& out_RegMask() const { return RegMask::EMPTY; }
764 #ifndef PRODUCT
765 virtual const char *Name() const { return "NullCheck"; }
766 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
767 #endif
768 };
769
770 //------------------------------MachProjNode----------------------------------
771 // Machine-dependent Ideal projections (how is that for an oxymoron). Really
772 // just MachNodes made by the Ideal world that replicate simple projections
773 // but with machine-dependent input & output register masks. Generally
774 // produced as part of calling conventions. Normally I make MachNodes as part
775 // of the Matcher process, but the Matcher is ill suited to issues involving
776 // frame handling, so frame handling is all done in the Ideal world with
777 // occasional callbacks to the machine model for important info.
778 class MachProjNode : public ProjNode {
779 public:
780 MachProjNode(Node* multi, uint con, const RegMask& out, uint ideal_reg)
781 : ProjNode(multi, con),
782 _rout(out, Compile::current()->comp_arena()),
783 _ideal_reg(ideal_reg) {
784 init_class_id(Class_MachProj);
785 }
786 RegMask _rout;
787 const uint _ideal_reg;
788 enum projType {
789 unmatched_proj = 0, // Projs for Control, I/O, memory not matched
790 fat_proj = 999 // Projs killing many regs, defined by _rout
791 };
792 virtual int Opcode() const;
793 virtual const Type *bottom_type() const;
794 virtual const TypePtr *adr_type() const;
795 virtual const RegMask& in_RegMask(uint) const { return RegMask::EMPTY; }
796 virtual const RegMask &out_RegMask() const { return _rout; }
797 virtual uint ideal_reg() const { return _ideal_reg; }
798 // Need size_of() for virtual ProjNode::clone()
799 virtual uint size_of() const { return sizeof(MachProjNode); }
800 #ifndef PRODUCT
801 virtual void dump_spec(outputStream *st) const;
802 #endif
803 };
804
805 //------------------------------MachIfNode-------------------------------------
806 // Machine-specific versions of IfNodes
807 class MachIfNode : public MachBranchNode {
808 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
809 public:
810 float _prob; // Probability branch goes either way
811 float _fcnt; // Frequency counter
812 MachIfNode() : MachBranchNode() {
813 init_class_id(Class_MachIf);
814 }
815 // Negate conditional branches.
816 virtual void negate() = 0;
817 #ifndef PRODUCT
818 virtual void dump_spec(outputStream *st) const;
819 #endif
820 };
821
822 //------------------------------MachJumpNode-----------------------------------
823 // Machine-specific versions of JumpNodes
824 class MachJumpNode : public MachConstantNode {
825 public:
826 float* _probs;
827 MachJumpNode() : MachConstantNode() {
828 init_class_id(Class_MachJump);
829 }
830 virtual uint size_of() const { return sizeof(MachJumpNode); }
831 };
832
833 //------------------------------MachGotoNode-----------------------------------
834 // Machine-specific versions of GotoNodes
835 class MachGotoNode : public MachBranchNode {
836 public:
837 MachGotoNode() : MachBranchNode() {
838 init_class_id(Class_MachGoto);
839 }
840 };
841
842 //------------------------------MachFastLockNode-------------------------------------
843 // Machine-specific versions of FastLockNodes
844 class MachFastLockNode : public MachNode {
845 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
846 public:
847 MachFastLockNode() : MachNode() {}
848 };
849
850 //------------------------------MachReturnNode--------------------------------
851 // Machine-specific versions of subroutine returns
852 class MachReturnNode : public MachNode {
853 virtual uint size_of() const; // Size is bigger
854 public:
855 RegMask *_in_rms; // Input register masks, set during allocation
856 ReallocMark _nesting; // assertion check for reallocations
857 const TypePtr* _adr_type; // memory effects of call or return
858 MachReturnNode() : MachNode() {
859 init_class_id(Class_MachReturn);
860 _adr_type = TypePtr::BOTTOM; // the default: all of memory
861 }
862
863 void set_adr_type(const TypePtr* atp) { _adr_type = atp; }
864
865 virtual const RegMask &in_RegMask(uint) const;
866 virtual bool pinned() const { return true; };
867 virtual const TypePtr *adr_type() const;
868 };
869
870 //------------------------------MachSafePointNode-----------------------------
871 // Machine-specific versions of safepoints
872 class MachSafePointNode : public MachReturnNode {
873 public:
874 OopMap* _oop_map; // Array of OopMap info (8-bit char) for GC
875 JVMState* _jvms; // Pointer to list of JVM State Objects
876 uint _jvmadj; // Extra delta to jvms indexes (mach. args)
877 bool _has_ea_local_in_scope; // NoEscape or ArgEscape objects in JVM States
878 OopMap* oop_map() const { return _oop_map; }
879 void set_oop_map(OopMap* om) { _oop_map = om; }
880
881 MachSafePointNode() : MachReturnNode(), _oop_map(nullptr), _jvms(nullptr), _jvmadj(0), _has_ea_local_in_scope(false) {
882 init_class_id(Class_MachSafePoint);
883 }
884
885 virtual JVMState* jvms() const { return _jvms; }
886 void set_jvms(JVMState* s) {
887 _jvms = s;
888 }
889 virtual const Type *bottom_type() const;
890
891 virtual const RegMask &in_RegMask(uint) const;
892
893 // Functionality from old debug nodes
894 Node *returnadr() const { return in(TypeFunc::ReturnAdr); }
895 Node *frameptr () const { return in(TypeFunc::FramePtr); }
896
897 Node *local(const JVMState* jvms, uint idx) const {
898 assert(verify_jvms(jvms), "jvms must match");
899 return in(_jvmadj + jvms->locoff() + idx);
900 }
901 Node *stack(const JVMState* jvms, uint idx) const {
902 assert(verify_jvms(jvms), "jvms must match");
903 return in(_jvmadj + jvms->stkoff() + idx);
904 }
905 Node *monitor_obj(const JVMState* jvms, uint idx) const {
906 assert(verify_jvms(jvms), "jvms must match");
907 return in(_jvmadj + jvms->monitor_obj_offset(idx));
908 }
909 Node *monitor_box(const JVMState* jvms, uint idx) const {
910 assert(verify_jvms(jvms), "jvms must match");
911 return in(_jvmadj + jvms->monitor_box_offset(idx));
912 }
913 Node* scalarized_obj(const JVMState* jvms, uint idx) const {
914 assert(verify_jvms(jvms), "jvms must match");
915 return in(_jvmadj + jvms->scloff() + idx);
916 }
917 void set_local(const JVMState* jvms, uint idx, Node *c) {
918 assert(verify_jvms(jvms), "jvms must match");
919 set_req(_jvmadj + jvms->locoff() + idx, c);
920 }
921 void set_stack(const JVMState* jvms, uint idx, Node *c) {
922 assert(verify_jvms(jvms), "jvms must match");
923 set_req(_jvmadj + jvms->stkoff() + idx, c);
924 }
925 void set_monitor(const JVMState* jvms, uint idx, Node *c) {
926 assert(verify_jvms(jvms), "jvms must match");
927 set_req(_jvmadj + jvms->monoff() + idx, c);
928 }
929 virtual uint size_of() const { return sizeof(MachSafePointNode); }
930 };
931
932 //------------------------------MachCallNode----------------------------------
933 // Machine-specific versions of subroutine calls
934 class MachCallNode : public MachSafePointNode {
935 protected:
936 virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash
937 virtual bool cmp( const Node &n ) const;
938 virtual uint size_of() const = 0; // Size is bigger
939 public:
940 const TypeFunc *_tf; // Function type
941 address _entry_point; // Address of the method being called
942 float _cnt; // Estimate of number of times called
943 bool _guaranteed_safepoint; // Do we need to observe safepoint?
944
945 const TypeFunc* tf() const { return _tf; }
946 address entry_point() const { return _entry_point; }
947 float cnt() const { return _cnt; }
948
949 void set_tf(const TypeFunc* tf) { _tf = tf; }
950 void set_entry_point(address p) { _entry_point = p; }
951 void set_cnt(float c) { _cnt = c; }
952 void set_guaranteed_safepoint(bool b) { _guaranteed_safepoint = b; }
953
954 MachCallNode() : MachSafePointNode() {
955 init_class_id(Class_MachCall);
956 }
957
958 virtual const Type *bottom_type() const;
959 virtual bool pinned() const { return false; }
960 virtual const Type* Value(PhaseGVN* phase) const;
961 virtual const RegMask &in_RegMask(uint) const;
962 virtual int ret_addr_offset() { return 0; }
963
964 NOT_LP64(bool return_value_is_used() const;)
965
966 // Similar to cousin class CallNode::returns_pointer
967 bool returns_pointer() const;
968
969 bool guaranteed_safepoint() const { return _guaranteed_safepoint; }
970
971 #ifndef PRODUCT
972 virtual void dump_spec(outputStream *st) const;
973 #endif
974 };
975
976 //------------------------------MachCallJavaNode------------------------------
977 // "Base" class for machine-specific versions of subroutine calls
978 class MachCallJavaNode : public MachCallNode {
979 protected:
980 virtual bool cmp( const Node &n ) const;
981 virtual uint size_of() const; // Size is bigger
982 public:
983 ciMethod* _method; // Method being direct called
984 bool _override_symbolic_info; // Override symbolic call site info from bytecode
985 bool _optimized_virtual; // Tells if node is a static call or an optimized virtual
986 bool _arg_escape; // ArgEscape in parameter list
987 MachCallJavaNode() : MachCallNode(), _override_symbolic_info(false) {
988 init_class_id(Class_MachCallJava);
989 }
990
991 virtual const RegMask &in_RegMask(uint) const;
992
993 int resolved_method_index(C2_MacroAssembler *masm) const {
994 if (_override_symbolic_info) {
995 // Attach corresponding Method* to the call site, so VM can use it during resolution
996 // instead of querying symbolic info from bytecode.
997 assert(_method != nullptr, "method should be set");
998 assert(_method->constant_encoding()->is_method(), "should point to a Method");
999 return masm->code()->oop_recorder()->find_index(_method->constant_encoding());
1000 }
1001 return 0; // Use symbolic info from bytecode (resolved_method is null).
1002 }
1003
1004 #ifndef PRODUCT
1005 virtual void dump_spec(outputStream *st) const;
1006 #endif
1007 };
1008
1009 //------------------------------MachCallStaticJavaNode------------------------
1010 // Machine-specific versions of monomorphic subroutine calls
1011 class MachCallStaticJavaNode : public MachCallJavaNode {
1012 virtual bool cmp( const Node &n ) const;
1013 virtual uint size_of() const; // Size is bigger
1014 public:
1015 const char *_name; // Runtime wrapper name
1016 MachCallStaticJavaNode() : MachCallJavaNode() {
1017 init_class_id(Class_MachCallStaticJava);
1018 }
1019
1020 // If this is an uncommon trap, return the request code, else zero.
1021 int uncommon_trap_request() const;
1022
1023 virtual int ret_addr_offset();
1024 #ifndef PRODUCT
1025 virtual void dump_spec(outputStream *st) const;
1026 void dump_trap_args(outputStream *st) const;
1027 #endif
1028 };
1029
1030 //------------------------------MachCallDynamicJavaNode------------------------
1031 // Machine-specific versions of possibly megamorphic subroutine calls
1032 class MachCallDynamicJavaNode : public MachCallJavaNode {
1033 public:
1034 int _vtable_index;
1035 MachCallDynamicJavaNode() : MachCallJavaNode() {
1036 init_class_id(Class_MachCallDynamicJava);
1037 DEBUG_ONLY(_vtable_index = -99); // throw an assert if uninitialized
1038 }
1039 virtual int ret_addr_offset();
1040 #ifndef PRODUCT
1041 virtual void dump_spec(outputStream *st) const;
1042 #endif
1043 virtual uint size_of() const { return sizeof(MachCallDynamicJavaNode); }
1044 };
1045
1046 //------------------------------MachCallRuntimeNode----------------------------
1047 // Machine-specific versions of subroutine calls
1048 class MachCallRuntimeNode : public MachCallNode {
1049 virtual bool cmp( const Node &n ) const;
1050 virtual uint size_of() const; // Size is bigger
1051 public:
1052 const char *_name; // Printable name, if _method is null
1053 bool _leaf_no_fp; // Is this CallLeafNoFP?
1054 MachCallRuntimeNode() : MachCallNode() {
1055 init_class_id(Class_MachCallRuntime);
1056 }
1057 virtual int ret_addr_offset();
1058 #ifndef PRODUCT
1059 virtual void dump_spec(outputStream *st) const;
1060 #endif
1061 };
1062
1063 class MachCallLeafNode: public MachCallRuntimeNode {
1064 public:
1065 MachCallLeafNode() : MachCallRuntimeNode() {
1066 init_class_id(Class_MachCallLeaf);
1067 }
1068 };
1069
1070 //------------------------------MachHaltNode-----------------------------------
1071 // Machine-specific versions of halt nodes
1072 class MachHaltNode : public MachReturnNode {
1073 public:
1074 bool _reachable;
1075 const char* _halt_reason;
1076 virtual JVMState* jvms() const;
1077 virtual uint size_of() const { return sizeof(MachHaltNode); }
1078 bool is_reachable() const {
1079 return _reachable;
1080 }
1081 };
1082
1083 class MachMemBarNode : public MachNode {
1084 virtual uint size_of() const; // Size is bigger
1085 public:
1086 const TypePtr* _adr_type; // memory effects
1087 MachMemBarNode() : MachNode() {
1088 init_class_id(Class_MachMemBar);
1089 _adr_type = TypePtr::BOTTOM; // the default: all of memory
1090 }
1091
1092 void set_adr_type(const TypePtr* atp) { _adr_type = atp; }
1093 virtual const TypePtr *adr_type() const;
1094 };
1095
1096
1097 //------------------------------MachTempNode-----------------------------------
1098 // Node used by the adlc to construct inputs to represent temporary registers
1099 class MachTempNode : public MachNode {
1100 private:
1101 MachOper *_opnd_array[1];
1102
1103 public:
1104 virtual const RegMask &out_RegMask() const { return *_opnds[0]->in_RegMask(0); }
1105 virtual uint rule() const { return 9999999; }
1106 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {}
1107
1108 MachTempNode(MachOper* oper) {
1109 init_class_id(Class_MachTemp);
1110 _num_opnds = 1;
1111 _opnds = _opnd_array;
1112 add_req(nullptr);
1113 _opnds[0] = oper;
1114 }
1115 virtual uint size_of() const { return sizeof(MachTempNode); }
1116
1117 #ifndef PRODUCT
1118 virtual void format(PhaseRegAlloc *, outputStream *st ) const {}
1119 virtual const char *Name() const { return "MachTemp";}
1120 #endif
1121 };
1122
1123
1124
1125 //------------------------------labelOper--------------------------------------
1126 // Machine-independent version of label operand
1127 class labelOper : public MachOper {
1128 private:
1129 virtual uint num_edges() const { return 0; }
1130 public:
1131 // Supported for fixed size branches
1132 Label* _label; // Label for branch(es)
1133
1134 uint _block_num;
1135
1136 labelOper() : _label(nullptr), _block_num(0) {}
1137
1138 labelOper(Label* label, uint block_num) : _label(label), _block_num(block_num) {}
1139
1140 labelOper(labelOper* l) : _label(l->_label) , _block_num(l->_block_num) {}
1141
1142 virtual MachOper *clone() const;
1143
1144 virtual Label *label() const { assert(_label != nullptr, "need Label"); return _label; }
1145
1146 virtual uint opcode() const;
1147
1148 virtual uint hash() const;
1149 virtual bool cmp( const MachOper &oper ) const;
1150 #ifndef PRODUCT
1151 virtual const char *Name() const { return "Label";}
1152
1153 virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const;
1154 virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { int_format( ra, node, st ); }
1155 #endif
1156 };
1157
1158
1159 //------------------------------methodOper--------------------------------------
1160 // Machine-independent version of method operand
1161 class methodOper : public MachOper {
1162 private:
1163 virtual uint num_edges() const { return 0; }
1164 public:
1165 intptr_t _method; // Address of method
1166 methodOper() : _method(0) {}
1167 methodOper(intptr_t method) : _method(method) {}
1168
1169 virtual MachOper *clone() const;
1170
1171 virtual intptr_t method() const { return _method; }
1172
1173 virtual uint opcode() const;
1174
1175 virtual uint hash() const;
1176 virtual bool cmp( const MachOper &oper ) const;
1177 #ifndef PRODUCT
1178 virtual const char *Name() const { return "Method";}
1179
1180 virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const;
1181 virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { int_format( ra, node, st ); }
1182 #endif
1183 };
1184
1185 #endif // SHARE_OPTO_MACHNODE_HPP