1 /*
2 * Copyright (c) 2018, 2021, Red Hat, Inc. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_LIRAssembler.hpp"
27 #include "c1/c1_MacroAssembler.hpp"
28 #include "compiler/compilerDefinitions.inline.hpp"
29 #include "gc/shared/gc_globals.hpp"
30 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
31 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
32 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"
33
34 #define __ masm->masm()->
35
36 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) {
37 Register addr = _addr->as_register_lo();
38 Register newval = _new_value->as_register();
39 Register cmpval = _cmp_value->as_register();
40 Register tmp1 = _tmp1->as_register();
41 Register tmp2 = _tmp2->as_register();
42 Register result = result_opr()->as_register();
43
44 ShenandoahBarrierSet::assembler()->iu_barrier(masm->masm(), newval, rscratch2);
45
46 if (UseCompressedOops) {
47 __ encode_heap_oop(tmp1, cmpval);
48 cmpval = tmp1;
49 __ encode_heap_oop(tmp2, newval);
50 newval = tmp2;
51 }
52
53 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmpval, newval, /*acquire*/ true, /*release*/ true, /*is_cae*/ false, result);
54
55 if (CompilerConfig::is_c1_only_no_jvmci()) {
56 // The membar here is necessary to prevent reordering between the
57 // release store in the CAS above and a subsequent volatile load.
58 // However for tiered compilation C1 inserts a full barrier before
59 // volatile loads which means we don't need an additional barrier
60 // here (see LIRGenerator::volatile_field_load()).
61 __ membar(__ AnyAny);
62 }
63 }
64
65 #undef __
66
67 #ifdef ASSERT
68 #define __ gen->lir(__FILE__, __LINE__)->
69 #else
70 #define __ gen->lir()->
71 #endif
72
73 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {
74 BasicType bt = access.type();
75 if (access.is_oop()) {
76 LIRGenerator *gen = access.gen();
77 if (ShenandoahSATBBarrier) {
78 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
79 LIR_OprFact::illegalOpr /* pre_val */);
80 }
81 if (ShenandoahCASBarrier) {
82 cmp_value.load_item();
83 new_value.load_item();
84
85 LIR_Opr t1 = gen->new_register(T_OBJECT);
86 LIR_Opr t2 = gen->new_register(T_OBJECT);
87 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
88 LIR_Opr result = gen->new_register(T_INT);
89
90 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));
91 return result;
92 }
93 }
94 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
95 }
96
97 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) {
98 LIRGenerator* gen = access.gen();
99 BasicType type = access.type();
100
101 LIR_Opr result = gen->new_register(type);
102 value.load_item();
103 LIR_Opr value_opr = value.result();
104
105 if (access.is_oop()) {
106 value_opr = iu_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());
107 }
108
109 assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type");
110 LIR_Opr tmp = gen->new_register(T_INT);
111 __ xchg(access.resolved_addr(), value_opr, result, tmp);
112
113 if (access.is_oop()) {
114 result = load_reference_barrier(access.gen(), result, LIR_OprFact::addressConst(0), access.decorators());
115 LIR_Opr tmp = gen->new_register(type);
116 __ move(result, tmp);
117 result = tmp;
118 if (ShenandoahSATBBarrier) {
119 pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr,
120 result /* pre_val */);
121 }
122 }
123
124 return result;
125 }