1 /*
2 * Copyright (c) 2018, 2021, Red Hat, Inc. All rights reserved.
3 * Copyright Amazon.com Inc. or its affiliates. All Rights Reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "compiler/compilerDefinitions.inline.hpp"
30 #include "gc/shared/gc_globals.hpp"
31 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
32 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
33 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"
34
35 #define __ masm->masm()->
36
37 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) {
38 Register addr = _addr->as_register_lo();
39 Register newval = _new_value->as_register();
40 Register cmpval = _cmp_value->as_register();
41 Register tmp1 = _tmp1->as_register();
42 Register tmp2 = _tmp2->as_register();
43 Register result = result_opr()->as_register();
44
45 ShenandoahBarrierSet::assembler()->iu_barrier(masm->masm(), newval, rscratch2);
46
47 if (UseCompressedOops) {
48 __ encode_heap_oop(tmp1, cmpval);
49 cmpval = tmp1;
50 __ encode_heap_oop(tmp2, newval);
51 newval = tmp2;
52 }
53
54 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmpval, newval, /*acquire*/ true, /*release*/ true, /*is_cae*/ false, result);
55
56 if (CompilerConfig::is_c1_only_no_jvmci()) {
57 // The membar here is necessary to prevent reordering between the
58 // release store in the CAS above and a subsequent volatile load.
59 // However for tiered compilation C1 inserts a full barrier before
60 // volatile loads which means we don't need an additional barrier
61 // here (see LIRGenerator::volatile_field_load()).
62 __ membar(__ AnyAny);
63 }
64 }
65
66 #undef __
67
68 #ifdef ASSERT
69 #define __ gen->lir(__FILE__, __LINE__)->
70 #else
71 #define __ gen->lir()->
72 #endif
73
74 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {
75 BasicType bt = access.type();
76 if (access.is_oop()) {
77 LIRGenerator *gen = access.gen();
78 if (ShenandoahSATBBarrier) {
79 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
80 LIR_OprFact::illegalOpr /* pre_val */);
81 }
82 if (ShenandoahCASBarrier) {
83 cmp_value.load_item();
84 new_value.load_item();
85
86 LIR_Opr t1 = gen->new_register(T_OBJECT);
87 LIR_Opr t2 = gen->new_register(T_OBJECT);
88 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
89 LIR_Opr result = gen->new_register(T_INT);
90
91 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));
92
93 if (ShenandoahCardBarrier) {
94 post_barrier(access, access.resolved_addr(), new_value.result());
95 }
96 return result;
97 }
98 }
99
100 LIR_Opr result = BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
101
102 if (ShenandoahCardBarrier && access.is_oop()) {
103 post_barrier(access, access.resolved_addr(), new_value.result());
104 }
105
106 return result;
107 }
108
109 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) {
110 LIRGenerator* gen = access.gen();
111 BasicType type = access.type();
112
113 LIR_Opr result = gen->new_register(type);
114 value.load_item();
115 LIR_Opr value_opr = value.result();
116
117 if (access.is_oop()) {
118 value_opr = iu_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());
119 }
120
121 assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type");
122 LIR_Opr tmp = gen->new_register(T_INT);
123 __ xchg(access.resolved_addr(), value_opr, result, tmp);
124
125 if (access.is_oop()) {
126 result = load_reference_barrier(access.gen(), result, LIR_OprFact::addressConst(0), access.decorators());
127 LIR_Opr tmp = gen->new_register(type);
128 __ move(result, tmp);
129 result = tmp;
130 if (ShenandoahSATBBarrier) {
131 pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr,
132 result /* pre_val */);
133 }
134 if (ShenandoahCardBarrier) {
135 post_barrier(access, access.resolved_addr(), result);
136 }
137 }
138
139 return result;
140 }