1 /*
  2  * Copyright (c) 2018, 2021, Red Hat, Inc. All rights reserved.
  3  * Copyright Amazon.com Inc. or its affiliates. All Rights Reserved.
  4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  5  *
  6  * This code is free software; you can redistribute it and/or modify it
  7  * under the terms of the GNU General Public License version 2 only, as
  8  * published by the Free Software Foundation.
  9  *
 10  * This code is distributed in the hope that it will be useful, but WITHOUT
 11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 13  * version 2 for more details (a copy is included in the LICENSE file that
 14  * accompanied this code).
 15  *
 16  * You should have received a copy of the GNU General Public License version
 17  * 2 along with this work; if not, write to the Free Software Foundation,
 18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 19  *
 20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 21  * or visit www.oracle.com if you need additional information or have any
 22  * questions.
 23  *
 24  */
 25 
 26 #include "precompiled.hpp"
 27 #include "c1/c1_LIRAssembler.hpp"
 28 #include "c1/c1_MacroAssembler.hpp"
 29 #include "compiler/compilerDefinitions.inline.hpp"
 30 #include "gc/shared/gc_globals.hpp"
 31 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
 32 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
 33 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"
 34 
 35 #define __ masm->masm()->
 36 
 37 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) {
 38   Register addr = _addr->as_register_lo();
 39   Register newval = _new_value->as_register();
 40   Register cmpval = _cmp_value->as_register();
 41   Register tmp1 = _tmp1->as_register();
 42   Register tmp2 = _tmp2->as_register();
 43   Register result = result_opr()->as_register();
 44 
 45   if (UseCompressedOops) {
 46     __ encode_heap_oop(tmp1, cmpval);
 47     cmpval = tmp1;
 48     __ encode_heap_oop(tmp2, newval);
 49     newval = tmp2;
 50   }
 51 
 52   ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmpval, newval, /*acquire*/ true, /*release*/ true, /*is_cae*/ false, result);
 53 
 54   if (CompilerConfig::is_c1_only_no_jvmci()) {
 55     // The membar here is necessary to prevent reordering between the
 56     // release store in the CAS above and a subsequent volatile load.
 57     // However for tiered compilation C1 inserts a full barrier before
 58     // volatile loads which means we don't need an additional barrier
 59     // here (see LIRGenerator::volatile_field_load()).
 60     __ membar(__ AnyAny);
 61   }
 62 }
 63 
 64 #undef __
 65 
 66 #ifdef ASSERT
 67 #define __ gen->lir(__FILE__, __LINE__)->
 68 #else
 69 #define __ gen->lir()->
 70 #endif
 71 
 72 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {
 73   BasicType bt = access.type();
 74   if (access.is_oop()) {
 75     LIRGenerator *gen = access.gen();
 76     if (ShenandoahSATBBarrier) {
 77       pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
 78                   LIR_OprFact::illegalOpr /* pre_val */);
 79     }
 80     if (ShenandoahCASBarrier) {
 81       cmp_value.load_item();
 82       new_value.load_item();
 83 
 84       LIR_Opr t1 = gen->new_register(T_OBJECT);
 85       LIR_Opr t2 = gen->new_register(T_OBJECT);
 86       LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
 87       LIR_Opr result = gen->new_register(T_INT);
 88 
 89       __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));
 90 
 91       if (ShenandoahCardBarrier) {
 92         post_barrier(access, access.resolved_addr(), new_value.result());
 93       }
 94       return result;
 95     }
 96   }
 97   return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
 98 }
 99 
100 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) {
101   LIRGenerator* gen = access.gen();
102   BasicType type = access.type();
103 
104   LIR_Opr result = gen->new_register(type);
105   value.load_item();
106   LIR_Opr value_opr = value.result();
107 
108   assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type");
109   LIR_Opr tmp = gen->new_register(T_INT);
110   __ xchg(access.resolved_addr(), value_opr, result, tmp);
111 
112   if (access.is_oop()) {
113     result = load_reference_barrier(access.gen(), result, LIR_OprFact::addressConst(0), access.decorators());
114     LIR_Opr tmp = gen->new_register(type);
115     __ move(result, tmp);
116     result = tmp;
117     if (ShenandoahSATBBarrier) {
118       pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr,
119                   result /* pre_val */);
120     }
121     if (ShenandoahCardBarrier) {
122       post_barrier(access, access.resolved_addr(), result);
123     }
124   }
125 
126   return result;
127 }
--- EOF ---