1 /*
2 * Copyright (c) 2018, 2021, Red Hat, Inc. All rights reserved.
3 * Copyright (c) 2012, 2021 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
31 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
32 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"
33
34 #define __ masm->masm()->
35
36 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler *masm) {
37 __ block_comment("LIR_OpShenandoahCompareAndSwap (shenandaohgc) {");
38
39 Register addr = _addr->as_register_lo();
40 Register new_val = _new_value->as_register();
41 Register cmp_val = _cmp_value->as_register();
42 Register tmp1 = _tmp1->as_register();
43 Register tmp2 = _tmp2->as_register();
44 Register result = result_opr()->as_register();
45
46 if (ShenandoahIUBarrier) {
47 ShenandoahBarrierSet::assembler()->iu_barrier(masm->masm(), new_val, tmp1, tmp2,
48 MacroAssembler::PRESERVATION_FRAME_LR_GP_FP_REGS);
49 }
50
51 if (UseCompressedOops) {
52 __ encode_heap_oop(cmp_val, cmp_val);
53 __ encode_heap_oop(new_val, new_val);
54 }
55
56 // Due to the memory barriers emitted in ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved,
57 // there is no need to specify stronger memory semantics.
58 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmp_val, new_val, tmp1, tmp2,
59 false, result);
60
61 if (UseCompressedOops) {
62 __ decode_heap_oop(cmp_val);
63 __ decode_heap_oop(new_val);
64 }
65
66 __ block_comment("} LIR_OpShenandoahCompareAndSwap (shenandaohgc)");
67 }
68
69 #undef __
70
71 #ifdef ASSERT
72 #define __ gen->lir(__FILE__, __LINE__)->
73 #else
74 #define __ gen->lir()->
75 #endif
76
77 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess &access, LIRItem &cmp_value, LIRItem &new_value) {
78 BasicType bt = access.type();
79
80 if (access.is_oop()) {
81 LIRGenerator* gen = access.gen();
82
83 if (ShenandoahCASBarrier) {
84 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
85 __ membar();
86 } else {
87 __ membar_release();
88 }
89 }
90
91 if (ShenandoahSATBBarrier) {
92 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
93 LIR_OprFact::illegalOpr);
94 }
95
96 if (ShenandoahCASBarrier) {
97 cmp_value.load_item();
98 new_value.load_item();
99
100 LIR_Opr t1 = gen->new_register(T_OBJECT);
101 LIR_Opr t2 = gen->new_register(T_OBJECT);
102 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
103 LIR_Opr result = gen->new_register(T_INT);
104
105 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));
106
107 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
108 __ membar_acquire();
109 } else {
110 __ membar();
111 }
112
113 return result;
114 }
115 }
116
117 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
118 }
119
120 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess &access, LIRItem &value) {
121 LIRGenerator* gen = access.gen();
122 BasicType type = access.type();
123
124 LIR_Opr result = gen->new_register(type);
125 value.load_item();
126 LIR_Opr value_opr = value.result();
127
128 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
129 __ membar();
130 } else {
131 __ membar_release();
132 }
133
134 if (access.is_oop()) {
135 value_opr = iu_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());
136 }
137
138 assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type");
139 LIR_Opr tmp_xchg = gen->new_register(T_INT);
140 __ xchg(access.resolved_addr(), value_opr, result, tmp_xchg);
141
142 if (access.is_oop()) {
143 result = load_reference_barrier_impl(access.gen(), result, LIR_OprFact::addressConst(0),
144 access.decorators());
145
146 LIR_Opr tmp_barrier = gen->new_register(type);
147 __ move(result, tmp_barrier);
148 result = tmp_barrier;
149
150 if (ShenandoahSATBBarrier) {
151 pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr, result);
152 }
153 }
154
155 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
156 __ membar_acquire();
157 } else {
158 __ membar();
159 }
160
161 return result;
162 }