1 /*
2 * Copyright (c) 2018, 2023, Red Hat, Inc. All rights reserved.
3 * Copyright (c) 2012, 2023 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
31 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
32 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"
33
34 #define __ masm->masm()->
35
36 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler *masm) {
37 __ block_comment("LIR_OpShenandoahCompareAndSwap (shenandaohgc) {");
38
39 Register addr = _addr->as_register_lo();
40 Register new_val = _new_value->as_register();
41 Register cmp_val = _cmp_value->as_register();
42 Register tmp1 = _tmp1->as_register();
43 Register tmp2 = _tmp2->as_register();
44 Register result = result_opr()->as_register();
45
46 if (UseCompressedOops) {
47 __ encode_heap_oop(cmp_val, cmp_val);
48 __ encode_heap_oop(new_val, new_val);
49 }
50
51 // There might be a volatile load before this Unsafe CAS.
52 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
53 __ sync();
54 } else {
55 __ lwsync();
56 }
57
58 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), addr, cmp_val, new_val, tmp1, tmp2,
59 false, result);
60
61 if (UseCompressedOops) {
62 __ decode_heap_oop(cmp_val);
63 __ decode_heap_oop(new_val);
64 }
65
66 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
67 __ isync();
68 } else {
69 __ sync();
70 }
71
72 __ block_comment("} LIR_OpShenandoahCompareAndSwap (shenandaohgc)");
73 }
74
75 #undef __
76
77 #ifdef ASSERT
78 #define __ gen->lir(__FILE__, __LINE__)->
79 #else
80 #define __ gen->lir()->
81 #endif
82
83 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess &access, LIRItem &cmp_value, LIRItem &new_value) {
84 BasicType bt = access.type();
85
86 if (access.is_oop()) {
87 LIRGenerator* gen = access.gen();
88
89 if (ShenandoahSATBBarrier) {
90 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
91 LIR_OprFact::illegalOpr);
92 }
93
94 if (ShenandoahCASBarrier) {
95 cmp_value.load_item();
96 new_value.load_item();
97
98 LIR_Opr t1 = gen->new_register(T_OBJECT);
99 LIR_Opr t2 = gen->new_register(T_OBJECT);
100 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
101 LIR_Opr result = gen->new_register(T_INT);
102
103 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));
104
105 return result;
106 }
107 }
108
109 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
110 }
111
112 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess &access, LIRItem &value) {
113 LIRGenerator* gen = access.gen();
114 BasicType type = access.type();
115
116 LIR_Opr result = gen->new_register(type);
117 value.load_item();
118 LIR_Opr value_opr = value.result();
119
120 assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type");
121 LIR_Opr tmp_xchg = gen->new_register(T_INT);
122 __ xchg(access.resolved_addr(), value_opr, result, tmp_xchg);
123
124 if (access.is_oop()) {
125 result = load_reference_barrier_impl(access.gen(), result, LIR_OprFact::addressConst(0),
126 access.decorators());
127
128 LIR_Opr tmp_barrier = gen->new_register(type);
129 __ move(result, tmp_barrier);
130 result = tmp_barrier;
131
132 if (ShenandoahSATBBarrier) {
133 pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr, result);
134 }
135 }
136
137 return result;
138 }