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src/hotspot/cpu/ppc/gc/shenandoah/c1/shenandoahBarrierSetC1_ppc.cpp

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 87         __ membar_release();
 88       }
 89     }
 90 
 91     if (ShenandoahSATBBarrier) {
 92       pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
 93                   LIR_OprFact::illegalOpr);
 94     }
 95 
 96     if (ShenandoahCASBarrier) {
 97       cmp_value.load_item();
 98       new_value.load_item();
 99 
100       LIR_Opr t1 = gen->new_register(T_OBJECT);
101       LIR_Opr t2 = gen->new_register(T_OBJECT);
102       LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
103       LIR_Opr result = gen->new_register(T_INT);
104 
105       __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));
106 


107       if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
108         __ membar_acquire();
109       } else {
110         __ membar();
111       }
112 
113       return result;
114     }
115   }
116 
117   return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);






118 }
119 
120 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess &access, LIRItem &value) {
121   LIRGenerator* gen = access.gen();
122   BasicType type = access.type();
123 
124   LIR_Opr result = gen->new_register(type);
125   value.load_item();
126   LIR_Opr value_opr = value.result();
127 
128   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
129     __ membar();
130   } else {
131     __ membar_release();
132   }
133 
134   if (access.is_oop()) {
135     value_opr = iu_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());
136   }
137 
138   assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type");
139   LIR_Opr tmp_xchg = gen->new_register(T_INT);
140   __ xchg(access.resolved_addr(), value_opr, result, tmp_xchg);
141 
142   if (access.is_oop()) {
143     result = load_reference_barrier_impl(access.gen(), result, LIR_OprFact::addressConst(0),
144                                          access.decorators());
145 
146     LIR_Opr tmp_barrier = gen->new_register(type);
147     __ move(result, tmp_barrier);
148     result = tmp_barrier;
149 
150     if (ShenandoahSATBBarrier) {
151       pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr, result);
152     }


153   }
154 
155   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
156     __ membar_acquire();
157   } else {
158     __ membar();
159   }
160 
161   return result;
162 }

 87         __ membar_release();
 88       }
 89     }
 90 
 91     if (ShenandoahSATBBarrier) {
 92       pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
 93                   LIR_OprFact::illegalOpr);
 94     }
 95 
 96     if (ShenandoahCASBarrier) {
 97       cmp_value.load_item();
 98       new_value.load_item();
 99 
100       LIR_Opr t1 = gen->new_register(T_OBJECT);
101       LIR_Opr t2 = gen->new_register(T_OBJECT);
102       LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
103       LIR_Opr result = gen->new_register(T_INT);
104 
105       __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));
106 
107       post_barrier(access, access.resolved_addr(), new_value.result());
108 
109       if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
110         __ membar_acquire();
111       } else {
112         __ membar();
113       }
114 
115       return result;
116     }
117   }
118 
119   LIR_Opr result = BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
120 
121   if (access.is_oop()) {
122     post_barrier(access, access.resolved_addr(), new_value.result());
123   }
124 
125   return result;
126 }
127 
128 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess &access, LIRItem &value) {
129   LIRGenerator* gen = access.gen();
130   BasicType type = access.type();
131 
132   LIR_Opr result = gen->new_register(type);
133   value.load_item();
134   LIR_Opr value_opr = value.result();
135 
136   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
137     __ membar();
138   } else {
139     __ membar_release();
140   }
141 
142   if (access.is_oop()) {
143     value_opr = iu_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());
144   }
145 
146   assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type");
147   LIR_Opr tmp_xchg = gen->new_register(T_INT);
148   __ xchg(access.resolved_addr(), value_opr, result, tmp_xchg);
149 
150   if (access.is_oop()) {
151     result = load_reference_barrier_impl(access.gen(), result, LIR_OprFact::addressConst(0),
152                                          access.decorators());
153 
154     LIR_Opr tmp_barrier = gen->new_register(type);
155     __ move(result, tmp_barrier);
156     result = tmp_barrier;
157 
158     if (ShenandoahSATBBarrier) {
159       pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr, result);
160     }
161 
162     post_barrier(access, access.resolved_addr(), result);
163   }
164 
165   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
166     __ membar_acquire();
167   } else {
168     __ membar();
169   }
170 
171   return result;
172 }
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