61 #endif
62
63 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {
64 BasicType bt = access.type();
65 if (access.is_oop()) {
66 LIRGenerator *gen = access.gen();
67 if (ShenandoahSATBBarrier) {
68 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
69 LIR_OprFact::illegalOpr /* pre_val */);
70 }
71 if (ShenandoahCASBarrier) {
72 cmp_value.load_item();
73 new_value.load_item();
74
75 LIR_Opr tmp1 = gen->new_register(T_OBJECT);
76 LIR_Opr tmp2 = gen->new_register(T_OBJECT);
77 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
78 LIR_Opr result = gen->new_register(T_INT);
79
80 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), tmp1, tmp2, result));
81 return result;
82 }
83 }
84 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
85 }
86
87 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) {
88 LIRGenerator* gen = access.gen();
89 BasicType type = access.type();
90
91 LIR_Opr result = gen->new_register(type);
92 value.load_item();
93 LIR_Opr value_opr = value.result();
94
95 assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type");
96 LIR_Opr tmp = gen->new_register(T_INT);
97 __ xchg(access.resolved_addr(), value_opr, result, tmp);
98
99 if (access.is_oop()) {
100 result = load_reference_barrier(access.gen(), result, LIR_OprFact::addressConst(0), access.decorators());
101 LIR_Opr tmp_opr = gen->new_register(type);
102 __ move(result, tmp_opr);
103 result = tmp_opr;
104 if (ShenandoahSATBBarrier) {
105 pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr,
106 result /* pre_val */);
107 }
108 }
109
110 return result;
111 }
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61 #endif
62
63 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {
64 BasicType bt = access.type();
65 if (access.is_oop()) {
66 LIRGenerator *gen = access.gen();
67 if (ShenandoahSATBBarrier) {
68 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
69 LIR_OprFact::illegalOpr /* pre_val */);
70 }
71 if (ShenandoahCASBarrier) {
72 cmp_value.load_item();
73 new_value.load_item();
74
75 LIR_Opr tmp1 = gen->new_register(T_OBJECT);
76 LIR_Opr tmp2 = gen->new_register(T_OBJECT);
77 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
78 LIR_Opr result = gen->new_register(T_INT);
79
80 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), tmp1, tmp2, result));
81
82 if (ShenandoahCardBarrier) {
83 post_barrier(access, access.resolved_addr(), new_value.result());
84 }
85 return result;
86 }
87 }
88
89 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
90 }
91
92 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) {
93 LIRGenerator* gen = access.gen();
94 BasicType type = access.type();
95
96 LIR_Opr result = gen->new_register(type);
97 value.load_item();
98 LIR_Opr value_opr = value.result();
99
100 assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type");
101 LIR_Opr tmp = gen->new_register(T_INT);
102 __ xchg(access.resolved_addr(), value_opr, result, tmp);
103
104 if (access.is_oop()) {
105 result = load_reference_barrier(access.gen(), result, LIR_OprFact::addressConst(0), access.decorators());
106 LIR_Opr tmp_opr = gen->new_register(type);
107 __ move(result, tmp_opr);
108 result = tmp_opr;
109 if (ShenandoahSATBBarrier) {
110 pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr,
111 result /* pre_val */);
112 }
113 if (ShenandoahCardBarrier) {
114 post_barrier(access, access.resolved_addr(), result);
115 }
116 }
117
118 return result;
119 }
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