1 /*
2 * Copyright (c) 2018, 2021, Red Hat, Inc. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_LIRAssembler.hpp"
27 #include "c1/c1_MacroAssembler.hpp"
28 #include "gc/shared/gc_globals.hpp"
29 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
30 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
31 #include "gc/shenandoah/c1/shenandoahBarrierSetC1.hpp"
32
33 #define __ masm->masm()->
34
35 void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler* masm) {
36 NOT_LP64(assert(_addr->is_single_cpu(), "must be single");)
37 Register addr = _addr->is_single_cpu() ? _addr->as_register() : _addr->as_register_lo();
38 Register newval = _new_value->as_register();
39 Register cmpval = _cmp_value->as_register();
40 Register tmp1 = _tmp1->as_register();
41 Register tmp2 = _tmp2->as_register();
42 Register result = result_opr()->as_register();
43 assert(cmpval == rax, "wrong register");
44 assert(newval != noreg, "new val must be register");
45 assert(cmpval != newval, "cmp and new values must be in different registers");
46 assert(cmpval != addr, "cmp and addr must be in different registers");
47 assert(newval != addr, "new value and addr must be in different registers");
48
49 // Apply IU barrier to newval.
50 ShenandoahBarrierSet::assembler()->iu_barrier(masm->masm(), newval, tmp1);
51
52 #ifdef _LP64
53 if (UseCompressedOops) {
54 __ encode_heap_oop(cmpval);
55 __ mov(rscratch1, newval);
56 __ encode_heap_oop(rscratch1);
57 newval = rscratch1;
58 }
59 #endif
60
61 ShenandoahBarrierSet::assembler()->cmpxchg_oop(masm->masm(), result, Address(addr, 0), cmpval, newval, false, tmp1, tmp2);
62 }
63
64 #undef __
65
66 #ifdef ASSERT
67 #define __ gen->lir(__FILE__, __LINE__)->
68 #else
69 #define __ gen->lir()->
70 #endif
71
72 LIR_Opr ShenandoahBarrierSetC1::atomic_cmpxchg_at_resolved(LIRAccess& access, LIRItem& cmp_value, LIRItem& new_value) {
73
74 if (access.is_oop()) {
75 LIRGenerator* gen = access.gen();
76 if (ShenandoahSATBBarrier) {
77 pre_barrier(gen, access.access_emit_info(), access.decorators(), access.resolved_addr(),
78 LIR_OprFact::illegalOpr /* pre_val */);
79 }
80 if (ShenandoahCASBarrier) {
81 cmp_value.load_item_force(FrameMap::rax_oop_opr);
82 new_value.load_item();
83
84 LIR_Opr t1 = gen->new_register(T_OBJECT);
85 LIR_Opr t2 = gen->new_register(T_OBJECT);
86 LIR_Opr addr = access.resolved_addr()->as_address_ptr()->base();
87 LIR_Opr result = gen->new_register(T_INT);
88
89 __ append(new LIR_OpShenandoahCompareAndSwap(addr, cmp_value.result(), new_value.result(), t1, t2, result));
90 return result;
91 }
92 }
93 return BarrierSetC1::atomic_cmpxchg_at_resolved(access, cmp_value, new_value);
94 }
95
96 LIR_Opr ShenandoahBarrierSetC1::atomic_xchg_at_resolved(LIRAccess& access, LIRItem& value) {
97 LIRGenerator* gen = access.gen();
98 BasicType type = access.type();
99
100 LIR_Opr result = gen->new_register(type);
101 value.load_item();
102 LIR_Opr value_opr = value.result();
103
104 if (access.is_oop()) {
105 value_opr = iu_barrier(access.gen(), value_opr, access.access_emit_info(), access.decorators());
106 }
107
108 // Because we want a 2-arg form of xchg and xadd
109 __ move(value_opr, result);
110
111 assert(type == T_INT || is_reference_type(type) LP64_ONLY( || type == T_LONG ), "unexpected type");
112 __ xchg(access.resolved_addr(), result, result, LIR_OprFact::illegalOpr);
113
114 if (access.is_oop()) {
115 result = load_reference_barrier(access.gen(), result, LIR_OprFact::addressConst(0), access.decorators());
116 LIR_Opr tmp = gen->new_register(type);
117 __ move(result, tmp);
118 result = tmp;
119 if (ShenandoahSATBBarrier) {
120 pre_barrier(access.gen(), access.access_emit_info(), access.decorators(), LIR_OprFact::illegalOpr,
121 result /* pre_val */);
122 }
123 }
124
125 return result;
126 }