1 /*
2 * Copyright (c) 2000, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * Copyright 2026 Arm Limited and/or its affiliates.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "code/aotCodeCache.hpp"
38 #include "code/compiledIC.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "runtime/stubRoutines.hpp"
46 #include "runtime/threadIdentifier.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_aarch64.inline.hpp"
49
50
51 #ifndef PRODUCT
52 #define COMMENT(x) do { __ block_comment(x); } while (0)
53 #else
54 #define COMMENT(x)
55 #endif
56
57 NEEDS_CLEANUP // remove this definitions ?
58 const Register SYNC_header = r0; // synchronization header
59 const Register SHIFT_count = r0; // where count for shift operations must be
60
61 #define __ _masm->
62
63
64 static void select_different_registers(Register preserve,
65 Register extra,
66 Register &tmp1,
67 Register &tmp2,
68 Register &tmp3) {
69 if (tmp1 == preserve) {
70 assert_different_registers(tmp1, tmp2, tmp3, extra);
71 tmp1 = extra;
72 } else if (tmp2 == preserve) {
73 assert_different_registers(tmp1, tmp2, tmp3, extra);
74 tmp2 = extra;
75 } else if (tmp3 == preserve) {
76 assert_different_registers(tmp1, tmp2, tmp3, extra);
77 tmp3 = extra;
78 }
79 assert_different_registers(preserve, tmp1, tmp2, tmp3);
80 }
81
82
83 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
84
85
86 LIR_Opr LIR_Assembler::receiverOpr() {
87 return FrameMap::receiver_opr;
88 }
89
90 LIR_Opr LIR_Assembler::osrBufferPointer() {
91 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
92 }
93
94 //--------------fpu register translations-----------------------
95
96
97 address LIR_Assembler::float_constant(float f) {
98 address const_addr = __ float_constant(f);
99 if (const_addr == nullptr) {
100 bailout("const section overflow");
101 return __ code()->consts()->start();
102 } else {
103 return const_addr;
104 }
105 }
106
107
108 address LIR_Assembler::double_constant(double d) {
109 address const_addr = __ double_constant(d);
110 if (const_addr == nullptr) {
111 bailout("const section overflow");
112 return __ code()->consts()->start();
113 } else {
114 return const_addr;
115 }
116 }
117
118 address LIR_Assembler::int_constant(jlong n) {
119 address const_addr = __ long_constant(n);
120 if (const_addr == nullptr) {
121 bailout("const section overflow");
122 return __ code()->consts()->start();
123 } else {
124 return const_addr;
125 }
126 }
127
128 void LIR_Assembler::breakpoint() { Unimplemented(); }
129
130 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
131
132 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
133
134 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
135 //-------------------------------------------
136
137 static Register as_reg(LIR_Opr op) {
138 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
139 }
140
141 static jlong as_long(LIR_Opr data) {
142 jlong result;
143 switch (data->type()) {
144 case T_INT:
145 result = (data->as_jint());
146 break;
147 case T_LONG:
148 result = (data->as_jlong());
149 break;
150 default:
151 ShouldNotReachHere();
152 result = 0; // unreachable
153 }
154 return result;
155 }
156
157 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
158 Register base = addr->base()->as_pointer_register();
159 LIR_Opr opr = addr->index();
160 if (opr->is_cpu_register()) {
161 Register index;
162 if (opr->is_single_cpu())
163 index = opr->as_register();
164 else
165 index = opr->as_register_lo();
166 assert(addr->disp() == 0, "must be");
167 switch(opr->type()) {
168 case T_INT:
169 return Address(base, index, Address::sxtw(addr->scale()));
170 case T_LONG:
171 return Address(base, index, Address::lsl(addr->scale()));
172 default:
173 ShouldNotReachHere();
174 }
175 } else {
176 assert(addr->scale() == 0,
177 "expected for immediate operand, was: %d", addr->scale());
178 ptrdiff_t offset = ptrdiff_t(addr->disp());
179 // NOTE: Does not handle any 16 byte vector access.
180 const uint type_size = type2aelembytes(addr->type(), true);
181 return __ legitimize_address(Address(base, offset), type_size, tmp);
182 }
183 return Address();
184 }
185
186 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
187 ShouldNotReachHere();
188 return Address();
189 }
190
191 Address LIR_Assembler::as_Address(LIR_Address* addr) {
192 return as_Address(addr, rscratch1);
193 }
194
195 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
196 return as_Address(addr, rscratch1); // Ouch
197 // FIXME: This needs to be much more clever. See x86.
198 }
199
200 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
201 // not encodable as a base + (immediate) offset, generate an explicit address
202 // calculation to hold the address in a temporary register.
203 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
204 precond(size == 4 || size == 8);
205 Address addr = frame_map()->address_for_slot(index, adjust);
206 precond(addr.getMode() == Address::base_plus_offset);
207 precond(addr.base() == sp);
208 precond(addr.offset() > 0);
209 uint mask = size - 1;
210 assert((addr.offset() & mask) == 0, "scaled offsets only");
211 return __ legitimize_address(addr, size, tmp);
212 }
213
214 void LIR_Assembler::osr_entry() {
215 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
216 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
217 ValueStack* entry_state = osr_entry->state();
218 int number_of_locks = entry_state->locks_size();
219
220 // we jump here if osr happens with the interpreter
221 // state set up to continue at the beginning of the
222 // loop that triggered osr - in particular, we have
223 // the following registers setup:
224 //
225 // r2: osr buffer
226 //
227
228 // build frame
229 ciMethod* m = compilation()->method();
230 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
231
232 // OSR buffer is
233 //
234 // locals[nlocals-1..0]
235 // monitors[0..number_of_locks]
236 //
237 // locals is a direct copy of the interpreter frame so in the osr buffer
238 // so first slot in the local array is the last local from the interpreter
239 // and last slot is local[0] (receiver) from the interpreter
240 //
241 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
242 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
243 // in the interpreter frame (the method lock if a sync method)
244
245 // Initialize monitors in the compiled activation.
246 // r2: pointer to osr buffer
247 //
248 // All other registers are dead at this point and the locals will be
249 // copied into place by code emitted in the IR.
250
251 Register OSR_buf = osrBufferPointer()->as_pointer_register();
252 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
253 int monitor_offset = BytesPerWord * method()->max_locals() +
254 (2 * BytesPerWord) * (number_of_locks - 1);
255 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
256 // the OSR buffer using 2 word entries: first the lock and then
257 // the oop.
258 for (int i = 0; i < number_of_locks; i++) {
259 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
260 #ifdef ASSERT
261 // verify the interpreter's monitor has a non-null object
262 {
263 Label L;
264 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
265 __ cbnz(rscratch1, L);
266 __ stop("locked object is null");
267 __ bind(L);
268 }
269 #endif
270 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
271 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
272 __ str(r19, frame_map()->address_for_monitor_lock(i));
273 __ str(r20, frame_map()->address_for_monitor_object(i));
274 }
275 }
276 }
277
278
279 // inline cache check; done before the frame is built.
280 int LIR_Assembler::check_icache() {
281 return __ ic_check(CodeEntryAlignment);
282 }
283
284 void LIR_Assembler::clinit_barrier(ciMethod* method) {
285 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
286 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
287
288 Label L_skip_barrier;
289
290 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
291 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
292 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
293 __ bind(L_skip_barrier);
294 }
295
296 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
297 if (o == nullptr) {
298 __ mov(reg, zr);
299 } else {
300 __ movoop(reg, o);
301 }
302 }
303
304 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
305 address target = nullptr;
306 relocInfo::relocType reloc_type = relocInfo::none;
307
308 switch (patching_id(info)) {
309 case PatchingStub::access_field_id:
310 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
311 reloc_type = relocInfo::section_word_type;
312 break;
313 case PatchingStub::load_klass_id:
314 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
315 reloc_type = relocInfo::metadata_type;
316 break;
317 case PatchingStub::load_mirror_id:
318 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
319 reloc_type = relocInfo::oop_type;
320 break;
321 case PatchingStub::load_appendix_id:
322 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
323 reloc_type = relocInfo::oop_type;
324 break;
325 default: ShouldNotReachHere();
326 }
327
328 __ far_call(RuntimeAddress(target));
329 add_call_info_here(info);
330 }
331
332 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
333 deoptimize_trap(info);
334 }
335
336
337 // This specifies the rsp decrement needed to build the frame
338 int LIR_Assembler::initial_frame_size_in_bytes() const {
339 // if rounding, must let FrameMap know!
340
341 return in_bytes(frame_map()->framesize_in_bytes());
342 }
343
344
345 int LIR_Assembler::emit_exception_handler() {
346 // generate code for exception handler
347 address handler_base = __ start_a_stub(exception_handler_size());
348 if (handler_base == nullptr) {
349 // not enough space left for the handler
350 bailout("exception handler overflow");
351 return -1;
352 }
353
354 int offset = code_offset();
355
356 // the exception oop and pc are in r0, and r3
357 // no other registers need to be preserved, so invalidate them
358 __ invalidate_registers(false, true, true, false, true, true);
359
360 // check that there is really an exception
361 __ verify_not_null_oop(r0);
362
363 // search an exception handler (r0: exception oop, r3: throwing pc)
364 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
365 __ should_not_reach_here();
366 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
367 __ end_a_stub();
368
369 return offset;
370 }
371
372
373 // Emit the code to remove the frame from the stack in the exception
374 // unwind path.
375 int LIR_Assembler::emit_unwind_handler() {
376 #ifndef PRODUCT
377 if (CommentedAssembly) {
378 _masm->block_comment("Unwind handler");
379 }
380 #endif
381
382 int offset = code_offset();
383
384 // Fetch the exception from TLS and clear out exception related thread state
385 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
386 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
387 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
388
389 __ bind(_unwind_handler_entry);
390 __ verify_not_null_oop(r0);
391 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
392 __ mov(r19, r0); // Preserve the exception
393 }
394
395 // Perform needed unlocking
396 MonitorExitStub* stub = nullptr;
397 if (method()->is_synchronized()) {
398 monitor_address(0, FrameMap::r0_opr);
399 stub = new MonitorExitStub(FrameMap::r0_opr, 0);
400 __ unlock_object(r5, r4, r0, r6, *stub->entry());
401 __ bind(*stub->continuation());
402 }
403
404 if (compilation()->env()->dtrace_method_probes()) {
405 __ mov(c_rarg0, rthread);
406 __ mov_metadata(c_rarg1, method()->constant_encoding());
407 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
408 }
409
410 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
411 __ mov(r0, r19); // Restore the exception
412 }
413
414 // remove the activation and dispatch to the unwind handler
415 __ block_comment("remove_frame and dispatch to the unwind handler");
416 __ remove_frame(initial_frame_size_in_bytes());
417 __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
418
419 // Emit the slow path assembly
420 if (stub != nullptr) {
421 stub->emit_code(this);
422 }
423
424 return offset;
425 }
426
427
428 int LIR_Assembler::emit_deopt_handler() {
429 // generate code for exception handler
430 address handler_base = __ start_a_stub(deopt_handler_size());
431 if (handler_base == nullptr) {
432 // not enough space left for the handler
433 bailout("deopt handler overflow");
434 return -1;
435 }
436
437 int offset = code_offset();
438
439 Label start;
440 __ bind(start);
441
442 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
443
444 int entry_offset = __ offset();
445 __ b(start);
446
447 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
448 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
449 "out of bounds read in post-call NOP check");
450 __ end_a_stub();
451
452 return entry_offset;
453 }
454
455 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
456 _masm->code_section()->relocate(adr, relocInfo::poll_type);
457 int pc_offset = code_offset();
458 flush_debug_info(pc_offset);
459 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
460 if (info->exception_handlers() != nullptr) {
461 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
462 }
463 }
464
465 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
466 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
467
468 // Pop the stack before the safepoint code
469 __ remove_frame(initial_frame_size_in_bytes());
470
471 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
472 __ reserved_stack_check();
473 }
474
475 code_stub->set_safepoint_offset(__ offset());
476 __ relocate(relocInfo::poll_return_type);
477 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
478 __ ret(lr);
479 }
480
481 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
482 guarantee(info != nullptr, "Shouldn't be null");
483 __ get_polling_page(rscratch1, relocInfo::poll_type);
484 add_debug_info_for_branch(info); // This isn't just debug info:
485 // it's the oop map
486 __ read_polling_page(rscratch1, relocInfo::poll_type);
487 return __ offset();
488 }
489
490
491 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
492 if (from_reg == r31_sp)
493 from_reg = sp;
494 if (to_reg == r31_sp)
495 to_reg = sp;
496 __ mov(to_reg, from_reg);
497 }
498
499 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
500
501
502 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
503 assert(src->is_constant(), "should not call otherwise");
504 assert(dest->is_register(), "should not call otherwise");
505 LIR_Const* c = src->as_constant_ptr();
506
507 switch (c->type()) {
508 case T_INT: {
509 assert(patch_code == lir_patch_none, "no patching handled here");
510 __ movw(dest->as_register(), c->as_jint());
511 break;
512 }
513
514 case T_ADDRESS: {
515 assert(patch_code == lir_patch_none, "no patching handled here");
516 __ mov(dest->as_register(), c->as_jint());
517 break;
518 }
519
520 case T_LONG: {
521 assert(patch_code == lir_patch_none, "no patching handled here");
522 #if INCLUDE_CDS
523 if (AOTCodeCache::is_on_for_dump()) {
524 address b = c->as_pointer();
525 if (b == (address)ThreadIdentifier::unsafe_offset()) {
526 __ lea(dest->as_register_lo(), ExternalAddress(b));
527 break;
528 }
529 if (AOTRuntimeConstants::contains(b)) {
530 __ load_aotrc_address(dest->as_register_lo(), b);
531 break;
532 }
533 }
534 #endif
535 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
536 break;
537 }
538
539 case T_OBJECT: {
540 if (patch_code == lir_patch_none) {
541 jobject2reg(c->as_jobject(), dest->as_register());
542 } else {
543 jobject2reg_with_patching(dest->as_register(), info);
544 }
545 break;
546 }
547
548 case T_METADATA: {
549 if (patch_code != lir_patch_none) {
550 klass2reg_with_patching(dest->as_register(), info);
551 } else {
552 __ mov_metadata(dest->as_register(), c->as_metadata());
553 }
554 break;
555 }
556
557 case T_FLOAT: {
558 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
559 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
560 } else {
561 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
562 __ ldrs(dest->as_float_reg(), Address(rscratch1));
563 }
564 break;
565 }
566
567 case T_DOUBLE: {
568 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
569 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
570 } else {
571 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
572 __ ldrd(dest->as_double_reg(), Address(rscratch1));
573 }
574 break;
575 }
576
577 default:
578 ShouldNotReachHere();
579 }
580 }
581
582 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
583 LIR_Const* c = src->as_constant_ptr();
584 switch (c->type()) {
585 case T_OBJECT:
586 {
587 if (! c->as_jobject())
588 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
589 else {
590 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
591 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
592 }
593 }
594 break;
595 case T_ADDRESS:
596 {
597 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
598 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
599 }
600 case T_INT:
601 case T_FLOAT:
602 {
603 Register reg = zr;
604 if (c->as_jint_bits() == 0)
605 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
606 else {
607 __ movw(rscratch1, c->as_jint_bits());
608 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
609 }
610 }
611 break;
612 case T_LONG:
613 case T_DOUBLE:
614 {
615 Register reg = zr;
616 if (c->as_jlong_bits() == 0)
617 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
618 lo_word_offset_in_bytes));
619 else {
620 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
621 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
622 lo_word_offset_in_bytes));
623 }
624 }
625 break;
626 default:
627 ShouldNotReachHere();
628 }
629 }
630
631 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
632 assert(src->is_constant(), "should not call otherwise");
633 LIR_Const* c = src->as_constant_ptr();
634 LIR_Address* to_addr = dest->as_address_ptr();
635
636 void (Assembler::* insn)(Register Rt, const Address &adr);
637
638 switch (type) {
639 case T_ADDRESS:
640 assert(c->as_jint() == 0, "should be");
641 insn = &Assembler::str;
642 break;
643 case T_LONG:
644 assert(c->as_jlong() == 0, "should be");
645 insn = &Assembler::str;
646 break;
647 case T_INT:
648 assert(c->as_jint() == 0, "should be");
649 insn = &Assembler::strw;
650 break;
651 case T_OBJECT:
652 case T_ARRAY:
653 assert(c->as_jobject() == nullptr, "should be");
654 if (UseCompressedOops && !wide) {
655 insn = &Assembler::strw;
656 } else {
657 insn = &Assembler::str;
658 }
659 break;
660 case T_CHAR:
661 case T_SHORT:
662 assert(c->as_jint() == 0, "should be");
663 insn = &Assembler::strh;
664 break;
665 case T_BOOLEAN:
666 case T_BYTE:
667 assert(c->as_jint() == 0, "should be");
668 insn = &Assembler::strb;
669 break;
670 default:
671 ShouldNotReachHere();
672 insn = &Assembler::str; // unreachable
673 }
674
675 if (info) add_debug_info_for_null_check_here(info);
676 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
677 }
678
679 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
680 assert(src->is_register(), "should not call otherwise");
681 assert(dest->is_register(), "should not call otherwise");
682
683 // move between cpu-registers
684 if (dest->is_single_cpu()) {
685 if (src->type() == T_LONG) {
686 // Can do LONG -> OBJECT
687 move_regs(src->as_register_lo(), dest->as_register());
688 return;
689 }
690 assert(src->is_single_cpu(), "must match");
691 if (src->type() == T_OBJECT) {
692 __ verify_oop(src->as_register());
693 }
694 move_regs(src->as_register(), dest->as_register());
695
696 } else if (dest->is_double_cpu()) {
697 if (is_reference_type(src->type())) {
698 // Surprising to me but we can see move of a long to t_object
699 __ verify_oop(src->as_register());
700 move_regs(src->as_register(), dest->as_register_lo());
701 return;
702 }
703 assert(src->is_double_cpu(), "must match");
704 Register f_lo = src->as_register_lo();
705 Register f_hi = src->as_register_hi();
706 Register t_lo = dest->as_register_lo();
707 Register t_hi = dest->as_register_hi();
708 assert(f_hi == f_lo, "must be same");
709 assert(t_hi == t_lo, "must be same");
710 move_regs(f_lo, t_lo);
711
712 } else if (dest->is_single_fpu()) {
713 __ fmovs(dest->as_float_reg(), src->as_float_reg());
714
715 } else if (dest->is_double_fpu()) {
716 __ fmovd(dest->as_double_reg(), src->as_double_reg());
717
718 } else {
719 ShouldNotReachHere();
720 }
721 }
722
723 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
724 precond(src->is_register() && dest->is_stack());
725
726 uint const c_sz32 = sizeof(uint32_t);
727 uint const c_sz64 = sizeof(uint64_t);
728
729 if (src->is_single_cpu()) {
730 int index = dest->single_stack_ix();
731 if (is_reference_type(type)) {
732 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
733 __ verify_oop(src->as_register());
734 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
735 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
736 } else {
737 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
738 }
739
740 } else if (src->is_double_cpu()) {
741 int index = dest->double_stack_ix();
742 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
743 __ str(src->as_register_lo(), dest_addr_LO);
744
745 } else if (src->is_single_fpu()) {
746 int index = dest->single_stack_ix();
747 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
748
749 } else if (src->is_double_fpu()) {
750 int index = dest->double_stack_ix();
751 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
752
753 } else {
754 ShouldNotReachHere();
755 }
756 }
757
758
759 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
760 LIR_Address* to_addr = dest->as_address_ptr();
761 PatchingStub* patch = nullptr;
762 Register compressed_src = rscratch1;
763
764 if (patch_code != lir_patch_none) {
765 deoptimize_trap(info);
766 return;
767 }
768
769 if (is_reference_type(type)) {
770 __ verify_oop(src->as_register());
771
772 if (UseCompressedOops && !wide) {
773 __ encode_heap_oop(compressed_src, src->as_register());
774 } else {
775 compressed_src = src->as_register();
776 }
777 }
778
779 int null_check_here = code_offset();
780 switch (type) {
781 case T_FLOAT: {
782 __ strs(src->as_float_reg(), as_Address(to_addr));
783 break;
784 }
785
786 case T_DOUBLE: {
787 __ strd(src->as_double_reg(), as_Address(to_addr));
788 break;
789 }
790
791 case T_ARRAY: // fall through
792 case T_OBJECT: // fall through
793 if (UseCompressedOops && !wide) {
794 __ strw(compressed_src, as_Address(to_addr, rscratch2));
795 } else {
796 __ str(compressed_src, as_Address(to_addr));
797 }
798 break;
799 case T_METADATA:
800 // We get here to store a method pointer to the stack to pass to
801 // a dtrace runtime call. This can't work on 64 bit with
802 // compressed klass ptrs: T_METADATA can be a compressed klass
803 // ptr or a 64 bit method pointer.
804 ShouldNotReachHere();
805 __ str(src->as_register(), as_Address(to_addr));
806 break;
807 case T_ADDRESS:
808 __ str(src->as_register(), as_Address(to_addr));
809 break;
810 case T_INT:
811 __ strw(src->as_register(), as_Address(to_addr));
812 break;
813
814 case T_LONG: {
815 __ str(src->as_register_lo(), as_Address_lo(to_addr));
816 break;
817 }
818
819 case T_BYTE: // fall through
820 case T_BOOLEAN: {
821 __ strb(src->as_register(), as_Address(to_addr));
822 break;
823 }
824
825 case T_CHAR: // fall through
826 case T_SHORT:
827 __ strh(src->as_register(), as_Address(to_addr));
828 break;
829
830 default:
831 ShouldNotReachHere();
832 }
833 if (info != nullptr) {
834 add_debug_info_for_null_check(null_check_here, info);
835 }
836 }
837
838
839 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
840 precond(src->is_stack() && dest->is_register());
841
842 uint const c_sz32 = sizeof(uint32_t);
843 uint const c_sz64 = sizeof(uint64_t);
844
845 if (dest->is_single_cpu()) {
846 int index = src->single_stack_ix();
847 if (is_reference_type(type)) {
848 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
849 __ verify_oop(dest->as_register());
850 } else if (type == T_METADATA || type == T_ADDRESS) {
851 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
852 } else {
853 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
854 }
855
856 } else if (dest->is_double_cpu()) {
857 int index = src->double_stack_ix();
858 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
859 __ ldr(dest->as_register_lo(), src_addr_LO);
860
861 } else if (dest->is_single_fpu()) {
862 int index = src->single_stack_ix();
863 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
864
865 } else if (dest->is_double_fpu()) {
866 int index = src->double_stack_ix();
867 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
868
869 } else {
870 ShouldNotReachHere();
871 }
872 }
873
874
875 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
876 address target = nullptr;
877 relocInfo::relocType reloc_type = relocInfo::none;
878
879 switch (patching_id(info)) {
880 case PatchingStub::access_field_id:
881 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
882 reloc_type = relocInfo::section_word_type;
883 break;
884 case PatchingStub::load_klass_id:
885 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
886 reloc_type = relocInfo::metadata_type;
887 break;
888 case PatchingStub::load_mirror_id:
889 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
890 reloc_type = relocInfo::oop_type;
891 break;
892 case PatchingStub::load_appendix_id:
893 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
894 reloc_type = relocInfo::oop_type;
895 break;
896 default: ShouldNotReachHere();
897 }
898
899 __ far_call(RuntimeAddress(target));
900 add_call_info_here(info);
901 }
902
903 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
904
905 LIR_Opr temp;
906 if (type == T_LONG || type == T_DOUBLE)
907 temp = FrameMap::rscratch1_long_opr;
908 else
909 temp = FrameMap::rscratch1_opr;
910
911 stack2reg(src, temp, src->type());
912 reg2stack(temp, dest, dest->type());
913 }
914
915 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
916 LIR_PatchCode patch_code, CodeEmitInfo* info,
917 bool wide) {
918 mem2reg(src, dest, type, patch_code, info, wide, false);
919 }
920
921 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
922 LIR_PatchCode patch_code, CodeEmitInfo* info,
923 bool wide, bool is_volatile) {
924 LIR_Address* addr = src->as_address_ptr();
925 LIR_Address* from_addr = src->as_address_ptr();
926
927 if (addr->base()->type() == T_OBJECT) {
928 __ verify_oop(addr->base()->as_pointer_register());
929 }
930
931 if (patch_code != lir_patch_none) {
932 deoptimize_trap(info);
933 return;
934 }
935
936 if (is_volatile) {
937 load_volatile(from_addr, dest, type, info);
938 } else {
939 load_unordered(from_addr, dest, type, wide, info);
940 }
941
942 if (is_reference_type(type)) {
943 if (UseCompressedOops && !wide) {
944 __ decode_heap_oop(dest->as_register());
945 }
946
947 __ verify_oop(dest->as_register());
948 }
949 }
950
951 void LIR_Assembler::load_unordered(LIR_Address *from_addr, LIR_Opr dest,
952 BasicType type, bool wide, CodeEmitInfo* info) {
953 if (info != nullptr) {
954 add_debug_info_for_null_check_here(info);
955 }
956
957 switch (type) {
958 case T_FLOAT: {
959 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
960 break;
961 }
962
963 case T_DOUBLE: {
964 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
965 break;
966 }
967
968 case T_ARRAY: // fall through
969 case T_OBJECT: // fall through
970 if (UseCompressedOops && !wide) {
971 __ ldrw(dest->as_register(), as_Address(from_addr));
972 } else {
973 __ ldr(dest->as_register(), as_Address(from_addr));
974 }
975 break;
976 case T_METADATA:
977 // We get here to store a method pointer to the stack to pass to
978 // a dtrace runtime call. This can't work on 64 bit with
979 // compressed klass ptrs: T_METADATA can be a compressed klass
980 // ptr or a 64 bit method pointer.
981 ShouldNotReachHere();
982 __ ldr(dest->as_register(), as_Address(from_addr));
983 break;
984 case T_ADDRESS:
985 __ ldr(dest->as_register(), as_Address(from_addr));
986 break;
987 case T_INT:
988 __ ldrw(dest->as_register(), as_Address(from_addr));
989 break;
990
991 case T_LONG: {
992 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
993 break;
994 }
995
996 case T_BYTE:
997 __ ldrsb(dest->as_register(), as_Address(from_addr));
998 break;
999 case T_BOOLEAN: {
1000 __ ldrb(dest->as_register(), as_Address(from_addr));
1001 break;
1002 }
1003
1004 case T_CHAR:
1005 __ ldrh(dest->as_register(), as_Address(from_addr));
1006 break;
1007 case T_SHORT:
1008 __ ldrsh(dest->as_register(), as_Address(from_addr));
1009 break;
1010
1011 default:
1012 ShouldNotReachHere();
1013 }
1014 }
1015
1016 void LIR_Assembler::load_volatile(LIR_Address *from_addr, LIR_Opr dest,
1017 BasicType type, CodeEmitInfo* info) {
1018 __ lea(rscratch1, as_Address(from_addr));
1019
1020 Register dest_reg = rscratch2;
1021 if (!is_floating_point_type(type)) {
1022 dest_reg = (dest->is_single_cpu()
1023 ? dest->as_register() : dest->as_register_lo());
1024 }
1025
1026 if (info != nullptr) {
1027 add_debug_info_for_null_check_here(info);
1028 }
1029
1030 // Uses LDAR to ensure memory ordering.
1031 __ load_store_volatile(dest_reg, type, rscratch1, /*is_load*/true);
1032
1033 switch (type) {
1034 // LDAR is unsigned so need to sign-extend for byte and short
1035 case T_BYTE:
1036 __ sxtb(dest_reg, dest_reg);
1037 break;
1038 case T_SHORT:
1039 __ sxth(dest_reg, dest_reg);
1040 break;
1041 // need to move from GPR to FPR after LDAR with FMOV for floating types
1042 case T_FLOAT:
1043 __ fmovs(dest->as_float_reg(), dest_reg);
1044 break;
1045 case T_DOUBLE:
1046 __ fmovd(dest->as_double_reg(), dest_reg);
1047 break;
1048 default:
1049 break;
1050 }
1051 }
1052
1053 int LIR_Assembler::array_element_size(BasicType type) const {
1054 int elem_size = type2aelembytes(type);
1055 return exact_log2(elem_size);
1056 }
1057
1058
1059 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1060 switch (op->code()) {
1061 case lir_idiv:
1062 case lir_irem:
1063 arithmetic_idiv(op->code(),
1064 op->in_opr1(),
1065 op->in_opr2(),
1066 op->in_opr3(),
1067 op->result_opr(),
1068 op->info());
1069 break;
1070 case lir_fmad:
1071 __ fmaddd(op->result_opr()->as_double_reg(),
1072 op->in_opr1()->as_double_reg(),
1073 op->in_opr2()->as_double_reg(),
1074 op->in_opr3()->as_double_reg());
1075 break;
1076 case lir_fmaf:
1077 __ fmadds(op->result_opr()->as_float_reg(),
1078 op->in_opr1()->as_float_reg(),
1079 op->in_opr2()->as_float_reg(),
1080 op->in_opr3()->as_float_reg());
1081 break;
1082 default: ShouldNotReachHere(); break;
1083 }
1084 }
1085
1086 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1087 #ifdef ASSERT
1088 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1089 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1090 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1091 #endif
1092
1093 if (op->cond() == lir_cond_always) {
1094 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1095 __ b(*(op->label()));
1096 } else {
1097 Assembler::Condition acond;
1098 if (op->code() == lir_cond_float_branch) {
1099 bool is_unordered = (op->ublock() == op->block());
1100 // Assembler::EQ does not permit unordered branches, so we add
1101 // another branch here. Likewise, Assembler::NE does not permit
1102 // ordered branches.
1103 if ((is_unordered && op->cond() == lir_cond_equal)
1104 || (!is_unordered && op->cond() == lir_cond_notEqual))
1105 __ br(Assembler::VS, *(op->ublock()->label()));
1106 switch(op->cond()) {
1107 case lir_cond_equal: acond = Assembler::EQ; break;
1108 case lir_cond_notEqual: acond = Assembler::NE; break;
1109 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1110 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1111 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1112 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1113 default: ShouldNotReachHere();
1114 acond = Assembler::EQ; // unreachable
1115 }
1116 } else {
1117 switch (op->cond()) {
1118 case lir_cond_equal: acond = Assembler::EQ; break;
1119 case lir_cond_notEqual: acond = Assembler::NE; break;
1120 case lir_cond_less: acond = Assembler::LT; break;
1121 case lir_cond_lessEqual: acond = Assembler::LE; break;
1122 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1123 case lir_cond_greater: acond = Assembler::GT; break;
1124 case lir_cond_belowEqual: acond = Assembler::LS; break;
1125 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1126 default: ShouldNotReachHere();
1127 acond = Assembler::EQ; // unreachable
1128 }
1129 }
1130 __ br(acond,*(op->label()));
1131 }
1132 }
1133
1134
1135
1136 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1137 LIR_Opr src = op->in_opr();
1138 LIR_Opr dest = op->result_opr();
1139
1140 switch (op->bytecode()) {
1141 case Bytecodes::_i2f:
1142 {
1143 __ scvtfws(dest->as_float_reg(), src->as_register());
1144 break;
1145 }
1146 case Bytecodes::_i2d:
1147 {
1148 __ scvtfwd(dest->as_double_reg(), src->as_register());
1149 break;
1150 }
1151 case Bytecodes::_l2d:
1152 {
1153 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1154 break;
1155 }
1156 case Bytecodes::_l2f:
1157 {
1158 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1159 break;
1160 }
1161 case Bytecodes::_f2d:
1162 {
1163 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1164 break;
1165 }
1166 case Bytecodes::_d2f:
1167 {
1168 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1169 break;
1170 }
1171 case Bytecodes::_i2c:
1172 {
1173 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1174 break;
1175 }
1176 case Bytecodes::_i2l:
1177 {
1178 __ sxtw(dest->as_register_lo(), src->as_register());
1179 break;
1180 }
1181 case Bytecodes::_i2s:
1182 {
1183 __ sxth(dest->as_register(), src->as_register());
1184 break;
1185 }
1186 case Bytecodes::_i2b:
1187 {
1188 __ sxtb(dest->as_register(), src->as_register());
1189 break;
1190 }
1191 case Bytecodes::_l2i:
1192 {
1193 _masm->block_comment("FIXME: This could be a no-op");
1194 __ uxtw(dest->as_register(), src->as_register_lo());
1195 break;
1196 }
1197 case Bytecodes::_d2l:
1198 {
1199 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1200 break;
1201 }
1202 case Bytecodes::_f2i:
1203 {
1204 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1205 break;
1206 }
1207 case Bytecodes::_f2l:
1208 {
1209 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1210 break;
1211 }
1212 case Bytecodes::_d2i:
1213 {
1214 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1215 break;
1216 }
1217 default: ShouldNotReachHere();
1218 }
1219 }
1220
1221 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1222 if (op->init_check()) {
1223 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1224 __ ldarb(rscratch1, rscratch1);
1225 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1226 add_debug_info_for_null_check_here(op->stub()->info());
1227 __ br(Assembler::NE, *op->stub()->entry());
1228 }
1229 __ allocate_object(op->obj()->as_register(),
1230 op->tmp1()->as_register(),
1231 op->tmp2()->as_register(),
1232 op->header_size(),
1233 op->object_size(),
1234 op->klass()->as_register(),
1235 *op->stub()->entry());
1236 __ bind(*op->stub()->continuation());
1237 }
1238
1239 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1240 Register len = op->len()->as_register();
1241 __ uxtw(len, len);
1242
1243 if (UseSlowPath ||
1244 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1245 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1246 __ b(*op->stub()->entry());
1247 } else {
1248 Register tmp1 = op->tmp1()->as_register();
1249 Register tmp2 = op->tmp2()->as_register();
1250 Register tmp3 = op->tmp3()->as_register();
1251 if (len == tmp1) {
1252 tmp1 = tmp3;
1253 } else if (len == tmp2) {
1254 tmp2 = tmp3;
1255 } else if (len == tmp3) {
1256 // everything is ok
1257 } else {
1258 __ mov(tmp3, len);
1259 }
1260 __ allocate_array(op->obj()->as_register(),
1261 len,
1262 tmp1,
1263 tmp2,
1264 arrayOopDesc::base_offset_in_bytes(op->type()),
1265 array_element_size(op->type()),
1266 op->klass()->as_register(),
1267 *op->stub()->entry(),
1268 op->zero_array());
1269 }
1270 __ bind(*op->stub()->continuation());
1271 }
1272
1273 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md,
1274 ciProfileData *data, Register recv) {
1275
1276 int mdp_offset = md->byte_offset_of_slot(data, in_ByteSize(0));
1277 __ profile_receiver_type(recv, mdo, mdp_offset);
1278 }
1279
1280 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1281 // we always need a stub for the failure case.
1282 CodeStub* stub = op->stub();
1283 Register obj = op->object()->as_register();
1284 Register k_RInfo = op->tmp1()->as_register();
1285 Register klass_RInfo = op->tmp2()->as_register();
1286 Register dst = op->result_opr()->as_register();
1287 ciKlass* k = op->klass();
1288 Register Rtmp1 = noreg;
1289
1290 // check if it needs to be profiled
1291 ciMethodData* md;
1292 ciProfileData* data;
1293
1294 const bool should_profile = op->should_profile();
1295
1296 if (should_profile) {
1297 ciMethod* method = op->profiled_method();
1298 assert(method != nullptr, "Should have method");
1299 int bci = op->profiled_bci();
1300 md = method->method_data_or_null();
1301 assert(md != nullptr, "Sanity");
1302 data = md->bci_to_data(bci);
1303 assert(data != nullptr, "need data for type check");
1304 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1305 }
1306 Label* success_target = success;
1307 Label* failure_target = failure;
1308
1309 if (obj == k_RInfo) {
1310 k_RInfo = dst;
1311 } else if (obj == klass_RInfo) {
1312 klass_RInfo = dst;
1313 }
1314
1315 Rtmp1 = op->tmp3()->as_register();
1316 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1317
1318 assert_different_registers(obj, k_RInfo, klass_RInfo);
1319
1320 if (should_profile) {
1321 Register mdo = klass_RInfo;
1322 __ mov_metadata(mdo, md->constant_encoding());
1323 Label not_null;
1324 __ cbnz(obj, not_null);
1325 // Object is null; update MDO and exit
1326 Address data_addr
1327 = __ form_address(rscratch2, mdo,
1328 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1329 0);
1330 __ ldrb(rscratch1, data_addr);
1331 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1332 __ strb(rscratch1, data_addr);
1333 __ b(*obj_is_null);
1334 __ bind(not_null);
1335
1336 Register recv = k_RInfo;
1337 __ load_klass(recv, obj);
1338 type_profile_helper(mdo, md, data, recv);
1339 } else {
1340 __ cbz(obj, *obj_is_null);
1341 }
1342
1343 if (!k->is_loaded()) {
1344 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1345 } else {
1346 __ mov_metadata(k_RInfo, k->constant_encoding());
1347 }
1348 __ verify_oop(obj);
1349
1350 if (op->fast_check()) {
1351 // get object class
1352 // not a safepoint as obj null check happens earlier
1353 __ load_klass(rscratch1, obj);
1354 __ cmp( rscratch1, k_RInfo);
1355
1356 __ br(Assembler::NE, *failure_target);
1357 // successful cast, fall through to profile or jump
1358 } else {
1359 // get object class
1360 // not a safepoint as obj null check happens earlier
1361 __ load_klass(klass_RInfo, obj);
1362 if (k->is_loaded()) {
1363 // See if we get an immediate positive hit
1364 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1365 __ cmp(k_RInfo, rscratch1);
1366 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1367 __ br(Assembler::NE, *failure_target);
1368 // successful cast, fall through to profile or jump
1369 } else {
1370 // See if we get an immediate positive hit
1371 __ br(Assembler::EQ, *success_target);
1372 // check for self
1373 __ cmp(klass_RInfo, k_RInfo);
1374 __ br(Assembler::EQ, *success_target);
1375
1376 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1377 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1378 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1379 // result is a boolean
1380 __ cbzw(klass_RInfo, *failure_target);
1381 // successful cast, fall through to profile or jump
1382 }
1383 } else {
1384 // perform the fast part of the checking logic
1385 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1386 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1387 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1388 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1389 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1390 // result is a boolean
1391 __ cbz(k_RInfo, *failure_target);
1392 // successful cast, fall through to profile or jump
1393 }
1394 }
1395 __ b(*success);
1396 }
1397
1398
1399 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1400 const bool should_profile = op->should_profile();
1401
1402 LIR_Code code = op->code();
1403 if (code == lir_store_check) {
1404 Register value = op->object()->as_register();
1405 Register array = op->array()->as_register();
1406 Register k_RInfo = op->tmp1()->as_register();
1407 Register klass_RInfo = op->tmp2()->as_register();
1408 Register Rtmp1 = op->tmp3()->as_register();
1409
1410 CodeStub* stub = op->stub();
1411
1412 // check if it needs to be profiled
1413 ciMethodData* md;
1414 ciProfileData* data;
1415
1416 if (should_profile) {
1417 ciMethod* method = op->profiled_method();
1418 assert(method != nullptr, "Should have method");
1419 int bci = op->profiled_bci();
1420 md = method->method_data_or_null();
1421 assert(md != nullptr, "Sanity");
1422 data = md->bci_to_data(bci);
1423 assert(data != nullptr, "need data for type check");
1424 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1425 }
1426 Label done;
1427 Label* success_target = &done;
1428 Label* failure_target = stub->entry();
1429
1430 if (should_profile) {
1431 Label not_null;
1432 Register mdo = klass_RInfo;
1433 __ mov_metadata(mdo, md->constant_encoding());
1434 __ cbnz(value, not_null);
1435 // Object is null; update MDO and exit
1436 Address data_addr
1437 = __ form_address(rscratch2, mdo,
1438 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1439 __ ldrb(rscratch1, data_addr);
1440 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1441 __ strb(rscratch1, data_addr);
1442 __ b(done);
1443 __ bind(not_null);
1444
1445 Register recv = k_RInfo;
1446 __ load_klass(recv, value);
1447 type_profile_helper(mdo, md, data, recv);
1448 } else {
1449 __ cbz(value, done);
1450 }
1451
1452 add_debug_info_for_null_check_here(op->info_for_exception());
1453 __ load_klass(k_RInfo, array);
1454 __ load_klass(klass_RInfo, value);
1455
1456 // get instance klass (it's already uncompressed)
1457 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1458 // perform the fast part of the checking logic
1459 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1460 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1461 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1462 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1463 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1464 // result is a boolean
1465 __ cbzw(k_RInfo, *failure_target);
1466 // fall through to the success case
1467
1468 __ bind(done);
1469 } else if (code == lir_checkcast) {
1470 Register obj = op->object()->as_register();
1471 Register dst = op->result_opr()->as_register();
1472 Label success;
1473 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1474 __ bind(success);
1475 if (dst != obj) {
1476 __ mov(dst, obj);
1477 }
1478 } else if (code == lir_instanceof) {
1479 Register obj = op->object()->as_register();
1480 Register dst = op->result_opr()->as_register();
1481 Label success, failure, done;
1482 emit_typecheck_helper(op, &success, &failure, &failure);
1483 __ bind(failure);
1484 __ mov(dst, zr);
1485 __ b(done);
1486 __ bind(success);
1487 __ mov(dst, 1);
1488 __ bind(done);
1489 } else {
1490 ShouldNotReachHere();
1491 }
1492 }
1493
1494 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1495 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1496 __ cset(rscratch1, Assembler::NE);
1497 }
1498
1499 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1500 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1501 __ cset(rscratch1, Assembler::NE);
1502 }
1503
1504
1505 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1506 Register addr;
1507 if (op->addr()->is_register()) {
1508 addr = as_reg(op->addr());
1509 } else {
1510 assert(op->addr()->is_address(), "what else?");
1511 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1512 assert(addr_ptr->disp() == 0, "need 0 disp");
1513 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1514 addr = as_reg(addr_ptr->base());
1515 }
1516 Register newval = as_reg(op->new_value());
1517 Register cmpval = as_reg(op->cmp_value());
1518
1519 if (op->code() == lir_cas_obj) {
1520 if (UseCompressedOops) {
1521 Register t1 = op->tmp1()->as_register();
1522 assert(op->tmp1()->is_valid(), "must be");
1523 __ encode_heap_oop(t1, cmpval);
1524 cmpval = t1;
1525 __ encode_heap_oop(rscratch2, newval);
1526 newval = rscratch2;
1527 casw(addr, newval, cmpval);
1528 } else {
1529 casl(addr, newval, cmpval);
1530 }
1531 } else if (op->code() == lir_cas_int) {
1532 casw(addr, newval, cmpval);
1533 } else {
1534 casl(addr, newval, cmpval);
1535 }
1536 }
1537
1538
1539 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1540 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1541 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1542
1543 Assembler::Condition acond, ncond;
1544 switch (condition) {
1545 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1546 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1547 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1548 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1549 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1550 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1551 case lir_cond_belowEqual:
1552 case lir_cond_aboveEqual:
1553 default: ShouldNotReachHere();
1554 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1555 }
1556
1557 assert(result->is_single_cpu() || result->is_double_cpu(),
1558 "expect single register for result");
1559 if (opr1->is_constant() && opr2->is_constant()
1560 && opr1->type() == T_INT && opr2->type() == T_INT) {
1561 jint val1 = opr1->as_jint();
1562 jint val2 = opr2->as_jint();
1563 if (val1 == 0 && val2 == 1) {
1564 __ cset(result->as_register(), ncond);
1565 return;
1566 } else if (val1 == 1 && val2 == 0) {
1567 __ cset(result->as_register(), acond);
1568 return;
1569 }
1570 }
1571
1572 if (opr1->is_constant() && opr2->is_constant()
1573 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1574 jlong val1 = opr1->as_jlong();
1575 jlong val2 = opr2->as_jlong();
1576 if (val1 == 0 && val2 == 1) {
1577 __ cset(result->as_register_lo(), ncond);
1578 return;
1579 } else if (val1 == 1 && val2 == 0) {
1580 __ cset(result->as_register_lo(), acond);
1581 return;
1582 }
1583 }
1584
1585 if (opr1->is_stack()) {
1586 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1587 opr1 = FrameMap::rscratch1_opr;
1588 } else if (opr1->is_constant()) {
1589 LIR_Opr tmp
1590 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1591 const2reg(opr1, tmp, lir_patch_none, nullptr);
1592 opr1 = tmp;
1593 }
1594
1595 if (opr2->is_stack()) {
1596 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1597 opr2 = FrameMap::rscratch2_opr;
1598 } else if (opr2->is_constant()) {
1599 LIR_Opr tmp
1600 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1601 const2reg(opr2, tmp, lir_patch_none, nullptr);
1602 opr2 = tmp;
1603 }
1604
1605 if (result->type() == T_LONG)
1606 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1607 else
1608 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1609 }
1610
1611 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1612 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1613
1614 if (left->is_single_cpu()) {
1615 Register lreg = left->as_register();
1616 Register dreg = as_reg(dest);
1617
1618 if (right->is_single_cpu()) {
1619 // cpu register - cpu register
1620
1621 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1622 "should be");
1623 Register rreg = right->as_register();
1624 switch (code) {
1625 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1626 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1627 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1628 default: ShouldNotReachHere();
1629 }
1630
1631 } else if (right->is_double_cpu()) {
1632 Register rreg = right->as_register_lo();
1633 // single_cpu + double_cpu: can happen with obj+long
1634 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1635 switch (code) {
1636 case lir_add: __ add(dreg, lreg, rreg); break;
1637 case lir_sub: __ sub(dreg, lreg, rreg); break;
1638 default: ShouldNotReachHere();
1639 }
1640 } else if (right->is_constant()) {
1641 // cpu register - constant
1642 jlong c;
1643
1644 // FIXME. This is fugly: we really need to factor all this logic.
1645 switch(right->type()) {
1646 case T_LONG:
1647 c = right->as_constant_ptr()->as_jlong();
1648 break;
1649 case T_INT:
1650 case T_ADDRESS:
1651 c = right->as_constant_ptr()->as_jint();
1652 break;
1653 default:
1654 ShouldNotReachHere();
1655 c = 0; // unreachable
1656 break;
1657 }
1658
1659 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1660 if (c == 0 && dreg == lreg) {
1661 COMMENT("effective nop elided");
1662 return;
1663 }
1664 switch(left->type()) {
1665 case T_INT:
1666 switch (code) {
1667 case lir_add: __ addw(dreg, lreg, c); break;
1668 case lir_sub: __ subw(dreg, lreg, c); break;
1669 default: ShouldNotReachHere();
1670 }
1671 break;
1672 case T_OBJECT:
1673 case T_ADDRESS:
1674 switch (code) {
1675 case lir_add: __ add(dreg, lreg, c); break;
1676 case lir_sub: __ sub(dreg, lreg, c); break;
1677 default: ShouldNotReachHere();
1678 }
1679 break;
1680 default:
1681 ShouldNotReachHere();
1682 }
1683 } else {
1684 ShouldNotReachHere();
1685 }
1686
1687 } else if (left->is_double_cpu()) {
1688 Register lreg_lo = left->as_register_lo();
1689
1690 if (right->is_double_cpu()) {
1691 // cpu register - cpu register
1692 Register rreg_lo = right->as_register_lo();
1693 switch (code) {
1694 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1695 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1696 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1697 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1698 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1699 default:
1700 ShouldNotReachHere();
1701 }
1702
1703 } else if (right->is_constant()) {
1704 jlong c = right->as_constant_ptr()->as_jlong();
1705 Register dreg = as_reg(dest);
1706 switch (code) {
1707 case lir_add:
1708 case lir_sub:
1709 if (c == 0 && dreg == lreg_lo) {
1710 COMMENT("effective nop elided");
1711 return;
1712 }
1713 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1714 break;
1715 case lir_div:
1716 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1717 if (c == 1) {
1718 // move lreg_lo to dreg if divisor is 1
1719 __ mov(dreg, lreg_lo);
1720 } else {
1721 unsigned int shift = log2i_exact(c);
1722 // use rscratch1 as intermediate result register
1723 __ asr(rscratch1, lreg_lo, 63);
1724 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1725 __ asr(dreg, rscratch1, shift);
1726 }
1727 break;
1728 case lir_rem:
1729 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1730 if (c == 1) {
1731 // move 0 to dreg if divisor is 1
1732 __ mov(dreg, zr);
1733 } else {
1734 // use rscratch1 as intermediate result register
1735 __ negs(rscratch1, lreg_lo);
1736 __ andr(dreg, lreg_lo, c - 1);
1737 __ andr(rscratch1, rscratch1, c - 1);
1738 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1739 }
1740 break;
1741 default:
1742 ShouldNotReachHere();
1743 }
1744 } else {
1745 ShouldNotReachHere();
1746 }
1747 } else if (left->is_single_fpu()) {
1748 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1749 switch (code) {
1750 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1751 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1752 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1753 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1754 default:
1755 ShouldNotReachHere();
1756 }
1757 } else if (left->is_double_fpu()) {
1758 if (right->is_double_fpu()) {
1759 // fpu register - fpu register
1760 switch (code) {
1761 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1762 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1763 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1764 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1765 default:
1766 ShouldNotReachHere();
1767 }
1768 } else {
1769 if (right->is_constant()) {
1770 ShouldNotReachHere();
1771 }
1772 ShouldNotReachHere();
1773 }
1774 } else if (left->is_single_stack() || left->is_address()) {
1775 assert(left == dest, "left and dest must be equal");
1776 ShouldNotReachHere();
1777 } else {
1778 ShouldNotReachHere();
1779 }
1780 }
1781
1782 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1783 switch(code) {
1784 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1785 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1786 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1787 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1788 default : ShouldNotReachHere();
1789 }
1790 }
1791
1792 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1793
1794 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1795 Register Rleft = left->is_single_cpu() ? left->as_register() :
1796 left->as_register_lo();
1797 if (dst->is_single_cpu()) {
1798 Register Rdst = dst->as_register();
1799 if (right->is_constant()) {
1800 switch (code) {
1801 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1802 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1803 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1804 default: ShouldNotReachHere(); break;
1805 }
1806 } else {
1807 Register Rright = right->is_single_cpu() ? right->as_register() :
1808 right->as_register_lo();
1809 switch (code) {
1810 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1811 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1812 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1813 default: ShouldNotReachHere(); break;
1814 }
1815 }
1816 } else {
1817 Register Rdst = dst->as_register_lo();
1818 if (right->is_constant()) {
1819 switch (code) {
1820 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1821 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1822 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1823 default: ShouldNotReachHere(); break;
1824 }
1825 } else {
1826 Register Rright = right->is_single_cpu() ? right->as_register() :
1827 right->as_register_lo();
1828 switch (code) {
1829 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1830 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1831 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1832 default: ShouldNotReachHere(); break;
1833 }
1834 }
1835 }
1836 }
1837
1838
1839
1840 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1841
1842 // opcode check
1843 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1844 bool is_irem = (code == lir_irem);
1845
1846 // operand check
1847 assert(left->is_single_cpu(), "left must be register");
1848 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1849 assert(result->is_single_cpu(), "result must be register");
1850 Register lreg = left->as_register();
1851 Register dreg = result->as_register();
1852
1853 // power-of-2 constant check and codegen
1854 if (right->is_constant()) {
1855 int c = right->as_constant_ptr()->as_jint();
1856 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1857 if (is_irem) {
1858 if (c == 1) {
1859 // move 0 to dreg if divisor is 1
1860 __ movw(dreg, zr);
1861 } else {
1862 // use rscratch1 as intermediate result register
1863 __ negsw(rscratch1, lreg);
1864 __ andw(dreg, lreg, c - 1);
1865 __ andw(rscratch1, rscratch1, c - 1);
1866 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1867 }
1868 } else {
1869 if (c == 1) {
1870 // move lreg to dreg if divisor is 1
1871 __ movw(dreg, lreg);
1872 } else {
1873 unsigned int shift = exact_log2(c);
1874 // use rscratch1 as intermediate result register
1875 __ asrw(rscratch1, lreg, 31);
1876 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1877 __ asrw(dreg, rscratch1, shift);
1878 }
1879 }
1880 } else {
1881 Register rreg = right->as_register();
1882 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1883 }
1884 }
1885
1886
1887 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1888 if (opr1->is_constant() && opr2->is_single_cpu()) {
1889 // tableswitch
1890 Register reg = as_reg(opr2);
1891 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1892 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1893 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1894 Register reg1 = as_reg(opr1);
1895 if (opr2->is_single_cpu()) {
1896 // cpu register - cpu register
1897 Register reg2 = opr2->as_register();
1898 if (is_reference_type(opr1->type())) {
1899 __ cmpoop(reg1, reg2);
1900 } else {
1901 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1902 __ cmpw(reg1, reg2);
1903 }
1904 return;
1905 }
1906 if (opr2->is_double_cpu()) {
1907 // cpu register - cpu register
1908 Register reg2 = opr2->as_register_lo();
1909 __ cmp(reg1, reg2);
1910 return;
1911 }
1912
1913 if (opr2->is_constant()) {
1914 bool is_32bit = false; // width of register operand
1915 jlong imm;
1916
1917 switch(opr2->type()) {
1918 case T_INT:
1919 imm = opr2->as_constant_ptr()->as_jint();
1920 is_32bit = true;
1921 break;
1922 case T_LONG:
1923 imm = opr2->as_constant_ptr()->as_jlong();
1924 break;
1925 case T_ADDRESS:
1926 imm = opr2->as_constant_ptr()->as_jint();
1927 break;
1928 case T_METADATA:
1929 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1930 break;
1931 case T_OBJECT:
1932 case T_ARRAY:
1933 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1934 __ cmpoop(reg1, rscratch1);
1935 return;
1936 default:
1937 ShouldNotReachHere();
1938 imm = 0; // unreachable
1939 break;
1940 }
1941
1942 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1943 if (is_32bit)
1944 __ cmpw(reg1, imm);
1945 else
1946 __ subs(zr, reg1, imm);
1947 return;
1948 } else {
1949 __ mov(rscratch1, imm);
1950 if (is_32bit)
1951 __ cmpw(reg1, rscratch1);
1952 else
1953 __ cmp(reg1, rscratch1);
1954 return;
1955 }
1956 } else
1957 ShouldNotReachHere();
1958 } else if (opr1->is_single_fpu()) {
1959 FloatRegister reg1 = opr1->as_float_reg();
1960 assert(opr2->is_single_fpu(), "expect single float register");
1961 FloatRegister reg2 = opr2->as_float_reg();
1962 __ fcmps(reg1, reg2);
1963 } else if (opr1->is_double_fpu()) {
1964 FloatRegister reg1 = opr1->as_double_reg();
1965 assert(opr2->is_double_fpu(), "expect double float register");
1966 FloatRegister reg2 = opr2->as_double_reg();
1967 __ fcmpd(reg1, reg2);
1968 } else {
1969 ShouldNotReachHere();
1970 }
1971 }
1972
1973 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1974 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1975 bool is_unordered_less = (code == lir_ucmp_fd2i);
1976 if (left->is_single_fpu()) {
1977 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1978 } else if (left->is_double_fpu()) {
1979 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1980 } else {
1981 ShouldNotReachHere();
1982 }
1983 } else if (code == lir_cmp_l2i) {
1984 Label done;
1985 __ cmp(left->as_register_lo(), right->as_register_lo());
1986 __ mov(dst->as_register(), (uint64_t)-1L);
1987 __ br(Assembler::LT, done);
1988 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1989 __ bind(done);
1990 } else {
1991 ShouldNotReachHere();
1992 }
1993 }
1994
1995
1996 void LIR_Assembler::align_call(LIR_Code code) { }
1997
1998
1999 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2000 address call = __ trampoline_call(Address(op->addr(), rtype));
2001 if (call == nullptr) {
2002 bailout("trampoline stub overflow");
2003 return;
2004 }
2005 add_call_info(code_offset(), op->info());
2006 __ post_call_nop();
2007 }
2008
2009
2010 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2011 address call = __ ic_call(op->addr());
2012 if (call == nullptr) {
2013 bailout("trampoline stub overflow");
2014 return;
2015 }
2016 add_call_info(code_offset(), op->info());
2017 __ post_call_nop();
2018 }
2019
2020 void LIR_Assembler::emit_static_call_stub() {
2021 address call_pc = __ pc();
2022 address stub = __ start_a_stub(call_stub_size());
2023 if (stub == nullptr) {
2024 bailout("static call stub overflow");
2025 return;
2026 }
2027
2028 int start = __ offset();
2029
2030 __ relocate(static_stub_Relocation::spec(call_pc));
2031 __ emit_static_call_stub();
2032
2033 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2034 <= call_stub_size(), "stub too big");
2035 __ end_a_stub();
2036 }
2037
2038
2039 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2040 assert(exceptionOop->as_register() == r0, "must match");
2041 assert(exceptionPC->as_register() == r3, "must match");
2042
2043 // exception object is not added to oop map by LinearScan
2044 // (LinearScan assumes that no oops are in fixed registers)
2045 info->add_register_oop(exceptionOop);
2046 StubId unwind_id;
2047
2048 // get current pc information
2049 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2050 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2051 // As no instructions have been generated yet for this LIR node it's
2052 // possible that an oop map already exists for the current offset.
2053 // In that case insert an dummy NOP here to ensure all oop map PCs
2054 // are unique. See JDK-8237483.
2055 __ nop();
2056 }
2057 int pc_for_athrow_offset = __ offset();
2058 InternalAddress pc_for_athrow(__ pc());
2059 __ adr(exceptionPC->as_register(), pc_for_athrow);
2060 add_call_info(pc_for_athrow_offset, info); // for exception handler
2061
2062 __ verify_not_null_oop(r0);
2063 // search an exception handler (r0: exception oop, r3: throwing pc)
2064 if (compilation()->has_fpu_code()) {
2065 unwind_id = StubId::c1_handle_exception_id;
2066 } else {
2067 unwind_id = StubId::c1_handle_exception_nofpu_id;
2068 }
2069 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2070
2071 // FIXME: enough room for two byte trap ????
2072 __ nop();
2073 }
2074
2075
2076 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2077 assert(exceptionOop->as_register() == r0, "must match");
2078
2079 __ b(_unwind_handler_entry);
2080 }
2081
2082
2083 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2084 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2085 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2086
2087 switch (left->type()) {
2088 case T_INT: {
2089 switch (code) {
2090 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2091 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2092 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2093 default:
2094 ShouldNotReachHere();
2095 break;
2096 }
2097 break;
2098 case T_LONG:
2099 case T_ADDRESS:
2100 case T_OBJECT:
2101 switch (code) {
2102 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2103 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2104 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2105 default:
2106 ShouldNotReachHere();
2107 break;
2108 }
2109 break;
2110 default:
2111 ShouldNotReachHere();
2112 break;
2113 }
2114 }
2115 }
2116
2117
2118 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2119 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2120 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2121
2122 switch (left->type()) {
2123 case T_INT: {
2124 switch (code) {
2125 case lir_shl: __ lslw (dreg, lreg, count); break;
2126 case lir_shr: __ asrw (dreg, lreg, count); break;
2127 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2128 default:
2129 ShouldNotReachHere();
2130 break;
2131 }
2132 break;
2133 case T_LONG:
2134 case T_ADDRESS:
2135 case T_OBJECT:
2136 switch (code) {
2137 case lir_shl: __ lsl (dreg, lreg, count); break;
2138 case lir_shr: __ asr (dreg, lreg, count); break;
2139 case lir_ushr: __ lsr (dreg, lreg, count); break;
2140 default:
2141 ShouldNotReachHere();
2142 break;
2143 }
2144 break;
2145 default:
2146 ShouldNotReachHere();
2147 break;
2148 }
2149 }
2150 }
2151
2152
2153 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2154 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2155 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2156 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2157 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2158 }
2159
2160
2161 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2162 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2163 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2164 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2165 __ mov (rscratch1, c);
2166 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2167 }
2168
2169
2170 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2171 ShouldNotReachHere();
2172 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2173 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2174 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2175 __ lea(rscratch1, __ constant_oop_address(o));
2176 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2177 }
2178
2179
2180 // This code replaces a call to arraycopy; no exception may
2181 // be thrown in this code, they must be thrown in the System.arraycopy
2182 // activation frame; we could save some checks if this would not be the case
2183 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2184 ciArrayKlass* default_type = op->expected_type();
2185 Register src = op->src()->as_register();
2186 Register dst = op->dst()->as_register();
2187 Register src_pos = op->src_pos()->as_register();
2188 Register dst_pos = op->dst_pos()->as_register();
2189 Register length = op->length()->as_register();
2190 Register tmp = op->tmp()->as_register();
2191
2192 CodeStub* stub = op->stub();
2193 int flags = op->flags();
2194 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2195 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2196
2197 // if we don't know anything, just go through the generic arraycopy
2198 if (default_type == nullptr // || basic_type == T_OBJECT
2199 ) {
2200 Label done;
2201 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2202
2203 // Save the arguments in case the generic arraycopy fails and we
2204 // have to fall back to the JNI stub
2205 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2206 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2207 __ str(src, Address(sp, 4*BytesPerWord));
2208
2209 address copyfunc_addr = StubRoutines::generic_arraycopy();
2210 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2211
2212 // The arguments are in java calling convention so we shift them
2213 // to C convention
2214 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2215 __ mov(c_rarg0, j_rarg0);
2216 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2217 __ mov(c_rarg1, j_rarg1);
2218 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2219 __ mov(c_rarg2, j_rarg2);
2220 assert_different_registers(c_rarg3, j_rarg4);
2221 __ mov(c_rarg3, j_rarg3);
2222 __ mov(c_rarg4, j_rarg4);
2223 #ifndef PRODUCT
2224 if (PrintC1Statistics) {
2225 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2226 }
2227 #endif
2228 __ far_call(RuntimeAddress(copyfunc_addr));
2229
2230 __ cbz(r0, *stub->continuation());
2231
2232 // Reload values from the stack so they are where the stub
2233 // expects them.
2234 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2235 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2236 __ ldr(src, Address(sp, 4*BytesPerWord));
2237
2238 // r0 is -1^K where K == partial copied count
2239 __ eonw(rscratch1, r0, zr);
2240 // adjust length down and src/end pos up by partial copied count
2241 __ subw(length, length, rscratch1);
2242 __ addw(src_pos, src_pos, rscratch1);
2243 __ addw(dst_pos, dst_pos, rscratch1);
2244 __ b(*stub->entry());
2245
2246 __ bind(*stub->continuation());
2247 return;
2248 }
2249
2250 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2251
2252 int elem_size = type2aelembytes(basic_type);
2253 int scale = exact_log2(elem_size);
2254
2255 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2256 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2257
2258 // test for null
2259 if (flags & LIR_OpArrayCopy::src_null_check) {
2260 __ cbz(src, *stub->entry());
2261 }
2262 if (flags & LIR_OpArrayCopy::dst_null_check) {
2263 __ cbz(dst, *stub->entry());
2264 }
2265
2266 // If the compiler was not able to prove that exact type of the source or the destination
2267 // of the arraycopy is an array type, check at runtime if the source or the destination is
2268 // an instance type.
2269 if (flags & LIR_OpArrayCopy::type_check) {
2270 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2271 __ load_klass(tmp, dst);
2272 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2273 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2274 __ br(Assembler::GE, *stub->entry());
2275 }
2276
2277 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2278 __ load_klass(tmp, src);
2279 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2280 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2281 __ br(Assembler::GE, *stub->entry());
2282 }
2283 }
2284
2285 // check if negative
2286 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2287 __ cmpw(src_pos, 0);
2288 __ br(Assembler::LT, *stub->entry());
2289 }
2290 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2291 __ cmpw(dst_pos, 0);
2292 __ br(Assembler::LT, *stub->entry());
2293 }
2294
2295 if (flags & LIR_OpArrayCopy::length_positive_check) {
2296 __ cmpw(length, 0);
2297 __ br(Assembler::LT, *stub->entry());
2298 }
2299
2300 if (flags & LIR_OpArrayCopy::src_range_check) {
2301 __ addw(tmp, src_pos, length);
2302 __ ldrw(rscratch1, src_length_addr);
2303 __ cmpw(tmp, rscratch1);
2304 __ br(Assembler::HI, *stub->entry());
2305 }
2306 if (flags & LIR_OpArrayCopy::dst_range_check) {
2307 __ addw(tmp, dst_pos, length);
2308 __ ldrw(rscratch1, dst_length_addr);
2309 __ cmpw(tmp, rscratch1);
2310 __ br(Assembler::HI, *stub->entry());
2311 }
2312
2313 if (flags & LIR_OpArrayCopy::type_check) {
2314 // We don't know the array types are compatible
2315 if (basic_type != T_OBJECT) {
2316 // Simple test for basic type arrays
2317 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2318 __ br(Assembler::NE, *stub->entry());
2319 } else {
2320 // For object arrays, if src is a sub class of dst then we can
2321 // safely do the copy.
2322 Label cont, slow;
2323
2324 #define PUSH(r1, r2) \
2325 stp(r1, r2, __ pre(sp, -2 * wordSize));
2326
2327 #define POP(r1, r2) \
2328 ldp(r1, r2, __ post(sp, 2 * wordSize));
2329
2330 __ PUSH(src, dst);
2331
2332 __ load_klass(src, src);
2333 __ load_klass(dst, dst);
2334
2335 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2336
2337 __ PUSH(src, dst);
2338 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2339 __ POP(src, dst);
2340
2341 __ cbnz(src, cont);
2342
2343 __ bind(slow);
2344 __ POP(src, dst);
2345
2346 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2347 if (copyfunc_addr != nullptr) { // use stub if available
2348 // src is not a sub class of dst so we have to do a
2349 // per-element check.
2350
2351 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2352 if ((flags & mask) != mask) {
2353 // Check that at least both of them object arrays.
2354 assert(flags & mask, "one of the two should be known to be an object array");
2355
2356 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2357 __ load_klass(tmp, src);
2358 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2359 __ load_klass(tmp, dst);
2360 }
2361 int lh_offset = in_bytes(Klass::layout_helper_offset());
2362 Address klass_lh_addr(tmp, lh_offset);
2363 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2364 __ ldrw(rscratch1, klass_lh_addr);
2365 __ mov(rscratch2, objArray_lh);
2366 __ eorw(rscratch1, rscratch1, rscratch2);
2367 __ cbnzw(rscratch1, *stub->entry());
2368 }
2369
2370 // Spill because stubs can use any register they like and it's
2371 // easier to restore just those that we care about.
2372 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2373 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2374 __ str(src, Address(sp, 4*BytesPerWord));
2375
2376 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2377 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2378 assert_different_registers(c_rarg0, dst, dst_pos, length);
2379 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2380 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2381 assert_different_registers(c_rarg1, dst, length);
2382 __ uxtw(c_rarg2, length);
2383 assert_different_registers(c_rarg2, dst);
2384
2385 __ load_klass(c_rarg4, dst);
2386 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2387 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2388 __ far_call(RuntimeAddress(copyfunc_addr));
2389
2390 #ifndef PRODUCT
2391 if (PrintC1Statistics) {
2392 Label failed;
2393 __ cbnz(r0, failed);
2394 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2395 __ bind(failed);
2396 }
2397 #endif
2398
2399 __ cbz(r0, *stub->continuation());
2400
2401 #ifndef PRODUCT
2402 if (PrintC1Statistics) {
2403 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2404 }
2405 #endif
2406 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2407
2408 // Restore previously spilled arguments
2409 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2410 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2411 __ ldr(src, Address(sp, 4*BytesPerWord));
2412
2413 // return value is -1^K where K is partial copied count
2414 __ eonw(rscratch1, r0, zr);
2415 // adjust length down and src/end pos up by partial copied count
2416 __ subw(length, length, rscratch1);
2417 __ addw(src_pos, src_pos, rscratch1);
2418 __ addw(dst_pos, dst_pos, rscratch1);
2419 }
2420
2421 __ b(*stub->entry());
2422
2423 __ bind(cont);
2424 __ POP(src, dst);
2425 }
2426 }
2427
2428 #ifdef ASSERT
2429 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2430 // Sanity check the known type with the incoming class. For the
2431 // primitive case the types must match exactly with src.klass and
2432 // dst.klass each exactly matching the default type. For the
2433 // object array case, if no type check is needed then either the
2434 // dst type is exactly the expected type and the src type is a
2435 // subtype which we can't check or src is the same array as dst
2436 // but not necessarily exactly of type default_type.
2437 Label known_ok, halt;
2438 __ mov_metadata(tmp, default_type->constant_encoding());
2439
2440 if (basic_type != T_OBJECT) {
2441 __ cmp_klass(dst, tmp, rscratch1);
2442 __ br(Assembler::NE, halt);
2443 __ cmp_klass(src, tmp, rscratch1);
2444 __ br(Assembler::EQ, known_ok);
2445 } else {
2446 __ cmp_klass(dst, tmp, rscratch1);
2447 __ br(Assembler::EQ, known_ok);
2448 __ cmp(src, dst);
2449 __ br(Assembler::EQ, known_ok);
2450 }
2451 __ bind(halt);
2452 __ stop("incorrect type information in arraycopy");
2453 __ bind(known_ok);
2454 }
2455 #endif
2456
2457 #ifndef PRODUCT
2458 if (PrintC1Statistics) {
2459 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2460 }
2461 #endif
2462
2463 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2464 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2465 assert_different_registers(c_rarg0, dst, dst_pos, length);
2466 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2467 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2468 assert_different_registers(c_rarg1, dst, length);
2469 __ uxtw(c_rarg2, length);
2470 assert_different_registers(c_rarg2, dst);
2471
2472 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2473 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2474 const char *name;
2475 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2476
2477 CodeBlob *cb = CodeCache::find_blob(entry);
2478 if (cb) {
2479 __ far_call(RuntimeAddress(entry));
2480 } else {
2481 __ call_VM_leaf(entry, 3);
2482 }
2483
2484 if (stub != nullptr) {
2485 __ bind(*stub->continuation());
2486 }
2487 }
2488
2489
2490
2491
2492 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2493 Register obj = op->obj_opr()->as_register(); // may not be an oop
2494 Register hdr = op->hdr_opr()->as_register();
2495 Register lock = op->lock_opr()->as_register();
2496 Register temp = op->scratch_opr()->as_register();
2497 if (op->code() == lir_lock) {
2498 // add debug info for NullPointerException only if one is possible
2499 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2500 if (op->info() != nullptr) {
2501 add_debug_info_for_null_check(null_check_offset, op->info());
2502 }
2503 // done
2504 } else if (op->code() == lir_unlock) {
2505 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2506 } else {
2507 Unimplemented();
2508 }
2509 __ bind(*op->stub()->continuation());
2510 }
2511
2512 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2513 Register obj = op->obj()->as_pointer_register();
2514 Register result = op->result_opr()->as_pointer_register();
2515
2516 CodeEmitInfo* info = op->info();
2517 if (info != nullptr) {
2518 add_debug_info_for_null_check_here(info);
2519 }
2520
2521 __ load_klass(result, obj);
2522 }
2523
2524 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2525 ciMethod* method = op->profiled_method();
2526 int bci = op->profiled_bci();
2527 ciMethod* callee = op->profiled_callee();
2528
2529 // Update counter for all call types
2530 ciMethodData* md = method->method_data_or_null();
2531 assert(md != nullptr, "Sanity");
2532 ciProfileData* data = md->bci_to_data(bci);
2533 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2534 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2535 Register mdo = op->mdo()->as_register();
2536 __ mov_metadata(mdo, md->constant_encoding());
2537 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2538 // Perform additional virtual call profiling for invokevirtual and
2539 // invokeinterface bytecodes
2540 if (op->should_profile_receiver_type()) {
2541 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2542 Register recv = op->recv()->as_register();
2543 assert_different_registers(mdo, recv);
2544 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2545 ciKlass* known_klass = op->known_holder();
2546 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2547 // We know the type that will be seen at this call site; we can
2548 // statically update the MethodData* rather than needing to do
2549 // dynamic tests on the receiver type.
2550 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2551 for (uint i = 0; i < VirtualCallData::row_limit(); i++) {
2552 ciKlass* receiver = vc_data->receiver(i);
2553 if (known_klass->equals(receiver)) {
2554 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2555 __ addptr(data_addr, DataLayout::counter_increment);
2556 return;
2557 }
2558 }
2559 // Receiver type is not found in profile data.
2560 // Fall back to runtime helper to handle the rest at runtime.
2561 __ mov_metadata(recv, known_klass->constant_encoding());
2562 } else {
2563 __ load_klass(recv, recv);
2564 }
2565 type_profile_helper(mdo, md, data, recv);
2566 } else {
2567 // Static call
2568 __ addptr(counter_addr, DataLayout::counter_increment);
2569 }
2570 }
2571
2572
2573 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2574 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2575 }
2576
2577 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2578 assert(op->crc()->is_single_cpu(), "crc must be register");
2579 assert(op->val()->is_single_cpu(), "byte value must be register");
2580 assert(op->result_opr()->is_single_cpu(), "result must be register");
2581 Register crc = op->crc()->as_register();
2582 Register val = op->val()->as_register();
2583 Register res = op->result_opr()->as_register();
2584
2585 assert_different_registers(val, crc, res);
2586 uint64_t offset;
2587 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2588 __ add(res, res, offset);
2589
2590 __ mvnw(crc, crc); // ~crc
2591 __ update_byte_crc32(crc, val, res);
2592 __ mvnw(res, crc); // ~crc
2593 }
2594
2595 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2596 COMMENT("emit_profile_type {");
2597 Register obj = op->obj()->as_register();
2598 Register tmp = op->tmp()->as_pointer_register();
2599 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2600 ciKlass* exact_klass = op->exact_klass();
2601 intptr_t current_klass = op->current_klass();
2602 bool not_null = op->not_null();
2603 bool no_conflict = op->no_conflict();
2604
2605 Label update, next, none;
2606
2607 bool do_null = !not_null;
2608 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2609 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2610
2611 assert(do_null || do_update, "why are we here?");
2612 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2613 assert(mdo_addr.base() != rscratch1, "wrong register");
2614
2615 __ verify_oop(obj);
2616
2617 if (tmp != obj) {
2618 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2619 __ mov(tmp, obj);
2620 } else {
2621 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2622 }
2623 if (do_null) {
2624 __ cbnz(tmp, update);
2625 if (!TypeEntries::was_null_seen(current_klass)) {
2626 __ ldr(rscratch2, mdo_addr);
2627 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2628 __ str(rscratch2, mdo_addr);
2629 }
2630 if (do_update) {
2631 #ifndef ASSERT
2632 __ b(next);
2633 }
2634 #else
2635 __ b(next);
2636 }
2637 } else {
2638 __ cbnz(tmp, update);
2639 __ stop("unexpected null obj");
2640 #endif
2641 }
2642
2643 __ bind(update);
2644
2645 if (do_update) {
2646 #ifdef ASSERT
2647 if (exact_klass != nullptr) {
2648 Label ok;
2649 __ load_klass(tmp, tmp);
2650 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2651 __ eor(rscratch1, tmp, rscratch1);
2652 __ cbz(rscratch1, ok);
2653 __ stop("exact klass and actual klass differ");
2654 __ bind(ok);
2655 }
2656 #endif
2657 if (!no_conflict) {
2658 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2659 if (exact_klass != nullptr) {
2660 __ mov_metadata(tmp, exact_klass->constant_encoding());
2661 } else {
2662 __ load_klass(tmp, tmp);
2663 }
2664
2665 __ ldr(rscratch2, mdo_addr);
2666 __ eor(tmp, tmp, rscratch2);
2667 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2668 // klass seen before, nothing to do. The unknown bit may have been
2669 // set already but no need to check.
2670 __ cbz(rscratch1, next);
2671
2672 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2673
2674 if (TypeEntries::is_type_none(current_klass)) {
2675 __ cbz(rscratch2, none);
2676 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2677 __ br(Assembler::EQ, none);
2678 // There is a chance that the checks above
2679 // fail if another thread has just set the
2680 // profiling to this obj's klass
2681 __ dmb(Assembler::ISHLD);
2682 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2683 __ ldr(rscratch2, mdo_addr);
2684 __ eor(tmp, tmp, rscratch2);
2685 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2686 __ cbz(rscratch1, next);
2687 }
2688 } else {
2689 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2690 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2691
2692 __ ldr(tmp, mdo_addr);
2693 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2694 }
2695
2696 // different than before. Cannot keep accurate profile.
2697 __ ldr(rscratch2, mdo_addr);
2698 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2699 __ str(rscratch2, mdo_addr);
2700
2701 if (TypeEntries::is_type_none(current_klass)) {
2702 __ b(next);
2703
2704 __ bind(none);
2705 // first time here. Set profile type.
2706 __ str(tmp, mdo_addr);
2707 #ifdef ASSERT
2708 __ andr(tmp, tmp, TypeEntries::type_mask);
2709 __ verify_klass_ptr(tmp);
2710 #endif
2711 }
2712 } else {
2713 // There's a single possible klass at this profile point
2714 assert(exact_klass != nullptr, "should be");
2715 if (TypeEntries::is_type_none(current_klass)) {
2716 __ mov_metadata(tmp, exact_klass->constant_encoding());
2717 __ ldr(rscratch2, mdo_addr);
2718 __ eor(tmp, tmp, rscratch2);
2719 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2720 __ cbz(rscratch1, next);
2721 #ifdef ASSERT
2722 {
2723 Label ok;
2724 __ ldr(rscratch1, mdo_addr);
2725 __ cbz(rscratch1, ok);
2726 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2727 __ br(Assembler::EQ, ok);
2728 // may have been set by another thread
2729 __ dmb(Assembler::ISHLD);
2730 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2731 __ ldr(rscratch2, mdo_addr);
2732 __ eor(rscratch2, rscratch1, rscratch2);
2733 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2734 __ cbz(rscratch2, ok);
2735
2736 __ stop("unexpected profiling mismatch");
2737 __ bind(ok);
2738 }
2739 #endif
2740 // first time here. Set profile type.
2741 __ str(tmp, mdo_addr);
2742 #ifdef ASSERT
2743 __ andr(tmp, tmp, TypeEntries::type_mask);
2744 __ verify_klass_ptr(tmp);
2745 #endif
2746 } else {
2747 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2748 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2749
2750 __ ldr(tmp, mdo_addr);
2751 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2752
2753 __ orr(tmp, tmp, TypeEntries::type_unknown);
2754 __ str(tmp, mdo_addr);
2755 // FIXME: Write barrier needed here?
2756 }
2757 }
2758
2759 __ bind(next);
2760 }
2761 COMMENT("} emit_profile_type");
2762 }
2763
2764
2765 void LIR_Assembler::align_backward_branch_target() {
2766 }
2767
2768
2769 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2770 // tmp must be unused
2771 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2772
2773 if (left->is_single_cpu()) {
2774 assert(dest->is_single_cpu(), "expect single result reg");
2775 __ negw(dest->as_register(), left->as_register());
2776 } else if (left->is_double_cpu()) {
2777 assert(dest->is_double_cpu(), "expect double result reg");
2778 __ neg(dest->as_register_lo(), left->as_register_lo());
2779 } else if (left->is_single_fpu()) {
2780 assert(dest->is_single_fpu(), "expect single float result reg");
2781 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2782 } else {
2783 assert(left->is_double_fpu(), "expect double float operand reg");
2784 assert(dest->is_double_fpu(), "expect double float result reg");
2785 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2786 }
2787 }
2788
2789
2790 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2791 if (patch_code != lir_patch_none) {
2792 deoptimize_trap(info);
2793 return;
2794 }
2795
2796 __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
2797 }
2798
2799
2800 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2801 assert(!tmp->is_valid(), "don't need temporary");
2802
2803 CodeBlob *cb = CodeCache::find_blob(dest);
2804 if (cb) {
2805 __ far_call(RuntimeAddress(dest));
2806 } else {
2807 __ mov(rscratch1, RuntimeAddress(dest));
2808 __ blr(rscratch1);
2809 }
2810
2811 if (info != nullptr) {
2812 add_call_info_here(info);
2813 }
2814 __ post_call_nop();
2815 }
2816
2817 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2818 if (src->is_address()) {
2819 mem2reg(src, dest, type, lir_patch_none, info, /*wide*/false, /*is_volatile*/true);
2820 } else if (dest->is_address()) {
2821 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
2822 } else {
2823 ShouldNotReachHere();
2824 }
2825 }
2826
2827 #ifdef ASSERT
2828 // emit run-time assertion
2829 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2830 assert(op->code() == lir_assert, "must be");
2831
2832 if (op->in_opr1()->is_valid()) {
2833 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2834 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2835 } else {
2836 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2837 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2838 }
2839
2840 Label ok;
2841 if (op->condition() != lir_cond_always) {
2842 Assembler::Condition acond = Assembler::AL;
2843 switch (op->condition()) {
2844 case lir_cond_equal: acond = Assembler::EQ; break;
2845 case lir_cond_notEqual: acond = Assembler::NE; break;
2846 case lir_cond_less: acond = Assembler::LT; break;
2847 case lir_cond_lessEqual: acond = Assembler::LE; break;
2848 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2849 case lir_cond_greater: acond = Assembler::GT; break;
2850 case lir_cond_belowEqual: acond = Assembler::LS; break;
2851 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2852 default: ShouldNotReachHere();
2853 }
2854 __ br(acond, ok);
2855 }
2856 if (op->halt()) {
2857 const char* str = __ code_string(op->msg());
2858 __ stop(str);
2859 } else {
2860 breakpoint();
2861 }
2862 __ bind(ok);
2863 }
2864 #endif
2865
2866 #ifndef PRODUCT
2867 #define COMMENT(x) do { __ block_comment(x); } while (0)
2868 #else
2869 #define COMMENT(x)
2870 #endif
2871
2872 void LIR_Assembler::membar() {
2873 COMMENT("membar");
2874 __ membar(MacroAssembler::AnyAny);
2875 }
2876
2877 void LIR_Assembler::membar_acquire() {
2878 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2879 }
2880
2881 void LIR_Assembler::membar_release() {
2882 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2883 }
2884
2885 void LIR_Assembler::membar_loadload() {
2886 __ membar(Assembler::LoadLoad);
2887 }
2888
2889 void LIR_Assembler::membar_storestore() {
2890 __ membar(MacroAssembler::StoreStore);
2891 }
2892
2893 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2894
2895 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2896
2897 void LIR_Assembler::on_spin_wait() {
2898 __ spin_wait();
2899 }
2900
2901 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2902 __ mov(result_reg->as_register(), rthread);
2903 }
2904
2905
2906 void LIR_Assembler::peephole(LIR_List *lir) {
2907 #if 0
2908 if (tableswitch_count >= max_tableswitches)
2909 return;
2910
2911 /*
2912 This finite-state automaton recognizes sequences of compare-and-
2913 branch instructions. We will turn them into a tableswitch. You
2914 could argue that C1 really shouldn't be doing this sort of
2915 optimization, but without it the code is really horrible.
2916 */
2917
2918 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2919 int first_key, last_key = -2147483648;
2920 int next_key = 0;
2921 int start_insn = -1;
2922 int last_insn = -1;
2923 Register reg = noreg;
2924 LIR_Opr reg_opr;
2925 state = start_s;
2926
2927 LIR_OpList* inst = lir->instructions_list();
2928 for (int i = 0; i < inst->length(); i++) {
2929 LIR_Op* op = inst->at(i);
2930 switch (state) {
2931 case start_s:
2932 first_key = -1;
2933 start_insn = i;
2934 switch (op->code()) {
2935 case lir_cmp:
2936 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2937 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2938 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2939 && opr2->is_constant()
2940 && opr2->type() == T_INT) {
2941 reg_opr = opr1;
2942 reg = opr1->as_register();
2943 first_key = opr2->as_constant_ptr()->as_jint();
2944 next_key = first_key + 1;
2945 state = cmp_s;
2946 goto next_state;
2947 }
2948 break;
2949 }
2950 break;
2951 case cmp_s:
2952 switch (op->code()) {
2953 case lir_branch:
2954 if (op->as_OpBranch()->cond() == lir_cond_equal) {
2955 state = beq_s;
2956 last_insn = i;
2957 goto next_state;
2958 }
2959 }
2960 state = start_s;
2961 break;
2962 case beq_s:
2963 switch (op->code()) {
2964 case lir_cmp: {
2965 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2966 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2967 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2968 && opr1->as_register() == reg
2969 && opr2->is_constant()
2970 && opr2->type() == T_INT
2971 && opr2->as_constant_ptr()->as_jint() == next_key) {
2972 last_key = next_key;
2973 next_key++;
2974 state = cmp_s;
2975 goto next_state;
2976 }
2977 }
2978 }
2979 last_key = next_key;
2980 state = start_s;
2981 break;
2982 default:
2983 assert(false, "impossible state");
2984 }
2985 if (state == start_s) {
2986 if (first_key < last_key - 5L && reg != noreg) {
2987 {
2988 // printf("found run register %d starting at insn %d low value %d high value %d\n",
2989 // reg->encoding(),
2990 // start_insn, first_key, last_key);
2991 // for (int i = 0; i < inst->length(); i++) {
2992 // inst->at(i)->print();
2993 // tty->print("\n");
2994 // }
2995 // tty->print("\n");
2996 }
2997
2998 struct tableswitch *sw = &switches[tableswitch_count];
2999 sw->_insn_index = start_insn, sw->_first_key = first_key,
3000 sw->_last_key = last_key, sw->_reg = reg;
3001 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3002 {
3003 // Insert the new table of branches
3004 int offset = last_insn;
3005 for (int n = first_key; n < last_key; n++) {
3006 inst->insert_before
3007 (last_insn + 1,
3008 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3009 inst->at(offset)->as_OpBranch()->label()));
3010 offset -= 2, i++;
3011 }
3012 }
3013 // Delete all the old compare-and-branch instructions
3014 for (int n = first_key; n < last_key; n++) {
3015 inst->remove_at(start_insn);
3016 inst->remove_at(start_insn);
3017 }
3018 // Insert the tableswitch instruction
3019 inst->insert_before(start_insn,
3020 new LIR_Op2(lir_cmp, lir_cond_always,
3021 LIR_OprFact::intConst(tableswitch_count),
3022 reg_opr));
3023 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3024 tableswitch_count++;
3025 }
3026 reg = noreg;
3027 last_key = -2147483648;
3028 }
3029 next_state:
3030 ;
3031 }
3032 #endif
3033 }
3034
3035 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3036 Address addr = as_Address(src->as_address_ptr());
3037 BasicType type = src->type();
3038 bool is_oop = is_reference_type(type);
3039
3040 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3041 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3042
3043 switch(type) {
3044 case T_INT:
3045 xchg = &MacroAssembler::atomic_xchgalw;
3046 add = &MacroAssembler::atomic_addalw;
3047 break;
3048 case T_LONG:
3049 xchg = &MacroAssembler::atomic_xchgal;
3050 add = &MacroAssembler::atomic_addal;
3051 break;
3052 case T_OBJECT:
3053 case T_ARRAY:
3054 if (UseCompressedOops) {
3055 xchg = &MacroAssembler::atomic_xchgalw;
3056 add = &MacroAssembler::atomic_addalw;
3057 } else {
3058 xchg = &MacroAssembler::atomic_xchgal;
3059 add = &MacroAssembler::atomic_addal;
3060 }
3061 break;
3062 default:
3063 ShouldNotReachHere();
3064 xchg = &MacroAssembler::atomic_xchgal;
3065 add = &MacroAssembler::atomic_addal; // unreachable
3066 }
3067
3068 switch (code) {
3069 case lir_xadd:
3070 {
3071 RegisterOrConstant inc;
3072 Register tmp = as_reg(tmp_op);
3073 Register dst = as_reg(dest);
3074 if (data->is_constant()) {
3075 inc = RegisterOrConstant(as_long(data));
3076 assert_different_registers(dst, addr.base(), tmp,
3077 rscratch1, rscratch2);
3078 } else {
3079 inc = RegisterOrConstant(as_reg(data));
3080 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3081 rscratch1, rscratch2);
3082 }
3083 __ lea(tmp, addr);
3084 (_masm->*add)(dst, inc, tmp);
3085 break;
3086 }
3087 case lir_xchg:
3088 {
3089 Register tmp = tmp_op->as_register();
3090 Register obj = as_reg(data);
3091 Register dst = as_reg(dest);
3092 if (is_oop && UseCompressedOops) {
3093 __ encode_heap_oop(rscratch2, obj);
3094 obj = rscratch2;
3095 }
3096 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3097 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3098 __ lea(tmp, addr);
3099 (_masm->*xchg)(dst, obj, tmp);
3100 if (is_oop && UseCompressedOops) {
3101 __ decode_heap_oop(dst);
3102 }
3103 }
3104 break;
3105 default:
3106 ShouldNotReachHere();
3107 }
3108 }
3109
3110 #undef __