1 /*
2 * Copyright (c) 2000, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "code/aotCodeCache.hpp"
37 #include "code/compiledIC.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_aarch64.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "runtime/frame.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "utilities/powerOfTwo.hpp"
46 #include "vmreg_aarch64.inline.hpp"
47
48
49 #ifndef PRODUCT
50 #define COMMENT(x) do { __ block_comment(x); } while (0)
51 #else
52 #define COMMENT(x)
53 #endif
54
55 NEEDS_CLEANUP // remove this definitions ?
56 const Register SYNC_header = r0; // synchronization header
57 const Register SHIFT_count = r0; // where count for shift operations must be
58
59 #define __ _masm->
60
61
62 static void select_different_registers(Register preserve,
63 Register extra,
64 Register &tmp1,
65 Register &tmp2,
66 Register &tmp3) {
67 if (tmp1 == preserve) {
68 assert_different_registers(tmp1, tmp2, tmp3, extra);
69 tmp1 = extra;
70 } else if (tmp2 == preserve) {
71 assert_different_registers(tmp1, tmp2, tmp3, extra);
72 tmp2 = extra;
73 } else if (tmp3 == preserve) {
74 assert_different_registers(tmp1, tmp2, tmp3, extra);
75 tmp3 = extra;
76 }
77 assert_different_registers(preserve, tmp1, tmp2, tmp3);
78 }
79
80
81 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
82
83
84 LIR_Opr LIR_Assembler::receiverOpr() {
85 return FrameMap::receiver_opr;
86 }
87
88 LIR_Opr LIR_Assembler::osrBufferPointer() {
89 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
90 }
91
92 //--------------fpu register translations-----------------------
93
94
95 address LIR_Assembler::float_constant(float f) {
96 address const_addr = __ float_constant(f);
97 if (const_addr == nullptr) {
98 bailout("const section overflow");
99 return __ code()->consts()->start();
100 } else {
101 return const_addr;
102 }
103 }
104
105
106 address LIR_Assembler::double_constant(double d) {
107 address const_addr = __ double_constant(d);
108 if (const_addr == nullptr) {
109 bailout("const section overflow");
110 return __ code()->consts()->start();
111 } else {
112 return const_addr;
113 }
114 }
115
116 address LIR_Assembler::int_constant(jlong n) {
117 address const_addr = __ long_constant(n);
118 if (const_addr == nullptr) {
119 bailout("const section overflow");
120 return __ code()->consts()->start();
121 } else {
122 return const_addr;
123 }
124 }
125
126 void LIR_Assembler::breakpoint() { Unimplemented(); }
127
128 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
129
130 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
131
132 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
133 //-------------------------------------------
134
135 static Register as_reg(LIR_Opr op) {
136 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
137 }
138
139 static jlong as_long(LIR_Opr data) {
140 jlong result;
141 switch (data->type()) {
142 case T_INT:
143 result = (data->as_jint());
144 break;
145 case T_LONG:
146 result = (data->as_jlong());
147 break;
148 default:
149 ShouldNotReachHere();
150 result = 0; // unreachable
151 }
152 return result;
153 }
154
155 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
156 Register base = addr->base()->as_pointer_register();
157 LIR_Opr opr = addr->index();
158 if (opr->is_cpu_register()) {
159 Register index;
160 if (opr->is_single_cpu())
161 index = opr->as_register();
162 else
163 index = opr->as_register_lo();
164 assert(addr->disp() == 0, "must be");
165 switch(opr->type()) {
166 case T_INT:
167 return Address(base, index, Address::sxtw(addr->scale()));
168 case T_LONG:
169 return Address(base, index, Address::lsl(addr->scale()));
170 default:
171 ShouldNotReachHere();
172 }
173 } else {
174 assert(addr->scale() == 0,
175 "expected for immediate operand, was: %d", addr->scale());
176 ptrdiff_t offset = ptrdiff_t(addr->disp());
177 // NOTE: Does not handle any 16 byte vector access.
178 const uint type_size = type2aelembytes(addr->type(), true);
179 return __ legitimize_address(Address(base, offset), type_size, tmp);
180 }
181 return Address();
182 }
183
184 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
185 ShouldNotReachHere();
186 return Address();
187 }
188
189 Address LIR_Assembler::as_Address(LIR_Address* addr) {
190 return as_Address(addr, rscratch1);
191 }
192
193 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
194 return as_Address(addr, rscratch1); // Ouch
195 // FIXME: This needs to be much more clever. See x86.
196 }
197
198 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
199 // not encodable as a base + (immediate) offset, generate an explicit address
200 // calculation to hold the address in a temporary register.
201 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
202 precond(size == 4 || size == 8);
203 Address addr = frame_map()->address_for_slot(index, adjust);
204 precond(addr.getMode() == Address::base_plus_offset);
205 precond(addr.base() == sp);
206 precond(addr.offset() > 0);
207 uint mask = size - 1;
208 assert((addr.offset() & mask) == 0, "scaled offsets only");
209 return __ legitimize_address(addr, size, tmp);
210 }
211
212 void LIR_Assembler::osr_entry() {
213 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
214 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
215 ValueStack* entry_state = osr_entry->state();
216 int number_of_locks = entry_state->locks_size();
217
218 // we jump here if osr happens with the interpreter
219 // state set up to continue at the beginning of the
220 // loop that triggered osr - in particular, we have
221 // the following registers setup:
222 //
223 // r2: osr buffer
224 //
225
226 // build frame
227 ciMethod* m = compilation()->method();
228 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
229
230 // OSR buffer is
231 //
232 // locals[nlocals-1..0]
233 // monitors[0..number_of_locks]
234 //
235 // locals is a direct copy of the interpreter frame so in the osr buffer
236 // so first slot in the local array is the last local from the interpreter
237 // and last slot is local[0] (receiver) from the interpreter
238 //
239 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
240 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
241 // in the interpreter frame (the method lock if a sync method)
242
243 // Initialize monitors in the compiled activation.
244 // r2: pointer to osr buffer
245 //
246 // All other registers are dead at this point and the locals will be
247 // copied into place by code emitted in the IR.
248
249 Register OSR_buf = osrBufferPointer()->as_pointer_register();
250 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
251 int monitor_offset = BytesPerWord * method()->max_locals() +
252 (2 * BytesPerWord) * (number_of_locks - 1);
253 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
254 // the OSR buffer using 2 word entries: first the lock and then
255 // the oop.
256 for (int i = 0; i < number_of_locks; i++) {
257 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
258 #ifdef ASSERT
259 // verify the interpreter's monitor has a non-null object
260 {
261 Label L;
262 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
263 __ cbnz(rscratch1, L);
264 __ stop("locked object is null");
265 __ bind(L);
266 }
267 #endif
268 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
269 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
270 __ str(r19, frame_map()->address_for_monitor_lock(i));
271 __ str(r20, frame_map()->address_for_monitor_object(i));
272 }
273 }
274 }
275
276
277 // inline cache check; done before the frame is built.
278 int LIR_Assembler::check_icache() {
279 return __ ic_check(CodeEntryAlignment);
280 }
281
282 void LIR_Assembler::clinit_barrier(ciMethod* method) {
283 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
284 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
285
286 Label L_skip_barrier;
287
288 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
289 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
290 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
291 __ bind(L_skip_barrier);
292 }
293
294 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
295 if (o == nullptr) {
296 __ mov(reg, zr);
297 } else {
298 __ movoop(reg, o);
299 }
300 }
301
302 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
303 address target = nullptr;
304 relocInfo::relocType reloc_type = relocInfo::none;
305
306 switch (patching_id(info)) {
307 case PatchingStub::access_field_id:
308 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
309 reloc_type = relocInfo::section_word_type;
310 break;
311 case PatchingStub::load_klass_id:
312 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
313 reloc_type = relocInfo::metadata_type;
314 break;
315 case PatchingStub::load_mirror_id:
316 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
317 reloc_type = relocInfo::oop_type;
318 break;
319 case PatchingStub::load_appendix_id:
320 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
321 reloc_type = relocInfo::oop_type;
322 break;
323 default: ShouldNotReachHere();
324 }
325
326 __ far_call(RuntimeAddress(target));
327 add_call_info_here(info);
328 }
329
330 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
331 deoptimize_trap(info);
332 }
333
334
335 // This specifies the rsp decrement needed to build the frame
336 int LIR_Assembler::initial_frame_size_in_bytes() const {
337 // if rounding, must let FrameMap know!
338
339 return in_bytes(frame_map()->framesize_in_bytes());
340 }
341
342
343 int LIR_Assembler::emit_exception_handler() {
344 // generate code for exception handler
345 address handler_base = __ start_a_stub(exception_handler_size());
346 if (handler_base == nullptr) {
347 // not enough space left for the handler
348 bailout("exception handler overflow");
349 return -1;
350 }
351
352 int offset = code_offset();
353
354 // the exception oop and pc are in r0, and r3
355 // no other registers need to be preserved, so invalidate them
356 __ invalidate_registers(false, true, true, false, true, true);
357
358 // check that there is really an exception
359 __ verify_not_null_oop(r0);
360
361 // search an exception handler (r0: exception oop, r3: throwing pc)
362 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
363 __ should_not_reach_here();
364 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
365 __ end_a_stub();
366
367 return offset;
368 }
369
370
371 // Emit the code to remove the frame from the stack in the exception
372 // unwind path.
373 int LIR_Assembler::emit_unwind_handler() {
374 #ifndef PRODUCT
375 if (CommentedAssembly) {
376 _masm->block_comment("Unwind handler");
377 }
378 #endif
379
380 int offset = code_offset();
381
382 // Fetch the exception from TLS and clear out exception related thread state
383 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
384 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
385 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
386
387 __ bind(_unwind_handler_entry);
388 __ verify_not_null_oop(r0);
389 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
390 __ mov(r19, r0); // Preserve the exception
391 }
392
393 // Perform needed unlocking
394 MonitorExitStub* stub = nullptr;
395 if (method()->is_synchronized()) {
396 monitor_address(0, FrameMap::r0_opr);
397 stub = new MonitorExitStub(FrameMap::r0_opr, 0);
398 __ unlock_object(r5, r4, r0, r6, *stub->entry());
399 __ bind(*stub->continuation());
400 }
401
402 if (compilation()->env()->dtrace_method_probes()) {
403 __ mov(c_rarg0, rthread);
404 __ mov_metadata(c_rarg1, method()->constant_encoding());
405 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
406 }
407
408 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
409 __ mov(r0, r19); // Restore the exception
410 }
411
412 // remove the activation and dispatch to the unwind handler
413 __ block_comment("remove_frame and dispatch to the unwind handler");
414 __ remove_frame(initial_frame_size_in_bytes());
415 __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
416
417 // Emit the slow path assembly
418 if (stub != nullptr) {
419 stub->emit_code(this);
420 }
421
422 return offset;
423 }
424
425
426 int LIR_Assembler::emit_deopt_handler() {
427 // generate code for exception handler
428 address handler_base = __ start_a_stub(deopt_handler_size());
429 if (handler_base == nullptr) {
430 // not enough space left for the handler
431 bailout("deopt handler overflow");
432 return -1;
433 }
434
435 int offset = code_offset();
436
437 Label start;
438 __ bind(start);
439
440 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
441
442 int entry_offset = __ offset();
443 __ b(start);
444
445 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
446 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
447 "out of bounds read in post-call NOP check");
448 __ end_a_stub();
449
450 return entry_offset;
451 }
452
453 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
454 _masm->code_section()->relocate(adr, relocInfo::poll_type);
455 int pc_offset = code_offset();
456 flush_debug_info(pc_offset);
457 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
458 if (info->exception_handlers() != nullptr) {
459 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
460 }
461 }
462
463 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
464 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
465
466 // Pop the stack before the safepoint code
467 __ remove_frame(initial_frame_size_in_bytes());
468
469 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
470 __ reserved_stack_check();
471 }
472
473 code_stub->set_safepoint_offset(__ offset());
474 __ relocate(relocInfo::poll_return_type);
475 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
476 __ ret(lr);
477 }
478
479 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
480 guarantee(info != nullptr, "Shouldn't be null");
481 __ get_polling_page(rscratch1, relocInfo::poll_type);
482 add_debug_info_for_branch(info); // This isn't just debug info:
483 // it's the oop map
484 __ read_polling_page(rscratch1, relocInfo::poll_type);
485 return __ offset();
486 }
487
488
489 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
490 if (from_reg == r31_sp)
491 from_reg = sp;
492 if (to_reg == r31_sp)
493 to_reg = sp;
494 __ mov(to_reg, from_reg);
495 }
496
497 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
498
499
500 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
501 assert(src->is_constant(), "should not call otherwise");
502 assert(dest->is_register(), "should not call otherwise");
503 LIR_Const* c = src->as_constant_ptr();
504
505 switch (c->type()) {
506 case T_INT: {
507 assert(patch_code == lir_patch_none, "no patching handled here");
508 __ movw(dest->as_register(), c->as_jint());
509 break;
510 }
511
512 case T_ADDRESS: {
513 assert(patch_code == lir_patch_none, "no patching handled here");
514 __ mov(dest->as_register(), c->as_jint());
515 break;
516 }
517
518 case T_LONG: {
519 assert(patch_code == lir_patch_none, "no patching handled here");
520 #if INCLUDE_CDS
521 if (AOTCodeCache::is_on_for_dump()) {
522 address b = c->as_pointer();
523 if (AOTRuntimeConstants::contains(b)) {
524 __ load_aotrc_address(dest->as_register_lo(), b);
525 break;
526 }
527 }
528 #endif
529 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
530 break;
531 }
532
533 case T_OBJECT: {
534 if (patch_code == lir_patch_none) {
535 jobject2reg(c->as_jobject(), dest->as_register());
536 } else {
537 jobject2reg_with_patching(dest->as_register(), info);
538 }
539 break;
540 }
541
542 case T_METADATA: {
543 if (patch_code != lir_patch_none) {
544 klass2reg_with_patching(dest->as_register(), info);
545 } else {
546 __ mov_metadata(dest->as_register(), c->as_metadata());
547 }
548 break;
549 }
550
551 case T_FLOAT: {
552 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
553 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
554 } else {
555 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
556 __ ldrs(dest->as_float_reg(), Address(rscratch1));
557 }
558 break;
559 }
560
561 case T_DOUBLE: {
562 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
563 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
564 } else {
565 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
566 __ ldrd(dest->as_double_reg(), Address(rscratch1));
567 }
568 break;
569 }
570
571 default:
572 ShouldNotReachHere();
573 }
574 }
575
576 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
577 LIR_Const* c = src->as_constant_ptr();
578 switch (c->type()) {
579 case T_OBJECT:
580 {
581 if (! c->as_jobject())
582 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
583 else {
584 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
585 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
586 }
587 }
588 break;
589 case T_ADDRESS:
590 {
591 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
592 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
593 }
594 case T_INT:
595 case T_FLOAT:
596 {
597 Register reg = zr;
598 if (c->as_jint_bits() == 0)
599 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
600 else {
601 __ movw(rscratch1, c->as_jint_bits());
602 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
603 }
604 }
605 break;
606 case T_LONG:
607 case T_DOUBLE:
608 {
609 Register reg = zr;
610 if (c->as_jlong_bits() == 0)
611 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
612 lo_word_offset_in_bytes));
613 else {
614 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
615 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
616 lo_word_offset_in_bytes));
617 }
618 }
619 break;
620 default:
621 ShouldNotReachHere();
622 }
623 }
624
625 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
626 assert(src->is_constant(), "should not call otherwise");
627 LIR_Const* c = src->as_constant_ptr();
628 LIR_Address* to_addr = dest->as_address_ptr();
629
630 void (Assembler::* insn)(Register Rt, const Address &adr);
631
632 switch (type) {
633 case T_ADDRESS:
634 assert(c->as_jint() == 0, "should be");
635 insn = &Assembler::str;
636 break;
637 case T_LONG:
638 assert(c->as_jlong() == 0, "should be");
639 insn = &Assembler::str;
640 break;
641 case T_INT:
642 assert(c->as_jint() == 0, "should be");
643 insn = &Assembler::strw;
644 break;
645 case T_OBJECT:
646 case T_ARRAY:
647 assert(c->as_jobject() == nullptr, "should be");
648 if (UseCompressedOops && !wide) {
649 insn = &Assembler::strw;
650 } else {
651 insn = &Assembler::str;
652 }
653 break;
654 case T_CHAR:
655 case T_SHORT:
656 assert(c->as_jint() == 0, "should be");
657 insn = &Assembler::strh;
658 break;
659 case T_BOOLEAN:
660 case T_BYTE:
661 assert(c->as_jint() == 0, "should be");
662 insn = &Assembler::strb;
663 break;
664 default:
665 ShouldNotReachHere();
666 insn = &Assembler::str; // unreachable
667 }
668
669 if (info) add_debug_info_for_null_check_here(info);
670 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
671 }
672
673 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
674 assert(src->is_register(), "should not call otherwise");
675 assert(dest->is_register(), "should not call otherwise");
676
677 // move between cpu-registers
678 if (dest->is_single_cpu()) {
679 if (src->type() == T_LONG) {
680 // Can do LONG -> OBJECT
681 move_regs(src->as_register_lo(), dest->as_register());
682 return;
683 }
684 assert(src->is_single_cpu(), "must match");
685 if (src->type() == T_OBJECT) {
686 __ verify_oop(src->as_register());
687 }
688 move_regs(src->as_register(), dest->as_register());
689
690 } else if (dest->is_double_cpu()) {
691 if (is_reference_type(src->type())) {
692 // Surprising to me but we can see move of a long to t_object
693 __ verify_oop(src->as_register());
694 move_regs(src->as_register(), dest->as_register_lo());
695 return;
696 }
697 assert(src->is_double_cpu(), "must match");
698 Register f_lo = src->as_register_lo();
699 Register f_hi = src->as_register_hi();
700 Register t_lo = dest->as_register_lo();
701 Register t_hi = dest->as_register_hi();
702 assert(f_hi == f_lo, "must be same");
703 assert(t_hi == t_lo, "must be same");
704 move_regs(f_lo, t_lo);
705
706 } else if (dest->is_single_fpu()) {
707 __ fmovs(dest->as_float_reg(), src->as_float_reg());
708
709 } else if (dest->is_double_fpu()) {
710 __ fmovd(dest->as_double_reg(), src->as_double_reg());
711
712 } else {
713 ShouldNotReachHere();
714 }
715 }
716
717 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
718 precond(src->is_register() && dest->is_stack());
719
720 uint const c_sz32 = sizeof(uint32_t);
721 uint const c_sz64 = sizeof(uint64_t);
722
723 if (src->is_single_cpu()) {
724 int index = dest->single_stack_ix();
725 if (is_reference_type(type)) {
726 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
727 __ verify_oop(src->as_register());
728 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
729 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
730 } else {
731 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
732 }
733
734 } else if (src->is_double_cpu()) {
735 int index = dest->double_stack_ix();
736 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
737 __ str(src->as_register_lo(), dest_addr_LO);
738
739 } else if (src->is_single_fpu()) {
740 int index = dest->single_stack_ix();
741 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
742
743 } else if (src->is_double_fpu()) {
744 int index = dest->double_stack_ix();
745 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
746
747 } else {
748 ShouldNotReachHere();
749 }
750 }
751
752
753 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
754 LIR_Address* to_addr = dest->as_address_ptr();
755 PatchingStub* patch = nullptr;
756 Register compressed_src = rscratch1;
757
758 if (patch_code != lir_patch_none) {
759 deoptimize_trap(info);
760 return;
761 }
762
763 if (is_reference_type(type)) {
764 __ verify_oop(src->as_register());
765
766 if (UseCompressedOops && !wide) {
767 __ encode_heap_oop(compressed_src, src->as_register());
768 } else {
769 compressed_src = src->as_register();
770 }
771 }
772
773 int null_check_here = code_offset();
774 switch (type) {
775 case T_FLOAT: {
776 __ strs(src->as_float_reg(), as_Address(to_addr));
777 break;
778 }
779
780 case T_DOUBLE: {
781 __ strd(src->as_double_reg(), as_Address(to_addr));
782 break;
783 }
784
785 case T_ARRAY: // fall through
786 case T_OBJECT: // fall through
787 if (UseCompressedOops && !wide) {
788 __ strw(compressed_src, as_Address(to_addr, rscratch2));
789 } else {
790 __ str(compressed_src, as_Address(to_addr));
791 }
792 break;
793 case T_METADATA:
794 // We get here to store a method pointer to the stack to pass to
795 // a dtrace runtime call. This can't work on 64 bit with
796 // compressed klass ptrs: T_METADATA can be a compressed klass
797 // ptr or a 64 bit method pointer.
798 ShouldNotReachHere();
799 __ str(src->as_register(), as_Address(to_addr));
800 break;
801 case T_ADDRESS:
802 __ str(src->as_register(), as_Address(to_addr));
803 break;
804 case T_INT:
805 __ strw(src->as_register(), as_Address(to_addr));
806 break;
807
808 case T_LONG: {
809 __ str(src->as_register_lo(), as_Address_lo(to_addr));
810 break;
811 }
812
813 case T_BYTE: // fall through
814 case T_BOOLEAN: {
815 __ strb(src->as_register(), as_Address(to_addr));
816 break;
817 }
818
819 case T_CHAR: // fall through
820 case T_SHORT:
821 __ strh(src->as_register(), as_Address(to_addr));
822 break;
823
824 default:
825 ShouldNotReachHere();
826 }
827 if (info != nullptr) {
828 add_debug_info_for_null_check(null_check_here, info);
829 }
830 }
831
832
833 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
834 precond(src->is_stack() && dest->is_register());
835
836 uint const c_sz32 = sizeof(uint32_t);
837 uint const c_sz64 = sizeof(uint64_t);
838
839 if (dest->is_single_cpu()) {
840 int index = src->single_stack_ix();
841 if (is_reference_type(type)) {
842 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
843 __ verify_oop(dest->as_register());
844 } else if (type == T_METADATA || type == T_ADDRESS) {
845 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
846 } else {
847 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
848 }
849
850 } else if (dest->is_double_cpu()) {
851 int index = src->double_stack_ix();
852 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
853 __ ldr(dest->as_register_lo(), src_addr_LO);
854
855 } else if (dest->is_single_fpu()) {
856 int index = src->single_stack_ix();
857 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
858
859 } else if (dest->is_double_fpu()) {
860 int index = src->double_stack_ix();
861 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
862
863 } else {
864 ShouldNotReachHere();
865 }
866 }
867
868
869 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
870 address target = nullptr;
871 relocInfo::relocType reloc_type = relocInfo::none;
872
873 switch (patching_id(info)) {
874 case PatchingStub::access_field_id:
875 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
876 reloc_type = relocInfo::section_word_type;
877 break;
878 case PatchingStub::load_klass_id:
879 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
880 reloc_type = relocInfo::metadata_type;
881 break;
882 case PatchingStub::load_mirror_id:
883 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
884 reloc_type = relocInfo::oop_type;
885 break;
886 case PatchingStub::load_appendix_id:
887 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
888 reloc_type = relocInfo::oop_type;
889 break;
890 default: ShouldNotReachHere();
891 }
892
893 __ far_call(RuntimeAddress(target));
894 add_call_info_here(info);
895 }
896
897 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
898
899 LIR_Opr temp;
900 if (type == T_LONG || type == T_DOUBLE)
901 temp = FrameMap::rscratch1_long_opr;
902 else
903 temp = FrameMap::rscratch1_opr;
904
905 stack2reg(src, temp, src->type());
906 reg2stack(temp, dest, dest->type());
907 }
908
909
910 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
911 LIR_Address* addr = src->as_address_ptr();
912 LIR_Address* from_addr = src->as_address_ptr();
913
914 if (addr->base()->type() == T_OBJECT) {
915 __ verify_oop(addr->base()->as_pointer_register());
916 }
917
918 if (patch_code != lir_patch_none) {
919 deoptimize_trap(info);
920 return;
921 }
922
923 if (info != nullptr) {
924 add_debug_info_for_null_check_here(info);
925 }
926 int null_check_here = code_offset();
927 switch (type) {
928 case T_FLOAT: {
929 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
930 break;
931 }
932
933 case T_DOUBLE: {
934 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
935 break;
936 }
937
938 case T_ARRAY: // fall through
939 case T_OBJECT: // fall through
940 if (UseCompressedOops && !wide) {
941 __ ldrw(dest->as_register(), as_Address(from_addr));
942 } else {
943 __ ldr(dest->as_register(), as_Address(from_addr));
944 }
945 break;
946 case T_METADATA:
947 // We get here to store a method pointer to the stack to pass to
948 // a dtrace runtime call. This can't work on 64 bit with
949 // compressed klass ptrs: T_METADATA can be a compressed klass
950 // ptr or a 64 bit method pointer.
951 ShouldNotReachHere();
952 __ ldr(dest->as_register(), as_Address(from_addr));
953 break;
954 case T_ADDRESS:
955 __ ldr(dest->as_register(), as_Address(from_addr));
956 break;
957 case T_INT:
958 __ ldrw(dest->as_register(), as_Address(from_addr));
959 break;
960
961 case T_LONG: {
962 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
963 break;
964 }
965
966 case T_BYTE:
967 __ ldrsb(dest->as_register(), as_Address(from_addr));
968 break;
969 case T_BOOLEAN: {
970 __ ldrb(dest->as_register(), as_Address(from_addr));
971 break;
972 }
973
974 case T_CHAR:
975 __ ldrh(dest->as_register(), as_Address(from_addr));
976 break;
977 case T_SHORT:
978 __ ldrsh(dest->as_register(), as_Address(from_addr));
979 break;
980
981 default:
982 ShouldNotReachHere();
983 }
984
985 if (is_reference_type(type)) {
986 if (UseCompressedOops && !wide) {
987 __ decode_heap_oop(dest->as_register());
988 }
989
990 __ verify_oop(dest->as_register());
991 }
992 }
993
994
995 int LIR_Assembler::array_element_size(BasicType type) const {
996 int elem_size = type2aelembytes(type);
997 return exact_log2(elem_size);
998 }
999
1000
1001 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1002 switch (op->code()) {
1003 case lir_idiv:
1004 case lir_irem:
1005 arithmetic_idiv(op->code(),
1006 op->in_opr1(),
1007 op->in_opr2(),
1008 op->in_opr3(),
1009 op->result_opr(),
1010 op->info());
1011 break;
1012 case lir_fmad:
1013 __ fmaddd(op->result_opr()->as_double_reg(),
1014 op->in_opr1()->as_double_reg(),
1015 op->in_opr2()->as_double_reg(),
1016 op->in_opr3()->as_double_reg());
1017 break;
1018 case lir_fmaf:
1019 __ fmadds(op->result_opr()->as_float_reg(),
1020 op->in_opr1()->as_float_reg(),
1021 op->in_opr2()->as_float_reg(),
1022 op->in_opr3()->as_float_reg());
1023 break;
1024 default: ShouldNotReachHere(); break;
1025 }
1026 }
1027
1028 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1029 #ifdef ASSERT
1030 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1031 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1032 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1033 #endif
1034
1035 if (op->cond() == lir_cond_always) {
1036 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1037 __ b(*(op->label()));
1038 } else {
1039 Assembler::Condition acond;
1040 if (op->code() == lir_cond_float_branch) {
1041 bool is_unordered = (op->ublock() == op->block());
1042 // Assembler::EQ does not permit unordered branches, so we add
1043 // another branch here. Likewise, Assembler::NE does not permit
1044 // ordered branches.
1045 if ((is_unordered && op->cond() == lir_cond_equal)
1046 || (!is_unordered && op->cond() == lir_cond_notEqual))
1047 __ br(Assembler::VS, *(op->ublock()->label()));
1048 switch(op->cond()) {
1049 case lir_cond_equal: acond = Assembler::EQ; break;
1050 case lir_cond_notEqual: acond = Assembler::NE; break;
1051 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1052 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1053 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1054 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1055 default: ShouldNotReachHere();
1056 acond = Assembler::EQ; // unreachable
1057 }
1058 } else {
1059 switch (op->cond()) {
1060 case lir_cond_equal: acond = Assembler::EQ; break;
1061 case lir_cond_notEqual: acond = Assembler::NE; break;
1062 case lir_cond_less: acond = Assembler::LT; break;
1063 case lir_cond_lessEqual: acond = Assembler::LE; break;
1064 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1065 case lir_cond_greater: acond = Assembler::GT; break;
1066 case lir_cond_belowEqual: acond = Assembler::LS; break;
1067 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1068 default: ShouldNotReachHere();
1069 acond = Assembler::EQ; // unreachable
1070 }
1071 }
1072 __ br(acond,*(op->label()));
1073 }
1074 }
1075
1076
1077
1078 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1079 LIR_Opr src = op->in_opr();
1080 LIR_Opr dest = op->result_opr();
1081
1082 switch (op->bytecode()) {
1083 case Bytecodes::_i2f:
1084 {
1085 __ scvtfws(dest->as_float_reg(), src->as_register());
1086 break;
1087 }
1088 case Bytecodes::_i2d:
1089 {
1090 __ scvtfwd(dest->as_double_reg(), src->as_register());
1091 break;
1092 }
1093 case Bytecodes::_l2d:
1094 {
1095 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1096 break;
1097 }
1098 case Bytecodes::_l2f:
1099 {
1100 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1101 break;
1102 }
1103 case Bytecodes::_f2d:
1104 {
1105 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1106 break;
1107 }
1108 case Bytecodes::_d2f:
1109 {
1110 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1111 break;
1112 }
1113 case Bytecodes::_i2c:
1114 {
1115 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1116 break;
1117 }
1118 case Bytecodes::_i2l:
1119 {
1120 __ sxtw(dest->as_register_lo(), src->as_register());
1121 break;
1122 }
1123 case Bytecodes::_i2s:
1124 {
1125 __ sxth(dest->as_register(), src->as_register());
1126 break;
1127 }
1128 case Bytecodes::_i2b:
1129 {
1130 __ sxtb(dest->as_register(), src->as_register());
1131 break;
1132 }
1133 case Bytecodes::_l2i:
1134 {
1135 _masm->block_comment("FIXME: This could be a no-op");
1136 __ uxtw(dest->as_register(), src->as_register_lo());
1137 break;
1138 }
1139 case Bytecodes::_d2l:
1140 {
1141 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1142 break;
1143 }
1144 case Bytecodes::_f2i:
1145 {
1146 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1147 break;
1148 }
1149 case Bytecodes::_f2l:
1150 {
1151 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1152 break;
1153 }
1154 case Bytecodes::_d2i:
1155 {
1156 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1157 break;
1158 }
1159 default: ShouldNotReachHere();
1160 }
1161 }
1162
1163 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1164 if (op->init_check()) {
1165 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1166 __ ldarb(rscratch1, rscratch1);
1167 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1168 add_debug_info_for_null_check_here(op->stub()->info());
1169 __ br(Assembler::NE, *op->stub()->entry());
1170 }
1171 __ allocate_object(op->obj()->as_register(),
1172 op->tmp1()->as_register(),
1173 op->tmp2()->as_register(),
1174 op->header_size(),
1175 op->object_size(),
1176 op->klass()->as_register(),
1177 *op->stub()->entry());
1178 __ bind(*op->stub()->continuation());
1179 }
1180
1181 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1182 Register len = op->len()->as_register();
1183 __ uxtw(len, len);
1184
1185 if (UseSlowPath ||
1186 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1187 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1188 __ b(*op->stub()->entry());
1189 } else {
1190 Register tmp1 = op->tmp1()->as_register();
1191 Register tmp2 = op->tmp2()->as_register();
1192 Register tmp3 = op->tmp3()->as_register();
1193 if (len == tmp1) {
1194 tmp1 = tmp3;
1195 } else if (len == tmp2) {
1196 tmp2 = tmp3;
1197 } else if (len == tmp3) {
1198 // everything is ok
1199 } else {
1200 __ mov(tmp3, len);
1201 }
1202 __ allocate_array(op->obj()->as_register(),
1203 len,
1204 tmp1,
1205 tmp2,
1206 arrayOopDesc::base_offset_in_bytes(op->type()),
1207 array_element_size(op->type()),
1208 op->klass()->as_register(),
1209 *op->stub()->entry(),
1210 op->zero_array());
1211 }
1212 __ bind(*op->stub()->continuation());
1213 }
1214
1215 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md,
1216 ciProfileData *data, Register recv) {
1217
1218 int mdp_offset = md->byte_offset_of_slot(data, in_ByteSize(0));
1219 __ profile_receiver_type(recv, mdo, mdp_offset);
1220 }
1221
1222 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1223 // we always need a stub for the failure case.
1224 CodeStub* stub = op->stub();
1225 Register obj = op->object()->as_register();
1226 Register k_RInfo = op->tmp1()->as_register();
1227 Register klass_RInfo = op->tmp2()->as_register();
1228 Register dst = op->result_opr()->as_register();
1229 ciKlass* k = op->klass();
1230 Register Rtmp1 = noreg;
1231
1232 // check if it needs to be profiled
1233 ciMethodData* md;
1234 ciProfileData* data;
1235
1236 const bool should_profile = op->should_profile();
1237
1238 if (should_profile) {
1239 ciMethod* method = op->profiled_method();
1240 assert(method != nullptr, "Should have method");
1241 int bci = op->profiled_bci();
1242 md = method->method_data_or_null();
1243 assert(md != nullptr, "Sanity");
1244 data = md->bci_to_data(bci);
1245 assert(data != nullptr, "need data for type check");
1246 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1247 }
1248 Label* success_target = success;
1249 Label* failure_target = failure;
1250
1251 if (obj == k_RInfo) {
1252 k_RInfo = dst;
1253 } else if (obj == klass_RInfo) {
1254 klass_RInfo = dst;
1255 }
1256
1257 Rtmp1 = op->tmp3()->as_register();
1258 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1259
1260 assert_different_registers(obj, k_RInfo, klass_RInfo);
1261
1262 if (should_profile) {
1263 Register mdo = klass_RInfo;
1264 __ mov_metadata(mdo, md->constant_encoding());
1265 Label not_null;
1266 __ cbnz(obj, not_null);
1267 // Object is null; update MDO and exit
1268 Address data_addr
1269 = __ form_address(rscratch2, mdo,
1270 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1271 0);
1272 __ ldrb(rscratch1, data_addr);
1273 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1274 __ strb(rscratch1, data_addr);
1275 __ b(*obj_is_null);
1276 __ bind(not_null);
1277
1278 Register recv = k_RInfo;
1279 __ load_klass(recv, obj);
1280 type_profile_helper(mdo, md, data, recv);
1281 } else {
1282 __ cbz(obj, *obj_is_null);
1283 }
1284
1285 if (!k->is_loaded()) {
1286 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1287 } else {
1288 __ mov_metadata(k_RInfo, k->constant_encoding());
1289 }
1290 __ verify_oop(obj);
1291
1292 if (op->fast_check()) {
1293 // get object class
1294 // not a safepoint as obj null check happens earlier
1295 __ load_klass(rscratch1, obj);
1296 __ cmp( rscratch1, k_RInfo);
1297
1298 __ br(Assembler::NE, *failure_target);
1299 // successful cast, fall through to profile or jump
1300 } else {
1301 // get object class
1302 // not a safepoint as obj null check happens earlier
1303 __ load_klass(klass_RInfo, obj);
1304 if (k->is_loaded()) {
1305 // See if we get an immediate positive hit
1306 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1307 __ cmp(k_RInfo, rscratch1);
1308 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1309 __ br(Assembler::NE, *failure_target);
1310 // successful cast, fall through to profile or jump
1311 } else {
1312 // See if we get an immediate positive hit
1313 __ br(Assembler::EQ, *success_target);
1314 // check for self
1315 __ cmp(klass_RInfo, k_RInfo);
1316 __ br(Assembler::EQ, *success_target);
1317
1318 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1319 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1320 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1321 // result is a boolean
1322 __ cbzw(klass_RInfo, *failure_target);
1323 // successful cast, fall through to profile or jump
1324 }
1325 } else {
1326 // perform the fast part of the checking logic
1327 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1328 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1329 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1330 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1331 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1332 // result is a boolean
1333 __ cbz(k_RInfo, *failure_target);
1334 // successful cast, fall through to profile or jump
1335 }
1336 }
1337 __ b(*success);
1338 }
1339
1340
1341 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1342 const bool should_profile = op->should_profile();
1343
1344 LIR_Code code = op->code();
1345 if (code == lir_store_check) {
1346 Register value = op->object()->as_register();
1347 Register array = op->array()->as_register();
1348 Register k_RInfo = op->tmp1()->as_register();
1349 Register klass_RInfo = op->tmp2()->as_register();
1350 Register Rtmp1 = op->tmp3()->as_register();
1351
1352 CodeStub* stub = op->stub();
1353
1354 // check if it needs to be profiled
1355 ciMethodData* md;
1356 ciProfileData* data;
1357
1358 if (should_profile) {
1359 ciMethod* method = op->profiled_method();
1360 assert(method != nullptr, "Should have method");
1361 int bci = op->profiled_bci();
1362 md = method->method_data_or_null();
1363 assert(md != nullptr, "Sanity");
1364 data = md->bci_to_data(bci);
1365 assert(data != nullptr, "need data for type check");
1366 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1367 }
1368 Label done;
1369 Label* success_target = &done;
1370 Label* failure_target = stub->entry();
1371
1372 if (should_profile) {
1373 Label not_null;
1374 Register mdo = klass_RInfo;
1375 __ mov_metadata(mdo, md->constant_encoding());
1376 __ cbnz(value, not_null);
1377 // Object is null; update MDO and exit
1378 Address data_addr
1379 = __ form_address(rscratch2, mdo,
1380 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1381 __ ldrb(rscratch1, data_addr);
1382 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1383 __ strb(rscratch1, data_addr);
1384 __ b(done);
1385 __ bind(not_null);
1386
1387 Register recv = k_RInfo;
1388 __ load_klass(recv, value);
1389 type_profile_helper(mdo, md, data, recv);
1390 } else {
1391 __ cbz(value, done);
1392 }
1393
1394 add_debug_info_for_null_check_here(op->info_for_exception());
1395 __ load_klass(k_RInfo, array);
1396 __ load_klass(klass_RInfo, value);
1397
1398 // get instance klass (it's already uncompressed)
1399 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1400 // perform the fast part of the checking logic
1401 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1402 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1403 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1404 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1405 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1406 // result is a boolean
1407 __ cbzw(k_RInfo, *failure_target);
1408 // fall through to the success case
1409
1410 __ bind(done);
1411 } else if (code == lir_checkcast) {
1412 Register obj = op->object()->as_register();
1413 Register dst = op->result_opr()->as_register();
1414 Label success;
1415 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1416 __ bind(success);
1417 if (dst != obj) {
1418 __ mov(dst, obj);
1419 }
1420 } else if (code == lir_instanceof) {
1421 Register obj = op->object()->as_register();
1422 Register dst = op->result_opr()->as_register();
1423 Label success, failure, done;
1424 emit_typecheck_helper(op, &success, &failure, &failure);
1425 __ bind(failure);
1426 __ mov(dst, zr);
1427 __ b(done);
1428 __ bind(success);
1429 __ mov(dst, 1);
1430 __ bind(done);
1431 } else {
1432 ShouldNotReachHere();
1433 }
1434 }
1435
1436 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1437 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1438 __ cset(rscratch1, Assembler::NE);
1439 __ membar(__ AnyAny);
1440 }
1441
1442 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1443 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1444 __ cset(rscratch1, Assembler::NE);
1445 __ membar(__ AnyAny);
1446 }
1447
1448
1449 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1450 Register addr;
1451 if (op->addr()->is_register()) {
1452 addr = as_reg(op->addr());
1453 } else {
1454 assert(op->addr()->is_address(), "what else?");
1455 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1456 assert(addr_ptr->disp() == 0, "need 0 disp");
1457 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1458 addr = as_reg(addr_ptr->base());
1459 }
1460 Register newval = as_reg(op->new_value());
1461 Register cmpval = as_reg(op->cmp_value());
1462
1463 if (op->code() == lir_cas_obj) {
1464 if (UseCompressedOops) {
1465 Register t1 = op->tmp1()->as_register();
1466 assert(op->tmp1()->is_valid(), "must be");
1467 __ encode_heap_oop(t1, cmpval);
1468 cmpval = t1;
1469 __ encode_heap_oop(rscratch2, newval);
1470 newval = rscratch2;
1471 casw(addr, newval, cmpval);
1472 } else {
1473 casl(addr, newval, cmpval);
1474 }
1475 } else if (op->code() == lir_cas_int) {
1476 casw(addr, newval, cmpval);
1477 } else {
1478 casl(addr, newval, cmpval);
1479 }
1480 }
1481
1482
1483 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1484 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1485 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1486
1487 Assembler::Condition acond, ncond;
1488 switch (condition) {
1489 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1490 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1491 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1492 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1493 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1494 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1495 case lir_cond_belowEqual:
1496 case lir_cond_aboveEqual:
1497 default: ShouldNotReachHere();
1498 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1499 }
1500
1501 assert(result->is_single_cpu() || result->is_double_cpu(),
1502 "expect single register for result");
1503 if (opr1->is_constant() && opr2->is_constant()
1504 && opr1->type() == T_INT && opr2->type() == T_INT) {
1505 jint val1 = opr1->as_jint();
1506 jint val2 = opr2->as_jint();
1507 if (val1 == 0 && val2 == 1) {
1508 __ cset(result->as_register(), ncond);
1509 return;
1510 } else if (val1 == 1 && val2 == 0) {
1511 __ cset(result->as_register(), acond);
1512 return;
1513 }
1514 }
1515
1516 if (opr1->is_constant() && opr2->is_constant()
1517 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1518 jlong val1 = opr1->as_jlong();
1519 jlong val2 = opr2->as_jlong();
1520 if (val1 == 0 && val2 == 1) {
1521 __ cset(result->as_register_lo(), ncond);
1522 return;
1523 } else if (val1 == 1 && val2 == 0) {
1524 __ cset(result->as_register_lo(), acond);
1525 return;
1526 }
1527 }
1528
1529 if (opr1->is_stack()) {
1530 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1531 opr1 = FrameMap::rscratch1_opr;
1532 } else if (opr1->is_constant()) {
1533 LIR_Opr tmp
1534 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1535 const2reg(opr1, tmp, lir_patch_none, nullptr);
1536 opr1 = tmp;
1537 }
1538
1539 if (opr2->is_stack()) {
1540 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1541 opr2 = FrameMap::rscratch2_opr;
1542 } else if (opr2->is_constant()) {
1543 LIR_Opr tmp
1544 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1545 const2reg(opr2, tmp, lir_patch_none, nullptr);
1546 opr2 = tmp;
1547 }
1548
1549 if (result->type() == T_LONG)
1550 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1551 else
1552 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1553 }
1554
1555 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1556 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1557
1558 if (left->is_single_cpu()) {
1559 Register lreg = left->as_register();
1560 Register dreg = as_reg(dest);
1561
1562 if (right->is_single_cpu()) {
1563 // cpu register - cpu register
1564
1565 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1566 "should be");
1567 Register rreg = right->as_register();
1568 switch (code) {
1569 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1570 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1571 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1572 default: ShouldNotReachHere();
1573 }
1574
1575 } else if (right->is_double_cpu()) {
1576 Register rreg = right->as_register_lo();
1577 // single_cpu + double_cpu: can happen with obj+long
1578 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1579 switch (code) {
1580 case lir_add: __ add(dreg, lreg, rreg); break;
1581 case lir_sub: __ sub(dreg, lreg, rreg); break;
1582 default: ShouldNotReachHere();
1583 }
1584 } else if (right->is_constant()) {
1585 // cpu register - constant
1586 jlong c;
1587
1588 // FIXME. This is fugly: we really need to factor all this logic.
1589 switch(right->type()) {
1590 case T_LONG:
1591 c = right->as_constant_ptr()->as_jlong();
1592 break;
1593 case T_INT:
1594 case T_ADDRESS:
1595 c = right->as_constant_ptr()->as_jint();
1596 break;
1597 default:
1598 ShouldNotReachHere();
1599 c = 0; // unreachable
1600 break;
1601 }
1602
1603 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1604 if (c == 0 && dreg == lreg) {
1605 COMMENT("effective nop elided");
1606 return;
1607 }
1608 switch(left->type()) {
1609 case T_INT:
1610 switch (code) {
1611 case lir_add: __ addw(dreg, lreg, c); break;
1612 case lir_sub: __ subw(dreg, lreg, c); break;
1613 default: ShouldNotReachHere();
1614 }
1615 break;
1616 case T_OBJECT:
1617 case T_ADDRESS:
1618 switch (code) {
1619 case lir_add: __ add(dreg, lreg, c); break;
1620 case lir_sub: __ sub(dreg, lreg, c); break;
1621 default: ShouldNotReachHere();
1622 }
1623 break;
1624 default:
1625 ShouldNotReachHere();
1626 }
1627 } else {
1628 ShouldNotReachHere();
1629 }
1630
1631 } else if (left->is_double_cpu()) {
1632 Register lreg_lo = left->as_register_lo();
1633
1634 if (right->is_double_cpu()) {
1635 // cpu register - cpu register
1636 Register rreg_lo = right->as_register_lo();
1637 switch (code) {
1638 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1639 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1640 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1641 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1642 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1643 default:
1644 ShouldNotReachHere();
1645 }
1646
1647 } else if (right->is_constant()) {
1648 jlong c = right->as_constant_ptr()->as_jlong();
1649 Register dreg = as_reg(dest);
1650 switch (code) {
1651 case lir_add:
1652 case lir_sub:
1653 if (c == 0 && dreg == lreg_lo) {
1654 COMMENT("effective nop elided");
1655 return;
1656 }
1657 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1658 break;
1659 case lir_div:
1660 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1661 if (c == 1) {
1662 // move lreg_lo to dreg if divisor is 1
1663 __ mov(dreg, lreg_lo);
1664 } else {
1665 unsigned int shift = log2i_exact(c);
1666 // use rscratch1 as intermediate result register
1667 __ asr(rscratch1, lreg_lo, 63);
1668 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1669 __ asr(dreg, rscratch1, shift);
1670 }
1671 break;
1672 case lir_rem:
1673 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1674 if (c == 1) {
1675 // move 0 to dreg if divisor is 1
1676 __ mov(dreg, zr);
1677 } else {
1678 // use rscratch1 as intermediate result register
1679 __ negs(rscratch1, lreg_lo);
1680 __ andr(dreg, lreg_lo, c - 1);
1681 __ andr(rscratch1, rscratch1, c - 1);
1682 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1683 }
1684 break;
1685 default:
1686 ShouldNotReachHere();
1687 }
1688 } else {
1689 ShouldNotReachHere();
1690 }
1691 } else if (left->is_single_fpu()) {
1692 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1693 switch (code) {
1694 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1695 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1696 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1697 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1698 default:
1699 ShouldNotReachHere();
1700 }
1701 } else if (left->is_double_fpu()) {
1702 if (right->is_double_fpu()) {
1703 // fpu register - fpu register
1704 switch (code) {
1705 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1706 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1707 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1708 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1709 default:
1710 ShouldNotReachHere();
1711 }
1712 } else {
1713 if (right->is_constant()) {
1714 ShouldNotReachHere();
1715 }
1716 ShouldNotReachHere();
1717 }
1718 } else if (left->is_single_stack() || left->is_address()) {
1719 assert(left == dest, "left and dest must be equal");
1720 ShouldNotReachHere();
1721 } else {
1722 ShouldNotReachHere();
1723 }
1724 }
1725
1726 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1727 switch(code) {
1728 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1729 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1730 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1731 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1732 default : ShouldNotReachHere();
1733 }
1734 }
1735
1736 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1737
1738 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1739 Register Rleft = left->is_single_cpu() ? left->as_register() :
1740 left->as_register_lo();
1741 if (dst->is_single_cpu()) {
1742 Register Rdst = dst->as_register();
1743 if (right->is_constant()) {
1744 switch (code) {
1745 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1746 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1747 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1748 default: ShouldNotReachHere(); break;
1749 }
1750 } else {
1751 Register Rright = right->is_single_cpu() ? right->as_register() :
1752 right->as_register_lo();
1753 switch (code) {
1754 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1755 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1756 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1757 default: ShouldNotReachHere(); break;
1758 }
1759 }
1760 } else {
1761 Register Rdst = dst->as_register_lo();
1762 if (right->is_constant()) {
1763 switch (code) {
1764 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1765 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1766 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1767 default: ShouldNotReachHere(); break;
1768 }
1769 } else {
1770 Register Rright = right->is_single_cpu() ? right->as_register() :
1771 right->as_register_lo();
1772 switch (code) {
1773 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1774 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1775 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1776 default: ShouldNotReachHere(); break;
1777 }
1778 }
1779 }
1780 }
1781
1782
1783
1784 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1785
1786 // opcode check
1787 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1788 bool is_irem = (code == lir_irem);
1789
1790 // operand check
1791 assert(left->is_single_cpu(), "left must be register");
1792 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1793 assert(result->is_single_cpu(), "result must be register");
1794 Register lreg = left->as_register();
1795 Register dreg = result->as_register();
1796
1797 // power-of-2 constant check and codegen
1798 if (right->is_constant()) {
1799 int c = right->as_constant_ptr()->as_jint();
1800 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1801 if (is_irem) {
1802 if (c == 1) {
1803 // move 0 to dreg if divisor is 1
1804 __ movw(dreg, zr);
1805 } else {
1806 // use rscratch1 as intermediate result register
1807 __ negsw(rscratch1, lreg);
1808 __ andw(dreg, lreg, c - 1);
1809 __ andw(rscratch1, rscratch1, c - 1);
1810 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1811 }
1812 } else {
1813 if (c == 1) {
1814 // move lreg to dreg if divisor is 1
1815 __ movw(dreg, lreg);
1816 } else {
1817 unsigned int shift = exact_log2(c);
1818 // use rscratch1 as intermediate result register
1819 __ asrw(rscratch1, lreg, 31);
1820 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1821 __ asrw(dreg, rscratch1, shift);
1822 }
1823 }
1824 } else {
1825 Register rreg = right->as_register();
1826 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1827 }
1828 }
1829
1830
1831 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1832 if (opr1->is_constant() && opr2->is_single_cpu()) {
1833 // tableswitch
1834 Register reg = as_reg(opr2);
1835 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1836 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1837 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1838 Register reg1 = as_reg(opr1);
1839 if (opr2->is_single_cpu()) {
1840 // cpu register - cpu register
1841 Register reg2 = opr2->as_register();
1842 if (is_reference_type(opr1->type())) {
1843 __ cmpoop(reg1, reg2);
1844 } else {
1845 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1846 __ cmpw(reg1, reg2);
1847 }
1848 return;
1849 }
1850 if (opr2->is_double_cpu()) {
1851 // cpu register - cpu register
1852 Register reg2 = opr2->as_register_lo();
1853 __ cmp(reg1, reg2);
1854 return;
1855 }
1856
1857 if (opr2->is_constant()) {
1858 bool is_32bit = false; // width of register operand
1859 jlong imm;
1860
1861 switch(opr2->type()) {
1862 case T_INT:
1863 imm = opr2->as_constant_ptr()->as_jint();
1864 is_32bit = true;
1865 break;
1866 case T_LONG:
1867 imm = opr2->as_constant_ptr()->as_jlong();
1868 break;
1869 case T_ADDRESS:
1870 imm = opr2->as_constant_ptr()->as_jint();
1871 break;
1872 case T_METADATA:
1873 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1874 break;
1875 case T_OBJECT:
1876 case T_ARRAY:
1877 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1878 __ cmpoop(reg1, rscratch1);
1879 return;
1880 default:
1881 ShouldNotReachHere();
1882 imm = 0; // unreachable
1883 break;
1884 }
1885
1886 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1887 if (is_32bit)
1888 __ cmpw(reg1, imm);
1889 else
1890 __ subs(zr, reg1, imm);
1891 return;
1892 } else {
1893 __ mov(rscratch1, imm);
1894 if (is_32bit)
1895 __ cmpw(reg1, rscratch1);
1896 else
1897 __ cmp(reg1, rscratch1);
1898 return;
1899 }
1900 } else
1901 ShouldNotReachHere();
1902 } else if (opr1->is_single_fpu()) {
1903 FloatRegister reg1 = opr1->as_float_reg();
1904 assert(opr2->is_single_fpu(), "expect single float register");
1905 FloatRegister reg2 = opr2->as_float_reg();
1906 __ fcmps(reg1, reg2);
1907 } else if (opr1->is_double_fpu()) {
1908 FloatRegister reg1 = opr1->as_double_reg();
1909 assert(opr2->is_double_fpu(), "expect double float register");
1910 FloatRegister reg2 = opr2->as_double_reg();
1911 __ fcmpd(reg1, reg2);
1912 } else {
1913 ShouldNotReachHere();
1914 }
1915 }
1916
1917 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1918 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1919 bool is_unordered_less = (code == lir_ucmp_fd2i);
1920 if (left->is_single_fpu()) {
1921 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1922 } else if (left->is_double_fpu()) {
1923 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1924 } else {
1925 ShouldNotReachHere();
1926 }
1927 } else if (code == lir_cmp_l2i) {
1928 Label done;
1929 __ cmp(left->as_register_lo(), right->as_register_lo());
1930 __ mov(dst->as_register(), (uint64_t)-1L);
1931 __ br(Assembler::LT, done);
1932 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1933 __ bind(done);
1934 } else {
1935 ShouldNotReachHere();
1936 }
1937 }
1938
1939
1940 void LIR_Assembler::align_call(LIR_Code code) { }
1941
1942
1943 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
1944 address call = __ trampoline_call(Address(op->addr(), rtype));
1945 if (call == nullptr) {
1946 bailout("trampoline stub overflow");
1947 return;
1948 }
1949 add_call_info(code_offset(), op->info());
1950 __ post_call_nop();
1951 }
1952
1953
1954 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
1955 address call = __ ic_call(op->addr());
1956 if (call == nullptr) {
1957 bailout("trampoline stub overflow");
1958 return;
1959 }
1960 add_call_info(code_offset(), op->info());
1961 __ post_call_nop();
1962 }
1963
1964 void LIR_Assembler::emit_static_call_stub() {
1965 address call_pc = __ pc();
1966 address stub = __ start_a_stub(call_stub_size());
1967 if (stub == nullptr) {
1968 bailout("static call stub overflow");
1969 return;
1970 }
1971
1972 int start = __ offset();
1973
1974 __ relocate(static_stub_Relocation::spec(call_pc));
1975 __ emit_static_call_stub();
1976
1977 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
1978 <= call_stub_size(), "stub too big");
1979 __ end_a_stub();
1980 }
1981
1982
1983 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1984 assert(exceptionOop->as_register() == r0, "must match");
1985 assert(exceptionPC->as_register() == r3, "must match");
1986
1987 // exception object is not added to oop map by LinearScan
1988 // (LinearScan assumes that no oops are in fixed registers)
1989 info->add_register_oop(exceptionOop);
1990 StubId unwind_id;
1991
1992 // get current pc information
1993 // pc is only needed if the method has an exception handler, the unwind code does not need it.
1994 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
1995 // As no instructions have been generated yet for this LIR node it's
1996 // possible that an oop map already exists for the current offset.
1997 // In that case insert an dummy NOP here to ensure all oop map PCs
1998 // are unique. See JDK-8237483.
1999 __ nop();
2000 }
2001 int pc_for_athrow_offset = __ offset();
2002 InternalAddress pc_for_athrow(__ pc());
2003 __ adr(exceptionPC->as_register(), pc_for_athrow);
2004 add_call_info(pc_for_athrow_offset, info); // for exception handler
2005
2006 __ verify_not_null_oop(r0);
2007 // search an exception handler (r0: exception oop, r3: throwing pc)
2008 if (compilation()->has_fpu_code()) {
2009 unwind_id = StubId::c1_handle_exception_id;
2010 } else {
2011 unwind_id = StubId::c1_handle_exception_nofpu_id;
2012 }
2013 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2014
2015 // FIXME: enough room for two byte trap ????
2016 __ nop();
2017 }
2018
2019
2020 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2021 assert(exceptionOop->as_register() == r0, "must match");
2022
2023 __ b(_unwind_handler_entry);
2024 }
2025
2026
2027 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2028 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2029 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2030
2031 switch (left->type()) {
2032 case T_INT: {
2033 switch (code) {
2034 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2035 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2036 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2037 default:
2038 ShouldNotReachHere();
2039 break;
2040 }
2041 break;
2042 case T_LONG:
2043 case T_ADDRESS:
2044 case T_OBJECT:
2045 switch (code) {
2046 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2047 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2048 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2049 default:
2050 ShouldNotReachHere();
2051 break;
2052 }
2053 break;
2054 default:
2055 ShouldNotReachHere();
2056 break;
2057 }
2058 }
2059 }
2060
2061
2062 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2063 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2064 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2065
2066 switch (left->type()) {
2067 case T_INT: {
2068 switch (code) {
2069 case lir_shl: __ lslw (dreg, lreg, count); break;
2070 case lir_shr: __ asrw (dreg, lreg, count); break;
2071 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2072 default:
2073 ShouldNotReachHere();
2074 break;
2075 }
2076 break;
2077 case T_LONG:
2078 case T_ADDRESS:
2079 case T_OBJECT:
2080 switch (code) {
2081 case lir_shl: __ lsl (dreg, lreg, count); break;
2082 case lir_shr: __ asr (dreg, lreg, count); break;
2083 case lir_ushr: __ lsr (dreg, lreg, count); break;
2084 default:
2085 ShouldNotReachHere();
2086 break;
2087 }
2088 break;
2089 default:
2090 ShouldNotReachHere();
2091 break;
2092 }
2093 }
2094 }
2095
2096
2097 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2098 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2099 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2100 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2101 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2102 }
2103
2104
2105 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2106 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2107 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2108 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2109 __ mov (rscratch1, c);
2110 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2111 }
2112
2113
2114 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2115 ShouldNotReachHere();
2116 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2117 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2118 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2119 __ lea(rscratch1, __ constant_oop_address(o));
2120 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2121 }
2122
2123
2124 // This code replaces a call to arraycopy; no exception may
2125 // be thrown in this code, they must be thrown in the System.arraycopy
2126 // activation frame; we could save some checks if this would not be the case
2127 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2128 ciArrayKlass* default_type = op->expected_type();
2129 Register src = op->src()->as_register();
2130 Register dst = op->dst()->as_register();
2131 Register src_pos = op->src_pos()->as_register();
2132 Register dst_pos = op->dst_pos()->as_register();
2133 Register length = op->length()->as_register();
2134 Register tmp = op->tmp()->as_register();
2135
2136 CodeStub* stub = op->stub();
2137 int flags = op->flags();
2138 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2139 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2140
2141 // if we don't know anything, just go through the generic arraycopy
2142 if (default_type == nullptr // || basic_type == T_OBJECT
2143 ) {
2144 Label done;
2145 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2146
2147 // Save the arguments in case the generic arraycopy fails and we
2148 // have to fall back to the JNI stub
2149 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2150 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2151 __ str(src, Address(sp, 4*BytesPerWord));
2152
2153 address copyfunc_addr = StubRoutines::generic_arraycopy();
2154 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2155
2156 // The arguments are in java calling convention so we shift them
2157 // to C convention
2158 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2159 __ mov(c_rarg0, j_rarg0);
2160 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2161 __ mov(c_rarg1, j_rarg1);
2162 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2163 __ mov(c_rarg2, j_rarg2);
2164 assert_different_registers(c_rarg3, j_rarg4);
2165 __ mov(c_rarg3, j_rarg3);
2166 __ mov(c_rarg4, j_rarg4);
2167 #ifndef PRODUCT
2168 if (PrintC1Statistics) {
2169 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2170 }
2171 #endif
2172 __ far_call(RuntimeAddress(copyfunc_addr));
2173
2174 __ cbz(r0, *stub->continuation());
2175
2176 // Reload values from the stack so they are where the stub
2177 // expects them.
2178 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2179 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2180 __ ldr(src, Address(sp, 4*BytesPerWord));
2181
2182 // r0 is -1^K where K == partial copied count
2183 __ eonw(rscratch1, r0, zr);
2184 // adjust length down and src/end pos up by partial copied count
2185 __ subw(length, length, rscratch1);
2186 __ addw(src_pos, src_pos, rscratch1);
2187 __ addw(dst_pos, dst_pos, rscratch1);
2188 __ b(*stub->entry());
2189
2190 __ bind(*stub->continuation());
2191 return;
2192 }
2193
2194 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2195
2196 int elem_size = type2aelembytes(basic_type);
2197 int scale = exact_log2(elem_size);
2198
2199 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2200 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2201
2202 // test for null
2203 if (flags & LIR_OpArrayCopy::src_null_check) {
2204 __ cbz(src, *stub->entry());
2205 }
2206 if (flags & LIR_OpArrayCopy::dst_null_check) {
2207 __ cbz(dst, *stub->entry());
2208 }
2209
2210 // If the compiler was not able to prove that exact type of the source or the destination
2211 // of the arraycopy is an array type, check at runtime if the source or the destination is
2212 // an instance type.
2213 if (flags & LIR_OpArrayCopy::type_check) {
2214 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2215 __ load_klass(tmp, dst);
2216 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2217 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2218 __ br(Assembler::GE, *stub->entry());
2219 }
2220
2221 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2222 __ load_klass(tmp, src);
2223 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2224 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2225 __ br(Assembler::GE, *stub->entry());
2226 }
2227 }
2228
2229 // check if negative
2230 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2231 __ cmpw(src_pos, 0);
2232 __ br(Assembler::LT, *stub->entry());
2233 }
2234 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2235 __ cmpw(dst_pos, 0);
2236 __ br(Assembler::LT, *stub->entry());
2237 }
2238
2239 if (flags & LIR_OpArrayCopy::length_positive_check) {
2240 __ cmpw(length, 0);
2241 __ br(Assembler::LT, *stub->entry());
2242 }
2243
2244 if (flags & LIR_OpArrayCopy::src_range_check) {
2245 __ addw(tmp, src_pos, length);
2246 __ ldrw(rscratch1, src_length_addr);
2247 __ cmpw(tmp, rscratch1);
2248 __ br(Assembler::HI, *stub->entry());
2249 }
2250 if (flags & LIR_OpArrayCopy::dst_range_check) {
2251 __ addw(tmp, dst_pos, length);
2252 __ ldrw(rscratch1, dst_length_addr);
2253 __ cmpw(tmp, rscratch1);
2254 __ br(Assembler::HI, *stub->entry());
2255 }
2256
2257 if (flags & LIR_OpArrayCopy::type_check) {
2258 // We don't know the array types are compatible
2259 if (basic_type != T_OBJECT) {
2260 // Simple test for basic type arrays
2261 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2262 __ br(Assembler::NE, *stub->entry());
2263 } else {
2264 // For object arrays, if src is a sub class of dst then we can
2265 // safely do the copy.
2266 Label cont, slow;
2267
2268 #define PUSH(r1, r2) \
2269 stp(r1, r2, __ pre(sp, -2 * wordSize));
2270
2271 #define POP(r1, r2) \
2272 ldp(r1, r2, __ post(sp, 2 * wordSize));
2273
2274 __ PUSH(src, dst);
2275
2276 __ load_klass(src, src);
2277 __ load_klass(dst, dst);
2278
2279 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2280
2281 __ PUSH(src, dst);
2282 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2283 __ POP(src, dst);
2284
2285 __ cbnz(src, cont);
2286
2287 __ bind(slow);
2288 __ POP(src, dst);
2289
2290 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2291 if (copyfunc_addr != nullptr) { // use stub if available
2292 // src is not a sub class of dst so we have to do a
2293 // per-element check.
2294
2295 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2296 if ((flags & mask) != mask) {
2297 // Check that at least both of them object arrays.
2298 assert(flags & mask, "one of the two should be known to be an object array");
2299
2300 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2301 __ load_klass(tmp, src);
2302 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2303 __ load_klass(tmp, dst);
2304 }
2305 int lh_offset = in_bytes(Klass::layout_helper_offset());
2306 Address klass_lh_addr(tmp, lh_offset);
2307 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2308 __ ldrw(rscratch1, klass_lh_addr);
2309 __ mov(rscratch2, objArray_lh);
2310 __ eorw(rscratch1, rscratch1, rscratch2);
2311 __ cbnzw(rscratch1, *stub->entry());
2312 }
2313
2314 // Spill because stubs can use any register they like and it's
2315 // easier to restore just those that we care about.
2316 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2317 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2318 __ str(src, Address(sp, 4*BytesPerWord));
2319
2320 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2321 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2322 assert_different_registers(c_rarg0, dst, dst_pos, length);
2323 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2324 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2325 assert_different_registers(c_rarg1, dst, length);
2326 __ uxtw(c_rarg2, length);
2327 assert_different_registers(c_rarg2, dst);
2328
2329 __ load_klass(c_rarg4, dst);
2330 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2331 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2332 __ far_call(RuntimeAddress(copyfunc_addr));
2333
2334 #ifndef PRODUCT
2335 if (PrintC1Statistics) {
2336 Label failed;
2337 __ cbnz(r0, failed);
2338 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2339 __ bind(failed);
2340 }
2341 #endif
2342
2343 __ cbz(r0, *stub->continuation());
2344
2345 #ifndef PRODUCT
2346 if (PrintC1Statistics) {
2347 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2348 }
2349 #endif
2350 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2351
2352 // Restore previously spilled arguments
2353 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2354 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2355 __ ldr(src, Address(sp, 4*BytesPerWord));
2356
2357 // return value is -1^K where K is partial copied count
2358 __ eonw(rscratch1, r0, zr);
2359 // adjust length down and src/end pos up by partial copied count
2360 __ subw(length, length, rscratch1);
2361 __ addw(src_pos, src_pos, rscratch1);
2362 __ addw(dst_pos, dst_pos, rscratch1);
2363 }
2364
2365 __ b(*stub->entry());
2366
2367 __ bind(cont);
2368 __ POP(src, dst);
2369 }
2370 }
2371
2372 #ifdef ASSERT
2373 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2374 // Sanity check the known type with the incoming class. For the
2375 // primitive case the types must match exactly with src.klass and
2376 // dst.klass each exactly matching the default type. For the
2377 // object array case, if no type check is needed then either the
2378 // dst type is exactly the expected type and the src type is a
2379 // subtype which we can't check or src is the same array as dst
2380 // but not necessarily exactly of type default_type.
2381 Label known_ok, halt;
2382 __ mov_metadata(tmp, default_type->constant_encoding());
2383
2384 if (basic_type != T_OBJECT) {
2385 __ cmp_klass(dst, tmp, rscratch1);
2386 __ br(Assembler::NE, halt);
2387 __ cmp_klass(src, tmp, rscratch1);
2388 __ br(Assembler::EQ, known_ok);
2389 } else {
2390 __ cmp_klass(dst, tmp, rscratch1);
2391 __ br(Assembler::EQ, known_ok);
2392 __ cmp(src, dst);
2393 __ br(Assembler::EQ, known_ok);
2394 }
2395 __ bind(halt);
2396 __ stop("incorrect type information in arraycopy");
2397 __ bind(known_ok);
2398 }
2399 #endif
2400
2401 #ifndef PRODUCT
2402 if (PrintC1Statistics) {
2403 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2404 }
2405 #endif
2406
2407 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2408 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2409 assert_different_registers(c_rarg0, dst, dst_pos, length);
2410 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2411 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2412 assert_different_registers(c_rarg1, dst, length);
2413 __ uxtw(c_rarg2, length);
2414 assert_different_registers(c_rarg2, dst);
2415
2416 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2417 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2418 const char *name;
2419 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2420
2421 CodeBlob *cb = CodeCache::find_blob(entry);
2422 if (cb) {
2423 __ far_call(RuntimeAddress(entry));
2424 } else {
2425 __ call_VM_leaf(entry, 3);
2426 }
2427
2428 if (stub != nullptr) {
2429 __ bind(*stub->continuation());
2430 }
2431 }
2432
2433
2434
2435
2436 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2437 Register obj = op->obj_opr()->as_register(); // may not be an oop
2438 Register hdr = op->hdr_opr()->as_register();
2439 Register lock = op->lock_opr()->as_register();
2440 Register temp = op->scratch_opr()->as_register();
2441 if (op->code() == lir_lock) {
2442 // add debug info for NullPointerException only if one is possible
2443 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2444 if (op->info() != nullptr) {
2445 add_debug_info_for_null_check(null_check_offset, op->info());
2446 }
2447 // done
2448 } else if (op->code() == lir_unlock) {
2449 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2450 } else {
2451 Unimplemented();
2452 }
2453 __ bind(*op->stub()->continuation());
2454 }
2455
2456 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2457 Register obj = op->obj()->as_pointer_register();
2458 Register result = op->result_opr()->as_pointer_register();
2459
2460 CodeEmitInfo* info = op->info();
2461 if (info != nullptr) {
2462 add_debug_info_for_null_check_here(info);
2463 }
2464
2465 __ load_klass(result, obj);
2466 }
2467
2468 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2469 ciMethod* method = op->profiled_method();
2470 int bci = op->profiled_bci();
2471 ciMethod* callee = op->profiled_callee();
2472
2473 // Update counter for all call types
2474 ciMethodData* md = method->method_data_or_null();
2475 assert(md != nullptr, "Sanity");
2476 ciProfileData* data = md->bci_to_data(bci);
2477 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2478 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2479 Register mdo = op->mdo()->as_register();
2480 __ mov_metadata(mdo, md->constant_encoding());
2481 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2482 // Perform additional virtual call profiling for invokevirtual and
2483 // invokeinterface bytecodes
2484 if (op->should_profile_receiver_type()) {
2485 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2486 Register recv = op->recv()->as_register();
2487 assert_different_registers(mdo, recv);
2488 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2489 ciKlass* known_klass = op->known_holder();
2490 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2491 // We know the type that will be seen at this call site; we can
2492 // statically update the MethodData* rather than needing to do
2493 // dynamic tests on the receiver type.
2494 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2495 for (uint i = 0; i < VirtualCallData::row_limit(); i++) {
2496 ciKlass* receiver = vc_data->receiver(i);
2497 if (known_klass->equals(receiver)) {
2498 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2499 __ addptr(data_addr, DataLayout::counter_increment);
2500 return;
2501 }
2502 }
2503 // Receiver type is not found in profile data.
2504 // Fall back to runtime helper to handle the rest at runtime.
2505 __ mov_metadata(recv, known_klass->constant_encoding());
2506 } else {
2507 __ load_klass(recv, recv);
2508 }
2509 type_profile_helper(mdo, md, data, recv);
2510 } else {
2511 // Static call
2512 __ addptr(counter_addr, DataLayout::counter_increment);
2513 }
2514 }
2515
2516
2517 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2518 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2519 }
2520
2521 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2522 assert(op->crc()->is_single_cpu(), "crc must be register");
2523 assert(op->val()->is_single_cpu(), "byte value must be register");
2524 assert(op->result_opr()->is_single_cpu(), "result must be register");
2525 Register crc = op->crc()->as_register();
2526 Register val = op->val()->as_register();
2527 Register res = op->result_opr()->as_register();
2528
2529 assert_different_registers(val, crc, res);
2530 uint64_t offset;
2531 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2532 __ add(res, res, offset);
2533
2534 __ mvnw(crc, crc); // ~crc
2535 __ update_byte_crc32(crc, val, res);
2536 __ mvnw(res, crc); // ~crc
2537 }
2538
2539 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2540 COMMENT("emit_profile_type {");
2541 Register obj = op->obj()->as_register();
2542 Register tmp = op->tmp()->as_pointer_register();
2543 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2544 ciKlass* exact_klass = op->exact_klass();
2545 intptr_t current_klass = op->current_klass();
2546 bool not_null = op->not_null();
2547 bool no_conflict = op->no_conflict();
2548
2549 Label update, next, none;
2550
2551 bool do_null = !not_null;
2552 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2553 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2554
2555 assert(do_null || do_update, "why are we here?");
2556 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2557 assert(mdo_addr.base() != rscratch1, "wrong register");
2558
2559 __ verify_oop(obj);
2560
2561 if (tmp != obj) {
2562 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2563 __ mov(tmp, obj);
2564 } else {
2565 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2566 }
2567 if (do_null) {
2568 __ cbnz(tmp, update);
2569 if (!TypeEntries::was_null_seen(current_klass)) {
2570 __ ldr(rscratch2, mdo_addr);
2571 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2572 __ str(rscratch2, mdo_addr);
2573 }
2574 if (do_update) {
2575 #ifndef ASSERT
2576 __ b(next);
2577 }
2578 #else
2579 __ b(next);
2580 }
2581 } else {
2582 __ cbnz(tmp, update);
2583 __ stop("unexpected null obj");
2584 #endif
2585 }
2586
2587 __ bind(update);
2588
2589 if (do_update) {
2590 #ifdef ASSERT
2591 if (exact_klass != nullptr) {
2592 Label ok;
2593 __ load_klass(tmp, tmp);
2594 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2595 __ eor(rscratch1, tmp, rscratch1);
2596 __ cbz(rscratch1, ok);
2597 __ stop("exact klass and actual klass differ");
2598 __ bind(ok);
2599 }
2600 #endif
2601 if (!no_conflict) {
2602 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2603 if (exact_klass != nullptr) {
2604 __ mov_metadata(tmp, exact_klass->constant_encoding());
2605 } else {
2606 __ load_klass(tmp, tmp);
2607 }
2608
2609 __ ldr(rscratch2, mdo_addr);
2610 __ eor(tmp, tmp, rscratch2);
2611 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2612 // klass seen before, nothing to do. The unknown bit may have been
2613 // set already but no need to check.
2614 __ cbz(rscratch1, next);
2615
2616 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2617
2618 if (TypeEntries::is_type_none(current_klass)) {
2619 __ cbz(rscratch2, none);
2620 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2621 __ br(Assembler::EQ, none);
2622 // There is a chance that the checks above
2623 // fail if another thread has just set the
2624 // profiling to this obj's klass
2625 __ dmb(Assembler::ISHLD);
2626 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2627 __ ldr(rscratch2, mdo_addr);
2628 __ eor(tmp, tmp, rscratch2);
2629 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2630 __ cbz(rscratch1, next);
2631 }
2632 } else {
2633 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2634 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2635
2636 __ ldr(tmp, mdo_addr);
2637 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2638 }
2639
2640 // different than before. Cannot keep accurate profile.
2641 __ ldr(rscratch2, mdo_addr);
2642 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2643 __ str(rscratch2, mdo_addr);
2644
2645 if (TypeEntries::is_type_none(current_klass)) {
2646 __ b(next);
2647
2648 __ bind(none);
2649 // first time here. Set profile type.
2650 __ str(tmp, mdo_addr);
2651 #ifdef ASSERT
2652 __ andr(tmp, tmp, TypeEntries::type_mask);
2653 __ verify_klass_ptr(tmp);
2654 #endif
2655 }
2656 } else {
2657 // There's a single possible klass at this profile point
2658 assert(exact_klass != nullptr, "should be");
2659 if (TypeEntries::is_type_none(current_klass)) {
2660 __ mov_metadata(tmp, exact_klass->constant_encoding());
2661 __ ldr(rscratch2, mdo_addr);
2662 __ eor(tmp, tmp, rscratch2);
2663 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2664 __ cbz(rscratch1, next);
2665 #ifdef ASSERT
2666 {
2667 Label ok;
2668 __ ldr(rscratch1, mdo_addr);
2669 __ cbz(rscratch1, ok);
2670 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2671 __ br(Assembler::EQ, ok);
2672 // may have been set by another thread
2673 __ dmb(Assembler::ISHLD);
2674 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2675 __ ldr(rscratch2, mdo_addr);
2676 __ eor(rscratch2, rscratch1, rscratch2);
2677 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2678 __ cbz(rscratch2, ok);
2679
2680 __ stop("unexpected profiling mismatch");
2681 __ bind(ok);
2682 }
2683 #endif
2684 // first time here. Set profile type.
2685 __ str(tmp, mdo_addr);
2686 #ifdef ASSERT
2687 __ andr(tmp, tmp, TypeEntries::type_mask);
2688 __ verify_klass_ptr(tmp);
2689 #endif
2690 } else {
2691 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2692 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2693
2694 __ ldr(tmp, mdo_addr);
2695 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2696
2697 __ orr(tmp, tmp, TypeEntries::type_unknown);
2698 __ str(tmp, mdo_addr);
2699 // FIXME: Write barrier needed here?
2700 }
2701 }
2702
2703 __ bind(next);
2704 }
2705 COMMENT("} emit_profile_type");
2706 }
2707
2708
2709 void LIR_Assembler::align_backward_branch_target() {
2710 }
2711
2712
2713 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2714 // tmp must be unused
2715 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2716
2717 if (left->is_single_cpu()) {
2718 assert(dest->is_single_cpu(), "expect single result reg");
2719 __ negw(dest->as_register(), left->as_register());
2720 } else if (left->is_double_cpu()) {
2721 assert(dest->is_double_cpu(), "expect double result reg");
2722 __ neg(dest->as_register_lo(), left->as_register_lo());
2723 } else if (left->is_single_fpu()) {
2724 assert(dest->is_single_fpu(), "expect single float result reg");
2725 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2726 } else {
2727 assert(left->is_double_fpu(), "expect double float operand reg");
2728 assert(dest->is_double_fpu(), "expect double float result reg");
2729 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2730 }
2731 }
2732
2733
2734 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2735 if (patch_code != lir_patch_none) {
2736 deoptimize_trap(info);
2737 return;
2738 }
2739
2740 __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
2741 }
2742
2743
2744 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2745 assert(!tmp->is_valid(), "don't need temporary");
2746
2747 CodeBlob *cb = CodeCache::find_blob(dest);
2748 if (cb) {
2749 __ far_call(RuntimeAddress(dest));
2750 } else {
2751 __ mov(rscratch1, RuntimeAddress(dest));
2752 __ blr(rscratch1);
2753 }
2754
2755 if (info != nullptr) {
2756 add_call_info_here(info);
2757 }
2758 __ post_call_nop();
2759 }
2760
2761 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2762 if (dest->is_address() || src->is_address()) {
2763 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
2764 } else {
2765 ShouldNotReachHere();
2766 }
2767 }
2768
2769 #ifdef ASSERT
2770 // emit run-time assertion
2771 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2772 assert(op->code() == lir_assert, "must be");
2773
2774 if (op->in_opr1()->is_valid()) {
2775 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2776 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2777 } else {
2778 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2779 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2780 }
2781
2782 Label ok;
2783 if (op->condition() != lir_cond_always) {
2784 Assembler::Condition acond = Assembler::AL;
2785 switch (op->condition()) {
2786 case lir_cond_equal: acond = Assembler::EQ; break;
2787 case lir_cond_notEqual: acond = Assembler::NE; break;
2788 case lir_cond_less: acond = Assembler::LT; break;
2789 case lir_cond_lessEqual: acond = Assembler::LE; break;
2790 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2791 case lir_cond_greater: acond = Assembler::GT; break;
2792 case lir_cond_belowEqual: acond = Assembler::LS; break;
2793 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2794 default: ShouldNotReachHere();
2795 }
2796 __ br(acond, ok);
2797 }
2798 if (op->halt()) {
2799 const char* str = __ code_string(op->msg());
2800 __ stop(str);
2801 } else {
2802 breakpoint();
2803 }
2804 __ bind(ok);
2805 }
2806 #endif
2807
2808 #ifndef PRODUCT
2809 #define COMMENT(x) do { __ block_comment(x); } while (0)
2810 #else
2811 #define COMMENT(x)
2812 #endif
2813
2814 void LIR_Assembler::membar() {
2815 COMMENT("membar");
2816 __ membar(MacroAssembler::AnyAny);
2817 }
2818
2819 void LIR_Assembler::membar_acquire() {
2820 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2821 }
2822
2823 void LIR_Assembler::membar_release() {
2824 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2825 }
2826
2827 void LIR_Assembler::membar_loadload() {
2828 __ membar(Assembler::LoadLoad);
2829 }
2830
2831 void LIR_Assembler::membar_storestore() {
2832 __ membar(MacroAssembler::StoreStore);
2833 }
2834
2835 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2836
2837 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2838
2839 void LIR_Assembler::on_spin_wait() {
2840 __ spin_wait();
2841 }
2842
2843 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2844 __ mov(result_reg->as_register(), rthread);
2845 }
2846
2847
2848 void LIR_Assembler::peephole(LIR_List *lir) {
2849 #if 0
2850 if (tableswitch_count >= max_tableswitches)
2851 return;
2852
2853 /*
2854 This finite-state automaton recognizes sequences of compare-and-
2855 branch instructions. We will turn them into a tableswitch. You
2856 could argue that C1 really shouldn't be doing this sort of
2857 optimization, but without it the code is really horrible.
2858 */
2859
2860 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2861 int first_key, last_key = -2147483648;
2862 int next_key = 0;
2863 int start_insn = -1;
2864 int last_insn = -1;
2865 Register reg = noreg;
2866 LIR_Opr reg_opr;
2867 state = start_s;
2868
2869 LIR_OpList* inst = lir->instructions_list();
2870 for (int i = 0; i < inst->length(); i++) {
2871 LIR_Op* op = inst->at(i);
2872 switch (state) {
2873 case start_s:
2874 first_key = -1;
2875 start_insn = i;
2876 switch (op->code()) {
2877 case lir_cmp:
2878 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2879 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2880 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2881 && opr2->is_constant()
2882 && opr2->type() == T_INT) {
2883 reg_opr = opr1;
2884 reg = opr1->as_register();
2885 first_key = opr2->as_constant_ptr()->as_jint();
2886 next_key = first_key + 1;
2887 state = cmp_s;
2888 goto next_state;
2889 }
2890 break;
2891 }
2892 break;
2893 case cmp_s:
2894 switch (op->code()) {
2895 case lir_branch:
2896 if (op->as_OpBranch()->cond() == lir_cond_equal) {
2897 state = beq_s;
2898 last_insn = i;
2899 goto next_state;
2900 }
2901 }
2902 state = start_s;
2903 break;
2904 case beq_s:
2905 switch (op->code()) {
2906 case lir_cmp: {
2907 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2908 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2909 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2910 && opr1->as_register() == reg
2911 && opr2->is_constant()
2912 && opr2->type() == T_INT
2913 && opr2->as_constant_ptr()->as_jint() == next_key) {
2914 last_key = next_key;
2915 next_key++;
2916 state = cmp_s;
2917 goto next_state;
2918 }
2919 }
2920 }
2921 last_key = next_key;
2922 state = start_s;
2923 break;
2924 default:
2925 assert(false, "impossible state");
2926 }
2927 if (state == start_s) {
2928 if (first_key < last_key - 5L && reg != noreg) {
2929 {
2930 // printf("found run register %d starting at insn %d low value %d high value %d\n",
2931 // reg->encoding(),
2932 // start_insn, first_key, last_key);
2933 // for (int i = 0; i < inst->length(); i++) {
2934 // inst->at(i)->print();
2935 // tty->print("\n");
2936 // }
2937 // tty->print("\n");
2938 }
2939
2940 struct tableswitch *sw = &switches[tableswitch_count];
2941 sw->_insn_index = start_insn, sw->_first_key = first_key,
2942 sw->_last_key = last_key, sw->_reg = reg;
2943 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
2944 {
2945 // Insert the new table of branches
2946 int offset = last_insn;
2947 for (int n = first_key; n < last_key; n++) {
2948 inst->insert_before
2949 (last_insn + 1,
2950 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
2951 inst->at(offset)->as_OpBranch()->label()));
2952 offset -= 2, i++;
2953 }
2954 }
2955 // Delete all the old compare-and-branch instructions
2956 for (int n = first_key; n < last_key; n++) {
2957 inst->remove_at(start_insn);
2958 inst->remove_at(start_insn);
2959 }
2960 // Insert the tableswitch instruction
2961 inst->insert_before(start_insn,
2962 new LIR_Op2(lir_cmp, lir_cond_always,
2963 LIR_OprFact::intConst(tableswitch_count),
2964 reg_opr));
2965 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
2966 tableswitch_count++;
2967 }
2968 reg = noreg;
2969 last_key = -2147483648;
2970 }
2971 next_state:
2972 ;
2973 }
2974 #endif
2975 }
2976
2977 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
2978 Address addr = as_Address(src->as_address_ptr());
2979 BasicType type = src->type();
2980 bool is_oop = is_reference_type(type);
2981
2982 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
2983 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
2984
2985 switch(type) {
2986 case T_INT:
2987 xchg = &MacroAssembler::atomic_xchgalw;
2988 add = &MacroAssembler::atomic_addalw;
2989 break;
2990 case T_LONG:
2991 xchg = &MacroAssembler::atomic_xchgal;
2992 add = &MacroAssembler::atomic_addal;
2993 break;
2994 case T_OBJECT:
2995 case T_ARRAY:
2996 if (UseCompressedOops) {
2997 xchg = &MacroAssembler::atomic_xchgalw;
2998 add = &MacroAssembler::atomic_addalw;
2999 } else {
3000 xchg = &MacroAssembler::atomic_xchgal;
3001 add = &MacroAssembler::atomic_addal;
3002 }
3003 break;
3004 default:
3005 ShouldNotReachHere();
3006 xchg = &MacroAssembler::atomic_xchgal;
3007 add = &MacroAssembler::atomic_addal; // unreachable
3008 }
3009
3010 switch (code) {
3011 case lir_xadd:
3012 {
3013 RegisterOrConstant inc;
3014 Register tmp = as_reg(tmp_op);
3015 Register dst = as_reg(dest);
3016 if (data->is_constant()) {
3017 inc = RegisterOrConstant(as_long(data));
3018 assert_different_registers(dst, addr.base(), tmp,
3019 rscratch1, rscratch2);
3020 } else {
3021 inc = RegisterOrConstant(as_reg(data));
3022 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3023 rscratch1, rscratch2);
3024 }
3025 __ lea(tmp, addr);
3026 (_masm->*add)(dst, inc, tmp);
3027 break;
3028 }
3029 case lir_xchg:
3030 {
3031 Register tmp = tmp_op->as_register();
3032 Register obj = as_reg(data);
3033 Register dst = as_reg(dest);
3034 if (is_oop && UseCompressedOops) {
3035 __ encode_heap_oop(rscratch2, obj);
3036 obj = rscratch2;
3037 }
3038 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3039 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3040 __ lea(tmp, addr);
3041 (_masm->*xchg)(dst, obj, tmp);
3042 if (is_oop && UseCompressedOops) {
3043 __ decode_heap_oop(dst);
3044 }
3045 }
3046 break;
3047 default:
3048 ShouldNotReachHere();
3049 }
3050 if(!UseLSE) {
3051 __ membar(__ AnyAny);
3052 }
3053 }
3054
3055 #undef __