1 /*
2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "code/compiledIC.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_aarch64.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "runtime/frame.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "utilities/powerOfTwo.hpp"
46 #include "vmreg_aarch64.inline.hpp"
47
48
49 #ifndef PRODUCT
50 #define COMMENT(x) do { __ block_comment(x); } while (0)
51 #else
52 #define COMMENT(x)
53 #endif
54
55 NEEDS_CLEANUP // remove this definitions ?
56 const Register SYNC_header = r0; // synchronization header
57 const Register SHIFT_count = r0; // where count for shift operations must be
58
59 #define __ _masm->
60
61
62 static void select_different_registers(Register preserve,
63 Register extra,
64 Register &tmp1,
65 Register &tmp2) {
66 if (tmp1 == preserve) {
67 assert_different_registers(tmp1, tmp2, extra);
68 tmp1 = extra;
69 } else if (tmp2 == preserve) {
70 assert_different_registers(tmp1, tmp2, extra);
71 tmp2 = extra;
72 }
73 assert_different_registers(preserve, tmp1, tmp2);
74 }
75
76
77
78 static void select_different_registers(Register preserve,
79 Register extra,
80 Register &tmp1,
81 Register &tmp2,
82 Register &tmp3) {
83 if (tmp1 == preserve) {
84 assert_different_registers(tmp1, tmp2, tmp3, extra);
85 tmp1 = extra;
86 } else if (tmp2 == preserve) {
87 assert_different_registers(tmp1, tmp2, tmp3, extra);
88 tmp2 = extra;
89 } else if (tmp3 == preserve) {
90 assert_different_registers(tmp1, tmp2, tmp3, extra);
91 tmp3 = extra;
92 }
93 assert_different_registers(preserve, tmp1, tmp2, tmp3);
94 }
95
96
97 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
98
99
100 LIR_Opr LIR_Assembler::receiverOpr() {
101 return FrameMap::receiver_opr;
102 }
103
104 LIR_Opr LIR_Assembler::osrBufferPointer() {
105 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
106 }
107
108 //--------------fpu register translations-----------------------
109
110
111 address LIR_Assembler::float_constant(float f) {
112 address const_addr = __ float_constant(f);
113 if (const_addr == nullptr) {
114 bailout("const section overflow");
115 return __ code()->consts()->start();
116 } else {
117 return const_addr;
118 }
119 }
120
121
122 address LIR_Assembler::double_constant(double d) {
123 address const_addr = __ double_constant(d);
124 if (const_addr == nullptr) {
125 bailout("const section overflow");
126 return __ code()->consts()->start();
127 } else {
128 return const_addr;
129 }
130 }
131
132 address LIR_Assembler::int_constant(jlong n) {
133 address const_addr = __ long_constant(n);
134 if (const_addr == nullptr) {
135 bailout("const section overflow");
136 return __ code()->consts()->start();
137 } else {
138 return const_addr;
139 }
140 }
141
142 void LIR_Assembler::breakpoint() { Unimplemented(); }
143
144 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
145
146 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
147
148 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
149 //-------------------------------------------
150
151 static Register as_reg(LIR_Opr op) {
152 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
153 }
154
155 static jlong as_long(LIR_Opr data) {
156 jlong result;
157 switch (data->type()) {
158 case T_INT:
159 result = (data->as_jint());
160 break;
161 case T_LONG:
162 result = (data->as_jlong());
163 break;
164 default:
165 ShouldNotReachHere();
166 result = 0; // unreachable
167 }
168 return result;
169 }
170
171 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
172 Register base = addr->base()->as_pointer_register();
173 LIR_Opr opr = addr->index();
174 if (opr->is_cpu_register()) {
175 Register index;
176 if (opr->is_single_cpu())
177 index = opr->as_register();
178 else
179 index = opr->as_register_lo();
180 assert(addr->disp() == 0, "must be");
181 switch(opr->type()) {
182 case T_INT:
183 return Address(base, index, Address::sxtw(addr->scale()));
184 case T_LONG:
185 return Address(base, index, Address::lsl(addr->scale()));
186 default:
187 ShouldNotReachHere();
188 }
189 } else {
190 assert(addr->scale() == 0,
191 "expected for immediate operand, was: %d", addr->scale());
192 ptrdiff_t offset = ptrdiff_t(addr->disp());
193 // NOTE: Does not handle any 16 byte vector access.
194 const uint type_size = type2aelembytes(addr->type(), true);
195 return __ legitimize_address(Address(base, offset), type_size, tmp);
196 }
197 return Address();
198 }
199
200 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
201 ShouldNotReachHere();
202 return Address();
203 }
204
205 Address LIR_Assembler::as_Address(LIR_Address* addr) {
206 return as_Address(addr, rscratch1);
207 }
208
209 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
210 return as_Address(addr, rscratch1); // Ouch
211 // FIXME: This needs to be much more clever. See x86.
212 }
213
214 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
215 // not encodable as a base + (immediate) offset, generate an explicit address
216 // calculation to hold the address in a temporary register.
217 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
218 precond(size == 4 || size == 8);
219 Address addr = frame_map()->address_for_slot(index, adjust);
220 precond(addr.getMode() == Address::base_plus_offset);
221 precond(addr.base() == sp);
222 precond(addr.offset() > 0);
223 uint mask = size - 1;
224 assert((addr.offset() & mask) == 0, "scaled offsets only");
225 return __ legitimize_address(addr, size, tmp);
226 }
227
228 void LIR_Assembler::osr_entry() {
229 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
230 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
231 ValueStack* entry_state = osr_entry->state();
232 int number_of_locks = entry_state->locks_size();
233
234 // we jump here if osr happens with the interpreter
235 // state set up to continue at the beginning of the
236 // loop that triggered osr - in particular, we have
237 // the following registers setup:
238 //
239 // r2: osr buffer
240 //
241
242 // build frame
243 ciMethod* m = compilation()->method();
244 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
245
246 // OSR buffer is
247 //
248 // locals[nlocals-1..0]
249 // monitors[0..number_of_locks]
250 //
251 // locals is a direct copy of the interpreter frame so in the osr buffer
252 // so first slot in the local array is the last local from the interpreter
253 // and last slot is local[0] (receiver) from the interpreter
254 //
255 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
256 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
257 // in the interpreter frame (the method lock if a sync method)
258
259 // Initialize monitors in the compiled activation.
260 // r2: pointer to osr buffer
261 //
262 // All other registers are dead at this point and the locals will be
263 // copied into place by code emitted in the IR.
264
265 Register OSR_buf = osrBufferPointer()->as_pointer_register();
266 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
267 int monitor_offset = BytesPerWord * method()->max_locals() +
268 (2 * BytesPerWord) * (number_of_locks - 1);
269 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
270 // the OSR buffer using 2 word entries: first the lock and then
271 // the oop.
272 for (int i = 0; i < number_of_locks; i++) {
273 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
274 #ifdef ASSERT
275 // verify the interpreter's monitor has a non-null object
276 {
277 Label L;
278 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
279 __ cbnz(rscratch1, L);
280 __ stop("locked object is null");
281 __ bind(L);
282 }
283 #endif
284 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
285 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
286 __ str(r19, frame_map()->address_for_monitor_lock(i));
287 __ str(r20, frame_map()->address_for_monitor_object(i));
288 }
289 }
290 }
291
292
293 // inline cache check; done before the frame is built.
294 int LIR_Assembler::check_icache() {
295 return __ ic_check(CodeEntryAlignment);
296 }
297
298 void LIR_Assembler::clinit_barrier(ciMethod* method) {
299 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
300 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
301
302 Label L_skip_barrier;
303
304 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
305 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
306 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
307 __ bind(L_skip_barrier);
308 }
309
310 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
311 if (o == nullptr) {
312 __ mov(reg, zr);
313 } else {
314 __ movoop(reg, o);
315 }
316 }
317
318 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
319 address target = nullptr;
320 relocInfo::relocType reloc_type = relocInfo::none;
321
322 switch (patching_id(info)) {
323 case PatchingStub::access_field_id:
324 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
325 reloc_type = relocInfo::section_word_type;
326 break;
327 case PatchingStub::load_klass_id:
328 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
329 reloc_type = relocInfo::metadata_type;
330 break;
331 case PatchingStub::load_mirror_id:
332 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
333 reloc_type = relocInfo::oop_type;
334 break;
335 case PatchingStub::load_appendix_id:
336 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
337 reloc_type = relocInfo::oop_type;
338 break;
339 default: ShouldNotReachHere();
340 }
341
342 __ far_call(RuntimeAddress(target));
343 add_call_info_here(info);
344 }
345
346 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
347 deoptimize_trap(info);
348 }
349
350
351 // This specifies the rsp decrement needed to build the frame
352 int LIR_Assembler::initial_frame_size_in_bytes() const {
353 // if rounding, must let FrameMap know!
354
355 return in_bytes(frame_map()->framesize_in_bytes());
356 }
357
358
359 int LIR_Assembler::emit_exception_handler() {
360 // generate code for exception handler
361 address handler_base = __ start_a_stub(exception_handler_size());
362 if (handler_base == nullptr) {
363 // not enough space left for the handler
364 bailout("exception handler overflow");
365 return -1;
366 }
367
368 int offset = code_offset();
369
370 // the exception oop and pc are in r0, and r3
371 // no other registers need to be preserved, so invalidate them
372 __ invalidate_registers(false, true, true, false, true, true);
373
374 // check that there is really an exception
375 __ verify_not_null_oop(r0);
376
377 // search an exception handler (r0: exception oop, r3: throwing pc)
378 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
379 __ should_not_reach_here();
380 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
381 __ end_a_stub();
382
383 return offset;
384 }
385
386
387 // Emit the code to remove the frame from the stack in the exception
388 // unwind path.
389 int LIR_Assembler::emit_unwind_handler() {
390 #ifndef PRODUCT
391 if (CommentedAssembly) {
392 _masm->block_comment("Unwind handler");
393 }
394 #endif
395
396 int offset = code_offset();
397
398 // Fetch the exception from TLS and clear out exception related thread state
399 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
400 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
401 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
402
403 __ bind(_unwind_handler_entry);
404 __ verify_not_null_oop(r0);
405 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
406 __ mov(r19, r0); // Preserve the exception
407 }
408
409 // Perform needed unlocking
410 MonitorExitStub* stub = nullptr;
411 if (method()->is_synchronized()) {
412 monitor_address(0, FrameMap::r0_opr);
413 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
414 if (LockingMode == LM_MONITOR) {
415 __ b(*stub->entry());
416 } else {
417 __ unlock_object(r5, r4, r0, r6, *stub->entry());
418 }
419 __ bind(*stub->continuation());
420 }
421
422 if (compilation()->env()->dtrace_method_probes()) {
423 __ mov(c_rarg0, rthread);
424 __ mov_metadata(c_rarg1, method()->constant_encoding());
425 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
426 }
427
428 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
429 __ mov(r0, r19); // Restore the exception
430 }
431
432 // remove the activation and dispatch to the unwind handler
433 __ block_comment("remove_frame and dispatch to the unwind handler");
434 __ remove_frame(initial_frame_size_in_bytes());
435 __ far_jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
436
437 // Emit the slow path assembly
438 if (stub != nullptr) {
439 stub->emit_code(this);
440 }
441
442 return offset;
443 }
444
445
446 int LIR_Assembler::emit_deopt_handler() {
447 // generate code for exception handler
448 address handler_base = __ start_a_stub(deopt_handler_size());
449 if (handler_base == nullptr) {
450 // not enough space left for the handler
451 bailout("deopt handler overflow");
452 return -1;
453 }
454
455 int offset = code_offset();
456
457 __ adr(lr, pc());
458 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
459 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
460 __ end_a_stub();
461
462 return offset;
463 }
464
465 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
466 _masm->code_section()->relocate(adr, relocInfo::poll_type);
467 int pc_offset = code_offset();
468 flush_debug_info(pc_offset);
469 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
470 if (info->exception_handlers() != nullptr) {
471 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
472 }
473 }
474
475 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
476 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
477
478 // Pop the stack before the safepoint code
479 __ remove_frame(initial_frame_size_in_bytes());
480
481 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
482 __ reserved_stack_check();
483 }
484
485 code_stub->set_safepoint_offset(__ offset());
486 __ relocate(relocInfo::poll_return_type);
487 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
488 __ ret(lr);
489 }
490
491 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
492 guarantee(info != nullptr, "Shouldn't be null");
493 __ get_polling_page(rscratch1, relocInfo::poll_type);
494 add_debug_info_for_branch(info); // This isn't just debug info:
495 // it's the oop map
496 __ read_polling_page(rscratch1, relocInfo::poll_type);
497 return __ offset();
498 }
499
500
501 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
502 if (from_reg == r31_sp)
503 from_reg = sp;
504 if (to_reg == r31_sp)
505 to_reg = sp;
506 __ mov(to_reg, from_reg);
507 }
508
509 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
510
511
512 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
513 assert(src->is_constant(), "should not call otherwise");
514 assert(dest->is_register(), "should not call otherwise");
515 LIR_Const* c = src->as_constant_ptr();
516
517 switch (c->type()) {
518 case T_INT: {
519 assert(patch_code == lir_patch_none, "no patching handled here");
520 __ movw(dest->as_register(), c->as_jint());
521 break;
522 }
523
524 case T_ADDRESS: {
525 assert(patch_code == lir_patch_none, "no patching handled here");
526 __ mov(dest->as_register(), c->as_jint());
527 break;
528 }
529
530 case T_LONG: {
531 assert(patch_code == lir_patch_none, "no patching handled here");
532 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
533 break;
534 }
535
536 case T_OBJECT: {
537 if (patch_code == lir_patch_none) {
538 jobject2reg(c->as_jobject(), dest->as_register());
539 } else {
540 jobject2reg_with_patching(dest->as_register(), info);
541 }
542 break;
543 }
544
545 case T_METADATA: {
546 if (patch_code != lir_patch_none) {
547 klass2reg_with_patching(dest->as_register(), info);
548 } else {
549 __ mov_metadata(dest->as_register(), c->as_metadata());
550 }
551 break;
552 }
553
554 case T_FLOAT: {
555 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
556 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
557 } else {
558 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
559 __ ldrs(dest->as_float_reg(), Address(rscratch1));
560 }
561 break;
562 }
563
564 case T_DOUBLE: {
565 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
566 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
567 } else {
568 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
569 __ ldrd(dest->as_double_reg(), Address(rscratch1));
570 }
571 break;
572 }
573
574 default:
575 ShouldNotReachHere();
576 }
577 }
578
579 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
580 LIR_Const* c = src->as_constant_ptr();
581 switch (c->type()) {
582 case T_OBJECT:
583 {
584 if (! c->as_jobject())
585 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
586 else {
587 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
588 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
589 }
590 }
591 break;
592 case T_ADDRESS:
593 {
594 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
595 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
596 }
597 case T_INT:
598 case T_FLOAT:
599 {
600 Register reg = zr;
601 if (c->as_jint_bits() == 0)
602 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
603 else {
604 __ movw(rscratch1, c->as_jint_bits());
605 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
606 }
607 }
608 break;
609 case T_LONG:
610 case T_DOUBLE:
611 {
612 Register reg = zr;
613 if (c->as_jlong_bits() == 0)
614 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
615 lo_word_offset_in_bytes));
616 else {
617 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
618 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
619 lo_word_offset_in_bytes));
620 }
621 }
622 break;
623 default:
624 ShouldNotReachHere();
625 }
626 }
627
628 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
629 assert(src->is_constant(), "should not call otherwise");
630 LIR_Const* c = src->as_constant_ptr();
631 LIR_Address* to_addr = dest->as_address_ptr();
632
633 void (Assembler::* insn)(Register Rt, const Address &adr);
634
635 switch (type) {
636 case T_ADDRESS:
637 assert(c->as_jint() == 0, "should be");
638 insn = &Assembler::str;
639 break;
640 case T_LONG:
641 assert(c->as_jlong() == 0, "should be");
642 insn = &Assembler::str;
643 break;
644 case T_INT:
645 assert(c->as_jint() == 0, "should be");
646 insn = &Assembler::strw;
647 break;
648 case T_OBJECT:
649 case T_ARRAY:
650 assert(c->as_jobject() == nullptr, "should be");
651 if (UseCompressedOops && !wide) {
652 insn = &Assembler::strw;
653 } else {
654 insn = &Assembler::str;
655 }
656 break;
657 case T_CHAR:
658 case T_SHORT:
659 assert(c->as_jint() == 0, "should be");
660 insn = &Assembler::strh;
661 break;
662 case T_BOOLEAN:
663 case T_BYTE:
664 assert(c->as_jint() == 0, "should be");
665 insn = &Assembler::strb;
666 break;
667 default:
668 ShouldNotReachHere();
669 insn = &Assembler::str; // unreachable
670 }
671
672 if (info) add_debug_info_for_null_check_here(info);
673 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
674 }
675
676 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
677 assert(src->is_register(), "should not call otherwise");
678 assert(dest->is_register(), "should not call otherwise");
679
680 // move between cpu-registers
681 if (dest->is_single_cpu()) {
682 if (src->type() == T_LONG) {
683 // Can do LONG -> OBJECT
684 move_regs(src->as_register_lo(), dest->as_register());
685 return;
686 }
687 assert(src->is_single_cpu(), "must match");
688 if (src->type() == T_OBJECT) {
689 __ verify_oop(src->as_register());
690 }
691 move_regs(src->as_register(), dest->as_register());
692
693 } else if (dest->is_double_cpu()) {
694 if (is_reference_type(src->type())) {
695 // Surprising to me but we can see move of a long to t_object
696 __ verify_oop(src->as_register());
697 move_regs(src->as_register(), dest->as_register_lo());
698 return;
699 }
700 assert(src->is_double_cpu(), "must match");
701 Register f_lo = src->as_register_lo();
702 Register f_hi = src->as_register_hi();
703 Register t_lo = dest->as_register_lo();
704 Register t_hi = dest->as_register_hi();
705 assert(f_hi == f_lo, "must be same");
706 assert(t_hi == t_lo, "must be same");
707 move_regs(f_lo, t_lo);
708
709 } else if (dest->is_single_fpu()) {
710 __ fmovs(dest->as_float_reg(), src->as_float_reg());
711
712 } else if (dest->is_double_fpu()) {
713 __ fmovd(dest->as_double_reg(), src->as_double_reg());
714
715 } else {
716 ShouldNotReachHere();
717 }
718 }
719
720 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
721 precond(src->is_register() && dest->is_stack());
722
723 uint const c_sz32 = sizeof(uint32_t);
724 uint const c_sz64 = sizeof(uint64_t);
725
726 if (src->is_single_cpu()) {
727 int index = dest->single_stack_ix();
728 if (is_reference_type(type)) {
729 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
730 __ verify_oop(src->as_register());
731 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
732 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
733 } else {
734 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
735 }
736
737 } else if (src->is_double_cpu()) {
738 int index = dest->double_stack_ix();
739 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
740 __ str(src->as_register_lo(), dest_addr_LO);
741
742 } else if (src->is_single_fpu()) {
743 int index = dest->single_stack_ix();
744 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
745
746 } else if (src->is_double_fpu()) {
747 int index = dest->double_stack_ix();
748 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
749
750 } else {
751 ShouldNotReachHere();
752 }
753 }
754
755
756 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
757 LIR_Address* to_addr = dest->as_address_ptr();
758 PatchingStub* patch = nullptr;
759 Register compressed_src = rscratch1;
760
761 if (patch_code != lir_patch_none) {
762 deoptimize_trap(info);
763 return;
764 }
765
766 if (is_reference_type(type)) {
767 __ verify_oop(src->as_register());
768
769 if (UseCompressedOops && !wide) {
770 __ encode_heap_oop(compressed_src, src->as_register());
771 } else {
772 compressed_src = src->as_register();
773 }
774 }
775
776 int null_check_here = code_offset();
777 switch (type) {
778 case T_FLOAT: {
779 __ strs(src->as_float_reg(), as_Address(to_addr));
780 break;
781 }
782
783 case T_DOUBLE: {
784 __ strd(src->as_double_reg(), as_Address(to_addr));
785 break;
786 }
787
788 case T_ARRAY: // fall through
789 case T_OBJECT: // fall through
790 if (UseCompressedOops && !wide) {
791 __ strw(compressed_src, as_Address(to_addr, rscratch2));
792 } else {
793 __ str(compressed_src, as_Address(to_addr));
794 }
795 break;
796 case T_METADATA:
797 // We get here to store a method pointer to the stack to pass to
798 // a dtrace runtime call. This can't work on 64 bit with
799 // compressed klass ptrs: T_METADATA can be a compressed klass
800 // ptr or a 64 bit method pointer.
801 ShouldNotReachHere();
802 __ str(src->as_register(), as_Address(to_addr));
803 break;
804 case T_ADDRESS:
805 __ str(src->as_register(), as_Address(to_addr));
806 break;
807 case T_INT:
808 __ strw(src->as_register(), as_Address(to_addr));
809 break;
810
811 case T_LONG: {
812 __ str(src->as_register_lo(), as_Address_lo(to_addr));
813 break;
814 }
815
816 case T_BYTE: // fall through
817 case T_BOOLEAN: {
818 __ strb(src->as_register(), as_Address(to_addr));
819 break;
820 }
821
822 case T_CHAR: // fall through
823 case T_SHORT:
824 __ strh(src->as_register(), as_Address(to_addr));
825 break;
826
827 default:
828 ShouldNotReachHere();
829 }
830 if (info != nullptr) {
831 add_debug_info_for_null_check(null_check_here, info);
832 }
833 }
834
835
836 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
837 precond(src->is_stack() && dest->is_register());
838
839 uint const c_sz32 = sizeof(uint32_t);
840 uint const c_sz64 = sizeof(uint64_t);
841
842 if (dest->is_single_cpu()) {
843 int index = src->single_stack_ix();
844 if (is_reference_type(type)) {
845 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
846 __ verify_oop(dest->as_register());
847 } else if (type == T_METADATA || type == T_ADDRESS) {
848 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
849 } else {
850 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
851 }
852
853 } else if (dest->is_double_cpu()) {
854 int index = src->double_stack_ix();
855 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
856 __ ldr(dest->as_register_lo(), src_addr_LO);
857
858 } else if (dest->is_single_fpu()) {
859 int index = src->single_stack_ix();
860 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
861
862 } else if (dest->is_double_fpu()) {
863 int index = src->double_stack_ix();
864 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
865
866 } else {
867 ShouldNotReachHere();
868 }
869 }
870
871
872 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
873 address target = nullptr;
874 relocInfo::relocType reloc_type = relocInfo::none;
875
876 switch (patching_id(info)) {
877 case PatchingStub::access_field_id:
878 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
879 reloc_type = relocInfo::section_word_type;
880 break;
881 case PatchingStub::load_klass_id:
882 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
883 reloc_type = relocInfo::metadata_type;
884 break;
885 case PatchingStub::load_mirror_id:
886 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
887 reloc_type = relocInfo::oop_type;
888 break;
889 case PatchingStub::load_appendix_id:
890 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
891 reloc_type = relocInfo::oop_type;
892 break;
893 default: ShouldNotReachHere();
894 }
895
896 __ far_call(RuntimeAddress(target));
897 add_call_info_here(info);
898 }
899
900 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
901
902 LIR_Opr temp;
903 if (type == T_LONG || type == T_DOUBLE)
904 temp = FrameMap::rscratch1_long_opr;
905 else
906 temp = FrameMap::rscratch1_opr;
907
908 stack2reg(src, temp, src->type());
909 reg2stack(temp, dest, dest->type(), false);
910 }
911
912
913 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
914 LIR_Address* addr = src->as_address_ptr();
915 LIR_Address* from_addr = src->as_address_ptr();
916
917 if (addr->base()->type() == T_OBJECT) {
918 __ verify_oop(addr->base()->as_pointer_register());
919 }
920
921 if (patch_code != lir_patch_none) {
922 deoptimize_trap(info);
923 return;
924 }
925
926 if (info != nullptr) {
927 add_debug_info_for_null_check_here(info);
928 }
929 int null_check_here = code_offset();
930 switch (type) {
931 case T_FLOAT: {
932 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
933 break;
934 }
935
936 case T_DOUBLE: {
937 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
938 break;
939 }
940
941 case T_ARRAY: // fall through
942 case T_OBJECT: // fall through
943 if (UseCompressedOops && !wide) {
944 __ ldrw(dest->as_register(), as_Address(from_addr));
945 } else {
946 __ ldr(dest->as_register(), as_Address(from_addr));
947 }
948 break;
949 case T_METADATA:
950 // We get here to store a method pointer to the stack to pass to
951 // a dtrace runtime call. This can't work on 64 bit with
952 // compressed klass ptrs: T_METADATA can be a compressed klass
953 // ptr or a 64 bit method pointer.
954 ShouldNotReachHere();
955 __ ldr(dest->as_register(), as_Address(from_addr));
956 break;
957 case T_ADDRESS:
958 __ ldr(dest->as_register(), as_Address(from_addr));
959 break;
960 case T_INT:
961 __ ldrw(dest->as_register(), as_Address(from_addr));
962 break;
963
964 case T_LONG: {
965 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
966 break;
967 }
968
969 case T_BYTE:
970 __ ldrsb(dest->as_register(), as_Address(from_addr));
971 break;
972 case T_BOOLEAN: {
973 __ ldrb(dest->as_register(), as_Address(from_addr));
974 break;
975 }
976
977 case T_CHAR:
978 __ ldrh(dest->as_register(), as_Address(from_addr));
979 break;
980 case T_SHORT:
981 __ ldrsh(dest->as_register(), as_Address(from_addr));
982 break;
983
984 default:
985 ShouldNotReachHere();
986 }
987
988 if (is_reference_type(type)) {
989 if (UseCompressedOops && !wide) {
990 __ decode_heap_oop(dest->as_register());
991 }
992
993 __ verify_oop(dest->as_register());
994 }
995 }
996
997
998 int LIR_Assembler::array_element_size(BasicType type) const {
999 int elem_size = type2aelembytes(type);
1000 return exact_log2(elem_size);
1001 }
1002
1003
1004 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1005 switch (op->code()) {
1006 case lir_idiv:
1007 case lir_irem:
1008 arithmetic_idiv(op->code(),
1009 op->in_opr1(),
1010 op->in_opr2(),
1011 op->in_opr3(),
1012 op->result_opr(),
1013 op->info());
1014 break;
1015 case lir_fmad:
1016 __ fmaddd(op->result_opr()->as_double_reg(),
1017 op->in_opr1()->as_double_reg(),
1018 op->in_opr2()->as_double_reg(),
1019 op->in_opr3()->as_double_reg());
1020 break;
1021 case lir_fmaf:
1022 __ fmadds(op->result_opr()->as_float_reg(),
1023 op->in_opr1()->as_float_reg(),
1024 op->in_opr2()->as_float_reg(),
1025 op->in_opr3()->as_float_reg());
1026 break;
1027 default: ShouldNotReachHere(); break;
1028 }
1029 }
1030
1031 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1032 #ifdef ASSERT
1033 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1034 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1035 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1036 #endif
1037
1038 if (op->cond() == lir_cond_always) {
1039 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1040 __ b(*(op->label()));
1041 } else {
1042 Assembler::Condition acond;
1043 if (op->code() == lir_cond_float_branch) {
1044 bool is_unordered = (op->ublock() == op->block());
1045 // Assembler::EQ does not permit unordered branches, so we add
1046 // another branch here. Likewise, Assembler::NE does not permit
1047 // ordered branches.
1048 if ((is_unordered && op->cond() == lir_cond_equal)
1049 || (!is_unordered && op->cond() == lir_cond_notEqual))
1050 __ br(Assembler::VS, *(op->ublock()->label()));
1051 switch(op->cond()) {
1052 case lir_cond_equal: acond = Assembler::EQ; break;
1053 case lir_cond_notEqual: acond = Assembler::NE; break;
1054 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1055 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1056 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1057 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1058 default: ShouldNotReachHere();
1059 acond = Assembler::EQ; // unreachable
1060 }
1061 } else {
1062 switch (op->cond()) {
1063 case lir_cond_equal: acond = Assembler::EQ; break;
1064 case lir_cond_notEqual: acond = Assembler::NE; break;
1065 case lir_cond_less: acond = Assembler::LT; break;
1066 case lir_cond_lessEqual: acond = Assembler::LE; break;
1067 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1068 case lir_cond_greater: acond = Assembler::GT; break;
1069 case lir_cond_belowEqual: acond = Assembler::LS; break;
1070 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1071 default: ShouldNotReachHere();
1072 acond = Assembler::EQ; // unreachable
1073 }
1074 }
1075 __ br(acond,*(op->label()));
1076 }
1077 }
1078
1079
1080
1081 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1082 LIR_Opr src = op->in_opr();
1083 LIR_Opr dest = op->result_opr();
1084
1085 switch (op->bytecode()) {
1086 case Bytecodes::_i2f:
1087 {
1088 __ scvtfws(dest->as_float_reg(), src->as_register());
1089 break;
1090 }
1091 case Bytecodes::_i2d:
1092 {
1093 __ scvtfwd(dest->as_double_reg(), src->as_register());
1094 break;
1095 }
1096 case Bytecodes::_l2d:
1097 {
1098 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1099 break;
1100 }
1101 case Bytecodes::_l2f:
1102 {
1103 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1104 break;
1105 }
1106 case Bytecodes::_f2d:
1107 {
1108 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1109 break;
1110 }
1111 case Bytecodes::_d2f:
1112 {
1113 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1114 break;
1115 }
1116 case Bytecodes::_i2c:
1117 {
1118 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1119 break;
1120 }
1121 case Bytecodes::_i2l:
1122 {
1123 __ sxtw(dest->as_register_lo(), src->as_register());
1124 break;
1125 }
1126 case Bytecodes::_i2s:
1127 {
1128 __ sxth(dest->as_register(), src->as_register());
1129 break;
1130 }
1131 case Bytecodes::_i2b:
1132 {
1133 __ sxtb(dest->as_register(), src->as_register());
1134 break;
1135 }
1136 case Bytecodes::_l2i:
1137 {
1138 _masm->block_comment("FIXME: This could be a no-op");
1139 __ uxtw(dest->as_register(), src->as_register_lo());
1140 break;
1141 }
1142 case Bytecodes::_d2l:
1143 {
1144 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1145 break;
1146 }
1147 case Bytecodes::_f2i:
1148 {
1149 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1150 break;
1151 }
1152 case Bytecodes::_f2l:
1153 {
1154 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1155 break;
1156 }
1157 case Bytecodes::_d2i:
1158 {
1159 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1160 break;
1161 }
1162 default: ShouldNotReachHere();
1163 }
1164 }
1165
1166 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1167 if (op->init_check()) {
1168 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1169 __ ldarb(rscratch1, rscratch1);
1170 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1171 add_debug_info_for_null_check_here(op->stub()->info());
1172 __ br(Assembler::NE, *op->stub()->entry());
1173 }
1174 __ allocate_object(op->obj()->as_register(),
1175 op->tmp1()->as_register(),
1176 op->tmp2()->as_register(),
1177 op->header_size(),
1178 op->object_size(),
1179 op->klass()->as_register(),
1180 *op->stub()->entry());
1181 __ bind(*op->stub()->continuation());
1182 }
1183
1184 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1185 Register len = op->len()->as_register();
1186 __ uxtw(len, len);
1187
1188 if (UseSlowPath ||
1189 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1190 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1191 __ b(*op->stub()->entry());
1192 } else {
1193 Register tmp1 = op->tmp1()->as_register();
1194 Register tmp2 = op->tmp2()->as_register();
1195 Register tmp3 = op->tmp3()->as_register();
1196 if (len == tmp1) {
1197 tmp1 = tmp3;
1198 } else if (len == tmp2) {
1199 tmp2 = tmp3;
1200 } else if (len == tmp3) {
1201 // everything is ok
1202 } else {
1203 __ mov(tmp3, len);
1204 }
1205 __ allocate_array(op->obj()->as_register(),
1206 len,
1207 tmp1,
1208 tmp2,
1209 arrayOopDesc::base_offset_in_bytes(op->type()),
1210 array_element_size(op->type()),
1211 op->klass()->as_register(),
1212 *op->stub()->entry(),
1213 op->zero_array());
1214 }
1215 __ bind(*op->stub()->continuation());
1216 }
1217
1218 void LIR_Assembler::type_profile_helper(Register mdo,
1219 ciMethodData *md, ciProfileData *data,
1220 Register recv, Label* update_done) {
1221 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1222 Label next_test;
1223 // See if the receiver is receiver[n].
1224 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1225 __ ldr(rscratch1, Address(rscratch2));
1226 __ cmp(recv, rscratch1);
1227 __ br(Assembler::NE, next_test);
1228 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1229 __ addptr(data_addr, DataLayout::counter_increment);
1230 __ b(*update_done);
1231 __ bind(next_test);
1232 }
1233
1234 // Didn't find receiver; find next empty slot and fill it in
1235 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1236 Label next_test;
1237 __ lea(rscratch2,
1238 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1239 Address recv_addr(rscratch2);
1240 __ ldr(rscratch1, recv_addr);
1241 __ cbnz(rscratch1, next_test);
1242 __ str(recv, recv_addr);
1243 __ mov(rscratch1, DataLayout::counter_increment);
1244 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1245 __ str(rscratch1, Address(rscratch2));
1246 __ b(*update_done);
1247 __ bind(next_test);
1248 }
1249 }
1250
1251 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1252 // we always need a stub for the failure case.
1253 CodeStub* stub = op->stub();
1254 Register obj = op->object()->as_register();
1255 Register k_RInfo = op->tmp1()->as_register();
1256 Register klass_RInfo = op->tmp2()->as_register();
1257 Register dst = op->result_opr()->as_register();
1258 ciKlass* k = op->klass();
1259 Register Rtmp1 = noreg;
1260
1261 // check if it needs to be profiled
1262 ciMethodData* md;
1263 ciProfileData* data;
1264
1265 const bool should_profile = op->should_profile();
1266
1267 if (should_profile) {
1268 ciMethod* method = op->profiled_method();
1269 assert(method != nullptr, "Should have method");
1270 int bci = op->profiled_bci();
1271 md = method->method_data_or_null();
1272 assert(md != nullptr, "Sanity");
1273 data = md->bci_to_data(bci);
1274 assert(data != nullptr, "need data for type check");
1275 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1276 }
1277 Label* success_target = success;
1278 Label* failure_target = failure;
1279
1280 if (obj == k_RInfo) {
1281 k_RInfo = dst;
1282 } else if (obj == klass_RInfo) {
1283 klass_RInfo = dst;
1284 }
1285 if (k->is_loaded() && !UseCompressedClassPointers) {
1286 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1287 } else {
1288 Rtmp1 = op->tmp3()->as_register();
1289 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1290 }
1291
1292 assert_different_registers(obj, k_RInfo, klass_RInfo);
1293
1294 if (should_profile) {
1295 Register mdo = klass_RInfo;
1296 __ mov_metadata(mdo, md->constant_encoding());
1297 Label not_null;
1298 __ cbnz(obj, not_null);
1299 // Object is null; update MDO and exit
1300 Address data_addr
1301 = __ form_address(rscratch2, mdo,
1302 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1303 0);
1304 __ ldrb(rscratch1, data_addr);
1305 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1306 __ strb(rscratch1, data_addr);
1307 __ b(*obj_is_null);
1308 __ bind(not_null);
1309
1310 Label update_done;
1311 Register recv = k_RInfo;
1312 __ load_klass(recv, obj);
1313 type_profile_helper(mdo, md, data, recv, &update_done);
1314 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1315 __ addptr(counter_addr, DataLayout::counter_increment);
1316
1317 __ bind(update_done);
1318 } else {
1319 __ cbz(obj, *obj_is_null);
1320 }
1321
1322 if (!k->is_loaded()) {
1323 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1324 } else {
1325 __ mov_metadata(k_RInfo, k->constant_encoding());
1326 }
1327 __ verify_oop(obj);
1328
1329 if (op->fast_check()) {
1330 // get object class
1331 // not a safepoint as obj null check happens earlier
1332 __ load_klass(rscratch1, obj);
1333 __ cmp( rscratch1, k_RInfo);
1334
1335 __ br(Assembler::NE, *failure_target);
1336 // successful cast, fall through to profile or jump
1337 } else {
1338 // get object class
1339 // not a safepoint as obj null check happens earlier
1340 __ load_klass(klass_RInfo, obj);
1341 if (k->is_loaded()) {
1342 // See if we get an immediate positive hit
1343 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1344 __ cmp(k_RInfo, rscratch1);
1345 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1346 __ br(Assembler::NE, *failure_target);
1347 // successful cast, fall through to profile or jump
1348 } else {
1349 // See if we get an immediate positive hit
1350 __ br(Assembler::EQ, *success_target);
1351 // check for self
1352 __ cmp(klass_RInfo, k_RInfo);
1353 __ br(Assembler::EQ, *success_target);
1354
1355 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1356 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1357 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1358 // result is a boolean
1359 __ cbzw(klass_RInfo, *failure_target);
1360 // successful cast, fall through to profile or jump
1361 }
1362 } else {
1363 // perform the fast part of the checking logic
1364 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1365 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1366 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1367 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1368 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1369 // result is a boolean
1370 __ cbz(k_RInfo, *failure_target);
1371 // successful cast, fall through to profile or jump
1372 }
1373 }
1374 __ b(*success);
1375 }
1376
1377
1378 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1379 const bool should_profile = op->should_profile();
1380
1381 LIR_Code code = op->code();
1382 if (code == lir_store_check) {
1383 Register value = op->object()->as_register();
1384 Register array = op->array()->as_register();
1385 Register k_RInfo = op->tmp1()->as_register();
1386 Register klass_RInfo = op->tmp2()->as_register();
1387 Register Rtmp1 = op->tmp3()->as_register();
1388
1389 CodeStub* stub = op->stub();
1390
1391 // check if it needs to be profiled
1392 ciMethodData* md;
1393 ciProfileData* data;
1394
1395 if (should_profile) {
1396 ciMethod* method = op->profiled_method();
1397 assert(method != nullptr, "Should have method");
1398 int bci = op->profiled_bci();
1399 md = method->method_data_or_null();
1400 assert(md != nullptr, "Sanity");
1401 data = md->bci_to_data(bci);
1402 assert(data != nullptr, "need data for type check");
1403 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1404 }
1405 Label done;
1406 Label* success_target = &done;
1407 Label* failure_target = stub->entry();
1408
1409 if (should_profile) {
1410 Label not_null;
1411 Register mdo = klass_RInfo;
1412 __ mov_metadata(mdo, md->constant_encoding());
1413 __ cbnz(value, not_null);
1414 // Object is null; update MDO and exit
1415 Address data_addr
1416 = __ form_address(rscratch2, mdo,
1417 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1418 0);
1419 __ ldrb(rscratch1, data_addr);
1420 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1421 __ strb(rscratch1, data_addr);
1422 __ b(done);
1423 __ bind(not_null);
1424
1425 Label update_done;
1426 Register recv = k_RInfo;
1427 __ load_klass(recv, value);
1428 type_profile_helper(mdo, md, data, recv, &update_done);
1429 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1430 __ addptr(counter_addr, DataLayout::counter_increment);
1431 __ bind(update_done);
1432 } else {
1433 __ cbz(value, done);
1434 }
1435
1436 add_debug_info_for_null_check_here(op->info_for_exception());
1437 __ load_klass(k_RInfo, array);
1438 __ load_klass(klass_RInfo, value);
1439
1440 // get instance klass (it's already uncompressed)
1441 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1442 // perform the fast part of the checking logic
1443 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1444 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1445 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1446 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1447 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1448 // result is a boolean
1449 __ cbzw(k_RInfo, *failure_target);
1450 // fall through to the success case
1451
1452 __ bind(done);
1453 } else if (code == lir_checkcast) {
1454 Register obj = op->object()->as_register();
1455 Register dst = op->result_opr()->as_register();
1456 Label success;
1457 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1458 __ bind(success);
1459 if (dst != obj) {
1460 __ mov(dst, obj);
1461 }
1462 } else if (code == lir_instanceof) {
1463 Register obj = op->object()->as_register();
1464 Register dst = op->result_opr()->as_register();
1465 Label success, failure, done;
1466 emit_typecheck_helper(op, &success, &failure, &failure);
1467 __ bind(failure);
1468 __ mov(dst, zr);
1469 __ b(done);
1470 __ bind(success);
1471 __ mov(dst, 1);
1472 __ bind(done);
1473 } else {
1474 ShouldNotReachHere();
1475 }
1476 }
1477
1478 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1479 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1480 __ cset(rscratch1, Assembler::NE);
1481 __ membar(__ AnyAny);
1482 }
1483
1484 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1485 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1486 __ cset(rscratch1, Assembler::NE);
1487 __ membar(__ AnyAny);
1488 }
1489
1490
1491 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1492 Register addr;
1493 if (op->addr()->is_register()) {
1494 addr = as_reg(op->addr());
1495 } else {
1496 assert(op->addr()->is_address(), "what else?");
1497 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1498 assert(addr_ptr->disp() == 0, "need 0 disp");
1499 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1500 addr = as_reg(addr_ptr->base());
1501 }
1502 Register newval = as_reg(op->new_value());
1503 Register cmpval = as_reg(op->cmp_value());
1504
1505 if (op->code() == lir_cas_obj) {
1506 if (UseCompressedOops) {
1507 Register t1 = op->tmp1()->as_register();
1508 assert(op->tmp1()->is_valid(), "must be");
1509 __ encode_heap_oop(t1, cmpval);
1510 cmpval = t1;
1511 __ encode_heap_oop(rscratch2, newval);
1512 newval = rscratch2;
1513 casw(addr, newval, cmpval);
1514 } else {
1515 casl(addr, newval, cmpval);
1516 }
1517 } else if (op->code() == lir_cas_int) {
1518 casw(addr, newval, cmpval);
1519 } else {
1520 casl(addr, newval, cmpval);
1521 }
1522 }
1523
1524
1525 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1526 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1527 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1528
1529 Assembler::Condition acond, ncond;
1530 switch (condition) {
1531 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1532 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1533 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1534 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1535 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1536 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1537 case lir_cond_belowEqual:
1538 case lir_cond_aboveEqual:
1539 default: ShouldNotReachHere();
1540 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1541 }
1542
1543 assert(result->is_single_cpu() || result->is_double_cpu(),
1544 "expect single register for result");
1545 if (opr1->is_constant() && opr2->is_constant()
1546 && opr1->type() == T_INT && opr2->type() == T_INT) {
1547 jint val1 = opr1->as_jint();
1548 jint val2 = opr2->as_jint();
1549 if (val1 == 0 && val2 == 1) {
1550 __ cset(result->as_register(), ncond);
1551 return;
1552 } else if (val1 == 1 && val2 == 0) {
1553 __ cset(result->as_register(), acond);
1554 return;
1555 }
1556 }
1557
1558 if (opr1->is_constant() && opr2->is_constant()
1559 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1560 jlong val1 = opr1->as_jlong();
1561 jlong val2 = opr2->as_jlong();
1562 if (val1 == 0 && val2 == 1) {
1563 __ cset(result->as_register_lo(), ncond);
1564 return;
1565 } else if (val1 == 1 && val2 == 0) {
1566 __ cset(result->as_register_lo(), acond);
1567 return;
1568 }
1569 }
1570
1571 if (opr1->is_stack()) {
1572 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1573 opr1 = FrameMap::rscratch1_opr;
1574 } else if (opr1->is_constant()) {
1575 LIR_Opr tmp
1576 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1577 const2reg(opr1, tmp, lir_patch_none, nullptr);
1578 opr1 = tmp;
1579 }
1580
1581 if (opr2->is_stack()) {
1582 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1583 opr2 = FrameMap::rscratch2_opr;
1584 } else if (opr2->is_constant()) {
1585 LIR_Opr tmp
1586 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1587 const2reg(opr2, tmp, lir_patch_none, nullptr);
1588 opr2 = tmp;
1589 }
1590
1591 if (result->type() == T_LONG)
1592 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1593 else
1594 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1595 }
1596
1597 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1598 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1599
1600 if (left->is_single_cpu()) {
1601 Register lreg = left->as_register();
1602 Register dreg = as_reg(dest);
1603
1604 if (right->is_single_cpu()) {
1605 // cpu register - cpu register
1606
1607 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1608 "should be");
1609 Register rreg = right->as_register();
1610 switch (code) {
1611 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1612 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1613 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1614 default: ShouldNotReachHere();
1615 }
1616
1617 } else if (right->is_double_cpu()) {
1618 Register rreg = right->as_register_lo();
1619 // single_cpu + double_cpu: can happen with obj+long
1620 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1621 switch (code) {
1622 case lir_add: __ add(dreg, lreg, rreg); break;
1623 case lir_sub: __ sub(dreg, lreg, rreg); break;
1624 default: ShouldNotReachHere();
1625 }
1626 } else if (right->is_constant()) {
1627 // cpu register - constant
1628 jlong c;
1629
1630 // FIXME. This is fugly: we really need to factor all this logic.
1631 switch(right->type()) {
1632 case T_LONG:
1633 c = right->as_constant_ptr()->as_jlong();
1634 break;
1635 case T_INT:
1636 case T_ADDRESS:
1637 c = right->as_constant_ptr()->as_jint();
1638 break;
1639 default:
1640 ShouldNotReachHere();
1641 c = 0; // unreachable
1642 break;
1643 }
1644
1645 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1646 if (c == 0 && dreg == lreg) {
1647 COMMENT("effective nop elided");
1648 return;
1649 }
1650 switch(left->type()) {
1651 case T_INT:
1652 switch (code) {
1653 case lir_add: __ addw(dreg, lreg, c); break;
1654 case lir_sub: __ subw(dreg, lreg, c); break;
1655 default: ShouldNotReachHere();
1656 }
1657 break;
1658 case T_OBJECT:
1659 case T_ADDRESS:
1660 switch (code) {
1661 case lir_add: __ add(dreg, lreg, c); break;
1662 case lir_sub: __ sub(dreg, lreg, c); break;
1663 default: ShouldNotReachHere();
1664 }
1665 break;
1666 default:
1667 ShouldNotReachHere();
1668 }
1669 } else {
1670 ShouldNotReachHere();
1671 }
1672
1673 } else if (left->is_double_cpu()) {
1674 Register lreg_lo = left->as_register_lo();
1675
1676 if (right->is_double_cpu()) {
1677 // cpu register - cpu register
1678 Register rreg_lo = right->as_register_lo();
1679 switch (code) {
1680 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1681 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1682 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1683 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1684 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1685 default:
1686 ShouldNotReachHere();
1687 }
1688
1689 } else if (right->is_constant()) {
1690 jlong c = right->as_constant_ptr()->as_jlong();
1691 Register dreg = as_reg(dest);
1692 switch (code) {
1693 case lir_add:
1694 case lir_sub:
1695 if (c == 0 && dreg == lreg_lo) {
1696 COMMENT("effective nop elided");
1697 return;
1698 }
1699 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1700 break;
1701 case lir_div:
1702 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1703 if (c == 1) {
1704 // move lreg_lo to dreg if divisor is 1
1705 __ mov(dreg, lreg_lo);
1706 } else {
1707 unsigned int shift = log2i_exact(c);
1708 // use rscratch1 as intermediate result register
1709 __ asr(rscratch1, lreg_lo, 63);
1710 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1711 __ asr(dreg, rscratch1, shift);
1712 }
1713 break;
1714 case lir_rem:
1715 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1716 if (c == 1) {
1717 // move 0 to dreg if divisor is 1
1718 __ mov(dreg, zr);
1719 } else {
1720 // use rscratch1 as intermediate result register
1721 __ negs(rscratch1, lreg_lo);
1722 __ andr(dreg, lreg_lo, c - 1);
1723 __ andr(rscratch1, rscratch1, c - 1);
1724 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1725 }
1726 break;
1727 default:
1728 ShouldNotReachHere();
1729 }
1730 } else {
1731 ShouldNotReachHere();
1732 }
1733 } else if (left->is_single_fpu()) {
1734 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1735 switch (code) {
1736 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1737 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1738 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1739 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1740 default:
1741 ShouldNotReachHere();
1742 }
1743 } else if (left->is_double_fpu()) {
1744 if (right->is_double_fpu()) {
1745 // fpu register - fpu register
1746 switch (code) {
1747 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1748 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1749 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1750 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1751 default:
1752 ShouldNotReachHere();
1753 }
1754 } else {
1755 if (right->is_constant()) {
1756 ShouldNotReachHere();
1757 }
1758 ShouldNotReachHere();
1759 }
1760 } else if (left->is_single_stack() || left->is_address()) {
1761 assert(left == dest, "left and dest must be equal");
1762 ShouldNotReachHere();
1763 } else {
1764 ShouldNotReachHere();
1765 }
1766 }
1767
1768 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1769
1770
1771 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1772 switch(code) {
1773 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1774 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1775 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1776 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1777 default : ShouldNotReachHere();
1778 }
1779 }
1780
1781 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1782
1783 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1784 Register Rleft = left->is_single_cpu() ? left->as_register() :
1785 left->as_register_lo();
1786 if (dst->is_single_cpu()) {
1787 Register Rdst = dst->as_register();
1788 if (right->is_constant()) {
1789 switch (code) {
1790 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1791 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1792 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1793 default: ShouldNotReachHere(); break;
1794 }
1795 } else {
1796 Register Rright = right->is_single_cpu() ? right->as_register() :
1797 right->as_register_lo();
1798 switch (code) {
1799 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1800 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1801 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1802 default: ShouldNotReachHere(); break;
1803 }
1804 }
1805 } else {
1806 Register Rdst = dst->as_register_lo();
1807 if (right->is_constant()) {
1808 switch (code) {
1809 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1810 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1811 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1812 default: ShouldNotReachHere(); break;
1813 }
1814 } else {
1815 Register Rright = right->is_single_cpu() ? right->as_register() :
1816 right->as_register_lo();
1817 switch (code) {
1818 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1819 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1820 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1821 default: ShouldNotReachHere(); break;
1822 }
1823 }
1824 }
1825 }
1826
1827
1828
1829 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1830
1831 // opcode check
1832 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1833 bool is_irem = (code == lir_irem);
1834
1835 // operand check
1836 assert(left->is_single_cpu(), "left must be register");
1837 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1838 assert(result->is_single_cpu(), "result must be register");
1839 Register lreg = left->as_register();
1840 Register dreg = result->as_register();
1841
1842 // power-of-2 constant check and codegen
1843 if (right->is_constant()) {
1844 int c = right->as_constant_ptr()->as_jint();
1845 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1846 if (is_irem) {
1847 if (c == 1) {
1848 // move 0 to dreg if divisor is 1
1849 __ movw(dreg, zr);
1850 } else {
1851 // use rscratch1 as intermediate result register
1852 __ negsw(rscratch1, lreg);
1853 __ andw(dreg, lreg, c - 1);
1854 __ andw(rscratch1, rscratch1, c - 1);
1855 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1856 }
1857 } else {
1858 if (c == 1) {
1859 // move lreg to dreg if divisor is 1
1860 __ movw(dreg, lreg);
1861 } else {
1862 unsigned int shift = exact_log2(c);
1863 // use rscratch1 as intermediate result register
1864 __ asrw(rscratch1, lreg, 31);
1865 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1866 __ asrw(dreg, rscratch1, shift);
1867 }
1868 }
1869 } else {
1870 Register rreg = right->as_register();
1871 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1872 }
1873 }
1874
1875
1876 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1877 if (opr1->is_constant() && opr2->is_single_cpu()) {
1878 // tableswitch
1879 Register reg = as_reg(opr2);
1880 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1881 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1882 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1883 Register reg1 = as_reg(opr1);
1884 if (opr2->is_single_cpu()) {
1885 // cpu register - cpu register
1886 Register reg2 = opr2->as_register();
1887 if (is_reference_type(opr1->type())) {
1888 __ cmpoop(reg1, reg2);
1889 } else {
1890 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1891 __ cmpw(reg1, reg2);
1892 }
1893 return;
1894 }
1895 if (opr2->is_double_cpu()) {
1896 // cpu register - cpu register
1897 Register reg2 = opr2->as_register_lo();
1898 __ cmp(reg1, reg2);
1899 return;
1900 }
1901
1902 if (opr2->is_constant()) {
1903 bool is_32bit = false; // width of register operand
1904 jlong imm;
1905
1906 switch(opr2->type()) {
1907 case T_INT:
1908 imm = opr2->as_constant_ptr()->as_jint();
1909 is_32bit = true;
1910 break;
1911 case T_LONG:
1912 imm = opr2->as_constant_ptr()->as_jlong();
1913 break;
1914 case T_ADDRESS:
1915 imm = opr2->as_constant_ptr()->as_jint();
1916 break;
1917 case T_METADATA:
1918 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1919 break;
1920 case T_OBJECT:
1921 case T_ARRAY:
1922 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1923 __ cmpoop(reg1, rscratch1);
1924 return;
1925 default:
1926 ShouldNotReachHere();
1927 imm = 0; // unreachable
1928 break;
1929 }
1930
1931 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1932 if (is_32bit)
1933 __ cmpw(reg1, imm);
1934 else
1935 __ subs(zr, reg1, imm);
1936 return;
1937 } else {
1938 __ mov(rscratch1, imm);
1939 if (is_32bit)
1940 __ cmpw(reg1, rscratch1);
1941 else
1942 __ cmp(reg1, rscratch1);
1943 return;
1944 }
1945 } else
1946 ShouldNotReachHere();
1947 } else if (opr1->is_single_fpu()) {
1948 FloatRegister reg1 = opr1->as_float_reg();
1949 assert(opr2->is_single_fpu(), "expect single float register");
1950 FloatRegister reg2 = opr2->as_float_reg();
1951 __ fcmps(reg1, reg2);
1952 } else if (opr1->is_double_fpu()) {
1953 FloatRegister reg1 = opr1->as_double_reg();
1954 assert(opr2->is_double_fpu(), "expect double float register");
1955 FloatRegister reg2 = opr2->as_double_reg();
1956 __ fcmpd(reg1, reg2);
1957 } else {
1958 ShouldNotReachHere();
1959 }
1960 }
1961
1962 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1963 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1964 bool is_unordered_less = (code == lir_ucmp_fd2i);
1965 if (left->is_single_fpu()) {
1966 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1967 } else if (left->is_double_fpu()) {
1968 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1969 } else {
1970 ShouldNotReachHere();
1971 }
1972 } else if (code == lir_cmp_l2i) {
1973 Label done;
1974 __ cmp(left->as_register_lo(), right->as_register_lo());
1975 __ mov(dst->as_register(), (uint64_t)-1L);
1976 __ br(Assembler::LT, done);
1977 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1978 __ bind(done);
1979 } else {
1980 ShouldNotReachHere();
1981 }
1982 }
1983
1984
1985 void LIR_Assembler::align_call(LIR_Code code) { }
1986
1987
1988 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
1989 address call = __ trampoline_call(Address(op->addr(), rtype));
1990 if (call == nullptr) {
1991 bailout("trampoline stub overflow");
1992 return;
1993 }
1994 add_call_info(code_offset(), op->info());
1995 __ post_call_nop();
1996 }
1997
1998
1999 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2000 address call = __ ic_call(op->addr());
2001 if (call == nullptr) {
2002 bailout("trampoline stub overflow");
2003 return;
2004 }
2005 add_call_info(code_offset(), op->info());
2006 __ post_call_nop();
2007 }
2008
2009 void LIR_Assembler::emit_static_call_stub() {
2010 address call_pc = __ pc();
2011 address stub = __ start_a_stub(call_stub_size());
2012 if (stub == nullptr) {
2013 bailout("static call stub overflow");
2014 return;
2015 }
2016
2017 int start = __ offset();
2018
2019 __ relocate(static_stub_Relocation::spec(call_pc));
2020 __ emit_static_call_stub();
2021
2022 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2023 <= call_stub_size(), "stub too big");
2024 __ end_a_stub();
2025 }
2026
2027
2028 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2029 assert(exceptionOop->as_register() == r0, "must match");
2030 assert(exceptionPC->as_register() == r3, "must match");
2031
2032 // exception object is not added to oop map by LinearScan
2033 // (LinearScan assumes that no oops are in fixed registers)
2034 info->add_register_oop(exceptionOop);
2035 C1StubId unwind_id;
2036
2037 // get current pc information
2038 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2039 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2040 // As no instructions have been generated yet for this LIR node it's
2041 // possible that an oop map already exists for the current offset.
2042 // In that case insert an dummy NOP here to ensure all oop map PCs
2043 // are unique. See JDK-8237483.
2044 __ nop();
2045 }
2046 int pc_for_athrow_offset = __ offset();
2047 InternalAddress pc_for_athrow(__ pc());
2048 __ adr(exceptionPC->as_register(), pc_for_athrow);
2049 add_call_info(pc_for_athrow_offset, info); // for exception handler
2050
2051 __ verify_not_null_oop(r0);
2052 // search an exception handler (r0: exception oop, r3: throwing pc)
2053 if (compilation()->has_fpu_code()) {
2054 unwind_id = C1StubId::handle_exception_id;
2055 } else {
2056 unwind_id = C1StubId::handle_exception_nofpu_id;
2057 }
2058 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2059
2060 // FIXME: enough room for two byte trap ????
2061 __ nop();
2062 }
2063
2064
2065 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2066 assert(exceptionOop->as_register() == r0, "must match");
2067
2068 __ b(_unwind_handler_entry);
2069 }
2070
2071
2072 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2073 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2074 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2075
2076 switch (left->type()) {
2077 case T_INT: {
2078 switch (code) {
2079 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2080 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2081 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2082 default:
2083 ShouldNotReachHere();
2084 break;
2085 }
2086 break;
2087 case T_LONG:
2088 case T_ADDRESS:
2089 case T_OBJECT:
2090 switch (code) {
2091 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2092 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2093 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2094 default:
2095 ShouldNotReachHere();
2096 break;
2097 }
2098 break;
2099 default:
2100 ShouldNotReachHere();
2101 break;
2102 }
2103 }
2104 }
2105
2106
2107 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2108 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2109 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2110
2111 switch (left->type()) {
2112 case T_INT: {
2113 switch (code) {
2114 case lir_shl: __ lslw (dreg, lreg, count); break;
2115 case lir_shr: __ asrw (dreg, lreg, count); break;
2116 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2117 default:
2118 ShouldNotReachHere();
2119 break;
2120 }
2121 break;
2122 case T_LONG:
2123 case T_ADDRESS:
2124 case T_OBJECT:
2125 switch (code) {
2126 case lir_shl: __ lsl (dreg, lreg, count); break;
2127 case lir_shr: __ asr (dreg, lreg, count); break;
2128 case lir_ushr: __ lsr (dreg, lreg, count); break;
2129 default:
2130 ShouldNotReachHere();
2131 break;
2132 }
2133 break;
2134 default:
2135 ShouldNotReachHere();
2136 break;
2137 }
2138 }
2139 }
2140
2141
2142 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2143 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2144 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2145 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2146 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2147 }
2148
2149
2150 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2151 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2152 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2153 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2154 __ mov (rscratch1, c);
2155 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2156 }
2157
2158
2159 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2160 ShouldNotReachHere();
2161 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2162 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2163 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2164 __ lea(rscratch1, __ constant_oop_address(o));
2165 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2166 }
2167
2168
2169 // This code replaces a call to arraycopy; no exception may
2170 // be thrown in this code, they must be thrown in the System.arraycopy
2171 // activation frame; we could save some checks if this would not be the case
2172 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2173 ciArrayKlass* default_type = op->expected_type();
2174 Register src = op->src()->as_register();
2175 Register dst = op->dst()->as_register();
2176 Register src_pos = op->src_pos()->as_register();
2177 Register dst_pos = op->dst_pos()->as_register();
2178 Register length = op->length()->as_register();
2179 Register tmp = op->tmp()->as_register();
2180
2181 CodeStub* stub = op->stub();
2182 int flags = op->flags();
2183 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2184 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2185
2186 // if we don't know anything, just go through the generic arraycopy
2187 if (default_type == nullptr // || basic_type == T_OBJECT
2188 ) {
2189 Label done;
2190 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2191
2192 // Save the arguments in case the generic arraycopy fails and we
2193 // have to fall back to the JNI stub
2194 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2195 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2196 __ str(src, Address(sp, 4*BytesPerWord));
2197
2198 address copyfunc_addr = StubRoutines::generic_arraycopy();
2199 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2200
2201 // The arguments are in java calling convention so we shift them
2202 // to C convention
2203 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2204 __ mov(c_rarg0, j_rarg0);
2205 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2206 __ mov(c_rarg1, j_rarg1);
2207 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2208 __ mov(c_rarg2, j_rarg2);
2209 assert_different_registers(c_rarg3, j_rarg4);
2210 __ mov(c_rarg3, j_rarg3);
2211 __ mov(c_rarg4, j_rarg4);
2212 #ifndef PRODUCT
2213 if (PrintC1Statistics) {
2214 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2215 }
2216 #endif
2217 __ far_call(RuntimeAddress(copyfunc_addr));
2218
2219 __ cbz(r0, *stub->continuation());
2220
2221 // Reload values from the stack so they are where the stub
2222 // expects them.
2223 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2224 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2225 __ ldr(src, Address(sp, 4*BytesPerWord));
2226
2227 // r0 is -1^K where K == partial copied count
2228 __ eonw(rscratch1, r0, zr);
2229 // adjust length down and src/end pos up by partial copied count
2230 __ subw(length, length, rscratch1);
2231 __ addw(src_pos, src_pos, rscratch1);
2232 __ addw(dst_pos, dst_pos, rscratch1);
2233 __ b(*stub->entry());
2234
2235 __ bind(*stub->continuation());
2236 return;
2237 }
2238
2239 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2240
2241 int elem_size = type2aelembytes(basic_type);
2242 int scale = exact_log2(elem_size);
2243
2244 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2245 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2246 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2247 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2248
2249 // test for null
2250 if (flags & LIR_OpArrayCopy::src_null_check) {
2251 __ cbz(src, *stub->entry());
2252 }
2253 if (flags & LIR_OpArrayCopy::dst_null_check) {
2254 __ cbz(dst, *stub->entry());
2255 }
2256
2257 // If the compiler was not able to prove that exact type of the source or the destination
2258 // of the arraycopy is an array type, check at runtime if the source or the destination is
2259 // an instance type.
2260 if (flags & LIR_OpArrayCopy::type_check) {
2261 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2262 __ load_klass(tmp, dst);
2263 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2264 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2265 __ br(Assembler::GE, *stub->entry());
2266 }
2267
2268 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2269 __ load_klass(tmp, src);
2270 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2271 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2272 __ br(Assembler::GE, *stub->entry());
2273 }
2274 }
2275
2276 // check if negative
2277 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2278 __ cmpw(src_pos, 0);
2279 __ br(Assembler::LT, *stub->entry());
2280 }
2281 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2282 __ cmpw(dst_pos, 0);
2283 __ br(Assembler::LT, *stub->entry());
2284 }
2285
2286 if (flags & LIR_OpArrayCopy::length_positive_check) {
2287 __ cmpw(length, 0);
2288 __ br(Assembler::LT, *stub->entry());
2289 }
2290
2291 if (flags & LIR_OpArrayCopy::src_range_check) {
2292 __ addw(tmp, src_pos, length);
2293 __ ldrw(rscratch1, src_length_addr);
2294 __ cmpw(tmp, rscratch1);
2295 __ br(Assembler::HI, *stub->entry());
2296 }
2297 if (flags & LIR_OpArrayCopy::dst_range_check) {
2298 __ addw(tmp, dst_pos, length);
2299 __ ldrw(rscratch1, dst_length_addr);
2300 __ cmpw(tmp, rscratch1);
2301 __ br(Assembler::HI, *stub->entry());
2302 }
2303
2304 if (flags & LIR_OpArrayCopy::type_check) {
2305 // We don't know the array types are compatible
2306 if (basic_type != T_OBJECT) {
2307 // Simple test for basic type arrays
2308 if (UseCompressedClassPointers) {
2309 __ ldrw(tmp, src_klass_addr);
2310 __ ldrw(rscratch1, dst_klass_addr);
2311 __ cmpw(tmp, rscratch1);
2312 } else {
2313 __ ldr(tmp, src_klass_addr);
2314 __ ldr(rscratch1, dst_klass_addr);
2315 __ cmp(tmp, rscratch1);
2316 }
2317 __ br(Assembler::NE, *stub->entry());
2318 } else {
2319 // For object arrays, if src is a sub class of dst then we can
2320 // safely do the copy.
2321 Label cont, slow;
2322
2323 #define PUSH(r1, r2) \
2324 stp(r1, r2, __ pre(sp, -2 * wordSize));
2325
2326 #define POP(r1, r2) \
2327 ldp(r1, r2, __ post(sp, 2 * wordSize));
2328
2329 __ PUSH(src, dst);
2330
2331 __ load_klass(src, src);
2332 __ load_klass(dst, dst);
2333
2334 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2335
2336 __ PUSH(src, dst);
2337 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
2338 __ POP(src, dst);
2339
2340 __ cbnz(src, cont);
2341
2342 __ bind(slow);
2343 __ POP(src, dst);
2344
2345 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2346 if (copyfunc_addr != nullptr) { // use stub if available
2347 // src is not a sub class of dst so we have to do a
2348 // per-element check.
2349
2350 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2351 if ((flags & mask) != mask) {
2352 // Check that at least both of them object arrays.
2353 assert(flags & mask, "one of the two should be known to be an object array");
2354
2355 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2356 __ load_klass(tmp, src);
2357 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2358 __ load_klass(tmp, dst);
2359 }
2360 int lh_offset = in_bytes(Klass::layout_helper_offset());
2361 Address klass_lh_addr(tmp, lh_offset);
2362 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2363 __ ldrw(rscratch1, klass_lh_addr);
2364 __ mov(rscratch2, objArray_lh);
2365 __ eorw(rscratch1, rscratch1, rscratch2);
2366 __ cbnzw(rscratch1, *stub->entry());
2367 }
2368
2369 // Spill because stubs can use any register they like and it's
2370 // easier to restore just those that we care about.
2371 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2372 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2373 __ str(src, Address(sp, 4*BytesPerWord));
2374
2375 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2376 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2377 assert_different_registers(c_rarg0, dst, dst_pos, length);
2378 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2379 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2380 assert_different_registers(c_rarg1, dst, length);
2381 __ uxtw(c_rarg2, length);
2382 assert_different_registers(c_rarg2, dst);
2383
2384 __ load_klass(c_rarg4, dst);
2385 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2386 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2387 __ far_call(RuntimeAddress(copyfunc_addr));
2388
2389 #ifndef PRODUCT
2390 if (PrintC1Statistics) {
2391 Label failed;
2392 __ cbnz(r0, failed);
2393 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2394 __ bind(failed);
2395 }
2396 #endif
2397
2398 __ cbz(r0, *stub->continuation());
2399
2400 #ifndef PRODUCT
2401 if (PrintC1Statistics) {
2402 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2403 }
2404 #endif
2405 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2406
2407 // Restore previously spilled arguments
2408 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2409 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2410 __ ldr(src, Address(sp, 4*BytesPerWord));
2411
2412 // return value is -1^K where K is partial copied count
2413 __ eonw(rscratch1, r0, zr);
2414 // adjust length down and src/end pos up by partial copied count
2415 __ subw(length, length, rscratch1);
2416 __ addw(src_pos, src_pos, rscratch1);
2417 __ addw(dst_pos, dst_pos, rscratch1);
2418 }
2419
2420 __ b(*stub->entry());
2421
2422 __ bind(cont);
2423 __ POP(src, dst);
2424 }
2425 }
2426
2427 #ifdef ASSERT
2428 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2429 // Sanity check the known type with the incoming class. For the
2430 // primitive case the types must match exactly with src.klass and
2431 // dst.klass each exactly matching the default type. For the
2432 // object array case, if no type check is needed then either the
2433 // dst type is exactly the expected type and the src type is a
2434 // subtype which we can't check or src is the same array as dst
2435 // but not necessarily exactly of type default_type.
2436 Label known_ok, halt;
2437 __ mov_metadata(tmp, default_type->constant_encoding());
2438 if (UseCompressedClassPointers) {
2439 __ encode_klass_not_null(tmp);
2440 }
2441
2442 if (basic_type != T_OBJECT) {
2443
2444 if (UseCompressedClassPointers) {
2445 __ ldrw(rscratch1, dst_klass_addr);
2446 __ cmpw(tmp, rscratch1);
2447 } else {
2448 __ ldr(rscratch1, dst_klass_addr);
2449 __ cmp(tmp, rscratch1);
2450 }
2451 __ br(Assembler::NE, halt);
2452 if (UseCompressedClassPointers) {
2453 __ ldrw(rscratch1, src_klass_addr);
2454 __ cmpw(tmp, rscratch1);
2455 } else {
2456 __ ldr(rscratch1, src_klass_addr);
2457 __ cmp(tmp, rscratch1);
2458 }
2459 __ br(Assembler::EQ, known_ok);
2460 } else {
2461 if (UseCompressedClassPointers) {
2462 __ ldrw(rscratch1, dst_klass_addr);
2463 __ cmpw(tmp, rscratch1);
2464 } else {
2465 __ ldr(rscratch1, dst_klass_addr);
2466 __ cmp(tmp, rscratch1);
2467 }
2468 __ br(Assembler::EQ, known_ok);
2469 __ cmp(src, dst);
2470 __ br(Assembler::EQ, known_ok);
2471 }
2472 __ bind(halt);
2473 __ stop("incorrect type information in arraycopy");
2474 __ bind(known_ok);
2475 }
2476 #endif
2477
2478 #ifndef PRODUCT
2479 if (PrintC1Statistics) {
2480 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2481 }
2482 #endif
2483
2484 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2485 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2486 assert_different_registers(c_rarg0, dst, dst_pos, length);
2487 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2488 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2489 assert_different_registers(c_rarg1, dst, length);
2490 __ uxtw(c_rarg2, length);
2491 assert_different_registers(c_rarg2, dst);
2492
2493 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2494 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2495 const char *name;
2496 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2497
2498 CodeBlob *cb = CodeCache::find_blob(entry);
2499 if (cb) {
2500 __ far_call(RuntimeAddress(entry));
2501 } else {
2502 __ call_VM_leaf(entry, 3);
2503 }
2504
2505 if (stub != nullptr) {
2506 __ bind(*stub->continuation());
2507 }
2508 }
2509
2510
2511
2512
2513 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2514 Register obj = op->obj_opr()->as_register(); // may not be an oop
2515 Register hdr = op->hdr_opr()->as_register();
2516 Register lock = op->lock_opr()->as_register();
2517 Register temp = op->scratch_opr()->as_register();
2518 if (LockingMode == LM_MONITOR) {
2519 if (op->info() != nullptr) {
2520 add_debug_info_for_null_check_here(op->info());
2521 __ null_check(obj, -1);
2522 }
2523 __ b(*op->stub()->entry());
2524 } else if (op->code() == lir_lock) {
2525 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2526 // add debug info for NullPointerException only if one is possible
2527 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2528 if (op->info() != nullptr) {
2529 add_debug_info_for_null_check(null_check_offset, op->info());
2530 }
2531 // done
2532 } else if (op->code() == lir_unlock) {
2533 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2534 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2535 } else {
2536 Unimplemented();
2537 }
2538 __ bind(*op->stub()->continuation());
2539 }
2540
2541 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2542 Register obj = op->obj()->as_pointer_register();
2543 Register result = op->result_opr()->as_pointer_register();
2544
2545 CodeEmitInfo* info = op->info();
2546 if (info != nullptr) {
2547 add_debug_info_for_null_check_here(info);
2548 }
2549
2550 if (UseCompressedClassPointers) {
2551 __ ldrw(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2552 __ decode_klass_not_null(result);
2553 } else {
2554 __ ldr(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2555 }
2556 }
2557
2558 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2559 ciMethod* method = op->profiled_method();
2560 int bci = op->profiled_bci();
2561 ciMethod* callee = op->profiled_callee();
2562
2563 // Update counter for all call types
2564 ciMethodData* md = method->method_data_or_null();
2565 assert(md != nullptr, "Sanity");
2566 ciProfileData* data = md->bci_to_data(bci);
2567 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2568 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2569 Register mdo = op->mdo()->as_register();
2570 __ mov_metadata(mdo, md->constant_encoding());
2571 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2572 // Perform additional virtual call profiling for invokevirtual and
2573 // invokeinterface bytecodes
2574 if (op->should_profile_receiver_type()) {
2575 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2576 Register recv = op->recv()->as_register();
2577 assert_different_registers(mdo, recv);
2578 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2579 ciKlass* known_klass = op->known_holder();
2580 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2581 // We know the type that will be seen at this call site; we can
2582 // statically update the MethodData* rather than needing to do
2583 // dynamic tests on the receiver type
2584
2585 // NOTE: we should probably put a lock around this search to
2586 // avoid collisions by concurrent compilations
2587 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2588 uint i;
2589 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2590 ciKlass* receiver = vc_data->receiver(i);
2591 if (known_klass->equals(receiver)) {
2592 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2593 __ addptr(data_addr, DataLayout::counter_increment);
2594 return;
2595 }
2596 }
2597
2598 // Receiver type not found in profile data; select an empty slot
2599
2600 // Note that this is less efficient than it should be because it
2601 // always does a write to the receiver part of the
2602 // VirtualCallData rather than just the first time
2603 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2604 ciKlass* receiver = vc_data->receiver(i);
2605 if (receiver == nullptr) {
2606 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2607 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2608 __ lea(rscratch2, recv_addr);
2609 __ str(rscratch1, Address(rscratch2));
2610 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2611 __ addptr(data_addr, DataLayout::counter_increment);
2612 return;
2613 }
2614 }
2615 } else {
2616 __ load_klass(recv, recv);
2617 Label update_done;
2618 type_profile_helper(mdo, md, data, recv, &update_done);
2619 // Receiver did not match any saved receiver and there is no empty row for it.
2620 // Increment total counter to indicate polymorphic case.
2621 __ addptr(counter_addr, DataLayout::counter_increment);
2622
2623 __ bind(update_done);
2624 }
2625 } else {
2626 // Static call
2627 __ addptr(counter_addr, DataLayout::counter_increment);
2628 }
2629 }
2630
2631
2632 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2633 Unimplemented();
2634 }
2635
2636
2637 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2638 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2639 }
2640
2641 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2642 assert(op->crc()->is_single_cpu(), "crc must be register");
2643 assert(op->val()->is_single_cpu(), "byte value must be register");
2644 assert(op->result_opr()->is_single_cpu(), "result must be register");
2645 Register crc = op->crc()->as_register();
2646 Register val = op->val()->as_register();
2647 Register res = op->result_opr()->as_register();
2648
2649 assert_different_registers(val, crc, res);
2650 uint64_t offset;
2651 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2652 __ add(res, res, offset);
2653
2654 __ mvnw(crc, crc); // ~crc
2655 __ update_byte_crc32(crc, val, res);
2656 __ mvnw(res, crc); // ~crc
2657 }
2658
2659 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2660 COMMENT("emit_profile_type {");
2661 Register obj = op->obj()->as_register();
2662 Register tmp = op->tmp()->as_pointer_register();
2663 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2664 ciKlass* exact_klass = op->exact_klass();
2665 intptr_t current_klass = op->current_klass();
2666 bool not_null = op->not_null();
2667 bool no_conflict = op->no_conflict();
2668
2669 Label update, next, none;
2670
2671 bool do_null = !not_null;
2672 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2673 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2674
2675 assert(do_null || do_update, "why are we here?");
2676 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2677 assert(mdo_addr.base() != rscratch1, "wrong register");
2678
2679 __ verify_oop(obj);
2680
2681 if (tmp != obj) {
2682 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2683 __ mov(tmp, obj);
2684 } else {
2685 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2686 }
2687 if (do_null) {
2688 __ cbnz(tmp, update);
2689 if (!TypeEntries::was_null_seen(current_klass)) {
2690 __ ldr(rscratch2, mdo_addr);
2691 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2692 __ str(rscratch2, mdo_addr);
2693 }
2694 if (do_update) {
2695 #ifndef ASSERT
2696 __ b(next);
2697 }
2698 #else
2699 __ b(next);
2700 }
2701 } else {
2702 __ cbnz(tmp, update);
2703 __ stop("unexpected null obj");
2704 #endif
2705 }
2706
2707 __ bind(update);
2708
2709 if (do_update) {
2710 #ifdef ASSERT
2711 if (exact_klass != nullptr) {
2712 Label ok;
2713 __ load_klass(tmp, tmp);
2714 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2715 __ eor(rscratch1, tmp, rscratch1);
2716 __ cbz(rscratch1, ok);
2717 __ stop("exact klass and actual klass differ");
2718 __ bind(ok);
2719 }
2720 #endif
2721 if (!no_conflict) {
2722 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2723 if (exact_klass != nullptr) {
2724 __ mov_metadata(tmp, exact_klass->constant_encoding());
2725 } else {
2726 __ load_klass(tmp, tmp);
2727 }
2728
2729 __ ldr(rscratch2, mdo_addr);
2730 __ eor(tmp, tmp, rscratch2);
2731 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2732 // klass seen before, nothing to do. The unknown bit may have been
2733 // set already but no need to check.
2734 __ cbz(rscratch1, next);
2735
2736 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2737
2738 if (TypeEntries::is_type_none(current_klass)) {
2739 __ cbz(rscratch2, none);
2740 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2741 __ br(Assembler::EQ, none);
2742 // There is a chance that the checks above
2743 // fail if another thread has just set the
2744 // profiling to this obj's klass
2745 __ dmb(Assembler::ISHLD);
2746 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2747 __ ldr(rscratch2, mdo_addr);
2748 __ eor(tmp, tmp, rscratch2);
2749 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2750 __ cbz(rscratch1, next);
2751 }
2752 } else {
2753 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2754 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2755
2756 __ ldr(tmp, mdo_addr);
2757 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2758 }
2759
2760 // different than before. Cannot keep accurate profile.
2761 __ ldr(rscratch2, mdo_addr);
2762 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2763 __ str(rscratch2, mdo_addr);
2764
2765 if (TypeEntries::is_type_none(current_klass)) {
2766 __ b(next);
2767
2768 __ bind(none);
2769 // first time here. Set profile type.
2770 __ str(tmp, mdo_addr);
2771 #ifdef ASSERT
2772 __ andr(tmp, tmp, TypeEntries::type_mask);
2773 __ verify_klass_ptr(tmp);
2774 #endif
2775 }
2776 } else {
2777 // There's a single possible klass at this profile point
2778 assert(exact_klass != nullptr, "should be");
2779 if (TypeEntries::is_type_none(current_klass)) {
2780 __ mov_metadata(tmp, exact_klass->constant_encoding());
2781 __ ldr(rscratch2, mdo_addr);
2782 __ eor(tmp, tmp, rscratch2);
2783 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2784 __ cbz(rscratch1, next);
2785 #ifdef ASSERT
2786 {
2787 Label ok;
2788 __ ldr(rscratch1, mdo_addr);
2789 __ cbz(rscratch1, ok);
2790 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2791 __ br(Assembler::EQ, ok);
2792 // may have been set by another thread
2793 __ dmb(Assembler::ISHLD);
2794 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2795 __ ldr(rscratch2, mdo_addr);
2796 __ eor(rscratch2, rscratch1, rscratch2);
2797 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2798 __ cbz(rscratch2, ok);
2799
2800 __ stop("unexpected profiling mismatch");
2801 __ bind(ok);
2802 }
2803 #endif
2804 // first time here. Set profile type.
2805 __ str(tmp, mdo_addr);
2806 #ifdef ASSERT
2807 __ andr(tmp, tmp, TypeEntries::type_mask);
2808 __ verify_klass_ptr(tmp);
2809 #endif
2810 } else {
2811 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2812 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2813
2814 __ ldr(tmp, mdo_addr);
2815 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2816
2817 __ orr(tmp, tmp, TypeEntries::type_unknown);
2818 __ str(tmp, mdo_addr);
2819 // FIXME: Write barrier needed here?
2820 }
2821 }
2822
2823 __ bind(next);
2824 }
2825 COMMENT("} emit_profile_type");
2826 }
2827
2828
2829 void LIR_Assembler::align_backward_branch_target() {
2830 }
2831
2832
2833 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2834 // tmp must be unused
2835 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2836
2837 if (left->is_single_cpu()) {
2838 assert(dest->is_single_cpu(), "expect single result reg");
2839 __ negw(dest->as_register(), left->as_register());
2840 } else if (left->is_double_cpu()) {
2841 assert(dest->is_double_cpu(), "expect double result reg");
2842 __ neg(dest->as_register_lo(), left->as_register_lo());
2843 } else if (left->is_single_fpu()) {
2844 assert(dest->is_single_fpu(), "expect single float result reg");
2845 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2846 } else {
2847 assert(left->is_double_fpu(), "expect double float operand reg");
2848 assert(dest->is_double_fpu(), "expect double float result reg");
2849 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2850 }
2851 }
2852
2853
2854 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2855 if (patch_code != lir_patch_none) {
2856 deoptimize_trap(info);
2857 return;
2858 }
2859
2860 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2861 }
2862
2863
2864 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2865 assert(!tmp->is_valid(), "don't need temporary");
2866
2867 CodeBlob *cb = CodeCache::find_blob(dest);
2868 if (cb) {
2869 __ far_call(RuntimeAddress(dest));
2870 } else {
2871 __ mov(rscratch1, RuntimeAddress(dest));
2872 __ blr(rscratch1);
2873 }
2874
2875 if (info != nullptr) {
2876 add_call_info_here(info);
2877 }
2878 __ post_call_nop();
2879 }
2880
2881 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2882 if (dest->is_address() || src->is_address()) {
2883 move_op(src, dest, type, lir_patch_none, info,
2884 /*pop_fpu_stack*/false, /*wide*/false);
2885 } else {
2886 ShouldNotReachHere();
2887 }
2888 }
2889
2890 #ifdef ASSERT
2891 // emit run-time assertion
2892 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2893 assert(op->code() == lir_assert, "must be");
2894
2895 if (op->in_opr1()->is_valid()) {
2896 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2897 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2898 } else {
2899 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2900 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2901 }
2902
2903 Label ok;
2904 if (op->condition() != lir_cond_always) {
2905 Assembler::Condition acond = Assembler::AL;
2906 switch (op->condition()) {
2907 case lir_cond_equal: acond = Assembler::EQ; break;
2908 case lir_cond_notEqual: acond = Assembler::NE; break;
2909 case lir_cond_less: acond = Assembler::LT; break;
2910 case lir_cond_lessEqual: acond = Assembler::LE; break;
2911 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2912 case lir_cond_greater: acond = Assembler::GT; break;
2913 case lir_cond_belowEqual: acond = Assembler::LS; break;
2914 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2915 default: ShouldNotReachHere();
2916 }
2917 __ br(acond, ok);
2918 }
2919 if (op->halt()) {
2920 const char* str = __ code_string(op->msg());
2921 __ stop(str);
2922 } else {
2923 breakpoint();
2924 }
2925 __ bind(ok);
2926 }
2927 #endif
2928
2929 #ifndef PRODUCT
2930 #define COMMENT(x) do { __ block_comment(x); } while (0)
2931 #else
2932 #define COMMENT(x)
2933 #endif
2934
2935 void LIR_Assembler::membar() {
2936 COMMENT("membar");
2937 __ membar(MacroAssembler::AnyAny);
2938 }
2939
2940 void LIR_Assembler::membar_acquire() {
2941 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2942 }
2943
2944 void LIR_Assembler::membar_release() {
2945 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2946 }
2947
2948 void LIR_Assembler::membar_loadload() {
2949 __ membar(Assembler::LoadLoad);
2950 }
2951
2952 void LIR_Assembler::membar_storestore() {
2953 __ membar(MacroAssembler::StoreStore);
2954 }
2955
2956 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2957
2958 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2959
2960 void LIR_Assembler::on_spin_wait() {
2961 __ spin_wait();
2962 }
2963
2964 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2965 __ mov(result_reg->as_register(), rthread);
2966 }
2967
2968
2969 void LIR_Assembler::peephole(LIR_List *lir) {
2970 #if 0
2971 if (tableswitch_count >= max_tableswitches)
2972 return;
2973
2974 /*
2975 This finite-state automaton recognizes sequences of compare-and-
2976 branch instructions. We will turn them into a tableswitch. You
2977 could argue that C1 really shouldn't be doing this sort of
2978 optimization, but without it the code is really horrible.
2979 */
2980
2981 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2982 int first_key, last_key = -2147483648;
2983 int next_key = 0;
2984 int start_insn = -1;
2985 int last_insn = -1;
2986 Register reg = noreg;
2987 LIR_Opr reg_opr;
2988 state = start_s;
2989
2990 LIR_OpList* inst = lir->instructions_list();
2991 for (int i = 0; i < inst->length(); i++) {
2992 LIR_Op* op = inst->at(i);
2993 switch (state) {
2994 case start_s:
2995 first_key = -1;
2996 start_insn = i;
2997 switch (op->code()) {
2998 case lir_cmp:
2999 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3000 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3001 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3002 && opr2->is_constant()
3003 && opr2->type() == T_INT) {
3004 reg_opr = opr1;
3005 reg = opr1->as_register();
3006 first_key = opr2->as_constant_ptr()->as_jint();
3007 next_key = first_key + 1;
3008 state = cmp_s;
3009 goto next_state;
3010 }
3011 break;
3012 }
3013 break;
3014 case cmp_s:
3015 switch (op->code()) {
3016 case lir_branch:
3017 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3018 state = beq_s;
3019 last_insn = i;
3020 goto next_state;
3021 }
3022 }
3023 state = start_s;
3024 break;
3025 case beq_s:
3026 switch (op->code()) {
3027 case lir_cmp: {
3028 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3029 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3030 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3031 && opr1->as_register() == reg
3032 && opr2->is_constant()
3033 && opr2->type() == T_INT
3034 && opr2->as_constant_ptr()->as_jint() == next_key) {
3035 last_key = next_key;
3036 next_key++;
3037 state = cmp_s;
3038 goto next_state;
3039 }
3040 }
3041 }
3042 last_key = next_key;
3043 state = start_s;
3044 break;
3045 default:
3046 assert(false, "impossible state");
3047 }
3048 if (state == start_s) {
3049 if (first_key < last_key - 5L && reg != noreg) {
3050 {
3051 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3052 // reg->encoding(),
3053 // start_insn, first_key, last_key);
3054 // for (int i = 0; i < inst->length(); i++) {
3055 // inst->at(i)->print();
3056 // tty->print("\n");
3057 // }
3058 // tty->print("\n");
3059 }
3060
3061 struct tableswitch *sw = &switches[tableswitch_count];
3062 sw->_insn_index = start_insn, sw->_first_key = first_key,
3063 sw->_last_key = last_key, sw->_reg = reg;
3064 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3065 {
3066 // Insert the new table of branches
3067 int offset = last_insn;
3068 for (int n = first_key; n < last_key; n++) {
3069 inst->insert_before
3070 (last_insn + 1,
3071 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3072 inst->at(offset)->as_OpBranch()->label()));
3073 offset -= 2, i++;
3074 }
3075 }
3076 // Delete all the old compare-and-branch instructions
3077 for (int n = first_key; n < last_key; n++) {
3078 inst->remove_at(start_insn);
3079 inst->remove_at(start_insn);
3080 }
3081 // Insert the tableswitch instruction
3082 inst->insert_before(start_insn,
3083 new LIR_Op2(lir_cmp, lir_cond_always,
3084 LIR_OprFact::intConst(tableswitch_count),
3085 reg_opr));
3086 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3087 tableswitch_count++;
3088 }
3089 reg = noreg;
3090 last_key = -2147483648;
3091 }
3092 next_state:
3093 ;
3094 }
3095 #endif
3096 }
3097
3098 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3099 Address addr = as_Address(src->as_address_ptr());
3100 BasicType type = src->type();
3101 bool is_oop = is_reference_type(type);
3102
3103 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3104 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3105
3106 switch(type) {
3107 case T_INT:
3108 xchg = &MacroAssembler::atomic_xchgalw;
3109 add = &MacroAssembler::atomic_addalw;
3110 break;
3111 case T_LONG:
3112 xchg = &MacroAssembler::atomic_xchgal;
3113 add = &MacroAssembler::atomic_addal;
3114 break;
3115 case T_OBJECT:
3116 case T_ARRAY:
3117 if (UseCompressedOops) {
3118 xchg = &MacroAssembler::atomic_xchgalw;
3119 add = &MacroAssembler::atomic_addalw;
3120 } else {
3121 xchg = &MacroAssembler::atomic_xchgal;
3122 add = &MacroAssembler::atomic_addal;
3123 }
3124 break;
3125 default:
3126 ShouldNotReachHere();
3127 xchg = &MacroAssembler::atomic_xchgal;
3128 add = &MacroAssembler::atomic_addal; // unreachable
3129 }
3130
3131 switch (code) {
3132 case lir_xadd:
3133 {
3134 RegisterOrConstant inc;
3135 Register tmp = as_reg(tmp_op);
3136 Register dst = as_reg(dest);
3137 if (data->is_constant()) {
3138 inc = RegisterOrConstant(as_long(data));
3139 assert_different_registers(dst, addr.base(), tmp,
3140 rscratch1, rscratch2);
3141 } else {
3142 inc = RegisterOrConstant(as_reg(data));
3143 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3144 rscratch1, rscratch2);
3145 }
3146 __ lea(tmp, addr);
3147 (_masm->*add)(dst, inc, tmp);
3148 break;
3149 }
3150 case lir_xchg:
3151 {
3152 Register tmp = tmp_op->as_register();
3153 Register obj = as_reg(data);
3154 Register dst = as_reg(dest);
3155 if (is_oop && UseCompressedOops) {
3156 __ encode_heap_oop(rscratch2, obj);
3157 obj = rscratch2;
3158 }
3159 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3160 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3161 __ lea(tmp, addr);
3162 (_masm->*xchg)(dst, obj, tmp);
3163 if (is_oop && UseCompressedOops) {
3164 __ decode_heap_oop(dst);
3165 }
3166 }
3167 break;
3168 default:
3169 ShouldNotReachHere();
3170 }
3171 __ membar(__ AnyAny);
3172 }
3173
3174 #undef __