1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInlineKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "ci/ciObjArrayKlass.hpp"
38 #include "code/compiledIC.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "oops/oop.inline.hpp"
44 #include "runtime/frame.inline.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_aarch64.inline.hpp"
49
50
51 #ifndef PRODUCT
52 #define COMMENT(x) do { __ block_comment(x); } while (0)
53 #else
54 #define COMMENT(x)
55 #endif
56
57 NEEDS_CLEANUP // remove this definitions ?
58 const Register SYNC_header = r0; // synchronization header
59 const Register SHIFT_count = r0; // where count for shift operations must be
60
61 #define __ _masm->
62
63
64 static void select_different_registers(Register preserve,
65 Register extra,
66 Register &tmp1,
67 Register &tmp2) {
68 if (tmp1 == preserve) {
69 assert_different_registers(tmp1, tmp2, extra);
70 tmp1 = extra;
71 } else if (tmp2 == preserve) {
72 assert_different_registers(tmp1, tmp2, extra);
73 tmp2 = extra;
74 }
75 assert_different_registers(preserve, tmp1, tmp2);
76 }
77
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2,
84 Register &tmp3) {
85 if (tmp1 == preserve) {
86 assert_different_registers(tmp1, tmp2, tmp3, extra);
87 tmp1 = extra;
88 } else if (tmp2 == preserve) {
89 assert_different_registers(tmp1, tmp2, tmp3, extra);
90 tmp2 = extra;
91 } else if (tmp3 == preserve) {
92 assert_different_registers(tmp1, tmp2, tmp3, extra);
93 tmp3 = extra;
94 }
95 assert_different_registers(preserve, tmp1, tmp2, tmp3);
96 }
97
98
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
100
101
102 LIR_Opr LIR_Assembler::receiverOpr() {
103 return FrameMap::receiver_opr;
104 }
105
106 LIR_Opr LIR_Assembler::osrBufferPointer() {
107 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
108 }
109
110 //--------------fpu register translations-----------------------
111
112
113 address LIR_Assembler::float_constant(float f) {
114 address const_addr = __ float_constant(f);
115 if (const_addr == nullptr) {
116 bailout("const section overflow");
117 return __ code()->consts()->start();
118 } else {
119 return const_addr;
120 }
121 }
122
123
124 address LIR_Assembler::double_constant(double d) {
125 address const_addr = __ double_constant(d);
126 if (const_addr == nullptr) {
127 bailout("const section overflow");
128 return __ code()->consts()->start();
129 } else {
130 return const_addr;
131 }
132 }
133
134 address LIR_Assembler::int_constant(jlong n) {
135 address const_addr = __ long_constant(n);
136 if (const_addr == nullptr) {
137 bailout("const section overflow");
138 return __ code()->consts()->start();
139 } else {
140 return const_addr;
141 }
142 }
143
144 void LIR_Assembler::breakpoint() { Unimplemented(); }
145
146 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
147
148 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
149
150 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
151 //-------------------------------------------
152
153 static Register as_reg(LIR_Opr op) {
154 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
155 }
156
157 static jlong as_long(LIR_Opr data) {
158 jlong result;
159 switch (data->type()) {
160 case T_INT:
161 result = (data->as_jint());
162 break;
163 case T_LONG:
164 result = (data->as_jlong());
165 break;
166 default:
167 ShouldNotReachHere();
168 result = 0; // unreachable
169 }
170 return result;
171 }
172
173 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
174 Register base = addr->base()->as_pointer_register();
175 LIR_Opr opr = addr->index();
176 if (opr->is_cpu_register()) {
177 Register index;
178 if (opr->is_single_cpu())
179 index = opr->as_register();
180 else
181 index = opr->as_register_lo();
182 assert(addr->disp() == 0, "must be");
183 switch(opr->type()) {
184 case T_INT:
185 return Address(base, index, Address::sxtw(addr->scale()));
186 case T_LONG:
187 return Address(base, index, Address::lsl(addr->scale()));
188 default:
189 ShouldNotReachHere();
190 }
191 } else {
192 assert(addr->scale() == 0,
193 "expected for immediate operand, was: %d", addr->scale());
194 ptrdiff_t offset = ptrdiff_t(addr->disp());
195 // NOTE: Does not handle any 16 byte vector access.
196 const uint type_size = type2aelembytes(addr->type(), true);
197 return __ legitimize_address(Address(base, offset), type_size, tmp);
198 }
199 return Address();
200 }
201
202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
203 ShouldNotReachHere();
204 return Address();
205 }
206
207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
208 return as_Address(addr, rscratch1);
209 }
210
211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
212 return as_Address(addr, rscratch1); // Ouch
213 // FIXME: This needs to be much more clever. See x86.
214 }
215
216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
217 // not encodable as a base + (immediate) offset, generate an explicit address
218 // calculation to hold the address in a temporary register.
219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
220 precond(size == 4 || size == 8);
221 Address addr = frame_map()->address_for_slot(index, adjust);
222 precond(addr.getMode() == Address::base_plus_offset);
223 precond(addr.base() == sp);
224 precond(addr.offset() > 0);
225 uint mask = size - 1;
226 assert((addr.offset() & mask) == 0, "scaled offsets only");
227 return __ legitimize_address(addr, size, tmp);
228 }
229
230 void LIR_Assembler::osr_entry() {
231 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
232 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
233 ValueStack* entry_state = osr_entry->state();
234 int number_of_locks = entry_state->locks_size();
235
236 // we jump here if osr happens with the interpreter
237 // state set up to continue at the beginning of the
238 // loop that triggered osr - in particular, we have
239 // the following registers setup:
240 //
241 // r2: osr buffer
242 //
243
244 // build frame
245 ciMethod* m = compilation()->method();
246 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
247
248 // OSR buffer is
249 //
250 // locals[nlocals-1..0]
251 // monitors[0..number_of_locks]
252 //
253 // locals is a direct copy of the interpreter frame so in the osr buffer
254 // so first slot in the local array is the last local from the interpreter
255 // and last slot is local[0] (receiver) from the interpreter
256 //
257 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
258 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
259 // in the interpreter frame (the method lock if a sync method)
260
261 // Initialize monitors in the compiled activation.
262 // r2: pointer to osr buffer
263 //
264 // All other registers are dead at this point and the locals will be
265 // copied into place by code emitted in the IR.
266
267 Register OSR_buf = osrBufferPointer()->as_pointer_register();
268 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
269 int monitor_offset = BytesPerWord * method()->max_locals() +
270 (2 * BytesPerWord) * (number_of_locks - 1);
271 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
272 // the OSR buffer using 2 word entries: first the lock and then
273 // the oop.
274 for (int i = 0; i < number_of_locks; i++) {
275 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
276 #ifdef ASSERT
277 // verify the interpreter's monitor has a non-null object
278 {
279 Label L;
280 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
281 __ cbnz(rscratch1, L);
282 __ stop("locked object is null");
283 __ bind(L);
284 }
285 #endif
286 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
287 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
288 __ str(r19, frame_map()->address_for_monitor_lock(i));
289 __ str(r20, frame_map()->address_for_monitor_object(i));
290 }
291 }
292 }
293
294
295 // inline cache check; done before the frame is built.
296 int LIR_Assembler::check_icache() {
297 return __ ic_check(CodeEntryAlignment);
298 }
299
300 void LIR_Assembler::clinit_barrier(ciMethod* method) {
301 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
302 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
303
304 Label L_skip_barrier;
305
306 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
307 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
308 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
309 __ bind(L_skip_barrier);
310 }
311
312 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
313 if (o == nullptr) {
314 __ mov(reg, zr);
315 } else {
316 __ movoop(reg, o);
317 }
318 }
319
320 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
321 address target = nullptr;
322 relocInfo::relocType reloc_type = relocInfo::none;
323
324 switch (patching_id(info)) {
325 case PatchingStub::access_field_id:
326 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
327 reloc_type = relocInfo::section_word_type;
328 break;
329 case PatchingStub::load_klass_id:
330 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
331 reloc_type = relocInfo::metadata_type;
332 break;
333 case PatchingStub::load_mirror_id:
334 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
335 reloc_type = relocInfo::oop_type;
336 break;
337 case PatchingStub::load_appendix_id:
338 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
339 reloc_type = relocInfo::oop_type;
340 break;
341 default: ShouldNotReachHere();
342 }
343
344 __ far_call(RuntimeAddress(target));
345 add_call_info_here(info);
346 }
347
348 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
349 deoptimize_trap(info);
350 }
351
352
353 // This specifies the rsp decrement needed to build the frame
354 int LIR_Assembler::initial_frame_size_in_bytes() const {
355 // if rounding, must let FrameMap know!
356
357 return in_bytes(frame_map()->framesize_in_bytes());
358 }
359
360
361 int LIR_Assembler::emit_exception_handler() {
362 // generate code for exception handler
363 address handler_base = __ start_a_stub(exception_handler_size());
364 if (handler_base == nullptr) {
365 // not enough space left for the handler
366 bailout("exception handler overflow");
367 return -1;
368 }
369
370 int offset = code_offset();
371
372 // the exception oop and pc are in r0, and r3
373 // no other registers need to be preserved, so invalidate them
374 __ invalidate_registers(false, true, true, false, true, true);
375
376 // check that there is really an exception
377 __ verify_not_null_oop(r0);
378
379 // search an exception handler (r0: exception oop, r3: throwing pc)
380 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
381 __ should_not_reach_here();
382 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
383 __ end_a_stub();
384
385 return offset;
386 }
387
388
389 // Emit the code to remove the frame from the stack in the exception
390 // unwind path.
391 int LIR_Assembler::emit_unwind_handler() {
392 #ifndef PRODUCT
393 if (CommentedAssembly) {
394 _masm->block_comment("Unwind handler");
395 }
396 #endif
397
398 int offset = code_offset();
399
400 // Fetch the exception from TLS and clear out exception related thread state
401 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
403 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
404
405 __ bind(_unwind_handler_entry);
406 __ verify_not_null_oop(r0);
407 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
408 __ mov(r19, r0); // Preserve the exception
409 }
410
411 // Perform needed unlocking
412 MonitorExitStub* stub = nullptr;
413 if (method()->is_synchronized()) {
414 monitor_address(0, FrameMap::r0_opr);
415 stub = new MonitorExitStub(FrameMap::r0_opr, 0);
416 __ unlock_object(r5, r4, r0, r6, *stub->entry());
417 __ bind(*stub->continuation());
418 }
419
420 if (compilation()->env()->dtrace_method_probes()) {
421 __ mov(c_rarg0, rthread);
422 __ mov_metadata(c_rarg1, method()->constant_encoding());
423 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
424 }
425
426 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
427 __ mov(r0, r19); // Restore the exception
428 }
429
430 // remove the activation and dispatch to the unwind handler
431 __ block_comment("remove_frame and dispatch to the unwind handler");
432 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
433 __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
434
435 // Emit the slow path assembly
436 if (stub != nullptr) {
437 stub->emit_code(this);
438 }
439
440 return offset;
441 }
442
443
444 int LIR_Assembler::emit_deopt_handler() {
445 // generate code for exception handler
446 address handler_base = __ start_a_stub(deopt_handler_size());
447 if (handler_base == nullptr) {
448 // not enough space left for the handler
449 bailout("deopt handler overflow");
450 return -1;
451 }
452
453 int offset = code_offset();
454
455 Label start;
456 __ bind(start);
457
458 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
459
460 int entry_offset = __ offset();
461 __ b(start);
462
463 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
464 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
465 "out of bounds read in post-call NOP check");
466 __ end_a_stub();
467
468 return entry_offset;
469 }
470
471 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
472 _masm->code_section()->relocate(adr, relocInfo::poll_type);
473 int pc_offset = code_offset();
474 flush_debug_info(pc_offset);
475 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
476 if (info->exception_handlers() != nullptr) {
477 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
478 }
479 }
480
481 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
482 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
483
484 if (InlineTypeReturnedAsFields) {
485 // Check if we are returning an non-null inline type and load its fields into registers
486 ciType* return_type = compilation()->method()->return_type();
487 if (return_type->is_inlinetype()) {
488 ciInlineKlass* vk = return_type->as_inline_klass();
489 if (vk->can_be_returned_as_fields()) {
490 address unpack_handler = vk->unpack_handler();
491 assert(unpack_handler != nullptr, "must be");
492 __ far_call(RuntimeAddress(unpack_handler));
493 }
494 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) {
495 Label skip;
496 Label not_null;
497 __ cbnz(r0, not_null);
498 // Returned value is null, zero all return registers because they may belong to oop fields
499 __ mov(j_rarg1, zr);
500 __ mov(j_rarg2, zr);
501 __ mov(j_rarg3, zr);
502 __ mov(j_rarg4, zr);
503 __ mov(j_rarg5, zr);
504 __ mov(j_rarg6, zr);
505 __ mov(j_rarg7, zr);
506 __ b(skip);
507 __ bind(not_null);
508
509 // Check if we are returning an non-null inline type and load its fields into registers
510 __ test_oop_is_not_inline_type(r0, rscratch2, skip, /* can_be_null= */ false);
511
512 // Load fields from a buffered value with an inline class specific handler
513 __ load_klass(rscratch1 /*dst*/, r0 /*src*/);
514 __ ldr(rscratch1, Address(rscratch1, InlineKlass::adr_members_offset()));
515 __ ldr(rscratch1, Address(rscratch1, InlineKlass::unpack_handler_offset()));
516 // Unpack handler can be null if inline type is not scalarizable in returns
517 __ cbz(rscratch1, skip);
518 __ blr(rscratch1);
519
520 __ bind(skip);
521 }
522 // At this point, r0 points to the value object (for interpreter or C1 caller).
523 // The fields of the object are copied into registers (for C2 caller).
524 }
525
526 // Pop the stack before the safepoint code
527 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
528
529 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
530 __ reserved_stack_check();
531 }
532
533 code_stub->set_safepoint_offset(__ offset());
534 __ relocate(relocInfo::poll_return_type);
535 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
536 __ ret(lr);
537 }
538
539 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
540 return (__ store_inline_type_fields_to_buf(vk, false));
541 }
542
543 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
544 guarantee(info != nullptr, "Shouldn't be null");
545 __ get_polling_page(rscratch1, relocInfo::poll_type);
546 add_debug_info_for_branch(info); // This isn't just debug info:
547 // it's the oop map
548 __ read_polling_page(rscratch1, relocInfo::poll_type);
549 return __ offset();
550 }
551
552
553 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
554 if (from_reg == r31_sp)
555 from_reg = sp;
556 if (to_reg == r31_sp)
557 to_reg = sp;
558 __ mov(to_reg, from_reg);
559 }
560
561 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
562
563
564 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
565 assert(src->is_constant(), "should not call otherwise");
566 assert(dest->is_register(), "should not call otherwise");
567 LIR_Const* c = src->as_constant_ptr();
568
569 switch (c->type()) {
570 case T_INT: {
571 assert(patch_code == lir_patch_none, "no patching handled here");
572 __ movw(dest->as_register(), c->as_jint());
573 break;
574 }
575
576 case T_ADDRESS: {
577 assert(patch_code == lir_patch_none, "no patching handled here");
578 __ mov(dest->as_register(), c->as_jint());
579 break;
580 }
581
582 case T_LONG: {
583 assert(patch_code == lir_patch_none, "no patching handled here");
584 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
585 break;
586 }
587
588 case T_OBJECT: {
589 if (patch_code != lir_patch_none) {
590 jobject2reg_with_patching(dest->as_register(), info);
591 } else {
592 jobject2reg(c->as_jobject(), dest->as_register());
593 }
594 break;
595 }
596
597 case T_METADATA: {
598 if (patch_code != lir_patch_none) {
599 klass2reg_with_patching(dest->as_register(), info);
600 } else {
601 __ mov_metadata(dest->as_register(), c->as_metadata());
602 }
603 break;
604 }
605
606 case T_FLOAT: {
607 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
608 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
609 } else {
610 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
611 __ ldrs(dest->as_float_reg(), Address(rscratch1));
612 }
613 break;
614 }
615
616 case T_DOUBLE: {
617 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
618 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
619 } else {
620 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
621 __ ldrd(dest->as_double_reg(), Address(rscratch1));
622 }
623 break;
624 }
625
626 default:
627 ShouldNotReachHere();
628 }
629 }
630
631 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
632 LIR_Const* c = src->as_constant_ptr();
633 switch (c->type()) {
634 case T_OBJECT:
635 {
636 if (! c->as_jobject())
637 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
638 else {
639 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
640 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
641 }
642 }
643 break;
644 case T_ADDRESS:
645 {
646 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
647 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
648 }
649 case T_INT:
650 case T_FLOAT:
651 {
652 Register reg = zr;
653 if (c->as_jint_bits() == 0)
654 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
655 else {
656 __ movw(rscratch1, c->as_jint_bits());
657 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
658 }
659 }
660 break;
661 case T_LONG:
662 case T_DOUBLE:
663 {
664 Register reg = zr;
665 if (c->as_jlong_bits() == 0)
666 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
667 lo_word_offset_in_bytes));
668 else {
669 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
670 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
671 lo_word_offset_in_bytes));
672 }
673 }
674 break;
675 default:
676 ShouldNotReachHere();
677 }
678 }
679
680 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
681 assert(src->is_constant(), "should not call otherwise");
682 LIR_Const* c = src->as_constant_ptr();
683 LIR_Address* to_addr = dest->as_address_ptr();
684
685 void (Assembler::* insn)(Register Rt, const Address &adr);
686
687 switch (type) {
688 case T_ADDRESS:
689 assert(c->as_jint() == 0, "should be");
690 insn = &Assembler::str;
691 break;
692 case T_LONG:
693 assert(c->as_jlong() == 0, "should be");
694 insn = &Assembler::str;
695 break;
696 case T_INT:
697 assert(c->as_jint() == 0, "should be");
698 insn = &Assembler::strw;
699 break;
700 case T_OBJECT:
701 case T_ARRAY:
702 // Non-null case is not handled on aarch64 but handled on x86
703 // FIXME: do we need to add it here?
704 assert(c->as_jobject() == nullptr, "should be");
705 if (UseCompressedOops && !wide) {
706 insn = &Assembler::strw;
707 } else {
708 insn = &Assembler::str;
709 }
710 break;
711 case T_CHAR:
712 case T_SHORT:
713 assert(c->as_jint() == 0, "should be");
714 insn = &Assembler::strh;
715 break;
716 case T_BOOLEAN:
717 case T_BYTE:
718 assert(c->as_jint() == 0, "should be");
719 insn = &Assembler::strb;
720 break;
721 default:
722 ShouldNotReachHere();
723 insn = &Assembler::str; // unreachable
724 }
725
726 if (info) add_debug_info_for_null_check_here(info);
727 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
728 }
729
730 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
731 assert(src->is_register(), "should not call otherwise");
732 assert(dest->is_register(), "should not call otherwise");
733
734 // move between cpu-registers
735 if (dest->is_single_cpu()) {
736 if (src->type() == T_LONG) {
737 // Can do LONG -> OBJECT
738 move_regs(src->as_register_lo(), dest->as_register());
739 return;
740 }
741 assert(src->is_single_cpu(), "must match");
742 if (src->type() == T_OBJECT) {
743 __ verify_oop(src->as_register());
744 }
745 move_regs(src->as_register(), dest->as_register());
746
747 } else if (dest->is_double_cpu()) {
748 if (is_reference_type(src->type())) {
749 // Surprising to me but we can see move of a long to t_object
750 __ verify_oop(src->as_register());
751 move_regs(src->as_register(), dest->as_register_lo());
752 return;
753 }
754 assert(src->is_double_cpu(), "must match");
755 Register f_lo = src->as_register_lo();
756 Register f_hi = src->as_register_hi();
757 Register t_lo = dest->as_register_lo();
758 Register t_hi = dest->as_register_hi();
759 assert(f_hi == f_lo, "must be same");
760 assert(t_hi == t_lo, "must be same");
761 move_regs(f_lo, t_lo);
762
763 } else if (dest->is_single_fpu()) {
764 __ fmovs(dest->as_float_reg(), src->as_float_reg());
765
766 } else if (dest->is_double_fpu()) {
767 __ fmovd(dest->as_double_reg(), src->as_double_reg());
768
769 } else {
770 ShouldNotReachHere();
771 }
772 }
773
774 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
775 precond(src->is_register() && dest->is_stack());
776
777 uint const c_sz32 = sizeof(uint32_t);
778 uint const c_sz64 = sizeof(uint64_t);
779
780 if (src->is_single_cpu()) {
781 int index = dest->single_stack_ix();
782 if (is_reference_type(type)) {
783 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
784 __ verify_oop(src->as_register());
785 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
786 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
787 } else {
788 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
789 }
790
791 } else if (src->is_double_cpu()) {
792 int index = dest->double_stack_ix();
793 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
794 __ str(src->as_register_lo(), dest_addr_LO);
795
796 } else if (src->is_single_fpu()) {
797 int index = dest->single_stack_ix();
798 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
799
800 } else if (src->is_double_fpu()) {
801 int index = dest->double_stack_ix();
802 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
803
804 } else {
805 ShouldNotReachHere();
806 }
807 }
808
809
810 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
811 LIR_Address* to_addr = dest->as_address_ptr();
812 PatchingStub* patch = nullptr;
813 Register compressed_src = rscratch1;
814
815 if (patch_code != lir_patch_none) {
816 deoptimize_trap(info);
817 return;
818 }
819
820 if (is_reference_type(type)) {
821 __ verify_oop(src->as_register());
822
823 if (UseCompressedOops && !wide) {
824 __ encode_heap_oop(compressed_src, src->as_register());
825 } else {
826 compressed_src = src->as_register();
827 }
828 }
829
830 int null_check_here = code_offset();
831 switch (type) {
832 case T_FLOAT: {
833 __ strs(src->as_float_reg(), as_Address(to_addr));
834 break;
835 }
836
837 case T_DOUBLE: {
838 __ strd(src->as_double_reg(), as_Address(to_addr));
839 break;
840 }
841
842 case T_ARRAY: // fall through
843 case T_OBJECT: // fall through
844 if (UseCompressedOops && !wide) {
845 __ strw(compressed_src, as_Address(to_addr, rscratch2));
846 } else {
847 __ str(compressed_src, as_Address(to_addr));
848 }
849 break;
850 case T_METADATA:
851 // We get here to store a method pointer to the stack to pass to
852 // a dtrace runtime call. This can't work on 64 bit with
853 // compressed klass ptrs: T_METADATA can be a compressed klass
854 // ptr or a 64 bit method pointer.
855 ShouldNotReachHere();
856 __ str(src->as_register(), as_Address(to_addr));
857 break;
858 case T_ADDRESS:
859 __ str(src->as_register(), as_Address(to_addr));
860 break;
861 case T_INT:
862 __ strw(src->as_register(), as_Address(to_addr));
863 break;
864
865 case T_LONG: {
866 __ str(src->as_register_lo(), as_Address_lo(to_addr));
867 break;
868 }
869
870 case T_BYTE: // fall through
871 case T_BOOLEAN: {
872 __ strb(src->as_register(), as_Address(to_addr));
873 break;
874 }
875
876 case T_CHAR: // fall through
877 case T_SHORT:
878 __ strh(src->as_register(), as_Address(to_addr));
879 break;
880
881 default:
882 ShouldNotReachHere();
883 }
884 if (info != nullptr) {
885 add_debug_info_for_null_check(null_check_here, info);
886 }
887 }
888
889
890 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
891 precond(src->is_stack() && dest->is_register());
892
893 uint const c_sz32 = sizeof(uint32_t);
894 uint const c_sz64 = sizeof(uint64_t);
895
896 if (dest->is_single_cpu()) {
897 int index = src->single_stack_ix();
898 if (is_reference_type(type)) {
899 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
900 __ verify_oop(dest->as_register());
901 } else if (type == T_METADATA || type == T_ADDRESS) {
902 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
903 } else {
904 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
905 }
906
907 } else if (dest->is_double_cpu()) {
908 int index = src->double_stack_ix();
909 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
910 __ ldr(dest->as_register_lo(), src_addr_LO);
911
912 } else if (dest->is_single_fpu()) {
913 int index = src->single_stack_ix();
914 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
915
916 } else if (dest->is_double_fpu()) {
917 int index = src->double_stack_ix();
918 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
919
920 } else {
921 ShouldNotReachHere();
922 }
923 }
924
925
926 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
927 address target = nullptr;
928 relocInfo::relocType reloc_type = relocInfo::none;
929
930 switch (patching_id(info)) {
931 case PatchingStub::access_field_id:
932 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
933 reloc_type = relocInfo::section_word_type;
934 break;
935 case PatchingStub::load_klass_id:
936 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
937 reloc_type = relocInfo::metadata_type;
938 break;
939 case PatchingStub::load_mirror_id:
940 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
941 reloc_type = relocInfo::oop_type;
942 break;
943 case PatchingStub::load_appendix_id:
944 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
945 reloc_type = relocInfo::oop_type;
946 break;
947 default: ShouldNotReachHere();
948 }
949
950 __ far_call(RuntimeAddress(target));
951 add_call_info_here(info);
952 }
953
954 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
955
956 LIR_Opr temp;
957 if (type == T_LONG || type == T_DOUBLE)
958 temp = FrameMap::rscratch1_long_opr;
959 else
960 temp = FrameMap::rscratch1_opr;
961
962 stack2reg(src, temp, src->type());
963 reg2stack(temp, dest, dest->type());
964 }
965
966
967 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
968 LIR_Address* addr = src->as_address_ptr();
969 LIR_Address* from_addr = src->as_address_ptr();
970
971 if (addr->base()->type() == T_OBJECT) {
972 __ verify_oop(addr->base()->as_pointer_register());
973 }
974
975 if (patch_code != lir_patch_none) {
976 deoptimize_trap(info);
977 return;
978 }
979
980 if (info != nullptr) {
981 add_debug_info_for_null_check_here(info);
982 }
983 int null_check_here = code_offset();
984 switch (type) {
985 case T_FLOAT: {
986 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
987 break;
988 }
989
990 case T_DOUBLE: {
991 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
992 break;
993 }
994
995 case T_ARRAY: // fall through
996 case T_OBJECT: // fall through
997 if (UseCompressedOops && !wide) {
998 __ ldrw(dest->as_register(), as_Address(from_addr));
999 } else {
1000 __ ldr(dest->as_register(), as_Address(from_addr));
1001 }
1002 break;
1003 case T_METADATA:
1004 // We get here to store a method pointer to the stack to pass to
1005 // a dtrace runtime call. This can't work on 64 bit with
1006 // compressed klass ptrs: T_METADATA can be a compressed klass
1007 // ptr or a 64 bit method pointer.
1008 ShouldNotReachHere();
1009 __ ldr(dest->as_register(), as_Address(from_addr));
1010 break;
1011 case T_ADDRESS:
1012 __ ldr(dest->as_register(), as_Address(from_addr));
1013 break;
1014 case T_INT:
1015 __ ldrw(dest->as_register(), as_Address(from_addr));
1016 break;
1017
1018 case T_LONG: {
1019 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1020 break;
1021 }
1022
1023 case T_BYTE:
1024 __ ldrsb(dest->as_register(), as_Address(from_addr));
1025 break;
1026 case T_BOOLEAN: {
1027 __ ldrb(dest->as_register(), as_Address(from_addr));
1028 break;
1029 }
1030
1031 case T_CHAR:
1032 __ ldrh(dest->as_register(), as_Address(from_addr));
1033 break;
1034 case T_SHORT:
1035 __ ldrsh(dest->as_register(), as_Address(from_addr));
1036 break;
1037
1038 default:
1039 ShouldNotReachHere();
1040 }
1041
1042 if (is_reference_type(type)) {
1043 if (UseCompressedOops && !wide) {
1044 __ decode_heap_oop(dest->as_register());
1045 }
1046
1047 __ verify_oop(dest->as_register());
1048 }
1049 }
1050
1051 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
1052 assert(dst->is_cpu_register(), "must be");
1053 assert(dst->type() == src->type(), "must be");
1054
1055 if (src->is_cpu_register()) {
1056 reg2reg(src, dst);
1057 } else if (src->is_stack()) {
1058 stack2reg(src, dst, dst->type());
1059 } else if (src->is_constant()) {
1060 const2reg(src, dst, lir_patch_none, nullptr);
1061 } else {
1062 ShouldNotReachHere();
1063 }
1064 }
1065
1066 int LIR_Assembler::array_element_size(BasicType type) const {
1067 int elem_size = type2aelembytes(type);
1068 return exact_log2(elem_size);
1069 }
1070
1071
1072 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1073 switch (op->code()) {
1074 case lir_idiv:
1075 case lir_irem:
1076 arithmetic_idiv(op->code(),
1077 op->in_opr1(),
1078 op->in_opr2(),
1079 op->in_opr3(),
1080 op->result_opr(),
1081 op->info());
1082 break;
1083 case lir_fmad:
1084 __ fmaddd(op->result_opr()->as_double_reg(),
1085 op->in_opr1()->as_double_reg(),
1086 op->in_opr2()->as_double_reg(),
1087 op->in_opr3()->as_double_reg());
1088 break;
1089 case lir_fmaf:
1090 __ fmadds(op->result_opr()->as_float_reg(),
1091 op->in_opr1()->as_float_reg(),
1092 op->in_opr2()->as_float_reg(),
1093 op->in_opr3()->as_float_reg());
1094 break;
1095 default: ShouldNotReachHere(); break;
1096 }
1097 }
1098
1099 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1100 #ifdef ASSERT
1101 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1102 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1103 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1104 #endif
1105
1106 if (op->cond() == lir_cond_always) {
1107 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1108 __ b(*(op->label()));
1109 } else {
1110 Assembler::Condition acond;
1111 if (op->code() == lir_cond_float_branch) {
1112 bool is_unordered = (op->ublock() == op->block());
1113 // Assembler::EQ does not permit unordered branches, so we add
1114 // another branch here. Likewise, Assembler::NE does not permit
1115 // ordered branches.
1116 if ((is_unordered && op->cond() == lir_cond_equal)
1117 || (!is_unordered && op->cond() == lir_cond_notEqual))
1118 __ br(Assembler::VS, *(op->ublock()->label()));
1119 switch(op->cond()) {
1120 case lir_cond_equal: acond = Assembler::EQ; break;
1121 case lir_cond_notEqual: acond = Assembler::NE; break;
1122 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1123 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1124 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1125 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1126 default: ShouldNotReachHere();
1127 acond = Assembler::EQ; // unreachable
1128 }
1129 } else {
1130 switch (op->cond()) {
1131 case lir_cond_equal: acond = Assembler::EQ; break;
1132 case lir_cond_notEqual: acond = Assembler::NE; break;
1133 case lir_cond_less: acond = Assembler::LT; break;
1134 case lir_cond_lessEqual: acond = Assembler::LE; break;
1135 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1136 case lir_cond_greater: acond = Assembler::GT; break;
1137 case lir_cond_belowEqual: acond = Assembler::LS; break;
1138 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1139 default: ShouldNotReachHere();
1140 acond = Assembler::EQ; // unreachable
1141 }
1142 }
1143 __ br(acond,*(op->label()));
1144 }
1145 }
1146
1147
1148
1149 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1150 LIR_Opr src = op->in_opr();
1151 LIR_Opr dest = op->result_opr();
1152
1153 switch (op->bytecode()) {
1154 case Bytecodes::_i2f:
1155 {
1156 __ scvtfws(dest->as_float_reg(), src->as_register());
1157 break;
1158 }
1159 case Bytecodes::_i2d:
1160 {
1161 __ scvtfwd(dest->as_double_reg(), src->as_register());
1162 break;
1163 }
1164 case Bytecodes::_l2d:
1165 {
1166 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1167 break;
1168 }
1169 case Bytecodes::_l2f:
1170 {
1171 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1172 break;
1173 }
1174 case Bytecodes::_f2d:
1175 {
1176 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1177 break;
1178 }
1179 case Bytecodes::_d2f:
1180 {
1181 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1182 break;
1183 }
1184 case Bytecodes::_i2c:
1185 {
1186 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1187 break;
1188 }
1189 case Bytecodes::_i2l:
1190 {
1191 __ sxtw(dest->as_register_lo(), src->as_register());
1192 break;
1193 }
1194 case Bytecodes::_i2s:
1195 {
1196 __ sxth(dest->as_register(), src->as_register());
1197 break;
1198 }
1199 case Bytecodes::_i2b:
1200 {
1201 __ sxtb(dest->as_register(), src->as_register());
1202 break;
1203 }
1204 case Bytecodes::_l2i:
1205 {
1206 _masm->block_comment("FIXME: This could be a no-op");
1207 __ uxtw(dest->as_register(), src->as_register_lo());
1208 break;
1209 }
1210 case Bytecodes::_d2l:
1211 {
1212 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1213 break;
1214 }
1215 case Bytecodes::_f2i:
1216 {
1217 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1218 break;
1219 }
1220 case Bytecodes::_f2l:
1221 {
1222 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1223 break;
1224 }
1225 case Bytecodes::_d2i:
1226 {
1227 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1228 break;
1229 }
1230 default: ShouldNotReachHere();
1231 }
1232 }
1233
1234 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1235 if (op->init_check()) {
1236 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1237 __ ldarb(rscratch1, rscratch1);
1238 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1239 add_debug_info_for_null_check_here(op->stub()->info());
1240 __ br(Assembler::NE, *op->stub()->entry());
1241 }
1242 __ allocate_object(op->obj()->as_register(),
1243 op->tmp1()->as_register(),
1244 op->tmp2()->as_register(),
1245 op->header_size(),
1246 op->object_size(),
1247 op->klass()->as_register(),
1248 *op->stub()->entry());
1249 __ bind(*op->stub()->continuation());
1250 }
1251
1252 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1253 Register len = op->len()->as_register();
1254 __ uxtw(len, len);
1255
1256 if (UseSlowPath || op->always_slow_path() ||
1257 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1258 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1259 __ b(*op->stub()->entry());
1260 } else {
1261 Register tmp1 = op->tmp1()->as_register();
1262 Register tmp2 = op->tmp2()->as_register();
1263 Register tmp3 = op->tmp3()->as_register();
1264 if (len == tmp1) {
1265 tmp1 = tmp3;
1266 } else if (len == tmp2) {
1267 tmp2 = tmp3;
1268 } else if (len == tmp3) {
1269 // everything is ok
1270 } else {
1271 __ mov(tmp3, len);
1272 }
1273 __ allocate_array(op->obj()->as_register(),
1274 len,
1275 tmp1,
1276 tmp2,
1277 arrayOopDesc::base_offset_in_bytes(op->type()),
1278 array_element_size(op->type()),
1279 op->klass()->as_register(),
1280 *op->stub()->entry(),
1281 op->zero_array());
1282 }
1283 __ bind(*op->stub()->continuation());
1284 }
1285
1286 void LIR_Assembler::type_profile_helper(Register mdo,
1287 ciMethodData *md, ciProfileData *data,
1288 Register recv, Label* update_done) {
1289
1290 // Given a profile data offset, generate an Address which points to
1291 // the corresponding slot in mdo->data().
1292 // Clobbers rscratch2.
1293 auto slot_at = [=](ByteSize offset) -> Address {
1294 return __ form_address(rscratch2, mdo,
1295 md->byte_offset_of_slot(data, offset),
1296 LogBytesPerWord);
1297 };
1298
1299 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1300 Label next_test;
1301 // See if the receiver is receiver[n].
1302 __ ldr(rscratch1, slot_at(ReceiverTypeData::receiver_offset(i)));
1303 __ cmp(recv, rscratch1);
1304 __ br(Assembler::NE, next_test);
1305 __ addptr(slot_at(ReceiverTypeData::receiver_count_offset(i)),
1306 DataLayout::counter_increment);
1307 __ b(*update_done);
1308 __ bind(next_test);
1309 }
1310
1311 // Didn't find receiver; find next empty slot and fill it in
1312 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1313 Label next_test;
1314 Address recv_addr(slot_at(ReceiverTypeData::receiver_offset(i)));
1315 __ ldr(rscratch1, recv_addr);
1316 __ cbnz(rscratch1, next_test);
1317 __ str(recv, recv_addr);
1318 __ mov(rscratch1, DataLayout::counter_increment);
1319 __ str(rscratch1, slot_at(ReceiverTypeData::receiver_count_offset(i)));
1320 __ b(*update_done);
1321 __ bind(next_test);
1322 }
1323 }
1324
1325 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1326 // we always need a stub for the failure case.
1327 CodeStub* stub = op->stub();
1328 Register obj = op->object()->as_register();
1329 Register k_RInfo = op->tmp1()->as_register();
1330 Register klass_RInfo = op->tmp2()->as_register();
1331 Register dst = op->result_opr()->as_register();
1332 ciKlass* k = op->klass();
1333 Register Rtmp1 = noreg;
1334
1335 // check if it needs to be profiled
1336 ciMethodData* md;
1337 ciProfileData* data;
1338
1339 const bool should_profile = op->should_profile();
1340
1341 if (should_profile) {
1342 ciMethod* method = op->profiled_method();
1343 assert(method != nullptr, "Should have method");
1344 int bci = op->profiled_bci();
1345 md = method->method_data_or_null();
1346 assert(md != nullptr, "Sanity");
1347 data = md->bci_to_data(bci);
1348 assert(data != nullptr, "need data for type check");
1349 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1350 }
1351 Label* success_target = success;
1352 Label* failure_target = failure;
1353
1354 if (obj == k_RInfo) {
1355 k_RInfo = dst;
1356 } else if (obj == klass_RInfo) {
1357 klass_RInfo = dst;
1358 }
1359 if (k->is_loaded() && !UseCompressedClassPointers) {
1360 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1361 } else {
1362 Rtmp1 = op->tmp3()->as_register();
1363 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1364 }
1365
1366 assert_different_registers(obj, k_RInfo, klass_RInfo);
1367
1368 if (op->need_null_check()) {
1369 if (should_profile) {
1370 Register mdo = klass_RInfo;
1371 __ mov_metadata(mdo, md->constant_encoding());
1372 Label not_null;
1373 __ cbnz(obj, not_null);
1374 // Object is null; update MDO and exit
1375 Address data_addr
1376 = __ form_address(rscratch2, mdo,
1377 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1378 0);
1379 __ ldrb(rscratch1, data_addr);
1380 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1381 __ strb(rscratch1, data_addr);
1382 __ b(*obj_is_null);
1383 __ bind(not_null);
1384
1385 Label update_done;
1386 Register recv = k_RInfo;
1387 __ load_klass(recv, obj);
1388 type_profile_helper(mdo, md, data, recv, &update_done);
1389 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1390 __ addptr(counter_addr, DataLayout::counter_increment);
1391
1392 __ bind(update_done);
1393 } else {
1394 __ cbz(obj, *obj_is_null);
1395 }
1396 }
1397
1398 if (!k->is_loaded()) {
1399 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1400 } else {
1401 __ mov_metadata(k_RInfo, k->constant_encoding());
1402 }
1403 __ verify_oop(obj);
1404
1405 if (op->fast_check()) {
1406 assert(!k->is_loaded() || !k->is_obj_array_klass(), "Use refined array for a direct pointer comparison");
1407 // get object class
1408 // not a safepoint as obj null check happens earlier
1409 __ load_klass(rscratch1, obj);
1410 __ cmp( rscratch1, k_RInfo);
1411
1412 __ br(Assembler::NE, *failure_target);
1413 // successful cast, fall through to profile or jump
1414 } else {
1415 // get object class
1416 // not a safepoint as obj null check happens earlier
1417 __ load_klass(klass_RInfo, obj);
1418 if (k->is_loaded()) {
1419 // See if we get an immediate positive hit
1420 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1421 __ cmp(k_RInfo, rscratch1);
1422 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1423 __ br(Assembler::NE, *failure_target);
1424 // successful cast, fall through to profile or jump
1425 } else {
1426 // See if we get an immediate positive hit
1427 __ br(Assembler::EQ, *success_target);
1428 // check for self
1429 if (k->is_loaded() && k->is_obj_array_klass()) {
1430 // For a direct pointer comparison, we need the refined array klass pointer
1431 ciKlass* k_refined = ciObjArrayKlass::make(k->as_obj_array_klass()->element_klass());
1432 __ mov_metadata(rscratch1, k_refined->constant_encoding());
1433 __ cmp(klass_RInfo, rscratch1);
1434 } else {
1435 __ cmp(klass_RInfo, k_RInfo);
1436 }
1437 __ br(Assembler::EQ, *success_target);
1438
1439 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1440 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1441 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1442 // result is a boolean
1443 __ cbzw(klass_RInfo, *failure_target);
1444 // successful cast, fall through to profile or jump
1445 }
1446 } else {
1447 // perform the fast part of the checking logic
1448 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1449 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1450 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1451 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1452 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1453 // result is a boolean
1454 __ cbz(k_RInfo, *failure_target);
1455 // successful cast, fall through to profile or jump
1456 }
1457 }
1458 __ b(*success);
1459 }
1460
1461
1462 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1463 const bool should_profile = op->should_profile();
1464
1465 LIR_Code code = op->code();
1466 if (code == lir_store_check) {
1467 Register value = op->object()->as_register();
1468 Register array = op->array()->as_register();
1469 Register k_RInfo = op->tmp1()->as_register();
1470 Register klass_RInfo = op->tmp2()->as_register();
1471 Register Rtmp1 = op->tmp3()->as_register();
1472
1473 CodeStub* stub = op->stub();
1474
1475 // check if it needs to be profiled
1476 ciMethodData* md;
1477 ciProfileData* data;
1478
1479 if (should_profile) {
1480 ciMethod* method = op->profiled_method();
1481 assert(method != nullptr, "Should have method");
1482 int bci = op->profiled_bci();
1483 md = method->method_data_or_null();
1484 assert(md != nullptr, "Sanity");
1485 data = md->bci_to_data(bci);
1486 assert(data != nullptr, "need data for type check");
1487 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1488 }
1489 Label done;
1490 Label* success_target = &done;
1491 Label* failure_target = stub->entry();
1492
1493 if (should_profile) {
1494 Label not_null;
1495 Register mdo = klass_RInfo;
1496 __ mov_metadata(mdo, md->constant_encoding());
1497 __ cbnz(value, not_null);
1498 // Object is null; update MDO and exit
1499 Address data_addr
1500 = __ form_address(rscratch2, mdo,
1501 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1502 __ ldrb(rscratch1, data_addr);
1503 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1504 __ strb(rscratch1, data_addr);
1505 __ b(done);
1506 __ bind(not_null);
1507
1508 Label update_done;
1509 Register recv = k_RInfo;
1510 __ load_klass(recv, value);
1511 type_profile_helper(mdo, md, data, recv, &update_done);
1512 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1513 __ addptr(counter_addr, DataLayout::counter_increment);
1514 __ bind(update_done);
1515 } else {
1516 __ cbz(value, done);
1517 }
1518
1519 add_debug_info_for_null_check_here(op->info_for_exception());
1520 __ load_klass(k_RInfo, array);
1521 __ load_klass(klass_RInfo, value);
1522
1523 // get instance klass (it's already uncompressed)
1524 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1525 // perform the fast part of the checking logic
1526 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1527 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1528 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1529 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1530 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1531 // result is a boolean
1532 __ cbzw(k_RInfo, *failure_target);
1533 // fall through to the success case
1534
1535 __ bind(done);
1536 } else if (code == lir_checkcast) {
1537 Register obj = op->object()->as_register();
1538 Register dst = op->result_opr()->as_register();
1539 Label success;
1540 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1541 __ bind(success);
1542 if (dst != obj) {
1543 __ mov(dst, obj);
1544 }
1545 } else if (code == lir_instanceof) {
1546 Register obj = op->object()->as_register();
1547 Register dst = op->result_opr()->as_register();
1548 Label success, failure, done;
1549 emit_typecheck_helper(op, &success, &failure, &failure);
1550 __ bind(failure);
1551 __ mov(dst, zr);
1552 __ b(done);
1553 __ bind(success);
1554 __ mov(dst, 1);
1555 __ bind(done);
1556 } else {
1557 ShouldNotReachHere();
1558 }
1559 }
1560
1561 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1562 // We are loading/storing from/to an array that *may* be a flat array (the
1563 // declared type is Object[], abstract[], interface[] or VT.ref[]).
1564 // If this array is a flat array, take the slow path.
1565 __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1566 if (!op->value()->is_illegal()) {
1567 // The array is not a flat array, but it might be null-free. If we are storing
1568 // a null into a null-free array, take the slow path (which will throw NPE).
1569 Label skip;
1570 __ cbnz(op->value()->as_register(), skip);
1571 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1572 __ bind(skip);
1573 }
1574 }
1575
1576 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1577 // We are storing into an array that *may* be null-free (the declared type is
1578 // Object[], abstract[], interface[] or VT.ref[]).
1579 Label test_mark_word;
1580 Register tmp = op->tmp()->as_register();
1581 __ ldr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
1582 __ tst(tmp, markWord::unlocked_value);
1583 __ br(Assembler::NE, test_mark_word);
1584 __ load_prototype_header(tmp, op->array()->as_register());
1585 __ bind(test_mark_word);
1586 __ tst(tmp, markWord::null_free_array_bit_in_place);
1587 }
1588
1589 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1590 Label L_oops_equal;
1591 Label L_oops_not_equal;
1592 Label L_end;
1593
1594 Register left = op->left()->as_register();
1595 Register right = op->right()->as_register();
1596
1597 __ cmp(left, right);
1598 __ br(Assembler::EQ, L_oops_equal);
1599
1600 // (1) Null check -- if one of the operands is null, the other must not be null (because
1601 // the two references are not equal), so they are not substitutable,
1602 // FIXME: do null check only if the operand is nullable
1603 {
1604 __ cbz(left, L_oops_not_equal);
1605 __ cbz(right, L_oops_not_equal);
1606 }
1607
1608 ciKlass* left_klass = op->left_klass();
1609 ciKlass* right_klass = op->right_klass();
1610
1611 // (2) Inline type check -- if either of the operands is not a inline type,
1612 // they are not substitutable. We do this only if we are not sure that the
1613 // operands are inline type
1614 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node.
1615 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
1616 Register tmp1 = op->tmp1()->as_register();
1617 __ mov(tmp1, markWord::inline_type_pattern);
1618 __ ldr(rscratch1, Address(left, oopDesc::mark_offset_in_bytes()));
1619 __ andr(tmp1, tmp1, rscratch1);
1620 __ ldr(rscratch1, Address(right, oopDesc::mark_offset_in_bytes()));
1621 __ andr(tmp1, tmp1, rscratch1);
1622 __ cmp(tmp1, (u1)markWord::inline_type_pattern);
1623 __ br(Assembler::NE, L_oops_not_equal);
1624 }
1625
1626 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
1627 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) {
1628 // No need to load klass -- the operands are statically known to be the same inline klass.
1629 __ b(*op->stub()->entry());
1630 } else {
1631 Register left_klass_op = op->left_klass_op()->as_register();
1632 Register right_klass_op = op->right_klass_op()->as_register();
1633
1634 if (UseCompressedClassPointers) {
1635 __ ldrw(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1636 __ ldrw(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1637 __ cmpw(left_klass_op, right_klass_op);
1638 } else {
1639 __ ldr(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1640 __ ldr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1641 __ cmp(left_klass_op, right_klass_op);
1642 }
1643
1644 __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check
1645 // fall through to L_oops_not_equal
1646 }
1647
1648 __ bind(L_oops_not_equal);
1649 move(op->not_equal_result(), op->result_opr());
1650 __ b(L_end);
1651
1652 __ bind(L_oops_equal);
1653 move(op->equal_result(), op->result_opr());
1654 __ b(L_end);
1655
1656 // We've returned from the stub. R0 contains 0x0 IFF the two
1657 // operands are not substitutable. (Don't compare against 0x1 in case the
1658 // C compiler is naughty)
1659 __ bind(*op->stub()->continuation());
1660 __ cbz(r0, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1661 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
1662 // fall-through
1663 __ bind(L_end);
1664 }
1665
1666
1667 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1668 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1669 __ cset(rscratch1, Assembler::NE);
1670 __ membar(__ AnyAny);
1671 }
1672
1673 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1674 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1675 __ cset(rscratch1, Assembler::NE);
1676 __ membar(__ AnyAny);
1677 }
1678
1679
1680 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1681 Register addr;
1682 if (op->addr()->is_register()) {
1683 addr = as_reg(op->addr());
1684 } else {
1685 assert(op->addr()->is_address(), "what else?");
1686 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1687 assert(addr_ptr->disp() == 0, "need 0 disp");
1688 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1689 addr = as_reg(addr_ptr->base());
1690 }
1691 Register newval = as_reg(op->new_value());
1692 Register cmpval = as_reg(op->cmp_value());
1693
1694 if (op->code() == lir_cas_obj) {
1695 if (UseCompressedOops) {
1696 Register t1 = op->tmp1()->as_register();
1697 assert(op->tmp1()->is_valid(), "must be");
1698 __ encode_heap_oop(t1, cmpval);
1699 cmpval = t1;
1700 __ encode_heap_oop(rscratch2, newval);
1701 newval = rscratch2;
1702 casw(addr, newval, cmpval);
1703 } else {
1704 casl(addr, newval, cmpval);
1705 }
1706 } else if (op->code() == lir_cas_int) {
1707 casw(addr, newval, cmpval);
1708 } else {
1709 casl(addr, newval, cmpval);
1710 }
1711 }
1712
1713
1714 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1715 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1716 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1717
1718 Assembler::Condition acond, ncond;
1719 switch (condition) {
1720 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1721 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1722 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1723 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1724 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1725 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1726 case lir_cond_belowEqual:
1727 case lir_cond_aboveEqual:
1728 default: ShouldNotReachHere();
1729 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1730 }
1731
1732 assert(result->is_single_cpu() || result->is_double_cpu(),
1733 "expect single register for result");
1734 if (opr1->is_constant() && opr2->is_constant()
1735 && opr1->type() == T_INT && opr2->type() == T_INT) {
1736 jint val1 = opr1->as_jint();
1737 jint val2 = opr2->as_jint();
1738 if (val1 == 0 && val2 == 1) {
1739 __ cset(result->as_register(), ncond);
1740 return;
1741 } else if (val1 == 1 && val2 == 0) {
1742 __ cset(result->as_register(), acond);
1743 return;
1744 }
1745 }
1746
1747 if (opr1->is_constant() && opr2->is_constant()
1748 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1749 jlong val1 = opr1->as_jlong();
1750 jlong val2 = opr2->as_jlong();
1751 if (val1 == 0 && val2 == 1) {
1752 __ cset(result->as_register_lo(), ncond);
1753 return;
1754 } else if (val1 == 1 && val2 == 0) {
1755 __ cset(result->as_register_lo(), acond);
1756 return;
1757 }
1758 }
1759
1760 if (opr1->is_stack()) {
1761 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1762 opr1 = FrameMap::rscratch1_opr;
1763 } else if (opr1->is_constant()) {
1764 LIR_Opr tmp
1765 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1766 const2reg(opr1, tmp, lir_patch_none, nullptr);
1767 opr1 = tmp;
1768 }
1769
1770 if (opr2->is_stack()) {
1771 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1772 opr2 = FrameMap::rscratch2_opr;
1773 } else if (opr2->is_constant()) {
1774 LIR_Opr tmp
1775 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1776 const2reg(opr2, tmp, lir_patch_none, nullptr);
1777 opr2 = tmp;
1778 }
1779
1780 if (result->type() == T_LONG)
1781 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1782 else
1783 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1784 }
1785
1786 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1787 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1788
1789 if (left->is_single_cpu()) {
1790 Register lreg = left->as_register();
1791 Register dreg = as_reg(dest);
1792
1793 if (right->is_single_cpu()) {
1794 // cpu register - cpu register
1795
1796 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1797 "should be");
1798 Register rreg = right->as_register();
1799 switch (code) {
1800 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1801 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1802 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1803 default: ShouldNotReachHere();
1804 }
1805
1806 } else if (right->is_double_cpu()) {
1807 Register rreg = right->as_register_lo();
1808 // single_cpu + double_cpu: can happen with obj+long
1809 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1810 switch (code) {
1811 case lir_add: __ add(dreg, lreg, rreg); break;
1812 case lir_sub: __ sub(dreg, lreg, rreg); break;
1813 default: ShouldNotReachHere();
1814 }
1815 } else if (right->is_constant()) {
1816 // cpu register - constant
1817 jlong c;
1818
1819 // FIXME. This is fugly: we really need to factor all this logic.
1820 switch(right->type()) {
1821 case T_LONG:
1822 c = right->as_constant_ptr()->as_jlong();
1823 break;
1824 case T_INT:
1825 case T_ADDRESS:
1826 c = right->as_constant_ptr()->as_jint();
1827 break;
1828 default:
1829 ShouldNotReachHere();
1830 c = 0; // unreachable
1831 break;
1832 }
1833
1834 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1835 if (c == 0 && dreg == lreg) {
1836 COMMENT("effective nop elided");
1837 return;
1838 }
1839 switch(left->type()) {
1840 case T_INT:
1841 switch (code) {
1842 case lir_add: __ addw(dreg, lreg, c); break;
1843 case lir_sub: __ subw(dreg, lreg, c); break;
1844 default: ShouldNotReachHere();
1845 }
1846 break;
1847 case T_OBJECT:
1848 case T_ADDRESS:
1849 switch (code) {
1850 case lir_add: __ add(dreg, lreg, c); break;
1851 case lir_sub: __ sub(dreg, lreg, c); break;
1852 default: ShouldNotReachHere();
1853 }
1854 break;
1855 default:
1856 ShouldNotReachHere();
1857 }
1858 } else {
1859 ShouldNotReachHere();
1860 }
1861
1862 } else if (left->is_double_cpu()) {
1863 Register lreg_lo = left->as_register_lo();
1864
1865 if (right->is_double_cpu()) {
1866 // cpu register - cpu register
1867 Register rreg_lo = right->as_register_lo();
1868 switch (code) {
1869 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1870 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1871 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1872 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1873 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1874 default:
1875 ShouldNotReachHere();
1876 }
1877
1878 } else if (right->is_constant()) {
1879 jlong c = right->as_constant_ptr()->as_jlong();
1880 Register dreg = as_reg(dest);
1881 switch (code) {
1882 case lir_add:
1883 case lir_sub:
1884 if (c == 0 && dreg == lreg_lo) {
1885 COMMENT("effective nop elided");
1886 return;
1887 }
1888 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1889 break;
1890 case lir_div:
1891 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1892 if (c == 1) {
1893 // move lreg_lo to dreg if divisor is 1
1894 __ mov(dreg, lreg_lo);
1895 } else {
1896 unsigned int shift = log2i_exact(c);
1897 // use rscratch1 as intermediate result register
1898 __ asr(rscratch1, lreg_lo, 63);
1899 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1900 __ asr(dreg, rscratch1, shift);
1901 }
1902 break;
1903 case lir_rem:
1904 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1905 if (c == 1) {
1906 // move 0 to dreg if divisor is 1
1907 __ mov(dreg, zr);
1908 } else {
1909 // use rscratch1 as intermediate result register
1910 __ negs(rscratch1, lreg_lo);
1911 __ andr(dreg, lreg_lo, c - 1);
1912 __ andr(rscratch1, rscratch1, c - 1);
1913 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1914 }
1915 break;
1916 default:
1917 ShouldNotReachHere();
1918 }
1919 } else {
1920 ShouldNotReachHere();
1921 }
1922 } else if (left->is_single_fpu()) {
1923 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1924 switch (code) {
1925 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1926 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1927 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1928 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1929 default:
1930 ShouldNotReachHere();
1931 }
1932 } else if (left->is_double_fpu()) {
1933 if (right->is_double_fpu()) {
1934 // fpu register - fpu register
1935 switch (code) {
1936 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1937 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1938 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1939 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1940 default:
1941 ShouldNotReachHere();
1942 }
1943 } else {
1944 if (right->is_constant()) {
1945 ShouldNotReachHere();
1946 }
1947 ShouldNotReachHere();
1948 }
1949 } else if (left->is_single_stack() || left->is_address()) {
1950 assert(left == dest, "left and dest must be equal");
1951 ShouldNotReachHere();
1952 } else {
1953 ShouldNotReachHere();
1954 }
1955 }
1956
1957 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1958 switch(code) {
1959 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1960 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1961 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1962 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1963 default : ShouldNotReachHere();
1964 }
1965 }
1966
1967 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1968
1969 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1970 Register Rleft = left->is_single_cpu() ? left->as_register() :
1971 left->as_register_lo();
1972 if (dst->is_single_cpu()) {
1973 Register Rdst = dst->as_register();
1974 if (right->is_constant()) {
1975 switch (code) {
1976 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1977 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1978 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1979 default: ShouldNotReachHere(); break;
1980 }
1981 } else {
1982 Register Rright = right->is_single_cpu() ? right->as_register() :
1983 right->as_register_lo();
1984 switch (code) {
1985 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1986 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1987 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1988 default: ShouldNotReachHere(); break;
1989 }
1990 }
1991 } else {
1992 Register Rdst = dst->as_register_lo();
1993 if (right->is_constant()) {
1994 switch (code) {
1995 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1996 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1997 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1998 default: ShouldNotReachHere(); break;
1999 }
2000 } else {
2001 Register Rright = right->is_single_cpu() ? right->as_register() :
2002 right->as_register_lo();
2003 switch (code) {
2004 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
2005 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
2006 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
2007 default: ShouldNotReachHere(); break;
2008 }
2009 }
2010 }
2011 }
2012
2013
2014
2015 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
2016
2017 // opcode check
2018 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
2019 bool is_irem = (code == lir_irem);
2020
2021 // operand check
2022 assert(left->is_single_cpu(), "left must be register");
2023 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2024 assert(result->is_single_cpu(), "result must be register");
2025 Register lreg = left->as_register();
2026 Register dreg = result->as_register();
2027
2028 // power-of-2 constant check and codegen
2029 if (right->is_constant()) {
2030 int c = right->as_constant_ptr()->as_jint();
2031 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
2032 if (is_irem) {
2033 if (c == 1) {
2034 // move 0 to dreg if divisor is 1
2035 __ movw(dreg, zr);
2036 } else {
2037 // use rscratch1 as intermediate result register
2038 __ negsw(rscratch1, lreg);
2039 __ andw(dreg, lreg, c - 1);
2040 __ andw(rscratch1, rscratch1, c - 1);
2041 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
2042 }
2043 } else {
2044 if (c == 1) {
2045 // move lreg to dreg if divisor is 1
2046 __ movw(dreg, lreg);
2047 } else {
2048 unsigned int shift = exact_log2(c);
2049 // use rscratch1 as intermediate result register
2050 __ asrw(rscratch1, lreg, 31);
2051 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
2052 __ asrw(dreg, rscratch1, shift);
2053 }
2054 }
2055 } else {
2056 Register rreg = right->as_register();
2057 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
2058 }
2059 }
2060
2061
2062 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2063 if (opr1->is_constant() && opr2->is_single_cpu()) {
2064 // tableswitch
2065 Register reg = as_reg(opr2);
2066 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
2067 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
2068 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
2069 Register reg1 = as_reg(opr1);
2070 if (opr2->is_single_cpu()) {
2071 // cpu register - cpu register
2072 Register reg2 = opr2->as_register();
2073 if (is_reference_type(opr1->type())) {
2074 __ cmpoop(reg1, reg2);
2075 } else {
2076 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2077 __ cmpw(reg1, reg2);
2078 }
2079 return;
2080 }
2081 if (opr2->is_double_cpu()) {
2082 // cpu register - cpu register
2083 Register reg2 = opr2->as_register_lo();
2084 __ cmp(reg1, reg2);
2085 return;
2086 }
2087
2088 if (opr2->is_constant()) {
2089 bool is_32bit = false; // width of register operand
2090 jlong imm;
2091
2092 switch(opr2->type()) {
2093 case T_INT:
2094 imm = opr2->as_constant_ptr()->as_jint();
2095 is_32bit = true;
2096 break;
2097 case T_LONG:
2098 imm = opr2->as_constant_ptr()->as_jlong();
2099 break;
2100 case T_ADDRESS:
2101 imm = opr2->as_constant_ptr()->as_jint();
2102 break;
2103 case T_METADATA:
2104 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
2105 break;
2106 case T_OBJECT:
2107 case T_ARRAY:
2108 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
2109 __ cmpoop(reg1, rscratch1);
2110 return;
2111 default:
2112 ShouldNotReachHere();
2113 imm = 0; // unreachable
2114 break;
2115 }
2116
2117 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
2118 if (is_32bit)
2119 __ cmpw(reg1, imm);
2120 else
2121 __ subs(zr, reg1, imm);
2122 return;
2123 } else {
2124 __ mov(rscratch1, imm);
2125 if (is_32bit)
2126 __ cmpw(reg1, rscratch1);
2127 else
2128 __ cmp(reg1, rscratch1);
2129 return;
2130 }
2131 } else
2132 ShouldNotReachHere();
2133 } else if (opr1->is_single_fpu()) {
2134 FloatRegister reg1 = opr1->as_float_reg();
2135 assert(opr2->is_single_fpu(), "expect single float register");
2136 FloatRegister reg2 = opr2->as_float_reg();
2137 __ fcmps(reg1, reg2);
2138 } else if (opr1->is_double_fpu()) {
2139 FloatRegister reg1 = opr1->as_double_reg();
2140 assert(opr2->is_double_fpu(), "expect double float register");
2141 FloatRegister reg2 = opr2->as_double_reg();
2142 __ fcmpd(reg1, reg2);
2143 } else {
2144 ShouldNotReachHere();
2145 }
2146 }
2147
2148 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2149 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2150 bool is_unordered_less = (code == lir_ucmp_fd2i);
2151 if (left->is_single_fpu()) {
2152 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2153 } else if (left->is_double_fpu()) {
2154 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2155 } else {
2156 ShouldNotReachHere();
2157 }
2158 } else if (code == lir_cmp_l2i) {
2159 Label done;
2160 __ cmp(left->as_register_lo(), right->as_register_lo());
2161 __ mov(dst->as_register(), (uint64_t)-1L);
2162 __ br(Assembler::LT, done);
2163 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2164 __ bind(done);
2165 } else {
2166 ShouldNotReachHere();
2167 }
2168 }
2169
2170
2171 void LIR_Assembler::align_call(LIR_Code code) { }
2172
2173
2174 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2175 address call = __ trampoline_call(Address(op->addr(), rtype));
2176 if (call == nullptr) {
2177 bailout("trampoline stub overflow");
2178 return;
2179 }
2180 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2181 __ post_call_nop();
2182 }
2183
2184
2185 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2186 address call = __ ic_call(op->addr());
2187 if (call == nullptr) {
2188 bailout("trampoline stub overflow");
2189 return;
2190 }
2191 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2192 __ post_call_nop();
2193 }
2194
2195 void LIR_Assembler::emit_static_call_stub() {
2196 address call_pc = __ pc();
2197 address stub = __ start_a_stub(call_stub_size());
2198 if (stub == nullptr) {
2199 bailout("static call stub overflow");
2200 return;
2201 }
2202
2203 int start = __ offset();
2204
2205 __ relocate(static_stub_Relocation::spec(call_pc));
2206 __ emit_static_call_stub();
2207
2208 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2209 <= call_stub_size(), "stub too big");
2210 __ end_a_stub();
2211 }
2212
2213
2214 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2215 assert(exceptionOop->as_register() == r0, "must match");
2216 assert(exceptionPC->as_register() == r3, "must match");
2217
2218 // exception object is not added to oop map by LinearScan
2219 // (LinearScan assumes that no oops are in fixed registers)
2220 info->add_register_oop(exceptionOop);
2221 StubId unwind_id;
2222
2223 // get current pc information
2224 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2225 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2226 // As no instructions have been generated yet for this LIR node it's
2227 // possible that an oop map already exists for the current offset.
2228 // In that case insert an dummy NOP here to ensure all oop map PCs
2229 // are unique. See JDK-8237483.
2230 __ nop();
2231 }
2232 int pc_for_athrow_offset = __ offset();
2233 InternalAddress pc_for_athrow(__ pc());
2234 __ adr(exceptionPC->as_register(), pc_for_athrow);
2235 add_call_info(pc_for_athrow_offset, info); // for exception handler
2236
2237 __ verify_not_null_oop(r0);
2238 // search an exception handler (r0: exception oop, r3: throwing pc)
2239 if (compilation()->has_fpu_code()) {
2240 unwind_id = StubId::c1_handle_exception_id;
2241 } else {
2242 unwind_id = StubId::c1_handle_exception_nofpu_id;
2243 }
2244 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2245
2246 // FIXME: enough room for two byte trap ????
2247 __ nop();
2248 }
2249
2250
2251 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2252 assert(exceptionOop->as_register() == r0, "must match");
2253
2254 __ b(_unwind_handler_entry);
2255 }
2256
2257
2258 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2259 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2260 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2261
2262 switch (left->type()) {
2263 case T_INT: {
2264 switch (code) {
2265 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2266 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2267 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2268 default:
2269 ShouldNotReachHere();
2270 break;
2271 }
2272 break;
2273 case T_LONG:
2274 case T_ADDRESS:
2275 case T_OBJECT:
2276 switch (code) {
2277 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2278 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2279 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2280 default:
2281 ShouldNotReachHere();
2282 break;
2283 }
2284 break;
2285 default:
2286 ShouldNotReachHere();
2287 break;
2288 }
2289 }
2290 }
2291
2292
2293 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2294 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2295 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2296
2297 switch (left->type()) {
2298 case T_INT: {
2299 switch (code) {
2300 case lir_shl: __ lslw (dreg, lreg, count); break;
2301 case lir_shr: __ asrw (dreg, lreg, count); break;
2302 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2303 default:
2304 ShouldNotReachHere();
2305 break;
2306 }
2307 break;
2308 case T_LONG:
2309 case T_ADDRESS:
2310 case T_OBJECT:
2311 switch (code) {
2312 case lir_shl: __ lsl (dreg, lreg, count); break;
2313 case lir_shr: __ asr (dreg, lreg, count); break;
2314 case lir_ushr: __ lsr (dreg, lreg, count); break;
2315 default:
2316 ShouldNotReachHere();
2317 break;
2318 }
2319 break;
2320 default:
2321 ShouldNotReachHere();
2322 break;
2323 }
2324 }
2325 }
2326
2327
2328 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2329 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2330 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2331 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2332 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2333 }
2334
2335
2336 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2337 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2338 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2339 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2340 __ mov (rscratch1, c);
2341 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2342 }
2343
2344
2345 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2346 ShouldNotReachHere();
2347 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2348 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2349 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2350 __ lea(rscratch1, __ constant_oop_address(o));
2351 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2352 }
2353
2354 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
2355 if (null_check) {
2356 __ cbz(obj, *slow_path->entry());
2357 }
2358 if (is_dest) {
2359 __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
2360 // TODO 8350865 Flat no longer implies null-free, so we need to check for flat dest. Can we do better here?
2361 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2362 } else {
2363 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2364 }
2365 }
2366
2367 // This code replaces a call to arraycopy; no exception may
2368 // be thrown in this code, they must be thrown in the System.arraycopy
2369 // activation frame; we could save some checks if this would not be the case
2370 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2371 ciArrayKlass* default_type = op->expected_type();
2372 Register src = op->src()->as_register();
2373 Register dst = op->dst()->as_register();
2374 Register src_pos = op->src_pos()->as_register();
2375 Register dst_pos = op->dst_pos()->as_register();
2376 Register length = op->length()->as_register();
2377 Register tmp = op->tmp()->as_register();
2378
2379 CodeStub* stub = op->stub();
2380 int flags = op->flags();
2381 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2382 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2383
2384 if (flags & LIR_OpArrayCopy::always_slow_path) {
2385 __ b(*stub->entry());
2386 __ bind(*stub->continuation());
2387 return;
2388 }
2389
2390 // if we don't know anything, just go through the generic arraycopy
2391 if (default_type == nullptr // || basic_type == T_OBJECT
2392 ) {
2393 Label done;
2394 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2395
2396 // Save the arguments in case the generic arraycopy fails and we
2397 // have to fall back to the JNI stub
2398 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2399 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2400 __ str(src, Address(sp, 4*BytesPerWord));
2401
2402 address copyfunc_addr = StubRoutines::generic_arraycopy();
2403 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2404
2405 // The arguments are in java calling convention so we shift them
2406 // to C convention
2407 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2408 __ mov(c_rarg0, j_rarg0);
2409 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2410 __ mov(c_rarg1, j_rarg1);
2411 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2412 __ mov(c_rarg2, j_rarg2);
2413 assert_different_registers(c_rarg3, j_rarg4);
2414 __ mov(c_rarg3, j_rarg3);
2415 __ mov(c_rarg4, j_rarg4);
2416 #ifndef PRODUCT
2417 if (PrintC1Statistics) {
2418 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2419 }
2420 #endif
2421 __ far_call(RuntimeAddress(copyfunc_addr));
2422
2423 __ cbz(r0, *stub->continuation());
2424
2425 // Reload values from the stack so they are where the stub
2426 // expects them.
2427 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2428 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2429 __ ldr(src, Address(sp, 4*BytesPerWord));
2430
2431 // r0 is -1^K where K == partial copied count
2432 __ eonw(rscratch1, r0, zr);
2433 // adjust length down and src/end pos up by partial copied count
2434 __ subw(length, length, rscratch1);
2435 __ addw(src_pos, src_pos, rscratch1);
2436 __ addw(dst_pos, dst_pos, rscratch1);
2437 __ b(*stub->entry());
2438
2439 __ bind(*stub->continuation());
2440 return;
2441 }
2442
2443 // Handle inline type arrays
2444 if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
2445 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
2446 }
2447 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
2448 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
2449 }
2450
2451 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2452
2453 int elem_size = type2aelembytes(basic_type);
2454 int scale = exact_log2(elem_size);
2455
2456 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2457 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2458
2459 // test for null
2460 if (flags & LIR_OpArrayCopy::src_null_check) {
2461 __ cbz(src, *stub->entry());
2462 }
2463 if (flags & LIR_OpArrayCopy::dst_null_check) {
2464 __ cbz(dst, *stub->entry());
2465 }
2466
2467 // If the compiler was not able to prove that exact type of the source or the destination
2468 // of the arraycopy is an array type, check at runtime if the source or the destination is
2469 // an instance type.
2470 if (flags & LIR_OpArrayCopy::type_check) {
2471 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2472 __ load_klass(tmp, dst);
2473 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2474 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2475 __ br(Assembler::GE, *stub->entry());
2476 }
2477
2478 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2479 __ load_klass(tmp, src);
2480 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2481 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2482 __ br(Assembler::GE, *stub->entry());
2483 }
2484 }
2485
2486 // check if negative
2487 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2488 __ cmpw(src_pos, 0);
2489 __ br(Assembler::LT, *stub->entry());
2490 }
2491 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2492 __ cmpw(dst_pos, 0);
2493 __ br(Assembler::LT, *stub->entry());
2494 }
2495
2496 if (flags & LIR_OpArrayCopy::length_positive_check) {
2497 __ cmpw(length, 0);
2498 __ br(Assembler::LT, *stub->entry());
2499 }
2500
2501 if (flags & LIR_OpArrayCopy::src_range_check) {
2502 __ addw(tmp, src_pos, length);
2503 __ ldrw(rscratch1, src_length_addr);
2504 __ cmpw(tmp, rscratch1);
2505 __ br(Assembler::HI, *stub->entry());
2506 }
2507 if (flags & LIR_OpArrayCopy::dst_range_check) {
2508 __ addw(tmp, dst_pos, length);
2509 __ ldrw(rscratch1, dst_length_addr);
2510 __ cmpw(tmp, rscratch1);
2511 __ br(Assembler::HI, *stub->entry());
2512 }
2513
2514 if (flags & LIR_OpArrayCopy::type_check) {
2515 // We don't know the array types are compatible
2516 if (basic_type != T_OBJECT) {
2517 // Simple test for basic type arrays
2518 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2519 __ br(Assembler::NE, *stub->entry());
2520 } else {
2521 // For object arrays, if src is a sub class of dst then we can
2522 // safely do the copy.
2523 Label cont, slow;
2524
2525 #define PUSH(r1, r2) \
2526 stp(r1, r2, __ pre(sp, -2 * wordSize));
2527
2528 #define POP(r1, r2) \
2529 ldp(r1, r2, __ post(sp, 2 * wordSize));
2530
2531 __ PUSH(src, dst);
2532
2533 __ load_klass(src, src);
2534 __ load_klass(dst, dst);
2535
2536 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2537
2538 __ PUSH(src, dst);
2539 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2540 __ POP(src, dst);
2541
2542 __ cbnz(src, cont);
2543
2544 __ bind(slow);
2545 __ POP(src, dst);
2546
2547 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2548 if (copyfunc_addr != nullptr) { // use stub if available
2549 // src is not a sub class of dst so we have to do a
2550 // per-element check.
2551
2552 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2553 if ((flags & mask) != mask) {
2554 // Check that at least both of them object arrays.
2555 assert(flags & mask, "one of the two should be known to be an object array");
2556
2557 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2558 __ load_klass(tmp, src);
2559 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2560 __ load_klass(tmp, dst);
2561 }
2562 int lh_offset = in_bytes(Klass::layout_helper_offset());
2563 Address klass_lh_addr(tmp, lh_offset);
2564 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2565 __ ldrw(rscratch1, klass_lh_addr);
2566 __ mov(rscratch2, objArray_lh);
2567 __ eorw(rscratch1, rscratch1, rscratch2);
2568 __ cbnzw(rscratch1, *stub->entry());
2569 }
2570
2571 // Spill because stubs can use any register they like and it's
2572 // easier to restore just those that we care about.
2573 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2574 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2575 __ str(src, Address(sp, 4*BytesPerWord));
2576
2577 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2578 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2579 assert_different_registers(c_rarg0, dst, dst_pos, length);
2580 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2581 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2582 assert_different_registers(c_rarg1, dst, length);
2583 __ uxtw(c_rarg2, length);
2584 assert_different_registers(c_rarg2, dst);
2585
2586 __ load_klass(c_rarg4, dst);
2587 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2588 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2589 __ far_call(RuntimeAddress(copyfunc_addr));
2590
2591 #ifndef PRODUCT
2592 if (PrintC1Statistics) {
2593 Label failed;
2594 __ cbnz(r0, failed);
2595 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2596 __ bind(failed);
2597 }
2598 #endif
2599
2600 __ cbz(r0, *stub->continuation());
2601
2602 #ifndef PRODUCT
2603 if (PrintC1Statistics) {
2604 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2605 }
2606 #endif
2607 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2608
2609 // Restore previously spilled arguments
2610 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2611 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2612 __ ldr(src, Address(sp, 4*BytesPerWord));
2613
2614 // return value is -1^K where K is partial copied count
2615 __ eonw(rscratch1, r0, zr);
2616 // adjust length down and src/end pos up by partial copied count
2617 __ subw(length, length, rscratch1);
2618 __ addw(src_pos, src_pos, rscratch1);
2619 __ addw(dst_pos, dst_pos, rscratch1);
2620 }
2621
2622 __ b(*stub->entry());
2623
2624 __ bind(cont);
2625 __ POP(src, dst);
2626 }
2627 }
2628
2629 #ifdef ASSERT
2630 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2631 // Sanity check the known type with the incoming class. For the
2632 // primitive case the types must match exactly with src.klass and
2633 // dst.klass each exactly matching the default type. For the
2634 // object array case, if no type check is needed then either the
2635 // dst type is exactly the expected type and the src type is a
2636 // subtype which we can't check or src is the same array as dst
2637 // but not necessarily exactly of type default_type.
2638 Label known_ok, halt;
2639 __ mov_metadata(tmp, default_type->constant_encoding());
2640
2641 if (basic_type != T_OBJECT) {
2642 __ cmp_klass(dst, tmp, rscratch1);
2643 __ br(Assembler::NE, halt);
2644 __ cmp_klass(src, tmp, rscratch1);
2645 __ br(Assembler::EQ, known_ok);
2646 } else {
2647 __ cmp_klass(dst, tmp, rscratch1);
2648 __ br(Assembler::EQ, known_ok);
2649 __ cmp(src, dst);
2650 __ br(Assembler::EQ, known_ok);
2651 }
2652 __ bind(halt);
2653 __ stop("incorrect type information in arraycopy");
2654 __ bind(known_ok);
2655 }
2656 #endif
2657
2658 #ifndef PRODUCT
2659 if (PrintC1Statistics) {
2660 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2661 }
2662 #endif
2663
2664 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2665 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2666 assert_different_registers(c_rarg0, dst, dst_pos, length);
2667 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2668 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2669 assert_different_registers(c_rarg1, dst, length);
2670 __ uxtw(c_rarg2, length);
2671 assert_different_registers(c_rarg2, dst);
2672
2673 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2674 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2675 const char *name;
2676 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2677
2678 CodeBlob *cb = CodeCache::find_blob(entry);
2679 if (cb) {
2680 __ far_call(RuntimeAddress(entry));
2681 } else {
2682 __ call_VM_leaf(entry, 3);
2683 }
2684
2685 if (stub != nullptr) {
2686 __ bind(*stub->continuation());
2687 }
2688 }
2689
2690
2691
2692
2693 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2694 Register obj = op->obj_opr()->as_register(); // may not be an oop
2695 Register hdr = op->hdr_opr()->as_register();
2696 Register lock = op->lock_opr()->as_register();
2697 Register temp = op->scratch_opr()->as_register();
2698 if (op->code() == lir_lock) {
2699 // add debug info for NullPointerException only if one is possible
2700 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2701 if (op->info() != nullptr) {
2702 add_debug_info_for_null_check(null_check_offset, op->info());
2703 }
2704 // done
2705 } else if (op->code() == lir_unlock) {
2706 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2707 } else {
2708 Unimplemented();
2709 }
2710 __ bind(*op->stub()->continuation());
2711 }
2712
2713 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2714 Register obj = op->obj()->as_pointer_register();
2715 Register result = op->result_opr()->as_pointer_register();
2716
2717 CodeEmitInfo* info = op->info();
2718 if (info != nullptr) {
2719 add_debug_info_for_null_check_here(info);
2720 }
2721
2722 __ load_klass(result, obj);
2723 }
2724
2725 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2726 ciMethod* method = op->profiled_method();
2727 int bci = op->profiled_bci();
2728 ciMethod* callee = op->profiled_callee();
2729
2730 // Update counter for all call types
2731 ciMethodData* md = method->method_data_or_null();
2732 assert(md != nullptr, "Sanity");
2733 ciProfileData* data = md->bci_to_data(bci);
2734 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2735 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2736 Register mdo = op->mdo()->as_register();
2737 __ mov_metadata(mdo, md->constant_encoding());
2738 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2739 // Perform additional virtual call profiling for invokevirtual and
2740 // invokeinterface bytecodes
2741 if (op->should_profile_receiver_type()) {
2742 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2743 Register recv = op->recv()->as_register();
2744 assert_different_registers(mdo, recv);
2745 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2746 ciKlass* known_klass = op->known_holder();
2747 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2748 // We know the type that will be seen at this call site; we can
2749 // statically update the MethodData* rather than needing to do
2750 // dynamic tests on the receiver type
2751
2752 // NOTE: we should probably put a lock around this search to
2753 // avoid collisions by concurrent compilations
2754 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2755 uint i;
2756 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2757 ciKlass* receiver = vc_data->receiver(i);
2758 if (known_klass->equals(receiver)) {
2759 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2760 __ addptr(data_addr, DataLayout::counter_increment);
2761 return;
2762 }
2763 }
2764
2765 // Receiver type not found in profile data; select an empty slot
2766
2767 // Note that this is less efficient than it should be because it
2768 // always does a write to the receiver part of the
2769 // VirtualCallData rather than just the first time
2770 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2771 ciKlass* receiver = vc_data->receiver(i);
2772 if (receiver == nullptr) {
2773 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2774 Address recv_addr =
2775 __ form_address(rscratch2, mdo,
2776 md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)),
2777 LogBytesPerWord);
2778 __ str(rscratch1, recv_addr);
2779 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2780 __ addptr(data_addr, DataLayout::counter_increment);
2781 return;
2782 }
2783 }
2784 } else {
2785 __ load_klass(recv, recv);
2786 Label update_done;
2787 type_profile_helper(mdo, md, data, recv, &update_done);
2788 // Receiver did not match any saved receiver and there is no empty row for it.
2789 // Increment total counter to indicate polymorphic case.
2790 __ addptr(counter_addr, DataLayout::counter_increment);
2791
2792 __ bind(update_done);
2793 }
2794 } else {
2795 // Static call
2796 __ addptr(counter_addr, DataLayout::counter_increment);
2797 }
2798 }
2799
2800
2801 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2802 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2803 }
2804
2805 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2806 assert(op->crc()->is_single_cpu(), "crc must be register");
2807 assert(op->val()->is_single_cpu(), "byte value must be register");
2808 assert(op->result_opr()->is_single_cpu(), "result must be register");
2809 Register crc = op->crc()->as_register();
2810 Register val = op->val()->as_register();
2811 Register res = op->result_opr()->as_register();
2812
2813 assert_different_registers(val, crc, res);
2814 uint64_t offset;
2815 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2816 __ add(res, res, offset);
2817
2818 __ mvnw(crc, crc); // ~crc
2819 __ update_byte_crc32(crc, val, res);
2820 __ mvnw(res, crc); // ~crc
2821 }
2822
2823 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2824 COMMENT("emit_profile_type {");
2825 Register obj = op->obj()->as_register();
2826 Register tmp = op->tmp()->as_pointer_register();
2827 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2828 ciKlass* exact_klass = op->exact_klass();
2829 intptr_t current_klass = op->current_klass();
2830 bool not_null = op->not_null();
2831 bool no_conflict = op->no_conflict();
2832
2833 Label update, next, none;
2834
2835 bool do_null = !not_null;
2836 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2837 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2838
2839 assert(do_null || do_update, "why are we here?");
2840 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2841 assert(mdo_addr.base() != rscratch1, "wrong register");
2842
2843 __ verify_oop(obj);
2844
2845 if (tmp != obj) {
2846 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2847 __ mov(tmp, obj);
2848 } else {
2849 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2850 }
2851 if (do_null) {
2852 __ cbnz(tmp, update);
2853 if (!TypeEntries::was_null_seen(current_klass)) {
2854 __ ldr(rscratch2, mdo_addr);
2855 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2856 __ str(rscratch2, mdo_addr);
2857 }
2858 if (do_update) {
2859 #ifndef ASSERT
2860 __ b(next);
2861 }
2862 #else
2863 __ b(next);
2864 }
2865 } else {
2866 __ cbnz(tmp, update);
2867 __ stop("unexpected null obj");
2868 #endif
2869 }
2870
2871 __ bind(update);
2872
2873 if (do_update) {
2874 #ifdef ASSERT
2875 if (exact_klass != nullptr) {
2876 Label ok;
2877 __ load_klass(tmp, tmp);
2878 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2879 __ eor(rscratch1, tmp, rscratch1);
2880 __ cbz(rscratch1, ok);
2881 __ stop("exact klass and actual klass differ");
2882 __ bind(ok);
2883 }
2884 #endif
2885 if (!no_conflict) {
2886 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2887 if (exact_klass != nullptr) {
2888 __ mov_metadata(tmp, exact_klass->constant_encoding());
2889 } else {
2890 __ load_klass(tmp, tmp);
2891 }
2892
2893 __ ldr(rscratch2, mdo_addr);
2894 __ eor(tmp, tmp, rscratch2);
2895 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2896 // klass seen before, nothing to do. The unknown bit may have been
2897 // set already but no need to check.
2898 __ cbz(rscratch1, next);
2899
2900 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2901
2902 if (TypeEntries::is_type_none(current_klass)) {
2903 __ cbz(rscratch2, none);
2904 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2905 __ br(Assembler::EQ, none);
2906 // There is a chance that the checks above
2907 // fail if another thread has just set the
2908 // profiling to this obj's klass
2909 __ dmb(Assembler::ISHLD);
2910 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2911 __ ldr(rscratch2, mdo_addr);
2912 __ eor(tmp, tmp, rscratch2);
2913 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2914 __ cbz(rscratch1, next);
2915 }
2916 } else {
2917 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2918 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2919
2920 __ ldr(tmp, mdo_addr);
2921 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2922 }
2923
2924 // different than before. Cannot keep accurate profile.
2925 __ ldr(rscratch2, mdo_addr);
2926 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2927 __ str(rscratch2, mdo_addr);
2928
2929 if (TypeEntries::is_type_none(current_klass)) {
2930 __ b(next);
2931
2932 __ bind(none);
2933 // first time here. Set profile type.
2934 __ str(tmp, mdo_addr);
2935 #ifdef ASSERT
2936 __ andr(tmp, tmp, TypeEntries::type_mask);
2937 __ verify_klass_ptr(tmp);
2938 #endif
2939 }
2940 } else {
2941 // There's a single possible klass at this profile point
2942 assert(exact_klass != nullptr, "should be");
2943 if (TypeEntries::is_type_none(current_klass)) {
2944 __ mov_metadata(tmp, exact_klass->constant_encoding());
2945 __ ldr(rscratch2, mdo_addr);
2946 __ eor(tmp, tmp, rscratch2);
2947 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2948 __ cbz(rscratch1, next);
2949 #ifdef ASSERT
2950 {
2951 Label ok;
2952 __ ldr(rscratch1, mdo_addr);
2953 __ cbz(rscratch1, ok);
2954 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2955 __ br(Assembler::EQ, ok);
2956 // may have been set by another thread
2957 __ dmb(Assembler::ISHLD);
2958 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2959 __ ldr(rscratch2, mdo_addr);
2960 __ eor(rscratch2, rscratch1, rscratch2);
2961 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2962 __ cbz(rscratch2, ok);
2963
2964 __ stop("unexpected profiling mismatch");
2965 __ bind(ok);
2966 }
2967 #endif
2968 // first time here. Set profile type.
2969 __ str(tmp, mdo_addr);
2970 #ifdef ASSERT
2971 __ andr(tmp, tmp, TypeEntries::type_mask);
2972 __ verify_klass_ptr(tmp);
2973 #endif
2974 } else {
2975 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2976 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2977
2978 __ ldr(tmp, mdo_addr);
2979 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2980
2981 __ orr(tmp, tmp, TypeEntries::type_unknown);
2982 __ str(tmp, mdo_addr);
2983 // FIXME: Write barrier needed here?
2984 }
2985 }
2986
2987 __ bind(next);
2988 }
2989 COMMENT("} emit_profile_type");
2990 }
2991
2992 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
2993 Register obj = op->obj()->as_register();
2994 Register tmp = op->tmp()->as_pointer_register();
2995 bool not_null = op->not_null();
2996 int flag = op->flag();
2997
2998 Label not_inline_type;
2999 if (!not_null) {
3000 __ cbz(obj, not_inline_type);
3001 }
3002
3003 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
3004
3005 Address mdo_addr = as_Address(op->mdp()->as_address_ptr(), rscratch2);
3006 __ ldrb(rscratch1, mdo_addr);
3007 __ orr(rscratch1, rscratch1, flag);
3008 __ strb(rscratch1, mdo_addr);
3009
3010 __ bind(not_inline_type);
3011 }
3012
3013 void LIR_Assembler::align_backward_branch_target() {
3014 }
3015
3016
3017 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3018 // tmp must be unused
3019 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3020
3021 if (left->is_single_cpu()) {
3022 assert(dest->is_single_cpu(), "expect single result reg");
3023 __ negw(dest->as_register(), left->as_register());
3024 } else if (left->is_double_cpu()) {
3025 assert(dest->is_double_cpu(), "expect double result reg");
3026 __ neg(dest->as_register_lo(), left->as_register_lo());
3027 } else if (left->is_single_fpu()) {
3028 assert(dest->is_single_fpu(), "expect single float result reg");
3029 __ fnegs(dest->as_float_reg(), left->as_float_reg());
3030 } else {
3031 assert(left->is_double_fpu(), "expect double float operand reg");
3032 assert(dest->is_double_fpu(), "expect double float result reg");
3033 __ fnegd(dest->as_double_reg(), left->as_double_reg());
3034 }
3035 }
3036
3037
3038 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3039 if (patch_code != lir_patch_none) {
3040 deoptimize_trap(info);
3041 return;
3042 }
3043
3044 __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
3045 }
3046
3047
3048 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3049 assert(!tmp->is_valid(), "don't need temporary");
3050
3051 CodeBlob *cb = CodeCache::find_blob(dest);
3052 if (cb) {
3053 __ far_call(RuntimeAddress(dest));
3054 } else {
3055 __ mov(rscratch1, RuntimeAddress(dest));
3056 __ blr(rscratch1);
3057 }
3058
3059 if (info != nullptr) {
3060 add_call_info_here(info);
3061 }
3062 __ post_call_nop();
3063 }
3064
3065 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3066 if (dest->is_address() || src->is_address()) {
3067 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
3068 } else {
3069 ShouldNotReachHere();
3070 }
3071 }
3072
3073 #ifdef ASSERT
3074 // emit run-time assertion
3075 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3076 assert(op->code() == lir_assert, "must be");
3077
3078 if (op->in_opr1()->is_valid()) {
3079 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3080 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3081 } else {
3082 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3083 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3084 }
3085
3086 Label ok;
3087 if (op->condition() != lir_cond_always) {
3088 Assembler::Condition acond = Assembler::AL;
3089 switch (op->condition()) {
3090 case lir_cond_equal: acond = Assembler::EQ; break;
3091 case lir_cond_notEqual: acond = Assembler::NE; break;
3092 case lir_cond_less: acond = Assembler::LT; break;
3093 case lir_cond_lessEqual: acond = Assembler::LE; break;
3094 case lir_cond_greaterEqual: acond = Assembler::GE; break;
3095 case lir_cond_greater: acond = Assembler::GT; break;
3096 case lir_cond_belowEqual: acond = Assembler::LS; break;
3097 case lir_cond_aboveEqual: acond = Assembler::HS; break;
3098 default: ShouldNotReachHere();
3099 }
3100 __ br(acond, ok);
3101 }
3102 if (op->halt()) {
3103 const char* str = __ code_string(op->msg());
3104 __ stop(str);
3105 } else {
3106 breakpoint();
3107 }
3108 __ bind(ok);
3109 }
3110 #endif
3111
3112 #ifndef PRODUCT
3113 #define COMMENT(x) do { __ block_comment(x); } while (0)
3114 #else
3115 #define COMMENT(x)
3116 #endif
3117
3118 void LIR_Assembler::membar() {
3119 COMMENT("membar");
3120 __ membar(MacroAssembler::AnyAny);
3121 }
3122
3123 void LIR_Assembler::membar_acquire() {
3124 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
3125 }
3126
3127 void LIR_Assembler::membar_release() {
3128 __ membar(Assembler::LoadStore|Assembler::StoreStore);
3129 }
3130
3131 void LIR_Assembler::membar_loadload() {
3132 __ membar(Assembler::LoadLoad);
3133 }
3134
3135 void LIR_Assembler::membar_storestore() {
3136 __ membar(MacroAssembler::StoreStore);
3137 }
3138
3139 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3140
3141 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3142
3143 void LIR_Assembler::on_spin_wait() {
3144 __ spin_wait();
3145 }
3146
3147 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3148 __ mov(result_reg->as_register(), rthread);
3149 }
3150
3151 void LIR_Assembler::check_orig_pc() {
3152 __ ldr(rscratch2, frame_map()->address_for_orig_pc_addr());
3153 __ cmp(rscratch2, (u1)NULL_WORD);
3154 }
3155
3156 void LIR_Assembler::peephole(LIR_List *lir) {
3157 #if 0
3158 if (tableswitch_count >= max_tableswitches)
3159 return;
3160
3161 /*
3162 This finite-state automaton recognizes sequences of compare-and-
3163 branch instructions. We will turn them into a tableswitch. You
3164 could argue that C1 really shouldn't be doing this sort of
3165 optimization, but without it the code is really horrible.
3166 */
3167
3168 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3169 int first_key, last_key = -2147483648;
3170 int next_key = 0;
3171 int start_insn = -1;
3172 int last_insn = -1;
3173 Register reg = noreg;
3174 LIR_Opr reg_opr;
3175 state = start_s;
3176
3177 LIR_OpList* inst = lir->instructions_list();
3178 for (int i = 0; i < inst->length(); i++) {
3179 LIR_Op* op = inst->at(i);
3180 switch (state) {
3181 case start_s:
3182 first_key = -1;
3183 start_insn = i;
3184 switch (op->code()) {
3185 case lir_cmp:
3186 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3187 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3188 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3189 && opr2->is_constant()
3190 && opr2->type() == T_INT) {
3191 reg_opr = opr1;
3192 reg = opr1->as_register();
3193 first_key = opr2->as_constant_ptr()->as_jint();
3194 next_key = first_key + 1;
3195 state = cmp_s;
3196 goto next_state;
3197 }
3198 break;
3199 }
3200 break;
3201 case cmp_s:
3202 switch (op->code()) {
3203 case lir_branch:
3204 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3205 state = beq_s;
3206 last_insn = i;
3207 goto next_state;
3208 }
3209 }
3210 state = start_s;
3211 break;
3212 case beq_s:
3213 switch (op->code()) {
3214 case lir_cmp: {
3215 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3216 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3217 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3218 && opr1->as_register() == reg
3219 && opr2->is_constant()
3220 && opr2->type() == T_INT
3221 && opr2->as_constant_ptr()->as_jint() == next_key) {
3222 last_key = next_key;
3223 next_key++;
3224 state = cmp_s;
3225 goto next_state;
3226 }
3227 }
3228 }
3229 last_key = next_key;
3230 state = start_s;
3231 break;
3232 default:
3233 assert(false, "impossible state");
3234 }
3235 if (state == start_s) {
3236 if (first_key < last_key - 5L && reg != noreg) {
3237 {
3238 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3239 // reg->encoding(),
3240 // start_insn, first_key, last_key);
3241 // for (int i = 0; i < inst->length(); i++) {
3242 // inst->at(i)->print();
3243 // tty->print("\n");
3244 // }
3245 // tty->print("\n");
3246 }
3247
3248 struct tableswitch *sw = &switches[tableswitch_count];
3249 sw->_insn_index = start_insn, sw->_first_key = first_key,
3250 sw->_last_key = last_key, sw->_reg = reg;
3251 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3252 {
3253 // Insert the new table of branches
3254 int offset = last_insn;
3255 for (int n = first_key; n < last_key; n++) {
3256 inst->insert_before
3257 (last_insn + 1,
3258 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3259 inst->at(offset)->as_OpBranch()->label()));
3260 offset -= 2, i++;
3261 }
3262 }
3263 // Delete all the old compare-and-branch instructions
3264 for (int n = first_key; n < last_key; n++) {
3265 inst->remove_at(start_insn);
3266 inst->remove_at(start_insn);
3267 }
3268 // Insert the tableswitch instruction
3269 inst->insert_before(start_insn,
3270 new LIR_Op2(lir_cmp, lir_cond_always,
3271 LIR_OprFact::intConst(tableswitch_count),
3272 reg_opr));
3273 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3274 tableswitch_count++;
3275 }
3276 reg = noreg;
3277 last_key = -2147483648;
3278 }
3279 next_state:
3280 ;
3281 }
3282 #endif
3283 }
3284
3285 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3286 Address addr = as_Address(src->as_address_ptr());
3287 BasicType type = src->type();
3288 bool is_oop = is_reference_type(type);
3289
3290 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3291 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3292
3293 switch(type) {
3294 case T_INT:
3295 xchg = &MacroAssembler::atomic_xchgalw;
3296 add = &MacroAssembler::atomic_addalw;
3297 break;
3298 case T_LONG:
3299 xchg = &MacroAssembler::atomic_xchgal;
3300 add = &MacroAssembler::atomic_addal;
3301 break;
3302 case T_OBJECT:
3303 case T_ARRAY:
3304 if (UseCompressedOops) {
3305 xchg = &MacroAssembler::atomic_xchgalw;
3306 add = &MacroAssembler::atomic_addalw;
3307 } else {
3308 xchg = &MacroAssembler::atomic_xchgal;
3309 add = &MacroAssembler::atomic_addal;
3310 }
3311 break;
3312 default:
3313 ShouldNotReachHere();
3314 xchg = &MacroAssembler::atomic_xchgal;
3315 add = &MacroAssembler::atomic_addal; // unreachable
3316 }
3317
3318 switch (code) {
3319 case lir_xadd:
3320 {
3321 RegisterOrConstant inc;
3322 Register tmp = as_reg(tmp_op);
3323 Register dst = as_reg(dest);
3324 if (data->is_constant()) {
3325 inc = RegisterOrConstant(as_long(data));
3326 assert_different_registers(dst, addr.base(), tmp,
3327 rscratch1, rscratch2);
3328 } else {
3329 inc = RegisterOrConstant(as_reg(data));
3330 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3331 rscratch1, rscratch2);
3332 }
3333 __ lea(tmp, addr);
3334 (_masm->*add)(dst, inc, tmp);
3335 break;
3336 }
3337 case lir_xchg:
3338 {
3339 Register tmp = tmp_op->as_register();
3340 Register obj = as_reg(data);
3341 Register dst = as_reg(dest);
3342 if (is_oop && UseCompressedOops) {
3343 __ encode_heap_oop(rscratch2, obj);
3344 obj = rscratch2;
3345 }
3346 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3347 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3348 __ lea(tmp, addr);
3349 (_masm->*xchg)(dst, obj, tmp);
3350 if (is_oop && UseCompressedOops) {
3351 __ decode_heap_oop(dst);
3352 }
3353 }
3354 break;
3355 default:
3356 ShouldNotReachHere();
3357 }
3358 if(!UseLSE) {
3359 __ membar(__ AnyAny);
3360 }
3361 }
3362
3363 #undef __