1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInlineKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "ci/ciObjArrayKlass.hpp"
38 #include "code/compiledIC.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "oops/oop.inline.hpp"
44 #include "runtime/frame.inline.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_aarch64.inline.hpp"
49
50
51 #ifndef PRODUCT
52 #define COMMENT(x) do { __ block_comment(x); } while (0)
53 #else
54 #define COMMENT(x)
55 #endif
56
57 NEEDS_CLEANUP // remove this definitions ?
58 const Register SYNC_header = r0; // synchronization header
59 const Register SHIFT_count = r0; // where count for shift operations must be
60
61 #define __ _masm->
62
63
64 static void select_different_registers(Register preserve,
65 Register extra,
66 Register &tmp1,
67 Register &tmp2) {
68 if (tmp1 == preserve) {
69 assert_different_registers(tmp1, tmp2, extra);
70 tmp1 = extra;
71 } else if (tmp2 == preserve) {
72 assert_different_registers(tmp1, tmp2, extra);
73 tmp2 = extra;
74 }
75 assert_different_registers(preserve, tmp1, tmp2);
76 }
77
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2,
84 Register &tmp3) {
85 if (tmp1 == preserve) {
86 assert_different_registers(tmp1, tmp2, tmp3, extra);
87 tmp1 = extra;
88 } else if (tmp2 == preserve) {
89 assert_different_registers(tmp1, tmp2, tmp3, extra);
90 tmp2 = extra;
91 } else if (tmp3 == preserve) {
92 assert_different_registers(tmp1, tmp2, tmp3, extra);
93 tmp3 = extra;
94 }
95 assert_different_registers(preserve, tmp1, tmp2, tmp3);
96 }
97
98
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
100
101
102 LIR_Opr LIR_Assembler::receiverOpr() {
103 return FrameMap::receiver_opr;
104 }
105
106 LIR_Opr LIR_Assembler::osrBufferPointer() {
107 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
108 }
109
110 //--------------fpu register translations-----------------------
111
112
113 address LIR_Assembler::float_constant(float f) {
114 address const_addr = __ float_constant(f);
115 if (const_addr == nullptr) {
116 bailout("const section overflow");
117 return __ code()->consts()->start();
118 } else {
119 return const_addr;
120 }
121 }
122
123
124 address LIR_Assembler::double_constant(double d) {
125 address const_addr = __ double_constant(d);
126 if (const_addr == nullptr) {
127 bailout("const section overflow");
128 return __ code()->consts()->start();
129 } else {
130 return const_addr;
131 }
132 }
133
134 address LIR_Assembler::int_constant(jlong n) {
135 address const_addr = __ long_constant(n);
136 if (const_addr == nullptr) {
137 bailout("const section overflow");
138 return __ code()->consts()->start();
139 } else {
140 return const_addr;
141 }
142 }
143
144 void LIR_Assembler::breakpoint() { Unimplemented(); }
145
146 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
147
148 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
149
150 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
151 //-------------------------------------------
152
153 static Register as_reg(LIR_Opr op) {
154 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
155 }
156
157 static jlong as_long(LIR_Opr data) {
158 jlong result;
159 switch (data->type()) {
160 case T_INT:
161 result = (data->as_jint());
162 break;
163 case T_LONG:
164 result = (data->as_jlong());
165 break;
166 default:
167 ShouldNotReachHere();
168 result = 0; // unreachable
169 }
170 return result;
171 }
172
173 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
174 Register base = addr->base()->as_pointer_register();
175 LIR_Opr opr = addr->index();
176 if (opr->is_cpu_register()) {
177 Register index;
178 if (opr->is_single_cpu())
179 index = opr->as_register();
180 else
181 index = opr->as_register_lo();
182 assert(addr->disp() == 0, "must be");
183 switch(opr->type()) {
184 case T_INT:
185 return Address(base, index, Address::sxtw(addr->scale()));
186 case T_LONG:
187 return Address(base, index, Address::lsl(addr->scale()));
188 default:
189 ShouldNotReachHere();
190 }
191 } else {
192 assert(addr->scale() == 0,
193 "expected for immediate operand, was: %d", addr->scale());
194 ptrdiff_t offset = ptrdiff_t(addr->disp());
195 // NOTE: Does not handle any 16 byte vector access.
196 const uint type_size = type2aelembytes(addr->type(), true);
197 return __ legitimize_address(Address(base, offset), type_size, tmp);
198 }
199 return Address();
200 }
201
202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
203 ShouldNotReachHere();
204 return Address();
205 }
206
207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
208 return as_Address(addr, rscratch1);
209 }
210
211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
212 return as_Address(addr, rscratch1); // Ouch
213 // FIXME: This needs to be much more clever. See x86.
214 }
215
216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
217 // not encodable as a base + (immediate) offset, generate an explicit address
218 // calculation to hold the address in a temporary register.
219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
220 precond(size == 4 || size == 8);
221 Address addr = frame_map()->address_for_slot(index, adjust);
222 precond(addr.getMode() == Address::base_plus_offset);
223 precond(addr.base() == sp);
224 precond(addr.offset() > 0);
225 uint mask = size - 1;
226 assert((addr.offset() & mask) == 0, "scaled offsets only");
227 return __ legitimize_address(addr, size, tmp);
228 }
229
230 void LIR_Assembler::osr_entry() {
231 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
232 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
233 ValueStack* entry_state = osr_entry->state();
234 int number_of_locks = entry_state->locks_size();
235
236 // we jump here if osr happens with the interpreter
237 // state set up to continue at the beginning of the
238 // loop that triggered osr - in particular, we have
239 // the following registers setup:
240 //
241 // r2: osr buffer
242 //
243
244 // build frame
245 ciMethod* m = compilation()->method();
246 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
247
248 // OSR buffer is
249 //
250 // locals[nlocals-1..0]
251 // monitors[0..number_of_locks]
252 //
253 // locals is a direct copy of the interpreter frame so in the osr buffer
254 // so first slot in the local array is the last local from the interpreter
255 // and last slot is local[0] (receiver) from the interpreter
256 //
257 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
258 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
259 // in the interpreter frame (the method lock if a sync method)
260
261 // Initialize monitors in the compiled activation.
262 // r2: pointer to osr buffer
263 //
264 // All other registers are dead at this point and the locals will be
265 // copied into place by code emitted in the IR.
266
267 Register OSR_buf = osrBufferPointer()->as_pointer_register();
268 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
269 int monitor_offset = BytesPerWord * method()->max_locals() +
270 (2 * BytesPerWord) * (number_of_locks - 1);
271 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
272 // the OSR buffer using 2 word entries: first the lock and then
273 // the oop.
274 for (int i = 0; i < number_of_locks; i++) {
275 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
276 #ifdef ASSERT
277 // verify the interpreter's monitor has a non-null object
278 {
279 Label L;
280 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
281 __ cbnz(rscratch1, L);
282 __ stop("locked object is null");
283 __ bind(L);
284 }
285 #endif
286 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
287 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
288 __ str(r19, frame_map()->address_for_monitor_lock(i));
289 __ str(r20, frame_map()->address_for_monitor_object(i));
290 }
291 }
292 }
293
294
295 // inline cache check; done before the frame is built.
296 int LIR_Assembler::check_icache() {
297 return __ ic_check(CodeEntryAlignment);
298 }
299
300 void LIR_Assembler::clinit_barrier(ciMethod* method) {
301 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
302 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
303
304 Label L_skip_barrier;
305
306 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
307 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
308 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
309 __ bind(L_skip_barrier);
310 }
311
312 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
313 if (o == nullptr) {
314 __ mov(reg, zr);
315 } else {
316 __ movoop(reg, o);
317 }
318 }
319
320 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
321 address target = nullptr;
322 relocInfo::relocType reloc_type = relocInfo::none;
323
324 switch (patching_id(info)) {
325 case PatchingStub::access_field_id:
326 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
327 reloc_type = relocInfo::section_word_type;
328 break;
329 case PatchingStub::load_klass_id:
330 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
331 reloc_type = relocInfo::metadata_type;
332 break;
333 case PatchingStub::load_mirror_id:
334 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
335 reloc_type = relocInfo::oop_type;
336 break;
337 case PatchingStub::load_appendix_id:
338 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
339 reloc_type = relocInfo::oop_type;
340 break;
341 default: ShouldNotReachHere();
342 }
343
344 __ far_call(RuntimeAddress(target));
345 add_call_info_here(info);
346 }
347
348 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
349 deoptimize_trap(info);
350 }
351
352
353 // This specifies the rsp decrement needed to build the frame
354 int LIR_Assembler::initial_frame_size_in_bytes() const {
355 // if rounding, must let FrameMap know!
356
357 return in_bytes(frame_map()->framesize_in_bytes());
358 }
359
360
361 int LIR_Assembler::emit_exception_handler() {
362 // generate code for exception handler
363 address handler_base = __ start_a_stub(exception_handler_size());
364 if (handler_base == nullptr) {
365 // not enough space left for the handler
366 bailout("exception handler overflow");
367 return -1;
368 }
369
370 int offset = code_offset();
371
372 // the exception oop and pc are in r0, and r3
373 // no other registers need to be preserved, so invalidate them
374 __ invalidate_registers(false, true, true, false, true, true);
375
376 // check that there is really an exception
377 __ verify_not_null_oop(r0);
378
379 // search an exception handler (r0: exception oop, r3: throwing pc)
380 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
381 __ should_not_reach_here();
382 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
383 __ end_a_stub();
384
385 return offset;
386 }
387
388
389 // Emit the code to remove the frame from the stack in the exception
390 // unwind path.
391 int LIR_Assembler::emit_unwind_handler() {
392 #ifndef PRODUCT
393 if (CommentedAssembly) {
394 _masm->block_comment("Unwind handler");
395 }
396 #endif
397
398 int offset = code_offset();
399
400 // Fetch the exception from TLS and clear out exception related thread state
401 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
403 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
404
405 __ bind(_unwind_handler_entry);
406 __ verify_not_null_oop(r0);
407 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
408 __ mov(r19, r0); // Preserve the exception
409 }
410
411 // Perform needed unlocking
412 MonitorExitStub* stub = nullptr;
413 if (method()->is_synchronized()) {
414 monitor_address(0, FrameMap::r0_opr);
415 stub = new MonitorExitStub(FrameMap::r0_opr, 0);
416 __ unlock_object(r5, r4, r0, r6, *stub->entry());
417 __ bind(*stub->continuation());
418 }
419
420 if (compilation()->env()->dtrace_method_probes()) {
421 __ mov(c_rarg0, rthread);
422 __ mov_metadata(c_rarg1, method()->constant_encoding());
423 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
424 }
425
426 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
427 __ mov(r0, r19); // Restore the exception
428 }
429
430 // remove the activation and dispatch to the unwind handler
431 __ block_comment("remove_frame and dispatch to the unwind handler");
432 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
433 __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
434
435 // Emit the slow path assembly
436 if (stub != nullptr) {
437 stub->emit_code(this);
438 }
439
440 return offset;
441 }
442
443
444 int LIR_Assembler::emit_deopt_handler() {
445 // generate code for exception handler
446 address handler_base = __ start_a_stub(deopt_handler_size());
447 if (handler_base == nullptr) {
448 // not enough space left for the handler
449 bailout("deopt handler overflow");
450 return -1;
451 }
452
453 int offset = code_offset();
454
455 Label start;
456 __ bind(start);
457
458 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
459
460 int entry_offset = __ offset();
461 __ b(start);
462
463 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
464 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
465 "out of bounds read in post-call NOP check");
466 __ end_a_stub();
467
468 return entry_offset;
469 }
470
471 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
472 _masm->code_section()->relocate(adr, relocInfo::poll_type);
473 int pc_offset = code_offset();
474 flush_debug_info(pc_offset);
475 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
476 if (info->exception_handlers() != nullptr) {
477 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
478 }
479 }
480
481 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
482 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
483
484 if (InlineTypeReturnedAsFields) {
485 // Check if we are returning an non-null inline type and load its fields into registers
486 ciType* return_type = compilation()->method()->return_type();
487 if (return_type->is_inlinetype()) {
488 ciInlineKlass* vk = return_type->as_inline_klass();
489 if (vk->can_be_returned_as_fields()) {
490 address unpack_handler = vk->unpack_handler();
491 assert(unpack_handler != nullptr, "must be");
492 __ far_call(RuntimeAddress(unpack_handler));
493 }
494 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) {
495 Label skip;
496 Label not_null;
497 __ cbnz(r0, not_null);
498 // Returned value is null, zero all return registers because they may belong to oop fields
499 __ mov(j_rarg1, zr);
500 __ mov(j_rarg2, zr);
501 __ mov(j_rarg3, zr);
502 __ mov(j_rarg4, zr);
503 __ mov(j_rarg5, zr);
504 __ mov(j_rarg6, zr);
505 __ mov(j_rarg7, zr);
506 __ b(skip);
507 __ bind(not_null);
508
509 // Check if we are returning an non-null inline type and load its fields into registers
510 __ test_oop_is_not_inline_type(r0, rscratch2, skip, /* can_be_null= */ false);
511
512 // Load fields from a buffered value with an inline class specific handler
513 __ load_klass(rscratch1 /*dst*/, r0 /*src*/);
514 __ ldr(rscratch1, Address(rscratch1, InlineKlass::adr_members_offset()));
515 __ ldr(rscratch1, Address(rscratch1, InlineKlass::unpack_handler_offset()));
516 // Unpack handler can be null if inline type is not scalarizable in returns
517 __ cbz(rscratch1, skip);
518 __ blr(rscratch1);
519
520 __ bind(skip);
521 }
522 // At this point, r0 points to the value object (for interpreter or C1 caller).
523 // The fields of the object are copied into registers (for C2 caller).
524 }
525
526 // Pop the stack before the safepoint code
527 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
528
529 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
530 __ reserved_stack_check();
531 }
532
533 code_stub->set_safepoint_offset(__ offset());
534 __ relocate(relocInfo::poll_return_type);
535 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
536 __ ret(lr);
537 }
538
539 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
540 return (__ store_inline_type_fields_to_buf(vk, false));
541 }
542
543 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
544 guarantee(info != nullptr, "Shouldn't be null");
545 __ get_polling_page(rscratch1, relocInfo::poll_type);
546 add_debug_info_for_branch(info); // This isn't just debug info:
547 // it's the oop map
548 __ read_polling_page(rscratch1, relocInfo::poll_type);
549 return __ offset();
550 }
551
552
553 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
554 if (from_reg == r31_sp)
555 from_reg = sp;
556 if (to_reg == r31_sp)
557 to_reg = sp;
558 __ mov(to_reg, from_reg);
559 }
560
561 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
562
563
564 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
565 assert(src->is_constant(), "should not call otherwise");
566 assert(dest->is_register(), "should not call otherwise");
567 LIR_Const* c = src->as_constant_ptr();
568
569 switch (c->type()) {
570 case T_INT: {
571 assert(patch_code == lir_patch_none, "no patching handled here");
572 __ movw(dest->as_register(), c->as_jint());
573 break;
574 }
575
576 case T_ADDRESS: {
577 assert(patch_code == lir_patch_none, "no patching handled here");
578 __ mov(dest->as_register(), c->as_jint());
579 break;
580 }
581
582 case T_LONG: {
583 assert(patch_code == lir_patch_none, "no patching handled here");
584 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
585 break;
586 }
587
588 case T_OBJECT: {
589 if (patch_code != lir_patch_none) {
590 jobject2reg_with_patching(dest->as_register(), info);
591 } else {
592 jobject2reg(c->as_jobject(), dest->as_register());
593 }
594 break;
595 }
596
597 case T_METADATA: {
598 if (patch_code != lir_patch_none) {
599 klass2reg_with_patching(dest->as_register(), info);
600 } else {
601 __ mov_metadata(dest->as_register(), c->as_metadata());
602 }
603 break;
604 }
605
606 case T_FLOAT: {
607 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
608 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
609 } else {
610 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
611 __ ldrs(dest->as_float_reg(), Address(rscratch1));
612 }
613 break;
614 }
615
616 case T_DOUBLE: {
617 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
618 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
619 } else {
620 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
621 __ ldrd(dest->as_double_reg(), Address(rscratch1));
622 }
623 break;
624 }
625
626 default:
627 ShouldNotReachHere();
628 }
629 }
630
631 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
632 LIR_Const* c = src->as_constant_ptr();
633 switch (c->type()) {
634 case T_OBJECT:
635 {
636 if (! c->as_jobject())
637 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
638 else {
639 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
640 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
641 }
642 }
643 break;
644 case T_ADDRESS:
645 {
646 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
647 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
648 }
649 case T_INT:
650 case T_FLOAT:
651 {
652 Register reg = zr;
653 if (c->as_jint_bits() == 0)
654 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
655 else {
656 __ movw(rscratch1, c->as_jint_bits());
657 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
658 }
659 }
660 break;
661 case T_LONG:
662 case T_DOUBLE:
663 {
664 Register reg = zr;
665 if (c->as_jlong_bits() == 0)
666 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
667 lo_word_offset_in_bytes));
668 else {
669 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
670 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
671 lo_word_offset_in_bytes));
672 }
673 }
674 break;
675 default:
676 ShouldNotReachHere();
677 }
678 }
679
680 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
681 assert(src->is_constant(), "should not call otherwise");
682 LIR_Const* c = src->as_constant_ptr();
683 LIR_Address* to_addr = dest->as_address_ptr();
684
685 void (Assembler::* insn)(Register Rt, const Address &adr);
686
687 switch (type) {
688 case T_ADDRESS:
689 assert(c->as_jint() == 0, "should be");
690 insn = &Assembler::str;
691 break;
692 case T_LONG:
693 assert(c->as_jlong() == 0, "should be");
694 insn = &Assembler::str;
695 break;
696 case T_INT:
697 assert(c->as_jint() == 0, "should be");
698 insn = &Assembler::strw;
699 break;
700 case T_OBJECT:
701 case T_ARRAY:
702 // Non-null case is not handled on aarch64 but handled on x86
703 // FIXME: do we need to add it here?
704 assert(c->as_jobject() == nullptr, "should be");
705 if (UseCompressedOops && !wide) {
706 insn = &Assembler::strw;
707 } else {
708 insn = &Assembler::str;
709 }
710 break;
711 case T_CHAR:
712 case T_SHORT:
713 assert(c->as_jint() == 0, "should be");
714 insn = &Assembler::strh;
715 break;
716 case T_BOOLEAN:
717 case T_BYTE:
718 assert(c->as_jint() == 0, "should be");
719 insn = &Assembler::strb;
720 break;
721 default:
722 ShouldNotReachHere();
723 insn = &Assembler::str; // unreachable
724 }
725
726 if (info) add_debug_info_for_null_check_here(info);
727 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
728 }
729
730 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
731 assert(src->is_register(), "should not call otherwise");
732 assert(dest->is_register(), "should not call otherwise");
733
734 // move between cpu-registers
735 if (dest->is_single_cpu()) {
736 if (src->type() == T_LONG) {
737 // Can do LONG -> OBJECT
738 move_regs(src->as_register_lo(), dest->as_register());
739 return;
740 }
741 assert(src->is_single_cpu(), "must match");
742 if (src->type() == T_OBJECT) {
743 __ verify_oop(src->as_register());
744 }
745 move_regs(src->as_register(), dest->as_register());
746
747 } else if (dest->is_double_cpu()) {
748 if (is_reference_type(src->type())) {
749 // Surprising to me but we can see move of a long to t_object
750 __ verify_oop(src->as_register());
751 move_regs(src->as_register(), dest->as_register_lo());
752 return;
753 }
754 assert(src->is_double_cpu(), "must match");
755 Register f_lo = src->as_register_lo();
756 Register f_hi = src->as_register_hi();
757 Register t_lo = dest->as_register_lo();
758 Register t_hi = dest->as_register_hi();
759 assert(f_hi == f_lo, "must be same");
760 assert(t_hi == t_lo, "must be same");
761 move_regs(f_lo, t_lo);
762
763 } else if (dest->is_single_fpu()) {
764 __ fmovs(dest->as_float_reg(), src->as_float_reg());
765
766 } else if (dest->is_double_fpu()) {
767 __ fmovd(dest->as_double_reg(), src->as_double_reg());
768
769 } else {
770 ShouldNotReachHere();
771 }
772 }
773
774 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
775 precond(src->is_register() && dest->is_stack());
776
777 uint const c_sz32 = sizeof(uint32_t);
778 uint const c_sz64 = sizeof(uint64_t);
779
780 if (src->is_single_cpu()) {
781 int index = dest->single_stack_ix();
782 if (is_reference_type(type)) {
783 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
784 __ verify_oop(src->as_register());
785 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
786 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
787 } else {
788 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
789 }
790
791 } else if (src->is_double_cpu()) {
792 int index = dest->double_stack_ix();
793 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
794 __ str(src->as_register_lo(), dest_addr_LO);
795
796 } else if (src->is_single_fpu()) {
797 int index = dest->single_stack_ix();
798 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
799
800 } else if (src->is_double_fpu()) {
801 int index = dest->double_stack_ix();
802 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
803
804 } else {
805 ShouldNotReachHere();
806 }
807 }
808
809
810 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
811 LIR_Address* to_addr = dest->as_address_ptr();
812 PatchingStub* patch = nullptr;
813 Register compressed_src = rscratch1;
814
815 if (patch_code != lir_patch_none) {
816 deoptimize_trap(info);
817 return;
818 }
819
820 if (is_reference_type(type)) {
821 __ verify_oop(src->as_register());
822
823 if (UseCompressedOops && !wide) {
824 __ encode_heap_oop(compressed_src, src->as_register());
825 } else {
826 compressed_src = src->as_register();
827 }
828 }
829
830 int null_check_here = code_offset();
831 switch (type) {
832 case T_FLOAT: {
833 __ strs(src->as_float_reg(), as_Address(to_addr));
834 break;
835 }
836
837 case T_DOUBLE: {
838 __ strd(src->as_double_reg(), as_Address(to_addr));
839 break;
840 }
841
842 case T_ARRAY: // fall through
843 case T_OBJECT: // fall through
844 if (UseCompressedOops && !wide) {
845 __ strw(compressed_src, as_Address(to_addr, rscratch2));
846 } else {
847 __ str(compressed_src, as_Address(to_addr));
848 }
849 break;
850 case T_METADATA:
851 // We get here to store a method pointer to the stack to pass to
852 // a dtrace runtime call. This can't work on 64 bit with
853 // compressed klass ptrs: T_METADATA can be a compressed klass
854 // ptr or a 64 bit method pointer.
855 ShouldNotReachHere();
856 __ str(src->as_register(), as_Address(to_addr));
857 break;
858 case T_ADDRESS:
859 __ str(src->as_register(), as_Address(to_addr));
860 break;
861 case T_INT:
862 __ strw(src->as_register(), as_Address(to_addr));
863 break;
864
865 case T_LONG: {
866 __ str(src->as_register_lo(), as_Address_lo(to_addr));
867 break;
868 }
869
870 case T_BYTE: // fall through
871 case T_BOOLEAN: {
872 __ strb(src->as_register(), as_Address(to_addr));
873 break;
874 }
875
876 case T_CHAR: // fall through
877 case T_SHORT:
878 __ strh(src->as_register(), as_Address(to_addr));
879 break;
880
881 default:
882 ShouldNotReachHere();
883 }
884 if (info != nullptr) {
885 add_debug_info_for_null_check(null_check_here, info);
886 }
887 }
888
889
890 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
891 precond(src->is_stack() && dest->is_register());
892
893 uint const c_sz32 = sizeof(uint32_t);
894 uint const c_sz64 = sizeof(uint64_t);
895
896 if (dest->is_single_cpu()) {
897 int index = src->single_stack_ix();
898 if (is_reference_type(type)) {
899 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
900 __ verify_oop(dest->as_register());
901 } else if (type == T_METADATA || type == T_ADDRESS) {
902 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
903 } else {
904 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
905 }
906
907 } else if (dest->is_double_cpu()) {
908 int index = src->double_stack_ix();
909 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
910 __ ldr(dest->as_register_lo(), src_addr_LO);
911
912 } else if (dest->is_single_fpu()) {
913 int index = src->single_stack_ix();
914 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
915
916 } else if (dest->is_double_fpu()) {
917 int index = src->double_stack_ix();
918 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
919
920 } else {
921 ShouldNotReachHere();
922 }
923 }
924
925
926 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
927 address target = nullptr;
928 relocInfo::relocType reloc_type = relocInfo::none;
929
930 switch (patching_id(info)) {
931 case PatchingStub::access_field_id:
932 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
933 reloc_type = relocInfo::section_word_type;
934 break;
935 case PatchingStub::load_klass_id:
936 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
937 reloc_type = relocInfo::metadata_type;
938 break;
939 case PatchingStub::load_mirror_id:
940 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
941 reloc_type = relocInfo::oop_type;
942 break;
943 case PatchingStub::load_appendix_id:
944 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
945 reloc_type = relocInfo::oop_type;
946 break;
947 default: ShouldNotReachHere();
948 }
949
950 __ far_call(RuntimeAddress(target));
951 add_call_info_here(info);
952 }
953
954 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
955
956 LIR_Opr temp;
957 if (type == T_LONG || type == T_DOUBLE)
958 temp = FrameMap::rscratch1_long_opr;
959 else
960 temp = FrameMap::rscratch1_opr;
961
962 stack2reg(src, temp, src->type());
963 reg2stack(temp, dest, dest->type());
964 }
965
966
967 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
968 LIR_Address* addr = src->as_address_ptr();
969 LIR_Address* from_addr = src->as_address_ptr();
970
971 if (addr->base()->type() == T_OBJECT) {
972 __ verify_oop(addr->base()->as_pointer_register());
973 }
974
975 if (patch_code != lir_patch_none) {
976 deoptimize_trap(info);
977 return;
978 }
979
980 if (info != nullptr) {
981 add_debug_info_for_null_check_here(info);
982 }
983 int null_check_here = code_offset();
984 switch (type) {
985 case T_FLOAT: {
986 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
987 break;
988 }
989
990 case T_DOUBLE: {
991 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
992 break;
993 }
994
995 case T_ARRAY: // fall through
996 case T_OBJECT: // fall through
997 if (UseCompressedOops && !wide) {
998 __ ldrw(dest->as_register(), as_Address(from_addr));
999 } else {
1000 __ ldr(dest->as_register(), as_Address(from_addr));
1001 }
1002 break;
1003 case T_METADATA:
1004 // We get here to store a method pointer to the stack to pass to
1005 // a dtrace runtime call. This can't work on 64 bit with
1006 // compressed klass ptrs: T_METADATA can be a compressed klass
1007 // ptr or a 64 bit method pointer.
1008 ShouldNotReachHere();
1009 __ ldr(dest->as_register(), as_Address(from_addr));
1010 break;
1011 case T_ADDRESS:
1012 __ ldr(dest->as_register(), as_Address(from_addr));
1013 break;
1014 case T_INT:
1015 __ ldrw(dest->as_register(), as_Address(from_addr));
1016 break;
1017
1018 case T_LONG: {
1019 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1020 break;
1021 }
1022
1023 case T_BYTE:
1024 __ ldrsb(dest->as_register(), as_Address(from_addr));
1025 break;
1026 case T_BOOLEAN: {
1027 __ ldrb(dest->as_register(), as_Address(from_addr));
1028 break;
1029 }
1030
1031 case T_CHAR:
1032 __ ldrh(dest->as_register(), as_Address(from_addr));
1033 break;
1034 case T_SHORT:
1035 __ ldrsh(dest->as_register(), as_Address(from_addr));
1036 break;
1037
1038 default:
1039 ShouldNotReachHere();
1040 }
1041
1042 if (is_reference_type(type)) {
1043 if (UseCompressedOops && !wide) {
1044 __ decode_heap_oop(dest->as_register());
1045 }
1046
1047 __ verify_oop(dest->as_register());
1048 }
1049 }
1050
1051 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
1052 assert(dst->is_cpu_register(), "must be");
1053 assert(dst->type() == src->type(), "must be");
1054
1055 if (src->is_cpu_register()) {
1056 reg2reg(src, dst);
1057 } else if (src->is_stack()) {
1058 stack2reg(src, dst, dst->type());
1059 } else if (src->is_constant()) {
1060 const2reg(src, dst, lir_patch_none, nullptr);
1061 } else {
1062 ShouldNotReachHere();
1063 }
1064 }
1065
1066 int LIR_Assembler::array_element_size(BasicType type) const {
1067 int elem_size = type2aelembytes(type);
1068 return exact_log2(elem_size);
1069 }
1070
1071
1072 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1073 switch (op->code()) {
1074 case lir_idiv:
1075 case lir_irem:
1076 arithmetic_idiv(op->code(),
1077 op->in_opr1(),
1078 op->in_opr2(),
1079 op->in_opr3(),
1080 op->result_opr(),
1081 op->info());
1082 break;
1083 case lir_fmad:
1084 __ fmaddd(op->result_opr()->as_double_reg(),
1085 op->in_opr1()->as_double_reg(),
1086 op->in_opr2()->as_double_reg(),
1087 op->in_opr3()->as_double_reg());
1088 break;
1089 case lir_fmaf:
1090 __ fmadds(op->result_opr()->as_float_reg(),
1091 op->in_opr1()->as_float_reg(),
1092 op->in_opr2()->as_float_reg(),
1093 op->in_opr3()->as_float_reg());
1094 break;
1095 default: ShouldNotReachHere(); break;
1096 }
1097 }
1098
1099 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1100 #ifdef ASSERT
1101 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1102 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1103 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1104 #endif
1105
1106 if (op->cond() == lir_cond_always) {
1107 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1108 __ b(*(op->label()));
1109 } else {
1110 Assembler::Condition acond;
1111 if (op->code() == lir_cond_float_branch) {
1112 bool is_unordered = (op->ublock() == op->block());
1113 // Assembler::EQ does not permit unordered branches, so we add
1114 // another branch here. Likewise, Assembler::NE does not permit
1115 // ordered branches.
1116 if ((is_unordered && op->cond() == lir_cond_equal)
1117 || (!is_unordered && op->cond() == lir_cond_notEqual))
1118 __ br(Assembler::VS, *(op->ublock()->label()));
1119 switch(op->cond()) {
1120 case lir_cond_equal: acond = Assembler::EQ; break;
1121 case lir_cond_notEqual: acond = Assembler::NE; break;
1122 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1123 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1124 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1125 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1126 default: ShouldNotReachHere();
1127 acond = Assembler::EQ; // unreachable
1128 }
1129 } else {
1130 switch (op->cond()) {
1131 case lir_cond_equal: acond = Assembler::EQ; break;
1132 case lir_cond_notEqual: acond = Assembler::NE; break;
1133 case lir_cond_less: acond = Assembler::LT; break;
1134 case lir_cond_lessEqual: acond = Assembler::LE; break;
1135 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1136 case lir_cond_greater: acond = Assembler::GT; break;
1137 case lir_cond_belowEqual: acond = Assembler::LS; break;
1138 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1139 default: ShouldNotReachHere();
1140 acond = Assembler::EQ; // unreachable
1141 }
1142 }
1143 __ br(acond,*(op->label()));
1144 }
1145 }
1146
1147
1148
1149 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1150 LIR_Opr src = op->in_opr();
1151 LIR_Opr dest = op->result_opr();
1152
1153 switch (op->bytecode()) {
1154 case Bytecodes::_i2f:
1155 {
1156 __ scvtfws(dest->as_float_reg(), src->as_register());
1157 break;
1158 }
1159 case Bytecodes::_i2d:
1160 {
1161 __ scvtfwd(dest->as_double_reg(), src->as_register());
1162 break;
1163 }
1164 case Bytecodes::_l2d:
1165 {
1166 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1167 break;
1168 }
1169 case Bytecodes::_l2f:
1170 {
1171 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1172 break;
1173 }
1174 case Bytecodes::_f2d:
1175 {
1176 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1177 break;
1178 }
1179 case Bytecodes::_d2f:
1180 {
1181 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1182 break;
1183 }
1184 case Bytecodes::_i2c:
1185 {
1186 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1187 break;
1188 }
1189 case Bytecodes::_i2l:
1190 {
1191 __ sxtw(dest->as_register_lo(), src->as_register());
1192 break;
1193 }
1194 case Bytecodes::_i2s:
1195 {
1196 __ sxth(dest->as_register(), src->as_register());
1197 break;
1198 }
1199 case Bytecodes::_i2b:
1200 {
1201 __ sxtb(dest->as_register(), src->as_register());
1202 break;
1203 }
1204 case Bytecodes::_l2i:
1205 {
1206 _masm->block_comment("FIXME: This could be a no-op");
1207 __ uxtw(dest->as_register(), src->as_register_lo());
1208 break;
1209 }
1210 case Bytecodes::_d2l:
1211 {
1212 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1213 break;
1214 }
1215 case Bytecodes::_f2i:
1216 {
1217 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1218 break;
1219 }
1220 case Bytecodes::_f2l:
1221 {
1222 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1223 break;
1224 }
1225 case Bytecodes::_d2i:
1226 {
1227 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1228 break;
1229 }
1230 default: ShouldNotReachHere();
1231 }
1232 }
1233
1234 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1235 if (op->init_check()) {
1236 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1237 __ ldarb(rscratch1, rscratch1);
1238 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1239 add_debug_info_for_null_check_here(op->stub()->info());
1240 __ br(Assembler::NE, *op->stub()->entry());
1241 }
1242 __ allocate_object(op->obj()->as_register(),
1243 op->tmp1()->as_register(),
1244 op->tmp2()->as_register(),
1245 op->header_size(),
1246 op->object_size(),
1247 op->klass()->as_register(),
1248 *op->stub()->entry());
1249 __ bind(*op->stub()->continuation());
1250 }
1251
1252 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1253 Register len = op->len()->as_register();
1254 __ uxtw(len, len);
1255
1256 if (UseSlowPath || op->always_slow_path() ||
1257 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1258 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1259 __ b(*op->stub()->entry());
1260 } else {
1261 Register tmp1 = op->tmp1()->as_register();
1262 Register tmp2 = op->tmp2()->as_register();
1263 Register tmp3 = op->tmp3()->as_register();
1264 if (len == tmp1) {
1265 tmp1 = tmp3;
1266 } else if (len == tmp2) {
1267 tmp2 = tmp3;
1268 } else if (len == tmp3) {
1269 // everything is ok
1270 } else {
1271 __ mov(tmp3, len);
1272 }
1273 __ allocate_array(op->obj()->as_register(),
1274 len,
1275 tmp1,
1276 tmp2,
1277 arrayOopDesc::base_offset_in_bytes(op->type()),
1278 array_element_size(op->type()),
1279 op->klass()->as_register(),
1280 *op->stub()->entry(),
1281 op->zero_array());
1282 }
1283 __ bind(*op->stub()->continuation());
1284 }
1285
1286 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md,
1287 ciProfileData *data, Register recv) {
1288
1289 int mdp_offset = md->byte_offset_of_slot(data, in_ByteSize(0));
1290 __ profile_receiver_type(recv, mdo, mdp_offset);
1291 }
1292
1293 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1294 // we always need a stub for the failure case.
1295 CodeStub* stub = op->stub();
1296 Register obj = op->object()->as_register();
1297 Register k_RInfo = op->tmp1()->as_register();
1298 Register klass_RInfo = op->tmp2()->as_register();
1299 Register dst = op->result_opr()->as_register();
1300 ciKlass* k = op->klass();
1301 Register Rtmp1 = noreg;
1302
1303 // check if it needs to be profiled
1304 ciMethodData* md;
1305 ciProfileData* data;
1306
1307 const bool should_profile = op->should_profile();
1308
1309 if (should_profile) {
1310 ciMethod* method = op->profiled_method();
1311 assert(method != nullptr, "Should have method");
1312 int bci = op->profiled_bci();
1313 md = method->method_data_or_null();
1314 assert(md != nullptr, "Sanity");
1315 data = md->bci_to_data(bci);
1316 assert(data != nullptr, "need data for type check");
1317 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1318 }
1319 Label* success_target = success;
1320 Label* failure_target = failure;
1321
1322 if (obj == k_RInfo) {
1323 k_RInfo = dst;
1324 } else if (obj == klass_RInfo) {
1325 klass_RInfo = dst;
1326 }
1327 if (k->is_loaded() && !UseCompressedClassPointers) {
1328 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1329 } else {
1330 Rtmp1 = op->tmp3()->as_register();
1331 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1332 }
1333
1334 assert_different_registers(obj, k_RInfo, klass_RInfo);
1335
1336 if (op->need_null_check()) {
1337 if (should_profile) {
1338 Register mdo = klass_RInfo;
1339 __ mov_metadata(mdo, md->constant_encoding());
1340 Label not_null;
1341 __ cbnz(obj, not_null);
1342 // Object is null; update MDO and exit
1343 Address data_addr
1344 = __ form_address(rscratch2, mdo,
1345 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1346 0);
1347 __ ldrb(rscratch1, data_addr);
1348 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1349 __ strb(rscratch1, data_addr);
1350 __ b(*obj_is_null);
1351 __ bind(not_null);
1352
1353 Register recv = k_RInfo;
1354 __ load_klass(recv, obj);
1355 type_profile_helper(mdo, md, data, recv);
1356 } else {
1357 __ cbz(obj, *obj_is_null);
1358 }
1359 }
1360
1361 if (!k->is_loaded()) {
1362 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1363 } else {
1364 __ mov_metadata(k_RInfo, k->constant_encoding());
1365 }
1366 __ verify_oop(obj);
1367
1368 if (op->fast_check()) {
1369 assert(!k->is_loaded() || !k->is_obj_array_klass(), "Use refined array for a direct pointer comparison");
1370 // get object class
1371 // not a safepoint as obj null check happens earlier
1372 __ load_klass(rscratch1, obj);
1373 __ cmp( rscratch1, k_RInfo);
1374
1375 __ br(Assembler::NE, *failure_target);
1376 // successful cast, fall through to profile or jump
1377 } else {
1378 // get object class
1379 // not a safepoint as obj null check happens earlier
1380 __ load_klass(klass_RInfo, obj);
1381 if (k->is_loaded()) {
1382 // See if we get an immediate positive hit
1383 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1384 __ cmp(k_RInfo, rscratch1);
1385 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1386 __ br(Assembler::NE, *failure_target);
1387 // successful cast, fall through to profile or jump
1388 } else {
1389 // See if we get an immediate positive hit
1390 __ br(Assembler::EQ, *success_target);
1391 // check for self
1392 if (k->is_loaded() && k->is_obj_array_klass()) {
1393 // For a direct pointer comparison, we need the refined array klass pointer
1394 ciKlass* k_refined = ciObjArrayKlass::make(k->as_obj_array_klass()->element_klass());
1395 __ mov_metadata(rscratch1, k_refined->constant_encoding());
1396 __ cmp(klass_RInfo, rscratch1);
1397 } else {
1398 __ cmp(klass_RInfo, k_RInfo);
1399 }
1400 __ br(Assembler::EQ, *success_target);
1401
1402 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1403 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1404 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1405 // result is a boolean
1406 __ cbzw(klass_RInfo, *failure_target);
1407 // successful cast, fall through to profile or jump
1408 }
1409 } else {
1410 // perform the fast part of the checking logic
1411 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1412 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1413 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1414 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1415 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1416 // result is a boolean
1417 __ cbz(k_RInfo, *failure_target);
1418 // successful cast, fall through to profile or jump
1419 }
1420 }
1421 __ b(*success);
1422 }
1423
1424
1425 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1426 const bool should_profile = op->should_profile();
1427
1428 LIR_Code code = op->code();
1429 if (code == lir_store_check) {
1430 Register value = op->object()->as_register();
1431 Register array = op->array()->as_register();
1432 Register k_RInfo = op->tmp1()->as_register();
1433 Register klass_RInfo = op->tmp2()->as_register();
1434 Register Rtmp1 = op->tmp3()->as_register();
1435
1436 CodeStub* stub = op->stub();
1437
1438 // check if it needs to be profiled
1439 ciMethodData* md;
1440 ciProfileData* data;
1441
1442 if (should_profile) {
1443 ciMethod* method = op->profiled_method();
1444 assert(method != nullptr, "Should have method");
1445 int bci = op->profiled_bci();
1446 md = method->method_data_or_null();
1447 assert(md != nullptr, "Sanity");
1448 data = md->bci_to_data(bci);
1449 assert(data != nullptr, "need data for type check");
1450 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1451 }
1452 Label done;
1453 Label* success_target = &done;
1454 Label* failure_target = stub->entry();
1455
1456 if (should_profile) {
1457 Label not_null;
1458 Register mdo = klass_RInfo;
1459 __ mov_metadata(mdo, md->constant_encoding());
1460 __ cbnz(value, not_null);
1461 // Object is null; update MDO and exit
1462 Address data_addr
1463 = __ form_address(rscratch2, mdo,
1464 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1465 __ ldrb(rscratch1, data_addr);
1466 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1467 __ strb(rscratch1, data_addr);
1468 __ b(done);
1469 __ bind(not_null);
1470
1471 Register recv = k_RInfo;
1472 __ load_klass(recv, value);
1473 type_profile_helper(mdo, md, data, recv);
1474 } else {
1475 __ cbz(value, done);
1476 }
1477
1478 add_debug_info_for_null_check_here(op->info_for_exception());
1479 __ load_klass(k_RInfo, array);
1480 __ load_klass(klass_RInfo, value);
1481
1482 // get instance klass (it's already uncompressed)
1483 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1484 // perform the fast part of the checking logic
1485 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1486 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1487 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1488 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1489 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1490 // result is a boolean
1491 __ cbzw(k_RInfo, *failure_target);
1492 // fall through to the success case
1493
1494 __ bind(done);
1495 } else if (code == lir_checkcast) {
1496 Register obj = op->object()->as_register();
1497 Register dst = op->result_opr()->as_register();
1498 Label success;
1499 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1500 __ bind(success);
1501 if (dst != obj) {
1502 __ mov(dst, obj);
1503 }
1504 } else if (code == lir_instanceof) {
1505 Register obj = op->object()->as_register();
1506 Register dst = op->result_opr()->as_register();
1507 Label success, failure, done;
1508 emit_typecheck_helper(op, &success, &failure, &failure);
1509 __ bind(failure);
1510 __ mov(dst, zr);
1511 __ b(done);
1512 __ bind(success);
1513 __ mov(dst, 1);
1514 __ bind(done);
1515 } else {
1516 ShouldNotReachHere();
1517 }
1518 }
1519
1520 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1521 // We are loading/storing from/to an array that *may* be a flat array (the
1522 // declared type is Object[], abstract[], interface[] or VT.ref[]).
1523 // If this array is a flat array, take the slow path.
1524 __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1525 if (!op->value()->is_illegal()) {
1526 // The array is not a flat array, but it might be null-free. If we are storing
1527 // a null into a null-free array, take the slow path (which will throw NPE).
1528 Label skip;
1529 __ cbnz(op->value()->as_register(), skip);
1530 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1531 __ bind(skip);
1532 }
1533 }
1534
1535 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1536 // We are storing into an array that *may* be null-free (the declared type is
1537 // Object[], abstract[], interface[] or VT.ref[]).
1538 Label test_mark_word;
1539 Register tmp = op->tmp()->as_register();
1540 __ ldr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
1541 __ tst(tmp, markWord::unlocked_value);
1542 __ br(Assembler::NE, test_mark_word);
1543 __ load_prototype_header(tmp, op->array()->as_register());
1544 __ bind(test_mark_word);
1545 __ tst(tmp, markWord::null_free_array_bit_in_place);
1546 }
1547
1548 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1549 Label L_oops_equal;
1550 Label L_oops_not_equal;
1551 Label L_end;
1552
1553 Register left = op->left()->as_register();
1554 Register right = op->right()->as_register();
1555
1556 __ cmp(left, right);
1557 __ br(Assembler::EQ, L_oops_equal);
1558
1559 // (1) Null check -- if one of the operands is null, the other must not be null (because
1560 // the two references are not equal), so they are not substitutable,
1561 // FIXME: do null check only if the operand is nullable
1562 {
1563 __ cbz(left, L_oops_not_equal);
1564 __ cbz(right, L_oops_not_equal);
1565 }
1566
1567 ciKlass* left_klass = op->left_klass();
1568 ciKlass* right_klass = op->right_klass();
1569
1570 // (2) Inline type check -- if either of the operands is not a inline type,
1571 // they are not substitutable. We do this only if we are not sure that the
1572 // operands are inline type
1573 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node.
1574 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
1575 Register tmp1 = op->tmp1()->as_register();
1576 __ mov(tmp1, markWord::inline_type_pattern);
1577 __ ldr(rscratch1, Address(left, oopDesc::mark_offset_in_bytes()));
1578 __ andr(tmp1, tmp1, rscratch1);
1579 __ ldr(rscratch1, Address(right, oopDesc::mark_offset_in_bytes()));
1580 __ andr(tmp1, tmp1, rscratch1);
1581 __ cmp(tmp1, (u1)markWord::inline_type_pattern);
1582 __ br(Assembler::NE, L_oops_not_equal);
1583 }
1584
1585 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
1586 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) {
1587 // No need to load klass -- the operands are statically known to be the same inline klass.
1588 __ b(*op->stub()->entry());
1589 } else {
1590 Register left_klass_op = op->left_klass_op()->as_register();
1591 Register right_klass_op = op->right_klass_op()->as_register();
1592
1593 if (UseCompressedClassPointers) {
1594 __ ldrw(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1595 __ ldrw(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1596 __ cmpw(left_klass_op, right_klass_op);
1597 } else {
1598 __ ldr(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1599 __ ldr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1600 __ cmp(left_klass_op, right_klass_op);
1601 }
1602
1603 __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check
1604 // fall through to L_oops_not_equal
1605 }
1606
1607 __ bind(L_oops_not_equal);
1608 move(op->not_equal_result(), op->result_opr());
1609 __ b(L_end);
1610
1611 __ bind(L_oops_equal);
1612 move(op->equal_result(), op->result_opr());
1613 __ b(L_end);
1614
1615 // We've returned from the stub. R0 contains 0x0 IFF the two
1616 // operands are not substitutable. (Don't compare against 0x1 in case the
1617 // C compiler is naughty)
1618 __ bind(*op->stub()->continuation());
1619 __ cbz(r0, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1620 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
1621 // fall-through
1622 __ bind(L_end);
1623 }
1624
1625
1626 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1627 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1628 __ cset(rscratch1, Assembler::NE);
1629 __ membar(__ AnyAny);
1630 }
1631
1632 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1633 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1634 __ cset(rscratch1, Assembler::NE);
1635 __ membar(__ AnyAny);
1636 }
1637
1638
1639 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1640 Register addr;
1641 if (op->addr()->is_register()) {
1642 addr = as_reg(op->addr());
1643 } else {
1644 assert(op->addr()->is_address(), "what else?");
1645 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1646 assert(addr_ptr->disp() == 0, "need 0 disp");
1647 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1648 addr = as_reg(addr_ptr->base());
1649 }
1650 Register newval = as_reg(op->new_value());
1651 Register cmpval = as_reg(op->cmp_value());
1652
1653 if (op->code() == lir_cas_obj) {
1654 if (UseCompressedOops) {
1655 Register t1 = op->tmp1()->as_register();
1656 assert(op->tmp1()->is_valid(), "must be");
1657 __ encode_heap_oop(t1, cmpval);
1658 cmpval = t1;
1659 __ encode_heap_oop(rscratch2, newval);
1660 newval = rscratch2;
1661 casw(addr, newval, cmpval);
1662 } else {
1663 casl(addr, newval, cmpval);
1664 }
1665 } else if (op->code() == lir_cas_int) {
1666 casw(addr, newval, cmpval);
1667 } else {
1668 casl(addr, newval, cmpval);
1669 }
1670 }
1671
1672
1673 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1674 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1675 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1676
1677 Assembler::Condition acond, ncond;
1678 switch (condition) {
1679 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1680 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1681 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1682 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1683 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1684 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1685 case lir_cond_belowEqual:
1686 case lir_cond_aboveEqual:
1687 default: ShouldNotReachHere();
1688 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1689 }
1690
1691 assert(result->is_single_cpu() || result->is_double_cpu(),
1692 "expect single register for result");
1693 if (opr1->is_constant() && opr2->is_constant()
1694 && opr1->type() == T_INT && opr2->type() == T_INT) {
1695 jint val1 = opr1->as_jint();
1696 jint val2 = opr2->as_jint();
1697 if (val1 == 0 && val2 == 1) {
1698 __ cset(result->as_register(), ncond);
1699 return;
1700 } else if (val1 == 1 && val2 == 0) {
1701 __ cset(result->as_register(), acond);
1702 return;
1703 }
1704 }
1705
1706 if (opr1->is_constant() && opr2->is_constant()
1707 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1708 jlong val1 = opr1->as_jlong();
1709 jlong val2 = opr2->as_jlong();
1710 if (val1 == 0 && val2 == 1) {
1711 __ cset(result->as_register_lo(), ncond);
1712 return;
1713 } else if (val1 == 1 && val2 == 0) {
1714 __ cset(result->as_register_lo(), acond);
1715 return;
1716 }
1717 }
1718
1719 if (opr1->is_stack()) {
1720 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1721 opr1 = FrameMap::rscratch1_opr;
1722 } else if (opr1->is_constant()) {
1723 LIR_Opr tmp
1724 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1725 const2reg(opr1, tmp, lir_patch_none, nullptr);
1726 opr1 = tmp;
1727 }
1728
1729 if (opr2->is_stack()) {
1730 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1731 opr2 = FrameMap::rscratch2_opr;
1732 } else if (opr2->is_constant()) {
1733 LIR_Opr tmp
1734 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1735 const2reg(opr2, tmp, lir_patch_none, nullptr);
1736 opr2 = tmp;
1737 }
1738
1739 if (result->type() == T_LONG)
1740 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1741 else
1742 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1743 }
1744
1745 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1746 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1747
1748 if (left->is_single_cpu()) {
1749 Register lreg = left->as_register();
1750 Register dreg = as_reg(dest);
1751
1752 if (right->is_single_cpu()) {
1753 // cpu register - cpu register
1754
1755 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1756 "should be");
1757 Register rreg = right->as_register();
1758 switch (code) {
1759 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1760 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1761 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1762 default: ShouldNotReachHere();
1763 }
1764
1765 } else if (right->is_double_cpu()) {
1766 Register rreg = right->as_register_lo();
1767 // single_cpu + double_cpu: can happen with obj+long
1768 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1769 switch (code) {
1770 case lir_add: __ add(dreg, lreg, rreg); break;
1771 case lir_sub: __ sub(dreg, lreg, rreg); break;
1772 default: ShouldNotReachHere();
1773 }
1774 } else if (right->is_constant()) {
1775 // cpu register - constant
1776 jlong c;
1777
1778 // FIXME. This is fugly: we really need to factor all this logic.
1779 switch(right->type()) {
1780 case T_LONG:
1781 c = right->as_constant_ptr()->as_jlong();
1782 break;
1783 case T_INT:
1784 case T_ADDRESS:
1785 c = right->as_constant_ptr()->as_jint();
1786 break;
1787 default:
1788 ShouldNotReachHere();
1789 c = 0; // unreachable
1790 break;
1791 }
1792
1793 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1794 if (c == 0 && dreg == lreg) {
1795 COMMENT("effective nop elided");
1796 return;
1797 }
1798 switch(left->type()) {
1799 case T_INT:
1800 switch (code) {
1801 case lir_add: __ addw(dreg, lreg, c); break;
1802 case lir_sub: __ subw(dreg, lreg, c); break;
1803 default: ShouldNotReachHere();
1804 }
1805 break;
1806 case T_OBJECT:
1807 case T_ADDRESS:
1808 switch (code) {
1809 case lir_add: __ add(dreg, lreg, c); break;
1810 case lir_sub: __ sub(dreg, lreg, c); break;
1811 default: ShouldNotReachHere();
1812 }
1813 break;
1814 default:
1815 ShouldNotReachHere();
1816 }
1817 } else {
1818 ShouldNotReachHere();
1819 }
1820
1821 } else if (left->is_double_cpu()) {
1822 Register lreg_lo = left->as_register_lo();
1823
1824 if (right->is_double_cpu()) {
1825 // cpu register - cpu register
1826 Register rreg_lo = right->as_register_lo();
1827 switch (code) {
1828 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1829 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1830 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1831 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1832 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1833 default:
1834 ShouldNotReachHere();
1835 }
1836
1837 } else if (right->is_constant()) {
1838 jlong c = right->as_constant_ptr()->as_jlong();
1839 Register dreg = as_reg(dest);
1840 switch (code) {
1841 case lir_add:
1842 case lir_sub:
1843 if (c == 0 && dreg == lreg_lo) {
1844 COMMENT("effective nop elided");
1845 return;
1846 }
1847 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1848 break;
1849 case lir_div:
1850 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1851 if (c == 1) {
1852 // move lreg_lo to dreg if divisor is 1
1853 __ mov(dreg, lreg_lo);
1854 } else {
1855 unsigned int shift = log2i_exact(c);
1856 // use rscratch1 as intermediate result register
1857 __ asr(rscratch1, lreg_lo, 63);
1858 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1859 __ asr(dreg, rscratch1, shift);
1860 }
1861 break;
1862 case lir_rem:
1863 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1864 if (c == 1) {
1865 // move 0 to dreg if divisor is 1
1866 __ mov(dreg, zr);
1867 } else {
1868 // use rscratch1 as intermediate result register
1869 __ negs(rscratch1, lreg_lo);
1870 __ andr(dreg, lreg_lo, c - 1);
1871 __ andr(rscratch1, rscratch1, c - 1);
1872 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1873 }
1874 break;
1875 default:
1876 ShouldNotReachHere();
1877 }
1878 } else {
1879 ShouldNotReachHere();
1880 }
1881 } else if (left->is_single_fpu()) {
1882 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1883 switch (code) {
1884 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1885 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1886 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1887 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1888 default:
1889 ShouldNotReachHere();
1890 }
1891 } else if (left->is_double_fpu()) {
1892 if (right->is_double_fpu()) {
1893 // fpu register - fpu register
1894 switch (code) {
1895 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1896 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1897 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1898 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1899 default:
1900 ShouldNotReachHere();
1901 }
1902 } else {
1903 if (right->is_constant()) {
1904 ShouldNotReachHere();
1905 }
1906 ShouldNotReachHere();
1907 }
1908 } else if (left->is_single_stack() || left->is_address()) {
1909 assert(left == dest, "left and dest must be equal");
1910 ShouldNotReachHere();
1911 } else {
1912 ShouldNotReachHere();
1913 }
1914 }
1915
1916 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1917 switch(code) {
1918 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1919 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1920 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1921 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1922 default : ShouldNotReachHere();
1923 }
1924 }
1925
1926 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1927
1928 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1929 Register Rleft = left->is_single_cpu() ? left->as_register() :
1930 left->as_register_lo();
1931 if (dst->is_single_cpu()) {
1932 Register Rdst = dst->as_register();
1933 if (right->is_constant()) {
1934 switch (code) {
1935 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1936 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1937 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1938 default: ShouldNotReachHere(); break;
1939 }
1940 } else {
1941 Register Rright = right->is_single_cpu() ? right->as_register() :
1942 right->as_register_lo();
1943 switch (code) {
1944 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1945 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1946 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1947 default: ShouldNotReachHere(); break;
1948 }
1949 }
1950 } else {
1951 Register Rdst = dst->as_register_lo();
1952 if (right->is_constant()) {
1953 switch (code) {
1954 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1955 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1956 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1957 default: ShouldNotReachHere(); break;
1958 }
1959 } else {
1960 Register Rright = right->is_single_cpu() ? right->as_register() :
1961 right->as_register_lo();
1962 switch (code) {
1963 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1964 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1965 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1966 default: ShouldNotReachHere(); break;
1967 }
1968 }
1969 }
1970 }
1971
1972
1973
1974 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1975
1976 // opcode check
1977 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1978 bool is_irem = (code == lir_irem);
1979
1980 // operand check
1981 assert(left->is_single_cpu(), "left must be register");
1982 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1983 assert(result->is_single_cpu(), "result must be register");
1984 Register lreg = left->as_register();
1985 Register dreg = result->as_register();
1986
1987 // power-of-2 constant check and codegen
1988 if (right->is_constant()) {
1989 int c = right->as_constant_ptr()->as_jint();
1990 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1991 if (is_irem) {
1992 if (c == 1) {
1993 // move 0 to dreg if divisor is 1
1994 __ movw(dreg, zr);
1995 } else {
1996 // use rscratch1 as intermediate result register
1997 __ negsw(rscratch1, lreg);
1998 __ andw(dreg, lreg, c - 1);
1999 __ andw(rscratch1, rscratch1, c - 1);
2000 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
2001 }
2002 } else {
2003 if (c == 1) {
2004 // move lreg to dreg if divisor is 1
2005 __ movw(dreg, lreg);
2006 } else {
2007 unsigned int shift = exact_log2(c);
2008 // use rscratch1 as intermediate result register
2009 __ asrw(rscratch1, lreg, 31);
2010 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
2011 __ asrw(dreg, rscratch1, shift);
2012 }
2013 }
2014 } else {
2015 Register rreg = right->as_register();
2016 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
2017 }
2018 }
2019
2020
2021 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2022 if (opr1->is_constant() && opr2->is_single_cpu()) {
2023 // tableswitch
2024 Register reg = as_reg(opr2);
2025 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
2026 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
2027 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
2028 Register reg1 = as_reg(opr1);
2029 if (opr2->is_single_cpu()) {
2030 // cpu register - cpu register
2031 Register reg2 = opr2->as_register();
2032 if (is_reference_type(opr1->type())) {
2033 __ cmpoop(reg1, reg2);
2034 } else {
2035 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2036 __ cmpw(reg1, reg2);
2037 }
2038 return;
2039 }
2040 if (opr2->is_double_cpu()) {
2041 // cpu register - cpu register
2042 Register reg2 = opr2->as_register_lo();
2043 __ cmp(reg1, reg2);
2044 return;
2045 }
2046
2047 if (opr2->is_constant()) {
2048 bool is_32bit = false; // width of register operand
2049 jlong imm;
2050
2051 switch(opr2->type()) {
2052 case T_INT:
2053 imm = opr2->as_constant_ptr()->as_jint();
2054 is_32bit = true;
2055 break;
2056 case T_LONG:
2057 imm = opr2->as_constant_ptr()->as_jlong();
2058 break;
2059 case T_ADDRESS:
2060 imm = opr2->as_constant_ptr()->as_jint();
2061 break;
2062 case T_METADATA:
2063 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
2064 break;
2065 case T_OBJECT:
2066 case T_ARRAY:
2067 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
2068 __ cmpoop(reg1, rscratch1);
2069 return;
2070 default:
2071 ShouldNotReachHere();
2072 imm = 0; // unreachable
2073 break;
2074 }
2075
2076 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
2077 if (is_32bit)
2078 __ cmpw(reg1, imm);
2079 else
2080 __ subs(zr, reg1, imm);
2081 return;
2082 } else {
2083 __ mov(rscratch1, imm);
2084 if (is_32bit)
2085 __ cmpw(reg1, rscratch1);
2086 else
2087 __ cmp(reg1, rscratch1);
2088 return;
2089 }
2090 } else
2091 ShouldNotReachHere();
2092 } else if (opr1->is_single_fpu()) {
2093 FloatRegister reg1 = opr1->as_float_reg();
2094 assert(opr2->is_single_fpu(), "expect single float register");
2095 FloatRegister reg2 = opr2->as_float_reg();
2096 __ fcmps(reg1, reg2);
2097 } else if (opr1->is_double_fpu()) {
2098 FloatRegister reg1 = opr1->as_double_reg();
2099 assert(opr2->is_double_fpu(), "expect double float register");
2100 FloatRegister reg2 = opr2->as_double_reg();
2101 __ fcmpd(reg1, reg2);
2102 } else {
2103 ShouldNotReachHere();
2104 }
2105 }
2106
2107 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2108 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2109 bool is_unordered_less = (code == lir_ucmp_fd2i);
2110 if (left->is_single_fpu()) {
2111 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2112 } else if (left->is_double_fpu()) {
2113 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2114 } else {
2115 ShouldNotReachHere();
2116 }
2117 } else if (code == lir_cmp_l2i) {
2118 Label done;
2119 __ cmp(left->as_register_lo(), right->as_register_lo());
2120 __ mov(dst->as_register(), (uint64_t)-1L);
2121 __ br(Assembler::LT, done);
2122 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2123 __ bind(done);
2124 } else {
2125 ShouldNotReachHere();
2126 }
2127 }
2128
2129
2130 void LIR_Assembler::align_call(LIR_Code code) { }
2131
2132
2133 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2134 address call = __ trampoline_call(Address(op->addr(), rtype));
2135 if (call == nullptr) {
2136 bailout("trampoline stub overflow");
2137 return;
2138 }
2139 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2140 __ post_call_nop();
2141 }
2142
2143
2144 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2145 address call = __ ic_call(op->addr());
2146 if (call == nullptr) {
2147 bailout("trampoline stub overflow");
2148 return;
2149 }
2150 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2151 __ post_call_nop();
2152 }
2153
2154 void LIR_Assembler::emit_static_call_stub() {
2155 address call_pc = __ pc();
2156 address stub = __ start_a_stub(call_stub_size());
2157 if (stub == nullptr) {
2158 bailout("static call stub overflow");
2159 return;
2160 }
2161
2162 int start = __ offset();
2163
2164 __ relocate(static_stub_Relocation::spec(call_pc));
2165 __ emit_static_call_stub();
2166
2167 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2168 <= call_stub_size(), "stub too big");
2169 __ end_a_stub();
2170 }
2171
2172
2173 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2174 assert(exceptionOop->as_register() == r0, "must match");
2175 assert(exceptionPC->as_register() == r3, "must match");
2176
2177 // exception object is not added to oop map by LinearScan
2178 // (LinearScan assumes that no oops are in fixed registers)
2179 info->add_register_oop(exceptionOop);
2180 StubId unwind_id;
2181
2182 // get current pc information
2183 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2184 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2185 // As no instructions have been generated yet for this LIR node it's
2186 // possible that an oop map already exists for the current offset.
2187 // In that case insert an dummy NOP here to ensure all oop map PCs
2188 // are unique. See JDK-8237483.
2189 __ nop();
2190 }
2191 int pc_for_athrow_offset = __ offset();
2192 InternalAddress pc_for_athrow(__ pc());
2193 __ adr(exceptionPC->as_register(), pc_for_athrow);
2194 add_call_info(pc_for_athrow_offset, info); // for exception handler
2195
2196 __ verify_not_null_oop(r0);
2197 // search an exception handler (r0: exception oop, r3: throwing pc)
2198 if (compilation()->has_fpu_code()) {
2199 unwind_id = StubId::c1_handle_exception_id;
2200 } else {
2201 unwind_id = StubId::c1_handle_exception_nofpu_id;
2202 }
2203 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2204
2205 // FIXME: enough room for two byte trap ????
2206 __ nop();
2207 }
2208
2209
2210 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2211 assert(exceptionOop->as_register() == r0, "must match");
2212
2213 __ b(_unwind_handler_entry);
2214 }
2215
2216
2217 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2218 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2219 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2220
2221 switch (left->type()) {
2222 case T_INT: {
2223 switch (code) {
2224 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2225 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2226 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2227 default:
2228 ShouldNotReachHere();
2229 break;
2230 }
2231 break;
2232 case T_LONG:
2233 case T_ADDRESS:
2234 case T_OBJECT:
2235 switch (code) {
2236 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2237 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2238 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2239 default:
2240 ShouldNotReachHere();
2241 break;
2242 }
2243 break;
2244 default:
2245 ShouldNotReachHere();
2246 break;
2247 }
2248 }
2249 }
2250
2251
2252 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2253 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2254 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2255
2256 switch (left->type()) {
2257 case T_INT: {
2258 switch (code) {
2259 case lir_shl: __ lslw (dreg, lreg, count); break;
2260 case lir_shr: __ asrw (dreg, lreg, count); break;
2261 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2262 default:
2263 ShouldNotReachHere();
2264 break;
2265 }
2266 break;
2267 case T_LONG:
2268 case T_ADDRESS:
2269 case T_OBJECT:
2270 switch (code) {
2271 case lir_shl: __ lsl (dreg, lreg, count); break;
2272 case lir_shr: __ asr (dreg, lreg, count); break;
2273 case lir_ushr: __ lsr (dreg, lreg, count); break;
2274 default:
2275 ShouldNotReachHere();
2276 break;
2277 }
2278 break;
2279 default:
2280 ShouldNotReachHere();
2281 break;
2282 }
2283 }
2284 }
2285
2286
2287 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2288 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2289 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2290 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2291 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2292 }
2293
2294
2295 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2296 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2297 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2298 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2299 __ mov (rscratch1, c);
2300 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2301 }
2302
2303
2304 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2305 ShouldNotReachHere();
2306 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2307 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2308 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2309 __ lea(rscratch1, __ constant_oop_address(o));
2310 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2311 }
2312
2313 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
2314 if (null_check) {
2315 __ cbz(obj, *slow_path->entry());
2316 }
2317 if (is_dest) {
2318 __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
2319 // TODO 8350865 Flat no longer implies null-free, so we need to check for flat dest. Can we do better here?
2320 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2321 } else {
2322 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2323 }
2324 }
2325
2326 // This code replaces a call to arraycopy; no exception may
2327 // be thrown in this code, they must be thrown in the System.arraycopy
2328 // activation frame; we could save some checks if this would not be the case
2329 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2330 ciArrayKlass* default_type = op->expected_type();
2331 Register src = op->src()->as_register();
2332 Register dst = op->dst()->as_register();
2333 Register src_pos = op->src_pos()->as_register();
2334 Register dst_pos = op->dst_pos()->as_register();
2335 Register length = op->length()->as_register();
2336 Register tmp = op->tmp()->as_register();
2337
2338 CodeStub* stub = op->stub();
2339 int flags = op->flags();
2340 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2341 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2342
2343 if (flags & LIR_OpArrayCopy::always_slow_path) {
2344 __ b(*stub->entry());
2345 __ bind(*stub->continuation());
2346 return;
2347 }
2348
2349 // if we don't know anything, just go through the generic arraycopy
2350 if (default_type == nullptr // || basic_type == T_OBJECT
2351 ) {
2352 Label done;
2353 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2354
2355 // Save the arguments in case the generic arraycopy fails and we
2356 // have to fall back to the JNI stub
2357 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2358 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2359 __ str(src, Address(sp, 4*BytesPerWord));
2360
2361 address copyfunc_addr = StubRoutines::generic_arraycopy();
2362 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2363
2364 // The arguments are in java calling convention so we shift them
2365 // to C convention
2366 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2367 __ mov(c_rarg0, j_rarg0);
2368 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2369 __ mov(c_rarg1, j_rarg1);
2370 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2371 __ mov(c_rarg2, j_rarg2);
2372 assert_different_registers(c_rarg3, j_rarg4);
2373 __ mov(c_rarg3, j_rarg3);
2374 __ mov(c_rarg4, j_rarg4);
2375 #ifndef PRODUCT
2376 if (PrintC1Statistics) {
2377 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2378 }
2379 #endif
2380 __ far_call(RuntimeAddress(copyfunc_addr));
2381
2382 __ cbz(r0, *stub->continuation());
2383
2384 // Reload values from the stack so they are where the stub
2385 // expects them.
2386 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2387 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2388 __ ldr(src, Address(sp, 4*BytesPerWord));
2389
2390 // r0 is -1^K where K == partial copied count
2391 __ eonw(rscratch1, r0, zr);
2392 // adjust length down and src/end pos up by partial copied count
2393 __ subw(length, length, rscratch1);
2394 __ addw(src_pos, src_pos, rscratch1);
2395 __ addw(dst_pos, dst_pos, rscratch1);
2396 __ b(*stub->entry());
2397
2398 __ bind(*stub->continuation());
2399 return;
2400 }
2401
2402 // Handle inline type arrays
2403 if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
2404 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
2405 }
2406 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
2407 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
2408 }
2409
2410 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2411
2412 int elem_size = type2aelembytes(basic_type);
2413 int scale = exact_log2(elem_size);
2414
2415 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2416 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2417
2418 // test for null
2419 if (flags & LIR_OpArrayCopy::src_null_check) {
2420 __ cbz(src, *stub->entry());
2421 }
2422 if (flags & LIR_OpArrayCopy::dst_null_check) {
2423 __ cbz(dst, *stub->entry());
2424 }
2425
2426 // If the compiler was not able to prove that exact type of the source or the destination
2427 // of the arraycopy is an array type, check at runtime if the source or the destination is
2428 // an instance type.
2429 if (flags & LIR_OpArrayCopy::type_check) {
2430 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2431 __ load_klass(tmp, dst);
2432 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2433 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2434 __ br(Assembler::GE, *stub->entry());
2435 }
2436
2437 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2438 __ load_klass(tmp, src);
2439 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2440 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2441 __ br(Assembler::GE, *stub->entry());
2442 }
2443 }
2444
2445 // check if negative
2446 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2447 __ cmpw(src_pos, 0);
2448 __ br(Assembler::LT, *stub->entry());
2449 }
2450 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2451 __ cmpw(dst_pos, 0);
2452 __ br(Assembler::LT, *stub->entry());
2453 }
2454
2455 if (flags & LIR_OpArrayCopy::length_positive_check) {
2456 __ cmpw(length, 0);
2457 __ br(Assembler::LT, *stub->entry());
2458 }
2459
2460 if (flags & LIR_OpArrayCopy::src_range_check) {
2461 __ addw(tmp, src_pos, length);
2462 __ ldrw(rscratch1, src_length_addr);
2463 __ cmpw(tmp, rscratch1);
2464 __ br(Assembler::HI, *stub->entry());
2465 }
2466 if (flags & LIR_OpArrayCopy::dst_range_check) {
2467 __ addw(tmp, dst_pos, length);
2468 __ ldrw(rscratch1, dst_length_addr);
2469 __ cmpw(tmp, rscratch1);
2470 __ br(Assembler::HI, *stub->entry());
2471 }
2472
2473 if (flags & LIR_OpArrayCopy::type_check) {
2474 // We don't know the array types are compatible
2475 if (basic_type != T_OBJECT) {
2476 // Simple test for basic type arrays
2477 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2478 __ br(Assembler::NE, *stub->entry());
2479 } else {
2480 // For object arrays, if src is a sub class of dst then we can
2481 // safely do the copy.
2482 Label cont, slow;
2483
2484 #define PUSH(r1, r2) \
2485 stp(r1, r2, __ pre(sp, -2 * wordSize));
2486
2487 #define POP(r1, r2) \
2488 ldp(r1, r2, __ post(sp, 2 * wordSize));
2489
2490 __ PUSH(src, dst);
2491
2492 __ load_klass(src, src);
2493 __ load_klass(dst, dst);
2494
2495 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2496
2497 __ PUSH(src, dst);
2498 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2499 __ POP(src, dst);
2500
2501 __ cbnz(src, cont);
2502
2503 __ bind(slow);
2504 __ POP(src, dst);
2505
2506 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2507 if (copyfunc_addr != nullptr) { // use stub if available
2508 // src is not a sub class of dst so we have to do a
2509 // per-element check.
2510
2511 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2512 if ((flags & mask) != mask) {
2513 // Check that at least both of them object arrays.
2514 assert(flags & mask, "one of the two should be known to be an object array");
2515
2516 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2517 __ load_klass(tmp, src);
2518 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2519 __ load_klass(tmp, dst);
2520 }
2521 int lh_offset = in_bytes(Klass::layout_helper_offset());
2522 Address klass_lh_addr(tmp, lh_offset);
2523 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2524 __ ldrw(rscratch1, klass_lh_addr);
2525 __ mov(rscratch2, objArray_lh);
2526 __ eorw(rscratch1, rscratch1, rscratch2);
2527 __ cbnzw(rscratch1, *stub->entry());
2528 }
2529
2530 // Spill because stubs can use any register they like and it's
2531 // easier to restore just those that we care about.
2532 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2533 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2534 __ str(src, Address(sp, 4*BytesPerWord));
2535
2536 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2537 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2538 assert_different_registers(c_rarg0, dst, dst_pos, length);
2539 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2540 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2541 assert_different_registers(c_rarg1, dst, length);
2542 __ uxtw(c_rarg2, length);
2543 assert_different_registers(c_rarg2, dst);
2544
2545 __ load_klass(c_rarg4, dst);
2546 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2547 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2548 __ far_call(RuntimeAddress(copyfunc_addr));
2549
2550 #ifndef PRODUCT
2551 if (PrintC1Statistics) {
2552 Label failed;
2553 __ cbnz(r0, failed);
2554 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2555 __ bind(failed);
2556 }
2557 #endif
2558
2559 __ cbz(r0, *stub->continuation());
2560
2561 #ifndef PRODUCT
2562 if (PrintC1Statistics) {
2563 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2564 }
2565 #endif
2566 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2567
2568 // Restore previously spilled arguments
2569 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2570 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2571 __ ldr(src, Address(sp, 4*BytesPerWord));
2572
2573 // return value is -1^K where K is partial copied count
2574 __ eonw(rscratch1, r0, zr);
2575 // adjust length down and src/end pos up by partial copied count
2576 __ subw(length, length, rscratch1);
2577 __ addw(src_pos, src_pos, rscratch1);
2578 __ addw(dst_pos, dst_pos, rscratch1);
2579 }
2580
2581 __ b(*stub->entry());
2582
2583 __ bind(cont);
2584 __ POP(src, dst);
2585 }
2586 }
2587
2588 #ifdef ASSERT
2589 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2590 // Sanity check the known type with the incoming class. For the
2591 // primitive case the types must match exactly with src.klass and
2592 // dst.klass each exactly matching the default type. For the
2593 // object array case, if no type check is needed then either the
2594 // dst type is exactly the expected type and the src type is a
2595 // subtype which we can't check or src is the same array as dst
2596 // but not necessarily exactly of type default_type.
2597 Label known_ok, halt;
2598 __ mov_metadata(tmp, default_type->constant_encoding());
2599
2600 if (basic_type != T_OBJECT) {
2601 __ cmp_klass(dst, tmp, rscratch1);
2602 __ br(Assembler::NE, halt);
2603 __ cmp_klass(src, tmp, rscratch1);
2604 __ br(Assembler::EQ, known_ok);
2605 } else {
2606 __ cmp_klass(dst, tmp, rscratch1);
2607 __ br(Assembler::EQ, known_ok);
2608 __ cmp(src, dst);
2609 __ br(Assembler::EQ, known_ok);
2610 }
2611 __ bind(halt);
2612 __ stop("incorrect type information in arraycopy");
2613 __ bind(known_ok);
2614 }
2615 #endif
2616
2617 #ifndef PRODUCT
2618 if (PrintC1Statistics) {
2619 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2620 }
2621 #endif
2622
2623 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2624 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2625 assert_different_registers(c_rarg0, dst, dst_pos, length);
2626 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2627 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2628 assert_different_registers(c_rarg1, dst, length);
2629 __ uxtw(c_rarg2, length);
2630 assert_different_registers(c_rarg2, dst);
2631
2632 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2633 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2634 const char *name;
2635 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2636
2637 CodeBlob *cb = CodeCache::find_blob(entry);
2638 if (cb) {
2639 __ far_call(RuntimeAddress(entry));
2640 } else {
2641 __ call_VM_leaf(entry, 3);
2642 }
2643
2644 if (stub != nullptr) {
2645 __ bind(*stub->continuation());
2646 }
2647 }
2648
2649
2650
2651
2652 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2653 Register obj = op->obj_opr()->as_register(); // may not be an oop
2654 Register hdr = op->hdr_opr()->as_register();
2655 Register lock = op->lock_opr()->as_register();
2656 Register temp = op->scratch_opr()->as_register();
2657 if (op->code() == lir_lock) {
2658 // add debug info for NullPointerException only if one is possible
2659 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2660 if (op->info() != nullptr) {
2661 add_debug_info_for_null_check(null_check_offset, op->info());
2662 }
2663 // done
2664 } else if (op->code() == lir_unlock) {
2665 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2666 } else {
2667 Unimplemented();
2668 }
2669 __ bind(*op->stub()->continuation());
2670 }
2671
2672 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2673 Register obj = op->obj()->as_pointer_register();
2674 Register result = op->result_opr()->as_pointer_register();
2675
2676 CodeEmitInfo* info = op->info();
2677 if (info != nullptr) {
2678 add_debug_info_for_null_check_here(info);
2679 }
2680
2681 __ load_klass(result, obj);
2682 }
2683
2684 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2685 ciMethod* method = op->profiled_method();
2686 int bci = op->profiled_bci();
2687 ciMethod* callee = op->profiled_callee();
2688
2689 // Update counter for all call types
2690 ciMethodData* md = method->method_data_or_null();
2691 assert(md != nullptr, "Sanity");
2692 ciProfileData* data = md->bci_to_data(bci);
2693 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2694 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2695 Register mdo = op->mdo()->as_register();
2696 __ mov_metadata(mdo, md->constant_encoding());
2697 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2698 // Perform additional virtual call profiling for invokevirtual and
2699 // invokeinterface bytecodes
2700 if (op->should_profile_receiver_type()) {
2701 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2702 Register recv = op->recv()->as_register();
2703 assert_different_registers(mdo, recv);
2704 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2705 ciKlass* known_klass = op->known_holder();
2706 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2707 // We know the type that will be seen at this call site; we can
2708 // statically update the MethodData* rather than needing to do
2709 // dynamic tests on the receiver type.
2710 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2711 for (uint i = 0; i < VirtualCallData::row_limit(); i++) {
2712 ciKlass* receiver = vc_data->receiver(i);
2713 if (known_klass->equals(receiver)) {
2714 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2715 __ addptr(data_addr, DataLayout::counter_increment);
2716 return;
2717 }
2718 }
2719 // Receiver type is not found in profile data.
2720 // Fall back to runtime helper to handle the rest at runtime.
2721 __ mov_metadata(recv, known_klass->constant_encoding());
2722 } else {
2723 __ load_klass(recv, recv);
2724 }
2725 type_profile_helper(mdo, md, data, recv);
2726 } else {
2727 // Static call
2728 __ addptr(counter_addr, DataLayout::counter_increment);
2729 }
2730 }
2731
2732
2733 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2734 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2735 }
2736
2737 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2738 assert(op->crc()->is_single_cpu(), "crc must be register");
2739 assert(op->val()->is_single_cpu(), "byte value must be register");
2740 assert(op->result_opr()->is_single_cpu(), "result must be register");
2741 Register crc = op->crc()->as_register();
2742 Register val = op->val()->as_register();
2743 Register res = op->result_opr()->as_register();
2744
2745 assert_different_registers(val, crc, res);
2746 uint64_t offset;
2747 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2748 __ add(res, res, offset);
2749
2750 __ mvnw(crc, crc); // ~crc
2751 __ update_byte_crc32(crc, val, res);
2752 __ mvnw(res, crc); // ~crc
2753 }
2754
2755 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2756 COMMENT("emit_profile_type {");
2757 Register obj = op->obj()->as_register();
2758 Register tmp = op->tmp()->as_pointer_register();
2759 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2760 ciKlass* exact_klass = op->exact_klass();
2761 intptr_t current_klass = op->current_klass();
2762 bool not_null = op->not_null();
2763 bool no_conflict = op->no_conflict();
2764
2765 Label update, next, none;
2766
2767 bool do_null = !not_null;
2768 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2769 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2770
2771 assert(do_null || do_update, "why are we here?");
2772 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2773 assert(mdo_addr.base() != rscratch1, "wrong register");
2774
2775 __ verify_oop(obj);
2776
2777 if (tmp != obj) {
2778 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2779 __ mov(tmp, obj);
2780 } else {
2781 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2782 }
2783 if (do_null) {
2784 __ cbnz(tmp, update);
2785 if (!TypeEntries::was_null_seen(current_klass)) {
2786 __ ldr(rscratch2, mdo_addr);
2787 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2788 __ str(rscratch2, mdo_addr);
2789 }
2790 if (do_update) {
2791 #ifndef ASSERT
2792 __ b(next);
2793 }
2794 #else
2795 __ b(next);
2796 }
2797 } else {
2798 __ cbnz(tmp, update);
2799 __ stop("unexpected null obj");
2800 #endif
2801 }
2802
2803 __ bind(update);
2804
2805 if (do_update) {
2806 #ifdef ASSERT
2807 if (exact_klass != nullptr) {
2808 Label ok;
2809 __ load_klass(tmp, tmp);
2810 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2811 __ eor(rscratch1, tmp, rscratch1);
2812 __ cbz(rscratch1, ok);
2813 __ stop("exact klass and actual klass differ");
2814 __ bind(ok);
2815 }
2816 #endif
2817 if (!no_conflict) {
2818 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2819 if (exact_klass != nullptr) {
2820 __ mov_metadata(tmp, exact_klass->constant_encoding());
2821 } else {
2822 __ load_klass(tmp, tmp);
2823 }
2824
2825 __ ldr(rscratch2, mdo_addr);
2826 __ eor(tmp, tmp, rscratch2);
2827 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2828 // klass seen before, nothing to do. The unknown bit may have been
2829 // set already but no need to check.
2830 __ cbz(rscratch1, next);
2831
2832 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2833
2834 if (TypeEntries::is_type_none(current_klass)) {
2835 __ cbz(rscratch2, none);
2836 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2837 __ br(Assembler::EQ, none);
2838 // There is a chance that the checks above
2839 // fail if another thread has just set the
2840 // profiling to this obj's klass
2841 __ dmb(Assembler::ISHLD);
2842 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2843 __ ldr(rscratch2, mdo_addr);
2844 __ eor(tmp, tmp, rscratch2);
2845 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2846 __ cbz(rscratch1, next);
2847 }
2848 } else {
2849 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2850 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2851
2852 __ ldr(tmp, mdo_addr);
2853 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2854 }
2855
2856 // different than before. Cannot keep accurate profile.
2857 __ ldr(rscratch2, mdo_addr);
2858 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2859 __ str(rscratch2, mdo_addr);
2860
2861 if (TypeEntries::is_type_none(current_klass)) {
2862 __ b(next);
2863
2864 __ bind(none);
2865 // first time here. Set profile type.
2866 __ str(tmp, mdo_addr);
2867 #ifdef ASSERT
2868 __ andr(tmp, tmp, TypeEntries::type_mask);
2869 __ verify_klass_ptr(tmp);
2870 #endif
2871 }
2872 } else {
2873 // There's a single possible klass at this profile point
2874 assert(exact_klass != nullptr, "should be");
2875 if (TypeEntries::is_type_none(current_klass)) {
2876 __ mov_metadata(tmp, exact_klass->constant_encoding());
2877 __ ldr(rscratch2, mdo_addr);
2878 __ eor(tmp, tmp, rscratch2);
2879 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2880 __ cbz(rscratch1, next);
2881 #ifdef ASSERT
2882 {
2883 Label ok;
2884 __ ldr(rscratch1, mdo_addr);
2885 __ cbz(rscratch1, ok);
2886 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2887 __ br(Assembler::EQ, ok);
2888 // may have been set by another thread
2889 __ dmb(Assembler::ISHLD);
2890 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2891 __ ldr(rscratch2, mdo_addr);
2892 __ eor(rscratch2, rscratch1, rscratch2);
2893 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2894 __ cbz(rscratch2, ok);
2895
2896 __ stop("unexpected profiling mismatch");
2897 __ bind(ok);
2898 }
2899 #endif
2900 // first time here. Set profile type.
2901 __ str(tmp, mdo_addr);
2902 #ifdef ASSERT
2903 __ andr(tmp, tmp, TypeEntries::type_mask);
2904 __ verify_klass_ptr(tmp);
2905 #endif
2906 } else {
2907 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2908 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2909
2910 __ ldr(tmp, mdo_addr);
2911 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2912
2913 __ orr(tmp, tmp, TypeEntries::type_unknown);
2914 __ str(tmp, mdo_addr);
2915 // FIXME: Write barrier needed here?
2916 }
2917 }
2918
2919 __ bind(next);
2920 }
2921 COMMENT("} emit_profile_type");
2922 }
2923
2924 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
2925 Register obj = op->obj()->as_register();
2926 Register tmp = op->tmp()->as_pointer_register();
2927 bool not_null = op->not_null();
2928 int flag = op->flag();
2929
2930 Label not_inline_type;
2931 if (!not_null) {
2932 __ cbz(obj, not_inline_type);
2933 }
2934
2935 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
2936
2937 Address mdo_addr = as_Address(op->mdp()->as_address_ptr(), rscratch2);
2938 __ ldrb(rscratch1, mdo_addr);
2939 __ orr(rscratch1, rscratch1, flag);
2940 __ strb(rscratch1, mdo_addr);
2941
2942 __ bind(not_inline_type);
2943 }
2944
2945 void LIR_Assembler::align_backward_branch_target() {
2946 }
2947
2948
2949 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2950 // tmp must be unused
2951 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2952
2953 if (left->is_single_cpu()) {
2954 assert(dest->is_single_cpu(), "expect single result reg");
2955 __ negw(dest->as_register(), left->as_register());
2956 } else if (left->is_double_cpu()) {
2957 assert(dest->is_double_cpu(), "expect double result reg");
2958 __ neg(dest->as_register_lo(), left->as_register_lo());
2959 } else if (left->is_single_fpu()) {
2960 assert(dest->is_single_fpu(), "expect single float result reg");
2961 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2962 } else {
2963 assert(left->is_double_fpu(), "expect double float operand reg");
2964 assert(dest->is_double_fpu(), "expect double float result reg");
2965 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2966 }
2967 }
2968
2969
2970 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2971 if (patch_code != lir_patch_none) {
2972 deoptimize_trap(info);
2973 return;
2974 }
2975
2976 __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
2977 }
2978
2979
2980 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2981 assert(!tmp->is_valid(), "don't need temporary");
2982
2983 CodeBlob *cb = CodeCache::find_blob(dest);
2984 if (cb) {
2985 __ far_call(RuntimeAddress(dest));
2986 } else {
2987 __ mov(rscratch1, RuntimeAddress(dest));
2988 __ blr(rscratch1);
2989 }
2990
2991 if (info != nullptr) {
2992 add_call_info_here(info);
2993 }
2994 __ post_call_nop();
2995 }
2996
2997 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2998 if (dest->is_address() || src->is_address()) {
2999 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
3000 } else {
3001 ShouldNotReachHere();
3002 }
3003 }
3004
3005 #ifdef ASSERT
3006 // emit run-time assertion
3007 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3008 assert(op->code() == lir_assert, "must be");
3009
3010 if (op->in_opr1()->is_valid()) {
3011 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3012 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3013 } else {
3014 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3015 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3016 }
3017
3018 Label ok;
3019 if (op->condition() != lir_cond_always) {
3020 Assembler::Condition acond = Assembler::AL;
3021 switch (op->condition()) {
3022 case lir_cond_equal: acond = Assembler::EQ; break;
3023 case lir_cond_notEqual: acond = Assembler::NE; break;
3024 case lir_cond_less: acond = Assembler::LT; break;
3025 case lir_cond_lessEqual: acond = Assembler::LE; break;
3026 case lir_cond_greaterEqual: acond = Assembler::GE; break;
3027 case lir_cond_greater: acond = Assembler::GT; break;
3028 case lir_cond_belowEqual: acond = Assembler::LS; break;
3029 case lir_cond_aboveEqual: acond = Assembler::HS; break;
3030 default: ShouldNotReachHere();
3031 }
3032 __ br(acond, ok);
3033 }
3034 if (op->halt()) {
3035 const char* str = __ code_string(op->msg());
3036 __ stop(str);
3037 } else {
3038 breakpoint();
3039 }
3040 __ bind(ok);
3041 }
3042 #endif
3043
3044 #ifndef PRODUCT
3045 #define COMMENT(x) do { __ block_comment(x); } while (0)
3046 #else
3047 #define COMMENT(x)
3048 #endif
3049
3050 void LIR_Assembler::membar() {
3051 COMMENT("membar");
3052 __ membar(MacroAssembler::AnyAny);
3053 }
3054
3055 void LIR_Assembler::membar_acquire() {
3056 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
3057 }
3058
3059 void LIR_Assembler::membar_release() {
3060 __ membar(Assembler::LoadStore|Assembler::StoreStore);
3061 }
3062
3063 void LIR_Assembler::membar_loadload() {
3064 __ membar(Assembler::LoadLoad);
3065 }
3066
3067 void LIR_Assembler::membar_storestore() {
3068 __ membar(MacroAssembler::StoreStore);
3069 }
3070
3071 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3072
3073 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3074
3075 void LIR_Assembler::on_spin_wait() {
3076 __ spin_wait();
3077 }
3078
3079 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3080 __ mov(result_reg->as_register(), rthread);
3081 }
3082
3083 void LIR_Assembler::check_orig_pc() {
3084 __ ldr(rscratch2, frame_map()->address_for_orig_pc_addr());
3085 __ cmp(rscratch2, (u1)NULL_WORD);
3086 }
3087
3088 void LIR_Assembler::peephole(LIR_List *lir) {
3089 #if 0
3090 if (tableswitch_count >= max_tableswitches)
3091 return;
3092
3093 /*
3094 This finite-state automaton recognizes sequences of compare-and-
3095 branch instructions. We will turn them into a tableswitch. You
3096 could argue that C1 really shouldn't be doing this sort of
3097 optimization, but without it the code is really horrible.
3098 */
3099
3100 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3101 int first_key, last_key = -2147483648;
3102 int next_key = 0;
3103 int start_insn = -1;
3104 int last_insn = -1;
3105 Register reg = noreg;
3106 LIR_Opr reg_opr;
3107 state = start_s;
3108
3109 LIR_OpList* inst = lir->instructions_list();
3110 for (int i = 0; i < inst->length(); i++) {
3111 LIR_Op* op = inst->at(i);
3112 switch (state) {
3113 case start_s:
3114 first_key = -1;
3115 start_insn = i;
3116 switch (op->code()) {
3117 case lir_cmp:
3118 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3119 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3120 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3121 && opr2->is_constant()
3122 && opr2->type() == T_INT) {
3123 reg_opr = opr1;
3124 reg = opr1->as_register();
3125 first_key = opr2->as_constant_ptr()->as_jint();
3126 next_key = first_key + 1;
3127 state = cmp_s;
3128 goto next_state;
3129 }
3130 break;
3131 }
3132 break;
3133 case cmp_s:
3134 switch (op->code()) {
3135 case lir_branch:
3136 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3137 state = beq_s;
3138 last_insn = i;
3139 goto next_state;
3140 }
3141 }
3142 state = start_s;
3143 break;
3144 case beq_s:
3145 switch (op->code()) {
3146 case lir_cmp: {
3147 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3148 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3149 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3150 && opr1->as_register() == reg
3151 && opr2->is_constant()
3152 && opr2->type() == T_INT
3153 && opr2->as_constant_ptr()->as_jint() == next_key) {
3154 last_key = next_key;
3155 next_key++;
3156 state = cmp_s;
3157 goto next_state;
3158 }
3159 }
3160 }
3161 last_key = next_key;
3162 state = start_s;
3163 break;
3164 default:
3165 assert(false, "impossible state");
3166 }
3167 if (state == start_s) {
3168 if (first_key < last_key - 5L && reg != noreg) {
3169 {
3170 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3171 // reg->encoding(),
3172 // start_insn, first_key, last_key);
3173 // for (int i = 0; i < inst->length(); i++) {
3174 // inst->at(i)->print();
3175 // tty->print("\n");
3176 // }
3177 // tty->print("\n");
3178 }
3179
3180 struct tableswitch *sw = &switches[tableswitch_count];
3181 sw->_insn_index = start_insn, sw->_first_key = first_key,
3182 sw->_last_key = last_key, sw->_reg = reg;
3183 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3184 {
3185 // Insert the new table of branches
3186 int offset = last_insn;
3187 for (int n = first_key; n < last_key; n++) {
3188 inst->insert_before
3189 (last_insn + 1,
3190 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3191 inst->at(offset)->as_OpBranch()->label()));
3192 offset -= 2, i++;
3193 }
3194 }
3195 // Delete all the old compare-and-branch instructions
3196 for (int n = first_key; n < last_key; n++) {
3197 inst->remove_at(start_insn);
3198 inst->remove_at(start_insn);
3199 }
3200 // Insert the tableswitch instruction
3201 inst->insert_before(start_insn,
3202 new LIR_Op2(lir_cmp, lir_cond_always,
3203 LIR_OprFact::intConst(tableswitch_count),
3204 reg_opr));
3205 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3206 tableswitch_count++;
3207 }
3208 reg = noreg;
3209 last_key = -2147483648;
3210 }
3211 next_state:
3212 ;
3213 }
3214 #endif
3215 }
3216
3217 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3218 Address addr = as_Address(src->as_address_ptr());
3219 BasicType type = src->type();
3220 bool is_oop = is_reference_type(type);
3221
3222 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3223 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3224
3225 switch(type) {
3226 case T_INT:
3227 xchg = &MacroAssembler::atomic_xchgalw;
3228 add = &MacroAssembler::atomic_addalw;
3229 break;
3230 case T_LONG:
3231 xchg = &MacroAssembler::atomic_xchgal;
3232 add = &MacroAssembler::atomic_addal;
3233 break;
3234 case T_OBJECT:
3235 case T_ARRAY:
3236 if (UseCompressedOops) {
3237 xchg = &MacroAssembler::atomic_xchgalw;
3238 add = &MacroAssembler::atomic_addalw;
3239 } else {
3240 xchg = &MacroAssembler::atomic_xchgal;
3241 add = &MacroAssembler::atomic_addal;
3242 }
3243 break;
3244 default:
3245 ShouldNotReachHere();
3246 xchg = &MacroAssembler::atomic_xchgal;
3247 add = &MacroAssembler::atomic_addal; // unreachable
3248 }
3249
3250 switch (code) {
3251 case lir_xadd:
3252 {
3253 RegisterOrConstant inc;
3254 Register tmp = as_reg(tmp_op);
3255 Register dst = as_reg(dest);
3256 if (data->is_constant()) {
3257 inc = RegisterOrConstant(as_long(data));
3258 assert_different_registers(dst, addr.base(), tmp,
3259 rscratch1, rscratch2);
3260 } else {
3261 inc = RegisterOrConstant(as_reg(data));
3262 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3263 rscratch1, rscratch2);
3264 }
3265 __ lea(tmp, addr);
3266 (_masm->*add)(dst, inc, tmp);
3267 break;
3268 }
3269 case lir_xchg:
3270 {
3271 Register tmp = tmp_op->as_register();
3272 Register obj = as_reg(data);
3273 Register dst = as_reg(dest);
3274 if (is_oop && UseCompressedOops) {
3275 __ encode_heap_oop(rscratch2, obj);
3276 obj = rscratch2;
3277 }
3278 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3279 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3280 __ lea(tmp, addr);
3281 (_masm->*xchg)(dst, obj, tmp);
3282 if (is_oop && UseCompressedOops) {
3283 __ decode_heap_oop(dst);
3284 }
3285 }
3286 break;
3287 default:
3288 ShouldNotReachHere();
3289 }
3290 if(!UseLSE) {
3291 __ membar(__ AnyAny);
3292 }
3293 }
3294
3295 #undef __