1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInlineKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "ci/ciObjArrayKlass.hpp"
38 #include "code/compiledIC.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "oops/oop.inline.hpp"
44 #include "runtime/frame.inline.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_aarch64.inline.hpp"
49
50
51 #ifndef PRODUCT
52 #define COMMENT(x) do { __ block_comment(x); } while (0)
53 #else
54 #define COMMENT(x)
55 #endif
56
57 NEEDS_CLEANUP // remove this definitions ?
58 const Register SYNC_header = r0; // synchronization header
59 const Register SHIFT_count = r0; // where count for shift operations must be
60
61 #define __ _masm->
62
63
64 static void select_different_registers(Register preserve,
65 Register extra,
66 Register &tmp1,
67 Register &tmp2) {
68 if (tmp1 == preserve) {
69 assert_different_registers(tmp1, tmp2, extra);
70 tmp1 = extra;
71 } else if (tmp2 == preserve) {
72 assert_different_registers(tmp1, tmp2, extra);
73 tmp2 = extra;
74 }
75 assert_different_registers(preserve, tmp1, tmp2);
76 }
77
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2,
84 Register &tmp3) {
85 if (tmp1 == preserve) {
86 assert_different_registers(tmp1, tmp2, tmp3, extra);
87 tmp1 = extra;
88 } else if (tmp2 == preserve) {
89 assert_different_registers(tmp1, tmp2, tmp3, extra);
90 tmp2 = extra;
91 } else if (tmp3 == preserve) {
92 assert_different_registers(tmp1, tmp2, tmp3, extra);
93 tmp3 = extra;
94 }
95 assert_different_registers(preserve, tmp1, tmp2, tmp3);
96 }
97
98
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
100
101
102 LIR_Opr LIR_Assembler::receiverOpr() {
103 return FrameMap::receiver_opr;
104 }
105
106 LIR_Opr LIR_Assembler::osrBufferPointer() {
107 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
108 }
109
110 //--------------fpu register translations-----------------------
111
112
113 address LIR_Assembler::float_constant(float f) {
114 address const_addr = __ float_constant(f);
115 if (const_addr == nullptr) {
116 bailout("const section overflow");
117 return __ code()->consts()->start();
118 } else {
119 return const_addr;
120 }
121 }
122
123
124 address LIR_Assembler::double_constant(double d) {
125 address const_addr = __ double_constant(d);
126 if (const_addr == nullptr) {
127 bailout("const section overflow");
128 return __ code()->consts()->start();
129 } else {
130 return const_addr;
131 }
132 }
133
134 address LIR_Assembler::int_constant(jlong n) {
135 address const_addr = __ long_constant(n);
136 if (const_addr == nullptr) {
137 bailout("const section overflow");
138 return __ code()->consts()->start();
139 } else {
140 return const_addr;
141 }
142 }
143
144 void LIR_Assembler::breakpoint() { Unimplemented(); }
145
146 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
147
148 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
149
150 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
151 //-------------------------------------------
152
153 static Register as_reg(LIR_Opr op) {
154 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
155 }
156
157 static jlong as_long(LIR_Opr data) {
158 jlong result;
159 switch (data->type()) {
160 case T_INT:
161 result = (data->as_jint());
162 break;
163 case T_LONG:
164 result = (data->as_jlong());
165 break;
166 default:
167 ShouldNotReachHere();
168 result = 0; // unreachable
169 }
170 return result;
171 }
172
173 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
174 Register base = addr->base()->as_pointer_register();
175 LIR_Opr opr = addr->index();
176 if (opr->is_cpu_register()) {
177 Register index;
178 if (opr->is_single_cpu())
179 index = opr->as_register();
180 else
181 index = opr->as_register_lo();
182 assert(addr->disp() == 0, "must be");
183 switch(opr->type()) {
184 case T_INT:
185 return Address(base, index, Address::sxtw(addr->scale()));
186 case T_LONG:
187 return Address(base, index, Address::lsl(addr->scale()));
188 default:
189 ShouldNotReachHere();
190 }
191 } else {
192 assert(addr->scale() == 0,
193 "expected for immediate operand, was: %d", addr->scale());
194 ptrdiff_t offset = ptrdiff_t(addr->disp());
195 // NOTE: Does not handle any 16 byte vector access.
196 const uint type_size = type2aelembytes(addr->type(), true);
197 return __ legitimize_address(Address(base, offset), type_size, tmp);
198 }
199 return Address();
200 }
201
202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
203 ShouldNotReachHere();
204 return Address();
205 }
206
207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
208 return as_Address(addr, rscratch1);
209 }
210
211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
212 return as_Address(addr, rscratch1); // Ouch
213 // FIXME: This needs to be much more clever. See x86.
214 }
215
216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
217 // not encodable as a base + (immediate) offset, generate an explicit address
218 // calculation to hold the address in a temporary register.
219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
220 precond(size == 4 || size == 8);
221 Address addr = frame_map()->address_for_slot(index, adjust);
222 precond(addr.getMode() == Address::base_plus_offset);
223 precond(addr.base() == sp);
224 precond(addr.offset() > 0);
225 uint mask = size - 1;
226 assert((addr.offset() & mask) == 0, "scaled offsets only");
227 return __ legitimize_address(addr, size, tmp);
228 }
229
230 void LIR_Assembler::osr_entry() {
231 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
232 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
233 ValueStack* entry_state = osr_entry->state();
234 int number_of_locks = entry_state->locks_size();
235
236 // we jump here if osr happens with the interpreter
237 // state set up to continue at the beginning of the
238 // loop that triggered osr - in particular, we have
239 // the following registers setup:
240 //
241 // r2: osr buffer
242 //
243
244 // build frame
245 ciMethod* m = compilation()->method();
246 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
247
248 // OSR buffer is
249 //
250 // locals[nlocals-1..0]
251 // monitors[0..number_of_locks]
252 //
253 // locals is a direct copy of the interpreter frame so in the osr buffer
254 // so first slot in the local array is the last local from the interpreter
255 // and last slot is local[0] (receiver) from the interpreter
256 //
257 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
258 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
259 // in the interpreter frame (the method lock if a sync method)
260
261 // Initialize monitors in the compiled activation.
262 // r2: pointer to osr buffer
263 //
264 // All other registers are dead at this point and the locals will be
265 // copied into place by code emitted in the IR.
266
267 Register OSR_buf = osrBufferPointer()->as_pointer_register();
268 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
269 int monitor_offset = BytesPerWord * method()->max_locals() +
270 (2 * BytesPerWord) * (number_of_locks - 1);
271 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
272 // the OSR buffer using 2 word entries: first the lock and then
273 // the oop.
274 for (int i = 0; i < number_of_locks; i++) {
275 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
276 #ifdef ASSERT
277 // verify the interpreter's monitor has a non-null object
278 {
279 Label L;
280 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
281 __ cbnz(rscratch1, L);
282 __ stop("locked object is null");
283 __ bind(L);
284 }
285 #endif
286 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
287 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
288 __ str(r19, frame_map()->address_for_monitor_lock(i));
289 __ str(r20, frame_map()->address_for_monitor_object(i));
290 }
291 }
292 }
293
294
295 // inline cache check; done before the frame is built.
296 int LIR_Assembler::check_icache() {
297 return __ ic_check(CodeEntryAlignment);
298 }
299
300 void LIR_Assembler::clinit_barrier(ciMethod* method) {
301 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
302 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
303
304 Label L_skip_barrier;
305
306 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
307 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
308 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
309 __ bind(L_skip_barrier);
310 }
311
312 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
313 if (o == nullptr) {
314 __ mov(reg, zr);
315 } else {
316 __ movoop(reg, o);
317 }
318 }
319
320 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
321 address target = nullptr;
322 relocInfo::relocType reloc_type = relocInfo::none;
323
324 switch (patching_id(info)) {
325 case PatchingStub::access_field_id:
326 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
327 reloc_type = relocInfo::section_word_type;
328 break;
329 case PatchingStub::load_klass_id:
330 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
331 reloc_type = relocInfo::metadata_type;
332 break;
333 case PatchingStub::load_mirror_id:
334 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
335 reloc_type = relocInfo::oop_type;
336 break;
337 case PatchingStub::load_appendix_id:
338 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
339 reloc_type = relocInfo::oop_type;
340 break;
341 default: ShouldNotReachHere();
342 }
343
344 __ far_call(RuntimeAddress(target));
345 add_call_info_here(info);
346 }
347
348 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
349 deoptimize_trap(info);
350 }
351
352
353 // This specifies the rsp decrement needed to build the frame
354 int LIR_Assembler::initial_frame_size_in_bytes() const {
355 // if rounding, must let FrameMap know!
356
357 return in_bytes(frame_map()->framesize_in_bytes());
358 }
359
360
361 int LIR_Assembler::emit_exception_handler() {
362 // generate code for exception handler
363 address handler_base = __ start_a_stub(exception_handler_size());
364 if (handler_base == nullptr) {
365 // not enough space left for the handler
366 bailout("exception handler overflow");
367 return -1;
368 }
369
370 int offset = code_offset();
371
372 // the exception oop and pc are in r0, and r3
373 // no other registers need to be preserved, so invalidate them
374 __ invalidate_registers(false, true, true, false, true, true);
375
376 // check that there is really an exception
377 __ verify_not_null_oop(r0);
378
379 // search an exception handler (r0: exception oop, r3: throwing pc)
380 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
381 __ should_not_reach_here();
382 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
383 __ end_a_stub();
384
385 return offset;
386 }
387
388
389 // Emit the code to remove the frame from the stack in the exception
390 // unwind path.
391 int LIR_Assembler::emit_unwind_handler() {
392 #ifndef PRODUCT
393 if (CommentedAssembly) {
394 _masm->block_comment("Unwind handler");
395 }
396 #endif
397
398 int offset = code_offset();
399
400 // Fetch the exception from TLS and clear out exception related thread state
401 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
403 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
404
405 __ bind(_unwind_handler_entry);
406 __ verify_not_null_oop(r0);
407 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
408 __ mov(r19, r0); // Preserve the exception
409 }
410
411 // Perform needed unlocking
412 MonitorExitStub* stub = nullptr;
413 if (method()->is_synchronized()) {
414 monitor_address(0, FrameMap::r0_opr);
415 stub = new MonitorExitStub(FrameMap::r0_opr, 0);
416 __ unlock_object(r5, r4, r0, r6, *stub->entry());
417 __ bind(*stub->continuation());
418 }
419
420 if (compilation()->env()->dtrace_method_probes()) {
421 __ mov(c_rarg0, rthread);
422 __ mov_metadata(c_rarg1, method()->constant_encoding());
423 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
424 }
425
426 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
427 __ mov(r0, r19); // Restore the exception
428 }
429
430 // remove the activation and dispatch to the unwind handler
431 __ block_comment("remove_frame and dispatch to the unwind handler");
432 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
433 __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
434
435 // Emit the slow path assembly
436 if (stub != nullptr) {
437 stub->emit_code(this);
438 }
439
440 return offset;
441 }
442
443
444 int LIR_Assembler::emit_deopt_handler() {
445 // generate code for exception handler
446 address handler_base = __ start_a_stub(deopt_handler_size());
447 if (handler_base == nullptr) {
448 // not enough space left for the handler
449 bailout("deopt handler overflow");
450 return -1;
451 }
452
453 int offset = code_offset();
454
455 Label start;
456 __ bind(start);
457
458 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
459
460 int entry_offset = __ offset();
461 __ b(start);
462
463 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
464 __ end_a_stub();
465
466 return entry_offset;
467 }
468
469 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
470 _masm->code_section()->relocate(adr, relocInfo::poll_type);
471 int pc_offset = code_offset();
472 flush_debug_info(pc_offset);
473 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
474 if (info->exception_handlers() != nullptr) {
475 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
476 }
477 }
478
479 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
480 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
481
482 if (InlineTypeReturnedAsFields) {
483 // Check if we are returning an non-null inline type and load its fields into registers
484 ciType* return_type = compilation()->method()->return_type();
485 if (return_type->is_inlinetype()) {
486 ciInlineKlass* vk = return_type->as_inline_klass();
487 if (vk->can_be_returned_as_fields()) {
488 address unpack_handler = vk->unpack_handler();
489 assert(unpack_handler != nullptr, "must be");
490 __ far_call(RuntimeAddress(unpack_handler));
491 }
492 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) {
493 Label skip;
494 Label not_null;
495 __ cbnz(r0, not_null);
496 // Returned value is null, zero all return registers because they may belong to oop fields
497 __ mov(j_rarg1, zr);
498 __ mov(j_rarg2, zr);
499 __ mov(j_rarg3, zr);
500 __ mov(j_rarg4, zr);
501 __ mov(j_rarg5, zr);
502 __ mov(j_rarg6, zr);
503 __ mov(j_rarg7, zr);
504 __ b(skip);
505 __ bind(not_null);
506
507 // Check if we are returning an non-null inline type and load its fields into registers
508 __ test_oop_is_not_inline_type(r0, rscratch2, skip, /* can_be_null= */ false);
509
510 // Load fields from a buffered value with an inline class specific handler
511 __ load_klass(rscratch1 /*dst*/, r0 /*src*/);
512 __ ldr(rscratch1, Address(rscratch1, InstanceKlass::adr_inlineklass_fixed_block_offset()));
513 __ ldr(rscratch1, Address(rscratch1, InlineKlass::unpack_handler_offset()));
514 // Unpack handler can be null if inline type is not scalarizable in returns
515 __ cbz(rscratch1, skip);
516 __ blr(rscratch1);
517
518 __ bind(skip);
519 }
520 // At this point, r0 points to the value object (for interpreter or C1 caller).
521 // The fields of the object are copied into registers (for C2 caller).
522 }
523
524 // Pop the stack before the safepoint code
525 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
526
527 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
528 __ reserved_stack_check();
529 }
530
531 code_stub->set_safepoint_offset(__ offset());
532 __ relocate(relocInfo::poll_return_type);
533 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
534 __ ret(lr);
535 }
536
537 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
538 return (__ store_inline_type_fields_to_buf(vk, false));
539 }
540
541 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
542 guarantee(info != nullptr, "Shouldn't be null");
543 __ get_polling_page(rscratch1, relocInfo::poll_type);
544 add_debug_info_for_branch(info); // This isn't just debug info:
545 // it's the oop map
546 __ read_polling_page(rscratch1, relocInfo::poll_type);
547 return __ offset();
548 }
549
550
551 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
552 if (from_reg == r31_sp)
553 from_reg = sp;
554 if (to_reg == r31_sp)
555 to_reg = sp;
556 __ mov(to_reg, from_reg);
557 }
558
559 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
560
561
562 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
563 assert(src->is_constant(), "should not call otherwise");
564 assert(dest->is_register(), "should not call otherwise");
565 LIR_Const* c = src->as_constant_ptr();
566
567 switch (c->type()) {
568 case T_INT: {
569 assert(patch_code == lir_patch_none, "no patching handled here");
570 __ movw(dest->as_register(), c->as_jint());
571 break;
572 }
573
574 case T_ADDRESS: {
575 assert(patch_code == lir_patch_none, "no patching handled here");
576 __ mov(dest->as_register(), c->as_jint());
577 break;
578 }
579
580 case T_LONG: {
581 assert(patch_code == lir_patch_none, "no patching handled here");
582 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
583 break;
584 }
585
586 case T_OBJECT: {
587 if (patch_code != lir_patch_none) {
588 jobject2reg_with_patching(dest->as_register(), info);
589 } else {
590 jobject2reg(c->as_jobject(), dest->as_register());
591 }
592 break;
593 }
594
595 case T_METADATA: {
596 if (patch_code != lir_patch_none) {
597 klass2reg_with_patching(dest->as_register(), info);
598 } else {
599 __ mov_metadata(dest->as_register(), c->as_metadata());
600 }
601 break;
602 }
603
604 case T_FLOAT: {
605 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
606 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
607 } else {
608 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
609 __ ldrs(dest->as_float_reg(), Address(rscratch1));
610 }
611 break;
612 }
613
614 case T_DOUBLE: {
615 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
616 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
617 } else {
618 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
619 __ ldrd(dest->as_double_reg(), Address(rscratch1));
620 }
621 break;
622 }
623
624 default:
625 ShouldNotReachHere();
626 }
627 }
628
629 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
630 LIR_Const* c = src->as_constant_ptr();
631 switch (c->type()) {
632 case T_OBJECT:
633 {
634 if (! c->as_jobject())
635 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
636 else {
637 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
638 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
639 }
640 }
641 break;
642 case T_ADDRESS:
643 {
644 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
645 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
646 }
647 case T_INT:
648 case T_FLOAT:
649 {
650 Register reg = zr;
651 if (c->as_jint_bits() == 0)
652 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
653 else {
654 __ movw(rscratch1, c->as_jint_bits());
655 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
656 }
657 }
658 break;
659 case T_LONG:
660 case T_DOUBLE:
661 {
662 Register reg = zr;
663 if (c->as_jlong_bits() == 0)
664 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
665 lo_word_offset_in_bytes));
666 else {
667 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
668 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
669 lo_word_offset_in_bytes));
670 }
671 }
672 break;
673 default:
674 ShouldNotReachHere();
675 }
676 }
677
678 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
679 assert(src->is_constant(), "should not call otherwise");
680 LIR_Const* c = src->as_constant_ptr();
681 LIR_Address* to_addr = dest->as_address_ptr();
682
683 void (Assembler::* insn)(Register Rt, const Address &adr);
684
685 switch (type) {
686 case T_ADDRESS:
687 assert(c->as_jint() == 0, "should be");
688 insn = &Assembler::str;
689 break;
690 case T_LONG:
691 assert(c->as_jlong() == 0, "should be");
692 insn = &Assembler::str;
693 break;
694 case T_INT:
695 assert(c->as_jint() == 0, "should be");
696 insn = &Assembler::strw;
697 break;
698 case T_OBJECT:
699 case T_ARRAY:
700 // Non-null case is not handled on aarch64 but handled on x86
701 // FIXME: do we need to add it here?
702 assert(c->as_jobject() == nullptr, "should be");
703 if (UseCompressedOops && !wide) {
704 insn = &Assembler::strw;
705 } else {
706 insn = &Assembler::str;
707 }
708 break;
709 case T_CHAR:
710 case T_SHORT:
711 assert(c->as_jint() == 0, "should be");
712 insn = &Assembler::strh;
713 break;
714 case T_BOOLEAN:
715 case T_BYTE:
716 assert(c->as_jint() == 0, "should be");
717 insn = &Assembler::strb;
718 break;
719 default:
720 ShouldNotReachHere();
721 insn = &Assembler::str; // unreachable
722 }
723
724 if (info) add_debug_info_for_null_check_here(info);
725 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
726 }
727
728 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
729 assert(src->is_register(), "should not call otherwise");
730 assert(dest->is_register(), "should not call otherwise");
731
732 // move between cpu-registers
733 if (dest->is_single_cpu()) {
734 if (src->type() == T_LONG) {
735 // Can do LONG -> OBJECT
736 move_regs(src->as_register_lo(), dest->as_register());
737 return;
738 }
739 assert(src->is_single_cpu(), "must match");
740 if (src->type() == T_OBJECT) {
741 __ verify_oop(src->as_register());
742 }
743 move_regs(src->as_register(), dest->as_register());
744
745 } else if (dest->is_double_cpu()) {
746 if (is_reference_type(src->type())) {
747 // Surprising to me but we can see move of a long to t_object
748 __ verify_oop(src->as_register());
749 move_regs(src->as_register(), dest->as_register_lo());
750 return;
751 }
752 assert(src->is_double_cpu(), "must match");
753 Register f_lo = src->as_register_lo();
754 Register f_hi = src->as_register_hi();
755 Register t_lo = dest->as_register_lo();
756 Register t_hi = dest->as_register_hi();
757 assert(f_hi == f_lo, "must be same");
758 assert(t_hi == t_lo, "must be same");
759 move_regs(f_lo, t_lo);
760
761 } else if (dest->is_single_fpu()) {
762 __ fmovs(dest->as_float_reg(), src->as_float_reg());
763
764 } else if (dest->is_double_fpu()) {
765 __ fmovd(dest->as_double_reg(), src->as_double_reg());
766
767 } else {
768 ShouldNotReachHere();
769 }
770 }
771
772 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
773 precond(src->is_register() && dest->is_stack());
774
775 uint const c_sz32 = sizeof(uint32_t);
776 uint const c_sz64 = sizeof(uint64_t);
777
778 if (src->is_single_cpu()) {
779 int index = dest->single_stack_ix();
780 if (is_reference_type(type)) {
781 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
782 __ verify_oop(src->as_register());
783 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
784 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
785 } else {
786 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
787 }
788
789 } else if (src->is_double_cpu()) {
790 int index = dest->double_stack_ix();
791 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
792 __ str(src->as_register_lo(), dest_addr_LO);
793
794 } else if (src->is_single_fpu()) {
795 int index = dest->single_stack_ix();
796 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
797
798 } else if (src->is_double_fpu()) {
799 int index = dest->double_stack_ix();
800 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
801
802 } else {
803 ShouldNotReachHere();
804 }
805 }
806
807
808 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
809 LIR_Address* to_addr = dest->as_address_ptr();
810 PatchingStub* patch = nullptr;
811 Register compressed_src = rscratch1;
812
813 if (patch_code != lir_patch_none) {
814 deoptimize_trap(info);
815 return;
816 }
817
818 if (is_reference_type(type)) {
819 __ verify_oop(src->as_register());
820
821 if (UseCompressedOops && !wide) {
822 __ encode_heap_oop(compressed_src, src->as_register());
823 } else {
824 compressed_src = src->as_register();
825 }
826 }
827
828 int null_check_here = code_offset();
829 switch (type) {
830 case T_FLOAT: {
831 __ strs(src->as_float_reg(), as_Address(to_addr));
832 break;
833 }
834
835 case T_DOUBLE: {
836 __ strd(src->as_double_reg(), as_Address(to_addr));
837 break;
838 }
839
840 case T_ARRAY: // fall through
841 case T_OBJECT: // fall through
842 if (UseCompressedOops && !wide) {
843 __ strw(compressed_src, as_Address(to_addr, rscratch2));
844 } else {
845 __ str(compressed_src, as_Address(to_addr));
846 }
847 break;
848 case T_METADATA:
849 // We get here to store a method pointer to the stack to pass to
850 // a dtrace runtime call. This can't work on 64 bit with
851 // compressed klass ptrs: T_METADATA can be a compressed klass
852 // ptr or a 64 bit method pointer.
853 ShouldNotReachHere();
854 __ str(src->as_register(), as_Address(to_addr));
855 break;
856 case T_ADDRESS:
857 __ str(src->as_register(), as_Address(to_addr));
858 break;
859 case T_INT:
860 __ strw(src->as_register(), as_Address(to_addr));
861 break;
862
863 case T_LONG: {
864 __ str(src->as_register_lo(), as_Address_lo(to_addr));
865 break;
866 }
867
868 case T_BYTE: // fall through
869 case T_BOOLEAN: {
870 __ strb(src->as_register(), as_Address(to_addr));
871 break;
872 }
873
874 case T_CHAR: // fall through
875 case T_SHORT:
876 __ strh(src->as_register(), as_Address(to_addr));
877 break;
878
879 default:
880 ShouldNotReachHere();
881 }
882 if (info != nullptr) {
883 add_debug_info_for_null_check(null_check_here, info);
884 }
885 }
886
887
888 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
889 precond(src->is_stack() && dest->is_register());
890
891 uint const c_sz32 = sizeof(uint32_t);
892 uint const c_sz64 = sizeof(uint64_t);
893
894 if (dest->is_single_cpu()) {
895 int index = src->single_stack_ix();
896 if (is_reference_type(type)) {
897 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
898 __ verify_oop(dest->as_register());
899 } else if (type == T_METADATA || type == T_ADDRESS) {
900 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
901 } else {
902 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
903 }
904
905 } else if (dest->is_double_cpu()) {
906 int index = src->double_stack_ix();
907 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
908 __ ldr(dest->as_register_lo(), src_addr_LO);
909
910 } else if (dest->is_single_fpu()) {
911 int index = src->single_stack_ix();
912 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
913
914 } else if (dest->is_double_fpu()) {
915 int index = src->double_stack_ix();
916 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
917
918 } else {
919 ShouldNotReachHere();
920 }
921 }
922
923
924 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
925 address target = nullptr;
926 relocInfo::relocType reloc_type = relocInfo::none;
927
928 switch (patching_id(info)) {
929 case PatchingStub::access_field_id:
930 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
931 reloc_type = relocInfo::section_word_type;
932 break;
933 case PatchingStub::load_klass_id:
934 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
935 reloc_type = relocInfo::metadata_type;
936 break;
937 case PatchingStub::load_mirror_id:
938 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
939 reloc_type = relocInfo::oop_type;
940 break;
941 case PatchingStub::load_appendix_id:
942 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
943 reloc_type = relocInfo::oop_type;
944 break;
945 default: ShouldNotReachHere();
946 }
947
948 __ far_call(RuntimeAddress(target));
949 add_call_info_here(info);
950 }
951
952 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
953
954 LIR_Opr temp;
955 if (type == T_LONG || type == T_DOUBLE)
956 temp = FrameMap::rscratch1_long_opr;
957 else
958 temp = FrameMap::rscratch1_opr;
959
960 stack2reg(src, temp, src->type());
961 reg2stack(temp, dest, dest->type());
962 }
963
964
965 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
966 LIR_Address* addr = src->as_address_ptr();
967 LIR_Address* from_addr = src->as_address_ptr();
968
969 if (addr->base()->type() == T_OBJECT) {
970 __ verify_oop(addr->base()->as_pointer_register());
971 }
972
973 if (patch_code != lir_patch_none) {
974 deoptimize_trap(info);
975 return;
976 }
977
978 if (info != nullptr) {
979 add_debug_info_for_null_check_here(info);
980 }
981 int null_check_here = code_offset();
982 switch (type) {
983 case T_FLOAT: {
984 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
985 break;
986 }
987
988 case T_DOUBLE: {
989 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
990 break;
991 }
992
993 case T_ARRAY: // fall through
994 case T_OBJECT: // fall through
995 if (UseCompressedOops && !wide) {
996 __ ldrw(dest->as_register(), as_Address(from_addr));
997 } else {
998 __ ldr(dest->as_register(), as_Address(from_addr));
999 }
1000 break;
1001 case T_METADATA:
1002 // We get here to store a method pointer to the stack to pass to
1003 // a dtrace runtime call. This can't work on 64 bit with
1004 // compressed klass ptrs: T_METADATA can be a compressed klass
1005 // ptr or a 64 bit method pointer.
1006 ShouldNotReachHere();
1007 __ ldr(dest->as_register(), as_Address(from_addr));
1008 break;
1009 case T_ADDRESS:
1010 __ ldr(dest->as_register(), as_Address(from_addr));
1011 break;
1012 case T_INT:
1013 __ ldrw(dest->as_register(), as_Address(from_addr));
1014 break;
1015
1016 case T_LONG: {
1017 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1018 break;
1019 }
1020
1021 case T_BYTE:
1022 __ ldrsb(dest->as_register(), as_Address(from_addr));
1023 break;
1024 case T_BOOLEAN: {
1025 __ ldrb(dest->as_register(), as_Address(from_addr));
1026 break;
1027 }
1028
1029 case T_CHAR:
1030 __ ldrh(dest->as_register(), as_Address(from_addr));
1031 break;
1032 case T_SHORT:
1033 __ ldrsh(dest->as_register(), as_Address(from_addr));
1034 break;
1035
1036 default:
1037 ShouldNotReachHere();
1038 }
1039
1040 if (is_reference_type(type)) {
1041 if (UseCompressedOops && !wide) {
1042 __ decode_heap_oop(dest->as_register());
1043 }
1044
1045 __ verify_oop(dest->as_register());
1046 }
1047 }
1048
1049 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
1050 assert(dst->is_cpu_register(), "must be");
1051 assert(dst->type() == src->type(), "must be");
1052
1053 if (src->is_cpu_register()) {
1054 reg2reg(src, dst);
1055 } else if (src->is_stack()) {
1056 stack2reg(src, dst, dst->type());
1057 } else if (src->is_constant()) {
1058 const2reg(src, dst, lir_patch_none, nullptr);
1059 } else {
1060 ShouldNotReachHere();
1061 }
1062 }
1063
1064 int LIR_Assembler::array_element_size(BasicType type) const {
1065 int elem_size = type2aelembytes(type);
1066 return exact_log2(elem_size);
1067 }
1068
1069
1070 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1071 switch (op->code()) {
1072 case lir_idiv:
1073 case lir_irem:
1074 arithmetic_idiv(op->code(),
1075 op->in_opr1(),
1076 op->in_opr2(),
1077 op->in_opr3(),
1078 op->result_opr(),
1079 op->info());
1080 break;
1081 case lir_fmad:
1082 __ fmaddd(op->result_opr()->as_double_reg(),
1083 op->in_opr1()->as_double_reg(),
1084 op->in_opr2()->as_double_reg(),
1085 op->in_opr3()->as_double_reg());
1086 break;
1087 case lir_fmaf:
1088 __ fmadds(op->result_opr()->as_float_reg(),
1089 op->in_opr1()->as_float_reg(),
1090 op->in_opr2()->as_float_reg(),
1091 op->in_opr3()->as_float_reg());
1092 break;
1093 default: ShouldNotReachHere(); break;
1094 }
1095 }
1096
1097 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1098 #ifdef ASSERT
1099 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1100 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1101 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1102 #endif
1103
1104 if (op->cond() == lir_cond_always) {
1105 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1106 __ b(*(op->label()));
1107 } else {
1108 Assembler::Condition acond;
1109 if (op->code() == lir_cond_float_branch) {
1110 bool is_unordered = (op->ublock() == op->block());
1111 // Assembler::EQ does not permit unordered branches, so we add
1112 // another branch here. Likewise, Assembler::NE does not permit
1113 // ordered branches.
1114 if ((is_unordered && op->cond() == lir_cond_equal)
1115 || (!is_unordered && op->cond() == lir_cond_notEqual))
1116 __ br(Assembler::VS, *(op->ublock()->label()));
1117 switch(op->cond()) {
1118 case lir_cond_equal: acond = Assembler::EQ; break;
1119 case lir_cond_notEqual: acond = Assembler::NE; break;
1120 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1121 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1122 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1123 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1124 default: ShouldNotReachHere();
1125 acond = Assembler::EQ; // unreachable
1126 }
1127 } else {
1128 switch (op->cond()) {
1129 case lir_cond_equal: acond = Assembler::EQ; break;
1130 case lir_cond_notEqual: acond = Assembler::NE; break;
1131 case lir_cond_less: acond = Assembler::LT; break;
1132 case lir_cond_lessEqual: acond = Assembler::LE; break;
1133 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1134 case lir_cond_greater: acond = Assembler::GT; break;
1135 case lir_cond_belowEqual: acond = Assembler::LS; break;
1136 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1137 default: ShouldNotReachHere();
1138 acond = Assembler::EQ; // unreachable
1139 }
1140 }
1141 __ br(acond,*(op->label()));
1142 }
1143 }
1144
1145
1146
1147 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1148 LIR_Opr src = op->in_opr();
1149 LIR_Opr dest = op->result_opr();
1150
1151 switch (op->bytecode()) {
1152 case Bytecodes::_i2f:
1153 {
1154 __ scvtfws(dest->as_float_reg(), src->as_register());
1155 break;
1156 }
1157 case Bytecodes::_i2d:
1158 {
1159 __ scvtfwd(dest->as_double_reg(), src->as_register());
1160 break;
1161 }
1162 case Bytecodes::_l2d:
1163 {
1164 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1165 break;
1166 }
1167 case Bytecodes::_l2f:
1168 {
1169 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1170 break;
1171 }
1172 case Bytecodes::_f2d:
1173 {
1174 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1175 break;
1176 }
1177 case Bytecodes::_d2f:
1178 {
1179 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1180 break;
1181 }
1182 case Bytecodes::_i2c:
1183 {
1184 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1185 break;
1186 }
1187 case Bytecodes::_i2l:
1188 {
1189 __ sxtw(dest->as_register_lo(), src->as_register());
1190 break;
1191 }
1192 case Bytecodes::_i2s:
1193 {
1194 __ sxth(dest->as_register(), src->as_register());
1195 break;
1196 }
1197 case Bytecodes::_i2b:
1198 {
1199 __ sxtb(dest->as_register(), src->as_register());
1200 break;
1201 }
1202 case Bytecodes::_l2i:
1203 {
1204 _masm->block_comment("FIXME: This could be a no-op");
1205 __ uxtw(dest->as_register(), src->as_register_lo());
1206 break;
1207 }
1208 case Bytecodes::_d2l:
1209 {
1210 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1211 break;
1212 }
1213 case Bytecodes::_f2i:
1214 {
1215 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1216 break;
1217 }
1218 case Bytecodes::_f2l:
1219 {
1220 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1221 break;
1222 }
1223 case Bytecodes::_d2i:
1224 {
1225 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1226 break;
1227 }
1228 default: ShouldNotReachHere();
1229 }
1230 }
1231
1232 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1233 if (op->init_check()) {
1234 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1235 __ ldarb(rscratch1, rscratch1);
1236 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1237 add_debug_info_for_null_check_here(op->stub()->info());
1238 __ br(Assembler::NE, *op->stub()->entry());
1239 }
1240 __ allocate_object(op->obj()->as_register(),
1241 op->tmp1()->as_register(),
1242 op->tmp2()->as_register(),
1243 op->header_size(),
1244 op->object_size(),
1245 op->klass()->as_register(),
1246 *op->stub()->entry());
1247 __ bind(*op->stub()->continuation());
1248 }
1249
1250 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1251 Register len = op->len()->as_register();
1252 __ uxtw(len, len);
1253
1254 if (UseSlowPath || op->always_slow_path() ||
1255 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1256 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1257 __ b(*op->stub()->entry());
1258 } else {
1259 Register tmp1 = op->tmp1()->as_register();
1260 Register tmp2 = op->tmp2()->as_register();
1261 Register tmp3 = op->tmp3()->as_register();
1262 if (len == tmp1) {
1263 tmp1 = tmp3;
1264 } else if (len == tmp2) {
1265 tmp2 = tmp3;
1266 } else if (len == tmp3) {
1267 // everything is ok
1268 } else {
1269 __ mov(tmp3, len);
1270 }
1271 __ allocate_array(op->obj()->as_register(),
1272 len,
1273 tmp1,
1274 tmp2,
1275 arrayOopDesc::base_offset_in_bytes(op->type()),
1276 array_element_size(op->type()),
1277 op->klass()->as_register(),
1278 *op->stub()->entry(),
1279 op->zero_array());
1280 }
1281 __ bind(*op->stub()->continuation());
1282 }
1283
1284 void LIR_Assembler::type_profile_helper(Register mdo,
1285 ciMethodData *md, ciProfileData *data,
1286 Register recv, Label* update_done) {
1287
1288 // Given a profile data offset, generate an Address which points to
1289 // the corresponding slot in mdo->data().
1290 // Clobbers rscratch2.
1291 auto slot_at = [=](ByteSize offset) -> Address {
1292 return __ form_address(rscratch2, mdo,
1293 md->byte_offset_of_slot(data, offset),
1294 LogBytesPerWord);
1295 };
1296
1297 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1298 Label next_test;
1299 // See if the receiver is receiver[n].
1300 __ ldr(rscratch1, slot_at(ReceiverTypeData::receiver_offset(i)));
1301 __ cmp(recv, rscratch1);
1302 __ br(Assembler::NE, next_test);
1303 __ addptr(slot_at(ReceiverTypeData::receiver_count_offset(i)),
1304 DataLayout::counter_increment);
1305 __ b(*update_done);
1306 __ bind(next_test);
1307 }
1308
1309 // Didn't find receiver; find next empty slot and fill it in
1310 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1311 Label next_test;
1312 Address recv_addr(slot_at(ReceiverTypeData::receiver_offset(i)));
1313 __ ldr(rscratch1, recv_addr);
1314 __ cbnz(rscratch1, next_test);
1315 __ str(recv, recv_addr);
1316 __ mov(rscratch1, DataLayout::counter_increment);
1317 __ str(rscratch1, slot_at(ReceiverTypeData::receiver_count_offset(i)));
1318 __ b(*update_done);
1319 __ bind(next_test);
1320 }
1321 }
1322
1323 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1324 // we always need a stub for the failure case.
1325 CodeStub* stub = op->stub();
1326 Register obj = op->object()->as_register();
1327 Register k_RInfo = op->tmp1()->as_register();
1328 Register klass_RInfo = op->tmp2()->as_register();
1329 Register dst = op->result_opr()->as_register();
1330 ciKlass* k = op->klass();
1331 Register Rtmp1 = noreg;
1332
1333 // check if it needs to be profiled
1334 ciMethodData* md;
1335 ciProfileData* data;
1336
1337 const bool should_profile = op->should_profile();
1338
1339 if (should_profile) {
1340 ciMethod* method = op->profiled_method();
1341 assert(method != nullptr, "Should have method");
1342 int bci = op->profiled_bci();
1343 md = method->method_data_or_null();
1344 assert(md != nullptr, "Sanity");
1345 data = md->bci_to_data(bci);
1346 assert(data != nullptr, "need data for type check");
1347 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1348 }
1349 Label* success_target = success;
1350 Label* failure_target = failure;
1351
1352 if (obj == k_RInfo) {
1353 k_RInfo = dst;
1354 } else if (obj == klass_RInfo) {
1355 klass_RInfo = dst;
1356 }
1357 if (k->is_loaded() && !UseCompressedClassPointers) {
1358 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1359 } else {
1360 Rtmp1 = op->tmp3()->as_register();
1361 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1362 }
1363
1364 assert_different_registers(obj, k_RInfo, klass_RInfo);
1365
1366 if (op->need_null_check()) {
1367 if (should_profile) {
1368 Register mdo = klass_RInfo;
1369 __ mov_metadata(mdo, md->constant_encoding());
1370 Label not_null;
1371 __ cbnz(obj, not_null);
1372 // Object is null; update MDO and exit
1373 Address data_addr
1374 = __ form_address(rscratch2, mdo,
1375 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1376 0);
1377 __ ldrb(rscratch1, data_addr);
1378 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1379 __ strb(rscratch1, data_addr);
1380 __ b(*obj_is_null);
1381 __ bind(not_null);
1382
1383 Label update_done;
1384 Register recv = k_RInfo;
1385 __ load_klass(recv, obj);
1386 type_profile_helper(mdo, md, data, recv, &update_done);
1387 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1388 __ addptr(counter_addr, DataLayout::counter_increment);
1389
1390 __ bind(update_done);
1391 } else {
1392 __ cbz(obj, *obj_is_null);
1393 }
1394 }
1395
1396 if (!k->is_loaded()) {
1397 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1398 } else {
1399 __ mov_metadata(k_RInfo, k->constant_encoding());
1400 }
1401 __ verify_oop(obj);
1402
1403 if (op->fast_check()) {
1404 assert(!k->is_loaded() || !k->is_obj_array_klass(), "Use refined array for a direct pointer comparison");
1405 // get object class
1406 // not a safepoint as obj null check happens earlier
1407 __ load_klass(rscratch1, obj);
1408 __ cmp( rscratch1, k_RInfo);
1409
1410 __ br(Assembler::NE, *failure_target);
1411 // successful cast, fall through to profile or jump
1412 } else {
1413 // get object class
1414 // not a safepoint as obj null check happens earlier
1415 __ load_klass(klass_RInfo, obj);
1416 if (k->is_loaded()) {
1417 // See if we get an immediate positive hit
1418 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1419 __ cmp(k_RInfo, rscratch1);
1420 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1421 __ br(Assembler::NE, *failure_target);
1422 // successful cast, fall through to profile or jump
1423 } else {
1424 // See if we get an immediate positive hit
1425 __ br(Assembler::EQ, *success_target);
1426 // check for self
1427 if (k->is_loaded() && k->is_obj_array_klass()) {
1428 // For a direct pointer comparison, we need the refined array klass pointer
1429 ciKlass* k_refined = ciObjArrayKlass::make(k->as_obj_array_klass()->element_klass());
1430 __ mov_metadata(rscratch1, k_refined->constant_encoding());
1431 __ cmp(klass_RInfo, rscratch1);
1432 } else {
1433 __ cmp(klass_RInfo, k_RInfo);
1434 }
1435 __ br(Assembler::EQ, *success_target);
1436
1437 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1438 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1439 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1440 // result is a boolean
1441 __ cbzw(klass_RInfo, *failure_target);
1442 // successful cast, fall through to profile or jump
1443 }
1444 } else {
1445 // perform the fast part of the checking logic
1446 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1447 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1448 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1449 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1450 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1451 // result is a boolean
1452 __ cbz(k_RInfo, *failure_target);
1453 // successful cast, fall through to profile or jump
1454 }
1455 }
1456 __ b(*success);
1457 }
1458
1459
1460 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1461 const bool should_profile = op->should_profile();
1462
1463 LIR_Code code = op->code();
1464 if (code == lir_store_check) {
1465 Register value = op->object()->as_register();
1466 Register array = op->array()->as_register();
1467 Register k_RInfo = op->tmp1()->as_register();
1468 Register klass_RInfo = op->tmp2()->as_register();
1469 Register Rtmp1 = op->tmp3()->as_register();
1470
1471 CodeStub* stub = op->stub();
1472
1473 // check if it needs to be profiled
1474 ciMethodData* md;
1475 ciProfileData* data;
1476
1477 if (should_profile) {
1478 ciMethod* method = op->profiled_method();
1479 assert(method != nullptr, "Should have method");
1480 int bci = op->profiled_bci();
1481 md = method->method_data_or_null();
1482 assert(md != nullptr, "Sanity");
1483 data = md->bci_to_data(bci);
1484 assert(data != nullptr, "need data for type check");
1485 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1486 }
1487 Label done;
1488 Label* success_target = &done;
1489 Label* failure_target = stub->entry();
1490
1491 if (should_profile) {
1492 Label not_null;
1493 Register mdo = klass_RInfo;
1494 __ mov_metadata(mdo, md->constant_encoding());
1495 __ cbnz(value, not_null);
1496 // Object is null; update MDO and exit
1497 Address data_addr
1498 = __ form_address(rscratch2, mdo,
1499 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1500 __ ldrb(rscratch1, data_addr);
1501 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1502 __ strb(rscratch1, data_addr);
1503 __ b(done);
1504 __ bind(not_null);
1505
1506 Label update_done;
1507 Register recv = k_RInfo;
1508 __ load_klass(recv, value);
1509 type_profile_helper(mdo, md, data, recv, &update_done);
1510 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1511 __ addptr(counter_addr, DataLayout::counter_increment);
1512 __ bind(update_done);
1513 } else {
1514 __ cbz(value, done);
1515 }
1516
1517 add_debug_info_for_null_check_here(op->info_for_exception());
1518 __ load_klass(k_RInfo, array);
1519 __ load_klass(klass_RInfo, value);
1520
1521 // get instance klass (it's already uncompressed)
1522 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1523 // perform the fast part of the checking logic
1524 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1525 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1526 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1527 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1528 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1529 // result is a boolean
1530 __ cbzw(k_RInfo, *failure_target);
1531 // fall through to the success case
1532
1533 __ bind(done);
1534 } else if (code == lir_checkcast) {
1535 Register obj = op->object()->as_register();
1536 Register dst = op->result_opr()->as_register();
1537 Label success;
1538 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1539 __ bind(success);
1540 if (dst != obj) {
1541 __ mov(dst, obj);
1542 }
1543 } else if (code == lir_instanceof) {
1544 Register obj = op->object()->as_register();
1545 Register dst = op->result_opr()->as_register();
1546 Label success, failure, done;
1547 emit_typecheck_helper(op, &success, &failure, &failure);
1548 __ bind(failure);
1549 __ mov(dst, zr);
1550 __ b(done);
1551 __ bind(success);
1552 __ mov(dst, 1);
1553 __ bind(done);
1554 } else {
1555 ShouldNotReachHere();
1556 }
1557 }
1558
1559 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1560 // We are loading/storing from/to an array that *may* be a flat array (the
1561 // declared type is Object[], abstract[], interface[] or VT.ref[]).
1562 // If this array is a flat array, take the slow path.
1563 __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1564 if (!op->value()->is_illegal()) {
1565 // The array is not a flat array, but it might be null-free. If we are storing
1566 // a null into a null-free array, take the slow path (which will throw NPE).
1567 Label skip;
1568 __ cbnz(op->value()->as_register(), skip);
1569 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1570 __ bind(skip);
1571 }
1572 }
1573
1574 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1575 // We are storing into an array that *may* be null-free (the declared type is
1576 // Object[], abstract[], interface[] or VT.ref[]).
1577 Label test_mark_word;
1578 Register tmp = op->tmp()->as_register();
1579 __ ldr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
1580 __ tst(tmp, markWord::unlocked_value);
1581 __ br(Assembler::NE, test_mark_word);
1582 __ load_prototype_header(tmp, op->array()->as_register());
1583 __ bind(test_mark_word);
1584 __ tst(tmp, markWord::null_free_array_bit_in_place);
1585 }
1586
1587 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1588 Label L_oops_equal;
1589 Label L_oops_not_equal;
1590 Label L_end;
1591
1592 Register left = op->left()->as_register();
1593 Register right = op->right()->as_register();
1594
1595 __ cmp(left, right);
1596 __ br(Assembler::EQ, L_oops_equal);
1597
1598 // (1) Null check -- if one of the operands is null, the other must not be null (because
1599 // the two references are not equal), so they are not substitutable,
1600 // FIXME: do null check only if the operand is nullable
1601 {
1602 __ cbz(left, L_oops_not_equal);
1603 __ cbz(right, L_oops_not_equal);
1604 }
1605
1606 ciKlass* left_klass = op->left_klass();
1607 ciKlass* right_klass = op->right_klass();
1608
1609 // (2) Inline type check -- if either of the operands is not a inline type,
1610 // they are not substitutable. We do this only if we are not sure that the
1611 // operands are inline type
1612 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node.
1613 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
1614 Register tmp1 = op->tmp1()->as_register();
1615 __ mov(tmp1, markWord::inline_type_pattern);
1616 __ ldr(rscratch1, Address(left, oopDesc::mark_offset_in_bytes()));
1617 __ andr(tmp1, tmp1, rscratch1);
1618 __ ldr(rscratch1, Address(right, oopDesc::mark_offset_in_bytes()));
1619 __ andr(tmp1, tmp1, rscratch1);
1620 __ cmp(tmp1, (u1)markWord::inline_type_pattern);
1621 __ br(Assembler::NE, L_oops_not_equal);
1622 }
1623
1624 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
1625 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) {
1626 // No need to load klass -- the operands are statically known to be the same inline klass.
1627 __ b(*op->stub()->entry());
1628 } else {
1629 Register left_klass_op = op->left_klass_op()->as_register();
1630 Register right_klass_op = op->right_klass_op()->as_register();
1631
1632 if (UseCompressedClassPointers) {
1633 __ ldrw(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1634 __ ldrw(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1635 __ cmpw(left_klass_op, right_klass_op);
1636 } else {
1637 __ ldr(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1638 __ ldr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1639 __ cmp(left_klass_op, right_klass_op);
1640 }
1641
1642 __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check
1643 // fall through to L_oops_not_equal
1644 }
1645
1646 __ bind(L_oops_not_equal);
1647 move(op->not_equal_result(), op->result_opr());
1648 __ b(L_end);
1649
1650 __ bind(L_oops_equal);
1651 move(op->equal_result(), op->result_opr());
1652 __ b(L_end);
1653
1654 // We've returned from the stub. R0 contains 0x0 IFF the two
1655 // operands are not substitutable. (Don't compare against 0x1 in case the
1656 // C compiler is naughty)
1657 __ bind(*op->stub()->continuation());
1658 __ cbz(r0, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1659 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
1660 // fall-through
1661 __ bind(L_end);
1662 }
1663
1664
1665 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1666 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1667 __ cset(rscratch1, Assembler::NE);
1668 __ membar(__ AnyAny);
1669 }
1670
1671 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1672 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1673 __ cset(rscratch1, Assembler::NE);
1674 __ membar(__ AnyAny);
1675 }
1676
1677
1678 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1679 Register addr;
1680 if (op->addr()->is_register()) {
1681 addr = as_reg(op->addr());
1682 } else {
1683 assert(op->addr()->is_address(), "what else?");
1684 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1685 assert(addr_ptr->disp() == 0, "need 0 disp");
1686 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1687 addr = as_reg(addr_ptr->base());
1688 }
1689 Register newval = as_reg(op->new_value());
1690 Register cmpval = as_reg(op->cmp_value());
1691
1692 if (op->code() == lir_cas_obj) {
1693 if (UseCompressedOops) {
1694 Register t1 = op->tmp1()->as_register();
1695 assert(op->tmp1()->is_valid(), "must be");
1696 __ encode_heap_oop(t1, cmpval);
1697 cmpval = t1;
1698 __ encode_heap_oop(rscratch2, newval);
1699 newval = rscratch2;
1700 casw(addr, newval, cmpval);
1701 } else {
1702 casl(addr, newval, cmpval);
1703 }
1704 } else if (op->code() == lir_cas_int) {
1705 casw(addr, newval, cmpval);
1706 } else {
1707 casl(addr, newval, cmpval);
1708 }
1709 }
1710
1711
1712 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1713 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1714 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1715
1716 Assembler::Condition acond, ncond;
1717 switch (condition) {
1718 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1719 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1720 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1721 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1722 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1723 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1724 case lir_cond_belowEqual:
1725 case lir_cond_aboveEqual:
1726 default: ShouldNotReachHere();
1727 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1728 }
1729
1730 assert(result->is_single_cpu() || result->is_double_cpu(),
1731 "expect single register for result");
1732 if (opr1->is_constant() && opr2->is_constant()
1733 && opr1->type() == T_INT && opr2->type() == T_INT) {
1734 jint val1 = opr1->as_jint();
1735 jint val2 = opr2->as_jint();
1736 if (val1 == 0 && val2 == 1) {
1737 __ cset(result->as_register(), ncond);
1738 return;
1739 } else if (val1 == 1 && val2 == 0) {
1740 __ cset(result->as_register(), acond);
1741 return;
1742 }
1743 }
1744
1745 if (opr1->is_constant() && opr2->is_constant()
1746 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1747 jlong val1 = opr1->as_jlong();
1748 jlong val2 = opr2->as_jlong();
1749 if (val1 == 0 && val2 == 1) {
1750 __ cset(result->as_register_lo(), ncond);
1751 return;
1752 } else if (val1 == 1 && val2 == 0) {
1753 __ cset(result->as_register_lo(), acond);
1754 return;
1755 }
1756 }
1757
1758 if (opr1->is_stack()) {
1759 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1760 opr1 = FrameMap::rscratch1_opr;
1761 } else if (opr1->is_constant()) {
1762 LIR_Opr tmp
1763 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1764 const2reg(opr1, tmp, lir_patch_none, nullptr);
1765 opr1 = tmp;
1766 }
1767
1768 if (opr2->is_stack()) {
1769 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1770 opr2 = FrameMap::rscratch2_opr;
1771 } else if (opr2->is_constant()) {
1772 LIR_Opr tmp
1773 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1774 const2reg(opr2, tmp, lir_patch_none, nullptr);
1775 opr2 = tmp;
1776 }
1777
1778 if (result->type() == T_LONG)
1779 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1780 else
1781 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1782 }
1783
1784 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1785 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1786
1787 if (left->is_single_cpu()) {
1788 Register lreg = left->as_register();
1789 Register dreg = as_reg(dest);
1790
1791 if (right->is_single_cpu()) {
1792 // cpu register - cpu register
1793
1794 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1795 "should be");
1796 Register rreg = right->as_register();
1797 switch (code) {
1798 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1799 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1800 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1801 default: ShouldNotReachHere();
1802 }
1803
1804 } else if (right->is_double_cpu()) {
1805 Register rreg = right->as_register_lo();
1806 // single_cpu + double_cpu: can happen with obj+long
1807 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1808 switch (code) {
1809 case lir_add: __ add(dreg, lreg, rreg); break;
1810 case lir_sub: __ sub(dreg, lreg, rreg); break;
1811 default: ShouldNotReachHere();
1812 }
1813 } else if (right->is_constant()) {
1814 // cpu register - constant
1815 jlong c;
1816
1817 // FIXME. This is fugly: we really need to factor all this logic.
1818 switch(right->type()) {
1819 case T_LONG:
1820 c = right->as_constant_ptr()->as_jlong();
1821 break;
1822 case T_INT:
1823 case T_ADDRESS:
1824 c = right->as_constant_ptr()->as_jint();
1825 break;
1826 default:
1827 ShouldNotReachHere();
1828 c = 0; // unreachable
1829 break;
1830 }
1831
1832 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1833 if (c == 0 && dreg == lreg) {
1834 COMMENT("effective nop elided");
1835 return;
1836 }
1837 switch(left->type()) {
1838 case T_INT:
1839 switch (code) {
1840 case lir_add: __ addw(dreg, lreg, c); break;
1841 case lir_sub: __ subw(dreg, lreg, c); break;
1842 default: ShouldNotReachHere();
1843 }
1844 break;
1845 case T_OBJECT:
1846 case T_ADDRESS:
1847 switch (code) {
1848 case lir_add: __ add(dreg, lreg, c); break;
1849 case lir_sub: __ sub(dreg, lreg, c); break;
1850 default: ShouldNotReachHere();
1851 }
1852 break;
1853 default:
1854 ShouldNotReachHere();
1855 }
1856 } else {
1857 ShouldNotReachHere();
1858 }
1859
1860 } else if (left->is_double_cpu()) {
1861 Register lreg_lo = left->as_register_lo();
1862
1863 if (right->is_double_cpu()) {
1864 // cpu register - cpu register
1865 Register rreg_lo = right->as_register_lo();
1866 switch (code) {
1867 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1868 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1869 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1870 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1871 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1872 default:
1873 ShouldNotReachHere();
1874 }
1875
1876 } else if (right->is_constant()) {
1877 jlong c = right->as_constant_ptr()->as_jlong();
1878 Register dreg = as_reg(dest);
1879 switch (code) {
1880 case lir_add:
1881 case lir_sub:
1882 if (c == 0 && dreg == lreg_lo) {
1883 COMMENT("effective nop elided");
1884 return;
1885 }
1886 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1887 break;
1888 case lir_div:
1889 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1890 if (c == 1) {
1891 // move lreg_lo to dreg if divisor is 1
1892 __ mov(dreg, lreg_lo);
1893 } else {
1894 unsigned int shift = log2i_exact(c);
1895 // use rscratch1 as intermediate result register
1896 __ asr(rscratch1, lreg_lo, 63);
1897 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1898 __ asr(dreg, rscratch1, shift);
1899 }
1900 break;
1901 case lir_rem:
1902 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1903 if (c == 1) {
1904 // move 0 to dreg if divisor is 1
1905 __ mov(dreg, zr);
1906 } else {
1907 // use rscratch1 as intermediate result register
1908 __ negs(rscratch1, lreg_lo);
1909 __ andr(dreg, lreg_lo, c - 1);
1910 __ andr(rscratch1, rscratch1, c - 1);
1911 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1912 }
1913 break;
1914 default:
1915 ShouldNotReachHere();
1916 }
1917 } else {
1918 ShouldNotReachHere();
1919 }
1920 } else if (left->is_single_fpu()) {
1921 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1922 switch (code) {
1923 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1924 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1925 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1926 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1927 default:
1928 ShouldNotReachHere();
1929 }
1930 } else if (left->is_double_fpu()) {
1931 if (right->is_double_fpu()) {
1932 // fpu register - fpu register
1933 switch (code) {
1934 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1935 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1936 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1937 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1938 default:
1939 ShouldNotReachHere();
1940 }
1941 } else {
1942 if (right->is_constant()) {
1943 ShouldNotReachHere();
1944 }
1945 ShouldNotReachHere();
1946 }
1947 } else if (left->is_single_stack() || left->is_address()) {
1948 assert(left == dest, "left and dest must be equal");
1949 ShouldNotReachHere();
1950 } else {
1951 ShouldNotReachHere();
1952 }
1953 }
1954
1955 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1956 switch(code) {
1957 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1958 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1959 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1960 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1961 default : ShouldNotReachHere();
1962 }
1963 }
1964
1965 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1966
1967 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1968 Register Rleft = left->is_single_cpu() ? left->as_register() :
1969 left->as_register_lo();
1970 if (dst->is_single_cpu()) {
1971 Register Rdst = dst->as_register();
1972 if (right->is_constant()) {
1973 switch (code) {
1974 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1975 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1976 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1977 default: ShouldNotReachHere(); break;
1978 }
1979 } else {
1980 Register Rright = right->is_single_cpu() ? right->as_register() :
1981 right->as_register_lo();
1982 switch (code) {
1983 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1984 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1985 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1986 default: ShouldNotReachHere(); break;
1987 }
1988 }
1989 } else {
1990 Register Rdst = dst->as_register_lo();
1991 if (right->is_constant()) {
1992 switch (code) {
1993 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1994 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1995 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1996 default: ShouldNotReachHere(); break;
1997 }
1998 } else {
1999 Register Rright = right->is_single_cpu() ? right->as_register() :
2000 right->as_register_lo();
2001 switch (code) {
2002 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
2003 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
2004 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
2005 default: ShouldNotReachHere(); break;
2006 }
2007 }
2008 }
2009 }
2010
2011
2012
2013 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
2014
2015 // opcode check
2016 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
2017 bool is_irem = (code == lir_irem);
2018
2019 // operand check
2020 assert(left->is_single_cpu(), "left must be register");
2021 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2022 assert(result->is_single_cpu(), "result must be register");
2023 Register lreg = left->as_register();
2024 Register dreg = result->as_register();
2025
2026 // power-of-2 constant check and codegen
2027 if (right->is_constant()) {
2028 int c = right->as_constant_ptr()->as_jint();
2029 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
2030 if (is_irem) {
2031 if (c == 1) {
2032 // move 0 to dreg if divisor is 1
2033 __ movw(dreg, zr);
2034 } else {
2035 // use rscratch1 as intermediate result register
2036 __ negsw(rscratch1, lreg);
2037 __ andw(dreg, lreg, c - 1);
2038 __ andw(rscratch1, rscratch1, c - 1);
2039 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
2040 }
2041 } else {
2042 if (c == 1) {
2043 // move lreg to dreg if divisor is 1
2044 __ movw(dreg, lreg);
2045 } else {
2046 unsigned int shift = exact_log2(c);
2047 // use rscratch1 as intermediate result register
2048 __ asrw(rscratch1, lreg, 31);
2049 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
2050 __ asrw(dreg, rscratch1, shift);
2051 }
2052 }
2053 } else {
2054 Register rreg = right->as_register();
2055 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
2056 }
2057 }
2058
2059
2060 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2061 if (opr1->is_constant() && opr2->is_single_cpu()) {
2062 // tableswitch
2063 Register reg = as_reg(opr2);
2064 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
2065 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
2066 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
2067 Register reg1 = as_reg(opr1);
2068 if (opr2->is_single_cpu()) {
2069 // cpu register - cpu register
2070 Register reg2 = opr2->as_register();
2071 if (is_reference_type(opr1->type())) {
2072 __ cmpoop(reg1, reg2);
2073 } else {
2074 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2075 __ cmpw(reg1, reg2);
2076 }
2077 return;
2078 }
2079 if (opr2->is_double_cpu()) {
2080 // cpu register - cpu register
2081 Register reg2 = opr2->as_register_lo();
2082 __ cmp(reg1, reg2);
2083 return;
2084 }
2085
2086 if (opr2->is_constant()) {
2087 bool is_32bit = false; // width of register operand
2088 jlong imm;
2089
2090 switch(opr2->type()) {
2091 case T_INT:
2092 imm = opr2->as_constant_ptr()->as_jint();
2093 is_32bit = true;
2094 break;
2095 case T_LONG:
2096 imm = opr2->as_constant_ptr()->as_jlong();
2097 break;
2098 case T_ADDRESS:
2099 imm = opr2->as_constant_ptr()->as_jint();
2100 break;
2101 case T_METADATA:
2102 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
2103 break;
2104 case T_OBJECT:
2105 case T_ARRAY:
2106 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
2107 __ cmpoop(reg1, rscratch1);
2108 return;
2109 default:
2110 ShouldNotReachHere();
2111 imm = 0; // unreachable
2112 break;
2113 }
2114
2115 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
2116 if (is_32bit)
2117 __ cmpw(reg1, imm);
2118 else
2119 __ subs(zr, reg1, imm);
2120 return;
2121 } else {
2122 __ mov(rscratch1, imm);
2123 if (is_32bit)
2124 __ cmpw(reg1, rscratch1);
2125 else
2126 __ cmp(reg1, rscratch1);
2127 return;
2128 }
2129 } else
2130 ShouldNotReachHere();
2131 } else if (opr1->is_single_fpu()) {
2132 FloatRegister reg1 = opr1->as_float_reg();
2133 assert(opr2->is_single_fpu(), "expect single float register");
2134 FloatRegister reg2 = opr2->as_float_reg();
2135 __ fcmps(reg1, reg2);
2136 } else if (opr1->is_double_fpu()) {
2137 FloatRegister reg1 = opr1->as_double_reg();
2138 assert(opr2->is_double_fpu(), "expect double float register");
2139 FloatRegister reg2 = opr2->as_double_reg();
2140 __ fcmpd(reg1, reg2);
2141 } else {
2142 ShouldNotReachHere();
2143 }
2144 }
2145
2146 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2147 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2148 bool is_unordered_less = (code == lir_ucmp_fd2i);
2149 if (left->is_single_fpu()) {
2150 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2151 } else if (left->is_double_fpu()) {
2152 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2153 } else {
2154 ShouldNotReachHere();
2155 }
2156 } else if (code == lir_cmp_l2i) {
2157 Label done;
2158 __ cmp(left->as_register_lo(), right->as_register_lo());
2159 __ mov(dst->as_register(), (uint64_t)-1L);
2160 __ br(Assembler::LT, done);
2161 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2162 __ bind(done);
2163 } else {
2164 ShouldNotReachHere();
2165 }
2166 }
2167
2168
2169 void LIR_Assembler::align_call(LIR_Code code) { }
2170
2171
2172 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2173 address call = __ trampoline_call(Address(op->addr(), rtype));
2174 if (call == nullptr) {
2175 bailout("trampoline stub overflow");
2176 return;
2177 }
2178 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2179 __ post_call_nop();
2180 }
2181
2182
2183 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2184 address call = __ ic_call(op->addr());
2185 if (call == nullptr) {
2186 bailout("trampoline stub overflow");
2187 return;
2188 }
2189 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2190 __ post_call_nop();
2191 }
2192
2193 void LIR_Assembler::emit_static_call_stub() {
2194 address call_pc = __ pc();
2195 address stub = __ start_a_stub(call_stub_size());
2196 if (stub == nullptr) {
2197 bailout("static call stub overflow");
2198 return;
2199 }
2200
2201 int start = __ offset();
2202
2203 __ relocate(static_stub_Relocation::spec(call_pc));
2204 __ emit_static_call_stub();
2205
2206 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2207 <= call_stub_size(), "stub too big");
2208 __ end_a_stub();
2209 }
2210
2211
2212 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2213 assert(exceptionOop->as_register() == r0, "must match");
2214 assert(exceptionPC->as_register() == r3, "must match");
2215
2216 // exception object is not added to oop map by LinearScan
2217 // (LinearScan assumes that no oops are in fixed registers)
2218 info->add_register_oop(exceptionOop);
2219 StubId unwind_id;
2220
2221 // get current pc information
2222 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2223 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2224 // As no instructions have been generated yet for this LIR node it's
2225 // possible that an oop map already exists for the current offset.
2226 // In that case insert an dummy NOP here to ensure all oop map PCs
2227 // are unique. See JDK-8237483.
2228 __ nop();
2229 }
2230 int pc_for_athrow_offset = __ offset();
2231 InternalAddress pc_for_athrow(__ pc());
2232 __ adr(exceptionPC->as_register(), pc_for_athrow);
2233 add_call_info(pc_for_athrow_offset, info); // for exception handler
2234
2235 __ verify_not_null_oop(r0);
2236 // search an exception handler (r0: exception oop, r3: throwing pc)
2237 if (compilation()->has_fpu_code()) {
2238 unwind_id = StubId::c1_handle_exception_id;
2239 } else {
2240 unwind_id = StubId::c1_handle_exception_nofpu_id;
2241 }
2242 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2243
2244 // FIXME: enough room for two byte trap ????
2245 __ nop();
2246 }
2247
2248
2249 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2250 assert(exceptionOop->as_register() == r0, "must match");
2251
2252 __ b(_unwind_handler_entry);
2253 }
2254
2255
2256 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2257 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2258 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2259
2260 switch (left->type()) {
2261 case T_INT: {
2262 switch (code) {
2263 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2264 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2265 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2266 default:
2267 ShouldNotReachHere();
2268 break;
2269 }
2270 break;
2271 case T_LONG:
2272 case T_ADDRESS:
2273 case T_OBJECT:
2274 switch (code) {
2275 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2276 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2277 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2278 default:
2279 ShouldNotReachHere();
2280 break;
2281 }
2282 break;
2283 default:
2284 ShouldNotReachHere();
2285 break;
2286 }
2287 }
2288 }
2289
2290
2291 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2292 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2293 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2294
2295 switch (left->type()) {
2296 case T_INT: {
2297 switch (code) {
2298 case lir_shl: __ lslw (dreg, lreg, count); break;
2299 case lir_shr: __ asrw (dreg, lreg, count); break;
2300 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2301 default:
2302 ShouldNotReachHere();
2303 break;
2304 }
2305 break;
2306 case T_LONG:
2307 case T_ADDRESS:
2308 case T_OBJECT:
2309 switch (code) {
2310 case lir_shl: __ lsl (dreg, lreg, count); break;
2311 case lir_shr: __ asr (dreg, lreg, count); break;
2312 case lir_ushr: __ lsr (dreg, lreg, count); break;
2313 default:
2314 ShouldNotReachHere();
2315 break;
2316 }
2317 break;
2318 default:
2319 ShouldNotReachHere();
2320 break;
2321 }
2322 }
2323 }
2324
2325
2326 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2327 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2328 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2329 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2330 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2331 }
2332
2333
2334 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2335 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2336 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2337 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2338 __ mov (rscratch1, c);
2339 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2340 }
2341
2342
2343 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2344 ShouldNotReachHere();
2345 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2346 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2347 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2348 __ lea(rscratch1, __ constant_oop_address(o));
2349 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2350 }
2351
2352 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
2353 if (null_check) {
2354 __ cbz(obj, *slow_path->entry());
2355 }
2356 if (is_dest) {
2357 __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
2358 // TODO 8350865 Flat no longer implies null-free, so we need to check for flat dest. Can we do better here?
2359 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2360 } else {
2361 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2362 }
2363 }
2364
2365 // This code replaces a call to arraycopy; no exception may
2366 // be thrown in this code, they must be thrown in the System.arraycopy
2367 // activation frame; we could save some checks if this would not be the case
2368 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2369 ciArrayKlass* default_type = op->expected_type();
2370 Register src = op->src()->as_register();
2371 Register dst = op->dst()->as_register();
2372 Register src_pos = op->src_pos()->as_register();
2373 Register dst_pos = op->dst_pos()->as_register();
2374 Register length = op->length()->as_register();
2375 Register tmp = op->tmp()->as_register();
2376
2377 CodeStub* stub = op->stub();
2378 int flags = op->flags();
2379 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2380 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2381
2382 if (flags & LIR_OpArrayCopy::always_slow_path) {
2383 __ b(*stub->entry());
2384 __ bind(*stub->continuation());
2385 return;
2386 }
2387
2388 // if we don't know anything, just go through the generic arraycopy
2389 if (default_type == nullptr // || basic_type == T_OBJECT
2390 ) {
2391 Label done;
2392 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2393
2394 // Save the arguments in case the generic arraycopy fails and we
2395 // have to fall back to the JNI stub
2396 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2397 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2398 __ str(src, Address(sp, 4*BytesPerWord));
2399
2400 address copyfunc_addr = StubRoutines::generic_arraycopy();
2401 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2402
2403 // The arguments are in java calling convention so we shift them
2404 // to C convention
2405 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2406 __ mov(c_rarg0, j_rarg0);
2407 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2408 __ mov(c_rarg1, j_rarg1);
2409 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2410 __ mov(c_rarg2, j_rarg2);
2411 assert_different_registers(c_rarg3, j_rarg4);
2412 __ mov(c_rarg3, j_rarg3);
2413 __ mov(c_rarg4, j_rarg4);
2414 #ifndef PRODUCT
2415 if (PrintC1Statistics) {
2416 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2417 }
2418 #endif
2419 __ far_call(RuntimeAddress(copyfunc_addr));
2420
2421 __ cbz(r0, *stub->continuation());
2422
2423 // Reload values from the stack so they are where the stub
2424 // expects them.
2425 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2426 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2427 __ ldr(src, Address(sp, 4*BytesPerWord));
2428
2429 // r0 is -1^K where K == partial copied count
2430 __ eonw(rscratch1, r0, zr);
2431 // adjust length down and src/end pos up by partial copied count
2432 __ subw(length, length, rscratch1);
2433 __ addw(src_pos, src_pos, rscratch1);
2434 __ addw(dst_pos, dst_pos, rscratch1);
2435 __ b(*stub->entry());
2436
2437 __ bind(*stub->continuation());
2438 return;
2439 }
2440
2441 // Handle inline type arrays
2442 if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
2443 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
2444 }
2445 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
2446 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
2447 }
2448
2449 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2450
2451 int elem_size = type2aelembytes(basic_type);
2452 int scale = exact_log2(elem_size);
2453
2454 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2455 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2456
2457 // test for null
2458 if (flags & LIR_OpArrayCopy::src_null_check) {
2459 __ cbz(src, *stub->entry());
2460 }
2461 if (flags & LIR_OpArrayCopy::dst_null_check) {
2462 __ cbz(dst, *stub->entry());
2463 }
2464
2465 // If the compiler was not able to prove that exact type of the source or the destination
2466 // of the arraycopy is an array type, check at runtime if the source or the destination is
2467 // an instance type.
2468 if (flags & LIR_OpArrayCopy::type_check) {
2469 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2470 __ load_klass(tmp, dst);
2471 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2472 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2473 __ br(Assembler::GE, *stub->entry());
2474 }
2475
2476 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2477 __ load_klass(tmp, src);
2478 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2479 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2480 __ br(Assembler::GE, *stub->entry());
2481 }
2482 }
2483
2484 // check if negative
2485 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2486 __ cmpw(src_pos, 0);
2487 __ br(Assembler::LT, *stub->entry());
2488 }
2489 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2490 __ cmpw(dst_pos, 0);
2491 __ br(Assembler::LT, *stub->entry());
2492 }
2493
2494 if (flags & LIR_OpArrayCopy::length_positive_check) {
2495 __ cmpw(length, 0);
2496 __ br(Assembler::LT, *stub->entry());
2497 }
2498
2499 if (flags & LIR_OpArrayCopy::src_range_check) {
2500 __ addw(tmp, src_pos, length);
2501 __ ldrw(rscratch1, src_length_addr);
2502 __ cmpw(tmp, rscratch1);
2503 __ br(Assembler::HI, *stub->entry());
2504 }
2505 if (flags & LIR_OpArrayCopy::dst_range_check) {
2506 __ addw(tmp, dst_pos, length);
2507 __ ldrw(rscratch1, dst_length_addr);
2508 __ cmpw(tmp, rscratch1);
2509 __ br(Assembler::HI, *stub->entry());
2510 }
2511
2512 if (flags & LIR_OpArrayCopy::type_check) {
2513 // We don't know the array types are compatible
2514 if (basic_type != T_OBJECT) {
2515 // Simple test for basic type arrays
2516 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2517 __ br(Assembler::NE, *stub->entry());
2518 } else {
2519 // For object arrays, if src is a sub class of dst then we can
2520 // safely do the copy.
2521 Label cont, slow;
2522
2523 #define PUSH(r1, r2) \
2524 stp(r1, r2, __ pre(sp, -2 * wordSize));
2525
2526 #define POP(r1, r2) \
2527 ldp(r1, r2, __ post(sp, 2 * wordSize));
2528
2529 __ PUSH(src, dst);
2530
2531 __ load_klass(src, src);
2532 __ load_klass(dst, dst);
2533
2534 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2535
2536 __ PUSH(src, dst);
2537 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2538 __ POP(src, dst);
2539
2540 __ cbnz(src, cont);
2541
2542 __ bind(slow);
2543 __ POP(src, dst);
2544
2545 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2546 if (copyfunc_addr != nullptr) { // use stub if available
2547 // src is not a sub class of dst so we have to do a
2548 // per-element check.
2549
2550 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2551 if ((flags & mask) != mask) {
2552 // Check that at least both of them object arrays.
2553 assert(flags & mask, "one of the two should be known to be an object array");
2554
2555 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2556 __ load_klass(tmp, src);
2557 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2558 __ load_klass(tmp, dst);
2559 }
2560 int lh_offset = in_bytes(Klass::layout_helper_offset());
2561 Address klass_lh_addr(tmp, lh_offset);
2562 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2563 __ ldrw(rscratch1, klass_lh_addr);
2564 __ mov(rscratch2, objArray_lh);
2565 __ eorw(rscratch1, rscratch1, rscratch2);
2566 __ cbnzw(rscratch1, *stub->entry());
2567 }
2568
2569 // Spill because stubs can use any register they like and it's
2570 // easier to restore just those that we care about.
2571 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2572 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2573 __ str(src, Address(sp, 4*BytesPerWord));
2574
2575 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2576 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2577 assert_different_registers(c_rarg0, dst, dst_pos, length);
2578 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2579 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2580 assert_different_registers(c_rarg1, dst, length);
2581 __ uxtw(c_rarg2, length);
2582 assert_different_registers(c_rarg2, dst);
2583
2584 __ load_klass(c_rarg4, dst);
2585 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2586 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2587 __ far_call(RuntimeAddress(copyfunc_addr));
2588
2589 #ifndef PRODUCT
2590 if (PrintC1Statistics) {
2591 Label failed;
2592 __ cbnz(r0, failed);
2593 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2594 __ bind(failed);
2595 }
2596 #endif
2597
2598 __ cbz(r0, *stub->continuation());
2599
2600 #ifndef PRODUCT
2601 if (PrintC1Statistics) {
2602 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2603 }
2604 #endif
2605 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2606
2607 // Restore previously spilled arguments
2608 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2609 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2610 __ ldr(src, Address(sp, 4*BytesPerWord));
2611
2612 // return value is -1^K where K is partial copied count
2613 __ eonw(rscratch1, r0, zr);
2614 // adjust length down and src/end pos up by partial copied count
2615 __ subw(length, length, rscratch1);
2616 __ addw(src_pos, src_pos, rscratch1);
2617 __ addw(dst_pos, dst_pos, rscratch1);
2618 }
2619
2620 __ b(*stub->entry());
2621
2622 __ bind(cont);
2623 __ POP(src, dst);
2624 }
2625 }
2626
2627 #ifdef ASSERT
2628 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2629 // Sanity check the known type with the incoming class. For the
2630 // primitive case the types must match exactly with src.klass and
2631 // dst.klass each exactly matching the default type. For the
2632 // object array case, if no type check is needed then either the
2633 // dst type is exactly the expected type and the src type is a
2634 // subtype which we can't check or src is the same array as dst
2635 // but not necessarily exactly of type default_type.
2636 Label known_ok, halt;
2637 __ mov_metadata(tmp, default_type->constant_encoding());
2638
2639 if (basic_type != T_OBJECT) {
2640 __ cmp_klass(dst, tmp, rscratch1);
2641 __ br(Assembler::NE, halt);
2642 __ cmp_klass(src, tmp, rscratch1);
2643 __ br(Assembler::EQ, known_ok);
2644 } else {
2645 __ cmp_klass(dst, tmp, rscratch1);
2646 __ br(Assembler::EQ, known_ok);
2647 __ cmp(src, dst);
2648 __ br(Assembler::EQ, known_ok);
2649 }
2650 __ bind(halt);
2651 __ stop("incorrect type information in arraycopy");
2652 __ bind(known_ok);
2653 }
2654 #endif
2655
2656 #ifndef PRODUCT
2657 if (PrintC1Statistics) {
2658 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2659 }
2660 #endif
2661
2662 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2663 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2664 assert_different_registers(c_rarg0, dst, dst_pos, length);
2665 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2666 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2667 assert_different_registers(c_rarg1, dst, length);
2668 __ uxtw(c_rarg2, length);
2669 assert_different_registers(c_rarg2, dst);
2670
2671 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2672 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2673 const char *name;
2674 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2675
2676 CodeBlob *cb = CodeCache::find_blob(entry);
2677 if (cb) {
2678 __ far_call(RuntimeAddress(entry));
2679 } else {
2680 __ call_VM_leaf(entry, 3);
2681 }
2682
2683 if (stub != nullptr) {
2684 __ bind(*stub->continuation());
2685 }
2686 }
2687
2688
2689
2690
2691 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2692 Register obj = op->obj_opr()->as_register(); // may not be an oop
2693 Register hdr = op->hdr_opr()->as_register();
2694 Register lock = op->lock_opr()->as_register();
2695 Register temp = op->scratch_opr()->as_register();
2696 if (op->code() == lir_lock) {
2697 // add debug info for NullPointerException only if one is possible
2698 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2699 if (op->info() != nullptr) {
2700 add_debug_info_for_null_check(null_check_offset, op->info());
2701 }
2702 // done
2703 } else if (op->code() == lir_unlock) {
2704 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2705 } else {
2706 Unimplemented();
2707 }
2708 __ bind(*op->stub()->continuation());
2709 }
2710
2711 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2712 Register obj = op->obj()->as_pointer_register();
2713 Register result = op->result_opr()->as_pointer_register();
2714
2715 CodeEmitInfo* info = op->info();
2716 if (info != nullptr) {
2717 add_debug_info_for_null_check_here(info);
2718 }
2719
2720 __ load_klass(result, obj);
2721 }
2722
2723 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2724 ciMethod* method = op->profiled_method();
2725 int bci = op->profiled_bci();
2726 ciMethod* callee = op->profiled_callee();
2727
2728 // Update counter for all call types
2729 ciMethodData* md = method->method_data_or_null();
2730 assert(md != nullptr, "Sanity");
2731 ciProfileData* data = md->bci_to_data(bci);
2732 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2733 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2734 Register mdo = op->mdo()->as_register();
2735 __ mov_metadata(mdo, md->constant_encoding());
2736 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2737 // Perform additional virtual call profiling for invokevirtual and
2738 // invokeinterface bytecodes
2739 if (op->should_profile_receiver_type()) {
2740 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2741 Register recv = op->recv()->as_register();
2742 assert_different_registers(mdo, recv);
2743 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2744 ciKlass* known_klass = op->known_holder();
2745 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2746 // We know the type that will be seen at this call site; we can
2747 // statically update the MethodData* rather than needing to do
2748 // dynamic tests on the receiver type
2749
2750 // NOTE: we should probably put a lock around this search to
2751 // avoid collisions by concurrent compilations
2752 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2753 uint i;
2754 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2755 ciKlass* receiver = vc_data->receiver(i);
2756 if (known_klass->equals(receiver)) {
2757 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2758 __ addptr(data_addr, DataLayout::counter_increment);
2759 return;
2760 }
2761 }
2762
2763 // Receiver type not found in profile data; select an empty slot
2764
2765 // Note that this is less efficient than it should be because it
2766 // always does a write to the receiver part of the
2767 // VirtualCallData rather than just the first time
2768 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2769 ciKlass* receiver = vc_data->receiver(i);
2770 if (receiver == nullptr) {
2771 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2772 Address recv_addr =
2773 __ form_address(rscratch2, mdo,
2774 md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)),
2775 LogBytesPerWord);
2776 __ str(rscratch1, recv_addr);
2777 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2778 __ addptr(data_addr, DataLayout::counter_increment);
2779 return;
2780 }
2781 }
2782 } else {
2783 __ load_klass(recv, recv);
2784 Label update_done;
2785 type_profile_helper(mdo, md, data, recv, &update_done);
2786 // Receiver did not match any saved receiver and there is no empty row for it.
2787 // Increment total counter to indicate polymorphic case.
2788 __ addptr(counter_addr, DataLayout::counter_increment);
2789
2790 __ bind(update_done);
2791 }
2792 } else {
2793 // Static call
2794 __ addptr(counter_addr, DataLayout::counter_increment);
2795 }
2796 }
2797
2798
2799 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2800 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2801 }
2802
2803 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2804 assert(op->crc()->is_single_cpu(), "crc must be register");
2805 assert(op->val()->is_single_cpu(), "byte value must be register");
2806 assert(op->result_opr()->is_single_cpu(), "result must be register");
2807 Register crc = op->crc()->as_register();
2808 Register val = op->val()->as_register();
2809 Register res = op->result_opr()->as_register();
2810
2811 assert_different_registers(val, crc, res);
2812 uint64_t offset;
2813 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2814 __ add(res, res, offset);
2815
2816 __ mvnw(crc, crc); // ~crc
2817 __ update_byte_crc32(crc, val, res);
2818 __ mvnw(res, crc); // ~crc
2819 }
2820
2821 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2822 COMMENT("emit_profile_type {");
2823 Register obj = op->obj()->as_register();
2824 Register tmp = op->tmp()->as_pointer_register();
2825 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2826 ciKlass* exact_klass = op->exact_klass();
2827 intptr_t current_klass = op->current_klass();
2828 bool not_null = op->not_null();
2829 bool no_conflict = op->no_conflict();
2830
2831 Label update, next, none;
2832
2833 bool do_null = !not_null;
2834 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2835 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2836
2837 assert(do_null || do_update, "why are we here?");
2838 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2839 assert(mdo_addr.base() != rscratch1, "wrong register");
2840
2841 __ verify_oop(obj);
2842
2843 if (tmp != obj) {
2844 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2845 __ mov(tmp, obj);
2846 } else {
2847 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2848 }
2849 if (do_null) {
2850 __ cbnz(tmp, update);
2851 if (!TypeEntries::was_null_seen(current_klass)) {
2852 __ ldr(rscratch2, mdo_addr);
2853 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2854 __ str(rscratch2, mdo_addr);
2855 }
2856 if (do_update) {
2857 #ifndef ASSERT
2858 __ b(next);
2859 }
2860 #else
2861 __ b(next);
2862 }
2863 } else {
2864 __ cbnz(tmp, update);
2865 __ stop("unexpected null obj");
2866 #endif
2867 }
2868
2869 __ bind(update);
2870
2871 if (do_update) {
2872 #ifdef ASSERT
2873 if (exact_klass != nullptr) {
2874 Label ok;
2875 __ load_klass(tmp, tmp);
2876 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2877 __ eor(rscratch1, tmp, rscratch1);
2878 __ cbz(rscratch1, ok);
2879 __ stop("exact klass and actual klass differ");
2880 __ bind(ok);
2881 }
2882 #endif
2883 if (!no_conflict) {
2884 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2885 if (exact_klass != nullptr) {
2886 __ mov_metadata(tmp, exact_klass->constant_encoding());
2887 } else {
2888 __ load_klass(tmp, tmp);
2889 }
2890
2891 __ ldr(rscratch2, mdo_addr);
2892 __ eor(tmp, tmp, rscratch2);
2893 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2894 // klass seen before, nothing to do. The unknown bit may have been
2895 // set already but no need to check.
2896 __ cbz(rscratch1, next);
2897
2898 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2899
2900 if (TypeEntries::is_type_none(current_klass)) {
2901 __ cbz(rscratch2, none);
2902 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2903 __ br(Assembler::EQ, none);
2904 // There is a chance that the checks above
2905 // fail if another thread has just set the
2906 // profiling to this obj's klass
2907 __ dmb(Assembler::ISHLD);
2908 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2909 __ ldr(rscratch2, mdo_addr);
2910 __ eor(tmp, tmp, rscratch2);
2911 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2912 __ cbz(rscratch1, next);
2913 }
2914 } else {
2915 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2916 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2917
2918 __ ldr(tmp, mdo_addr);
2919 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2920 }
2921
2922 // different than before. Cannot keep accurate profile.
2923 __ ldr(rscratch2, mdo_addr);
2924 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2925 __ str(rscratch2, mdo_addr);
2926
2927 if (TypeEntries::is_type_none(current_klass)) {
2928 __ b(next);
2929
2930 __ bind(none);
2931 // first time here. Set profile type.
2932 __ str(tmp, mdo_addr);
2933 #ifdef ASSERT
2934 __ andr(tmp, tmp, TypeEntries::type_mask);
2935 __ verify_klass_ptr(tmp);
2936 #endif
2937 }
2938 } else {
2939 // There's a single possible klass at this profile point
2940 assert(exact_klass != nullptr, "should be");
2941 if (TypeEntries::is_type_none(current_klass)) {
2942 __ mov_metadata(tmp, exact_klass->constant_encoding());
2943 __ ldr(rscratch2, mdo_addr);
2944 __ eor(tmp, tmp, rscratch2);
2945 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2946 __ cbz(rscratch1, next);
2947 #ifdef ASSERT
2948 {
2949 Label ok;
2950 __ ldr(rscratch1, mdo_addr);
2951 __ cbz(rscratch1, ok);
2952 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2953 __ br(Assembler::EQ, ok);
2954 // may have been set by another thread
2955 __ dmb(Assembler::ISHLD);
2956 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2957 __ ldr(rscratch2, mdo_addr);
2958 __ eor(rscratch2, rscratch1, rscratch2);
2959 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2960 __ cbz(rscratch2, ok);
2961
2962 __ stop("unexpected profiling mismatch");
2963 __ bind(ok);
2964 }
2965 #endif
2966 // first time here. Set profile type.
2967 __ str(tmp, mdo_addr);
2968 #ifdef ASSERT
2969 __ andr(tmp, tmp, TypeEntries::type_mask);
2970 __ verify_klass_ptr(tmp);
2971 #endif
2972 } else {
2973 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2974 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2975
2976 __ ldr(tmp, mdo_addr);
2977 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2978
2979 __ orr(tmp, tmp, TypeEntries::type_unknown);
2980 __ str(tmp, mdo_addr);
2981 // FIXME: Write barrier needed here?
2982 }
2983 }
2984
2985 __ bind(next);
2986 }
2987 COMMENT("} emit_profile_type");
2988 }
2989
2990 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
2991 Register obj = op->obj()->as_register();
2992 Register tmp = op->tmp()->as_pointer_register();
2993 bool not_null = op->not_null();
2994 int flag = op->flag();
2995
2996 Label not_inline_type;
2997 if (!not_null) {
2998 __ cbz(obj, not_inline_type);
2999 }
3000
3001 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
3002
3003 Address mdo_addr = as_Address(op->mdp()->as_address_ptr(), rscratch2);
3004 __ ldrb(rscratch1, mdo_addr);
3005 __ orr(rscratch1, rscratch1, flag);
3006 __ strb(rscratch1, mdo_addr);
3007
3008 __ bind(not_inline_type);
3009 }
3010
3011 void LIR_Assembler::align_backward_branch_target() {
3012 }
3013
3014
3015 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3016 // tmp must be unused
3017 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3018
3019 if (left->is_single_cpu()) {
3020 assert(dest->is_single_cpu(), "expect single result reg");
3021 __ negw(dest->as_register(), left->as_register());
3022 } else if (left->is_double_cpu()) {
3023 assert(dest->is_double_cpu(), "expect double result reg");
3024 __ neg(dest->as_register_lo(), left->as_register_lo());
3025 } else if (left->is_single_fpu()) {
3026 assert(dest->is_single_fpu(), "expect single float result reg");
3027 __ fnegs(dest->as_float_reg(), left->as_float_reg());
3028 } else {
3029 assert(left->is_double_fpu(), "expect double float operand reg");
3030 assert(dest->is_double_fpu(), "expect double float result reg");
3031 __ fnegd(dest->as_double_reg(), left->as_double_reg());
3032 }
3033 }
3034
3035
3036 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3037 if (patch_code != lir_patch_none) {
3038 deoptimize_trap(info);
3039 return;
3040 }
3041
3042 __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
3043 }
3044
3045
3046 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3047 assert(!tmp->is_valid(), "don't need temporary");
3048
3049 CodeBlob *cb = CodeCache::find_blob(dest);
3050 if (cb) {
3051 __ far_call(RuntimeAddress(dest));
3052 } else {
3053 __ mov(rscratch1, RuntimeAddress(dest));
3054 __ blr(rscratch1);
3055 }
3056
3057 if (info != nullptr) {
3058 add_call_info_here(info);
3059 }
3060 __ post_call_nop();
3061 }
3062
3063 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3064 if (dest->is_address() || src->is_address()) {
3065 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
3066 } else {
3067 ShouldNotReachHere();
3068 }
3069 }
3070
3071 #ifdef ASSERT
3072 // emit run-time assertion
3073 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3074 assert(op->code() == lir_assert, "must be");
3075
3076 if (op->in_opr1()->is_valid()) {
3077 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3078 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3079 } else {
3080 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3081 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3082 }
3083
3084 Label ok;
3085 if (op->condition() != lir_cond_always) {
3086 Assembler::Condition acond = Assembler::AL;
3087 switch (op->condition()) {
3088 case lir_cond_equal: acond = Assembler::EQ; break;
3089 case lir_cond_notEqual: acond = Assembler::NE; break;
3090 case lir_cond_less: acond = Assembler::LT; break;
3091 case lir_cond_lessEqual: acond = Assembler::LE; break;
3092 case lir_cond_greaterEqual: acond = Assembler::GE; break;
3093 case lir_cond_greater: acond = Assembler::GT; break;
3094 case lir_cond_belowEqual: acond = Assembler::LS; break;
3095 case lir_cond_aboveEqual: acond = Assembler::HS; break;
3096 default: ShouldNotReachHere();
3097 }
3098 __ br(acond, ok);
3099 }
3100 if (op->halt()) {
3101 const char* str = __ code_string(op->msg());
3102 __ stop(str);
3103 } else {
3104 breakpoint();
3105 }
3106 __ bind(ok);
3107 }
3108 #endif
3109
3110 #ifndef PRODUCT
3111 #define COMMENT(x) do { __ block_comment(x); } while (0)
3112 #else
3113 #define COMMENT(x)
3114 #endif
3115
3116 void LIR_Assembler::membar() {
3117 COMMENT("membar");
3118 __ membar(MacroAssembler::AnyAny);
3119 }
3120
3121 void LIR_Assembler::membar_acquire() {
3122 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
3123 }
3124
3125 void LIR_Assembler::membar_release() {
3126 __ membar(Assembler::LoadStore|Assembler::StoreStore);
3127 }
3128
3129 void LIR_Assembler::membar_loadload() {
3130 __ membar(Assembler::LoadLoad);
3131 }
3132
3133 void LIR_Assembler::membar_storestore() {
3134 __ membar(MacroAssembler::StoreStore);
3135 }
3136
3137 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3138
3139 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3140
3141 void LIR_Assembler::on_spin_wait() {
3142 __ spin_wait();
3143 }
3144
3145 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3146 __ mov(result_reg->as_register(), rthread);
3147 }
3148
3149 void LIR_Assembler::check_orig_pc() {
3150 __ ldr(rscratch2, frame_map()->address_for_orig_pc_addr());
3151 __ cmp(rscratch2, (u1)NULL_WORD);
3152 }
3153
3154 void LIR_Assembler::peephole(LIR_List *lir) {
3155 #if 0
3156 if (tableswitch_count >= max_tableswitches)
3157 return;
3158
3159 /*
3160 This finite-state automaton recognizes sequences of compare-and-
3161 branch instructions. We will turn them into a tableswitch. You
3162 could argue that C1 really shouldn't be doing this sort of
3163 optimization, but without it the code is really horrible.
3164 */
3165
3166 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3167 int first_key, last_key = -2147483648;
3168 int next_key = 0;
3169 int start_insn = -1;
3170 int last_insn = -1;
3171 Register reg = noreg;
3172 LIR_Opr reg_opr;
3173 state = start_s;
3174
3175 LIR_OpList* inst = lir->instructions_list();
3176 for (int i = 0; i < inst->length(); i++) {
3177 LIR_Op* op = inst->at(i);
3178 switch (state) {
3179 case start_s:
3180 first_key = -1;
3181 start_insn = i;
3182 switch (op->code()) {
3183 case lir_cmp:
3184 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3185 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3186 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3187 && opr2->is_constant()
3188 && opr2->type() == T_INT) {
3189 reg_opr = opr1;
3190 reg = opr1->as_register();
3191 first_key = opr2->as_constant_ptr()->as_jint();
3192 next_key = first_key + 1;
3193 state = cmp_s;
3194 goto next_state;
3195 }
3196 break;
3197 }
3198 break;
3199 case cmp_s:
3200 switch (op->code()) {
3201 case lir_branch:
3202 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3203 state = beq_s;
3204 last_insn = i;
3205 goto next_state;
3206 }
3207 }
3208 state = start_s;
3209 break;
3210 case beq_s:
3211 switch (op->code()) {
3212 case lir_cmp: {
3213 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3214 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3215 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3216 && opr1->as_register() == reg
3217 && opr2->is_constant()
3218 && opr2->type() == T_INT
3219 && opr2->as_constant_ptr()->as_jint() == next_key) {
3220 last_key = next_key;
3221 next_key++;
3222 state = cmp_s;
3223 goto next_state;
3224 }
3225 }
3226 }
3227 last_key = next_key;
3228 state = start_s;
3229 break;
3230 default:
3231 assert(false, "impossible state");
3232 }
3233 if (state == start_s) {
3234 if (first_key < last_key - 5L && reg != noreg) {
3235 {
3236 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3237 // reg->encoding(),
3238 // start_insn, first_key, last_key);
3239 // for (int i = 0; i < inst->length(); i++) {
3240 // inst->at(i)->print();
3241 // tty->print("\n");
3242 // }
3243 // tty->print("\n");
3244 }
3245
3246 struct tableswitch *sw = &switches[tableswitch_count];
3247 sw->_insn_index = start_insn, sw->_first_key = first_key,
3248 sw->_last_key = last_key, sw->_reg = reg;
3249 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3250 {
3251 // Insert the new table of branches
3252 int offset = last_insn;
3253 for (int n = first_key; n < last_key; n++) {
3254 inst->insert_before
3255 (last_insn + 1,
3256 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3257 inst->at(offset)->as_OpBranch()->label()));
3258 offset -= 2, i++;
3259 }
3260 }
3261 // Delete all the old compare-and-branch instructions
3262 for (int n = first_key; n < last_key; n++) {
3263 inst->remove_at(start_insn);
3264 inst->remove_at(start_insn);
3265 }
3266 // Insert the tableswitch instruction
3267 inst->insert_before(start_insn,
3268 new LIR_Op2(lir_cmp, lir_cond_always,
3269 LIR_OprFact::intConst(tableswitch_count),
3270 reg_opr));
3271 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3272 tableswitch_count++;
3273 }
3274 reg = noreg;
3275 last_key = -2147483648;
3276 }
3277 next_state:
3278 ;
3279 }
3280 #endif
3281 }
3282
3283 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3284 Address addr = as_Address(src->as_address_ptr());
3285 BasicType type = src->type();
3286 bool is_oop = is_reference_type(type);
3287
3288 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3289 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3290
3291 switch(type) {
3292 case T_INT:
3293 xchg = &MacroAssembler::atomic_xchgalw;
3294 add = &MacroAssembler::atomic_addalw;
3295 break;
3296 case T_LONG:
3297 xchg = &MacroAssembler::atomic_xchgal;
3298 add = &MacroAssembler::atomic_addal;
3299 break;
3300 case T_OBJECT:
3301 case T_ARRAY:
3302 if (UseCompressedOops) {
3303 xchg = &MacroAssembler::atomic_xchgalw;
3304 add = &MacroAssembler::atomic_addalw;
3305 } else {
3306 xchg = &MacroAssembler::atomic_xchgal;
3307 add = &MacroAssembler::atomic_addal;
3308 }
3309 break;
3310 default:
3311 ShouldNotReachHere();
3312 xchg = &MacroAssembler::atomic_xchgal;
3313 add = &MacroAssembler::atomic_addal; // unreachable
3314 }
3315
3316 switch (code) {
3317 case lir_xadd:
3318 {
3319 RegisterOrConstant inc;
3320 Register tmp = as_reg(tmp_op);
3321 Register dst = as_reg(dest);
3322 if (data->is_constant()) {
3323 inc = RegisterOrConstant(as_long(data));
3324 assert_different_registers(dst, addr.base(), tmp,
3325 rscratch1, rscratch2);
3326 } else {
3327 inc = RegisterOrConstant(as_reg(data));
3328 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3329 rscratch1, rscratch2);
3330 }
3331 __ lea(tmp, addr);
3332 (_masm->*add)(dst, inc, tmp);
3333 break;
3334 }
3335 case lir_xchg:
3336 {
3337 Register tmp = tmp_op->as_register();
3338 Register obj = as_reg(data);
3339 Register dst = as_reg(dest);
3340 if (is_oop && UseCompressedOops) {
3341 __ encode_heap_oop(rscratch2, obj);
3342 obj = rscratch2;
3343 }
3344 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3345 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3346 __ lea(tmp, addr);
3347 (_masm->*xchg)(dst, obj, tmp);
3348 if (is_oop && UseCompressedOops) {
3349 __ decode_heap_oop(dst);
3350 }
3351 }
3352 break;
3353 default:
3354 ShouldNotReachHere();
3355 }
3356 if(!UseLSE) {
3357 __ membar(__ AnyAny);
3358 }
3359 }
3360
3361 #undef __