1 /*
   2  * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "asm/macroAssembler.inline.hpp"
  27 #include "asm/assembler.hpp"
  28 #include "c1/c1_CodeStubs.hpp"
  29 #include "c1/c1_Compilation.hpp"
  30 #include "c1/c1_LIRAssembler.hpp"
  31 #include "c1/c1_MacroAssembler.hpp"
  32 #include "c1/c1_Runtime1.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "ci/ciArrayKlass.hpp"
  35 #include "ci/ciInlineKlass.hpp"
  36 #include "ci/ciInstance.hpp"
  37 #include "ci/ciObjArrayKlass.hpp"
  38 #include "code/compiledIC.hpp"
  39 #include "gc/shared/collectedHeap.hpp"
  40 #include "gc/shared/gc_globals.hpp"
  41 #include "nativeInst_aarch64.hpp"
  42 #include "oops/objArrayKlass.hpp"
  43 #include "oops/oop.inline.hpp"
  44 #include "runtime/frame.inline.hpp"
  45 #include "runtime/sharedRuntime.hpp"
  46 #include "runtime/stubRoutines.hpp"
  47 #include "utilities/powerOfTwo.hpp"
  48 #include "vmreg_aarch64.inline.hpp"
  49 
  50 
  51 #ifndef PRODUCT
  52 #define COMMENT(x)   do { __ block_comment(x); } while (0)
  53 #else
  54 #define COMMENT(x)
  55 #endif
  56 
  57 NEEDS_CLEANUP // remove this definitions ?
  58 const Register SYNC_header = r0;   // synchronization header
  59 const Register SHIFT_count = r0;   // where count for shift operations must be
  60 
  61 #define __ _masm->
  62 
  63 
  64 static void select_different_registers(Register preserve,
  65                                        Register extra,
  66                                        Register &tmp1,
  67                                        Register &tmp2) {
  68   if (tmp1 == preserve) {
  69     assert_different_registers(tmp1, tmp2, extra);
  70     tmp1 = extra;
  71   } else if (tmp2 == preserve) {
  72     assert_different_registers(tmp1, tmp2, extra);
  73     tmp2 = extra;
  74   }
  75   assert_different_registers(preserve, tmp1, tmp2);
  76 }
  77 
  78 
  79 
  80 static void select_different_registers(Register preserve,
  81                                        Register extra,
  82                                        Register &tmp1,
  83                                        Register &tmp2,
  84                                        Register &tmp3) {
  85   if (tmp1 == preserve) {
  86     assert_different_registers(tmp1, tmp2, tmp3, extra);
  87     tmp1 = extra;
  88   } else if (tmp2 == preserve) {
  89     assert_different_registers(tmp1, tmp2, tmp3, extra);
  90     tmp2 = extra;
  91   } else if (tmp3 == preserve) {
  92     assert_different_registers(tmp1, tmp2, tmp3, extra);
  93     tmp3 = extra;
  94   }
  95   assert_different_registers(preserve, tmp1, tmp2, tmp3);
  96 }
  97 
  98 
  99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
 100 
 101 
 102 LIR_Opr LIR_Assembler::receiverOpr() {
 103   return FrameMap::receiver_opr;
 104 }
 105 
 106 LIR_Opr LIR_Assembler::osrBufferPointer() {
 107   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 108 }
 109 
 110 //--------------fpu register translations-----------------------
 111 
 112 
 113 address LIR_Assembler::float_constant(float f) {
 114   address const_addr = __ float_constant(f);
 115   if (const_addr == nullptr) {
 116     bailout("const section overflow");
 117     return __ code()->consts()->start();
 118   } else {
 119     return const_addr;
 120   }
 121 }
 122 
 123 
 124 address LIR_Assembler::double_constant(double d) {
 125   address const_addr = __ double_constant(d);
 126   if (const_addr == nullptr) {
 127     bailout("const section overflow");
 128     return __ code()->consts()->start();
 129   } else {
 130     return const_addr;
 131   }
 132 }
 133 
 134 address LIR_Assembler::int_constant(jlong n) {
 135   address const_addr = __ long_constant(n);
 136   if (const_addr == nullptr) {
 137     bailout("const section overflow");
 138     return __ code()->consts()->start();
 139   } else {
 140     return const_addr;
 141   }
 142 }
 143 
 144 void LIR_Assembler::breakpoint() { Unimplemented(); }
 145 
 146 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
 147 
 148 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
 149 
 150 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
 151 //-------------------------------------------
 152 
 153 static Register as_reg(LIR_Opr op) {
 154   return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
 155 }
 156 
 157 static jlong as_long(LIR_Opr data) {
 158   jlong result;
 159   switch (data->type()) {
 160   case T_INT:
 161     result = (data->as_jint());
 162     break;
 163   case T_LONG:
 164     result = (data->as_jlong());
 165     break;
 166   default:
 167     ShouldNotReachHere();
 168     result = 0;  // unreachable
 169   }
 170   return result;
 171 }
 172 
 173 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 174   Register base = addr->base()->as_pointer_register();
 175   LIR_Opr opr = addr->index();
 176   if (opr->is_cpu_register()) {
 177     Register index;
 178     if (opr->is_single_cpu())
 179       index = opr->as_register();
 180     else
 181       index = opr->as_register_lo();
 182     assert(addr->disp() == 0, "must be");
 183     switch(opr->type()) {
 184       case T_INT:
 185         return Address(base, index, Address::sxtw(addr->scale()));
 186       case T_LONG:
 187         return Address(base, index, Address::lsl(addr->scale()));
 188       default:
 189         ShouldNotReachHere();
 190       }
 191   } else {
 192     assert(addr->scale() == 0,
 193            "expected for immediate operand, was: %d", addr->scale());
 194     ptrdiff_t offset = ptrdiff_t(addr->disp());
 195     // NOTE: Does not handle any 16 byte vector access.
 196     const uint type_size = type2aelembytes(addr->type(), true);
 197     return __ legitimize_address(Address(base, offset), type_size, tmp);
 198   }
 199   return Address();
 200 }
 201 
 202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 203   ShouldNotReachHere();
 204   return Address();
 205 }
 206 
 207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 208   return as_Address(addr, rscratch1);
 209 }
 210 
 211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 212   return as_Address(addr, rscratch1);  // Ouch
 213   // FIXME: This needs to be much more clever.  See x86.
 214 }
 215 
 216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
 217 // not encodable as a base + (immediate) offset, generate an explicit address
 218 // calculation to hold the address in a temporary register.
 219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
 220   precond(size == 4 || size == 8);
 221   Address addr = frame_map()->address_for_slot(index, adjust);
 222   precond(addr.getMode() == Address::base_plus_offset);
 223   precond(addr.base() == sp);
 224   precond(addr.offset() > 0);
 225   uint mask = size - 1;
 226   assert((addr.offset() & mask) == 0, "scaled offsets only");
 227   return __ legitimize_address(addr, size, tmp);
 228 }
 229 
 230 void LIR_Assembler::osr_entry() {
 231   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 232   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 233   ValueStack* entry_state = osr_entry->state();
 234   int number_of_locks = entry_state->locks_size();
 235 
 236   // we jump here if osr happens with the interpreter
 237   // state set up to continue at the beginning of the
 238   // loop that triggered osr - in particular, we have
 239   // the following registers setup:
 240   //
 241   // r2: osr buffer
 242   //
 243 
 244   // build frame
 245   ciMethod* m = compilation()->method();
 246   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 247 
 248   // OSR buffer is
 249   //
 250   // locals[nlocals-1..0]
 251   // monitors[0..number_of_locks]
 252   //
 253   // locals is a direct copy of the interpreter frame so in the osr buffer
 254   // so first slot in the local array is the last local from the interpreter
 255   // and last slot is local[0] (receiver) from the interpreter
 256   //
 257   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 258   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 259   // in the interpreter frame (the method lock if a sync method)
 260 
 261   // Initialize monitors in the compiled activation.
 262   //   r2: pointer to osr buffer
 263   //
 264   // All other registers are dead at this point and the locals will be
 265   // copied into place by code emitted in the IR.
 266 
 267   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 268   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 269     int monitor_offset = BytesPerWord * method()->max_locals() +
 270       (2 * BytesPerWord) * (number_of_locks - 1);
 271     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 272     // the OSR buffer using 2 word entries: first the lock and then
 273     // the oop.
 274     for (int i = 0; i < number_of_locks; i++) {
 275       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 276 #ifdef ASSERT
 277       // verify the interpreter's monitor has a non-null object
 278       {
 279         Label L;
 280         __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
 281         __ cbnz(rscratch1, L);
 282         __ stop("locked object is null");
 283         __ bind(L);
 284       }
 285 #endif
 286       __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
 287       __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
 288       __ str(r19, frame_map()->address_for_monitor_lock(i));
 289       __ str(r20, frame_map()->address_for_monitor_object(i));
 290     }
 291   }
 292 }
 293 
 294 
 295 // inline cache check; done before the frame is built.
 296 int LIR_Assembler::check_icache() {
 297   return __ ic_check(CodeEntryAlignment);
 298 }
 299 
 300 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 301   assert(VM_Version::supports_fast_class_init_checks(), "sanity");
 302   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
 303 
 304   Label L_skip_barrier;
 305 
 306   __ mov_metadata(rscratch2, method->holder()->constant_encoding());
 307   __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
 308   __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 309   __ bind(L_skip_barrier);
 310 }
 311 
 312 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 313   if (o == nullptr) {
 314     __ mov(reg, zr);
 315   } else {
 316     __ movoop(reg, o);
 317   }
 318 }
 319 
 320 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
 321   address target = nullptr;
 322   relocInfo::relocType reloc_type = relocInfo::none;
 323 
 324   switch (patching_id(info)) {
 325   case PatchingStub::access_field_id:
 326     target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
 327     reloc_type = relocInfo::section_word_type;
 328     break;
 329   case PatchingStub::load_klass_id:
 330     target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
 331     reloc_type = relocInfo::metadata_type;
 332     break;
 333   case PatchingStub::load_mirror_id:
 334     target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
 335     reloc_type = relocInfo::oop_type;
 336     break;
 337   case PatchingStub::load_appendix_id:
 338     target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
 339     reloc_type = relocInfo::oop_type;
 340     break;
 341   default: ShouldNotReachHere();
 342   }
 343 
 344   __ far_call(RuntimeAddress(target));
 345   add_call_info_here(info);
 346 }
 347 
 348 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 349   deoptimize_trap(info);
 350 }
 351 
 352 
 353 // This specifies the rsp decrement needed to build the frame
 354 int LIR_Assembler::initial_frame_size_in_bytes() const {
 355   // if rounding, must let FrameMap know!
 356 
 357   return in_bytes(frame_map()->framesize_in_bytes());
 358 }
 359 
 360 
 361 int LIR_Assembler::emit_exception_handler() {
 362   // generate code for exception handler
 363   address handler_base = __ start_a_stub(exception_handler_size());
 364   if (handler_base == nullptr) {
 365     // not enough space left for the handler
 366     bailout("exception handler overflow");
 367     return -1;
 368   }
 369 
 370   int offset = code_offset();
 371 
 372   // the exception oop and pc are in r0, and r3
 373   // no other registers need to be preserved, so invalidate them
 374   __ invalidate_registers(false, true, true, false, true, true);
 375 
 376   // check that there is really an exception
 377   __ verify_not_null_oop(r0);
 378 
 379   // search an exception handler (r0: exception oop, r3: throwing pc)
 380   __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
 381   __ should_not_reach_here();
 382   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 383   __ end_a_stub();
 384 
 385   return offset;
 386 }
 387 
 388 
 389 // Emit the code to remove the frame from the stack in the exception
 390 // unwind path.
 391 int LIR_Assembler::emit_unwind_handler() {
 392 #ifndef PRODUCT
 393   if (CommentedAssembly) {
 394     _masm->block_comment("Unwind handler");
 395   }
 396 #endif
 397 
 398   int offset = code_offset();
 399 
 400   // Fetch the exception from TLS and clear out exception related thread state
 401   __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
 402   __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
 403   __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
 404 
 405   __ bind(_unwind_handler_entry);
 406   __ verify_not_null_oop(r0);
 407   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 408     __ mov(r19, r0);  // Preserve the exception
 409   }
 410 
 411   // Perform needed unlocking
 412   MonitorExitStub* stub = nullptr;
 413   if (method()->is_synchronized()) {
 414     monitor_address(0, FrameMap::r0_opr);
 415     stub = new MonitorExitStub(FrameMap::r0_opr, 0);
 416     __ unlock_object(r5, r4, r0, r6, *stub->entry());
 417     __ bind(*stub->continuation());
 418   }
 419 
 420   if (compilation()->env()->dtrace_method_probes()) {
 421     __ mov(c_rarg0, rthread);
 422     __ mov_metadata(c_rarg1, method()->constant_encoding());
 423     __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
 424   }
 425 
 426   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 427     __ mov(r0, r19);  // Restore the exception
 428   }
 429 
 430   // remove the activation and dispatch to the unwind handler
 431   __ block_comment("remove_frame and dispatch to the unwind handler");
 432   __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
 433   __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
 434 
 435   // Emit the slow path assembly
 436   if (stub != nullptr) {
 437     stub->emit_code(this);
 438   }
 439 
 440   return offset;
 441 }
 442 
 443 
 444 int LIR_Assembler::emit_deopt_handler() {
 445   // generate code for exception handler
 446   address handler_base = __ start_a_stub(deopt_handler_size());
 447   if (handler_base == nullptr) {
 448     // not enough space left for the handler
 449     bailout("deopt handler overflow");
 450     return -1;
 451   }
 452 
 453   int offset = code_offset();
 454 
 455   __ adr(lr, pc());
 456   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 457   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 458   __ end_a_stub();
 459 
 460   return offset;
 461 }
 462 
 463 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
 464   _masm->code_section()->relocate(adr, relocInfo::poll_type);
 465   int pc_offset = code_offset();
 466   flush_debug_info(pc_offset);
 467   info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
 468   if (info->exception_handlers() != nullptr) {
 469     compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
 470   }
 471 }
 472 
 473 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
 474   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
 475 
 476   if (InlineTypeReturnedAsFields) {
 477     // Check if we are returning an non-null inline type and load its fields into registers
 478     ciType* return_type = compilation()->method()->return_type();
 479     if (return_type->is_inlinetype()) {
 480       ciInlineKlass* vk = return_type->as_inline_klass();
 481       if (vk->can_be_returned_as_fields()) {
 482         address unpack_handler = vk->unpack_handler();
 483         assert(unpack_handler != nullptr, "must be");
 484         __ far_call(RuntimeAddress(unpack_handler));
 485       }
 486     } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) {
 487       Label skip;
 488       Label not_null;
 489       __ cbnz(r0, not_null);
 490       // Returned value is null, zero all return registers because they may belong to oop fields
 491       __ mov(j_rarg1, zr);
 492       __ mov(j_rarg2, zr);
 493       __ mov(j_rarg3, zr);
 494       __ mov(j_rarg4, zr);
 495       __ mov(j_rarg5, zr);
 496       __ mov(j_rarg6, zr);
 497       __ mov(j_rarg7, zr);
 498       __ b(skip);
 499       __ bind(not_null);
 500 
 501       // Check if we are returning an non-null inline type and load its fields into registers
 502       __ test_oop_is_not_inline_type(r0, rscratch2, skip, /* can_be_null= */ false);
 503 
 504       // Load fields from a buffered value with an inline class specific handler
 505       __ load_klass(rscratch1 /*dst*/, r0 /*src*/);
 506       __ ldr(rscratch1, Address(rscratch1, InstanceKlass::adr_inlineklass_fixed_block_offset()));
 507       __ ldr(rscratch1, Address(rscratch1, InlineKlass::unpack_handler_offset()));
 508       // Unpack handler can be null if inline type is not scalarizable in returns
 509       __ cbz(rscratch1, skip);
 510       __ blr(rscratch1);
 511 
 512       __ bind(skip);
 513     }
 514     // At this point, r0 points to the value object (for interpreter or C1 caller).
 515     // The fields of the object are copied into registers (for C2 caller).
 516   }
 517 
 518   // Pop the stack before the safepoint code
 519   __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
 520 
 521   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 522     __ reserved_stack_check();
 523   }
 524 
 525   code_stub->set_safepoint_offset(__ offset());
 526   __ relocate(relocInfo::poll_return_type);
 527   __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
 528   __ ret(lr);
 529 }
 530 
 531 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
 532   return (__ store_inline_type_fields_to_buf(vk, false));
 533 }
 534 
 535 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 536   guarantee(info != nullptr, "Shouldn't be null");
 537   __ get_polling_page(rscratch1, relocInfo::poll_type);
 538   add_debug_info_for_branch(info);  // This isn't just debug info:
 539                                     // it's the oop map
 540   __ read_polling_page(rscratch1, relocInfo::poll_type);
 541   return __ offset();
 542 }
 543 
 544 
 545 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 546   if (from_reg == r31_sp)
 547     from_reg = sp;
 548   if (to_reg == r31_sp)
 549     to_reg = sp;
 550   __ mov(to_reg, from_reg);
 551 }
 552 
 553 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
 554 
 555 
 556 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 557   assert(src->is_constant(), "should not call otherwise");
 558   assert(dest->is_register(), "should not call otherwise");
 559   LIR_Const* c = src->as_constant_ptr();
 560 
 561   switch (c->type()) {
 562     case T_INT: {
 563       assert(patch_code == lir_patch_none, "no patching handled here");
 564       __ movw(dest->as_register(), c->as_jint());
 565       break;
 566     }
 567 
 568     case T_ADDRESS: {
 569       assert(patch_code == lir_patch_none, "no patching handled here");
 570       __ mov(dest->as_register(), c->as_jint());
 571       break;
 572     }
 573 
 574     case T_LONG: {
 575       assert(patch_code == lir_patch_none, "no patching handled here");
 576       __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
 577       break;
 578     }
 579 
 580     case T_OBJECT: {
 581         if (patch_code != lir_patch_none) {
 582           jobject2reg_with_patching(dest->as_register(), info);
 583         } else {
 584           jobject2reg(c->as_jobject(), dest->as_register());
 585         }
 586       break;
 587     }
 588 
 589     case T_METADATA: {
 590       if (patch_code != lir_patch_none) {
 591         klass2reg_with_patching(dest->as_register(), info);
 592       } else {
 593         __ mov_metadata(dest->as_register(), c->as_metadata());
 594       }
 595       break;
 596     }
 597 
 598     case T_FLOAT: {
 599       if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
 600         __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
 601       } else {
 602         __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
 603         __ ldrs(dest->as_float_reg(), Address(rscratch1));
 604       }
 605       break;
 606     }
 607 
 608     case T_DOUBLE: {
 609       if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
 610         __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
 611       } else {
 612         __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
 613         __ ldrd(dest->as_double_reg(), Address(rscratch1));
 614       }
 615       break;
 616     }
 617 
 618     default:
 619       ShouldNotReachHere();
 620   }
 621 }
 622 
 623 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 624   LIR_Const* c = src->as_constant_ptr();
 625   switch (c->type()) {
 626   case T_OBJECT:
 627     {
 628       if (! c->as_jobject())
 629         __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 630       else {
 631         const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
 632         reg2stack(FrameMap::rscratch1_opr, dest, c->type());
 633       }
 634     }
 635     break;
 636   case T_ADDRESS:
 637     {
 638       const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
 639       reg2stack(FrameMap::rscratch1_opr, dest, c->type());
 640     }
 641   case T_INT:
 642   case T_FLOAT:
 643     {
 644       Register reg = zr;
 645       if (c->as_jint_bits() == 0)
 646         __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 647       else {
 648         __ movw(rscratch1, c->as_jint_bits());
 649         __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
 650       }
 651     }
 652     break;
 653   case T_LONG:
 654   case T_DOUBLE:
 655     {
 656       Register reg = zr;
 657       if (c->as_jlong_bits() == 0)
 658         __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
 659                                                  lo_word_offset_in_bytes));
 660       else {
 661         __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
 662         __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
 663                                                         lo_word_offset_in_bytes));
 664       }
 665     }
 666     break;
 667   default:
 668     ShouldNotReachHere();
 669   }
 670 }
 671 
 672 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 673   assert(src->is_constant(), "should not call otherwise");
 674   LIR_Const* c = src->as_constant_ptr();
 675   LIR_Address* to_addr = dest->as_address_ptr();
 676 
 677   void (Assembler::* insn)(Register Rt, const Address &adr);
 678 
 679   switch (type) {
 680   case T_ADDRESS:
 681     assert(c->as_jint() == 0, "should be");
 682     insn = &Assembler::str;
 683     break;
 684   case T_LONG:
 685     assert(c->as_jlong() == 0, "should be");
 686     insn = &Assembler::str;
 687     break;
 688   case T_INT:
 689     assert(c->as_jint() == 0, "should be");
 690     insn = &Assembler::strw;
 691     break;
 692   case T_OBJECT:
 693   case T_ARRAY:
 694     // Non-null case is not handled on aarch64 but handled on x86
 695     // FIXME: do we need to add it here?
 696     assert(c->as_jobject() == nullptr, "should be");
 697     if (UseCompressedOops && !wide) {
 698       insn = &Assembler::strw;
 699     } else {
 700       insn = &Assembler::str;
 701     }
 702     break;
 703   case T_CHAR:
 704   case T_SHORT:
 705     assert(c->as_jint() == 0, "should be");
 706     insn = &Assembler::strh;
 707     break;
 708   case T_BOOLEAN:
 709   case T_BYTE:
 710     assert(c->as_jint() == 0, "should be");
 711     insn = &Assembler::strb;
 712     break;
 713   default:
 714     ShouldNotReachHere();
 715     insn = &Assembler::str;  // unreachable
 716   }
 717 
 718   if (info) add_debug_info_for_null_check_here(info);
 719   (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
 720 }
 721 
 722 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 723   assert(src->is_register(), "should not call otherwise");
 724   assert(dest->is_register(), "should not call otherwise");
 725 
 726   // move between cpu-registers
 727   if (dest->is_single_cpu()) {
 728     if (src->type() == T_LONG) {
 729       // Can do LONG -> OBJECT
 730       move_regs(src->as_register_lo(), dest->as_register());
 731       return;
 732     }
 733     assert(src->is_single_cpu(), "must match");
 734     if (src->type() == T_OBJECT) {
 735       __ verify_oop(src->as_register());
 736     }
 737     move_regs(src->as_register(), dest->as_register());
 738 
 739   } else if (dest->is_double_cpu()) {
 740     if (is_reference_type(src->type())) {
 741       // Surprising to me but we can see move of a long to t_object
 742       __ verify_oop(src->as_register());
 743       move_regs(src->as_register(), dest->as_register_lo());
 744       return;
 745     }
 746     assert(src->is_double_cpu(), "must match");
 747     Register f_lo = src->as_register_lo();
 748     Register f_hi = src->as_register_hi();
 749     Register t_lo = dest->as_register_lo();
 750     Register t_hi = dest->as_register_hi();
 751     assert(f_hi == f_lo, "must be same");
 752     assert(t_hi == t_lo, "must be same");
 753     move_regs(f_lo, t_lo);
 754 
 755   } else if (dest->is_single_fpu()) {
 756     __ fmovs(dest->as_float_reg(), src->as_float_reg());
 757 
 758   } else if (dest->is_double_fpu()) {
 759     __ fmovd(dest->as_double_reg(), src->as_double_reg());
 760 
 761   } else {
 762     ShouldNotReachHere();
 763   }
 764 }
 765 
 766 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 767   precond(src->is_register() && dest->is_stack());
 768 
 769   uint const c_sz32 = sizeof(uint32_t);
 770   uint const c_sz64 = sizeof(uint64_t);
 771 
 772   if (src->is_single_cpu()) {
 773     int index = dest->single_stack_ix();
 774     if (is_reference_type(type)) {
 775       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 776       __ verify_oop(src->as_register());
 777     } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
 778       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 779     } else {
 780       __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 781     }
 782 
 783   } else if (src->is_double_cpu()) {
 784     int index = dest->double_stack_ix();
 785     Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 786     __ str(src->as_register_lo(), dest_addr_LO);
 787 
 788   } else if (src->is_single_fpu()) {
 789     int index = dest->single_stack_ix();
 790     __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 791 
 792   } else if (src->is_double_fpu()) {
 793     int index = dest->double_stack_ix();
 794     __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 795 
 796   } else {
 797     ShouldNotReachHere();
 798   }
 799 }
 800 
 801 
 802 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
 803   LIR_Address* to_addr = dest->as_address_ptr();
 804   PatchingStub* patch = nullptr;
 805   Register compressed_src = rscratch1;
 806 
 807   if (patch_code != lir_patch_none) {
 808     deoptimize_trap(info);
 809     return;
 810   }
 811 
 812   if (is_reference_type(type)) {
 813     __ verify_oop(src->as_register());
 814 
 815     if (UseCompressedOops && !wide) {
 816       __ encode_heap_oop(compressed_src, src->as_register());
 817     } else {
 818       compressed_src = src->as_register();
 819     }
 820   }
 821 
 822   int null_check_here = code_offset();
 823   switch (type) {
 824     case T_FLOAT: {
 825       __ strs(src->as_float_reg(), as_Address(to_addr));
 826       break;
 827     }
 828 
 829     case T_DOUBLE: {
 830       __ strd(src->as_double_reg(), as_Address(to_addr));
 831       break;
 832     }
 833 
 834     case T_ARRAY:   // fall through
 835     case T_OBJECT:  // fall through
 836       if (UseCompressedOops && !wide) {
 837         __ strw(compressed_src, as_Address(to_addr, rscratch2));
 838       } else {
 839          __ str(compressed_src, as_Address(to_addr));
 840       }
 841       break;
 842     case T_METADATA:
 843       // We get here to store a method pointer to the stack to pass to
 844       // a dtrace runtime call. This can't work on 64 bit with
 845       // compressed klass ptrs: T_METADATA can be a compressed klass
 846       // ptr or a 64 bit method pointer.
 847       ShouldNotReachHere();
 848       __ str(src->as_register(), as_Address(to_addr));
 849       break;
 850     case T_ADDRESS:
 851       __ str(src->as_register(), as_Address(to_addr));
 852       break;
 853     case T_INT:
 854       __ strw(src->as_register(), as_Address(to_addr));
 855       break;
 856 
 857     case T_LONG: {
 858       __ str(src->as_register_lo(), as_Address_lo(to_addr));
 859       break;
 860     }
 861 
 862     case T_BYTE:    // fall through
 863     case T_BOOLEAN: {
 864       __ strb(src->as_register(), as_Address(to_addr));
 865       break;
 866     }
 867 
 868     case T_CHAR:    // fall through
 869     case T_SHORT:
 870       __ strh(src->as_register(), as_Address(to_addr));
 871       break;
 872 
 873     default:
 874       ShouldNotReachHere();
 875   }
 876   if (info != nullptr) {
 877     add_debug_info_for_null_check(null_check_here, info);
 878   }
 879 }
 880 
 881 
 882 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
 883   precond(src->is_stack() && dest->is_register());
 884 
 885   uint const c_sz32 = sizeof(uint32_t);
 886   uint const c_sz64 = sizeof(uint64_t);
 887 
 888   if (dest->is_single_cpu()) {
 889     int index = src->single_stack_ix();
 890     if (is_reference_type(type)) {
 891       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 892       __ verify_oop(dest->as_register());
 893     } else if (type == T_METADATA || type == T_ADDRESS) {
 894       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 895     } else {
 896       __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 897     }
 898 
 899   } else if (dest->is_double_cpu()) {
 900     int index = src->double_stack_ix();
 901     Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 902     __ ldr(dest->as_register_lo(), src_addr_LO);
 903 
 904   } else if (dest->is_single_fpu()) {
 905     int index = src->single_stack_ix();
 906     __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 907 
 908   } else if (dest->is_double_fpu()) {
 909     int index = src->double_stack_ix();
 910     __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 911 
 912   } else {
 913     ShouldNotReachHere();
 914   }
 915 }
 916 
 917 
 918 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 919   address target = nullptr;
 920   relocInfo::relocType reloc_type = relocInfo::none;
 921 
 922   switch (patching_id(info)) {
 923   case PatchingStub::access_field_id:
 924     target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
 925     reloc_type = relocInfo::section_word_type;
 926     break;
 927   case PatchingStub::load_klass_id:
 928     target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
 929     reloc_type = relocInfo::metadata_type;
 930     break;
 931   case PatchingStub::load_mirror_id:
 932     target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
 933     reloc_type = relocInfo::oop_type;
 934     break;
 935   case PatchingStub::load_appendix_id:
 936     target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
 937     reloc_type = relocInfo::oop_type;
 938     break;
 939   default: ShouldNotReachHere();
 940   }
 941 
 942   __ far_call(RuntimeAddress(target));
 943   add_call_info_here(info);
 944 }
 945 
 946 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 947 
 948   LIR_Opr temp;
 949   if (type == T_LONG || type == T_DOUBLE)
 950     temp = FrameMap::rscratch1_long_opr;
 951   else
 952     temp = FrameMap::rscratch1_opr;
 953 
 954   stack2reg(src, temp, src->type());
 955   reg2stack(temp, dest, dest->type());
 956 }
 957 
 958 
 959 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
 960   LIR_Address* addr = src->as_address_ptr();
 961   LIR_Address* from_addr = src->as_address_ptr();
 962 
 963   if (addr->base()->type() == T_OBJECT) {
 964     __ verify_oop(addr->base()->as_pointer_register());
 965   }
 966 
 967   if (patch_code != lir_patch_none) {
 968     deoptimize_trap(info);
 969     return;
 970   }
 971 
 972   if (info != nullptr) {
 973     add_debug_info_for_null_check_here(info);
 974   }
 975   int null_check_here = code_offset();
 976   switch (type) {
 977     case T_FLOAT: {
 978       __ ldrs(dest->as_float_reg(), as_Address(from_addr));
 979       break;
 980     }
 981 
 982     case T_DOUBLE: {
 983       __ ldrd(dest->as_double_reg(), as_Address(from_addr));
 984       break;
 985     }
 986 
 987     case T_ARRAY:   // fall through
 988     case T_OBJECT:  // fall through
 989       if (UseCompressedOops && !wide) {
 990         __ ldrw(dest->as_register(), as_Address(from_addr));
 991       } else {
 992         __ ldr(dest->as_register(), as_Address(from_addr));
 993       }
 994       break;
 995     case T_METADATA:
 996       // We get here to store a method pointer to the stack to pass to
 997       // a dtrace runtime call. This can't work on 64 bit with
 998       // compressed klass ptrs: T_METADATA can be a compressed klass
 999       // ptr or a 64 bit method pointer.
1000       ShouldNotReachHere();
1001       __ ldr(dest->as_register(), as_Address(from_addr));
1002       break;
1003     case T_ADDRESS:
1004       __ ldr(dest->as_register(), as_Address(from_addr));
1005       break;
1006     case T_INT:
1007       __ ldrw(dest->as_register(), as_Address(from_addr));
1008       break;
1009 
1010     case T_LONG: {
1011       __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1012       break;
1013     }
1014 
1015     case T_BYTE:
1016       __ ldrsb(dest->as_register(), as_Address(from_addr));
1017       break;
1018     case T_BOOLEAN: {
1019       __ ldrb(dest->as_register(), as_Address(from_addr));
1020       break;
1021     }
1022 
1023     case T_CHAR:
1024       __ ldrh(dest->as_register(), as_Address(from_addr));
1025       break;
1026     case T_SHORT:
1027       __ ldrsh(dest->as_register(), as_Address(from_addr));
1028       break;
1029 
1030     default:
1031       ShouldNotReachHere();
1032   }
1033 
1034   if (is_reference_type(type)) {
1035     if (UseCompressedOops && !wide) {
1036       __ decode_heap_oop(dest->as_register());
1037     }
1038 
1039     __ verify_oop(dest->as_register());
1040   }
1041 }
1042 
1043 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
1044   assert(dst->is_cpu_register(), "must be");
1045   assert(dst->type() == src->type(), "must be");
1046 
1047   if (src->is_cpu_register()) {
1048     reg2reg(src, dst);
1049   } else if (src->is_stack()) {
1050     stack2reg(src, dst, dst->type());
1051   } else if (src->is_constant()) {
1052     const2reg(src, dst, lir_patch_none, nullptr);
1053   } else {
1054     ShouldNotReachHere();
1055   }
1056 }
1057 
1058 int LIR_Assembler::array_element_size(BasicType type) const {
1059   int elem_size = type2aelembytes(type);
1060   return exact_log2(elem_size);
1061 }
1062 
1063 
1064 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1065   switch (op->code()) {
1066   case lir_idiv:
1067   case lir_irem:
1068     arithmetic_idiv(op->code(),
1069                     op->in_opr1(),
1070                     op->in_opr2(),
1071                     op->in_opr3(),
1072                     op->result_opr(),
1073                     op->info());
1074     break;
1075   case lir_fmad:
1076     __ fmaddd(op->result_opr()->as_double_reg(),
1077               op->in_opr1()->as_double_reg(),
1078               op->in_opr2()->as_double_reg(),
1079               op->in_opr3()->as_double_reg());
1080     break;
1081   case lir_fmaf:
1082     __ fmadds(op->result_opr()->as_float_reg(),
1083               op->in_opr1()->as_float_reg(),
1084               op->in_opr2()->as_float_reg(),
1085               op->in_opr3()->as_float_reg());
1086     break;
1087   default:      ShouldNotReachHere(); break;
1088   }
1089 }
1090 
1091 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1092 #ifdef ASSERT
1093   assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1094   if (op->block() != nullptr)  _branch_target_blocks.append(op->block());
1095   if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1096 #endif
1097 
1098   if (op->cond() == lir_cond_always) {
1099     if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1100     __ b(*(op->label()));
1101   } else {
1102     Assembler::Condition acond;
1103     if (op->code() == lir_cond_float_branch) {
1104       bool is_unordered = (op->ublock() == op->block());
1105       // Assembler::EQ does not permit unordered branches, so we add
1106       // another branch here.  Likewise, Assembler::NE does not permit
1107       // ordered branches.
1108       if ((is_unordered && op->cond() == lir_cond_equal)
1109           || (!is_unordered && op->cond() == lir_cond_notEqual))
1110         __ br(Assembler::VS, *(op->ublock()->label()));
1111       switch(op->cond()) {
1112       case lir_cond_equal:        acond = Assembler::EQ; break;
1113       case lir_cond_notEqual:     acond = Assembler::NE; break;
1114       case lir_cond_less:         acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1115       case lir_cond_lessEqual:    acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1116       case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1117       case lir_cond_greater:      acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1118       default:                    ShouldNotReachHere();
1119         acond = Assembler::EQ;  // unreachable
1120       }
1121     } else {
1122       switch (op->cond()) {
1123         case lir_cond_equal:        acond = Assembler::EQ; break;
1124         case lir_cond_notEqual:     acond = Assembler::NE; break;
1125         case lir_cond_less:         acond = Assembler::LT; break;
1126         case lir_cond_lessEqual:    acond = Assembler::LE; break;
1127         case lir_cond_greaterEqual: acond = Assembler::GE; break;
1128         case lir_cond_greater:      acond = Assembler::GT; break;
1129         case lir_cond_belowEqual:   acond = Assembler::LS; break;
1130         case lir_cond_aboveEqual:   acond = Assembler::HS; break;
1131         default:                    ShouldNotReachHere();
1132           acond = Assembler::EQ;  // unreachable
1133       }
1134     }
1135     __ br(acond,*(op->label()));
1136   }
1137 }
1138 
1139 
1140 
1141 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1142   LIR_Opr src  = op->in_opr();
1143   LIR_Opr dest = op->result_opr();
1144 
1145   switch (op->bytecode()) {
1146     case Bytecodes::_i2f:
1147       {
1148         __ scvtfws(dest->as_float_reg(), src->as_register());
1149         break;
1150       }
1151     case Bytecodes::_i2d:
1152       {
1153         __ scvtfwd(dest->as_double_reg(), src->as_register());
1154         break;
1155       }
1156     case Bytecodes::_l2d:
1157       {
1158         __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1159         break;
1160       }
1161     case Bytecodes::_l2f:
1162       {
1163         __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1164         break;
1165       }
1166     case Bytecodes::_f2d:
1167       {
1168         __ fcvts(dest->as_double_reg(), src->as_float_reg());
1169         break;
1170       }
1171     case Bytecodes::_d2f:
1172       {
1173         __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1174         break;
1175       }
1176     case Bytecodes::_i2c:
1177       {
1178         __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1179         break;
1180       }
1181     case Bytecodes::_i2l:
1182       {
1183         __ sxtw(dest->as_register_lo(), src->as_register());
1184         break;
1185       }
1186     case Bytecodes::_i2s:
1187       {
1188         __ sxth(dest->as_register(), src->as_register());
1189         break;
1190       }
1191     case Bytecodes::_i2b:
1192       {
1193         __ sxtb(dest->as_register(), src->as_register());
1194         break;
1195       }
1196     case Bytecodes::_l2i:
1197       {
1198         _masm->block_comment("FIXME: This could be a no-op");
1199         __ uxtw(dest->as_register(), src->as_register_lo());
1200         break;
1201       }
1202     case Bytecodes::_d2l:
1203       {
1204         __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1205         break;
1206       }
1207     case Bytecodes::_f2i:
1208       {
1209         __ fcvtzsw(dest->as_register(), src->as_float_reg());
1210         break;
1211       }
1212     case Bytecodes::_f2l:
1213       {
1214         __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1215         break;
1216       }
1217     case Bytecodes::_d2i:
1218       {
1219         __ fcvtzdw(dest->as_register(), src->as_double_reg());
1220         break;
1221       }
1222     default: ShouldNotReachHere();
1223   }
1224 }
1225 
1226 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1227   if (op->init_check()) {
1228     __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1229     __ ldarb(rscratch1, rscratch1);
1230     __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1231     add_debug_info_for_null_check_here(op->stub()->info());
1232     __ br(Assembler::NE, *op->stub()->entry());
1233   }
1234   __ allocate_object(op->obj()->as_register(),
1235                      op->tmp1()->as_register(),
1236                      op->tmp2()->as_register(),
1237                      op->header_size(),
1238                      op->object_size(),
1239                      op->klass()->as_register(),
1240                      *op->stub()->entry());
1241   __ bind(*op->stub()->continuation());
1242 }
1243 
1244 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1245   Register len =  op->len()->as_register();
1246   __ uxtw(len, len);
1247 
1248   if (UseSlowPath || op->always_slow_path() ||
1249       (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1250       (!UseFastNewTypeArray   && !is_reference_type(op->type()))) {
1251     __ b(*op->stub()->entry());
1252   } else {
1253     Register tmp1 = op->tmp1()->as_register();
1254     Register tmp2 = op->tmp2()->as_register();
1255     Register tmp3 = op->tmp3()->as_register();
1256     if (len == tmp1) {
1257       tmp1 = tmp3;
1258     } else if (len == tmp2) {
1259       tmp2 = tmp3;
1260     } else if (len == tmp3) {
1261       // everything is ok
1262     } else {
1263       __ mov(tmp3, len);
1264     }
1265     __ allocate_array(op->obj()->as_register(),
1266                       len,
1267                       tmp1,
1268                       tmp2,
1269                       arrayOopDesc::base_offset_in_bytes(op->type()),
1270                       array_element_size(op->type()),
1271                       op->klass()->as_register(),
1272                       *op->stub()->entry(),
1273                       op->zero_array());
1274   }
1275   __ bind(*op->stub()->continuation());
1276 }
1277 
1278 void LIR_Assembler::type_profile_helper(Register mdo,
1279                                         ciMethodData *md, ciProfileData *data,
1280                                         Register recv, Label* update_done) {
1281 
1282   // Given a profile data offset, generate an Address which points to
1283   // the corresponding slot in mdo->data().
1284   // Clobbers rscratch2.
1285   auto slot_at = [=](ByteSize offset) -> Address {
1286     return __ form_address(rscratch2, mdo,
1287                            md->byte_offset_of_slot(data, offset),
1288                            LogBytesPerWord);
1289   };
1290 
1291   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1292     Label next_test;
1293     // See if the receiver is receiver[n].
1294     __ ldr(rscratch1, slot_at(ReceiverTypeData::receiver_offset(i)));
1295     __ cmp(recv, rscratch1);
1296     __ br(Assembler::NE, next_test);
1297     __ addptr(slot_at(ReceiverTypeData::receiver_count_offset(i)),
1298               DataLayout::counter_increment);
1299     __ b(*update_done);
1300     __ bind(next_test);
1301   }
1302 
1303   // Didn't find receiver; find next empty slot and fill it in
1304   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1305     Label next_test;
1306     Address recv_addr(slot_at(ReceiverTypeData::receiver_offset(i)));
1307     __ ldr(rscratch1, recv_addr);
1308     __ cbnz(rscratch1, next_test);
1309     __ str(recv, recv_addr);
1310     __ mov(rscratch1, DataLayout::counter_increment);
1311     __ str(rscratch1, slot_at(ReceiverTypeData::receiver_count_offset(i)));
1312     __ b(*update_done);
1313     __ bind(next_test);
1314   }
1315 }
1316 
1317 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1318   // we always need a stub for the failure case.
1319   CodeStub* stub = op->stub();
1320   Register obj = op->object()->as_register();
1321   Register k_RInfo = op->tmp1()->as_register();
1322   Register klass_RInfo = op->tmp2()->as_register();
1323   Register dst = op->result_opr()->as_register();
1324   ciKlass* k = op->klass();
1325   Register Rtmp1 = noreg;
1326 
1327   // check if it needs to be profiled
1328   ciMethodData* md;
1329   ciProfileData* data;
1330 
1331   const bool should_profile = op->should_profile();
1332 
1333   if (should_profile) {
1334     ciMethod* method = op->profiled_method();
1335     assert(method != nullptr, "Should have method");
1336     int bci = op->profiled_bci();
1337     md = method->method_data_or_null();
1338     assert(md != nullptr, "Sanity");
1339     data = md->bci_to_data(bci);
1340     assert(data != nullptr,                "need data for type check");
1341     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1342   }
1343   Label* success_target = success;
1344   Label* failure_target = failure;
1345 
1346   if (obj == k_RInfo) {
1347     k_RInfo = dst;
1348   } else if (obj == klass_RInfo) {
1349     klass_RInfo = dst;
1350   }
1351   if (k->is_loaded() && !UseCompressedClassPointers) {
1352     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1353   } else {
1354     Rtmp1 = op->tmp3()->as_register();
1355     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1356   }
1357 
1358   assert_different_registers(obj, k_RInfo, klass_RInfo);
1359 
1360   if (op->need_null_check()) {
1361     if (should_profile) {
1362       Register mdo  = klass_RInfo;
1363       __ mov_metadata(mdo, md->constant_encoding());
1364       Label not_null;
1365       __ cbnz(obj, not_null);
1366       // Object is null; update MDO and exit
1367       Address data_addr
1368         = __ form_address(rscratch2, mdo,
1369                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1370                           0);
1371       __ ldrb(rscratch1, data_addr);
1372       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1373       __ strb(rscratch1, data_addr);
1374       __ b(*obj_is_null);
1375       __ bind(not_null);
1376 
1377       Label update_done;
1378       Register recv = k_RInfo;
1379       __ load_klass(recv, obj);
1380       type_profile_helper(mdo, md, data, recv, &update_done);
1381       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1382       __ addptr(counter_addr, DataLayout::counter_increment);
1383 
1384       __ bind(update_done);
1385     } else {
1386       __ cbz(obj, *obj_is_null);
1387     }
1388   }
1389 
1390   if (!k->is_loaded()) {
1391     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1392   } else {
1393     __ mov_metadata(k_RInfo, k->constant_encoding());
1394   }
1395   __ verify_oop(obj);
1396 
1397   if (op->fast_check()) {
1398     assert(!k->is_loaded() || !k->is_obj_array_klass(), "Use refined array for a direct pointer comparison");
1399     // get object class
1400     // not a safepoint as obj null check happens earlier
1401     __ load_klass(rscratch1, obj);
1402     __ cmp( rscratch1, k_RInfo);
1403 
1404     __ br(Assembler::NE, *failure_target);
1405     // successful cast, fall through to profile or jump
1406   } else {
1407     // get object class
1408     // not a safepoint as obj null check happens earlier
1409     __ load_klass(klass_RInfo, obj);
1410     if (k->is_loaded()) {
1411       // See if we get an immediate positive hit
1412       __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1413       __ cmp(k_RInfo, rscratch1);
1414       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1415         __ br(Assembler::NE, *failure_target);
1416         // successful cast, fall through to profile or jump
1417       } else {
1418         // See if we get an immediate positive hit
1419         __ br(Assembler::EQ, *success_target);
1420         // check for self
1421         if (k->is_loaded() && k->is_obj_array_klass()) {
1422           // For a direct pointer comparison, we need the refined array klass pointer
1423           ciKlass* k_refined = ciObjArrayKlass::make(k->as_obj_array_klass()->element_klass());
1424           __ mov_metadata(rscratch1, k_refined->constant_encoding());
1425           __ cmp(klass_RInfo, rscratch1);
1426         } else {
1427           __ cmp(klass_RInfo, k_RInfo);
1428         }
1429         __ br(Assembler::EQ, *success_target);
1430 
1431         __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1432         __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1433         __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1434         // result is a boolean
1435         __ cbzw(klass_RInfo, *failure_target);
1436         // successful cast, fall through to profile or jump
1437       }
1438     } else {
1439       // perform the fast part of the checking logic
1440       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1441       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1442       __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1443       __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1444       __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1445       // result is a boolean
1446       __ cbz(k_RInfo, *failure_target);
1447       // successful cast, fall through to profile or jump
1448     }
1449   }
1450   __ b(*success);
1451 }
1452 
1453 
1454 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1455   const bool should_profile = op->should_profile();
1456 
1457   LIR_Code code = op->code();
1458   if (code == lir_store_check) {
1459     Register value = op->object()->as_register();
1460     Register array = op->array()->as_register();
1461     Register k_RInfo = op->tmp1()->as_register();
1462     Register klass_RInfo = op->tmp2()->as_register();
1463     Register Rtmp1 = op->tmp3()->as_register();
1464 
1465     CodeStub* stub = op->stub();
1466 
1467     // check if it needs to be profiled
1468     ciMethodData* md;
1469     ciProfileData* data;
1470 
1471     if (should_profile) {
1472       ciMethod* method = op->profiled_method();
1473       assert(method != nullptr, "Should have method");
1474       int bci = op->profiled_bci();
1475       md = method->method_data_or_null();
1476       assert(md != nullptr, "Sanity");
1477       data = md->bci_to_data(bci);
1478       assert(data != nullptr,                "need data for type check");
1479       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1480     }
1481     Label done;
1482     Label* success_target = &done;
1483     Label* failure_target = stub->entry();
1484 
1485     if (should_profile) {
1486       Label not_null;
1487       Register mdo  = klass_RInfo;
1488       __ mov_metadata(mdo, md->constant_encoding());
1489       __ cbnz(value, not_null);
1490       // Object is null; update MDO and exit
1491       Address data_addr
1492         = __ form_address(rscratch2, mdo,
1493                           md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1494       __ ldrb(rscratch1, data_addr);
1495       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1496       __ strb(rscratch1, data_addr);
1497       __ b(done);
1498       __ bind(not_null);
1499 
1500       Label update_done;
1501       Register recv = k_RInfo;
1502       __ load_klass(recv, value);
1503       type_profile_helper(mdo, md, data, recv, &update_done);
1504       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1505       __ addptr(counter_addr, DataLayout::counter_increment);
1506       __ bind(update_done);
1507     } else {
1508       __ cbz(value, done);
1509     }
1510 
1511     add_debug_info_for_null_check_here(op->info_for_exception());
1512     __ load_klass(k_RInfo, array);
1513     __ load_klass(klass_RInfo, value);
1514 
1515     // get instance klass (it's already uncompressed)
1516     __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1517     // perform the fast part of the checking logic
1518     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1519     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1520     __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1521     __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1522     __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1523     // result is a boolean
1524     __ cbzw(k_RInfo, *failure_target);
1525     // fall through to the success case
1526 
1527     __ bind(done);
1528   } else if (code == lir_checkcast) {
1529     Register obj = op->object()->as_register();
1530     Register dst = op->result_opr()->as_register();
1531     Label success;
1532     emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1533     __ bind(success);
1534     if (dst != obj) {
1535       __ mov(dst, obj);
1536     }
1537   } else if (code == lir_instanceof) {
1538     Register obj = op->object()->as_register();
1539     Register dst = op->result_opr()->as_register();
1540     Label success, failure, done;
1541     emit_typecheck_helper(op, &success, &failure, &failure);
1542     __ bind(failure);
1543     __ mov(dst, zr);
1544     __ b(done);
1545     __ bind(success);
1546     __ mov(dst, 1);
1547     __ bind(done);
1548   } else {
1549     ShouldNotReachHere();
1550   }
1551 }
1552 
1553 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1554   // We are loading/storing from/to an array that *may* be a flat array (the
1555   // declared type is Object[], abstract[], interface[] or VT.ref[]).
1556   // If this array is a flat array, take the slow path.
1557   __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1558   if (!op->value()->is_illegal()) {
1559     // The array is not a flat array, but it might be null-free. If we are storing
1560     // a null into a null-free array, take the slow path (which will throw NPE).
1561     Label skip;
1562     __ cbnz(op->value()->as_register(), skip);
1563     __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1564     __ bind(skip);
1565   }
1566 }
1567 
1568 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1569   // We are storing into an array that *may* be null-free (the declared type is
1570   // Object[], abstract[], interface[] or VT.ref[]).
1571   Label test_mark_word;
1572   Register tmp = op->tmp()->as_register();
1573   __ ldr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
1574   __ tst(tmp, markWord::unlocked_value);
1575   __ br(Assembler::NE, test_mark_word);
1576   __ load_prototype_header(tmp, op->array()->as_register());
1577   __ bind(test_mark_word);
1578   __ tst(tmp, markWord::null_free_array_bit_in_place);
1579 }
1580 
1581 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1582   Label L_oops_equal;
1583   Label L_oops_not_equal;
1584   Label L_end;
1585 
1586   Register left  = op->left()->as_register();
1587   Register right = op->right()->as_register();
1588 
1589   __ cmp(left, right);
1590   __ br(Assembler::EQ, L_oops_equal);
1591 
1592   // (1) Null check -- if one of the operands is null, the other must not be null (because
1593   //     the two references are not equal), so they are not substitutable,
1594   //     FIXME: do null check only if the operand is nullable
1595   {
1596     __ cbz(left, L_oops_not_equal);
1597     __ cbz(right, L_oops_not_equal);
1598   }
1599 
1600   ciKlass* left_klass = op->left_klass();
1601   ciKlass* right_klass = op->right_klass();
1602 
1603   // (2) Inline type check -- if either of the operands is not a inline type,
1604   //     they are not substitutable. We do this only if we are not sure that the
1605   //     operands are inline type
1606   if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node.
1607       !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
1608     Register tmp1  = op->tmp1()->as_register();
1609     __ mov(tmp1, markWord::inline_type_pattern);
1610     __ ldr(rscratch1, Address(left, oopDesc::mark_offset_in_bytes()));
1611     __ andr(tmp1, tmp1, rscratch1);
1612     __ ldr(rscratch1, Address(right, oopDesc::mark_offset_in_bytes()));
1613     __ andr(tmp1, tmp1, rscratch1);
1614     __ cmp(tmp1, (u1)markWord::inline_type_pattern);
1615     __ br(Assembler::NE, L_oops_not_equal);
1616   }
1617 
1618   // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
1619   if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) {
1620     // No need to load klass -- the operands are statically known to be the same inline klass.
1621     __ b(*op->stub()->entry());
1622   } else {
1623     Register left_klass_op = op->left_klass_op()->as_register();
1624     Register right_klass_op = op->right_klass_op()->as_register();
1625 
1626     if (UseCompressedClassPointers) {
1627       __ ldrw(left_klass_op,  Address(left,  oopDesc::klass_offset_in_bytes()));
1628       __ ldrw(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1629       __ cmpw(left_klass_op, right_klass_op);
1630     } else {
1631       __ ldr(left_klass_op,  Address(left,  oopDesc::klass_offset_in_bytes()));
1632       __ ldr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1633       __ cmp(left_klass_op, right_klass_op);
1634     }
1635 
1636     __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check
1637     // fall through to L_oops_not_equal
1638   }
1639 
1640   __ bind(L_oops_not_equal);
1641   move(op->not_equal_result(), op->result_opr());
1642   __ b(L_end);
1643 
1644   __ bind(L_oops_equal);
1645   move(op->equal_result(), op->result_opr());
1646   __ b(L_end);
1647 
1648   // We've returned from the stub. R0 contains 0x0 IFF the two
1649   // operands are not substitutable. (Don't compare against 0x1 in case the
1650   // C compiler is naughty)
1651   __ bind(*op->stub()->continuation());
1652   __ cbz(r0, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1653   move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
1654   // fall-through
1655   __ bind(L_end);
1656 }
1657 
1658 
1659 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1660   __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1661   __ cset(rscratch1, Assembler::NE);
1662   __ membar(__ AnyAny);
1663 }
1664 
1665 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1666   __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1667   __ cset(rscratch1, Assembler::NE);
1668   __ membar(__ AnyAny);
1669 }
1670 
1671 
1672 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1673   Register addr;
1674   if (op->addr()->is_register()) {
1675     addr = as_reg(op->addr());
1676   } else {
1677     assert(op->addr()->is_address(), "what else?");
1678     LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1679     assert(addr_ptr->disp() == 0, "need 0 disp");
1680     assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1681     addr = as_reg(addr_ptr->base());
1682   }
1683   Register newval = as_reg(op->new_value());
1684   Register cmpval = as_reg(op->cmp_value());
1685 
1686   if (op->code() == lir_cas_obj) {
1687     if (UseCompressedOops) {
1688       Register t1 = op->tmp1()->as_register();
1689       assert(op->tmp1()->is_valid(), "must be");
1690       __ encode_heap_oop(t1, cmpval);
1691       cmpval = t1;
1692       __ encode_heap_oop(rscratch2, newval);
1693       newval = rscratch2;
1694       casw(addr, newval, cmpval);
1695     } else {
1696       casl(addr, newval, cmpval);
1697     }
1698   } else if (op->code() == lir_cas_int) {
1699     casw(addr, newval, cmpval);
1700   } else {
1701     casl(addr, newval, cmpval);
1702   }
1703 }
1704 
1705 
1706 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1707                           LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1708   assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1709 
1710   Assembler::Condition acond, ncond;
1711   switch (condition) {
1712   case lir_cond_equal:        acond = Assembler::EQ; ncond = Assembler::NE; break;
1713   case lir_cond_notEqual:     acond = Assembler::NE; ncond = Assembler::EQ; break;
1714   case lir_cond_less:         acond = Assembler::LT; ncond = Assembler::GE; break;
1715   case lir_cond_lessEqual:    acond = Assembler::LE; ncond = Assembler::GT; break;
1716   case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1717   case lir_cond_greater:      acond = Assembler::GT; ncond = Assembler::LE; break;
1718   case lir_cond_belowEqual:
1719   case lir_cond_aboveEqual:
1720   default:                    ShouldNotReachHere();
1721     acond = Assembler::EQ; ncond = Assembler::NE;  // unreachable
1722   }
1723 
1724   assert(result->is_single_cpu() || result->is_double_cpu(),
1725          "expect single register for result");
1726   if (opr1->is_constant() && opr2->is_constant()
1727       && opr1->type() == T_INT && opr2->type() == T_INT) {
1728     jint val1 = opr1->as_jint();
1729     jint val2 = opr2->as_jint();
1730     if (val1 == 0 && val2 == 1) {
1731       __ cset(result->as_register(), ncond);
1732       return;
1733     } else if (val1 == 1 && val2 == 0) {
1734       __ cset(result->as_register(), acond);
1735       return;
1736     }
1737   }
1738 
1739   if (opr1->is_constant() && opr2->is_constant()
1740       && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1741     jlong val1 = opr1->as_jlong();
1742     jlong val2 = opr2->as_jlong();
1743     if (val1 == 0 && val2 == 1) {
1744       __ cset(result->as_register_lo(), ncond);
1745       return;
1746     } else if (val1 == 1 && val2 == 0) {
1747       __ cset(result->as_register_lo(), acond);
1748       return;
1749     }
1750   }
1751 
1752   if (opr1->is_stack()) {
1753     stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1754     opr1 = FrameMap::rscratch1_opr;
1755   } else if (opr1->is_constant()) {
1756     LIR_Opr tmp
1757       = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1758     const2reg(opr1, tmp, lir_patch_none, nullptr);
1759     opr1 = tmp;
1760   }
1761 
1762   if (opr2->is_stack()) {
1763     stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1764     opr2 = FrameMap::rscratch2_opr;
1765   } else if (opr2->is_constant()) {
1766     LIR_Opr tmp
1767       = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1768     const2reg(opr2, tmp, lir_patch_none, nullptr);
1769     opr2 = tmp;
1770   }
1771 
1772   if (result->type() == T_LONG)
1773     __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1774   else
1775     __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1776 }
1777 
1778 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1779   assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1780 
1781   if (left->is_single_cpu()) {
1782     Register lreg = left->as_register();
1783     Register dreg = as_reg(dest);
1784 
1785     if (right->is_single_cpu()) {
1786       // cpu register - cpu register
1787 
1788       assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1789              "should be");
1790       Register rreg = right->as_register();
1791       switch (code) {
1792       case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1793       case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1794       case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1795       default:      ShouldNotReachHere();
1796       }
1797 
1798     } else if (right->is_double_cpu()) {
1799       Register rreg = right->as_register_lo();
1800       // single_cpu + double_cpu: can happen with obj+long
1801       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1802       switch (code) {
1803       case lir_add: __ add(dreg, lreg, rreg); break;
1804       case lir_sub: __ sub(dreg, lreg, rreg); break;
1805       default: ShouldNotReachHere();
1806       }
1807     } else if (right->is_constant()) {
1808       // cpu register - constant
1809       jlong c;
1810 
1811       // FIXME.  This is fugly: we really need to factor all this logic.
1812       switch(right->type()) {
1813       case T_LONG:
1814         c = right->as_constant_ptr()->as_jlong();
1815         break;
1816       case T_INT:
1817       case T_ADDRESS:
1818         c = right->as_constant_ptr()->as_jint();
1819         break;
1820       default:
1821         ShouldNotReachHere();
1822         c = 0;  // unreachable
1823         break;
1824       }
1825 
1826       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1827       if (c == 0 && dreg == lreg) {
1828         COMMENT("effective nop elided");
1829         return;
1830       }
1831       switch(left->type()) {
1832       case T_INT:
1833         switch (code) {
1834         case lir_add: __ addw(dreg, lreg, c); break;
1835         case lir_sub: __ subw(dreg, lreg, c); break;
1836         default: ShouldNotReachHere();
1837         }
1838         break;
1839       case T_OBJECT:
1840       case T_ADDRESS:
1841         switch (code) {
1842         case lir_add: __ add(dreg, lreg, c); break;
1843         case lir_sub: __ sub(dreg, lreg, c); break;
1844         default: ShouldNotReachHere();
1845         }
1846         break;
1847       default:
1848         ShouldNotReachHere();
1849       }
1850     } else {
1851       ShouldNotReachHere();
1852     }
1853 
1854   } else if (left->is_double_cpu()) {
1855     Register lreg_lo = left->as_register_lo();
1856 
1857     if (right->is_double_cpu()) {
1858       // cpu register - cpu register
1859       Register rreg_lo = right->as_register_lo();
1860       switch (code) {
1861       case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1862       case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1863       case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1864       case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1865       case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1866       default:
1867         ShouldNotReachHere();
1868       }
1869 
1870     } else if (right->is_constant()) {
1871       jlong c = right->as_constant_ptr()->as_jlong();
1872       Register dreg = as_reg(dest);
1873       switch (code) {
1874         case lir_add:
1875         case lir_sub:
1876           if (c == 0 && dreg == lreg_lo) {
1877             COMMENT("effective nop elided");
1878             return;
1879           }
1880           code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1881           break;
1882         case lir_div:
1883           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1884           if (c == 1) {
1885             // move lreg_lo to dreg if divisor is 1
1886             __ mov(dreg, lreg_lo);
1887           } else {
1888             unsigned int shift = log2i_exact(c);
1889             // use rscratch1 as intermediate result register
1890             __ asr(rscratch1, lreg_lo, 63);
1891             __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1892             __ asr(dreg, rscratch1, shift);
1893           }
1894           break;
1895         case lir_rem:
1896           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1897           if (c == 1) {
1898             // move 0 to dreg if divisor is 1
1899             __ mov(dreg, zr);
1900           } else {
1901             // use rscratch1 as intermediate result register
1902             __ negs(rscratch1, lreg_lo);
1903             __ andr(dreg, lreg_lo, c - 1);
1904             __ andr(rscratch1, rscratch1, c - 1);
1905             __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1906           }
1907           break;
1908         default:
1909           ShouldNotReachHere();
1910       }
1911     } else {
1912       ShouldNotReachHere();
1913     }
1914   } else if (left->is_single_fpu()) {
1915     assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1916     switch (code) {
1917     case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1918     case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1919     case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1920     case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1921     default:
1922       ShouldNotReachHere();
1923     }
1924   } else if (left->is_double_fpu()) {
1925     if (right->is_double_fpu()) {
1926       // fpu register - fpu register
1927       switch (code) {
1928       case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1929       case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1930       case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1931       case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1932       default:
1933         ShouldNotReachHere();
1934       }
1935     } else {
1936       if (right->is_constant()) {
1937         ShouldNotReachHere();
1938       }
1939       ShouldNotReachHere();
1940     }
1941   } else if (left->is_single_stack() || left->is_address()) {
1942     assert(left == dest, "left and dest must be equal");
1943     ShouldNotReachHere();
1944   } else {
1945     ShouldNotReachHere();
1946   }
1947 }
1948 
1949 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1950   switch(code) {
1951   case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1952   case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1953   case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1954   case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1955   default      : ShouldNotReachHere();
1956   }
1957 }
1958 
1959 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1960 
1961   assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1962   Register Rleft = left->is_single_cpu() ? left->as_register() :
1963                                            left->as_register_lo();
1964    if (dst->is_single_cpu()) {
1965      Register Rdst = dst->as_register();
1966      if (right->is_constant()) {
1967        switch (code) {
1968          case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1969          case lir_logic_or:  __ orrw (Rdst, Rleft, right->as_jint()); break;
1970          case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1971          default: ShouldNotReachHere(); break;
1972        }
1973      } else {
1974        Register Rright = right->is_single_cpu() ? right->as_register() :
1975                                                   right->as_register_lo();
1976        switch (code) {
1977          case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1978          case lir_logic_or:  __ orrw (Rdst, Rleft, Rright); break;
1979          case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1980          default: ShouldNotReachHere(); break;
1981        }
1982      }
1983    } else {
1984      Register Rdst = dst->as_register_lo();
1985      if (right->is_constant()) {
1986        switch (code) {
1987          case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1988          case lir_logic_or:  __ orr (Rdst, Rleft, right->as_jlong()); break;
1989          case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1990          default: ShouldNotReachHere(); break;
1991        }
1992      } else {
1993        Register Rright = right->is_single_cpu() ? right->as_register() :
1994                                                   right->as_register_lo();
1995        switch (code) {
1996          case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1997          case lir_logic_or:  __ orr (Rdst, Rleft, Rright); break;
1998          case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1999          default: ShouldNotReachHere(); break;
2000        }
2001      }
2002    }
2003 }
2004 
2005 
2006 
2007 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
2008 
2009   // opcode check
2010   assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
2011   bool is_irem = (code == lir_irem);
2012 
2013   // operand check
2014   assert(left->is_single_cpu(),   "left must be register");
2015   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
2016   assert(result->is_single_cpu(), "result must be register");
2017   Register lreg = left->as_register();
2018   Register dreg = result->as_register();
2019 
2020   // power-of-2 constant check and codegen
2021   if (right->is_constant()) {
2022     int c = right->as_constant_ptr()->as_jint();
2023     assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
2024     if (is_irem) {
2025       if (c == 1) {
2026         // move 0 to dreg if divisor is 1
2027         __ movw(dreg, zr);
2028       } else {
2029         // use rscratch1 as intermediate result register
2030         __ negsw(rscratch1, lreg);
2031         __ andw(dreg, lreg, c - 1);
2032         __ andw(rscratch1, rscratch1, c - 1);
2033         __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
2034       }
2035     } else {
2036       if (c == 1) {
2037         // move lreg to dreg if divisor is 1
2038         __ movw(dreg, lreg);
2039       } else {
2040         unsigned int shift = exact_log2(c);
2041         // use rscratch1 as intermediate result register
2042         __ asrw(rscratch1, lreg, 31);
2043         __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
2044         __ asrw(dreg, rscratch1, shift);
2045       }
2046     }
2047   } else {
2048     Register rreg = right->as_register();
2049     __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
2050   }
2051 }
2052 
2053 
2054 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2055   if (opr1->is_constant() && opr2->is_single_cpu()) {
2056     // tableswitch
2057     Register reg = as_reg(opr2);
2058     struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
2059     __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
2060   } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
2061     Register reg1 = as_reg(opr1);
2062     if (opr2->is_single_cpu()) {
2063       // cpu register - cpu register
2064       Register reg2 = opr2->as_register();
2065       if (is_reference_type(opr1->type())) {
2066         __ cmpoop(reg1, reg2);
2067       } else {
2068         assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2069         __ cmpw(reg1, reg2);
2070       }
2071       return;
2072     }
2073     if (opr2->is_double_cpu()) {
2074       // cpu register - cpu register
2075       Register reg2 = opr2->as_register_lo();
2076       __ cmp(reg1, reg2);
2077       return;
2078     }
2079 
2080     if (opr2->is_constant()) {
2081       bool is_32bit = false; // width of register operand
2082       jlong imm;
2083 
2084       switch(opr2->type()) {
2085       case T_INT:
2086         imm = opr2->as_constant_ptr()->as_jint();
2087         is_32bit = true;
2088         break;
2089       case T_LONG:
2090         imm = opr2->as_constant_ptr()->as_jlong();
2091         break;
2092       case T_ADDRESS:
2093         imm = opr2->as_constant_ptr()->as_jint();
2094         break;
2095       case T_METADATA:
2096         imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
2097         break;
2098       case T_OBJECT:
2099       case T_ARRAY:
2100         jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
2101         __ cmpoop(reg1, rscratch1);
2102         return;
2103       default:
2104         ShouldNotReachHere();
2105         imm = 0;  // unreachable
2106         break;
2107       }
2108 
2109       if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
2110         if (is_32bit)
2111           __ cmpw(reg1, imm);
2112         else
2113           __ subs(zr, reg1, imm);
2114         return;
2115       } else {
2116         __ mov(rscratch1, imm);
2117         if (is_32bit)
2118           __ cmpw(reg1, rscratch1);
2119         else
2120           __ cmp(reg1, rscratch1);
2121         return;
2122       }
2123     } else
2124       ShouldNotReachHere();
2125   } else if (opr1->is_single_fpu()) {
2126     FloatRegister reg1 = opr1->as_float_reg();
2127     assert(opr2->is_single_fpu(), "expect single float register");
2128     FloatRegister reg2 = opr2->as_float_reg();
2129     __ fcmps(reg1, reg2);
2130   } else if (opr1->is_double_fpu()) {
2131     FloatRegister reg1 = opr1->as_double_reg();
2132     assert(opr2->is_double_fpu(), "expect double float register");
2133     FloatRegister reg2 = opr2->as_double_reg();
2134     __ fcmpd(reg1, reg2);
2135   } else {
2136     ShouldNotReachHere();
2137   }
2138 }
2139 
2140 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2141   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2142     bool is_unordered_less = (code == lir_ucmp_fd2i);
2143     if (left->is_single_fpu()) {
2144       __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2145     } else if (left->is_double_fpu()) {
2146       __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2147     } else {
2148       ShouldNotReachHere();
2149     }
2150   } else if (code == lir_cmp_l2i) {
2151     Label done;
2152     __ cmp(left->as_register_lo(), right->as_register_lo());
2153     __ mov(dst->as_register(), (uint64_t)-1L);
2154     __ br(Assembler::LT, done);
2155     __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2156     __ bind(done);
2157   } else {
2158     ShouldNotReachHere();
2159   }
2160 }
2161 
2162 
2163 void LIR_Assembler::align_call(LIR_Code code) {  }
2164 
2165 
2166 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2167   address call = __ trampoline_call(Address(op->addr(), rtype));
2168   if (call == nullptr) {
2169     bailout("trampoline stub overflow");
2170     return;
2171   }
2172   add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2173   __ post_call_nop();
2174 }
2175 
2176 
2177 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2178   address call = __ ic_call(op->addr());
2179   if (call == nullptr) {
2180     bailout("trampoline stub overflow");
2181     return;
2182   }
2183   add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2184   __ post_call_nop();
2185 }
2186 
2187 void LIR_Assembler::emit_static_call_stub() {
2188   address call_pc = __ pc();
2189   address stub = __ start_a_stub(call_stub_size());
2190   if (stub == nullptr) {
2191     bailout("static call stub overflow");
2192     return;
2193   }
2194 
2195   int start = __ offset();
2196 
2197   __ relocate(static_stub_Relocation::spec(call_pc));
2198   __ emit_static_call_stub();
2199 
2200   assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2201         <= call_stub_size(), "stub too big");
2202   __ end_a_stub();
2203 }
2204 
2205 
2206 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2207   assert(exceptionOop->as_register() == r0, "must match");
2208   assert(exceptionPC->as_register() == r3, "must match");
2209 
2210   // exception object is not added to oop map by LinearScan
2211   // (LinearScan assumes that no oops are in fixed registers)
2212   info->add_register_oop(exceptionOop);
2213   StubId unwind_id;
2214 
2215   // get current pc information
2216   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2217   if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2218     // As no instructions have been generated yet for this LIR node it's
2219     // possible that an oop map already exists for the current offset.
2220     // In that case insert an dummy NOP here to ensure all oop map PCs
2221     // are unique. See JDK-8237483.
2222     __ nop();
2223   }
2224   int pc_for_athrow_offset = __ offset();
2225   InternalAddress pc_for_athrow(__ pc());
2226   __ adr(exceptionPC->as_register(), pc_for_athrow);
2227   add_call_info(pc_for_athrow_offset, info); // for exception handler
2228 
2229   __ verify_not_null_oop(r0);
2230   // search an exception handler (r0: exception oop, r3: throwing pc)
2231   if (compilation()->has_fpu_code()) {
2232     unwind_id = StubId::c1_handle_exception_id;
2233   } else {
2234     unwind_id = StubId::c1_handle_exception_nofpu_id;
2235   }
2236   __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2237 
2238   // FIXME: enough room for two byte trap   ????
2239   __ nop();
2240 }
2241 
2242 
2243 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2244   assert(exceptionOop->as_register() == r0, "must match");
2245 
2246   __ b(_unwind_handler_entry);
2247 }
2248 
2249 
2250 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2251   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2252   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2253 
2254   switch (left->type()) {
2255     case T_INT: {
2256       switch (code) {
2257       case lir_shl:  __ lslvw (dreg, lreg, count->as_register()); break;
2258       case lir_shr:  __ asrvw (dreg, lreg, count->as_register()); break;
2259       case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2260       default:
2261         ShouldNotReachHere();
2262         break;
2263       }
2264       break;
2265     case T_LONG:
2266     case T_ADDRESS:
2267     case T_OBJECT:
2268       switch (code) {
2269       case lir_shl:  __ lslv (dreg, lreg, count->as_register()); break;
2270       case lir_shr:  __ asrv (dreg, lreg, count->as_register()); break;
2271       case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2272       default:
2273         ShouldNotReachHere();
2274         break;
2275       }
2276       break;
2277     default:
2278       ShouldNotReachHere();
2279       break;
2280     }
2281   }
2282 }
2283 
2284 
2285 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2286   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2287   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2288 
2289   switch (left->type()) {
2290     case T_INT: {
2291       switch (code) {
2292       case lir_shl:  __ lslw (dreg, lreg, count); break;
2293       case lir_shr:  __ asrw (dreg, lreg, count); break;
2294       case lir_ushr: __ lsrw (dreg, lreg, count); break;
2295       default:
2296         ShouldNotReachHere();
2297         break;
2298       }
2299       break;
2300     case T_LONG:
2301     case T_ADDRESS:
2302     case T_OBJECT:
2303       switch (code) {
2304       case lir_shl:  __ lsl (dreg, lreg, count); break;
2305       case lir_shr:  __ asr (dreg, lreg, count); break;
2306       case lir_ushr: __ lsr (dreg, lreg, count); break;
2307       default:
2308         ShouldNotReachHere();
2309         break;
2310       }
2311       break;
2312     default:
2313       ShouldNotReachHere();
2314       break;
2315     }
2316   }
2317 }
2318 
2319 
2320 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2321   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2322   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2323   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2324   __ str (r, Address(sp, offset_from_rsp_in_bytes));
2325 }
2326 
2327 
2328 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
2329   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2330   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2331   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2332   __ mov (rscratch1, c);
2333   __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2334 }
2335 
2336 
2337 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
2338   ShouldNotReachHere();
2339   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2340   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2341   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2342   __ lea(rscratch1, __ constant_oop_address(o));
2343   __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2344 }
2345 
2346 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
2347   if (null_check) {
2348     __ cbz(obj, *slow_path->entry());
2349   }
2350   if (is_dest) {
2351     __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
2352     // TODO 8350865 Flat no longer implies null-free, so we need to check for flat dest. Can we do better here?
2353     __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2354   } else {
2355     __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2356   }
2357 }
2358 
2359 // This code replaces a call to arraycopy; no exception may
2360 // be thrown in this code, they must be thrown in the System.arraycopy
2361 // activation frame; we could save some checks if this would not be the case
2362 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2363   ciArrayKlass* default_type = op->expected_type();
2364   Register src = op->src()->as_register();
2365   Register dst = op->dst()->as_register();
2366   Register src_pos = op->src_pos()->as_register();
2367   Register dst_pos = op->dst_pos()->as_register();
2368   Register length  = op->length()->as_register();
2369   Register tmp = op->tmp()->as_register();
2370 
2371   CodeStub* stub = op->stub();
2372   int flags = op->flags();
2373   BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2374   if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2375 
2376   if (flags & LIR_OpArrayCopy::always_slow_path) {
2377     __ b(*stub->entry());
2378     __ bind(*stub->continuation());
2379     return;
2380   }
2381 
2382   // if we don't know anything, just go through the generic arraycopy
2383   if (default_type == nullptr // || basic_type == T_OBJECT
2384       ) {
2385     Label done;
2386     assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2387 
2388     // Save the arguments in case the generic arraycopy fails and we
2389     // have to fall back to the JNI stub
2390     __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2391     __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2392     __ str(src,              Address(sp, 4*BytesPerWord));
2393 
2394     address copyfunc_addr = StubRoutines::generic_arraycopy();
2395     assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2396 
2397     // The arguments are in java calling convention so we shift them
2398     // to C convention
2399     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2400     __ mov(c_rarg0, j_rarg0);
2401     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2402     __ mov(c_rarg1, j_rarg1);
2403     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2404     __ mov(c_rarg2, j_rarg2);
2405     assert_different_registers(c_rarg3, j_rarg4);
2406     __ mov(c_rarg3, j_rarg3);
2407     __ mov(c_rarg4, j_rarg4);
2408 #ifndef PRODUCT
2409     if (PrintC1Statistics) {
2410       __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2411     }
2412 #endif
2413     __ far_call(RuntimeAddress(copyfunc_addr));
2414 
2415     __ cbz(r0, *stub->continuation());
2416 
2417     // Reload values from the stack so they are where the stub
2418     // expects them.
2419     __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2420     __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2421     __ ldr(src,              Address(sp, 4*BytesPerWord));
2422 
2423     // r0 is -1^K where K == partial copied count
2424     __ eonw(rscratch1, r0, zr);
2425     // adjust length down and src/end pos up by partial copied count
2426     __ subw(length, length, rscratch1);
2427     __ addw(src_pos, src_pos, rscratch1);
2428     __ addw(dst_pos, dst_pos, rscratch1);
2429     __ b(*stub->entry());
2430 
2431     __ bind(*stub->continuation());
2432     return;
2433   }
2434 
2435   // Handle inline type arrays
2436   if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
2437     arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
2438   }
2439   if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
2440     arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
2441   }
2442 
2443   assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2444 
2445   int elem_size = type2aelembytes(basic_type);
2446   int scale = exact_log2(elem_size);
2447 
2448   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2449   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2450 
2451   // test for null
2452   if (flags & LIR_OpArrayCopy::src_null_check) {
2453     __ cbz(src, *stub->entry());
2454   }
2455   if (flags & LIR_OpArrayCopy::dst_null_check) {
2456     __ cbz(dst, *stub->entry());
2457   }
2458 
2459   // If the compiler was not able to prove that exact type of the source or the destination
2460   // of the arraycopy is an array type, check at runtime if the source or the destination is
2461   // an instance type.
2462   if (flags & LIR_OpArrayCopy::type_check) {
2463     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2464       __ load_klass(tmp, dst);
2465       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2466       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2467       __ br(Assembler::GE, *stub->entry());
2468     }
2469 
2470     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2471       __ load_klass(tmp, src);
2472       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2473       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2474       __ br(Assembler::GE, *stub->entry());
2475     }
2476   }
2477 
2478   // check if negative
2479   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2480     __ cmpw(src_pos, 0);
2481     __ br(Assembler::LT, *stub->entry());
2482   }
2483   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2484     __ cmpw(dst_pos, 0);
2485     __ br(Assembler::LT, *stub->entry());
2486   }
2487 
2488   if (flags & LIR_OpArrayCopy::length_positive_check) {
2489     __ cmpw(length, 0);
2490     __ br(Assembler::LT, *stub->entry());
2491   }
2492 
2493   if (flags & LIR_OpArrayCopy::src_range_check) {
2494     __ addw(tmp, src_pos, length);
2495     __ ldrw(rscratch1, src_length_addr);
2496     __ cmpw(tmp, rscratch1);
2497     __ br(Assembler::HI, *stub->entry());
2498   }
2499   if (flags & LIR_OpArrayCopy::dst_range_check) {
2500     __ addw(tmp, dst_pos, length);
2501     __ ldrw(rscratch1, dst_length_addr);
2502     __ cmpw(tmp, rscratch1);
2503     __ br(Assembler::HI, *stub->entry());
2504   }
2505 
2506   if (flags & LIR_OpArrayCopy::type_check) {
2507     // We don't know the array types are compatible
2508     if (basic_type != T_OBJECT) {
2509       // Simple test for basic type arrays
2510       __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2511       __ br(Assembler::NE, *stub->entry());
2512     } else {
2513       // For object arrays, if src is a sub class of dst then we can
2514       // safely do the copy.
2515       Label cont, slow;
2516 
2517 #define PUSH(r1, r2)                                    \
2518       stp(r1, r2, __ pre(sp, -2 * wordSize));
2519 
2520 #define POP(r1, r2)                                     \
2521       ldp(r1, r2, __ post(sp, 2 * wordSize));
2522 
2523       __ PUSH(src, dst);
2524 
2525       __ load_klass(src, src);
2526       __ load_klass(dst, dst);
2527 
2528       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2529 
2530       __ PUSH(src, dst);
2531       __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2532       __ POP(src, dst);
2533 
2534       __ cbnz(src, cont);
2535 
2536       __ bind(slow);
2537       __ POP(src, dst);
2538 
2539       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2540       if (copyfunc_addr != nullptr) { // use stub if available
2541         // src is not a sub class of dst so we have to do a
2542         // per-element check.
2543 
2544         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2545         if ((flags & mask) != mask) {
2546           // Check that at least both of them object arrays.
2547           assert(flags & mask, "one of the two should be known to be an object array");
2548 
2549           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2550             __ load_klass(tmp, src);
2551           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2552             __ load_klass(tmp, dst);
2553           }
2554           int lh_offset = in_bytes(Klass::layout_helper_offset());
2555           Address klass_lh_addr(tmp, lh_offset);
2556           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2557           __ ldrw(rscratch1, klass_lh_addr);
2558           __ mov(rscratch2, objArray_lh);
2559           __ eorw(rscratch1, rscratch1, rscratch2);
2560           __ cbnzw(rscratch1, *stub->entry());
2561         }
2562 
2563        // Spill because stubs can use any register they like and it's
2564        // easier to restore just those that we care about.
2565         __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2566         __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2567         __ str(src,              Address(sp, 4*BytesPerWord));
2568 
2569         __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2570         __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2571         assert_different_registers(c_rarg0, dst, dst_pos, length);
2572         __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2573         __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2574         assert_different_registers(c_rarg1, dst, length);
2575         __ uxtw(c_rarg2, length);
2576         assert_different_registers(c_rarg2, dst);
2577 
2578         __ load_klass(c_rarg4, dst);
2579         __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2580         __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2581         __ far_call(RuntimeAddress(copyfunc_addr));
2582 
2583 #ifndef PRODUCT
2584         if (PrintC1Statistics) {
2585           Label failed;
2586           __ cbnz(r0, failed);
2587           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2588           __ bind(failed);
2589         }
2590 #endif
2591 
2592         __ cbz(r0, *stub->continuation());
2593 
2594 #ifndef PRODUCT
2595         if (PrintC1Statistics) {
2596           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2597         }
2598 #endif
2599         assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2600 
2601         // Restore previously spilled arguments
2602         __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2603         __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2604         __ ldr(src,              Address(sp, 4*BytesPerWord));
2605 
2606         // return value is -1^K where K is partial copied count
2607         __ eonw(rscratch1, r0, zr);
2608         // adjust length down and src/end pos up by partial copied count
2609         __ subw(length, length, rscratch1);
2610         __ addw(src_pos, src_pos, rscratch1);
2611         __ addw(dst_pos, dst_pos, rscratch1);
2612       }
2613 
2614       __ b(*stub->entry());
2615 
2616       __ bind(cont);
2617       __ POP(src, dst);
2618     }
2619   }
2620 
2621 #ifdef ASSERT
2622   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2623     // Sanity check the known type with the incoming class.  For the
2624     // primitive case the types must match exactly with src.klass and
2625     // dst.klass each exactly matching the default type.  For the
2626     // object array case, if no type check is needed then either the
2627     // dst type is exactly the expected type and the src type is a
2628     // subtype which we can't check or src is the same array as dst
2629     // but not necessarily exactly of type default_type.
2630     Label known_ok, halt;
2631     __ mov_metadata(tmp, default_type->constant_encoding());
2632 
2633     if (basic_type != T_OBJECT) {
2634       __ cmp_klass(dst, tmp, rscratch1);
2635       __ br(Assembler::NE, halt);
2636       __ cmp_klass(src, tmp, rscratch1);
2637       __ br(Assembler::EQ, known_ok);
2638     } else {
2639       __ cmp_klass(dst, tmp, rscratch1);
2640       __ br(Assembler::EQ, known_ok);
2641       __ cmp(src, dst);
2642       __ br(Assembler::EQ, known_ok);
2643     }
2644     __ bind(halt);
2645     __ stop("incorrect type information in arraycopy");
2646     __ bind(known_ok);
2647   }
2648 #endif
2649 
2650 #ifndef PRODUCT
2651   if (PrintC1Statistics) {
2652     __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2653   }
2654 #endif
2655 
2656   __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2657   __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2658   assert_different_registers(c_rarg0, dst, dst_pos, length);
2659   __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2660   __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2661   assert_different_registers(c_rarg1, dst, length);
2662   __ uxtw(c_rarg2, length);
2663   assert_different_registers(c_rarg2, dst);
2664 
2665   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2666   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2667   const char *name;
2668   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2669 
2670  CodeBlob *cb = CodeCache::find_blob(entry);
2671  if (cb) {
2672    __ far_call(RuntimeAddress(entry));
2673  } else {
2674    __ call_VM_leaf(entry, 3);
2675  }
2676 
2677   if (stub != nullptr) {
2678     __ bind(*stub->continuation());
2679   }
2680 }
2681 
2682 
2683 
2684 
2685 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2686   Register obj = op->obj_opr()->as_register();  // may not be an oop
2687   Register hdr = op->hdr_opr()->as_register();
2688   Register lock = op->lock_opr()->as_register();
2689   Register temp = op->scratch_opr()->as_register();
2690   if (op->code() == lir_lock) {
2691     // add debug info for NullPointerException only if one is possible
2692     int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2693     if (op->info() != nullptr) {
2694       add_debug_info_for_null_check(null_check_offset, op->info());
2695     }
2696     // done
2697   } else if (op->code() == lir_unlock) {
2698     __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2699   } else {
2700     Unimplemented();
2701   }
2702   __ bind(*op->stub()->continuation());
2703 }
2704 
2705 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2706   Register obj = op->obj()->as_pointer_register();
2707   Register result = op->result_opr()->as_pointer_register();
2708 
2709   CodeEmitInfo* info = op->info();
2710   if (info != nullptr) {
2711     add_debug_info_for_null_check_here(info);
2712   }
2713 
2714   __ load_klass(result, obj);
2715 }
2716 
2717 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2718   ciMethod* method = op->profiled_method();
2719   int bci          = op->profiled_bci();
2720   ciMethod* callee = op->profiled_callee();
2721 
2722   // Update counter for all call types
2723   ciMethodData* md = method->method_data_or_null();
2724   assert(md != nullptr, "Sanity");
2725   ciProfileData* data = md->bci_to_data(bci);
2726   assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2727   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2728   Register mdo  = op->mdo()->as_register();
2729   __ mov_metadata(mdo, md->constant_encoding());
2730   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2731   // Perform additional virtual call profiling for invokevirtual and
2732   // invokeinterface bytecodes
2733   if (op->should_profile_receiver_type()) {
2734     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2735     Register recv = op->recv()->as_register();
2736     assert_different_registers(mdo, recv);
2737     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2738     ciKlass* known_klass = op->known_holder();
2739     if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2740       // We know the type that will be seen at this call site; we can
2741       // statically update the MethodData* rather than needing to do
2742       // dynamic tests on the receiver type
2743 
2744       // NOTE: we should probably put a lock around this search to
2745       // avoid collisions by concurrent compilations
2746       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2747       uint i;
2748       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2749         ciKlass* receiver = vc_data->receiver(i);
2750         if (known_klass->equals(receiver)) {
2751           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2752           __ addptr(data_addr, DataLayout::counter_increment);
2753           return;
2754         }
2755       }
2756 
2757       // Receiver type not found in profile data; select an empty slot
2758 
2759       // Note that this is less efficient than it should be because it
2760       // always does a write to the receiver part of the
2761       // VirtualCallData rather than just the first time
2762       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2763         ciKlass* receiver = vc_data->receiver(i);
2764         if (receiver == nullptr) {
2765           __ mov_metadata(rscratch1, known_klass->constant_encoding());
2766           Address recv_addr =
2767             __ form_address(rscratch2, mdo,
2768                             md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)),
2769                             LogBytesPerWord);
2770           __ str(rscratch1, recv_addr);
2771           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2772           __ addptr(data_addr, DataLayout::counter_increment);
2773           return;
2774         }
2775       }
2776     } else {
2777       __ load_klass(recv, recv);
2778       Label update_done;
2779       type_profile_helper(mdo, md, data, recv, &update_done);
2780       // Receiver did not match any saved receiver and there is no empty row for it.
2781       // Increment total counter to indicate polymorphic case.
2782       __ addptr(counter_addr, DataLayout::counter_increment);
2783 
2784       __ bind(update_done);
2785     }
2786   } else {
2787     // Static call
2788     __ addptr(counter_addr, DataLayout::counter_increment);
2789   }
2790 }
2791 
2792 
2793 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2794   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2795 }
2796 
2797 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2798   assert(op->crc()->is_single_cpu(),  "crc must be register");
2799   assert(op->val()->is_single_cpu(),  "byte value must be register");
2800   assert(op->result_opr()->is_single_cpu(), "result must be register");
2801   Register crc = op->crc()->as_register();
2802   Register val = op->val()->as_register();
2803   Register res = op->result_opr()->as_register();
2804 
2805   assert_different_registers(val, crc, res);
2806   uint64_t offset;
2807   __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2808   __ add(res, res, offset);
2809 
2810   __ mvnw(crc, crc); // ~crc
2811   __ update_byte_crc32(crc, val, res);
2812   __ mvnw(res, crc); // ~crc
2813 }
2814 
2815 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2816   COMMENT("emit_profile_type {");
2817   Register obj = op->obj()->as_register();
2818   Register tmp = op->tmp()->as_pointer_register();
2819   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2820   ciKlass* exact_klass = op->exact_klass();
2821   intptr_t current_klass = op->current_klass();
2822   bool not_null = op->not_null();
2823   bool no_conflict = op->no_conflict();
2824 
2825   Label update, next, none;
2826 
2827   bool do_null = !not_null;
2828   bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2829   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2830 
2831   assert(do_null || do_update, "why are we here?");
2832   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2833   assert(mdo_addr.base() != rscratch1, "wrong register");
2834 
2835   __ verify_oop(obj);
2836 
2837   if (tmp != obj) {
2838     assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2839     __ mov(tmp, obj);
2840   } else {
2841     assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2842   }
2843   if (do_null) {
2844     __ cbnz(tmp, update);
2845     if (!TypeEntries::was_null_seen(current_klass)) {
2846       __ ldr(rscratch2, mdo_addr);
2847       __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2848       __ str(rscratch2, mdo_addr);
2849     }
2850     if (do_update) {
2851 #ifndef ASSERT
2852       __ b(next);
2853     }
2854 #else
2855       __ b(next);
2856     }
2857   } else {
2858     __ cbnz(tmp, update);
2859     __ stop("unexpected null obj");
2860 #endif
2861   }
2862 
2863   __ bind(update);
2864 
2865   if (do_update) {
2866 #ifdef ASSERT
2867     if (exact_klass != nullptr) {
2868       Label ok;
2869       __ load_klass(tmp, tmp);
2870       __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2871       __ eor(rscratch1, tmp, rscratch1);
2872       __ cbz(rscratch1, ok);
2873       __ stop("exact klass and actual klass differ");
2874       __ bind(ok);
2875     }
2876 #endif
2877     if (!no_conflict) {
2878       if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2879         if (exact_klass != nullptr) {
2880           __ mov_metadata(tmp, exact_klass->constant_encoding());
2881         } else {
2882           __ load_klass(tmp, tmp);
2883         }
2884 
2885         __ ldr(rscratch2, mdo_addr);
2886         __ eor(tmp, tmp, rscratch2);
2887         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2888         // klass seen before, nothing to do. The unknown bit may have been
2889         // set already but no need to check.
2890         __ cbz(rscratch1, next);
2891 
2892         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2893 
2894         if (TypeEntries::is_type_none(current_klass)) {
2895           __ cbz(rscratch2, none);
2896           __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2897           __ br(Assembler::EQ, none);
2898           // There is a chance that the checks above
2899           // fail if another thread has just set the
2900           // profiling to this obj's klass
2901           __ dmb(Assembler::ISHLD);
2902           __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2903           __ ldr(rscratch2, mdo_addr);
2904           __ eor(tmp, tmp, rscratch2);
2905           __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2906           __ cbz(rscratch1, next);
2907         }
2908       } else {
2909         assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2910                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2911 
2912         __ ldr(tmp, mdo_addr);
2913         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2914       }
2915 
2916       // different than before. Cannot keep accurate profile.
2917       __ ldr(rscratch2, mdo_addr);
2918       __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2919       __ str(rscratch2, mdo_addr);
2920 
2921       if (TypeEntries::is_type_none(current_klass)) {
2922         __ b(next);
2923 
2924         __ bind(none);
2925         // first time here. Set profile type.
2926         __ str(tmp, mdo_addr);
2927 #ifdef ASSERT
2928         __ andr(tmp, tmp, TypeEntries::type_mask);
2929         __ verify_klass_ptr(tmp);
2930 #endif
2931       }
2932     } else {
2933       // There's a single possible klass at this profile point
2934       assert(exact_klass != nullptr, "should be");
2935       if (TypeEntries::is_type_none(current_klass)) {
2936         __ mov_metadata(tmp, exact_klass->constant_encoding());
2937         __ ldr(rscratch2, mdo_addr);
2938         __ eor(tmp, tmp, rscratch2);
2939         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2940         __ cbz(rscratch1, next);
2941 #ifdef ASSERT
2942         {
2943           Label ok;
2944           __ ldr(rscratch1, mdo_addr);
2945           __ cbz(rscratch1, ok);
2946           __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2947           __ br(Assembler::EQ, ok);
2948           // may have been set by another thread
2949           __ dmb(Assembler::ISHLD);
2950           __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2951           __ ldr(rscratch2, mdo_addr);
2952           __ eor(rscratch2, rscratch1, rscratch2);
2953           __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2954           __ cbz(rscratch2, ok);
2955 
2956           __ stop("unexpected profiling mismatch");
2957           __ bind(ok);
2958         }
2959 #endif
2960         // first time here. Set profile type.
2961         __ str(tmp, mdo_addr);
2962 #ifdef ASSERT
2963         __ andr(tmp, tmp, TypeEntries::type_mask);
2964         __ verify_klass_ptr(tmp);
2965 #endif
2966       } else {
2967         assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2968                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2969 
2970         __ ldr(tmp, mdo_addr);
2971         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2972 
2973         __ orr(tmp, tmp, TypeEntries::type_unknown);
2974         __ str(tmp, mdo_addr);
2975         // FIXME: Write barrier needed here?
2976       }
2977     }
2978 
2979     __ bind(next);
2980   }
2981   COMMENT("} emit_profile_type");
2982 }
2983 
2984 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
2985   Register obj = op->obj()->as_register();
2986   Register tmp = op->tmp()->as_pointer_register();
2987   bool not_null = op->not_null();
2988   int flag = op->flag();
2989 
2990   Label not_inline_type;
2991   if (!not_null) {
2992     __ cbz(obj, not_inline_type);
2993   }
2994 
2995   __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
2996 
2997   Address mdo_addr = as_Address(op->mdp()->as_address_ptr(), rscratch2);
2998   __ ldrb(rscratch1, mdo_addr);
2999   __ orr(rscratch1, rscratch1, flag);
3000   __ strb(rscratch1, mdo_addr);
3001 
3002   __ bind(not_inline_type);
3003 }
3004 
3005 void LIR_Assembler::align_backward_branch_target() {
3006 }
3007 
3008 
3009 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3010   // tmp must be unused
3011   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3012 
3013   if (left->is_single_cpu()) {
3014     assert(dest->is_single_cpu(), "expect single result reg");
3015     __ negw(dest->as_register(), left->as_register());
3016   } else if (left->is_double_cpu()) {
3017     assert(dest->is_double_cpu(), "expect double result reg");
3018     __ neg(dest->as_register_lo(), left->as_register_lo());
3019   } else if (left->is_single_fpu()) {
3020     assert(dest->is_single_fpu(), "expect single float result reg");
3021     __ fnegs(dest->as_float_reg(), left->as_float_reg());
3022   } else {
3023     assert(left->is_double_fpu(), "expect double float operand reg");
3024     assert(dest->is_double_fpu(), "expect double float result reg");
3025     __ fnegd(dest->as_double_reg(), left->as_double_reg());
3026   }
3027 }
3028 
3029 
3030 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3031   if (patch_code != lir_patch_none) {
3032     deoptimize_trap(info);
3033     return;
3034   }
3035 
3036   __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
3037 }
3038 
3039 
3040 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3041   assert(!tmp->is_valid(), "don't need temporary");
3042 
3043   CodeBlob *cb = CodeCache::find_blob(dest);
3044   if (cb) {
3045     __ far_call(RuntimeAddress(dest));
3046   } else {
3047     __ mov(rscratch1, RuntimeAddress(dest));
3048     __ blr(rscratch1);
3049   }
3050 
3051   if (info != nullptr) {
3052     add_call_info_here(info);
3053   }
3054   __ post_call_nop();
3055 }
3056 
3057 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3058   if (dest->is_address() || src->is_address()) {
3059     move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
3060   } else {
3061     ShouldNotReachHere();
3062   }
3063 }
3064 
3065 #ifdef ASSERT
3066 // emit run-time assertion
3067 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3068   assert(op->code() == lir_assert, "must be");
3069 
3070   if (op->in_opr1()->is_valid()) {
3071     assert(op->in_opr2()->is_valid(), "both operands must be valid");
3072     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3073   } else {
3074     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3075     assert(op->condition() == lir_cond_always, "no other conditions allowed");
3076   }
3077 
3078   Label ok;
3079   if (op->condition() != lir_cond_always) {
3080     Assembler::Condition acond = Assembler::AL;
3081     switch (op->condition()) {
3082       case lir_cond_equal:        acond = Assembler::EQ;  break;
3083       case lir_cond_notEqual:     acond = Assembler::NE;  break;
3084       case lir_cond_less:         acond = Assembler::LT;  break;
3085       case lir_cond_lessEqual:    acond = Assembler::LE;  break;
3086       case lir_cond_greaterEqual: acond = Assembler::GE;  break;
3087       case lir_cond_greater:      acond = Assembler::GT;  break;
3088       case lir_cond_belowEqual:   acond = Assembler::LS;  break;
3089       case lir_cond_aboveEqual:   acond = Assembler::HS;  break;
3090       default:                    ShouldNotReachHere();
3091     }
3092     __ br(acond, ok);
3093   }
3094   if (op->halt()) {
3095     const char* str = __ code_string(op->msg());
3096     __ stop(str);
3097   } else {
3098     breakpoint();
3099   }
3100   __ bind(ok);
3101 }
3102 #endif
3103 
3104 #ifndef PRODUCT
3105 #define COMMENT(x)   do { __ block_comment(x); } while (0)
3106 #else
3107 #define COMMENT(x)
3108 #endif
3109 
3110 void LIR_Assembler::membar() {
3111   COMMENT("membar");
3112   __ membar(MacroAssembler::AnyAny);
3113 }
3114 
3115 void LIR_Assembler::membar_acquire() {
3116   __ membar(Assembler::LoadLoad|Assembler::LoadStore);
3117 }
3118 
3119 void LIR_Assembler::membar_release() {
3120   __ membar(Assembler::LoadStore|Assembler::StoreStore);
3121 }
3122 
3123 void LIR_Assembler::membar_loadload() {
3124   __ membar(Assembler::LoadLoad);
3125 }
3126 
3127 void LIR_Assembler::membar_storestore() {
3128   __ membar(MacroAssembler::StoreStore);
3129 }
3130 
3131 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3132 
3133 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3134 
3135 void LIR_Assembler::on_spin_wait() {
3136   __ spin_wait();
3137 }
3138 
3139 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3140   __ mov(result_reg->as_register(), rthread);
3141 }
3142 
3143 void LIR_Assembler::check_orig_pc() {
3144   __ ldr(rscratch2, frame_map()->address_for_orig_pc_addr());
3145   __ cmp(rscratch2, (u1)NULL_WORD);
3146 }
3147 
3148 void LIR_Assembler::peephole(LIR_List *lir) {
3149 #if 0
3150   if (tableswitch_count >= max_tableswitches)
3151     return;
3152 
3153   /*
3154     This finite-state automaton recognizes sequences of compare-and-
3155     branch instructions.  We will turn them into a tableswitch.  You
3156     could argue that C1 really shouldn't be doing this sort of
3157     optimization, but without it the code is really horrible.
3158   */
3159 
3160   enum { start_s, cmp1_s, beq_s, cmp_s } state;
3161   int first_key, last_key = -2147483648;
3162   int next_key = 0;
3163   int start_insn = -1;
3164   int last_insn = -1;
3165   Register reg = noreg;
3166   LIR_Opr reg_opr;
3167   state = start_s;
3168 
3169   LIR_OpList* inst = lir->instructions_list();
3170   for (int i = 0; i < inst->length(); i++) {
3171     LIR_Op* op = inst->at(i);
3172     switch (state) {
3173     case start_s:
3174       first_key = -1;
3175       start_insn = i;
3176       switch (op->code()) {
3177       case lir_cmp:
3178         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3179         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3180         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3181             && opr2->is_constant()
3182             && opr2->type() == T_INT) {
3183           reg_opr = opr1;
3184           reg = opr1->as_register();
3185           first_key = opr2->as_constant_ptr()->as_jint();
3186           next_key = first_key + 1;
3187           state = cmp_s;
3188           goto next_state;
3189         }
3190         break;
3191       }
3192       break;
3193     case cmp_s:
3194       switch (op->code()) {
3195       case lir_branch:
3196         if (op->as_OpBranch()->cond() == lir_cond_equal) {
3197           state = beq_s;
3198           last_insn = i;
3199           goto next_state;
3200         }
3201       }
3202       state = start_s;
3203       break;
3204     case beq_s:
3205       switch (op->code()) {
3206       case lir_cmp: {
3207         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3208         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3209         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3210             && opr1->as_register() == reg
3211             && opr2->is_constant()
3212             && opr2->type() == T_INT
3213             && opr2->as_constant_ptr()->as_jint() == next_key) {
3214           last_key = next_key;
3215           next_key++;
3216           state = cmp_s;
3217           goto next_state;
3218         }
3219       }
3220       }
3221       last_key = next_key;
3222       state = start_s;
3223       break;
3224     default:
3225       assert(false, "impossible state");
3226     }
3227     if (state == start_s) {
3228       if (first_key < last_key - 5L && reg != noreg) {
3229         {
3230           // printf("found run register %d starting at insn %d low value %d high value %d\n",
3231           //        reg->encoding(),
3232           //        start_insn, first_key, last_key);
3233           //   for (int i = 0; i < inst->length(); i++) {
3234           //     inst->at(i)->print();
3235           //     tty->print("\n");
3236           //   }
3237           //   tty->print("\n");
3238         }
3239 
3240         struct tableswitch *sw = &switches[tableswitch_count];
3241         sw->_insn_index = start_insn, sw->_first_key = first_key,
3242           sw->_last_key = last_key, sw->_reg = reg;
3243         inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3244         {
3245           // Insert the new table of branches
3246           int offset = last_insn;
3247           for (int n = first_key; n < last_key; n++) {
3248             inst->insert_before
3249               (last_insn + 1,
3250                new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3251                                 inst->at(offset)->as_OpBranch()->label()));
3252             offset -= 2, i++;
3253           }
3254         }
3255         // Delete all the old compare-and-branch instructions
3256         for (int n = first_key; n < last_key; n++) {
3257           inst->remove_at(start_insn);
3258           inst->remove_at(start_insn);
3259         }
3260         // Insert the tableswitch instruction
3261         inst->insert_before(start_insn,
3262                             new LIR_Op2(lir_cmp, lir_cond_always,
3263                                         LIR_OprFact::intConst(tableswitch_count),
3264                                         reg_opr));
3265         inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3266         tableswitch_count++;
3267       }
3268       reg = noreg;
3269       last_key = -2147483648;
3270     }
3271   next_state:
3272     ;
3273   }
3274 #endif
3275 }
3276 
3277 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3278   Address addr = as_Address(src->as_address_ptr());
3279   BasicType type = src->type();
3280   bool is_oop = is_reference_type(type);
3281 
3282   void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3283   void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3284 
3285   switch(type) {
3286   case T_INT:
3287     xchg = &MacroAssembler::atomic_xchgalw;
3288     add = &MacroAssembler::atomic_addalw;
3289     break;
3290   case T_LONG:
3291     xchg = &MacroAssembler::atomic_xchgal;
3292     add = &MacroAssembler::atomic_addal;
3293     break;
3294   case T_OBJECT:
3295   case T_ARRAY:
3296     if (UseCompressedOops) {
3297       xchg = &MacroAssembler::atomic_xchgalw;
3298       add = &MacroAssembler::atomic_addalw;
3299     } else {
3300       xchg = &MacroAssembler::atomic_xchgal;
3301       add = &MacroAssembler::atomic_addal;
3302     }
3303     break;
3304   default:
3305     ShouldNotReachHere();
3306     xchg = &MacroAssembler::atomic_xchgal;
3307     add = &MacroAssembler::atomic_addal; // unreachable
3308   }
3309 
3310   switch (code) {
3311   case lir_xadd:
3312     {
3313       RegisterOrConstant inc;
3314       Register tmp = as_reg(tmp_op);
3315       Register dst = as_reg(dest);
3316       if (data->is_constant()) {
3317         inc = RegisterOrConstant(as_long(data));
3318         assert_different_registers(dst, addr.base(), tmp,
3319                                    rscratch1, rscratch2);
3320       } else {
3321         inc = RegisterOrConstant(as_reg(data));
3322         assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3323                                    rscratch1, rscratch2);
3324       }
3325       __ lea(tmp, addr);
3326       (_masm->*add)(dst, inc, tmp);
3327       break;
3328     }
3329   case lir_xchg:
3330     {
3331       Register tmp = tmp_op->as_register();
3332       Register obj = as_reg(data);
3333       Register dst = as_reg(dest);
3334       if (is_oop && UseCompressedOops) {
3335         __ encode_heap_oop(rscratch2, obj);
3336         obj = rscratch2;
3337       }
3338       assert_different_registers(obj, addr.base(), tmp, rscratch1);
3339       assert_different_registers(dst, addr.base(), tmp, rscratch1);
3340       __ lea(tmp, addr);
3341       (_masm->*xchg)(dst, obj, tmp);
3342       if (is_oop && UseCompressedOops) {
3343         __ decode_heap_oop(dst);
3344       }
3345     }
3346     break;
3347   default:
3348     ShouldNotReachHere();
3349   }
3350   if(!UseLSE) {
3351     __ membar(__ AnyAny);
3352   }
3353 }
3354 
3355 #undef __