1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInlineKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "code/compiledIC.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_aarch64.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "oops/oop.inline.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "runtime/stubRoutines.hpp"
46 #include "utilities/powerOfTwo.hpp"
47 #include "vmreg_aarch64.inline.hpp"
48
49
50 #ifndef PRODUCT
51 #define COMMENT(x) do { __ block_comment(x); } while (0)
52 #else
53 #define COMMENT(x)
54 #endif
55
56 NEEDS_CLEANUP // remove this definitions ?
57 const Register SYNC_header = r0; // synchronization header
58 const Register SHIFT_count = r0; // where count for shift operations must be
59
60 #define __ _masm->
61
62
63 static void select_different_registers(Register preserve,
64 Register extra,
65 Register &tmp1,
66 Register &tmp2) {
67 if (tmp1 == preserve) {
68 assert_different_registers(tmp1, tmp2, extra);
69 tmp1 = extra;
70 } else if (tmp2 == preserve) {
71 assert_different_registers(tmp1, tmp2, extra);
72 tmp2 = extra;
73 }
74 assert_different_registers(preserve, tmp1, tmp2);
75 }
76
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2,
83 Register &tmp3) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, tmp3, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, tmp3, extra);
89 tmp2 = extra;
90 } else if (tmp3 == preserve) {
91 assert_different_registers(tmp1, tmp2, tmp3, extra);
92 tmp3 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2, tmp3);
95 }
96
97
98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
99
100
101 LIR_Opr LIR_Assembler::receiverOpr() {
102 return FrameMap::receiver_opr;
103 }
104
105 LIR_Opr LIR_Assembler::osrBufferPointer() {
106 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
107 }
108
109 //--------------fpu register translations-----------------------
110
111
112 address LIR_Assembler::float_constant(float f) {
113 address const_addr = __ float_constant(f);
114 if (const_addr == nullptr) {
115 bailout("const section overflow");
116 return __ code()->consts()->start();
117 } else {
118 return const_addr;
119 }
120 }
121
122
123 address LIR_Assembler::double_constant(double d) {
124 address const_addr = __ double_constant(d);
125 if (const_addr == nullptr) {
126 bailout("const section overflow");
127 return __ code()->consts()->start();
128 } else {
129 return const_addr;
130 }
131 }
132
133 address LIR_Assembler::int_constant(jlong n) {
134 address const_addr = __ long_constant(n);
135 if (const_addr == nullptr) {
136 bailout("const section overflow");
137 return __ code()->consts()->start();
138 } else {
139 return const_addr;
140 }
141 }
142
143 void LIR_Assembler::breakpoint() { Unimplemented(); }
144
145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
146
147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
148
149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
150 //-------------------------------------------
151
152 static Register as_reg(LIR_Opr op) {
153 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
154 }
155
156 static jlong as_long(LIR_Opr data) {
157 jlong result;
158 switch (data->type()) {
159 case T_INT:
160 result = (data->as_jint());
161 break;
162 case T_LONG:
163 result = (data->as_jlong());
164 break;
165 default:
166 ShouldNotReachHere();
167 result = 0; // unreachable
168 }
169 return result;
170 }
171
172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
173 Register base = addr->base()->as_pointer_register();
174 LIR_Opr opr = addr->index();
175 if (opr->is_cpu_register()) {
176 Register index;
177 if (opr->is_single_cpu())
178 index = opr->as_register();
179 else
180 index = opr->as_register_lo();
181 assert(addr->disp() == 0, "must be");
182 switch(opr->type()) {
183 case T_INT:
184 return Address(base, index, Address::sxtw(addr->scale()));
185 case T_LONG:
186 return Address(base, index, Address::lsl(addr->scale()));
187 default:
188 ShouldNotReachHere();
189 }
190 } else {
191 assert(addr->scale() == 0,
192 "expected for immediate operand, was: %d", addr->scale());
193 ptrdiff_t offset = ptrdiff_t(addr->disp());
194 // NOTE: Does not handle any 16 byte vector access.
195 const uint type_size = type2aelembytes(addr->type(), true);
196 return __ legitimize_address(Address(base, offset), type_size, tmp);
197 }
198 return Address();
199 }
200
201 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
202 ShouldNotReachHere();
203 return Address();
204 }
205
206 Address LIR_Assembler::as_Address(LIR_Address* addr) {
207 return as_Address(addr, rscratch1);
208 }
209
210 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
211 return as_Address(addr, rscratch1); // Ouch
212 // FIXME: This needs to be much more clever. See x86.
213 }
214
215 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
216 // not encodable as a base + (immediate) offset, generate an explicit address
217 // calculation to hold the address in a temporary register.
218 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
219 precond(size == 4 || size == 8);
220 Address addr = frame_map()->address_for_slot(index, adjust);
221 precond(addr.getMode() == Address::base_plus_offset);
222 precond(addr.base() == sp);
223 precond(addr.offset() > 0);
224 uint mask = size - 1;
225 assert((addr.offset() & mask) == 0, "scaled offsets only");
226 return __ legitimize_address(addr, size, tmp);
227 }
228
229 void LIR_Assembler::osr_entry() {
230 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
231 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
232 ValueStack* entry_state = osr_entry->state();
233 int number_of_locks = entry_state->locks_size();
234
235 // we jump here if osr happens with the interpreter
236 // state set up to continue at the beginning of the
237 // loop that triggered osr - in particular, we have
238 // the following registers setup:
239 //
240 // r2: osr buffer
241 //
242
243 // build frame
244 ciMethod* m = compilation()->method();
245 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
246
247 // OSR buffer is
248 //
249 // locals[nlocals-1..0]
250 // monitors[0..number_of_locks]
251 //
252 // locals is a direct copy of the interpreter frame so in the osr buffer
253 // so first slot in the local array is the last local from the interpreter
254 // and last slot is local[0] (receiver) from the interpreter
255 //
256 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
257 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
258 // in the interpreter frame (the method lock if a sync method)
259
260 // Initialize monitors in the compiled activation.
261 // r2: pointer to osr buffer
262 //
263 // All other registers are dead at this point and the locals will be
264 // copied into place by code emitted in the IR.
265
266 Register OSR_buf = osrBufferPointer()->as_pointer_register();
267 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
268 int monitor_offset = BytesPerWord * method()->max_locals() +
269 (2 * BytesPerWord) * (number_of_locks - 1);
270 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
271 // the OSR buffer using 2 word entries: first the lock and then
272 // the oop.
273 for (int i = 0; i < number_of_locks; i++) {
274 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
275 #ifdef ASSERT
276 // verify the interpreter's monitor has a non-null object
277 {
278 Label L;
279 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
280 __ cbnz(rscratch1, L);
281 __ stop("locked object is null");
282 __ bind(L);
283 }
284 #endif
285 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
286 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
287 __ str(r19, frame_map()->address_for_monitor_lock(i));
288 __ str(r20, frame_map()->address_for_monitor_object(i));
289 }
290 }
291 }
292
293
294 // inline cache check; done before the frame is built.
295 int LIR_Assembler::check_icache() {
296 return __ ic_check(CodeEntryAlignment);
297 }
298
299 void LIR_Assembler::clinit_barrier(ciMethod* method) {
300 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
301 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
302
303 Label L_skip_barrier;
304
305 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
306 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
307 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
308 __ bind(L_skip_barrier);
309 }
310
311 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
312 if (o == nullptr) {
313 __ mov(reg, zr);
314 } else {
315 __ movoop(reg, o);
316 }
317 }
318
319 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
320 address target = nullptr;
321 relocInfo::relocType reloc_type = relocInfo::none;
322
323 switch (patching_id(info)) {
324 case PatchingStub::access_field_id:
325 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
326 reloc_type = relocInfo::section_word_type;
327 break;
328 case PatchingStub::load_klass_id:
329 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
330 reloc_type = relocInfo::metadata_type;
331 break;
332 case PatchingStub::load_mirror_id:
333 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
334 reloc_type = relocInfo::oop_type;
335 break;
336 case PatchingStub::load_appendix_id:
337 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
338 reloc_type = relocInfo::oop_type;
339 break;
340 default: ShouldNotReachHere();
341 }
342
343 __ far_call(RuntimeAddress(target));
344 add_call_info_here(info);
345 }
346
347 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
348 deoptimize_trap(info);
349 }
350
351
352 // This specifies the rsp decrement needed to build the frame
353 int LIR_Assembler::initial_frame_size_in_bytes() const {
354 // if rounding, must let FrameMap know!
355
356 return in_bytes(frame_map()->framesize_in_bytes());
357 }
358
359
360 int LIR_Assembler::emit_exception_handler() {
361 // generate code for exception handler
362 address handler_base = __ start_a_stub(exception_handler_size());
363 if (handler_base == nullptr) {
364 // not enough space left for the handler
365 bailout("exception handler overflow");
366 return -1;
367 }
368
369 int offset = code_offset();
370
371 // the exception oop and pc are in r0, and r3
372 // no other registers need to be preserved, so invalidate them
373 __ invalidate_registers(false, true, true, false, true, true);
374
375 // check that there is really an exception
376 __ verify_not_null_oop(r0);
377
378 // search an exception handler (r0: exception oop, r3: throwing pc)
379 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
380 __ should_not_reach_here();
381 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
382 __ end_a_stub();
383
384 return offset;
385 }
386
387
388 // Emit the code to remove the frame from the stack in the exception
389 // unwind path.
390 int LIR_Assembler::emit_unwind_handler() {
391 #ifndef PRODUCT
392 if (CommentedAssembly) {
393 _masm->block_comment("Unwind handler");
394 }
395 #endif
396
397 int offset = code_offset();
398
399 // Fetch the exception from TLS and clear out exception related thread state
400 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
401 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
403
404 __ bind(_unwind_handler_entry);
405 __ verify_not_null_oop(r0);
406 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
407 __ mov(r19, r0); // Preserve the exception
408 }
409
410 // Perform needed unlocking
411 MonitorExitStub* stub = nullptr;
412 if (method()->is_synchronized()) {
413 monitor_address(0, FrameMap::r0_opr);
414 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
415 if (LockingMode == LM_MONITOR) {
416 __ b(*stub->entry());
417 } else {
418 __ unlock_object(r5, r4, r0, r6, *stub->entry());
419 }
420 __ bind(*stub->continuation());
421 }
422
423 if (compilation()->env()->dtrace_method_probes()) {
424 __ mov(c_rarg0, rthread);
425 __ mov_metadata(c_rarg1, method()->constant_encoding());
426 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
427 }
428
429 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
430 __ mov(r0, r19); // Restore the exception
431 }
432
433 // remove the activation and dispatch to the unwind handler
434 __ block_comment("remove_frame and dispatch to the unwind handler");
435 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
436 __ far_jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
437
438 // Emit the slow path assembly
439 if (stub != nullptr) {
440 stub->emit_code(this);
441 }
442
443 return offset;
444 }
445
446
447 int LIR_Assembler::emit_deopt_handler() {
448 // generate code for exception handler
449 address handler_base = __ start_a_stub(deopt_handler_size());
450 if (handler_base == nullptr) {
451 // not enough space left for the handler
452 bailout("deopt handler overflow");
453 return -1;
454 }
455
456 int offset = code_offset();
457
458 __ adr(lr, pc());
459 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
460 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
461 __ end_a_stub();
462
463 return offset;
464 }
465
466 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
467 _masm->code_section()->relocate(adr, relocInfo::poll_type);
468 int pc_offset = code_offset();
469 flush_debug_info(pc_offset);
470 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
471 if (info->exception_handlers() != nullptr) {
472 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
473 }
474 }
475
476 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
477 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
478
479 if (InlineTypeReturnedAsFields) {
480 // Check if we are returning an non-null inline type and load its fields into registers
481 ciType* return_type = compilation()->method()->return_type();
482 if (return_type->is_inlinetype()) {
483 ciInlineKlass* vk = return_type->as_inline_klass();
484 if (vk->can_be_returned_as_fields()) {
485 address unpack_handler = vk->unpack_handler();
486 assert(unpack_handler != nullptr, "must be");
487 __ far_call(RuntimeAddress(unpack_handler));
488 }
489 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) {
490 Label skip;
491 __ test_oop_is_not_inline_type(r0, rscratch2, skip);
492
493 // Load fields from a buffered value with an inline class specific handler
494 __ load_klass(rscratch1 /*dst*/, r0 /*src*/);
495 __ ldr(rscratch1, Address(rscratch1, InstanceKlass::adr_inlineklass_fixed_block_offset()));
496 __ ldr(rscratch1, Address(rscratch1, InlineKlass::unpack_handler_offset()));
497 // Unpack handler can be null if inline type is not scalarizable in returns
498 __ cbz(rscratch1, skip);
499 __ blr(rscratch1);
500
501 __ bind(skip);
502 }
503 // At this point, r0 points to the value object (for interpreter or C1 caller).
504 // The fields of the object are copied into registers (for C2 caller).
505 }
506
507 // Pop the stack before the safepoint code
508 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
509
510 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
511 __ reserved_stack_check();
512 }
513
514 code_stub->set_safepoint_offset(__ offset());
515 __ relocate(relocInfo::poll_return_type);
516 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
517 __ ret(lr);
518 }
519
520 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
521 return (__ store_inline_type_fields_to_buf(vk, false));
522 }
523
524 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
525 guarantee(info != nullptr, "Shouldn't be null");
526 __ get_polling_page(rscratch1, relocInfo::poll_type);
527 add_debug_info_for_branch(info); // This isn't just debug info:
528 // it's the oop map
529 __ read_polling_page(rscratch1, relocInfo::poll_type);
530 return __ offset();
531 }
532
533
534 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
535 if (from_reg == r31_sp)
536 from_reg = sp;
537 if (to_reg == r31_sp)
538 to_reg = sp;
539 __ mov(to_reg, from_reg);
540 }
541
542 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
543
544
545 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
546 assert(src->is_constant(), "should not call otherwise");
547 assert(dest->is_register(), "should not call otherwise");
548 LIR_Const* c = src->as_constant_ptr();
549
550 switch (c->type()) {
551 case T_INT: {
552 assert(patch_code == lir_patch_none, "no patching handled here");
553 __ movw(dest->as_register(), c->as_jint());
554 break;
555 }
556
557 case T_ADDRESS: {
558 assert(patch_code == lir_patch_none, "no patching handled here");
559 __ mov(dest->as_register(), c->as_jint());
560 break;
561 }
562
563 case T_LONG: {
564 assert(patch_code == lir_patch_none, "no patching handled here");
565 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
566 break;
567 }
568
569 case T_OBJECT: {
570 if (patch_code != lir_patch_none) {
571 jobject2reg_with_patching(dest->as_register(), info);
572 } else {
573 jobject2reg(c->as_jobject(), dest->as_register());
574 }
575 break;
576 }
577
578 case T_METADATA: {
579 if (patch_code != lir_patch_none) {
580 klass2reg_with_patching(dest->as_register(), info);
581 } else {
582 __ mov_metadata(dest->as_register(), c->as_metadata());
583 }
584 break;
585 }
586
587 case T_FLOAT: {
588 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
589 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
590 } else {
591 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
592 __ ldrs(dest->as_float_reg(), Address(rscratch1));
593 }
594 break;
595 }
596
597 case T_DOUBLE: {
598 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
599 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
600 } else {
601 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
602 __ ldrd(dest->as_double_reg(), Address(rscratch1));
603 }
604 break;
605 }
606
607 default:
608 ShouldNotReachHere();
609 }
610 }
611
612 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
613 LIR_Const* c = src->as_constant_ptr();
614 switch (c->type()) {
615 case T_OBJECT:
616 {
617 if (! c->as_jobject())
618 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
619 else {
620 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
621 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
622 }
623 }
624 break;
625 case T_ADDRESS:
626 {
627 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
628 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
629 }
630 case T_INT:
631 case T_FLOAT:
632 {
633 Register reg = zr;
634 if (c->as_jint_bits() == 0)
635 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
636 else {
637 __ movw(rscratch1, c->as_jint_bits());
638 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
639 }
640 }
641 break;
642 case T_LONG:
643 case T_DOUBLE:
644 {
645 Register reg = zr;
646 if (c->as_jlong_bits() == 0)
647 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
648 lo_word_offset_in_bytes));
649 else {
650 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
651 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
652 lo_word_offset_in_bytes));
653 }
654 }
655 break;
656 default:
657 ShouldNotReachHere();
658 }
659 }
660
661 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
662 assert(src->is_constant(), "should not call otherwise");
663 LIR_Const* c = src->as_constant_ptr();
664 LIR_Address* to_addr = dest->as_address_ptr();
665
666 void (Assembler::* insn)(Register Rt, const Address &adr);
667
668 switch (type) {
669 case T_ADDRESS:
670 assert(c->as_jint() == 0, "should be");
671 insn = &Assembler::str;
672 break;
673 case T_LONG:
674 assert(c->as_jlong() == 0, "should be");
675 insn = &Assembler::str;
676 break;
677 case T_INT:
678 assert(c->as_jint() == 0, "should be");
679 insn = &Assembler::strw;
680 break;
681 case T_OBJECT:
682 case T_ARRAY:
683 // Non-null case is not handled on aarch64 but handled on x86
684 // FIXME: do we need to add it here?
685 assert(c->as_jobject() == nullptr, "should be");
686 if (UseCompressedOops && !wide) {
687 insn = &Assembler::strw;
688 } else {
689 insn = &Assembler::str;
690 }
691 break;
692 case T_CHAR:
693 case T_SHORT:
694 assert(c->as_jint() == 0, "should be");
695 insn = &Assembler::strh;
696 break;
697 case T_BOOLEAN:
698 case T_BYTE:
699 assert(c->as_jint() == 0, "should be");
700 insn = &Assembler::strb;
701 break;
702 default:
703 ShouldNotReachHere();
704 insn = &Assembler::str; // unreachable
705 }
706
707 if (info) add_debug_info_for_null_check_here(info);
708 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
709 }
710
711 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
712 assert(src->is_register(), "should not call otherwise");
713 assert(dest->is_register(), "should not call otherwise");
714
715 // move between cpu-registers
716 if (dest->is_single_cpu()) {
717 if (src->type() == T_LONG) {
718 // Can do LONG -> OBJECT
719 move_regs(src->as_register_lo(), dest->as_register());
720 return;
721 }
722 assert(src->is_single_cpu(), "must match");
723 if (src->type() == T_OBJECT) {
724 __ verify_oop(src->as_register());
725 }
726 move_regs(src->as_register(), dest->as_register());
727
728 } else if (dest->is_double_cpu()) {
729 if (is_reference_type(src->type())) {
730 // Surprising to me but we can see move of a long to t_object
731 __ verify_oop(src->as_register());
732 move_regs(src->as_register(), dest->as_register_lo());
733 return;
734 }
735 assert(src->is_double_cpu(), "must match");
736 Register f_lo = src->as_register_lo();
737 Register f_hi = src->as_register_hi();
738 Register t_lo = dest->as_register_lo();
739 Register t_hi = dest->as_register_hi();
740 assert(f_hi == f_lo, "must be same");
741 assert(t_hi == t_lo, "must be same");
742 move_regs(f_lo, t_lo);
743
744 } else if (dest->is_single_fpu()) {
745 __ fmovs(dest->as_float_reg(), src->as_float_reg());
746
747 } else if (dest->is_double_fpu()) {
748 __ fmovd(dest->as_double_reg(), src->as_double_reg());
749
750 } else {
751 ShouldNotReachHere();
752 }
753 }
754
755 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
756 precond(src->is_register() && dest->is_stack());
757
758 uint const c_sz32 = sizeof(uint32_t);
759 uint const c_sz64 = sizeof(uint64_t);
760
761 if (src->is_single_cpu()) {
762 int index = dest->single_stack_ix();
763 if (is_reference_type(type)) {
764 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
765 __ verify_oop(src->as_register());
766 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
767 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
768 } else {
769 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
770 }
771
772 } else if (src->is_double_cpu()) {
773 int index = dest->double_stack_ix();
774 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
775 __ str(src->as_register_lo(), dest_addr_LO);
776
777 } else if (src->is_single_fpu()) {
778 int index = dest->single_stack_ix();
779 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
780
781 } else if (src->is_double_fpu()) {
782 int index = dest->double_stack_ix();
783 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
784
785 } else {
786 ShouldNotReachHere();
787 }
788 }
789
790
791 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
792 LIR_Address* to_addr = dest->as_address_ptr();
793 PatchingStub* patch = nullptr;
794 Register compressed_src = rscratch1;
795
796 if (patch_code != lir_patch_none) {
797 deoptimize_trap(info);
798 return;
799 }
800
801 if (is_reference_type(type)) {
802 __ verify_oop(src->as_register());
803
804 if (UseCompressedOops && !wide) {
805 __ encode_heap_oop(compressed_src, src->as_register());
806 } else {
807 compressed_src = src->as_register();
808 }
809 }
810
811 int null_check_here = code_offset();
812 switch (type) {
813 case T_FLOAT: {
814 __ strs(src->as_float_reg(), as_Address(to_addr));
815 break;
816 }
817
818 case T_DOUBLE: {
819 __ strd(src->as_double_reg(), as_Address(to_addr));
820 break;
821 }
822
823 case T_ARRAY: // fall through
824 case T_OBJECT: // fall through
825 if (UseCompressedOops && !wide) {
826 __ strw(compressed_src, as_Address(to_addr, rscratch2));
827 } else {
828 __ str(compressed_src, as_Address(to_addr));
829 }
830 break;
831 case T_METADATA:
832 // We get here to store a method pointer to the stack to pass to
833 // a dtrace runtime call. This can't work on 64 bit with
834 // compressed klass ptrs: T_METADATA can be a compressed klass
835 // ptr or a 64 bit method pointer.
836 ShouldNotReachHere();
837 __ str(src->as_register(), as_Address(to_addr));
838 break;
839 case T_ADDRESS:
840 __ str(src->as_register(), as_Address(to_addr));
841 break;
842 case T_INT:
843 __ strw(src->as_register(), as_Address(to_addr));
844 break;
845
846 case T_LONG: {
847 __ str(src->as_register_lo(), as_Address_lo(to_addr));
848 break;
849 }
850
851 case T_BYTE: // fall through
852 case T_BOOLEAN: {
853 __ strb(src->as_register(), as_Address(to_addr));
854 break;
855 }
856
857 case T_CHAR: // fall through
858 case T_SHORT:
859 __ strh(src->as_register(), as_Address(to_addr));
860 break;
861
862 default:
863 ShouldNotReachHere();
864 }
865 if (info != nullptr) {
866 add_debug_info_for_null_check(null_check_here, info);
867 }
868 }
869
870
871 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
872 precond(src->is_stack() && dest->is_register());
873
874 uint const c_sz32 = sizeof(uint32_t);
875 uint const c_sz64 = sizeof(uint64_t);
876
877 if (dest->is_single_cpu()) {
878 int index = src->single_stack_ix();
879 if (is_reference_type(type)) {
880 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
881 __ verify_oop(dest->as_register());
882 } else if (type == T_METADATA || type == T_ADDRESS) {
883 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
884 } else {
885 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
886 }
887
888 } else if (dest->is_double_cpu()) {
889 int index = src->double_stack_ix();
890 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
891 __ ldr(dest->as_register_lo(), src_addr_LO);
892
893 } else if (dest->is_single_fpu()) {
894 int index = src->single_stack_ix();
895 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
896
897 } else if (dest->is_double_fpu()) {
898 int index = src->double_stack_ix();
899 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
900
901 } else {
902 ShouldNotReachHere();
903 }
904 }
905
906
907 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
908 address target = nullptr;
909 relocInfo::relocType reloc_type = relocInfo::none;
910
911 switch (patching_id(info)) {
912 case PatchingStub::access_field_id:
913 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
914 reloc_type = relocInfo::section_word_type;
915 break;
916 case PatchingStub::load_klass_id:
917 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
918 reloc_type = relocInfo::metadata_type;
919 break;
920 case PatchingStub::load_mirror_id:
921 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
922 reloc_type = relocInfo::oop_type;
923 break;
924 case PatchingStub::load_appendix_id:
925 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
926 reloc_type = relocInfo::oop_type;
927 break;
928 default: ShouldNotReachHere();
929 }
930
931 __ far_call(RuntimeAddress(target));
932 add_call_info_here(info);
933 }
934
935 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
936
937 LIR_Opr temp;
938 if (type == T_LONG || type == T_DOUBLE)
939 temp = FrameMap::rscratch1_long_opr;
940 else
941 temp = FrameMap::rscratch1_opr;
942
943 stack2reg(src, temp, src->type());
944 reg2stack(temp, dest, dest->type(), false);
945 }
946
947
948 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
949 LIR_Address* addr = src->as_address_ptr();
950 LIR_Address* from_addr = src->as_address_ptr();
951
952 if (addr->base()->type() == T_OBJECT) {
953 __ verify_oop(addr->base()->as_pointer_register());
954 }
955
956 if (patch_code != lir_patch_none) {
957 deoptimize_trap(info);
958 return;
959 }
960
961 if (info != nullptr) {
962 add_debug_info_for_null_check_here(info);
963 }
964 int null_check_here = code_offset();
965 switch (type) {
966 case T_FLOAT: {
967 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
968 break;
969 }
970
971 case T_DOUBLE: {
972 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
973 break;
974 }
975
976 case T_ARRAY: // fall through
977 case T_OBJECT: // fall through
978 if (UseCompressedOops && !wide) {
979 __ ldrw(dest->as_register(), as_Address(from_addr));
980 } else {
981 __ ldr(dest->as_register(), as_Address(from_addr));
982 }
983 break;
984 case T_METADATA:
985 // We get here to store a method pointer to the stack to pass to
986 // a dtrace runtime call. This can't work on 64 bit with
987 // compressed klass ptrs: T_METADATA can be a compressed klass
988 // ptr or a 64 bit method pointer.
989 ShouldNotReachHere();
990 __ ldr(dest->as_register(), as_Address(from_addr));
991 break;
992 case T_ADDRESS:
993 __ ldr(dest->as_register(), as_Address(from_addr));
994 break;
995 case T_INT:
996 __ ldrw(dest->as_register(), as_Address(from_addr));
997 break;
998
999 case T_LONG: {
1000 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1001 break;
1002 }
1003
1004 case T_BYTE:
1005 __ ldrsb(dest->as_register(), as_Address(from_addr));
1006 break;
1007 case T_BOOLEAN: {
1008 __ ldrb(dest->as_register(), as_Address(from_addr));
1009 break;
1010 }
1011
1012 case T_CHAR:
1013 __ ldrh(dest->as_register(), as_Address(from_addr));
1014 break;
1015 case T_SHORT:
1016 __ ldrsh(dest->as_register(), as_Address(from_addr));
1017 break;
1018
1019 default:
1020 ShouldNotReachHere();
1021 }
1022
1023 if (is_reference_type(type)) {
1024 if (UseCompressedOops && !wide) {
1025 __ decode_heap_oop(dest->as_register());
1026 }
1027
1028 __ verify_oop(dest->as_register());
1029 }
1030 }
1031
1032 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
1033 assert(dst->is_cpu_register(), "must be");
1034 assert(dst->type() == src->type(), "must be");
1035
1036 if (src->is_cpu_register()) {
1037 reg2reg(src, dst);
1038 } else if (src->is_stack()) {
1039 stack2reg(src, dst, dst->type());
1040 } else if (src->is_constant()) {
1041 const2reg(src, dst, lir_patch_none, nullptr);
1042 } else {
1043 ShouldNotReachHere();
1044 }
1045 }
1046
1047 int LIR_Assembler::array_element_size(BasicType type) const {
1048 int elem_size = type2aelembytes(type);
1049 return exact_log2(elem_size);
1050 }
1051
1052
1053 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1054 switch (op->code()) {
1055 case lir_idiv:
1056 case lir_irem:
1057 arithmetic_idiv(op->code(),
1058 op->in_opr1(),
1059 op->in_opr2(),
1060 op->in_opr3(),
1061 op->result_opr(),
1062 op->info());
1063 break;
1064 case lir_fmad:
1065 __ fmaddd(op->result_opr()->as_double_reg(),
1066 op->in_opr1()->as_double_reg(),
1067 op->in_opr2()->as_double_reg(),
1068 op->in_opr3()->as_double_reg());
1069 break;
1070 case lir_fmaf:
1071 __ fmadds(op->result_opr()->as_float_reg(),
1072 op->in_opr1()->as_float_reg(),
1073 op->in_opr2()->as_float_reg(),
1074 op->in_opr3()->as_float_reg());
1075 break;
1076 default: ShouldNotReachHere(); break;
1077 }
1078 }
1079
1080 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1081 #ifdef ASSERT
1082 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1083 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1084 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1085 #endif
1086
1087 if (op->cond() == lir_cond_always) {
1088 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1089 __ b(*(op->label()));
1090 } else {
1091 Assembler::Condition acond;
1092 if (op->code() == lir_cond_float_branch) {
1093 bool is_unordered = (op->ublock() == op->block());
1094 // Assembler::EQ does not permit unordered branches, so we add
1095 // another branch here. Likewise, Assembler::NE does not permit
1096 // ordered branches.
1097 if ((is_unordered && op->cond() == lir_cond_equal)
1098 || (!is_unordered && op->cond() == lir_cond_notEqual))
1099 __ br(Assembler::VS, *(op->ublock()->label()));
1100 switch(op->cond()) {
1101 case lir_cond_equal: acond = Assembler::EQ; break;
1102 case lir_cond_notEqual: acond = Assembler::NE; break;
1103 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1104 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1105 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1106 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1107 default: ShouldNotReachHere();
1108 acond = Assembler::EQ; // unreachable
1109 }
1110 } else {
1111 switch (op->cond()) {
1112 case lir_cond_equal: acond = Assembler::EQ; break;
1113 case lir_cond_notEqual: acond = Assembler::NE; break;
1114 case lir_cond_less: acond = Assembler::LT; break;
1115 case lir_cond_lessEqual: acond = Assembler::LE; break;
1116 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1117 case lir_cond_greater: acond = Assembler::GT; break;
1118 case lir_cond_belowEqual: acond = Assembler::LS; break;
1119 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1120 default: ShouldNotReachHere();
1121 acond = Assembler::EQ; // unreachable
1122 }
1123 }
1124 __ br(acond,*(op->label()));
1125 }
1126 }
1127
1128
1129
1130 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1131 LIR_Opr src = op->in_opr();
1132 LIR_Opr dest = op->result_opr();
1133
1134 switch (op->bytecode()) {
1135 case Bytecodes::_i2f:
1136 {
1137 __ scvtfws(dest->as_float_reg(), src->as_register());
1138 break;
1139 }
1140 case Bytecodes::_i2d:
1141 {
1142 __ scvtfwd(dest->as_double_reg(), src->as_register());
1143 break;
1144 }
1145 case Bytecodes::_l2d:
1146 {
1147 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1148 break;
1149 }
1150 case Bytecodes::_l2f:
1151 {
1152 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1153 break;
1154 }
1155 case Bytecodes::_f2d:
1156 {
1157 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1158 break;
1159 }
1160 case Bytecodes::_d2f:
1161 {
1162 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1163 break;
1164 }
1165 case Bytecodes::_i2c:
1166 {
1167 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1168 break;
1169 }
1170 case Bytecodes::_i2l:
1171 {
1172 __ sxtw(dest->as_register_lo(), src->as_register());
1173 break;
1174 }
1175 case Bytecodes::_i2s:
1176 {
1177 __ sxth(dest->as_register(), src->as_register());
1178 break;
1179 }
1180 case Bytecodes::_i2b:
1181 {
1182 __ sxtb(dest->as_register(), src->as_register());
1183 break;
1184 }
1185 case Bytecodes::_l2i:
1186 {
1187 _masm->block_comment("FIXME: This could be a no-op");
1188 __ uxtw(dest->as_register(), src->as_register_lo());
1189 break;
1190 }
1191 case Bytecodes::_d2l:
1192 {
1193 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1194 break;
1195 }
1196 case Bytecodes::_f2i:
1197 {
1198 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1199 break;
1200 }
1201 case Bytecodes::_f2l:
1202 {
1203 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1204 break;
1205 }
1206 case Bytecodes::_d2i:
1207 {
1208 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1209 break;
1210 }
1211 default: ShouldNotReachHere();
1212 }
1213 }
1214
1215 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1216 if (op->init_check()) {
1217 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1218 __ ldarb(rscratch1, rscratch1);
1219 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1220 add_debug_info_for_null_check_here(op->stub()->info());
1221 __ br(Assembler::NE, *op->stub()->entry());
1222 }
1223 __ allocate_object(op->obj()->as_register(),
1224 op->tmp1()->as_register(),
1225 op->tmp2()->as_register(),
1226 op->header_size(),
1227 op->object_size(),
1228 op->klass()->as_register(),
1229 *op->stub()->entry());
1230 __ bind(*op->stub()->continuation());
1231 }
1232
1233 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1234 Register len = op->len()->as_register();
1235 __ uxtw(len, len);
1236
1237 if (UseSlowPath || op->is_null_free() ||
1238 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1239 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1240 __ b(*op->stub()->entry());
1241 } else {
1242 Register tmp1 = op->tmp1()->as_register();
1243 Register tmp2 = op->tmp2()->as_register();
1244 Register tmp3 = op->tmp3()->as_register();
1245 if (len == tmp1) {
1246 tmp1 = tmp3;
1247 } else if (len == tmp2) {
1248 tmp2 = tmp3;
1249 } else if (len == tmp3) {
1250 // everything is ok
1251 } else {
1252 __ mov(tmp3, len);
1253 }
1254 __ allocate_array(op->obj()->as_register(),
1255 len,
1256 tmp1,
1257 tmp2,
1258 arrayOopDesc::base_offset_in_bytes(op->type()),
1259 array_element_size(op->type()),
1260 op->klass()->as_register(),
1261 *op->stub()->entry(),
1262 op->zero_array());
1263 }
1264 __ bind(*op->stub()->continuation());
1265 }
1266
1267 void LIR_Assembler::type_profile_helper(Register mdo,
1268 ciMethodData *md, ciProfileData *data,
1269 Register recv, Label* update_done) {
1270
1271 // Given a profile data offset, generate an Address which points to
1272 // the corresponding slot in mdo->data().
1273 // Clobbers rscratch2.
1274 auto slot_at = [=](ByteSize offset) -> Address {
1275 return __ form_address(rscratch2, mdo,
1276 md->byte_offset_of_slot(data, offset),
1277 LogBytesPerWord);
1278 };
1279
1280 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1281 Label next_test;
1282 // See if the receiver is receiver[n].
1283 __ ldr(rscratch1, slot_at(ReceiverTypeData::receiver_offset(i)));
1284 __ cmp(recv, rscratch1);
1285 __ br(Assembler::NE, next_test);
1286 __ addptr(slot_at(ReceiverTypeData::receiver_count_offset(i)),
1287 DataLayout::counter_increment);
1288 __ b(*update_done);
1289 __ bind(next_test);
1290 }
1291
1292 // Didn't find receiver; find next empty slot and fill it in
1293 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1294 Label next_test;
1295 Address recv_addr(slot_at(ReceiverTypeData::receiver_offset(i)));
1296 __ ldr(rscratch1, recv_addr);
1297 __ cbnz(rscratch1, next_test);
1298 __ str(recv, recv_addr);
1299 __ mov(rscratch1, DataLayout::counter_increment);
1300 __ str(rscratch1, slot_at(ReceiverTypeData::receiver_count_offset(i)));
1301 __ b(*update_done);
1302 __ bind(next_test);
1303 }
1304 }
1305
1306 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1307 // we always need a stub for the failure case.
1308 CodeStub* stub = op->stub();
1309 Register obj = op->object()->as_register();
1310 Register k_RInfo = op->tmp1()->as_register();
1311 Register klass_RInfo = op->tmp2()->as_register();
1312 Register dst = op->result_opr()->as_register();
1313 ciKlass* k = op->klass();
1314 Register Rtmp1 = noreg;
1315
1316 // check if it needs to be profiled
1317 ciMethodData* md;
1318 ciProfileData* data;
1319
1320 const bool should_profile = op->should_profile();
1321
1322 if (should_profile) {
1323 ciMethod* method = op->profiled_method();
1324 assert(method != nullptr, "Should have method");
1325 int bci = op->profiled_bci();
1326 md = method->method_data_or_null();
1327 assert(md != nullptr, "Sanity");
1328 data = md->bci_to_data(bci);
1329 assert(data != nullptr, "need data for type check");
1330 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1331 }
1332 Label* success_target = success;
1333 Label* failure_target = failure;
1334
1335 if (obj == k_RInfo) {
1336 k_RInfo = dst;
1337 } else if (obj == klass_RInfo) {
1338 klass_RInfo = dst;
1339 }
1340 if (k->is_loaded() && !UseCompressedClassPointers) {
1341 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1342 } else {
1343 Rtmp1 = op->tmp3()->as_register();
1344 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1345 }
1346
1347 assert_different_registers(obj, k_RInfo, klass_RInfo);
1348
1349 if (op->need_null_check()) {
1350 if (should_profile) {
1351 Register mdo = klass_RInfo;
1352 __ mov_metadata(mdo, md->constant_encoding());
1353 Label not_null;
1354 __ cbnz(obj, not_null);
1355 // Object is null; update MDO and exit
1356 Address data_addr
1357 = __ form_address(rscratch2, mdo,
1358 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1359 0);
1360 __ ldrb(rscratch1, data_addr);
1361 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1362 __ strb(rscratch1, data_addr);
1363 __ b(*obj_is_null);
1364 __ bind(not_null);
1365
1366 Label update_done;
1367 Register recv = k_RInfo;
1368 __ load_klass(recv, obj);
1369 type_profile_helper(mdo, md, data, recv, &update_done);
1370 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1371 __ addptr(counter_addr, DataLayout::counter_increment);
1372
1373 __ bind(update_done);
1374 } else {
1375 __ cbz(obj, *obj_is_null);
1376 }
1377 }
1378
1379 if (!k->is_loaded()) {
1380 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1381 } else {
1382 __ mov_metadata(k_RInfo, k->constant_encoding());
1383 }
1384 __ verify_oop(obj);
1385
1386 if (op->fast_check()) {
1387 // get object class
1388 // not a safepoint as obj null check happens earlier
1389 __ load_klass(rscratch1, obj);
1390 __ cmp( rscratch1, k_RInfo);
1391
1392 __ br(Assembler::NE, *failure_target);
1393 // successful cast, fall through to profile or jump
1394 } else {
1395 // get object class
1396 // not a safepoint as obj null check happens earlier
1397 __ load_klass(klass_RInfo, obj);
1398 if (k->is_loaded()) {
1399 // See if we get an immediate positive hit
1400 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1401 __ cmp(k_RInfo, rscratch1);
1402 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1403 __ br(Assembler::NE, *failure_target);
1404 // successful cast, fall through to profile or jump
1405 } else {
1406 // See if we get an immediate positive hit
1407 __ br(Assembler::EQ, *success_target);
1408 // check for self
1409 __ cmp(klass_RInfo, k_RInfo);
1410 __ br(Assembler::EQ, *success_target);
1411
1412 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1413 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1414 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1415 // result is a boolean
1416 __ cbzw(klass_RInfo, *failure_target);
1417 // successful cast, fall through to profile or jump
1418 }
1419 } else {
1420 // perform the fast part of the checking logic
1421 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1422 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1423 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1424 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1425 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1426 // result is a boolean
1427 __ cbz(k_RInfo, *failure_target);
1428 // successful cast, fall through to profile or jump
1429 }
1430 }
1431 __ b(*success);
1432 }
1433
1434
1435 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1436 const bool should_profile = op->should_profile();
1437
1438 LIR_Code code = op->code();
1439 if (code == lir_store_check) {
1440 Register value = op->object()->as_register();
1441 Register array = op->array()->as_register();
1442 Register k_RInfo = op->tmp1()->as_register();
1443 Register klass_RInfo = op->tmp2()->as_register();
1444 Register Rtmp1 = op->tmp3()->as_register();
1445
1446 CodeStub* stub = op->stub();
1447
1448 // check if it needs to be profiled
1449 ciMethodData* md;
1450 ciProfileData* data;
1451
1452 if (should_profile) {
1453 ciMethod* method = op->profiled_method();
1454 assert(method != nullptr, "Should have method");
1455 int bci = op->profiled_bci();
1456 md = method->method_data_or_null();
1457 assert(md != nullptr, "Sanity");
1458 data = md->bci_to_data(bci);
1459 assert(data != nullptr, "need data for type check");
1460 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1461 }
1462 Label done;
1463 Label* success_target = &done;
1464 Label* failure_target = stub->entry();
1465
1466 if (should_profile) {
1467 Label not_null;
1468 Register mdo = klass_RInfo;
1469 __ mov_metadata(mdo, md->constant_encoding());
1470 __ cbnz(value, not_null);
1471 // Object is null; update MDO and exit
1472 Address data_addr
1473 = __ form_address(rscratch2, mdo,
1474 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1475 __ ldrb(rscratch1, data_addr);
1476 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1477 __ strb(rscratch1, data_addr);
1478 __ b(done);
1479 __ bind(not_null);
1480
1481 Label update_done;
1482 Register recv = k_RInfo;
1483 __ load_klass(recv, value);
1484 type_profile_helper(mdo, md, data, recv, &update_done);
1485 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1486 __ addptr(counter_addr, DataLayout::counter_increment);
1487 __ bind(update_done);
1488 } else {
1489 __ cbz(value, done);
1490 }
1491
1492 add_debug_info_for_null_check_here(op->info_for_exception());
1493 __ load_klass(k_RInfo, array);
1494 __ load_klass(klass_RInfo, value);
1495
1496 // get instance klass (it's already uncompressed)
1497 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1498 // perform the fast part of the checking logic
1499 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1500 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1501 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1502 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1503 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1504 // result is a boolean
1505 __ cbzw(k_RInfo, *failure_target);
1506 // fall through to the success case
1507
1508 __ bind(done);
1509 } else if (code == lir_checkcast) {
1510 Register obj = op->object()->as_register();
1511 Register dst = op->result_opr()->as_register();
1512 Label success;
1513 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1514 __ bind(success);
1515 if (dst != obj) {
1516 __ mov(dst, obj);
1517 }
1518 } else if (code == lir_instanceof) {
1519 Register obj = op->object()->as_register();
1520 Register dst = op->result_opr()->as_register();
1521 Label success, failure, done;
1522 emit_typecheck_helper(op, &success, &failure, &failure);
1523 __ bind(failure);
1524 __ mov(dst, zr);
1525 __ b(done);
1526 __ bind(success);
1527 __ mov(dst, 1);
1528 __ bind(done);
1529 } else {
1530 ShouldNotReachHere();
1531 }
1532 }
1533
1534 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1535 // We are loading/storing from/to an array that *may* be a flat array (the
1536 // declared type is Object[], abstract[], interface[] or VT.ref[]).
1537 // If this array is a flat array, take the slow path.
1538 __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1539 if (!op->value()->is_illegal()) {
1540 // The array is not a flat array, but it might be null-free. If we are storing
1541 // a null into a null-free array, take the slow path (which will throw NPE).
1542 Label skip;
1543 __ cbnz(op->value()->as_register(), skip);
1544 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1545 __ bind(skip);
1546 }
1547 }
1548
1549 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1550 // We are storing into an array that *may* be null-free (the declared type is
1551 // Object[], abstract[], interface[] or VT.ref[]).
1552 Label test_mark_word;
1553 Register tmp = op->tmp()->as_register();
1554 __ ldr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
1555 __ tst(tmp, markWord::unlocked_value);
1556 __ br(Assembler::NE, test_mark_word);
1557 __ load_prototype_header(tmp, op->array()->as_register());
1558 __ bind(test_mark_word);
1559 __ tst(tmp, markWord::null_free_array_bit_in_place);
1560 }
1561
1562 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1563 Label L_oops_equal;
1564 Label L_oops_not_equal;
1565 Label L_end;
1566
1567 Register left = op->left()->as_register();
1568 Register right = op->right()->as_register();
1569
1570 __ cmp(left, right);
1571 __ br(Assembler::EQ, L_oops_equal);
1572
1573 // (1) Null check -- if one of the operands is null, the other must not be null (because
1574 // the two references are not equal), so they are not substitutable,
1575 // FIXME: do null check only if the operand is nullable
1576 {
1577 __ cbz(left, L_oops_not_equal);
1578 __ cbz(right, L_oops_not_equal);
1579 }
1580
1581 ciKlass* left_klass = op->left_klass();
1582 ciKlass* right_klass = op->right_klass();
1583
1584 // (2) Inline type check -- if either of the operands is not a inline type,
1585 // they are not substitutable. We do this only if we are not sure that the
1586 // operands are inline type
1587 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node.
1588 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
1589 Register tmp1 = op->tmp1()->as_register();
1590 __ mov(tmp1, markWord::inline_type_pattern);
1591 __ ldr(rscratch1, Address(left, oopDesc::mark_offset_in_bytes()));
1592 __ andr(tmp1, tmp1, rscratch1);
1593 __ ldr(rscratch1, Address(right, oopDesc::mark_offset_in_bytes()));
1594 __ andr(tmp1, tmp1, rscratch1);
1595 __ cmp(tmp1, (u1)markWord::inline_type_pattern);
1596 __ br(Assembler::NE, L_oops_not_equal);
1597 }
1598
1599 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
1600 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) {
1601 // No need to load klass -- the operands are statically known to be the same inline klass.
1602 __ b(*op->stub()->entry());
1603 } else {
1604 Register left_klass_op = op->left_klass_op()->as_register();
1605 Register right_klass_op = op->right_klass_op()->as_register();
1606
1607 if (UseCompressedClassPointers) {
1608 __ ldrw(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1609 __ ldrw(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1610 __ cmpw(left_klass_op, right_klass_op);
1611 } else {
1612 __ ldr(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1613 __ ldr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1614 __ cmp(left_klass_op, right_klass_op);
1615 }
1616
1617 __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check
1618 // fall through to L_oops_not_equal
1619 }
1620
1621 __ bind(L_oops_not_equal);
1622 move(op->not_equal_result(), op->result_opr());
1623 __ b(L_end);
1624
1625 __ bind(L_oops_equal);
1626 move(op->equal_result(), op->result_opr());
1627 __ b(L_end);
1628
1629 // We've returned from the stub. R0 contains 0x0 IFF the two
1630 // operands are not substitutable. (Don't compare against 0x1 in case the
1631 // C compiler is naughty)
1632 __ bind(*op->stub()->continuation());
1633 __ cbz(r0, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1634 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
1635 // fall-through
1636 __ bind(L_end);
1637 }
1638
1639
1640 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1641 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1642 __ cset(rscratch1, Assembler::NE);
1643 __ membar(__ AnyAny);
1644 }
1645
1646 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1647 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1648 __ cset(rscratch1, Assembler::NE);
1649 __ membar(__ AnyAny);
1650 }
1651
1652
1653 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1654 Register addr;
1655 if (op->addr()->is_register()) {
1656 addr = as_reg(op->addr());
1657 } else {
1658 assert(op->addr()->is_address(), "what else?");
1659 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1660 assert(addr_ptr->disp() == 0, "need 0 disp");
1661 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1662 addr = as_reg(addr_ptr->base());
1663 }
1664 Register newval = as_reg(op->new_value());
1665 Register cmpval = as_reg(op->cmp_value());
1666
1667 if (op->code() == lir_cas_obj) {
1668 if (UseCompressedOops) {
1669 Register t1 = op->tmp1()->as_register();
1670 assert(op->tmp1()->is_valid(), "must be");
1671 __ encode_heap_oop(t1, cmpval);
1672 cmpval = t1;
1673 __ encode_heap_oop(rscratch2, newval);
1674 newval = rscratch2;
1675 casw(addr, newval, cmpval);
1676 } else {
1677 casl(addr, newval, cmpval);
1678 }
1679 } else if (op->code() == lir_cas_int) {
1680 casw(addr, newval, cmpval);
1681 } else {
1682 casl(addr, newval, cmpval);
1683 }
1684 }
1685
1686
1687 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1688 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1689 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1690
1691 Assembler::Condition acond, ncond;
1692 switch (condition) {
1693 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1694 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1695 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1696 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1697 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1698 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1699 case lir_cond_belowEqual:
1700 case lir_cond_aboveEqual:
1701 default: ShouldNotReachHere();
1702 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1703 }
1704
1705 assert(result->is_single_cpu() || result->is_double_cpu(),
1706 "expect single register for result");
1707 if (opr1->is_constant() && opr2->is_constant()
1708 && opr1->type() == T_INT && opr2->type() == T_INT) {
1709 jint val1 = opr1->as_jint();
1710 jint val2 = opr2->as_jint();
1711 if (val1 == 0 && val2 == 1) {
1712 __ cset(result->as_register(), ncond);
1713 return;
1714 } else if (val1 == 1 && val2 == 0) {
1715 __ cset(result->as_register(), acond);
1716 return;
1717 }
1718 }
1719
1720 if (opr1->is_constant() && opr2->is_constant()
1721 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1722 jlong val1 = opr1->as_jlong();
1723 jlong val2 = opr2->as_jlong();
1724 if (val1 == 0 && val2 == 1) {
1725 __ cset(result->as_register_lo(), ncond);
1726 return;
1727 } else if (val1 == 1 && val2 == 0) {
1728 __ cset(result->as_register_lo(), acond);
1729 return;
1730 }
1731 }
1732
1733 if (opr1->is_stack()) {
1734 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1735 opr1 = FrameMap::rscratch1_opr;
1736 } else if (opr1->is_constant()) {
1737 LIR_Opr tmp
1738 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1739 const2reg(opr1, tmp, lir_patch_none, nullptr);
1740 opr1 = tmp;
1741 }
1742
1743 if (opr2->is_stack()) {
1744 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1745 opr2 = FrameMap::rscratch2_opr;
1746 } else if (opr2->is_constant()) {
1747 LIR_Opr tmp
1748 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1749 const2reg(opr2, tmp, lir_patch_none, nullptr);
1750 opr2 = tmp;
1751 }
1752
1753 if (result->type() == T_LONG)
1754 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1755 else
1756 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1757 }
1758
1759 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1760 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1761
1762 if (left->is_single_cpu()) {
1763 Register lreg = left->as_register();
1764 Register dreg = as_reg(dest);
1765
1766 if (right->is_single_cpu()) {
1767 // cpu register - cpu register
1768
1769 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1770 "should be");
1771 Register rreg = right->as_register();
1772 switch (code) {
1773 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1774 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1775 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1776 default: ShouldNotReachHere();
1777 }
1778
1779 } else if (right->is_double_cpu()) {
1780 Register rreg = right->as_register_lo();
1781 // single_cpu + double_cpu: can happen with obj+long
1782 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1783 switch (code) {
1784 case lir_add: __ add(dreg, lreg, rreg); break;
1785 case lir_sub: __ sub(dreg, lreg, rreg); break;
1786 default: ShouldNotReachHere();
1787 }
1788 } else if (right->is_constant()) {
1789 // cpu register - constant
1790 jlong c;
1791
1792 // FIXME. This is fugly: we really need to factor all this logic.
1793 switch(right->type()) {
1794 case T_LONG:
1795 c = right->as_constant_ptr()->as_jlong();
1796 break;
1797 case T_INT:
1798 case T_ADDRESS:
1799 c = right->as_constant_ptr()->as_jint();
1800 break;
1801 default:
1802 ShouldNotReachHere();
1803 c = 0; // unreachable
1804 break;
1805 }
1806
1807 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1808 if (c == 0 && dreg == lreg) {
1809 COMMENT("effective nop elided");
1810 return;
1811 }
1812 switch(left->type()) {
1813 case T_INT:
1814 switch (code) {
1815 case lir_add: __ addw(dreg, lreg, c); break;
1816 case lir_sub: __ subw(dreg, lreg, c); break;
1817 default: ShouldNotReachHere();
1818 }
1819 break;
1820 case T_OBJECT:
1821 case T_ADDRESS:
1822 switch (code) {
1823 case lir_add: __ add(dreg, lreg, c); break;
1824 case lir_sub: __ sub(dreg, lreg, c); break;
1825 default: ShouldNotReachHere();
1826 }
1827 break;
1828 default:
1829 ShouldNotReachHere();
1830 }
1831 } else {
1832 ShouldNotReachHere();
1833 }
1834
1835 } else if (left->is_double_cpu()) {
1836 Register lreg_lo = left->as_register_lo();
1837
1838 if (right->is_double_cpu()) {
1839 // cpu register - cpu register
1840 Register rreg_lo = right->as_register_lo();
1841 switch (code) {
1842 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1843 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1844 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1845 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1846 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1847 default:
1848 ShouldNotReachHere();
1849 }
1850
1851 } else if (right->is_constant()) {
1852 jlong c = right->as_constant_ptr()->as_jlong();
1853 Register dreg = as_reg(dest);
1854 switch (code) {
1855 case lir_add:
1856 case lir_sub:
1857 if (c == 0 && dreg == lreg_lo) {
1858 COMMENT("effective nop elided");
1859 return;
1860 }
1861 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1862 break;
1863 case lir_div:
1864 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1865 if (c == 1) {
1866 // move lreg_lo to dreg if divisor is 1
1867 __ mov(dreg, lreg_lo);
1868 } else {
1869 unsigned int shift = log2i_exact(c);
1870 // use rscratch1 as intermediate result register
1871 __ asr(rscratch1, lreg_lo, 63);
1872 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1873 __ asr(dreg, rscratch1, shift);
1874 }
1875 break;
1876 case lir_rem:
1877 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1878 if (c == 1) {
1879 // move 0 to dreg if divisor is 1
1880 __ mov(dreg, zr);
1881 } else {
1882 // use rscratch1 as intermediate result register
1883 __ negs(rscratch1, lreg_lo);
1884 __ andr(dreg, lreg_lo, c - 1);
1885 __ andr(rscratch1, rscratch1, c - 1);
1886 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1887 }
1888 break;
1889 default:
1890 ShouldNotReachHere();
1891 }
1892 } else {
1893 ShouldNotReachHere();
1894 }
1895 } else if (left->is_single_fpu()) {
1896 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1897 switch (code) {
1898 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1899 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1900 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1901 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1902 default:
1903 ShouldNotReachHere();
1904 }
1905 } else if (left->is_double_fpu()) {
1906 if (right->is_double_fpu()) {
1907 // fpu register - fpu register
1908 switch (code) {
1909 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1910 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1911 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1912 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1913 default:
1914 ShouldNotReachHere();
1915 }
1916 } else {
1917 if (right->is_constant()) {
1918 ShouldNotReachHere();
1919 }
1920 ShouldNotReachHere();
1921 }
1922 } else if (left->is_single_stack() || left->is_address()) {
1923 assert(left == dest, "left and dest must be equal");
1924 ShouldNotReachHere();
1925 } else {
1926 ShouldNotReachHere();
1927 }
1928 }
1929
1930 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1931
1932
1933 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1934 switch(code) {
1935 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1936 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1937 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1938 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1939 default : ShouldNotReachHere();
1940 }
1941 }
1942
1943 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1944
1945 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1946 Register Rleft = left->is_single_cpu() ? left->as_register() :
1947 left->as_register_lo();
1948 if (dst->is_single_cpu()) {
1949 Register Rdst = dst->as_register();
1950 if (right->is_constant()) {
1951 switch (code) {
1952 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1953 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1954 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1955 default: ShouldNotReachHere(); break;
1956 }
1957 } else {
1958 Register Rright = right->is_single_cpu() ? right->as_register() :
1959 right->as_register_lo();
1960 switch (code) {
1961 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1962 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1963 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1964 default: ShouldNotReachHere(); break;
1965 }
1966 }
1967 } else {
1968 Register Rdst = dst->as_register_lo();
1969 if (right->is_constant()) {
1970 switch (code) {
1971 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1972 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1973 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1974 default: ShouldNotReachHere(); break;
1975 }
1976 } else {
1977 Register Rright = right->is_single_cpu() ? right->as_register() :
1978 right->as_register_lo();
1979 switch (code) {
1980 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1981 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1982 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1983 default: ShouldNotReachHere(); break;
1984 }
1985 }
1986 }
1987 }
1988
1989
1990
1991 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1992
1993 // opcode check
1994 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1995 bool is_irem = (code == lir_irem);
1996
1997 // operand check
1998 assert(left->is_single_cpu(), "left must be register");
1999 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2000 assert(result->is_single_cpu(), "result must be register");
2001 Register lreg = left->as_register();
2002 Register dreg = result->as_register();
2003
2004 // power-of-2 constant check and codegen
2005 if (right->is_constant()) {
2006 int c = right->as_constant_ptr()->as_jint();
2007 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
2008 if (is_irem) {
2009 if (c == 1) {
2010 // move 0 to dreg if divisor is 1
2011 __ movw(dreg, zr);
2012 } else {
2013 // use rscratch1 as intermediate result register
2014 __ negsw(rscratch1, lreg);
2015 __ andw(dreg, lreg, c - 1);
2016 __ andw(rscratch1, rscratch1, c - 1);
2017 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
2018 }
2019 } else {
2020 if (c == 1) {
2021 // move lreg to dreg if divisor is 1
2022 __ movw(dreg, lreg);
2023 } else {
2024 unsigned int shift = exact_log2(c);
2025 // use rscratch1 as intermediate result register
2026 __ asrw(rscratch1, lreg, 31);
2027 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
2028 __ asrw(dreg, rscratch1, shift);
2029 }
2030 }
2031 } else {
2032 Register rreg = right->as_register();
2033 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
2034 }
2035 }
2036
2037
2038 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2039 if (opr1->is_constant() && opr2->is_single_cpu()) {
2040 // tableswitch
2041 Register reg = as_reg(opr2);
2042 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
2043 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
2044 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
2045 Register reg1 = as_reg(opr1);
2046 if (opr2->is_single_cpu()) {
2047 // cpu register - cpu register
2048 Register reg2 = opr2->as_register();
2049 if (is_reference_type(opr1->type())) {
2050 __ cmpoop(reg1, reg2);
2051 } else {
2052 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2053 __ cmpw(reg1, reg2);
2054 }
2055 return;
2056 }
2057 if (opr2->is_double_cpu()) {
2058 // cpu register - cpu register
2059 Register reg2 = opr2->as_register_lo();
2060 __ cmp(reg1, reg2);
2061 return;
2062 }
2063
2064 if (opr2->is_constant()) {
2065 bool is_32bit = false; // width of register operand
2066 jlong imm;
2067
2068 switch(opr2->type()) {
2069 case T_INT:
2070 imm = opr2->as_constant_ptr()->as_jint();
2071 is_32bit = true;
2072 break;
2073 case T_LONG:
2074 imm = opr2->as_constant_ptr()->as_jlong();
2075 break;
2076 case T_ADDRESS:
2077 imm = opr2->as_constant_ptr()->as_jint();
2078 break;
2079 case T_METADATA:
2080 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
2081 break;
2082 case T_OBJECT:
2083 case T_ARRAY:
2084 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
2085 __ cmpoop(reg1, rscratch1);
2086 return;
2087 default:
2088 ShouldNotReachHere();
2089 imm = 0; // unreachable
2090 break;
2091 }
2092
2093 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
2094 if (is_32bit)
2095 __ cmpw(reg1, imm);
2096 else
2097 __ subs(zr, reg1, imm);
2098 return;
2099 } else {
2100 __ mov(rscratch1, imm);
2101 if (is_32bit)
2102 __ cmpw(reg1, rscratch1);
2103 else
2104 __ cmp(reg1, rscratch1);
2105 return;
2106 }
2107 } else
2108 ShouldNotReachHere();
2109 } else if (opr1->is_single_fpu()) {
2110 FloatRegister reg1 = opr1->as_float_reg();
2111 assert(opr2->is_single_fpu(), "expect single float register");
2112 FloatRegister reg2 = opr2->as_float_reg();
2113 __ fcmps(reg1, reg2);
2114 } else if (opr1->is_double_fpu()) {
2115 FloatRegister reg1 = opr1->as_double_reg();
2116 assert(opr2->is_double_fpu(), "expect double float register");
2117 FloatRegister reg2 = opr2->as_double_reg();
2118 __ fcmpd(reg1, reg2);
2119 } else {
2120 ShouldNotReachHere();
2121 }
2122 }
2123
2124 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2125 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2126 bool is_unordered_less = (code == lir_ucmp_fd2i);
2127 if (left->is_single_fpu()) {
2128 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2129 } else if (left->is_double_fpu()) {
2130 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2131 } else {
2132 ShouldNotReachHere();
2133 }
2134 } else if (code == lir_cmp_l2i) {
2135 Label done;
2136 __ cmp(left->as_register_lo(), right->as_register_lo());
2137 __ mov(dst->as_register(), (uint64_t)-1L);
2138 __ br(Assembler::LT, done);
2139 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2140 __ bind(done);
2141 } else {
2142 ShouldNotReachHere();
2143 }
2144 }
2145
2146
2147 void LIR_Assembler::align_call(LIR_Code code) { }
2148
2149
2150 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2151 address call = __ trampoline_call(Address(op->addr(), rtype));
2152 if (call == nullptr) {
2153 bailout("trampoline stub overflow");
2154 return;
2155 }
2156 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2157 __ post_call_nop();
2158 }
2159
2160
2161 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2162 address call = __ ic_call(op->addr());
2163 if (call == nullptr) {
2164 bailout("trampoline stub overflow");
2165 return;
2166 }
2167 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2168 __ post_call_nop();
2169 }
2170
2171 void LIR_Assembler::emit_static_call_stub() {
2172 address call_pc = __ pc();
2173 address stub = __ start_a_stub(call_stub_size());
2174 if (stub == nullptr) {
2175 bailout("static call stub overflow");
2176 return;
2177 }
2178
2179 int start = __ offset();
2180
2181 __ relocate(static_stub_Relocation::spec(call_pc));
2182 __ emit_static_call_stub();
2183
2184 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2185 <= call_stub_size(), "stub too big");
2186 __ end_a_stub();
2187 }
2188
2189
2190 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2191 assert(exceptionOop->as_register() == r0, "must match");
2192 assert(exceptionPC->as_register() == r3, "must match");
2193
2194 // exception object is not added to oop map by LinearScan
2195 // (LinearScan assumes that no oops are in fixed registers)
2196 info->add_register_oop(exceptionOop);
2197 C1StubId unwind_id;
2198
2199 // get current pc information
2200 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2201 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2202 // As no instructions have been generated yet for this LIR node it's
2203 // possible that an oop map already exists for the current offset.
2204 // In that case insert an dummy NOP here to ensure all oop map PCs
2205 // are unique. See JDK-8237483.
2206 __ nop();
2207 }
2208 int pc_for_athrow_offset = __ offset();
2209 InternalAddress pc_for_athrow(__ pc());
2210 __ adr(exceptionPC->as_register(), pc_for_athrow);
2211 add_call_info(pc_for_athrow_offset, info); // for exception handler
2212
2213 __ verify_not_null_oop(r0);
2214 // search an exception handler (r0: exception oop, r3: throwing pc)
2215 if (compilation()->has_fpu_code()) {
2216 unwind_id = C1StubId::handle_exception_id;
2217 } else {
2218 unwind_id = C1StubId::handle_exception_nofpu_id;
2219 }
2220 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2221
2222 // FIXME: enough room for two byte trap ????
2223 __ nop();
2224 }
2225
2226
2227 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2228 assert(exceptionOop->as_register() == r0, "must match");
2229
2230 __ b(_unwind_handler_entry);
2231 }
2232
2233
2234 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2235 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2236 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2237
2238 switch (left->type()) {
2239 case T_INT: {
2240 switch (code) {
2241 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2242 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2243 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2244 default:
2245 ShouldNotReachHere();
2246 break;
2247 }
2248 break;
2249 case T_LONG:
2250 case T_ADDRESS:
2251 case T_OBJECT:
2252 switch (code) {
2253 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2254 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2255 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2256 default:
2257 ShouldNotReachHere();
2258 break;
2259 }
2260 break;
2261 default:
2262 ShouldNotReachHere();
2263 break;
2264 }
2265 }
2266 }
2267
2268
2269 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2270 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2271 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2272
2273 switch (left->type()) {
2274 case T_INT: {
2275 switch (code) {
2276 case lir_shl: __ lslw (dreg, lreg, count); break;
2277 case lir_shr: __ asrw (dreg, lreg, count); break;
2278 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2279 default:
2280 ShouldNotReachHere();
2281 break;
2282 }
2283 break;
2284 case T_LONG:
2285 case T_ADDRESS:
2286 case T_OBJECT:
2287 switch (code) {
2288 case lir_shl: __ lsl (dreg, lreg, count); break;
2289 case lir_shr: __ asr (dreg, lreg, count); break;
2290 case lir_ushr: __ lsr (dreg, lreg, count); break;
2291 default:
2292 ShouldNotReachHere();
2293 break;
2294 }
2295 break;
2296 default:
2297 ShouldNotReachHere();
2298 break;
2299 }
2300 }
2301 }
2302
2303
2304 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2305 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2306 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2307 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2308 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2309 }
2310
2311
2312 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2313 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2314 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2315 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2316 __ mov (rscratch1, c);
2317 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2318 }
2319
2320
2321 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2322 ShouldNotReachHere();
2323 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2324 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2325 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2326 __ lea(rscratch1, __ constant_oop_address(o));
2327 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2328 }
2329
2330 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
2331 if (null_check) {
2332 __ cbz(obj, *slow_path->entry());
2333 }
2334 if (is_dest) {
2335 __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
2336 // TODO 8350865 Flat no longer implies null-free, so we need to check for flat dest. Can we do better here?
2337 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2338 } else {
2339 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2340 }
2341 }
2342
2343 // This code replaces a call to arraycopy; no exception may
2344 // be thrown in this code, they must be thrown in the System.arraycopy
2345 // activation frame; we could save some checks if this would not be the case
2346 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2347 ciArrayKlass* default_type = op->expected_type();
2348 Register src = op->src()->as_register();
2349 Register dst = op->dst()->as_register();
2350 Register src_pos = op->src_pos()->as_register();
2351 Register dst_pos = op->dst_pos()->as_register();
2352 Register length = op->length()->as_register();
2353 Register tmp = op->tmp()->as_register();
2354
2355 CodeStub* stub = op->stub();
2356 int flags = op->flags();
2357 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2358 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2359
2360 if (flags & LIR_OpArrayCopy::always_slow_path) {
2361 __ b(*stub->entry());
2362 __ bind(*stub->continuation());
2363 return;
2364 }
2365
2366 // if we don't know anything, just go through the generic arraycopy
2367 if (default_type == nullptr // || basic_type == T_OBJECT
2368 ) {
2369 Label done;
2370 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2371
2372 // Save the arguments in case the generic arraycopy fails and we
2373 // have to fall back to the JNI stub
2374 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2375 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2376 __ str(src, Address(sp, 4*BytesPerWord));
2377
2378 address copyfunc_addr = StubRoutines::generic_arraycopy();
2379 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2380
2381 // The arguments are in java calling convention so we shift them
2382 // to C convention
2383 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2384 __ mov(c_rarg0, j_rarg0);
2385 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2386 __ mov(c_rarg1, j_rarg1);
2387 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2388 __ mov(c_rarg2, j_rarg2);
2389 assert_different_registers(c_rarg3, j_rarg4);
2390 __ mov(c_rarg3, j_rarg3);
2391 __ mov(c_rarg4, j_rarg4);
2392 #ifndef PRODUCT
2393 if (PrintC1Statistics) {
2394 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2395 }
2396 #endif
2397 __ far_call(RuntimeAddress(copyfunc_addr));
2398
2399 __ cbz(r0, *stub->continuation());
2400
2401 // Reload values from the stack so they are where the stub
2402 // expects them.
2403 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2404 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2405 __ ldr(src, Address(sp, 4*BytesPerWord));
2406
2407 // r0 is -1^K where K == partial copied count
2408 __ eonw(rscratch1, r0, zr);
2409 // adjust length down and src/end pos up by partial copied count
2410 __ subw(length, length, rscratch1);
2411 __ addw(src_pos, src_pos, rscratch1);
2412 __ addw(dst_pos, dst_pos, rscratch1);
2413 __ b(*stub->entry());
2414
2415 __ bind(*stub->continuation());
2416 return;
2417 }
2418
2419 // Handle inline type arrays
2420 if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
2421 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
2422 }
2423 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
2424 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
2425 }
2426
2427 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2428
2429 int elem_size = type2aelembytes(basic_type);
2430 int scale = exact_log2(elem_size);
2431
2432 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2433 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2434
2435 // test for null
2436 if (flags & LIR_OpArrayCopy::src_null_check) {
2437 __ cbz(src, *stub->entry());
2438 }
2439 if (flags & LIR_OpArrayCopy::dst_null_check) {
2440 __ cbz(dst, *stub->entry());
2441 }
2442
2443 // If the compiler was not able to prove that exact type of the source or the destination
2444 // of the arraycopy is an array type, check at runtime if the source or the destination is
2445 // an instance type.
2446 if (flags & LIR_OpArrayCopy::type_check) {
2447 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2448 __ load_klass(tmp, dst);
2449 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2450 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2451 __ br(Assembler::GE, *stub->entry());
2452 }
2453
2454 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2455 __ load_klass(tmp, src);
2456 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2457 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2458 __ br(Assembler::GE, *stub->entry());
2459 }
2460 }
2461
2462 // check if negative
2463 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2464 __ cmpw(src_pos, 0);
2465 __ br(Assembler::LT, *stub->entry());
2466 }
2467 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2468 __ cmpw(dst_pos, 0);
2469 __ br(Assembler::LT, *stub->entry());
2470 }
2471
2472 if (flags & LIR_OpArrayCopy::length_positive_check) {
2473 __ cmpw(length, 0);
2474 __ br(Assembler::LT, *stub->entry());
2475 }
2476
2477 if (flags & LIR_OpArrayCopy::src_range_check) {
2478 __ addw(tmp, src_pos, length);
2479 __ ldrw(rscratch1, src_length_addr);
2480 __ cmpw(tmp, rscratch1);
2481 __ br(Assembler::HI, *stub->entry());
2482 }
2483 if (flags & LIR_OpArrayCopy::dst_range_check) {
2484 __ addw(tmp, dst_pos, length);
2485 __ ldrw(rscratch1, dst_length_addr);
2486 __ cmpw(tmp, rscratch1);
2487 __ br(Assembler::HI, *stub->entry());
2488 }
2489
2490 if (flags & LIR_OpArrayCopy::type_check) {
2491 // We don't know the array types are compatible
2492 if (basic_type != T_OBJECT) {
2493 // Simple test for basic type arrays
2494 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2495 __ br(Assembler::NE, *stub->entry());
2496 } else {
2497 // For object arrays, if src is a sub class of dst then we can
2498 // safely do the copy.
2499 Label cont, slow;
2500
2501 #define PUSH(r1, r2) \
2502 stp(r1, r2, __ pre(sp, -2 * wordSize));
2503
2504 #define POP(r1, r2) \
2505 ldp(r1, r2, __ post(sp, 2 * wordSize));
2506
2507 __ PUSH(src, dst);
2508
2509 __ load_klass(src, src);
2510 __ load_klass(dst, dst);
2511
2512 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2513
2514 __ PUSH(src, dst);
2515 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
2516 __ POP(src, dst);
2517
2518 __ cbnz(src, cont);
2519
2520 __ bind(slow);
2521 __ POP(src, dst);
2522
2523 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2524 if (copyfunc_addr != nullptr) { // use stub if available
2525 // src is not a sub class of dst so we have to do a
2526 // per-element check.
2527
2528 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2529 if ((flags & mask) != mask) {
2530 // Check that at least both of them object arrays.
2531 assert(flags & mask, "one of the two should be known to be an object array");
2532
2533 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2534 __ load_klass(tmp, src);
2535 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2536 __ load_klass(tmp, dst);
2537 }
2538 int lh_offset = in_bytes(Klass::layout_helper_offset());
2539 Address klass_lh_addr(tmp, lh_offset);
2540 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2541 __ ldrw(rscratch1, klass_lh_addr);
2542 __ mov(rscratch2, objArray_lh);
2543 __ eorw(rscratch1, rscratch1, rscratch2);
2544 __ cbnzw(rscratch1, *stub->entry());
2545 }
2546
2547 // Spill because stubs can use any register they like and it's
2548 // easier to restore just those that we care about.
2549 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2550 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2551 __ str(src, Address(sp, 4*BytesPerWord));
2552
2553 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2554 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2555 assert_different_registers(c_rarg0, dst, dst_pos, length);
2556 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2557 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2558 assert_different_registers(c_rarg1, dst, length);
2559 __ uxtw(c_rarg2, length);
2560 assert_different_registers(c_rarg2, dst);
2561
2562 __ load_klass(c_rarg4, dst);
2563 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2564 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2565 __ far_call(RuntimeAddress(copyfunc_addr));
2566
2567 #ifndef PRODUCT
2568 if (PrintC1Statistics) {
2569 Label failed;
2570 __ cbnz(r0, failed);
2571 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2572 __ bind(failed);
2573 }
2574 #endif
2575
2576 __ cbz(r0, *stub->continuation());
2577
2578 #ifndef PRODUCT
2579 if (PrintC1Statistics) {
2580 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2581 }
2582 #endif
2583 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2584
2585 // Restore previously spilled arguments
2586 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2587 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2588 __ ldr(src, Address(sp, 4*BytesPerWord));
2589
2590 // return value is -1^K where K is partial copied count
2591 __ eonw(rscratch1, r0, zr);
2592 // adjust length down and src/end pos up by partial copied count
2593 __ subw(length, length, rscratch1);
2594 __ addw(src_pos, src_pos, rscratch1);
2595 __ addw(dst_pos, dst_pos, rscratch1);
2596 }
2597
2598 __ b(*stub->entry());
2599
2600 __ bind(cont);
2601 __ POP(src, dst);
2602 }
2603 }
2604
2605 #ifdef ASSERT
2606 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2607 // Sanity check the known type with the incoming class. For the
2608 // primitive case the types must match exactly with src.klass and
2609 // dst.klass each exactly matching the default type. For the
2610 // object array case, if no type check is needed then either the
2611 // dst type is exactly the expected type and the src type is a
2612 // subtype which we can't check or src is the same array as dst
2613 // but not necessarily exactly of type default_type.
2614 Label known_ok, halt;
2615 __ mov_metadata(tmp, default_type->constant_encoding());
2616
2617 if (basic_type != T_OBJECT) {
2618 __ cmp_klass(dst, tmp, rscratch1);
2619 __ br(Assembler::NE, halt);
2620 __ cmp_klass(src, tmp, rscratch1);
2621 __ br(Assembler::EQ, known_ok);
2622 } else {
2623 __ cmp_klass(dst, tmp, rscratch1);
2624 __ br(Assembler::EQ, known_ok);
2625 __ cmp(src, dst);
2626 __ br(Assembler::EQ, known_ok);
2627 }
2628 __ bind(halt);
2629 __ stop("incorrect type information in arraycopy");
2630 __ bind(known_ok);
2631 }
2632 #endif
2633
2634 #ifndef PRODUCT
2635 if (PrintC1Statistics) {
2636 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2637 }
2638 #endif
2639
2640 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2641 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2642 assert_different_registers(c_rarg0, dst, dst_pos, length);
2643 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2644 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2645 assert_different_registers(c_rarg1, dst, length);
2646 __ uxtw(c_rarg2, length);
2647 assert_different_registers(c_rarg2, dst);
2648
2649 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2650 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2651 const char *name;
2652 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2653
2654 CodeBlob *cb = CodeCache::find_blob(entry);
2655 if (cb) {
2656 __ far_call(RuntimeAddress(entry));
2657 } else {
2658 __ call_VM_leaf(entry, 3);
2659 }
2660
2661 if (stub != nullptr) {
2662 __ bind(*stub->continuation());
2663 }
2664 }
2665
2666
2667
2668
2669 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2670 Register obj = op->obj_opr()->as_register(); // may not be an oop
2671 Register hdr = op->hdr_opr()->as_register();
2672 Register lock = op->lock_opr()->as_register();
2673 Register temp = op->scratch_opr()->as_register();
2674 if (LockingMode == LM_MONITOR) {
2675 if (op->info() != nullptr) {
2676 add_debug_info_for_null_check_here(op->info());
2677 __ null_check(obj, -1);
2678 }
2679 __ b(*op->stub()->entry());
2680 } else if (op->code() == lir_lock) {
2681 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2682 // add debug info for NullPointerException only if one is possible
2683 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2684 if (op->info() != nullptr) {
2685 add_debug_info_for_null_check(null_check_offset, op->info());
2686 }
2687 // done
2688 } else if (op->code() == lir_unlock) {
2689 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2690 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2691 } else {
2692 Unimplemented();
2693 }
2694 __ bind(*op->stub()->continuation());
2695 }
2696
2697 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2698 Register obj = op->obj()->as_pointer_register();
2699 Register result = op->result_opr()->as_pointer_register();
2700
2701 CodeEmitInfo* info = op->info();
2702 if (info != nullptr) {
2703 add_debug_info_for_null_check_here(info);
2704 }
2705
2706 __ load_klass(result, obj);
2707 }
2708
2709 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2710 ciMethod* method = op->profiled_method();
2711 int bci = op->profiled_bci();
2712 ciMethod* callee = op->profiled_callee();
2713
2714 // Update counter for all call types
2715 ciMethodData* md = method->method_data_or_null();
2716 assert(md != nullptr, "Sanity");
2717 ciProfileData* data = md->bci_to_data(bci);
2718 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2719 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2720 Register mdo = op->mdo()->as_register();
2721 __ mov_metadata(mdo, md->constant_encoding());
2722 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2723 // Perform additional virtual call profiling for invokevirtual and
2724 // invokeinterface bytecodes
2725 if (op->should_profile_receiver_type()) {
2726 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2727 Register recv = op->recv()->as_register();
2728 assert_different_registers(mdo, recv);
2729 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2730 ciKlass* known_klass = op->known_holder();
2731 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2732 // We know the type that will be seen at this call site; we can
2733 // statically update the MethodData* rather than needing to do
2734 // dynamic tests on the receiver type
2735
2736 // NOTE: we should probably put a lock around this search to
2737 // avoid collisions by concurrent compilations
2738 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2739 uint i;
2740 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2741 ciKlass* receiver = vc_data->receiver(i);
2742 if (known_klass->equals(receiver)) {
2743 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2744 __ addptr(data_addr, DataLayout::counter_increment);
2745 return;
2746 }
2747 }
2748
2749 // Receiver type not found in profile data; select an empty slot
2750
2751 // Note that this is less efficient than it should be because it
2752 // always does a write to the receiver part of the
2753 // VirtualCallData rather than just the first time
2754 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2755 ciKlass* receiver = vc_data->receiver(i);
2756 if (receiver == nullptr) {
2757 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2758 Address recv_addr =
2759 __ form_address(rscratch2, mdo,
2760 md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)),
2761 LogBytesPerWord);
2762 __ str(rscratch1, recv_addr);
2763 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2764 __ addptr(data_addr, DataLayout::counter_increment);
2765 return;
2766 }
2767 }
2768 } else {
2769 __ load_klass(recv, recv);
2770 Label update_done;
2771 type_profile_helper(mdo, md, data, recv, &update_done);
2772 // Receiver did not match any saved receiver and there is no empty row for it.
2773 // Increment total counter to indicate polymorphic case.
2774 __ addptr(counter_addr, DataLayout::counter_increment);
2775
2776 __ bind(update_done);
2777 }
2778 } else {
2779 // Static call
2780 __ addptr(counter_addr, DataLayout::counter_increment);
2781 }
2782 }
2783
2784
2785 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2786 Unimplemented();
2787 }
2788
2789
2790 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2791 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2792 }
2793
2794 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2795 assert(op->crc()->is_single_cpu(), "crc must be register");
2796 assert(op->val()->is_single_cpu(), "byte value must be register");
2797 assert(op->result_opr()->is_single_cpu(), "result must be register");
2798 Register crc = op->crc()->as_register();
2799 Register val = op->val()->as_register();
2800 Register res = op->result_opr()->as_register();
2801
2802 assert_different_registers(val, crc, res);
2803 uint64_t offset;
2804 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2805 __ add(res, res, offset);
2806
2807 __ mvnw(crc, crc); // ~crc
2808 __ update_byte_crc32(crc, val, res);
2809 __ mvnw(res, crc); // ~crc
2810 }
2811
2812 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2813 COMMENT("emit_profile_type {");
2814 Register obj = op->obj()->as_register();
2815 Register tmp = op->tmp()->as_pointer_register();
2816 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2817 ciKlass* exact_klass = op->exact_klass();
2818 intptr_t current_klass = op->current_klass();
2819 bool not_null = op->not_null();
2820 bool no_conflict = op->no_conflict();
2821
2822 Label update, next, none;
2823
2824 bool do_null = !not_null;
2825 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2826 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2827
2828 assert(do_null || do_update, "why are we here?");
2829 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2830 assert(mdo_addr.base() != rscratch1, "wrong register");
2831
2832 __ verify_oop(obj);
2833
2834 if (tmp != obj) {
2835 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2836 __ mov(tmp, obj);
2837 } else {
2838 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2839 }
2840 if (do_null) {
2841 __ cbnz(tmp, update);
2842 if (!TypeEntries::was_null_seen(current_klass)) {
2843 __ ldr(rscratch2, mdo_addr);
2844 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2845 __ str(rscratch2, mdo_addr);
2846 }
2847 if (do_update) {
2848 #ifndef ASSERT
2849 __ b(next);
2850 }
2851 #else
2852 __ b(next);
2853 }
2854 } else {
2855 __ cbnz(tmp, update);
2856 __ stop("unexpected null obj");
2857 #endif
2858 }
2859
2860 __ bind(update);
2861
2862 if (do_update) {
2863 #ifdef ASSERT
2864 if (exact_klass != nullptr) {
2865 Label ok;
2866 __ load_klass(tmp, tmp);
2867 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2868 __ eor(rscratch1, tmp, rscratch1);
2869 __ cbz(rscratch1, ok);
2870 __ stop("exact klass and actual klass differ");
2871 __ bind(ok);
2872 }
2873 #endif
2874 if (!no_conflict) {
2875 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2876 if (exact_klass != nullptr) {
2877 __ mov_metadata(tmp, exact_klass->constant_encoding());
2878 } else {
2879 __ load_klass(tmp, tmp);
2880 }
2881
2882 __ ldr(rscratch2, mdo_addr);
2883 __ eor(tmp, tmp, rscratch2);
2884 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2885 // klass seen before, nothing to do. The unknown bit may have been
2886 // set already but no need to check.
2887 __ cbz(rscratch1, next);
2888
2889 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2890
2891 if (TypeEntries::is_type_none(current_klass)) {
2892 __ cbz(rscratch2, none);
2893 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2894 __ br(Assembler::EQ, none);
2895 // There is a chance that the checks above
2896 // fail if another thread has just set the
2897 // profiling to this obj's klass
2898 __ dmb(Assembler::ISHLD);
2899 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2900 __ ldr(rscratch2, mdo_addr);
2901 __ eor(tmp, tmp, rscratch2);
2902 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2903 __ cbz(rscratch1, next);
2904 }
2905 } else {
2906 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2907 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2908
2909 __ ldr(tmp, mdo_addr);
2910 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2911 }
2912
2913 // different than before. Cannot keep accurate profile.
2914 __ ldr(rscratch2, mdo_addr);
2915 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2916 __ str(rscratch2, mdo_addr);
2917
2918 if (TypeEntries::is_type_none(current_klass)) {
2919 __ b(next);
2920
2921 __ bind(none);
2922 // first time here. Set profile type.
2923 __ str(tmp, mdo_addr);
2924 #ifdef ASSERT
2925 __ andr(tmp, tmp, TypeEntries::type_mask);
2926 __ verify_klass_ptr(tmp);
2927 #endif
2928 }
2929 } else {
2930 // There's a single possible klass at this profile point
2931 assert(exact_klass != nullptr, "should be");
2932 if (TypeEntries::is_type_none(current_klass)) {
2933 __ mov_metadata(tmp, exact_klass->constant_encoding());
2934 __ ldr(rscratch2, mdo_addr);
2935 __ eor(tmp, tmp, rscratch2);
2936 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2937 __ cbz(rscratch1, next);
2938 #ifdef ASSERT
2939 {
2940 Label ok;
2941 __ ldr(rscratch1, mdo_addr);
2942 __ cbz(rscratch1, ok);
2943 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2944 __ br(Assembler::EQ, ok);
2945 // may have been set by another thread
2946 __ dmb(Assembler::ISHLD);
2947 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2948 __ ldr(rscratch2, mdo_addr);
2949 __ eor(rscratch2, rscratch1, rscratch2);
2950 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2951 __ cbz(rscratch2, ok);
2952
2953 __ stop("unexpected profiling mismatch");
2954 __ bind(ok);
2955 }
2956 #endif
2957 // first time here. Set profile type.
2958 __ str(tmp, mdo_addr);
2959 #ifdef ASSERT
2960 __ andr(tmp, tmp, TypeEntries::type_mask);
2961 __ verify_klass_ptr(tmp);
2962 #endif
2963 } else {
2964 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2965 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2966
2967 __ ldr(tmp, mdo_addr);
2968 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2969
2970 __ orr(tmp, tmp, TypeEntries::type_unknown);
2971 __ str(tmp, mdo_addr);
2972 // FIXME: Write barrier needed here?
2973 }
2974 }
2975
2976 __ bind(next);
2977 }
2978 COMMENT("} emit_profile_type");
2979 }
2980
2981 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
2982 Register obj = op->obj()->as_register();
2983 Register tmp = op->tmp()->as_pointer_register();
2984 bool not_null = op->not_null();
2985 int flag = op->flag();
2986
2987 Label not_inline_type;
2988 if (!not_null) {
2989 __ cbz(obj, not_inline_type);
2990 }
2991
2992 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
2993
2994 Address mdo_addr = as_Address(op->mdp()->as_address_ptr(), rscratch2);
2995 __ ldrb(rscratch1, mdo_addr);
2996 __ orr(rscratch1, rscratch1, flag);
2997 __ strb(rscratch1, mdo_addr);
2998
2999 __ bind(not_inline_type);
3000 }
3001
3002 void LIR_Assembler::align_backward_branch_target() {
3003 }
3004
3005
3006 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3007 // tmp must be unused
3008 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3009
3010 if (left->is_single_cpu()) {
3011 assert(dest->is_single_cpu(), "expect single result reg");
3012 __ negw(dest->as_register(), left->as_register());
3013 } else if (left->is_double_cpu()) {
3014 assert(dest->is_double_cpu(), "expect double result reg");
3015 __ neg(dest->as_register_lo(), left->as_register_lo());
3016 } else if (left->is_single_fpu()) {
3017 assert(dest->is_single_fpu(), "expect single float result reg");
3018 __ fnegs(dest->as_float_reg(), left->as_float_reg());
3019 } else {
3020 assert(left->is_double_fpu(), "expect double float operand reg");
3021 assert(dest->is_double_fpu(), "expect double float result reg");
3022 __ fnegd(dest->as_double_reg(), left->as_double_reg());
3023 }
3024 }
3025
3026
3027 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3028 if (patch_code != lir_patch_none) {
3029 deoptimize_trap(info);
3030 return;
3031 }
3032
3033 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
3034 }
3035
3036
3037 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3038 assert(!tmp->is_valid(), "don't need temporary");
3039
3040 CodeBlob *cb = CodeCache::find_blob(dest);
3041 if (cb) {
3042 __ far_call(RuntimeAddress(dest));
3043 } else {
3044 __ mov(rscratch1, RuntimeAddress(dest));
3045 __ blr(rscratch1);
3046 }
3047
3048 if (info != nullptr) {
3049 add_call_info_here(info);
3050 }
3051 __ post_call_nop();
3052 }
3053
3054 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3055 if (dest->is_address() || src->is_address()) {
3056 move_op(src, dest, type, lir_patch_none, info,
3057 /*pop_fpu_stack*/false, /*wide*/false);
3058 } else {
3059 ShouldNotReachHere();
3060 }
3061 }
3062
3063 #ifdef ASSERT
3064 // emit run-time assertion
3065 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3066 assert(op->code() == lir_assert, "must be");
3067
3068 if (op->in_opr1()->is_valid()) {
3069 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3070 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3071 } else {
3072 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3073 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3074 }
3075
3076 Label ok;
3077 if (op->condition() != lir_cond_always) {
3078 Assembler::Condition acond = Assembler::AL;
3079 switch (op->condition()) {
3080 case lir_cond_equal: acond = Assembler::EQ; break;
3081 case lir_cond_notEqual: acond = Assembler::NE; break;
3082 case lir_cond_less: acond = Assembler::LT; break;
3083 case lir_cond_lessEqual: acond = Assembler::LE; break;
3084 case lir_cond_greaterEqual: acond = Assembler::GE; break;
3085 case lir_cond_greater: acond = Assembler::GT; break;
3086 case lir_cond_belowEqual: acond = Assembler::LS; break;
3087 case lir_cond_aboveEqual: acond = Assembler::HS; break;
3088 default: ShouldNotReachHere();
3089 }
3090 __ br(acond, ok);
3091 }
3092 if (op->halt()) {
3093 const char* str = __ code_string(op->msg());
3094 __ stop(str);
3095 } else {
3096 breakpoint();
3097 }
3098 __ bind(ok);
3099 }
3100 #endif
3101
3102 #ifndef PRODUCT
3103 #define COMMENT(x) do { __ block_comment(x); } while (0)
3104 #else
3105 #define COMMENT(x)
3106 #endif
3107
3108 void LIR_Assembler::membar() {
3109 COMMENT("membar");
3110 __ membar(MacroAssembler::AnyAny);
3111 }
3112
3113 void LIR_Assembler::membar_acquire() {
3114 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
3115 }
3116
3117 void LIR_Assembler::membar_release() {
3118 __ membar(Assembler::LoadStore|Assembler::StoreStore);
3119 }
3120
3121 void LIR_Assembler::membar_loadload() {
3122 __ membar(Assembler::LoadLoad);
3123 }
3124
3125 void LIR_Assembler::membar_storestore() {
3126 __ membar(MacroAssembler::StoreStore);
3127 }
3128
3129 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3130
3131 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3132
3133 void LIR_Assembler::on_spin_wait() {
3134 __ spin_wait();
3135 }
3136
3137 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3138 __ mov(result_reg->as_register(), rthread);
3139 }
3140
3141 void LIR_Assembler::check_orig_pc() {
3142 __ ldr(rscratch2, frame_map()->address_for_orig_pc_addr());
3143 __ cmp(rscratch2, (u1)NULL_WORD);
3144 }
3145
3146 void LIR_Assembler::peephole(LIR_List *lir) {
3147 #if 0
3148 if (tableswitch_count >= max_tableswitches)
3149 return;
3150
3151 /*
3152 This finite-state automaton recognizes sequences of compare-and-
3153 branch instructions. We will turn them into a tableswitch. You
3154 could argue that C1 really shouldn't be doing this sort of
3155 optimization, but without it the code is really horrible.
3156 */
3157
3158 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3159 int first_key, last_key = -2147483648;
3160 int next_key = 0;
3161 int start_insn = -1;
3162 int last_insn = -1;
3163 Register reg = noreg;
3164 LIR_Opr reg_opr;
3165 state = start_s;
3166
3167 LIR_OpList* inst = lir->instructions_list();
3168 for (int i = 0; i < inst->length(); i++) {
3169 LIR_Op* op = inst->at(i);
3170 switch (state) {
3171 case start_s:
3172 first_key = -1;
3173 start_insn = i;
3174 switch (op->code()) {
3175 case lir_cmp:
3176 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3177 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3178 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3179 && opr2->is_constant()
3180 && opr2->type() == T_INT) {
3181 reg_opr = opr1;
3182 reg = opr1->as_register();
3183 first_key = opr2->as_constant_ptr()->as_jint();
3184 next_key = first_key + 1;
3185 state = cmp_s;
3186 goto next_state;
3187 }
3188 break;
3189 }
3190 break;
3191 case cmp_s:
3192 switch (op->code()) {
3193 case lir_branch:
3194 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3195 state = beq_s;
3196 last_insn = i;
3197 goto next_state;
3198 }
3199 }
3200 state = start_s;
3201 break;
3202 case beq_s:
3203 switch (op->code()) {
3204 case lir_cmp: {
3205 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3206 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3207 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3208 && opr1->as_register() == reg
3209 && opr2->is_constant()
3210 && opr2->type() == T_INT
3211 && opr2->as_constant_ptr()->as_jint() == next_key) {
3212 last_key = next_key;
3213 next_key++;
3214 state = cmp_s;
3215 goto next_state;
3216 }
3217 }
3218 }
3219 last_key = next_key;
3220 state = start_s;
3221 break;
3222 default:
3223 assert(false, "impossible state");
3224 }
3225 if (state == start_s) {
3226 if (first_key < last_key - 5L && reg != noreg) {
3227 {
3228 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3229 // reg->encoding(),
3230 // start_insn, first_key, last_key);
3231 // for (int i = 0; i < inst->length(); i++) {
3232 // inst->at(i)->print();
3233 // tty->print("\n");
3234 // }
3235 // tty->print("\n");
3236 }
3237
3238 struct tableswitch *sw = &switches[tableswitch_count];
3239 sw->_insn_index = start_insn, sw->_first_key = first_key,
3240 sw->_last_key = last_key, sw->_reg = reg;
3241 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3242 {
3243 // Insert the new table of branches
3244 int offset = last_insn;
3245 for (int n = first_key; n < last_key; n++) {
3246 inst->insert_before
3247 (last_insn + 1,
3248 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3249 inst->at(offset)->as_OpBranch()->label()));
3250 offset -= 2, i++;
3251 }
3252 }
3253 // Delete all the old compare-and-branch instructions
3254 for (int n = first_key; n < last_key; n++) {
3255 inst->remove_at(start_insn);
3256 inst->remove_at(start_insn);
3257 }
3258 // Insert the tableswitch instruction
3259 inst->insert_before(start_insn,
3260 new LIR_Op2(lir_cmp, lir_cond_always,
3261 LIR_OprFact::intConst(tableswitch_count),
3262 reg_opr));
3263 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3264 tableswitch_count++;
3265 }
3266 reg = noreg;
3267 last_key = -2147483648;
3268 }
3269 next_state:
3270 ;
3271 }
3272 #endif
3273 }
3274
3275 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3276 Address addr = as_Address(src->as_address_ptr());
3277 BasicType type = src->type();
3278 bool is_oop = is_reference_type(type);
3279
3280 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3281 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3282
3283 switch(type) {
3284 case T_INT:
3285 xchg = &MacroAssembler::atomic_xchgalw;
3286 add = &MacroAssembler::atomic_addalw;
3287 break;
3288 case T_LONG:
3289 xchg = &MacroAssembler::atomic_xchgal;
3290 add = &MacroAssembler::atomic_addal;
3291 break;
3292 case T_OBJECT:
3293 case T_ARRAY:
3294 if (UseCompressedOops) {
3295 xchg = &MacroAssembler::atomic_xchgalw;
3296 add = &MacroAssembler::atomic_addalw;
3297 } else {
3298 xchg = &MacroAssembler::atomic_xchgal;
3299 add = &MacroAssembler::atomic_addal;
3300 }
3301 break;
3302 default:
3303 ShouldNotReachHere();
3304 xchg = &MacroAssembler::atomic_xchgal;
3305 add = &MacroAssembler::atomic_addal; // unreachable
3306 }
3307
3308 switch (code) {
3309 case lir_xadd:
3310 {
3311 RegisterOrConstant inc;
3312 Register tmp = as_reg(tmp_op);
3313 Register dst = as_reg(dest);
3314 if (data->is_constant()) {
3315 inc = RegisterOrConstant(as_long(data));
3316 assert_different_registers(dst, addr.base(), tmp,
3317 rscratch1, rscratch2);
3318 } else {
3319 inc = RegisterOrConstant(as_reg(data));
3320 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3321 rscratch1, rscratch2);
3322 }
3323 __ lea(tmp, addr);
3324 (_masm->*add)(dst, inc, tmp);
3325 break;
3326 }
3327 case lir_xchg:
3328 {
3329 Register tmp = tmp_op->as_register();
3330 Register obj = as_reg(data);
3331 Register dst = as_reg(dest);
3332 if (is_oop && UseCompressedOops) {
3333 __ encode_heap_oop(rscratch2, obj);
3334 obj = rscratch2;
3335 }
3336 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3337 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3338 __ lea(tmp, addr);
3339 (_masm->*xchg)(dst, obj, tmp);
3340 if (is_oop && UseCompressedOops) {
3341 __ decode_heap_oop(dst);
3342 }
3343 }
3344 break;
3345 default:
3346 ShouldNotReachHere();
3347 }
3348 __ membar(__ AnyAny);
3349 }
3350
3351 #undef __