1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInlineKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "code/compiledIC.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_aarch64.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "oops/oop.inline.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "runtime/stubRoutines.hpp"
46 #include "utilities/powerOfTwo.hpp"
47 #include "vmreg_aarch64.inline.hpp"
48
49
50 #ifndef PRODUCT
51 #define COMMENT(x) do { __ block_comment(x); } while (0)
52 #else
53 #define COMMENT(x)
54 #endif
55
56 NEEDS_CLEANUP // remove this definitions ?
57 const Register SYNC_header = r0; // synchronization header
58 const Register SHIFT_count = r0; // where count for shift operations must be
59
60 #define __ _masm->
61
62
63 static void select_different_registers(Register preserve,
64 Register extra,
65 Register &tmp1,
66 Register &tmp2) {
67 if (tmp1 == preserve) {
68 assert_different_registers(tmp1, tmp2, extra);
69 tmp1 = extra;
70 } else if (tmp2 == preserve) {
71 assert_different_registers(tmp1, tmp2, extra);
72 tmp2 = extra;
73 }
74 assert_different_registers(preserve, tmp1, tmp2);
75 }
76
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2,
83 Register &tmp3) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, tmp3, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, tmp3, extra);
89 tmp2 = extra;
90 } else if (tmp3 == preserve) {
91 assert_different_registers(tmp1, tmp2, tmp3, extra);
92 tmp3 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2, tmp3);
95 }
96
97
98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
99
100
101 LIR_Opr LIR_Assembler::receiverOpr() {
102 return FrameMap::receiver_opr;
103 }
104
105 LIR_Opr LIR_Assembler::osrBufferPointer() {
106 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
107 }
108
109 //--------------fpu register translations-----------------------
110
111
112 address LIR_Assembler::float_constant(float f) {
113 address const_addr = __ float_constant(f);
114 if (const_addr == nullptr) {
115 bailout("const section overflow");
116 return __ code()->consts()->start();
117 } else {
118 return const_addr;
119 }
120 }
121
122
123 address LIR_Assembler::double_constant(double d) {
124 address const_addr = __ double_constant(d);
125 if (const_addr == nullptr) {
126 bailout("const section overflow");
127 return __ code()->consts()->start();
128 } else {
129 return const_addr;
130 }
131 }
132
133 address LIR_Assembler::int_constant(jlong n) {
134 address const_addr = __ long_constant(n);
135 if (const_addr == nullptr) {
136 bailout("const section overflow");
137 return __ code()->consts()->start();
138 } else {
139 return const_addr;
140 }
141 }
142
143 void LIR_Assembler::breakpoint() { Unimplemented(); }
144
145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
146
147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
148
149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
150 //-------------------------------------------
151
152 static Register as_reg(LIR_Opr op) {
153 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
154 }
155
156 static jlong as_long(LIR_Opr data) {
157 jlong result;
158 switch (data->type()) {
159 case T_INT:
160 result = (data->as_jint());
161 break;
162 case T_LONG:
163 result = (data->as_jlong());
164 break;
165 default:
166 ShouldNotReachHere();
167 result = 0; // unreachable
168 }
169 return result;
170 }
171
172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
173 Register base = addr->base()->as_pointer_register();
174 LIR_Opr opr = addr->index();
175 if (opr->is_cpu_register()) {
176 Register index;
177 if (opr->is_single_cpu())
178 index = opr->as_register();
179 else
180 index = opr->as_register_lo();
181 assert(addr->disp() == 0, "must be");
182 switch(opr->type()) {
183 case T_INT:
184 return Address(base, index, Address::sxtw(addr->scale()));
185 case T_LONG:
186 return Address(base, index, Address::lsl(addr->scale()));
187 default:
188 ShouldNotReachHere();
189 }
190 } else {
191 assert(addr->scale() == 0,
192 "expected for immediate operand, was: %d", addr->scale());
193 ptrdiff_t offset = ptrdiff_t(addr->disp());
194 // NOTE: Does not handle any 16 byte vector access.
195 const uint type_size = type2aelembytes(addr->type(), true);
196 return __ legitimize_address(Address(base, offset), type_size, tmp);
197 }
198 return Address();
199 }
200
201 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
202 ShouldNotReachHere();
203 return Address();
204 }
205
206 Address LIR_Assembler::as_Address(LIR_Address* addr) {
207 return as_Address(addr, rscratch1);
208 }
209
210 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
211 return as_Address(addr, rscratch1); // Ouch
212 // FIXME: This needs to be much more clever. See x86.
213 }
214
215 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
216 // not encodable as a base + (immediate) offset, generate an explicit address
217 // calculation to hold the address in a temporary register.
218 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
219 precond(size == 4 || size == 8);
220 Address addr = frame_map()->address_for_slot(index, adjust);
221 precond(addr.getMode() == Address::base_plus_offset);
222 precond(addr.base() == sp);
223 precond(addr.offset() > 0);
224 uint mask = size - 1;
225 assert((addr.offset() & mask) == 0, "scaled offsets only");
226 return __ legitimize_address(addr, size, tmp);
227 }
228
229 void LIR_Assembler::osr_entry() {
230 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
231 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
232 ValueStack* entry_state = osr_entry->state();
233 int number_of_locks = entry_state->locks_size();
234
235 // we jump here if osr happens with the interpreter
236 // state set up to continue at the beginning of the
237 // loop that triggered osr - in particular, we have
238 // the following registers setup:
239 //
240 // r2: osr buffer
241 //
242
243 // build frame
244 ciMethod* m = compilation()->method();
245 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
246
247 // OSR buffer is
248 //
249 // locals[nlocals-1..0]
250 // monitors[0..number_of_locks]
251 //
252 // locals is a direct copy of the interpreter frame so in the osr buffer
253 // so first slot in the local array is the last local from the interpreter
254 // and last slot is local[0] (receiver) from the interpreter
255 //
256 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
257 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
258 // in the interpreter frame (the method lock if a sync method)
259
260 // Initialize monitors in the compiled activation.
261 // r2: pointer to osr buffer
262 //
263 // All other registers are dead at this point and the locals will be
264 // copied into place by code emitted in the IR.
265
266 Register OSR_buf = osrBufferPointer()->as_pointer_register();
267 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
268 int monitor_offset = BytesPerWord * method()->max_locals() +
269 (2 * BytesPerWord) * (number_of_locks - 1);
270 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
271 // the OSR buffer using 2 word entries: first the lock and then
272 // the oop.
273 for (int i = 0; i < number_of_locks; i++) {
274 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
275 #ifdef ASSERT
276 // verify the interpreter's monitor has a non-null object
277 {
278 Label L;
279 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
280 __ cbnz(rscratch1, L);
281 __ stop("locked object is null");
282 __ bind(L);
283 }
284 #endif
285 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
286 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
287 __ str(r19, frame_map()->address_for_monitor_lock(i));
288 __ str(r20, frame_map()->address_for_monitor_object(i));
289 }
290 }
291 }
292
293
294 // inline cache check; done before the frame is built.
295 int LIR_Assembler::check_icache() {
296 return __ ic_check(CodeEntryAlignment);
297 }
298
299 void LIR_Assembler::clinit_barrier(ciMethod* method) {
300 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
301 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
302
303 Label L_skip_barrier;
304
305 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
306 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
307 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
308 __ bind(L_skip_barrier);
309 }
310
311 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
312 if (o == nullptr) {
313 __ mov(reg, zr);
314 } else {
315 __ movoop(reg, o);
316 }
317 }
318
319 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
320 address target = nullptr;
321 relocInfo::relocType reloc_type = relocInfo::none;
322
323 switch (patching_id(info)) {
324 case PatchingStub::access_field_id:
325 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
326 reloc_type = relocInfo::section_word_type;
327 break;
328 case PatchingStub::load_klass_id:
329 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
330 reloc_type = relocInfo::metadata_type;
331 break;
332 case PatchingStub::load_mirror_id:
333 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
334 reloc_type = relocInfo::oop_type;
335 break;
336 case PatchingStub::load_appendix_id:
337 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
338 reloc_type = relocInfo::oop_type;
339 break;
340 default: ShouldNotReachHere();
341 }
342
343 __ far_call(RuntimeAddress(target));
344 add_call_info_here(info);
345 }
346
347 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
348 deoptimize_trap(info);
349 }
350
351
352 // This specifies the rsp decrement needed to build the frame
353 int LIR_Assembler::initial_frame_size_in_bytes() const {
354 // if rounding, must let FrameMap know!
355
356 return in_bytes(frame_map()->framesize_in_bytes());
357 }
358
359
360 int LIR_Assembler::emit_exception_handler() {
361 // generate code for exception handler
362 address handler_base = __ start_a_stub(exception_handler_size());
363 if (handler_base == nullptr) {
364 // not enough space left for the handler
365 bailout("exception handler overflow");
366 return -1;
367 }
368
369 int offset = code_offset();
370
371 // the exception oop and pc are in r0, and r3
372 // no other registers need to be preserved, so invalidate them
373 __ invalidate_registers(false, true, true, false, true, true);
374
375 // check that there is really an exception
376 __ verify_not_null_oop(r0);
377
378 // search an exception handler (r0: exception oop, r3: throwing pc)
379 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
380 __ should_not_reach_here();
381 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
382 __ end_a_stub();
383
384 return offset;
385 }
386
387
388 // Emit the code to remove the frame from the stack in the exception
389 // unwind path.
390 int LIR_Assembler::emit_unwind_handler() {
391 #ifndef PRODUCT
392 if (CommentedAssembly) {
393 _masm->block_comment("Unwind handler");
394 }
395 #endif
396
397 int offset = code_offset();
398
399 // Fetch the exception from TLS and clear out exception related thread state
400 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
401 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
403
404 __ bind(_unwind_handler_entry);
405 __ verify_not_null_oop(r0);
406 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
407 __ mov(r19, r0); // Preserve the exception
408 }
409
410 // Perform needed unlocking
411 MonitorExitStub* stub = nullptr;
412 if (method()->is_synchronized()) {
413 monitor_address(0, FrameMap::r0_opr);
414 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
415 __ unlock_object(r5, r4, r0, r6, *stub->entry());
416 __ bind(*stub->continuation());
417 }
418
419 if (compilation()->env()->dtrace_method_probes()) {
420 __ mov(c_rarg0, rthread);
421 __ mov_metadata(c_rarg1, method()->constant_encoding());
422 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
423 }
424
425 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
426 __ mov(r0, r19); // Restore the exception
427 }
428
429 // remove the activation and dispatch to the unwind handler
430 __ block_comment("remove_frame and dispatch to the unwind handler");
431 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
432 __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
433
434 // Emit the slow path assembly
435 if (stub != nullptr) {
436 stub->emit_code(this);
437 }
438
439 return offset;
440 }
441
442
443 int LIR_Assembler::emit_deopt_handler() {
444 // generate code for exception handler
445 address handler_base = __ start_a_stub(deopt_handler_size());
446 if (handler_base == nullptr) {
447 // not enough space left for the handler
448 bailout("deopt handler overflow");
449 return -1;
450 }
451
452 int offset = code_offset();
453
454 __ adr(lr, pc());
455 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
456 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
457 __ end_a_stub();
458
459 return offset;
460 }
461
462 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
463 _masm->code_section()->relocate(adr, relocInfo::poll_type);
464 int pc_offset = code_offset();
465 flush_debug_info(pc_offset);
466 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
467 if (info->exception_handlers() != nullptr) {
468 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
469 }
470 }
471
472 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
473 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
474
475 if (InlineTypeReturnedAsFields) {
476 // Check if we are returning an non-null inline type and load its fields into registers
477 ciType* return_type = compilation()->method()->return_type();
478 if (return_type->is_inlinetype()) {
479 ciInlineKlass* vk = return_type->as_inline_klass();
480 if (vk->can_be_returned_as_fields()) {
481 address unpack_handler = vk->unpack_handler();
482 assert(unpack_handler != nullptr, "must be");
483 __ far_call(RuntimeAddress(unpack_handler));
484 }
485 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) {
486 Label skip;
487 Label not_null;
488 __ cbnz(r0, not_null);
489 // Returned value is null, zero all return registers because they may belong to oop fields
490 __ mov(j_rarg1, zr);
491 __ mov(j_rarg2, zr);
492 __ mov(j_rarg3, zr);
493 __ mov(j_rarg4, zr);
494 __ mov(j_rarg5, zr);
495 __ mov(j_rarg6, zr);
496 __ mov(j_rarg7, zr);
497 __ b(skip);
498 __ bind(not_null);
499
500 // Check if we are returning an non-null inline type and load its fields into registers
501 __ test_oop_is_not_inline_type(r0, rscratch2, skip, /* can_be_null= */ false);
502
503 // Load fields from a buffered value with an inline class specific handler
504 __ load_klass(rscratch1 /*dst*/, r0 /*src*/);
505 __ ldr(rscratch1, Address(rscratch1, InstanceKlass::adr_inlineklass_fixed_block_offset()));
506 __ ldr(rscratch1, Address(rscratch1, InlineKlass::unpack_handler_offset()));
507 // Unpack handler can be null if inline type is not scalarizable in returns
508 __ cbz(rscratch1, skip);
509 __ blr(rscratch1);
510
511 __ bind(skip);
512 }
513 // At this point, r0 points to the value object (for interpreter or C1 caller).
514 // The fields of the object are copied into registers (for C2 caller).
515 }
516
517 // Pop the stack before the safepoint code
518 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
519
520 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
521 __ reserved_stack_check();
522 }
523
524 code_stub->set_safepoint_offset(__ offset());
525 __ relocate(relocInfo::poll_return_type);
526 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
527 __ ret(lr);
528 }
529
530 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
531 return (__ store_inline_type_fields_to_buf(vk, false));
532 }
533
534 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
535 guarantee(info != nullptr, "Shouldn't be null");
536 __ get_polling_page(rscratch1, relocInfo::poll_type);
537 add_debug_info_for_branch(info); // This isn't just debug info:
538 // it's the oop map
539 __ read_polling_page(rscratch1, relocInfo::poll_type);
540 return __ offset();
541 }
542
543
544 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
545 if (from_reg == r31_sp)
546 from_reg = sp;
547 if (to_reg == r31_sp)
548 to_reg = sp;
549 __ mov(to_reg, from_reg);
550 }
551
552 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
553
554
555 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
556 assert(src->is_constant(), "should not call otherwise");
557 assert(dest->is_register(), "should not call otherwise");
558 LIR_Const* c = src->as_constant_ptr();
559
560 switch (c->type()) {
561 case T_INT: {
562 assert(patch_code == lir_patch_none, "no patching handled here");
563 __ movw(dest->as_register(), c->as_jint());
564 break;
565 }
566
567 case T_ADDRESS: {
568 assert(patch_code == lir_patch_none, "no patching handled here");
569 __ mov(dest->as_register(), c->as_jint());
570 break;
571 }
572
573 case T_LONG: {
574 assert(patch_code == lir_patch_none, "no patching handled here");
575 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
576 break;
577 }
578
579 case T_OBJECT: {
580 if (patch_code != lir_patch_none) {
581 jobject2reg_with_patching(dest->as_register(), info);
582 } else {
583 jobject2reg(c->as_jobject(), dest->as_register());
584 }
585 break;
586 }
587
588 case T_METADATA: {
589 if (patch_code != lir_patch_none) {
590 klass2reg_with_patching(dest->as_register(), info);
591 } else {
592 __ mov_metadata(dest->as_register(), c->as_metadata());
593 }
594 break;
595 }
596
597 case T_FLOAT: {
598 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
599 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
600 } else {
601 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
602 __ ldrs(dest->as_float_reg(), Address(rscratch1));
603 }
604 break;
605 }
606
607 case T_DOUBLE: {
608 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
609 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
610 } else {
611 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
612 __ ldrd(dest->as_double_reg(), Address(rscratch1));
613 }
614 break;
615 }
616
617 default:
618 ShouldNotReachHere();
619 }
620 }
621
622 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
623 LIR_Const* c = src->as_constant_ptr();
624 switch (c->type()) {
625 case T_OBJECT:
626 {
627 if (! c->as_jobject())
628 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
629 else {
630 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
631 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
632 }
633 }
634 break;
635 case T_ADDRESS:
636 {
637 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
638 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
639 }
640 case T_INT:
641 case T_FLOAT:
642 {
643 Register reg = zr;
644 if (c->as_jint_bits() == 0)
645 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
646 else {
647 __ movw(rscratch1, c->as_jint_bits());
648 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
649 }
650 }
651 break;
652 case T_LONG:
653 case T_DOUBLE:
654 {
655 Register reg = zr;
656 if (c->as_jlong_bits() == 0)
657 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
658 lo_word_offset_in_bytes));
659 else {
660 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
661 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
662 lo_word_offset_in_bytes));
663 }
664 }
665 break;
666 default:
667 ShouldNotReachHere();
668 }
669 }
670
671 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
672 assert(src->is_constant(), "should not call otherwise");
673 LIR_Const* c = src->as_constant_ptr();
674 LIR_Address* to_addr = dest->as_address_ptr();
675
676 void (Assembler::* insn)(Register Rt, const Address &adr);
677
678 switch (type) {
679 case T_ADDRESS:
680 assert(c->as_jint() == 0, "should be");
681 insn = &Assembler::str;
682 break;
683 case T_LONG:
684 assert(c->as_jlong() == 0, "should be");
685 insn = &Assembler::str;
686 break;
687 case T_INT:
688 assert(c->as_jint() == 0, "should be");
689 insn = &Assembler::strw;
690 break;
691 case T_OBJECT:
692 case T_ARRAY:
693 // Non-null case is not handled on aarch64 but handled on x86
694 // FIXME: do we need to add it here?
695 assert(c->as_jobject() == nullptr, "should be");
696 if (UseCompressedOops && !wide) {
697 insn = &Assembler::strw;
698 } else {
699 insn = &Assembler::str;
700 }
701 break;
702 case T_CHAR:
703 case T_SHORT:
704 assert(c->as_jint() == 0, "should be");
705 insn = &Assembler::strh;
706 break;
707 case T_BOOLEAN:
708 case T_BYTE:
709 assert(c->as_jint() == 0, "should be");
710 insn = &Assembler::strb;
711 break;
712 default:
713 ShouldNotReachHere();
714 insn = &Assembler::str; // unreachable
715 }
716
717 if (info) add_debug_info_for_null_check_here(info);
718 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
719 }
720
721 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
722 assert(src->is_register(), "should not call otherwise");
723 assert(dest->is_register(), "should not call otherwise");
724
725 // move between cpu-registers
726 if (dest->is_single_cpu()) {
727 if (src->type() == T_LONG) {
728 // Can do LONG -> OBJECT
729 move_regs(src->as_register_lo(), dest->as_register());
730 return;
731 }
732 assert(src->is_single_cpu(), "must match");
733 if (src->type() == T_OBJECT) {
734 __ verify_oop(src->as_register());
735 }
736 move_regs(src->as_register(), dest->as_register());
737
738 } else if (dest->is_double_cpu()) {
739 if (is_reference_type(src->type())) {
740 // Surprising to me but we can see move of a long to t_object
741 __ verify_oop(src->as_register());
742 move_regs(src->as_register(), dest->as_register_lo());
743 return;
744 }
745 assert(src->is_double_cpu(), "must match");
746 Register f_lo = src->as_register_lo();
747 Register f_hi = src->as_register_hi();
748 Register t_lo = dest->as_register_lo();
749 Register t_hi = dest->as_register_hi();
750 assert(f_hi == f_lo, "must be same");
751 assert(t_hi == t_lo, "must be same");
752 move_regs(f_lo, t_lo);
753
754 } else if (dest->is_single_fpu()) {
755 __ fmovs(dest->as_float_reg(), src->as_float_reg());
756
757 } else if (dest->is_double_fpu()) {
758 __ fmovd(dest->as_double_reg(), src->as_double_reg());
759
760 } else {
761 ShouldNotReachHere();
762 }
763 }
764
765 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
766 precond(src->is_register() && dest->is_stack());
767
768 uint const c_sz32 = sizeof(uint32_t);
769 uint const c_sz64 = sizeof(uint64_t);
770
771 if (src->is_single_cpu()) {
772 int index = dest->single_stack_ix();
773 if (is_reference_type(type)) {
774 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
775 __ verify_oop(src->as_register());
776 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
777 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
778 } else {
779 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
780 }
781
782 } else if (src->is_double_cpu()) {
783 int index = dest->double_stack_ix();
784 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
785 __ str(src->as_register_lo(), dest_addr_LO);
786
787 } else if (src->is_single_fpu()) {
788 int index = dest->single_stack_ix();
789 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
790
791 } else if (src->is_double_fpu()) {
792 int index = dest->double_stack_ix();
793 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
794
795 } else {
796 ShouldNotReachHere();
797 }
798 }
799
800
801 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
802 LIR_Address* to_addr = dest->as_address_ptr();
803 PatchingStub* patch = nullptr;
804 Register compressed_src = rscratch1;
805
806 if (patch_code != lir_patch_none) {
807 deoptimize_trap(info);
808 return;
809 }
810
811 if (is_reference_type(type)) {
812 __ verify_oop(src->as_register());
813
814 if (UseCompressedOops && !wide) {
815 __ encode_heap_oop(compressed_src, src->as_register());
816 } else {
817 compressed_src = src->as_register();
818 }
819 }
820
821 int null_check_here = code_offset();
822 switch (type) {
823 case T_FLOAT: {
824 __ strs(src->as_float_reg(), as_Address(to_addr));
825 break;
826 }
827
828 case T_DOUBLE: {
829 __ strd(src->as_double_reg(), as_Address(to_addr));
830 break;
831 }
832
833 case T_ARRAY: // fall through
834 case T_OBJECT: // fall through
835 if (UseCompressedOops && !wide) {
836 __ strw(compressed_src, as_Address(to_addr, rscratch2));
837 } else {
838 __ str(compressed_src, as_Address(to_addr));
839 }
840 break;
841 case T_METADATA:
842 // We get here to store a method pointer to the stack to pass to
843 // a dtrace runtime call. This can't work on 64 bit with
844 // compressed klass ptrs: T_METADATA can be a compressed klass
845 // ptr or a 64 bit method pointer.
846 ShouldNotReachHere();
847 __ str(src->as_register(), as_Address(to_addr));
848 break;
849 case T_ADDRESS:
850 __ str(src->as_register(), as_Address(to_addr));
851 break;
852 case T_INT:
853 __ strw(src->as_register(), as_Address(to_addr));
854 break;
855
856 case T_LONG: {
857 __ str(src->as_register_lo(), as_Address_lo(to_addr));
858 break;
859 }
860
861 case T_BYTE: // fall through
862 case T_BOOLEAN: {
863 __ strb(src->as_register(), as_Address(to_addr));
864 break;
865 }
866
867 case T_CHAR: // fall through
868 case T_SHORT:
869 __ strh(src->as_register(), as_Address(to_addr));
870 break;
871
872 default:
873 ShouldNotReachHere();
874 }
875 if (info != nullptr) {
876 add_debug_info_for_null_check(null_check_here, info);
877 }
878 }
879
880
881 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
882 precond(src->is_stack() && dest->is_register());
883
884 uint const c_sz32 = sizeof(uint32_t);
885 uint const c_sz64 = sizeof(uint64_t);
886
887 if (dest->is_single_cpu()) {
888 int index = src->single_stack_ix();
889 if (is_reference_type(type)) {
890 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
891 __ verify_oop(dest->as_register());
892 } else if (type == T_METADATA || type == T_ADDRESS) {
893 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
894 } else {
895 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
896 }
897
898 } else if (dest->is_double_cpu()) {
899 int index = src->double_stack_ix();
900 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
901 __ ldr(dest->as_register_lo(), src_addr_LO);
902
903 } else if (dest->is_single_fpu()) {
904 int index = src->single_stack_ix();
905 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
906
907 } else if (dest->is_double_fpu()) {
908 int index = src->double_stack_ix();
909 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
910
911 } else {
912 ShouldNotReachHere();
913 }
914 }
915
916
917 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
918 address target = nullptr;
919 relocInfo::relocType reloc_type = relocInfo::none;
920
921 switch (patching_id(info)) {
922 case PatchingStub::access_field_id:
923 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
924 reloc_type = relocInfo::section_word_type;
925 break;
926 case PatchingStub::load_klass_id:
927 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
928 reloc_type = relocInfo::metadata_type;
929 break;
930 case PatchingStub::load_mirror_id:
931 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
932 reloc_type = relocInfo::oop_type;
933 break;
934 case PatchingStub::load_appendix_id:
935 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
936 reloc_type = relocInfo::oop_type;
937 break;
938 default: ShouldNotReachHere();
939 }
940
941 __ far_call(RuntimeAddress(target));
942 add_call_info_here(info);
943 }
944
945 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
946
947 LIR_Opr temp;
948 if (type == T_LONG || type == T_DOUBLE)
949 temp = FrameMap::rscratch1_long_opr;
950 else
951 temp = FrameMap::rscratch1_opr;
952
953 stack2reg(src, temp, src->type());
954 reg2stack(temp, dest, dest->type());
955 }
956
957
958 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
959 LIR_Address* addr = src->as_address_ptr();
960 LIR_Address* from_addr = src->as_address_ptr();
961
962 if (addr->base()->type() == T_OBJECT) {
963 __ verify_oop(addr->base()->as_pointer_register());
964 }
965
966 if (patch_code != lir_patch_none) {
967 deoptimize_trap(info);
968 return;
969 }
970
971 if (info != nullptr) {
972 add_debug_info_for_null_check_here(info);
973 }
974 int null_check_here = code_offset();
975 switch (type) {
976 case T_FLOAT: {
977 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
978 break;
979 }
980
981 case T_DOUBLE: {
982 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
983 break;
984 }
985
986 case T_ARRAY: // fall through
987 case T_OBJECT: // fall through
988 if (UseCompressedOops && !wide) {
989 __ ldrw(dest->as_register(), as_Address(from_addr));
990 } else {
991 __ ldr(dest->as_register(), as_Address(from_addr));
992 }
993 break;
994 case T_METADATA:
995 // We get here to store a method pointer to the stack to pass to
996 // a dtrace runtime call. This can't work on 64 bit with
997 // compressed klass ptrs: T_METADATA can be a compressed klass
998 // ptr or a 64 bit method pointer.
999 ShouldNotReachHere();
1000 __ ldr(dest->as_register(), as_Address(from_addr));
1001 break;
1002 case T_ADDRESS:
1003 __ ldr(dest->as_register(), as_Address(from_addr));
1004 break;
1005 case T_INT:
1006 __ ldrw(dest->as_register(), as_Address(from_addr));
1007 break;
1008
1009 case T_LONG: {
1010 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1011 break;
1012 }
1013
1014 case T_BYTE:
1015 __ ldrsb(dest->as_register(), as_Address(from_addr));
1016 break;
1017 case T_BOOLEAN: {
1018 __ ldrb(dest->as_register(), as_Address(from_addr));
1019 break;
1020 }
1021
1022 case T_CHAR:
1023 __ ldrh(dest->as_register(), as_Address(from_addr));
1024 break;
1025 case T_SHORT:
1026 __ ldrsh(dest->as_register(), as_Address(from_addr));
1027 break;
1028
1029 default:
1030 ShouldNotReachHere();
1031 }
1032
1033 if (is_reference_type(type)) {
1034 if (UseCompressedOops && !wide) {
1035 __ decode_heap_oop(dest->as_register());
1036 }
1037
1038 __ verify_oop(dest->as_register());
1039 }
1040 }
1041
1042 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
1043 assert(dst->is_cpu_register(), "must be");
1044 assert(dst->type() == src->type(), "must be");
1045
1046 if (src->is_cpu_register()) {
1047 reg2reg(src, dst);
1048 } else if (src->is_stack()) {
1049 stack2reg(src, dst, dst->type());
1050 } else if (src->is_constant()) {
1051 const2reg(src, dst, lir_patch_none, nullptr);
1052 } else {
1053 ShouldNotReachHere();
1054 }
1055 }
1056
1057 int LIR_Assembler::array_element_size(BasicType type) const {
1058 int elem_size = type2aelembytes(type);
1059 return exact_log2(elem_size);
1060 }
1061
1062
1063 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1064 switch (op->code()) {
1065 case lir_idiv:
1066 case lir_irem:
1067 arithmetic_idiv(op->code(),
1068 op->in_opr1(),
1069 op->in_opr2(),
1070 op->in_opr3(),
1071 op->result_opr(),
1072 op->info());
1073 break;
1074 case lir_fmad:
1075 __ fmaddd(op->result_opr()->as_double_reg(),
1076 op->in_opr1()->as_double_reg(),
1077 op->in_opr2()->as_double_reg(),
1078 op->in_opr3()->as_double_reg());
1079 break;
1080 case lir_fmaf:
1081 __ fmadds(op->result_opr()->as_float_reg(),
1082 op->in_opr1()->as_float_reg(),
1083 op->in_opr2()->as_float_reg(),
1084 op->in_opr3()->as_float_reg());
1085 break;
1086 default: ShouldNotReachHere(); break;
1087 }
1088 }
1089
1090 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1091 #ifdef ASSERT
1092 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1093 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1094 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1095 #endif
1096
1097 if (op->cond() == lir_cond_always) {
1098 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1099 __ b(*(op->label()));
1100 } else {
1101 Assembler::Condition acond;
1102 if (op->code() == lir_cond_float_branch) {
1103 bool is_unordered = (op->ublock() == op->block());
1104 // Assembler::EQ does not permit unordered branches, so we add
1105 // another branch here. Likewise, Assembler::NE does not permit
1106 // ordered branches.
1107 if ((is_unordered && op->cond() == lir_cond_equal)
1108 || (!is_unordered && op->cond() == lir_cond_notEqual))
1109 __ br(Assembler::VS, *(op->ublock()->label()));
1110 switch(op->cond()) {
1111 case lir_cond_equal: acond = Assembler::EQ; break;
1112 case lir_cond_notEqual: acond = Assembler::NE; break;
1113 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1114 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1115 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1116 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1117 default: ShouldNotReachHere();
1118 acond = Assembler::EQ; // unreachable
1119 }
1120 } else {
1121 switch (op->cond()) {
1122 case lir_cond_equal: acond = Assembler::EQ; break;
1123 case lir_cond_notEqual: acond = Assembler::NE; break;
1124 case lir_cond_less: acond = Assembler::LT; break;
1125 case lir_cond_lessEqual: acond = Assembler::LE; break;
1126 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1127 case lir_cond_greater: acond = Assembler::GT; break;
1128 case lir_cond_belowEqual: acond = Assembler::LS; break;
1129 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1130 default: ShouldNotReachHere();
1131 acond = Assembler::EQ; // unreachable
1132 }
1133 }
1134 __ br(acond,*(op->label()));
1135 }
1136 }
1137
1138
1139
1140 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1141 LIR_Opr src = op->in_opr();
1142 LIR_Opr dest = op->result_opr();
1143
1144 switch (op->bytecode()) {
1145 case Bytecodes::_i2f:
1146 {
1147 __ scvtfws(dest->as_float_reg(), src->as_register());
1148 break;
1149 }
1150 case Bytecodes::_i2d:
1151 {
1152 __ scvtfwd(dest->as_double_reg(), src->as_register());
1153 break;
1154 }
1155 case Bytecodes::_l2d:
1156 {
1157 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1158 break;
1159 }
1160 case Bytecodes::_l2f:
1161 {
1162 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1163 break;
1164 }
1165 case Bytecodes::_f2d:
1166 {
1167 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1168 break;
1169 }
1170 case Bytecodes::_d2f:
1171 {
1172 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1173 break;
1174 }
1175 case Bytecodes::_i2c:
1176 {
1177 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1178 break;
1179 }
1180 case Bytecodes::_i2l:
1181 {
1182 __ sxtw(dest->as_register_lo(), src->as_register());
1183 break;
1184 }
1185 case Bytecodes::_i2s:
1186 {
1187 __ sxth(dest->as_register(), src->as_register());
1188 break;
1189 }
1190 case Bytecodes::_i2b:
1191 {
1192 __ sxtb(dest->as_register(), src->as_register());
1193 break;
1194 }
1195 case Bytecodes::_l2i:
1196 {
1197 _masm->block_comment("FIXME: This could be a no-op");
1198 __ uxtw(dest->as_register(), src->as_register_lo());
1199 break;
1200 }
1201 case Bytecodes::_d2l:
1202 {
1203 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1204 break;
1205 }
1206 case Bytecodes::_f2i:
1207 {
1208 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1209 break;
1210 }
1211 case Bytecodes::_f2l:
1212 {
1213 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1214 break;
1215 }
1216 case Bytecodes::_d2i:
1217 {
1218 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1219 break;
1220 }
1221 default: ShouldNotReachHere();
1222 }
1223 }
1224
1225 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1226 if (op->init_check()) {
1227 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1228 __ ldarb(rscratch1, rscratch1);
1229 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1230 add_debug_info_for_null_check_here(op->stub()->info());
1231 __ br(Assembler::NE, *op->stub()->entry());
1232 }
1233 __ allocate_object(op->obj()->as_register(),
1234 op->tmp1()->as_register(),
1235 op->tmp2()->as_register(),
1236 op->header_size(),
1237 op->object_size(),
1238 op->klass()->as_register(),
1239 *op->stub()->entry());
1240 __ bind(*op->stub()->continuation());
1241 }
1242
1243 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1244 Register len = op->len()->as_register();
1245 __ uxtw(len, len);
1246
1247 if (UseSlowPath || op->always_slow_path() ||
1248 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1249 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1250 __ b(*op->stub()->entry());
1251 } else {
1252 Register tmp1 = op->tmp1()->as_register();
1253 Register tmp2 = op->tmp2()->as_register();
1254 Register tmp3 = op->tmp3()->as_register();
1255 if (len == tmp1) {
1256 tmp1 = tmp3;
1257 } else if (len == tmp2) {
1258 tmp2 = tmp3;
1259 } else if (len == tmp3) {
1260 // everything is ok
1261 } else {
1262 __ mov(tmp3, len);
1263 }
1264 __ allocate_array(op->obj()->as_register(),
1265 len,
1266 tmp1,
1267 tmp2,
1268 arrayOopDesc::base_offset_in_bytes(op->type()),
1269 array_element_size(op->type()),
1270 op->klass()->as_register(),
1271 *op->stub()->entry(),
1272 op->zero_array());
1273 }
1274 __ bind(*op->stub()->continuation());
1275 }
1276
1277 void LIR_Assembler::type_profile_helper(Register mdo,
1278 ciMethodData *md, ciProfileData *data,
1279 Register recv, Label* update_done) {
1280
1281 // Given a profile data offset, generate an Address which points to
1282 // the corresponding slot in mdo->data().
1283 // Clobbers rscratch2.
1284 auto slot_at = [=](ByteSize offset) -> Address {
1285 return __ form_address(rscratch2, mdo,
1286 md->byte_offset_of_slot(data, offset),
1287 LogBytesPerWord);
1288 };
1289
1290 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1291 Label next_test;
1292 // See if the receiver is receiver[n].
1293 __ ldr(rscratch1, slot_at(ReceiverTypeData::receiver_offset(i)));
1294 __ cmp(recv, rscratch1);
1295 __ br(Assembler::NE, next_test);
1296 __ addptr(slot_at(ReceiverTypeData::receiver_count_offset(i)),
1297 DataLayout::counter_increment);
1298 __ b(*update_done);
1299 __ bind(next_test);
1300 }
1301
1302 // Didn't find receiver; find next empty slot and fill it in
1303 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1304 Label next_test;
1305 Address recv_addr(slot_at(ReceiverTypeData::receiver_offset(i)));
1306 __ ldr(rscratch1, recv_addr);
1307 __ cbnz(rscratch1, next_test);
1308 __ str(recv, recv_addr);
1309 __ mov(rscratch1, DataLayout::counter_increment);
1310 __ str(rscratch1, slot_at(ReceiverTypeData::receiver_count_offset(i)));
1311 __ b(*update_done);
1312 __ bind(next_test);
1313 }
1314 }
1315
1316 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1317 // we always need a stub for the failure case.
1318 CodeStub* stub = op->stub();
1319 Register obj = op->object()->as_register();
1320 Register k_RInfo = op->tmp1()->as_register();
1321 Register klass_RInfo = op->tmp2()->as_register();
1322 Register dst = op->result_opr()->as_register();
1323 ciKlass* k = op->klass();
1324 Register Rtmp1 = noreg;
1325
1326 // check if it needs to be profiled
1327 ciMethodData* md;
1328 ciProfileData* data;
1329
1330 const bool should_profile = op->should_profile();
1331
1332 if (should_profile) {
1333 ciMethod* method = op->profiled_method();
1334 assert(method != nullptr, "Should have method");
1335 int bci = op->profiled_bci();
1336 md = method->method_data_or_null();
1337 assert(md != nullptr, "Sanity");
1338 data = md->bci_to_data(bci);
1339 assert(data != nullptr, "need data for type check");
1340 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1341 }
1342 Label* success_target = success;
1343 Label* failure_target = failure;
1344
1345 if (obj == k_RInfo) {
1346 k_RInfo = dst;
1347 } else if (obj == klass_RInfo) {
1348 klass_RInfo = dst;
1349 }
1350 if (k->is_loaded() && !UseCompressedClassPointers) {
1351 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1352 } else {
1353 Rtmp1 = op->tmp3()->as_register();
1354 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1355 }
1356
1357 assert_different_registers(obj, k_RInfo, klass_RInfo);
1358
1359 if (op->need_null_check()) {
1360 if (should_profile) {
1361 Register mdo = klass_RInfo;
1362 __ mov_metadata(mdo, md->constant_encoding());
1363 Label not_null;
1364 __ cbnz(obj, not_null);
1365 // Object is null; update MDO and exit
1366 Address data_addr
1367 = __ form_address(rscratch2, mdo,
1368 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1369 0);
1370 __ ldrb(rscratch1, data_addr);
1371 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1372 __ strb(rscratch1, data_addr);
1373 __ b(*obj_is_null);
1374 __ bind(not_null);
1375
1376 Label update_done;
1377 Register recv = k_RInfo;
1378 __ load_klass(recv, obj);
1379 type_profile_helper(mdo, md, data, recv, &update_done);
1380 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1381 __ addptr(counter_addr, DataLayout::counter_increment);
1382
1383 __ bind(update_done);
1384 } else {
1385 __ cbz(obj, *obj_is_null);
1386 }
1387 }
1388
1389 if (!k->is_loaded()) {
1390 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1391 } else {
1392 __ mov_metadata(k_RInfo, k->constant_encoding());
1393 }
1394 __ verify_oop(obj);
1395
1396 if (op->fast_check()) {
1397 // get object class
1398 // not a safepoint as obj null check happens earlier
1399 __ load_klass(rscratch1, obj);
1400 __ cmp( rscratch1, k_RInfo);
1401
1402 __ br(Assembler::NE, *failure_target);
1403 // successful cast, fall through to profile or jump
1404 } else {
1405 // get object class
1406 // not a safepoint as obj null check happens earlier
1407 __ load_klass(klass_RInfo, obj);
1408 if (k->is_loaded()) {
1409 // See if we get an immediate positive hit
1410 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1411 __ cmp(k_RInfo, rscratch1);
1412 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1413 __ br(Assembler::NE, *failure_target);
1414 // successful cast, fall through to profile or jump
1415 } else {
1416 // See if we get an immediate positive hit
1417 __ br(Assembler::EQ, *success_target);
1418 // check for self
1419 __ cmp(klass_RInfo, k_RInfo);
1420 __ br(Assembler::EQ, *success_target);
1421
1422 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1423 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1424 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1425 // result is a boolean
1426 __ cbzw(klass_RInfo, *failure_target);
1427 // successful cast, fall through to profile or jump
1428 }
1429 } else {
1430 // perform the fast part of the checking logic
1431 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1432 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1433 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1434 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1435 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1436 // result is a boolean
1437 __ cbz(k_RInfo, *failure_target);
1438 // successful cast, fall through to profile or jump
1439 }
1440 }
1441 __ b(*success);
1442 }
1443
1444
1445 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1446 const bool should_profile = op->should_profile();
1447
1448 LIR_Code code = op->code();
1449 if (code == lir_store_check) {
1450 Register value = op->object()->as_register();
1451 Register array = op->array()->as_register();
1452 Register k_RInfo = op->tmp1()->as_register();
1453 Register klass_RInfo = op->tmp2()->as_register();
1454 Register Rtmp1 = op->tmp3()->as_register();
1455
1456 CodeStub* stub = op->stub();
1457
1458 // check if it needs to be profiled
1459 ciMethodData* md;
1460 ciProfileData* data;
1461
1462 if (should_profile) {
1463 ciMethod* method = op->profiled_method();
1464 assert(method != nullptr, "Should have method");
1465 int bci = op->profiled_bci();
1466 md = method->method_data_or_null();
1467 assert(md != nullptr, "Sanity");
1468 data = md->bci_to_data(bci);
1469 assert(data != nullptr, "need data for type check");
1470 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1471 }
1472 Label done;
1473 Label* success_target = &done;
1474 Label* failure_target = stub->entry();
1475
1476 if (should_profile) {
1477 Label not_null;
1478 Register mdo = klass_RInfo;
1479 __ mov_metadata(mdo, md->constant_encoding());
1480 __ cbnz(value, not_null);
1481 // Object is null; update MDO and exit
1482 Address data_addr
1483 = __ form_address(rscratch2, mdo,
1484 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1485 __ ldrb(rscratch1, data_addr);
1486 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1487 __ strb(rscratch1, data_addr);
1488 __ b(done);
1489 __ bind(not_null);
1490
1491 Label update_done;
1492 Register recv = k_RInfo;
1493 __ load_klass(recv, value);
1494 type_profile_helper(mdo, md, data, recv, &update_done);
1495 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1496 __ addptr(counter_addr, DataLayout::counter_increment);
1497 __ bind(update_done);
1498 } else {
1499 __ cbz(value, done);
1500 }
1501
1502 add_debug_info_for_null_check_here(op->info_for_exception());
1503 __ load_klass(k_RInfo, array);
1504 __ load_klass(klass_RInfo, value);
1505
1506 // get instance klass (it's already uncompressed)
1507 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1508 // perform the fast part of the checking logic
1509 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1510 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1511 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1512 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1513 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1514 // result is a boolean
1515 __ cbzw(k_RInfo, *failure_target);
1516 // fall through to the success case
1517
1518 __ bind(done);
1519 } else if (code == lir_checkcast) {
1520 Register obj = op->object()->as_register();
1521 Register dst = op->result_opr()->as_register();
1522 Label success;
1523 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1524 __ bind(success);
1525 if (dst != obj) {
1526 __ mov(dst, obj);
1527 }
1528 } else if (code == lir_instanceof) {
1529 Register obj = op->object()->as_register();
1530 Register dst = op->result_opr()->as_register();
1531 Label success, failure, done;
1532 emit_typecheck_helper(op, &success, &failure, &failure);
1533 __ bind(failure);
1534 __ mov(dst, zr);
1535 __ b(done);
1536 __ bind(success);
1537 __ mov(dst, 1);
1538 __ bind(done);
1539 } else {
1540 ShouldNotReachHere();
1541 }
1542 }
1543
1544 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1545 // We are loading/storing from/to an array that *may* be a flat array (the
1546 // declared type is Object[], abstract[], interface[] or VT.ref[]).
1547 // If this array is a flat array, take the slow path.
1548 __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1549 if (!op->value()->is_illegal()) {
1550 // The array is not a flat array, but it might be null-free. If we are storing
1551 // a null into a null-free array, take the slow path (which will throw NPE).
1552 Label skip;
1553 __ cbnz(op->value()->as_register(), skip);
1554 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1555 __ bind(skip);
1556 }
1557 }
1558
1559 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1560 // We are storing into an array that *may* be null-free (the declared type is
1561 // Object[], abstract[], interface[] or VT.ref[]).
1562 Label test_mark_word;
1563 Register tmp = op->tmp()->as_register();
1564 __ ldr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
1565 __ tst(tmp, markWord::unlocked_value);
1566 __ br(Assembler::NE, test_mark_word);
1567 __ load_prototype_header(tmp, op->array()->as_register());
1568 __ bind(test_mark_word);
1569 __ tst(tmp, markWord::null_free_array_bit_in_place);
1570 }
1571
1572 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1573 Label L_oops_equal;
1574 Label L_oops_not_equal;
1575 Label L_end;
1576
1577 Register left = op->left()->as_register();
1578 Register right = op->right()->as_register();
1579
1580 __ cmp(left, right);
1581 __ br(Assembler::EQ, L_oops_equal);
1582
1583 // (1) Null check -- if one of the operands is null, the other must not be null (because
1584 // the two references are not equal), so they are not substitutable,
1585 // FIXME: do null check only if the operand is nullable
1586 {
1587 __ cbz(left, L_oops_not_equal);
1588 __ cbz(right, L_oops_not_equal);
1589 }
1590
1591 ciKlass* left_klass = op->left_klass();
1592 ciKlass* right_klass = op->right_klass();
1593
1594 // (2) Inline type check -- if either of the operands is not a inline type,
1595 // they are not substitutable. We do this only if we are not sure that the
1596 // operands are inline type
1597 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node.
1598 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
1599 Register tmp1 = op->tmp1()->as_register();
1600 __ mov(tmp1, markWord::inline_type_pattern);
1601 __ ldr(rscratch1, Address(left, oopDesc::mark_offset_in_bytes()));
1602 __ andr(tmp1, tmp1, rscratch1);
1603 __ ldr(rscratch1, Address(right, oopDesc::mark_offset_in_bytes()));
1604 __ andr(tmp1, tmp1, rscratch1);
1605 __ cmp(tmp1, (u1)markWord::inline_type_pattern);
1606 __ br(Assembler::NE, L_oops_not_equal);
1607 }
1608
1609 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
1610 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) {
1611 // No need to load klass -- the operands are statically known to be the same inline klass.
1612 __ b(*op->stub()->entry());
1613 } else {
1614 Register left_klass_op = op->left_klass_op()->as_register();
1615 Register right_klass_op = op->right_klass_op()->as_register();
1616
1617 if (UseCompressedClassPointers) {
1618 __ ldrw(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1619 __ ldrw(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1620 __ cmpw(left_klass_op, right_klass_op);
1621 } else {
1622 __ ldr(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1623 __ ldr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1624 __ cmp(left_klass_op, right_klass_op);
1625 }
1626
1627 __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check
1628 // fall through to L_oops_not_equal
1629 }
1630
1631 __ bind(L_oops_not_equal);
1632 move(op->not_equal_result(), op->result_opr());
1633 __ b(L_end);
1634
1635 __ bind(L_oops_equal);
1636 move(op->equal_result(), op->result_opr());
1637 __ b(L_end);
1638
1639 // We've returned from the stub. R0 contains 0x0 IFF the two
1640 // operands are not substitutable. (Don't compare against 0x1 in case the
1641 // C compiler is naughty)
1642 __ bind(*op->stub()->continuation());
1643 __ cbz(r0, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1644 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
1645 // fall-through
1646 __ bind(L_end);
1647 }
1648
1649
1650 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1651 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1652 __ cset(rscratch1, Assembler::NE);
1653 __ membar(__ AnyAny);
1654 }
1655
1656 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1657 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1658 __ cset(rscratch1, Assembler::NE);
1659 __ membar(__ AnyAny);
1660 }
1661
1662
1663 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1664 Register addr;
1665 if (op->addr()->is_register()) {
1666 addr = as_reg(op->addr());
1667 } else {
1668 assert(op->addr()->is_address(), "what else?");
1669 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1670 assert(addr_ptr->disp() == 0, "need 0 disp");
1671 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1672 addr = as_reg(addr_ptr->base());
1673 }
1674 Register newval = as_reg(op->new_value());
1675 Register cmpval = as_reg(op->cmp_value());
1676
1677 if (op->code() == lir_cas_obj) {
1678 if (UseCompressedOops) {
1679 Register t1 = op->tmp1()->as_register();
1680 assert(op->tmp1()->is_valid(), "must be");
1681 __ encode_heap_oop(t1, cmpval);
1682 cmpval = t1;
1683 __ encode_heap_oop(rscratch2, newval);
1684 newval = rscratch2;
1685 casw(addr, newval, cmpval);
1686 } else {
1687 casl(addr, newval, cmpval);
1688 }
1689 } else if (op->code() == lir_cas_int) {
1690 casw(addr, newval, cmpval);
1691 } else {
1692 casl(addr, newval, cmpval);
1693 }
1694 }
1695
1696
1697 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1698 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1699 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1700
1701 Assembler::Condition acond, ncond;
1702 switch (condition) {
1703 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1704 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1705 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1706 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1707 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1708 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1709 case lir_cond_belowEqual:
1710 case lir_cond_aboveEqual:
1711 default: ShouldNotReachHere();
1712 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1713 }
1714
1715 assert(result->is_single_cpu() || result->is_double_cpu(),
1716 "expect single register for result");
1717 if (opr1->is_constant() && opr2->is_constant()
1718 && opr1->type() == T_INT && opr2->type() == T_INT) {
1719 jint val1 = opr1->as_jint();
1720 jint val2 = opr2->as_jint();
1721 if (val1 == 0 && val2 == 1) {
1722 __ cset(result->as_register(), ncond);
1723 return;
1724 } else if (val1 == 1 && val2 == 0) {
1725 __ cset(result->as_register(), acond);
1726 return;
1727 }
1728 }
1729
1730 if (opr1->is_constant() && opr2->is_constant()
1731 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1732 jlong val1 = opr1->as_jlong();
1733 jlong val2 = opr2->as_jlong();
1734 if (val1 == 0 && val2 == 1) {
1735 __ cset(result->as_register_lo(), ncond);
1736 return;
1737 } else if (val1 == 1 && val2 == 0) {
1738 __ cset(result->as_register_lo(), acond);
1739 return;
1740 }
1741 }
1742
1743 if (opr1->is_stack()) {
1744 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1745 opr1 = FrameMap::rscratch1_opr;
1746 } else if (opr1->is_constant()) {
1747 LIR_Opr tmp
1748 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1749 const2reg(opr1, tmp, lir_patch_none, nullptr);
1750 opr1 = tmp;
1751 }
1752
1753 if (opr2->is_stack()) {
1754 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1755 opr2 = FrameMap::rscratch2_opr;
1756 } else if (opr2->is_constant()) {
1757 LIR_Opr tmp
1758 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1759 const2reg(opr2, tmp, lir_patch_none, nullptr);
1760 opr2 = tmp;
1761 }
1762
1763 if (result->type() == T_LONG)
1764 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1765 else
1766 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1767 }
1768
1769 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1770 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1771
1772 if (left->is_single_cpu()) {
1773 Register lreg = left->as_register();
1774 Register dreg = as_reg(dest);
1775
1776 if (right->is_single_cpu()) {
1777 // cpu register - cpu register
1778
1779 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1780 "should be");
1781 Register rreg = right->as_register();
1782 switch (code) {
1783 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1784 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1785 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1786 default: ShouldNotReachHere();
1787 }
1788
1789 } else if (right->is_double_cpu()) {
1790 Register rreg = right->as_register_lo();
1791 // single_cpu + double_cpu: can happen with obj+long
1792 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1793 switch (code) {
1794 case lir_add: __ add(dreg, lreg, rreg); break;
1795 case lir_sub: __ sub(dreg, lreg, rreg); break;
1796 default: ShouldNotReachHere();
1797 }
1798 } else if (right->is_constant()) {
1799 // cpu register - constant
1800 jlong c;
1801
1802 // FIXME. This is fugly: we really need to factor all this logic.
1803 switch(right->type()) {
1804 case T_LONG:
1805 c = right->as_constant_ptr()->as_jlong();
1806 break;
1807 case T_INT:
1808 case T_ADDRESS:
1809 c = right->as_constant_ptr()->as_jint();
1810 break;
1811 default:
1812 ShouldNotReachHere();
1813 c = 0; // unreachable
1814 break;
1815 }
1816
1817 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1818 if (c == 0 && dreg == lreg) {
1819 COMMENT("effective nop elided");
1820 return;
1821 }
1822 switch(left->type()) {
1823 case T_INT:
1824 switch (code) {
1825 case lir_add: __ addw(dreg, lreg, c); break;
1826 case lir_sub: __ subw(dreg, lreg, c); break;
1827 default: ShouldNotReachHere();
1828 }
1829 break;
1830 case T_OBJECT:
1831 case T_ADDRESS:
1832 switch (code) {
1833 case lir_add: __ add(dreg, lreg, c); break;
1834 case lir_sub: __ sub(dreg, lreg, c); break;
1835 default: ShouldNotReachHere();
1836 }
1837 break;
1838 default:
1839 ShouldNotReachHere();
1840 }
1841 } else {
1842 ShouldNotReachHere();
1843 }
1844
1845 } else if (left->is_double_cpu()) {
1846 Register lreg_lo = left->as_register_lo();
1847
1848 if (right->is_double_cpu()) {
1849 // cpu register - cpu register
1850 Register rreg_lo = right->as_register_lo();
1851 switch (code) {
1852 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1853 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1854 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1855 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1856 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1857 default:
1858 ShouldNotReachHere();
1859 }
1860
1861 } else if (right->is_constant()) {
1862 jlong c = right->as_constant_ptr()->as_jlong();
1863 Register dreg = as_reg(dest);
1864 switch (code) {
1865 case lir_add:
1866 case lir_sub:
1867 if (c == 0 && dreg == lreg_lo) {
1868 COMMENT("effective nop elided");
1869 return;
1870 }
1871 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1872 break;
1873 case lir_div:
1874 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1875 if (c == 1) {
1876 // move lreg_lo to dreg if divisor is 1
1877 __ mov(dreg, lreg_lo);
1878 } else {
1879 unsigned int shift = log2i_exact(c);
1880 // use rscratch1 as intermediate result register
1881 __ asr(rscratch1, lreg_lo, 63);
1882 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1883 __ asr(dreg, rscratch1, shift);
1884 }
1885 break;
1886 case lir_rem:
1887 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1888 if (c == 1) {
1889 // move 0 to dreg if divisor is 1
1890 __ mov(dreg, zr);
1891 } else {
1892 // use rscratch1 as intermediate result register
1893 __ negs(rscratch1, lreg_lo);
1894 __ andr(dreg, lreg_lo, c - 1);
1895 __ andr(rscratch1, rscratch1, c - 1);
1896 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1897 }
1898 break;
1899 default:
1900 ShouldNotReachHere();
1901 }
1902 } else {
1903 ShouldNotReachHere();
1904 }
1905 } else if (left->is_single_fpu()) {
1906 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1907 switch (code) {
1908 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1909 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1910 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1911 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1912 default:
1913 ShouldNotReachHere();
1914 }
1915 } else if (left->is_double_fpu()) {
1916 if (right->is_double_fpu()) {
1917 // fpu register - fpu register
1918 switch (code) {
1919 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1920 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1921 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1922 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1923 default:
1924 ShouldNotReachHere();
1925 }
1926 } else {
1927 if (right->is_constant()) {
1928 ShouldNotReachHere();
1929 }
1930 ShouldNotReachHere();
1931 }
1932 } else if (left->is_single_stack() || left->is_address()) {
1933 assert(left == dest, "left and dest must be equal");
1934 ShouldNotReachHere();
1935 } else {
1936 ShouldNotReachHere();
1937 }
1938 }
1939
1940 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1941 switch(code) {
1942 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1943 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1944 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1945 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1946 default : ShouldNotReachHere();
1947 }
1948 }
1949
1950 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1951
1952 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1953 Register Rleft = left->is_single_cpu() ? left->as_register() :
1954 left->as_register_lo();
1955 if (dst->is_single_cpu()) {
1956 Register Rdst = dst->as_register();
1957 if (right->is_constant()) {
1958 switch (code) {
1959 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1960 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1961 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1962 default: ShouldNotReachHere(); break;
1963 }
1964 } else {
1965 Register Rright = right->is_single_cpu() ? right->as_register() :
1966 right->as_register_lo();
1967 switch (code) {
1968 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1969 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1970 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1971 default: ShouldNotReachHere(); break;
1972 }
1973 }
1974 } else {
1975 Register Rdst = dst->as_register_lo();
1976 if (right->is_constant()) {
1977 switch (code) {
1978 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1979 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1980 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1981 default: ShouldNotReachHere(); break;
1982 }
1983 } else {
1984 Register Rright = right->is_single_cpu() ? right->as_register() :
1985 right->as_register_lo();
1986 switch (code) {
1987 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1988 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1989 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1990 default: ShouldNotReachHere(); break;
1991 }
1992 }
1993 }
1994 }
1995
1996
1997
1998 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1999
2000 // opcode check
2001 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
2002 bool is_irem = (code == lir_irem);
2003
2004 // operand check
2005 assert(left->is_single_cpu(), "left must be register");
2006 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2007 assert(result->is_single_cpu(), "result must be register");
2008 Register lreg = left->as_register();
2009 Register dreg = result->as_register();
2010
2011 // power-of-2 constant check and codegen
2012 if (right->is_constant()) {
2013 int c = right->as_constant_ptr()->as_jint();
2014 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
2015 if (is_irem) {
2016 if (c == 1) {
2017 // move 0 to dreg if divisor is 1
2018 __ movw(dreg, zr);
2019 } else {
2020 // use rscratch1 as intermediate result register
2021 __ negsw(rscratch1, lreg);
2022 __ andw(dreg, lreg, c - 1);
2023 __ andw(rscratch1, rscratch1, c - 1);
2024 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
2025 }
2026 } else {
2027 if (c == 1) {
2028 // move lreg to dreg if divisor is 1
2029 __ movw(dreg, lreg);
2030 } else {
2031 unsigned int shift = exact_log2(c);
2032 // use rscratch1 as intermediate result register
2033 __ asrw(rscratch1, lreg, 31);
2034 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
2035 __ asrw(dreg, rscratch1, shift);
2036 }
2037 }
2038 } else {
2039 Register rreg = right->as_register();
2040 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
2041 }
2042 }
2043
2044
2045 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2046 if (opr1->is_constant() && opr2->is_single_cpu()) {
2047 // tableswitch
2048 Register reg = as_reg(opr2);
2049 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
2050 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
2051 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
2052 Register reg1 = as_reg(opr1);
2053 if (opr2->is_single_cpu()) {
2054 // cpu register - cpu register
2055 Register reg2 = opr2->as_register();
2056 if (is_reference_type(opr1->type())) {
2057 __ cmpoop(reg1, reg2);
2058 } else {
2059 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2060 __ cmpw(reg1, reg2);
2061 }
2062 return;
2063 }
2064 if (opr2->is_double_cpu()) {
2065 // cpu register - cpu register
2066 Register reg2 = opr2->as_register_lo();
2067 __ cmp(reg1, reg2);
2068 return;
2069 }
2070
2071 if (opr2->is_constant()) {
2072 bool is_32bit = false; // width of register operand
2073 jlong imm;
2074
2075 switch(opr2->type()) {
2076 case T_INT:
2077 imm = opr2->as_constant_ptr()->as_jint();
2078 is_32bit = true;
2079 break;
2080 case T_LONG:
2081 imm = opr2->as_constant_ptr()->as_jlong();
2082 break;
2083 case T_ADDRESS:
2084 imm = opr2->as_constant_ptr()->as_jint();
2085 break;
2086 case T_METADATA:
2087 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
2088 break;
2089 case T_OBJECT:
2090 case T_ARRAY:
2091 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
2092 __ cmpoop(reg1, rscratch1);
2093 return;
2094 default:
2095 ShouldNotReachHere();
2096 imm = 0; // unreachable
2097 break;
2098 }
2099
2100 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
2101 if (is_32bit)
2102 __ cmpw(reg1, imm);
2103 else
2104 __ subs(zr, reg1, imm);
2105 return;
2106 } else {
2107 __ mov(rscratch1, imm);
2108 if (is_32bit)
2109 __ cmpw(reg1, rscratch1);
2110 else
2111 __ cmp(reg1, rscratch1);
2112 return;
2113 }
2114 } else
2115 ShouldNotReachHere();
2116 } else if (opr1->is_single_fpu()) {
2117 FloatRegister reg1 = opr1->as_float_reg();
2118 assert(opr2->is_single_fpu(), "expect single float register");
2119 FloatRegister reg2 = opr2->as_float_reg();
2120 __ fcmps(reg1, reg2);
2121 } else if (opr1->is_double_fpu()) {
2122 FloatRegister reg1 = opr1->as_double_reg();
2123 assert(opr2->is_double_fpu(), "expect double float register");
2124 FloatRegister reg2 = opr2->as_double_reg();
2125 __ fcmpd(reg1, reg2);
2126 } else {
2127 ShouldNotReachHere();
2128 }
2129 }
2130
2131 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2132 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2133 bool is_unordered_less = (code == lir_ucmp_fd2i);
2134 if (left->is_single_fpu()) {
2135 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2136 } else if (left->is_double_fpu()) {
2137 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2138 } else {
2139 ShouldNotReachHere();
2140 }
2141 } else if (code == lir_cmp_l2i) {
2142 Label done;
2143 __ cmp(left->as_register_lo(), right->as_register_lo());
2144 __ mov(dst->as_register(), (uint64_t)-1L);
2145 __ br(Assembler::LT, done);
2146 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2147 __ bind(done);
2148 } else {
2149 ShouldNotReachHere();
2150 }
2151 }
2152
2153
2154 void LIR_Assembler::align_call(LIR_Code code) { }
2155
2156
2157 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2158 address call = __ trampoline_call(Address(op->addr(), rtype));
2159 if (call == nullptr) {
2160 bailout("trampoline stub overflow");
2161 return;
2162 }
2163 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2164 __ post_call_nop();
2165 }
2166
2167
2168 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2169 address call = __ ic_call(op->addr());
2170 if (call == nullptr) {
2171 bailout("trampoline stub overflow");
2172 return;
2173 }
2174 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2175 __ post_call_nop();
2176 }
2177
2178 void LIR_Assembler::emit_static_call_stub() {
2179 address call_pc = __ pc();
2180 address stub = __ start_a_stub(call_stub_size());
2181 if (stub == nullptr) {
2182 bailout("static call stub overflow");
2183 return;
2184 }
2185
2186 int start = __ offset();
2187
2188 __ relocate(static_stub_Relocation::spec(call_pc));
2189 __ emit_static_call_stub();
2190
2191 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2192 <= call_stub_size(), "stub too big");
2193 __ end_a_stub();
2194 }
2195
2196
2197 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2198 assert(exceptionOop->as_register() == r0, "must match");
2199 assert(exceptionPC->as_register() == r3, "must match");
2200
2201 // exception object is not added to oop map by LinearScan
2202 // (LinearScan assumes that no oops are in fixed registers)
2203 info->add_register_oop(exceptionOop);
2204 StubId unwind_id;
2205
2206 // get current pc information
2207 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2208 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2209 // As no instructions have been generated yet for this LIR node it's
2210 // possible that an oop map already exists for the current offset.
2211 // In that case insert an dummy NOP here to ensure all oop map PCs
2212 // are unique. See JDK-8237483.
2213 __ nop();
2214 }
2215 int pc_for_athrow_offset = __ offset();
2216 InternalAddress pc_for_athrow(__ pc());
2217 __ adr(exceptionPC->as_register(), pc_for_athrow);
2218 add_call_info(pc_for_athrow_offset, info); // for exception handler
2219
2220 __ verify_not_null_oop(r0);
2221 // search an exception handler (r0: exception oop, r3: throwing pc)
2222 if (compilation()->has_fpu_code()) {
2223 unwind_id = StubId::c1_handle_exception_id;
2224 } else {
2225 unwind_id = StubId::c1_handle_exception_nofpu_id;
2226 }
2227 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2228
2229 // FIXME: enough room for two byte trap ????
2230 __ nop();
2231 }
2232
2233
2234 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2235 assert(exceptionOop->as_register() == r0, "must match");
2236
2237 __ b(_unwind_handler_entry);
2238 }
2239
2240
2241 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2242 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2243 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2244
2245 switch (left->type()) {
2246 case T_INT: {
2247 switch (code) {
2248 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2249 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2250 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2251 default:
2252 ShouldNotReachHere();
2253 break;
2254 }
2255 break;
2256 case T_LONG:
2257 case T_ADDRESS:
2258 case T_OBJECT:
2259 switch (code) {
2260 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2261 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2262 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2263 default:
2264 ShouldNotReachHere();
2265 break;
2266 }
2267 break;
2268 default:
2269 ShouldNotReachHere();
2270 break;
2271 }
2272 }
2273 }
2274
2275
2276 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2277 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2278 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2279
2280 switch (left->type()) {
2281 case T_INT: {
2282 switch (code) {
2283 case lir_shl: __ lslw (dreg, lreg, count); break;
2284 case lir_shr: __ asrw (dreg, lreg, count); break;
2285 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2286 default:
2287 ShouldNotReachHere();
2288 break;
2289 }
2290 break;
2291 case T_LONG:
2292 case T_ADDRESS:
2293 case T_OBJECT:
2294 switch (code) {
2295 case lir_shl: __ lsl (dreg, lreg, count); break;
2296 case lir_shr: __ asr (dreg, lreg, count); break;
2297 case lir_ushr: __ lsr (dreg, lreg, count); break;
2298 default:
2299 ShouldNotReachHere();
2300 break;
2301 }
2302 break;
2303 default:
2304 ShouldNotReachHere();
2305 break;
2306 }
2307 }
2308 }
2309
2310
2311 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2312 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2313 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2314 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2315 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2316 }
2317
2318
2319 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2320 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2321 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2322 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2323 __ mov (rscratch1, c);
2324 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2325 }
2326
2327
2328 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2329 ShouldNotReachHere();
2330 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2331 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2332 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2333 __ lea(rscratch1, __ constant_oop_address(o));
2334 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2335 }
2336
2337 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
2338 if (null_check) {
2339 __ cbz(obj, *slow_path->entry());
2340 }
2341 if (is_dest) {
2342 __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
2343 // TODO 8350865 Flat no longer implies null-free, so we need to check for flat dest. Can we do better here?
2344 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2345 } else {
2346 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2347 }
2348 }
2349
2350 // This code replaces a call to arraycopy; no exception may
2351 // be thrown in this code, they must be thrown in the System.arraycopy
2352 // activation frame; we could save some checks if this would not be the case
2353 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2354 ciArrayKlass* default_type = op->expected_type();
2355 Register src = op->src()->as_register();
2356 Register dst = op->dst()->as_register();
2357 Register src_pos = op->src_pos()->as_register();
2358 Register dst_pos = op->dst_pos()->as_register();
2359 Register length = op->length()->as_register();
2360 Register tmp = op->tmp()->as_register();
2361
2362 CodeStub* stub = op->stub();
2363 int flags = op->flags();
2364 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2365 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2366
2367 if (flags & LIR_OpArrayCopy::always_slow_path) {
2368 __ b(*stub->entry());
2369 __ bind(*stub->continuation());
2370 return;
2371 }
2372
2373 // if we don't know anything, just go through the generic arraycopy
2374 if (default_type == nullptr // || basic_type == T_OBJECT
2375 ) {
2376 Label done;
2377 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2378
2379 // Save the arguments in case the generic arraycopy fails and we
2380 // have to fall back to the JNI stub
2381 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2382 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2383 __ str(src, Address(sp, 4*BytesPerWord));
2384
2385 address copyfunc_addr = StubRoutines::generic_arraycopy();
2386 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2387
2388 // The arguments are in java calling convention so we shift them
2389 // to C convention
2390 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2391 __ mov(c_rarg0, j_rarg0);
2392 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2393 __ mov(c_rarg1, j_rarg1);
2394 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2395 __ mov(c_rarg2, j_rarg2);
2396 assert_different_registers(c_rarg3, j_rarg4);
2397 __ mov(c_rarg3, j_rarg3);
2398 __ mov(c_rarg4, j_rarg4);
2399 #ifndef PRODUCT
2400 if (PrintC1Statistics) {
2401 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2402 }
2403 #endif
2404 __ far_call(RuntimeAddress(copyfunc_addr));
2405
2406 __ cbz(r0, *stub->continuation());
2407
2408 // Reload values from the stack so they are where the stub
2409 // expects them.
2410 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2411 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2412 __ ldr(src, Address(sp, 4*BytesPerWord));
2413
2414 // r0 is -1^K where K == partial copied count
2415 __ eonw(rscratch1, r0, zr);
2416 // adjust length down and src/end pos up by partial copied count
2417 __ subw(length, length, rscratch1);
2418 __ addw(src_pos, src_pos, rscratch1);
2419 __ addw(dst_pos, dst_pos, rscratch1);
2420 __ b(*stub->entry());
2421
2422 __ bind(*stub->continuation());
2423 return;
2424 }
2425
2426 // Handle inline type arrays
2427 if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
2428 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
2429 }
2430 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
2431 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
2432 }
2433
2434 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2435
2436 int elem_size = type2aelembytes(basic_type);
2437 int scale = exact_log2(elem_size);
2438
2439 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2440 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2441
2442 // test for null
2443 if (flags & LIR_OpArrayCopy::src_null_check) {
2444 __ cbz(src, *stub->entry());
2445 }
2446 if (flags & LIR_OpArrayCopy::dst_null_check) {
2447 __ cbz(dst, *stub->entry());
2448 }
2449
2450 // If the compiler was not able to prove that exact type of the source or the destination
2451 // of the arraycopy is an array type, check at runtime if the source or the destination is
2452 // an instance type.
2453 if (flags & LIR_OpArrayCopy::type_check) {
2454 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2455 __ load_klass(tmp, dst);
2456 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2457 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2458 __ br(Assembler::GE, *stub->entry());
2459 }
2460
2461 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2462 __ load_klass(tmp, src);
2463 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2464 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2465 __ br(Assembler::GE, *stub->entry());
2466 }
2467 }
2468
2469 // check if negative
2470 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2471 __ cmpw(src_pos, 0);
2472 __ br(Assembler::LT, *stub->entry());
2473 }
2474 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2475 __ cmpw(dst_pos, 0);
2476 __ br(Assembler::LT, *stub->entry());
2477 }
2478
2479 if (flags & LIR_OpArrayCopy::length_positive_check) {
2480 __ cmpw(length, 0);
2481 __ br(Assembler::LT, *stub->entry());
2482 }
2483
2484 if (flags & LIR_OpArrayCopy::src_range_check) {
2485 __ addw(tmp, src_pos, length);
2486 __ ldrw(rscratch1, src_length_addr);
2487 __ cmpw(tmp, rscratch1);
2488 __ br(Assembler::HI, *stub->entry());
2489 }
2490 if (flags & LIR_OpArrayCopy::dst_range_check) {
2491 __ addw(tmp, dst_pos, length);
2492 __ ldrw(rscratch1, dst_length_addr);
2493 __ cmpw(tmp, rscratch1);
2494 __ br(Assembler::HI, *stub->entry());
2495 }
2496
2497 if (flags & LIR_OpArrayCopy::type_check) {
2498 // We don't know the array types are compatible
2499 if (basic_type != T_OBJECT) {
2500 // Simple test for basic type arrays
2501 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2502 __ br(Assembler::NE, *stub->entry());
2503 } else {
2504 // For object arrays, if src is a sub class of dst then we can
2505 // safely do the copy.
2506 Label cont, slow;
2507
2508 #define PUSH(r1, r2) \
2509 stp(r1, r2, __ pre(sp, -2 * wordSize));
2510
2511 #define POP(r1, r2) \
2512 ldp(r1, r2, __ post(sp, 2 * wordSize));
2513
2514 __ PUSH(src, dst);
2515
2516 __ load_klass(src, src);
2517 __ load_klass(dst, dst);
2518
2519 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2520
2521 __ PUSH(src, dst);
2522 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2523 __ POP(src, dst);
2524
2525 __ cbnz(src, cont);
2526
2527 __ bind(slow);
2528 __ POP(src, dst);
2529
2530 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2531 if (copyfunc_addr != nullptr) { // use stub if available
2532 // src is not a sub class of dst so we have to do a
2533 // per-element check.
2534
2535 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2536 if ((flags & mask) != mask) {
2537 // Check that at least both of them object arrays.
2538 assert(flags & mask, "one of the two should be known to be an object array");
2539
2540 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2541 __ load_klass(tmp, src);
2542 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2543 __ load_klass(tmp, dst);
2544 }
2545 int lh_offset = in_bytes(Klass::layout_helper_offset());
2546 Address klass_lh_addr(tmp, lh_offset);
2547 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2548 __ ldrw(rscratch1, klass_lh_addr);
2549 __ mov(rscratch2, objArray_lh);
2550 __ eorw(rscratch1, rscratch1, rscratch2);
2551 __ cbnzw(rscratch1, *stub->entry());
2552 }
2553
2554 // Spill because stubs can use any register they like and it's
2555 // easier to restore just those that we care about.
2556 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2557 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2558 __ str(src, Address(sp, 4*BytesPerWord));
2559
2560 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2561 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2562 assert_different_registers(c_rarg0, dst, dst_pos, length);
2563 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2564 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2565 assert_different_registers(c_rarg1, dst, length);
2566 __ uxtw(c_rarg2, length);
2567 assert_different_registers(c_rarg2, dst);
2568
2569 __ load_klass(c_rarg4, dst);
2570 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2571 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2572 __ far_call(RuntimeAddress(copyfunc_addr));
2573
2574 #ifndef PRODUCT
2575 if (PrintC1Statistics) {
2576 Label failed;
2577 __ cbnz(r0, failed);
2578 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2579 __ bind(failed);
2580 }
2581 #endif
2582
2583 __ cbz(r0, *stub->continuation());
2584
2585 #ifndef PRODUCT
2586 if (PrintC1Statistics) {
2587 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2588 }
2589 #endif
2590 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2591
2592 // Restore previously spilled arguments
2593 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2594 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2595 __ ldr(src, Address(sp, 4*BytesPerWord));
2596
2597 // return value is -1^K where K is partial copied count
2598 __ eonw(rscratch1, r0, zr);
2599 // adjust length down and src/end pos up by partial copied count
2600 __ subw(length, length, rscratch1);
2601 __ addw(src_pos, src_pos, rscratch1);
2602 __ addw(dst_pos, dst_pos, rscratch1);
2603 }
2604
2605 __ b(*stub->entry());
2606
2607 __ bind(cont);
2608 __ POP(src, dst);
2609 }
2610 }
2611
2612 #ifdef ASSERT
2613 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2614 // Sanity check the known type with the incoming class. For the
2615 // primitive case the types must match exactly with src.klass and
2616 // dst.klass each exactly matching the default type. For the
2617 // object array case, if no type check is needed then either the
2618 // dst type is exactly the expected type and the src type is a
2619 // subtype which we can't check or src is the same array as dst
2620 // but not necessarily exactly of type default_type.
2621 Label known_ok, halt;
2622 __ mov_metadata(tmp, default_type->constant_encoding());
2623
2624 if (basic_type != T_OBJECT) {
2625 __ cmp_klass(dst, tmp, rscratch1);
2626 __ br(Assembler::NE, halt);
2627 __ cmp_klass(src, tmp, rscratch1);
2628 __ br(Assembler::EQ, known_ok);
2629 } else {
2630 __ cmp_klass(dst, tmp, rscratch1);
2631 __ br(Assembler::EQ, known_ok);
2632 __ cmp(src, dst);
2633 __ br(Assembler::EQ, known_ok);
2634 }
2635 __ bind(halt);
2636 __ stop("incorrect type information in arraycopy");
2637 __ bind(known_ok);
2638 }
2639 #endif
2640
2641 #ifndef PRODUCT
2642 if (PrintC1Statistics) {
2643 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2644 }
2645 #endif
2646
2647 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2648 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2649 assert_different_registers(c_rarg0, dst, dst_pos, length);
2650 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2651 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2652 assert_different_registers(c_rarg1, dst, length);
2653 __ uxtw(c_rarg2, length);
2654 assert_different_registers(c_rarg2, dst);
2655
2656 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2657 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2658 const char *name;
2659 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2660
2661 CodeBlob *cb = CodeCache::find_blob(entry);
2662 if (cb) {
2663 __ far_call(RuntimeAddress(entry));
2664 } else {
2665 __ call_VM_leaf(entry, 3);
2666 }
2667
2668 if (stub != nullptr) {
2669 __ bind(*stub->continuation());
2670 }
2671 }
2672
2673
2674
2675
2676 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2677 Register obj = op->obj_opr()->as_register(); // may not be an oop
2678 Register hdr = op->hdr_opr()->as_register();
2679 Register lock = op->lock_opr()->as_register();
2680 Register temp = op->scratch_opr()->as_register();
2681 if (op->code() == lir_lock) {
2682 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2683 // add debug info for NullPointerException only if one is possible
2684 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2685 if (op->info() != nullptr) {
2686 add_debug_info_for_null_check(null_check_offset, op->info());
2687 }
2688 // done
2689 } else if (op->code() == lir_unlock) {
2690 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2691 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2692 } else {
2693 Unimplemented();
2694 }
2695 __ bind(*op->stub()->continuation());
2696 }
2697
2698 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2699 Register obj = op->obj()->as_pointer_register();
2700 Register result = op->result_opr()->as_pointer_register();
2701
2702 CodeEmitInfo* info = op->info();
2703 if (info != nullptr) {
2704 add_debug_info_for_null_check_here(info);
2705 }
2706
2707 __ load_klass(result, obj);
2708 }
2709
2710 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2711 ciMethod* method = op->profiled_method();
2712 int bci = op->profiled_bci();
2713 ciMethod* callee = op->profiled_callee();
2714
2715 // Update counter for all call types
2716 ciMethodData* md = method->method_data_or_null();
2717 assert(md != nullptr, "Sanity");
2718 ciProfileData* data = md->bci_to_data(bci);
2719 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2720 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2721 Register mdo = op->mdo()->as_register();
2722 __ mov_metadata(mdo, md->constant_encoding());
2723 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2724 // Perform additional virtual call profiling for invokevirtual and
2725 // invokeinterface bytecodes
2726 if (op->should_profile_receiver_type()) {
2727 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2728 Register recv = op->recv()->as_register();
2729 assert_different_registers(mdo, recv);
2730 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2731 ciKlass* known_klass = op->known_holder();
2732 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2733 // We know the type that will be seen at this call site; we can
2734 // statically update the MethodData* rather than needing to do
2735 // dynamic tests on the receiver type
2736
2737 // NOTE: we should probably put a lock around this search to
2738 // avoid collisions by concurrent compilations
2739 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2740 uint i;
2741 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2742 ciKlass* receiver = vc_data->receiver(i);
2743 if (known_klass->equals(receiver)) {
2744 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2745 __ addptr(data_addr, DataLayout::counter_increment);
2746 return;
2747 }
2748 }
2749
2750 // Receiver type not found in profile data; select an empty slot
2751
2752 // Note that this is less efficient than it should be because it
2753 // always does a write to the receiver part of the
2754 // VirtualCallData rather than just the first time
2755 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2756 ciKlass* receiver = vc_data->receiver(i);
2757 if (receiver == nullptr) {
2758 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2759 Address recv_addr =
2760 __ form_address(rscratch2, mdo,
2761 md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)),
2762 LogBytesPerWord);
2763 __ str(rscratch1, recv_addr);
2764 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2765 __ addptr(data_addr, DataLayout::counter_increment);
2766 return;
2767 }
2768 }
2769 } else {
2770 __ load_klass(recv, recv);
2771 Label update_done;
2772 type_profile_helper(mdo, md, data, recv, &update_done);
2773 // Receiver did not match any saved receiver and there is no empty row for it.
2774 // Increment total counter to indicate polymorphic case.
2775 __ addptr(counter_addr, DataLayout::counter_increment);
2776
2777 __ bind(update_done);
2778 }
2779 } else {
2780 // Static call
2781 __ addptr(counter_addr, DataLayout::counter_increment);
2782 }
2783 }
2784
2785
2786 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2787 Unimplemented();
2788 }
2789
2790
2791 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2792 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2793 }
2794
2795 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2796 assert(op->crc()->is_single_cpu(), "crc must be register");
2797 assert(op->val()->is_single_cpu(), "byte value must be register");
2798 assert(op->result_opr()->is_single_cpu(), "result must be register");
2799 Register crc = op->crc()->as_register();
2800 Register val = op->val()->as_register();
2801 Register res = op->result_opr()->as_register();
2802
2803 assert_different_registers(val, crc, res);
2804 uint64_t offset;
2805 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2806 __ add(res, res, offset);
2807
2808 __ mvnw(crc, crc); // ~crc
2809 __ update_byte_crc32(crc, val, res);
2810 __ mvnw(res, crc); // ~crc
2811 }
2812
2813 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2814 COMMENT("emit_profile_type {");
2815 Register obj = op->obj()->as_register();
2816 Register tmp = op->tmp()->as_pointer_register();
2817 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2818 ciKlass* exact_klass = op->exact_klass();
2819 intptr_t current_klass = op->current_klass();
2820 bool not_null = op->not_null();
2821 bool no_conflict = op->no_conflict();
2822
2823 Label update, next, none;
2824
2825 bool do_null = !not_null;
2826 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2827 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2828
2829 assert(do_null || do_update, "why are we here?");
2830 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2831 assert(mdo_addr.base() != rscratch1, "wrong register");
2832
2833 __ verify_oop(obj);
2834
2835 if (tmp != obj) {
2836 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2837 __ mov(tmp, obj);
2838 } else {
2839 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2840 }
2841 if (do_null) {
2842 __ cbnz(tmp, update);
2843 if (!TypeEntries::was_null_seen(current_klass)) {
2844 __ ldr(rscratch2, mdo_addr);
2845 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2846 __ str(rscratch2, mdo_addr);
2847 }
2848 if (do_update) {
2849 #ifndef ASSERT
2850 __ b(next);
2851 }
2852 #else
2853 __ b(next);
2854 }
2855 } else {
2856 __ cbnz(tmp, update);
2857 __ stop("unexpected null obj");
2858 #endif
2859 }
2860
2861 __ bind(update);
2862
2863 if (do_update) {
2864 #ifdef ASSERT
2865 if (exact_klass != nullptr) {
2866 Label ok;
2867 __ load_klass(tmp, tmp);
2868 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2869 __ eor(rscratch1, tmp, rscratch1);
2870 __ cbz(rscratch1, ok);
2871 __ stop("exact klass and actual klass differ");
2872 __ bind(ok);
2873 }
2874 #endif
2875 if (!no_conflict) {
2876 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2877 if (exact_klass != nullptr) {
2878 __ mov_metadata(tmp, exact_klass->constant_encoding());
2879 } else {
2880 __ load_klass(tmp, tmp);
2881 }
2882
2883 __ ldr(rscratch2, mdo_addr);
2884 __ eor(tmp, tmp, rscratch2);
2885 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2886 // klass seen before, nothing to do. The unknown bit may have been
2887 // set already but no need to check.
2888 __ cbz(rscratch1, next);
2889
2890 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2891
2892 if (TypeEntries::is_type_none(current_klass)) {
2893 __ cbz(rscratch2, none);
2894 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2895 __ br(Assembler::EQ, none);
2896 // There is a chance that the checks above
2897 // fail if another thread has just set the
2898 // profiling to this obj's klass
2899 __ dmb(Assembler::ISHLD);
2900 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2901 __ ldr(rscratch2, mdo_addr);
2902 __ eor(tmp, tmp, rscratch2);
2903 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2904 __ cbz(rscratch1, next);
2905 }
2906 } else {
2907 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2908 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2909
2910 __ ldr(tmp, mdo_addr);
2911 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2912 }
2913
2914 // different than before. Cannot keep accurate profile.
2915 __ ldr(rscratch2, mdo_addr);
2916 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2917 __ str(rscratch2, mdo_addr);
2918
2919 if (TypeEntries::is_type_none(current_klass)) {
2920 __ b(next);
2921
2922 __ bind(none);
2923 // first time here. Set profile type.
2924 __ str(tmp, mdo_addr);
2925 #ifdef ASSERT
2926 __ andr(tmp, tmp, TypeEntries::type_mask);
2927 __ verify_klass_ptr(tmp);
2928 #endif
2929 }
2930 } else {
2931 // There's a single possible klass at this profile point
2932 assert(exact_klass != nullptr, "should be");
2933 if (TypeEntries::is_type_none(current_klass)) {
2934 __ mov_metadata(tmp, exact_klass->constant_encoding());
2935 __ ldr(rscratch2, mdo_addr);
2936 __ eor(tmp, tmp, rscratch2);
2937 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2938 __ cbz(rscratch1, next);
2939 #ifdef ASSERT
2940 {
2941 Label ok;
2942 __ ldr(rscratch1, mdo_addr);
2943 __ cbz(rscratch1, ok);
2944 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2945 __ br(Assembler::EQ, ok);
2946 // may have been set by another thread
2947 __ dmb(Assembler::ISHLD);
2948 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2949 __ ldr(rscratch2, mdo_addr);
2950 __ eor(rscratch2, rscratch1, rscratch2);
2951 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2952 __ cbz(rscratch2, ok);
2953
2954 __ stop("unexpected profiling mismatch");
2955 __ bind(ok);
2956 }
2957 #endif
2958 // first time here. Set profile type.
2959 __ str(tmp, mdo_addr);
2960 #ifdef ASSERT
2961 __ andr(tmp, tmp, TypeEntries::type_mask);
2962 __ verify_klass_ptr(tmp);
2963 #endif
2964 } else {
2965 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2966 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2967
2968 __ ldr(tmp, mdo_addr);
2969 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2970
2971 __ orr(tmp, tmp, TypeEntries::type_unknown);
2972 __ str(tmp, mdo_addr);
2973 // FIXME: Write barrier needed here?
2974 }
2975 }
2976
2977 __ bind(next);
2978 }
2979 COMMENT("} emit_profile_type");
2980 }
2981
2982 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
2983 Register obj = op->obj()->as_register();
2984 Register tmp = op->tmp()->as_pointer_register();
2985 bool not_null = op->not_null();
2986 int flag = op->flag();
2987
2988 Label not_inline_type;
2989 if (!not_null) {
2990 __ cbz(obj, not_inline_type);
2991 }
2992
2993 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
2994
2995 Address mdo_addr = as_Address(op->mdp()->as_address_ptr(), rscratch2);
2996 __ ldrb(rscratch1, mdo_addr);
2997 __ orr(rscratch1, rscratch1, flag);
2998 __ strb(rscratch1, mdo_addr);
2999
3000 __ bind(not_inline_type);
3001 }
3002
3003 void LIR_Assembler::align_backward_branch_target() {
3004 }
3005
3006
3007 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3008 // tmp must be unused
3009 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3010
3011 if (left->is_single_cpu()) {
3012 assert(dest->is_single_cpu(), "expect single result reg");
3013 __ negw(dest->as_register(), left->as_register());
3014 } else if (left->is_double_cpu()) {
3015 assert(dest->is_double_cpu(), "expect double result reg");
3016 __ neg(dest->as_register_lo(), left->as_register_lo());
3017 } else if (left->is_single_fpu()) {
3018 assert(dest->is_single_fpu(), "expect single float result reg");
3019 __ fnegs(dest->as_float_reg(), left->as_float_reg());
3020 } else {
3021 assert(left->is_double_fpu(), "expect double float operand reg");
3022 assert(dest->is_double_fpu(), "expect double float result reg");
3023 __ fnegd(dest->as_double_reg(), left->as_double_reg());
3024 }
3025 }
3026
3027
3028 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3029 if (patch_code != lir_patch_none) {
3030 deoptimize_trap(info);
3031 return;
3032 }
3033
3034 __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
3035 }
3036
3037
3038 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3039 assert(!tmp->is_valid(), "don't need temporary");
3040
3041 CodeBlob *cb = CodeCache::find_blob(dest);
3042 if (cb) {
3043 __ far_call(RuntimeAddress(dest));
3044 } else {
3045 __ mov(rscratch1, RuntimeAddress(dest));
3046 __ blr(rscratch1);
3047 }
3048
3049 if (info != nullptr) {
3050 add_call_info_here(info);
3051 }
3052 __ post_call_nop();
3053 }
3054
3055 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3056 if (dest->is_address() || src->is_address()) {
3057 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
3058 } else {
3059 ShouldNotReachHere();
3060 }
3061 }
3062
3063 #ifdef ASSERT
3064 // emit run-time assertion
3065 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3066 assert(op->code() == lir_assert, "must be");
3067
3068 if (op->in_opr1()->is_valid()) {
3069 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3070 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3071 } else {
3072 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3073 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3074 }
3075
3076 Label ok;
3077 if (op->condition() != lir_cond_always) {
3078 Assembler::Condition acond = Assembler::AL;
3079 switch (op->condition()) {
3080 case lir_cond_equal: acond = Assembler::EQ; break;
3081 case lir_cond_notEqual: acond = Assembler::NE; break;
3082 case lir_cond_less: acond = Assembler::LT; break;
3083 case lir_cond_lessEqual: acond = Assembler::LE; break;
3084 case lir_cond_greaterEqual: acond = Assembler::GE; break;
3085 case lir_cond_greater: acond = Assembler::GT; break;
3086 case lir_cond_belowEqual: acond = Assembler::LS; break;
3087 case lir_cond_aboveEqual: acond = Assembler::HS; break;
3088 default: ShouldNotReachHere();
3089 }
3090 __ br(acond, ok);
3091 }
3092 if (op->halt()) {
3093 const char* str = __ code_string(op->msg());
3094 __ stop(str);
3095 } else {
3096 breakpoint();
3097 }
3098 __ bind(ok);
3099 }
3100 #endif
3101
3102 #ifndef PRODUCT
3103 #define COMMENT(x) do { __ block_comment(x); } while (0)
3104 #else
3105 #define COMMENT(x)
3106 #endif
3107
3108 void LIR_Assembler::membar() {
3109 COMMENT("membar");
3110 __ membar(MacroAssembler::AnyAny);
3111 }
3112
3113 void LIR_Assembler::membar_acquire() {
3114 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
3115 }
3116
3117 void LIR_Assembler::membar_release() {
3118 __ membar(Assembler::LoadStore|Assembler::StoreStore);
3119 }
3120
3121 void LIR_Assembler::membar_loadload() {
3122 __ membar(Assembler::LoadLoad);
3123 }
3124
3125 void LIR_Assembler::membar_storestore() {
3126 __ membar(MacroAssembler::StoreStore);
3127 }
3128
3129 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3130
3131 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3132
3133 void LIR_Assembler::on_spin_wait() {
3134 __ spin_wait();
3135 }
3136
3137 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3138 __ mov(result_reg->as_register(), rthread);
3139 }
3140
3141 void LIR_Assembler::check_orig_pc() {
3142 __ ldr(rscratch2, frame_map()->address_for_orig_pc_addr());
3143 __ cmp(rscratch2, (u1)NULL_WORD);
3144 }
3145
3146 void LIR_Assembler::peephole(LIR_List *lir) {
3147 #if 0
3148 if (tableswitch_count >= max_tableswitches)
3149 return;
3150
3151 /*
3152 This finite-state automaton recognizes sequences of compare-and-
3153 branch instructions. We will turn them into a tableswitch. You
3154 could argue that C1 really shouldn't be doing this sort of
3155 optimization, but without it the code is really horrible.
3156 */
3157
3158 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3159 int first_key, last_key = -2147483648;
3160 int next_key = 0;
3161 int start_insn = -1;
3162 int last_insn = -1;
3163 Register reg = noreg;
3164 LIR_Opr reg_opr;
3165 state = start_s;
3166
3167 LIR_OpList* inst = lir->instructions_list();
3168 for (int i = 0; i < inst->length(); i++) {
3169 LIR_Op* op = inst->at(i);
3170 switch (state) {
3171 case start_s:
3172 first_key = -1;
3173 start_insn = i;
3174 switch (op->code()) {
3175 case lir_cmp:
3176 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3177 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3178 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3179 && opr2->is_constant()
3180 && opr2->type() == T_INT) {
3181 reg_opr = opr1;
3182 reg = opr1->as_register();
3183 first_key = opr2->as_constant_ptr()->as_jint();
3184 next_key = first_key + 1;
3185 state = cmp_s;
3186 goto next_state;
3187 }
3188 break;
3189 }
3190 break;
3191 case cmp_s:
3192 switch (op->code()) {
3193 case lir_branch:
3194 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3195 state = beq_s;
3196 last_insn = i;
3197 goto next_state;
3198 }
3199 }
3200 state = start_s;
3201 break;
3202 case beq_s:
3203 switch (op->code()) {
3204 case lir_cmp: {
3205 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3206 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3207 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3208 && opr1->as_register() == reg
3209 && opr2->is_constant()
3210 && opr2->type() == T_INT
3211 && opr2->as_constant_ptr()->as_jint() == next_key) {
3212 last_key = next_key;
3213 next_key++;
3214 state = cmp_s;
3215 goto next_state;
3216 }
3217 }
3218 }
3219 last_key = next_key;
3220 state = start_s;
3221 break;
3222 default:
3223 assert(false, "impossible state");
3224 }
3225 if (state == start_s) {
3226 if (first_key < last_key - 5L && reg != noreg) {
3227 {
3228 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3229 // reg->encoding(),
3230 // start_insn, first_key, last_key);
3231 // for (int i = 0; i < inst->length(); i++) {
3232 // inst->at(i)->print();
3233 // tty->print("\n");
3234 // }
3235 // tty->print("\n");
3236 }
3237
3238 struct tableswitch *sw = &switches[tableswitch_count];
3239 sw->_insn_index = start_insn, sw->_first_key = first_key,
3240 sw->_last_key = last_key, sw->_reg = reg;
3241 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3242 {
3243 // Insert the new table of branches
3244 int offset = last_insn;
3245 for (int n = first_key; n < last_key; n++) {
3246 inst->insert_before
3247 (last_insn + 1,
3248 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3249 inst->at(offset)->as_OpBranch()->label()));
3250 offset -= 2, i++;
3251 }
3252 }
3253 // Delete all the old compare-and-branch instructions
3254 for (int n = first_key; n < last_key; n++) {
3255 inst->remove_at(start_insn);
3256 inst->remove_at(start_insn);
3257 }
3258 // Insert the tableswitch instruction
3259 inst->insert_before(start_insn,
3260 new LIR_Op2(lir_cmp, lir_cond_always,
3261 LIR_OprFact::intConst(tableswitch_count),
3262 reg_opr));
3263 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3264 tableswitch_count++;
3265 }
3266 reg = noreg;
3267 last_key = -2147483648;
3268 }
3269 next_state:
3270 ;
3271 }
3272 #endif
3273 }
3274
3275 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3276 Address addr = as_Address(src->as_address_ptr());
3277 BasicType type = src->type();
3278 bool is_oop = is_reference_type(type);
3279
3280 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3281 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3282
3283 switch(type) {
3284 case T_INT:
3285 xchg = &MacroAssembler::atomic_xchgalw;
3286 add = &MacroAssembler::atomic_addalw;
3287 break;
3288 case T_LONG:
3289 xchg = &MacroAssembler::atomic_xchgal;
3290 add = &MacroAssembler::atomic_addal;
3291 break;
3292 case T_OBJECT:
3293 case T_ARRAY:
3294 if (UseCompressedOops) {
3295 xchg = &MacroAssembler::atomic_xchgalw;
3296 add = &MacroAssembler::atomic_addalw;
3297 } else {
3298 xchg = &MacroAssembler::atomic_xchgal;
3299 add = &MacroAssembler::atomic_addal;
3300 }
3301 break;
3302 default:
3303 ShouldNotReachHere();
3304 xchg = &MacroAssembler::atomic_xchgal;
3305 add = &MacroAssembler::atomic_addal; // unreachable
3306 }
3307
3308 switch (code) {
3309 case lir_xadd:
3310 {
3311 RegisterOrConstant inc;
3312 Register tmp = as_reg(tmp_op);
3313 Register dst = as_reg(dest);
3314 if (data->is_constant()) {
3315 inc = RegisterOrConstant(as_long(data));
3316 assert_different_registers(dst, addr.base(), tmp,
3317 rscratch1, rscratch2);
3318 } else {
3319 inc = RegisterOrConstant(as_reg(data));
3320 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3321 rscratch1, rscratch2);
3322 }
3323 __ lea(tmp, addr);
3324 (_masm->*add)(dst, inc, tmp);
3325 break;
3326 }
3327 case lir_xchg:
3328 {
3329 Register tmp = tmp_op->as_register();
3330 Register obj = as_reg(data);
3331 Register dst = as_reg(dest);
3332 if (is_oop && UseCompressedOops) {
3333 __ encode_heap_oop(rscratch2, obj);
3334 obj = rscratch2;
3335 }
3336 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3337 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3338 __ lea(tmp, addr);
3339 (_masm->*xchg)(dst, obj, tmp);
3340 if (is_oop && UseCompressedOops) {
3341 __ decode_heap_oop(dst);
3342 }
3343 }
3344 break;
3345 default:
3346 ShouldNotReachHere();
3347 }
3348 if(!UseLSE) {
3349 __ membar(__ AnyAny);
3350 }
3351 }
3352
3353 #undef __