1 /*
   2  * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "asm/assembler.hpp"
  29 #include "c1/c1_CodeStubs.hpp"
  30 #include "c1/c1_Compilation.hpp"
  31 #include "c1/c1_LIRAssembler.hpp"
  32 #include "c1/c1_MacroAssembler.hpp"
  33 #include "c1/c1_Runtime1.hpp"
  34 #include "c1/c1_ValueStack.hpp"
  35 #include "ci/ciArrayKlass.hpp"
  36 #include "ci/ciInlineKlass.hpp"
  37 #include "ci/ciInstance.hpp"
  38 #include "code/compiledIC.hpp"
  39 #include "gc/shared/collectedHeap.hpp"
  40 #include "gc/shared/gc_globals.hpp"
  41 #include "nativeInst_aarch64.hpp"
  42 #include "oops/objArrayKlass.hpp"
  43 #include "oops/oop.inline.hpp"
  44 #include "runtime/frame.inline.hpp"
  45 #include "runtime/sharedRuntime.hpp"
  46 #include "runtime/stubRoutines.hpp"
  47 #include "utilities/powerOfTwo.hpp"
  48 #include "vmreg_aarch64.inline.hpp"
  49 
  50 
  51 #ifndef PRODUCT
  52 #define COMMENT(x)   do { __ block_comment(x); } while (0)
  53 #else
  54 #define COMMENT(x)
  55 #endif
  56 
  57 NEEDS_CLEANUP // remove this definitions ?
  58 const Register IC_Klass    = rscratch2;   // where the IC klass is cached
  59 const Register SYNC_header = r0;   // synchronization header
  60 const Register SHIFT_count = r0;   // where count for shift operations must be
  61 
  62 #define __ _masm->
  63 
  64 
  65 static void select_different_registers(Register preserve,
  66                                        Register extra,
  67                                        Register &tmp1,
  68                                        Register &tmp2) {
  69   if (tmp1 == preserve) {
  70     assert_different_registers(tmp1, tmp2, extra);
  71     tmp1 = extra;
  72   } else if (tmp2 == preserve) {
  73     assert_different_registers(tmp1, tmp2, extra);
  74     tmp2 = extra;
  75   }
  76   assert_different_registers(preserve, tmp1, tmp2);
  77 }
  78 
  79 
  80 
  81 static void select_different_registers(Register preserve,
  82                                        Register extra,
  83                                        Register &tmp1,
  84                                        Register &tmp2,
  85                                        Register &tmp3) {
  86   if (tmp1 == preserve) {
  87     assert_different_registers(tmp1, tmp2, tmp3, extra);
  88     tmp1 = extra;
  89   } else if (tmp2 == preserve) {
  90     assert_different_registers(tmp1, tmp2, tmp3, extra);
  91     tmp2 = extra;
  92   } else if (tmp3 == preserve) {
  93     assert_different_registers(tmp1, tmp2, tmp3, extra);
  94     tmp3 = extra;
  95   }
  96   assert_different_registers(preserve, tmp1, tmp2, tmp3);
  97 }
  98 
  99 
 100 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
 101 
 102 
 103 LIR_Opr LIR_Assembler::receiverOpr() {
 104   return FrameMap::receiver_opr;
 105 }
 106 
 107 LIR_Opr LIR_Assembler::osrBufferPointer() {
 108   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 109 }
 110 
 111 //--------------fpu register translations-----------------------
 112 
 113 
 114 address LIR_Assembler::float_constant(float f) {
 115   address const_addr = __ float_constant(f);
 116   if (const_addr == NULL) {
 117     bailout("const section overflow");
 118     return __ code()->consts()->start();
 119   } else {
 120     return const_addr;
 121   }
 122 }
 123 
 124 
 125 address LIR_Assembler::double_constant(double d) {
 126   address const_addr = __ double_constant(d);
 127   if (const_addr == NULL) {
 128     bailout("const section overflow");
 129     return __ code()->consts()->start();
 130   } else {
 131     return const_addr;
 132   }
 133 }
 134 
 135 address LIR_Assembler::int_constant(jlong n) {
 136   address const_addr = __ long_constant(n);
 137   if (const_addr == NULL) {
 138     bailout("const section overflow");
 139     return __ code()->consts()->start();
 140   } else {
 141     return const_addr;
 142   }
 143 }
 144 
 145 void LIR_Assembler::breakpoint() { Unimplemented(); }
 146 
 147 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
 148 
 149 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
 150 
 151 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
 152 //-------------------------------------------
 153 
 154 static Register as_reg(LIR_Opr op) {
 155   return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
 156 }
 157 
 158 static jlong as_long(LIR_Opr data) {
 159   jlong result;
 160   switch (data->type()) {
 161   case T_INT:
 162     result = (data->as_jint());
 163     break;
 164   case T_LONG:
 165     result = (data->as_jlong());
 166     break;
 167   default:
 168     ShouldNotReachHere();
 169     result = 0;  // unreachable
 170   }
 171   return result;
 172 }
 173 
 174 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 175   Register base = addr->base()->as_pointer_register();
 176   LIR_Opr opr = addr->index();
 177   if (opr->is_cpu_register()) {
 178     Register index;
 179     if (opr->is_single_cpu())
 180       index = opr->as_register();
 181     else
 182       index = opr->as_register_lo();
 183     assert(addr->disp() == 0, "must be");
 184     switch(opr->type()) {
 185       case T_INT:
 186         return Address(base, index, Address::sxtw(addr->scale()));
 187       case T_LONG:
 188         return Address(base, index, Address::lsl(addr->scale()));
 189       default:
 190         ShouldNotReachHere();
 191       }
 192   } else {
 193     assert(addr->scale() == 0,
 194            "expected for immediate operand, was: %d", addr->scale());
 195     ptrdiff_t offset = ptrdiff_t(addr->disp());
 196     // NOTE: Does not handle any 16 byte vector access.
 197     const uint type_size = type2aelembytes(addr->type(), true);
 198     return __ legitimize_address(Address(base, offset), type_size, tmp);
 199   }
 200   return Address();
 201 }
 202 
 203 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 204   ShouldNotReachHere();
 205   return Address();
 206 }
 207 
 208 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 209   return as_Address(addr, rscratch1);
 210 }
 211 
 212 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 213   return as_Address(addr, rscratch1);  // Ouch
 214   // FIXME: This needs to be much more clever.  See x86.
 215 }
 216 
 217 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
 218 // not encodable as a base + (immediate) offset, generate an explicit address
 219 // calculation to hold the address in a temporary register.
 220 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
 221   precond(size == 4 || size == 8);
 222   Address addr = frame_map()->address_for_slot(index, adjust);
 223   precond(addr.getMode() == Address::base_plus_offset);
 224   precond(addr.base() == sp);
 225   precond(addr.offset() > 0);
 226   uint mask = size - 1;
 227   assert((addr.offset() & mask) == 0, "scaled offsets only");
 228   return __ legitimize_address(addr, size, tmp);
 229 }
 230 
 231 void LIR_Assembler::osr_entry() {
 232   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 233   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 234   ValueStack* entry_state = osr_entry->state();
 235   int number_of_locks = entry_state->locks_size();
 236 
 237   // we jump here if osr happens with the interpreter
 238   // state set up to continue at the beginning of the
 239   // loop that triggered osr - in particular, we have
 240   // the following registers setup:
 241   //
 242   // r2: osr buffer
 243   //
 244 
 245   // build frame
 246   ciMethod* m = compilation()->method();
 247   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 248 
 249   // OSR buffer is
 250   //
 251   // locals[nlocals-1..0]
 252   // monitors[0..number_of_locks]
 253   //
 254   // locals is a direct copy of the interpreter frame so in the osr buffer
 255   // so first slot in the local array is the last local from the interpreter
 256   // and last slot is local[0] (receiver) from the interpreter
 257   //
 258   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 259   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 260   // in the interpreter frame (the method lock if a sync method)
 261 
 262   // Initialize monitors in the compiled activation.
 263   //   r2: pointer to osr buffer
 264   //
 265   // All other registers are dead at this point and the locals will be
 266   // copied into place by code emitted in the IR.
 267 
 268   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 269   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 270     int monitor_offset = BytesPerWord * method()->max_locals() +
 271       (2 * BytesPerWord) * (number_of_locks - 1);
 272     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 273     // the OSR buffer using 2 word entries: first the lock and then
 274     // the oop.
 275     for (int i = 0; i < number_of_locks; i++) {
 276       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 277 #ifdef ASSERT
 278       // verify the interpreter's monitor has a non-null object
 279       {
 280         Label L;
 281         __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 282         __ cbnz(rscratch1, L);
 283         __ stop("locked object is NULL");
 284         __ bind(L);
 285       }
 286 #endif
 287       __ ldr(r19, Address(OSR_buf, slot_offset + 0));
 288       __ str(r19, frame_map()->address_for_monitor_lock(i));
 289       __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 290       __ str(r19, frame_map()->address_for_monitor_object(i));
 291     }
 292   }
 293 }
 294 
 295 
 296 // inline cache check; done before the frame is built.
 297 int LIR_Assembler::check_icache() {
 298   Register receiver = FrameMap::receiver_opr->as_register();
 299   Register ic_klass = IC_Klass;
 300   int start_offset = __ offset();
 301   __ inline_cache_check(receiver, ic_klass);
 302 
 303   // if icache check fails, then jump to runtime routine
 304   // Note: RECEIVER must still contain the receiver!
 305   Label dont;
 306   __ br(Assembler::EQ, dont);
 307   __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 308 
 309   // We align the verified entry point unless the method body
 310   // (including its inline cache check) will fit in a single 64-byte
 311   // icache line.
 312   if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
 313     // force alignment after the cache check.
 314     __ align(CodeEntryAlignment);
 315   }
 316 
 317   __ bind(dont);
 318   return start_offset;
 319 }
 320 
 321 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 322   assert(VM_Version::supports_fast_class_init_checks(), "sanity");
 323   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
 324 
 325   Label L_skip_barrier;
 326 
 327   __ mov_metadata(rscratch2, method->holder()->constant_encoding());
 328   __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
 329   __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 330   __ bind(L_skip_barrier);
 331 }
 332 
 333 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 334   if (o == NULL) {
 335     __ mov(reg, zr);
 336   } else {
 337     __ movoop(reg, o, /*immediate*/true);
 338   }
 339 }
 340 
 341 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
 342   address target = NULL;
 343   relocInfo::relocType reloc_type = relocInfo::none;
 344 
 345   switch (patching_id(info)) {
 346   case PatchingStub::access_field_id:
 347     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 348     reloc_type = relocInfo::section_word_type;
 349     break;
 350   case PatchingStub::load_klass_id:
 351     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 352     reloc_type = relocInfo::metadata_type;
 353     break;
 354   case PatchingStub::load_mirror_id:
 355     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 356     reloc_type = relocInfo::oop_type;
 357     break;
 358   case PatchingStub::load_appendix_id:
 359     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 360     reloc_type = relocInfo::oop_type;
 361     break;
 362   default: ShouldNotReachHere();
 363   }
 364 
 365   __ far_call(RuntimeAddress(target));
 366   add_call_info_here(info);
 367 }
 368 
 369 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 370   deoptimize_trap(info);
 371 }
 372 
 373 
 374 // This specifies the rsp decrement needed to build the frame
 375 int LIR_Assembler::initial_frame_size_in_bytes() const {
 376   // if rounding, must let FrameMap know!
 377 
 378   return in_bytes(frame_map()->framesize_in_bytes());
 379 }
 380 
 381 
 382 int LIR_Assembler::emit_exception_handler() {
 383   // if the last instruction is a call (typically to do a throw which
 384   // is coming at the end after block reordering) the return address
 385   // must still point into the code area in order to avoid assertion
 386   // failures when searching for the corresponding bci => add a nop
 387   // (was bug 5/14/1999 - gri)
 388   __ nop();
 389 
 390   // generate code for exception handler
 391   address handler_base = __ start_a_stub(exception_handler_size());
 392   if (handler_base == NULL) {
 393     // not enough space left for the handler
 394     bailout("exception handler overflow");
 395     return -1;
 396   }
 397 
 398   int offset = code_offset();
 399 
 400   // the exception oop and pc are in r0, and r3
 401   // no other registers need to be preserved, so invalidate them
 402   __ invalidate_registers(false, true, true, false, true, true);
 403 
 404   // check that there is really an exception
 405   __ verify_not_null_oop(r0);
 406 
 407   // search an exception handler (r0: exception oop, r3: throwing pc)
 408   __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));  __ should_not_reach_here();
 409   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 410   __ end_a_stub();
 411 
 412   return offset;
 413 }
 414 
 415 
 416 // Emit the code to remove the frame from the stack in the exception
 417 // unwind path.
 418 int LIR_Assembler::emit_unwind_handler() {
 419 #ifndef PRODUCT
 420   if (CommentedAssembly) {
 421     _masm->block_comment("Unwind handler");
 422   }
 423 #endif
 424 
 425   int offset = code_offset();
 426 
 427   // Fetch the exception from TLS and clear out exception related thread state
 428   __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
 429   __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
 430   __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
 431 
 432   __ bind(_unwind_handler_entry);
 433   __ verify_not_null_oop(r0);
 434   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 435     __ mov(r19, r0);  // Preserve the exception
 436   }
 437 
 438   // Preform needed unlocking
 439   MonitorExitStub* stub = NULL;
 440   if (method()->is_synchronized()) {
 441     monitor_address(0, FrameMap::r0_opr);
 442     stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
 443     if (UseHeavyMonitors) {
 444       __ b(*stub->entry());
 445     } else {
 446       __ unlock_object(r5, r4, r0, *stub->entry());
 447     }
 448     __ bind(*stub->continuation());
 449   }
 450 
 451   if (compilation()->env()->dtrace_method_probes()) {
 452     __ mov(c_rarg0, rthread);
 453     __ mov_metadata(c_rarg1, method()->constant_encoding());
 454     __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
 455   }
 456 
 457   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 458     __ mov(r0, r19);  // Restore the exception
 459   }
 460 
 461   // remove the activation and dispatch to the unwind handler
 462   __ block_comment("remove_frame and dispatch to the unwind handler");
 463   __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
 464   __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 465 
 466   // Emit the slow path assembly
 467   if (stub != NULL) {
 468     stub->emit_code(this);
 469   }
 470 
 471   return offset;
 472 }
 473 
 474 
 475 int LIR_Assembler::emit_deopt_handler() {
 476   // if the last instruction is a call (typically to do a throw which
 477   // is coming at the end after block reordering) the return address
 478   // must still point into the code area in order to avoid assertion
 479   // failures when searching for the corresponding bci => add a nop
 480   // (was bug 5/14/1999 - gri)
 481   __ nop();
 482 
 483   // generate code for exception handler
 484   address handler_base = __ start_a_stub(deopt_handler_size());
 485   if (handler_base == NULL) {
 486     // not enough space left for the handler
 487     bailout("deopt handler overflow");
 488     return -1;
 489   }
 490 
 491   int offset = code_offset();
 492 
 493   __ adr(lr, pc());
 494   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 495   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 496   __ end_a_stub();
 497 
 498   return offset;
 499 }
 500 
 501 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
 502   _masm->code_section()->relocate(adr, relocInfo::poll_type);
 503   int pc_offset = code_offset();
 504   flush_debug_info(pc_offset);
 505   info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
 506   if (info->exception_handlers() != NULL) {
 507     compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
 508   }
 509 }
 510 
 511 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
 512   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
 513 
 514   ciMethod* method = compilation()->method();
 515   if (InlineTypeReturnedAsFields && method->return_type()->is_inlinetype()) {
 516     ciInlineKlass* vk = method->return_type()->as_inline_klass();
 517     if (vk->can_be_returned_as_fields()) {
 518       address unpack_handler = vk->unpack_handler();
 519       assert(unpack_handler != NULL, "must be");
 520       __ far_call(RuntimeAddress(unpack_handler));
 521       // At this point, r0 points to the value object (for interpreter or C1 caller).
 522       // The fields of the object are copied into registers (for C2 caller).
 523     }
 524   }
 525 
 526   // Pop the stack before the safepoint code
 527   __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
 528 
 529   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 530     __ reserved_stack_check();
 531   }
 532 
 533   code_stub->set_safepoint_offset(__ offset());
 534   __ relocate(relocInfo::poll_return_type);
 535   __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
 536   __ ret(lr);
 537 }
 538 
 539 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
 540   return (__ store_inline_type_fields_to_buf(vk, false));
 541 }
 542 
 543 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 544   guarantee(info != NULL, "Shouldn't be NULL");
 545   __ get_polling_page(rscratch1, relocInfo::poll_type);
 546   add_debug_info_for_branch(info);  // This isn't just debug info:
 547                                     // it's the oop map
 548   __ read_polling_page(rscratch1, relocInfo::poll_type);
 549   return __ offset();
 550 }
 551 
 552 
 553 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 554   if (from_reg == r31_sp)
 555     from_reg = sp;
 556   if (to_reg == r31_sp)
 557     to_reg = sp;
 558   __ mov(to_reg, from_reg);
 559 }
 560 
 561 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
 562 
 563 
 564 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 565   assert(src->is_constant(), "should not call otherwise");
 566   assert(dest->is_register(), "should not call otherwise");
 567   LIR_Const* c = src->as_constant_ptr();
 568 
 569   switch (c->type()) {
 570     case T_INT: {
 571       assert(patch_code == lir_patch_none, "no patching handled here");
 572       __ movw(dest->as_register(), c->as_jint());
 573       break;
 574     }
 575 
 576     case T_ADDRESS: {
 577       assert(patch_code == lir_patch_none, "no patching handled here");
 578       __ mov(dest->as_register(), c->as_jint());
 579       break;
 580     }
 581 
 582     case T_LONG: {
 583       assert(patch_code == lir_patch_none, "no patching handled here");
 584       __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
 585       break;
 586     }
 587 
 588     case T_PRIMITIVE_OBJECT:
 589     case T_OBJECT: {
 590         if (patch_code != lir_patch_none) {
 591           jobject2reg_with_patching(dest->as_register(), info);
 592         } else {
 593           jobject2reg(c->as_jobject(), dest->as_register());
 594         }
 595       break;
 596     }
 597 
 598     case T_METADATA: {
 599       if (patch_code != lir_patch_none) {
 600         klass2reg_with_patching(dest->as_register(), info);
 601       } else {
 602         __ mov_metadata(dest->as_register(), c->as_metadata());
 603       }
 604       break;
 605     }
 606 
 607     case T_FLOAT: {
 608       if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
 609         __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
 610       } else {
 611         __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
 612         __ ldrs(dest->as_float_reg(), Address(rscratch1));
 613       }
 614       break;
 615     }
 616 
 617     case T_DOUBLE: {
 618       if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
 619         __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
 620       } else {
 621         __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
 622         __ ldrd(dest->as_double_reg(), Address(rscratch1));
 623       }
 624       break;
 625     }
 626 
 627     default:
 628       ShouldNotReachHere();
 629   }
 630 }
 631 
 632 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 633   LIR_Const* c = src->as_constant_ptr();
 634   switch (c->type()) {
 635   case T_PRIMITIVE_OBJECT:
 636   case T_OBJECT:
 637     {
 638       if (! c->as_jobject())
 639         __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 640       else {
 641         const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 642         reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 643       }
 644     }
 645     break;
 646   case T_ADDRESS:
 647     {
 648       const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 649       reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 650     }
 651   case T_INT:
 652   case T_FLOAT:
 653     {
 654       Register reg = zr;
 655       if (c->as_jint_bits() == 0)
 656         __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 657       else {
 658         __ movw(rscratch1, c->as_jint_bits());
 659         __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
 660       }
 661     }
 662     break;
 663   case T_LONG:
 664   case T_DOUBLE:
 665     {
 666       Register reg = zr;
 667       if (c->as_jlong_bits() == 0)
 668         __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
 669                                                  lo_word_offset_in_bytes));
 670       else {
 671         __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
 672         __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
 673                                                         lo_word_offset_in_bytes));
 674       }
 675     }
 676     break;
 677   default:
 678     ShouldNotReachHere();
 679   }
 680 }
 681 
 682 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 683   assert(src->is_constant(), "should not call otherwise");
 684   LIR_Const* c = src->as_constant_ptr();
 685   LIR_Address* to_addr = dest->as_address_ptr();
 686 
 687   void (Assembler::* insn)(Register Rt, const Address &adr);
 688 
 689   switch (type) {
 690   case T_ADDRESS:
 691     assert(c->as_jint() == 0, "should be");
 692     insn = &Assembler::str;
 693     break;
 694   case T_LONG:
 695     assert(c->as_jlong() == 0, "should be");
 696     insn = &Assembler::str;
 697     break;
 698   case T_INT:
 699     assert(c->as_jint() == 0, "should be");
 700     insn = &Assembler::strw;
 701     break;
 702   case T_PRIMITIVE_OBJECT:
 703   case T_OBJECT:
 704   case T_ARRAY:
 705     // Non-null case is not handled on aarch64 but handled on x86
 706     // FIXME: do we need to add it here?
 707     assert(c->as_jobject() == 0, "should be");
 708     if (UseCompressedOops && !wide) {
 709       insn = &Assembler::strw;
 710     } else {
 711       insn = &Assembler::str;
 712     }
 713     break;
 714   case T_CHAR:
 715   case T_SHORT:
 716     assert(c->as_jint() == 0, "should be");
 717     insn = &Assembler::strh;
 718     break;
 719   case T_BOOLEAN:
 720   case T_BYTE:
 721     assert(c->as_jint() == 0, "should be");
 722     insn = &Assembler::strb;
 723     break;
 724   default:
 725     ShouldNotReachHere();
 726     insn = &Assembler::str;  // unreachable
 727   }
 728 
 729   if (info) add_debug_info_for_null_check_here(info);
 730   (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
 731 }
 732 
 733 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 734   assert(src->is_register(), "should not call otherwise");
 735   assert(dest->is_register(), "should not call otherwise");
 736 
 737   // move between cpu-registers
 738   if (dest->is_single_cpu()) {
 739     if (src->type() == T_LONG) {
 740       // Can do LONG -> OBJECT
 741       move_regs(src->as_register_lo(), dest->as_register());
 742       return;
 743     }
 744     assert(src->is_single_cpu(), "must match");
 745     if (src->type() == T_OBJECT || src->type() == T_PRIMITIVE_OBJECT) {
 746       __ verify_oop(src->as_register());
 747     }
 748     move_regs(src->as_register(), dest->as_register());
 749 
 750   } else if (dest->is_double_cpu()) {
 751     if (is_reference_type(src->type())) {
 752       // Surprising to me but we can see move of a long to t_object
 753       __ verify_oop(src->as_register());
 754       move_regs(src->as_register(), dest->as_register_lo());
 755       return;
 756     }
 757     assert(src->is_double_cpu(), "must match");
 758     Register f_lo = src->as_register_lo();
 759     Register f_hi = src->as_register_hi();
 760     Register t_lo = dest->as_register_lo();
 761     Register t_hi = dest->as_register_hi();
 762     assert(f_hi == f_lo, "must be same");
 763     assert(t_hi == t_lo, "must be same");
 764     move_regs(f_lo, t_lo);
 765 
 766   } else if (dest->is_single_fpu()) {
 767     __ fmovs(dest->as_float_reg(), src->as_float_reg());
 768 
 769   } else if (dest->is_double_fpu()) {
 770     __ fmovd(dest->as_double_reg(), src->as_double_reg());
 771 
 772   } else {
 773     ShouldNotReachHere();
 774   }
 775 }
 776 
 777 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 778   precond(src->is_register() && dest->is_stack());
 779 
 780   uint const c_sz32 = sizeof(uint32_t);
 781   uint const c_sz64 = sizeof(uint64_t);
 782 
 783   if (src->is_single_cpu()) {
 784     int index = dest->single_stack_ix();
 785     if (is_reference_type(type)) {
 786       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 787       __ verify_oop(src->as_register());
 788     } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
 789       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 790     } else {
 791       __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 792     }
 793 
 794   } else if (src->is_double_cpu()) {
 795     int index = dest->double_stack_ix();
 796     Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 797     __ str(src->as_register_lo(), dest_addr_LO);
 798 
 799   } else if (src->is_single_fpu()) {
 800     int index = dest->single_stack_ix();
 801     __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 802 
 803   } else if (src->is_double_fpu()) {
 804     int index = dest->double_stack_ix();
 805     __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 806 
 807   } else {
 808     ShouldNotReachHere();
 809   }
 810 }
 811 
 812 
 813 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
 814   LIR_Address* to_addr = dest->as_address_ptr();
 815   PatchingStub* patch = NULL;
 816   Register compressed_src = rscratch1;
 817 
 818   if (patch_code != lir_patch_none) {
 819     deoptimize_trap(info);
 820     return;
 821   }
 822 
 823   if (is_reference_type(type)) {
 824     __ verify_oop(src->as_register());
 825 
 826     if (UseCompressedOops && !wide) {
 827       __ encode_heap_oop(compressed_src, src->as_register());
 828     } else {
 829       compressed_src = src->as_register();
 830     }
 831   }
 832 
 833   int null_check_here = code_offset();
 834   switch (type) {
 835     case T_FLOAT: {
 836       __ strs(src->as_float_reg(), as_Address(to_addr));
 837       break;
 838     }
 839 
 840     case T_DOUBLE: {
 841       __ strd(src->as_double_reg(), as_Address(to_addr));
 842       break;
 843     }
 844 
 845     case T_PRIMITIVE_OBJECT: // fall through
 846     case T_ARRAY:   // fall through
 847     case T_OBJECT:  // fall through
 848       if (UseCompressedOops && !wide) {
 849         __ strw(compressed_src, as_Address(to_addr, rscratch2));
 850       } else {
 851          __ str(compressed_src, as_Address(to_addr));
 852       }
 853       break;
 854     case T_METADATA:
 855       // We get here to store a method pointer to the stack to pass to
 856       // a dtrace runtime call. This can't work on 64 bit with
 857       // compressed klass ptrs: T_METADATA can be a compressed klass
 858       // ptr or a 64 bit method pointer.
 859       ShouldNotReachHere();
 860       __ str(src->as_register(), as_Address(to_addr));
 861       break;
 862     case T_ADDRESS:
 863       __ str(src->as_register(), as_Address(to_addr));
 864       break;
 865     case T_INT:
 866       __ strw(src->as_register(), as_Address(to_addr));
 867       break;
 868 
 869     case T_LONG: {
 870       __ str(src->as_register_lo(), as_Address_lo(to_addr));
 871       break;
 872     }
 873 
 874     case T_BYTE:    // fall through
 875     case T_BOOLEAN: {
 876       __ strb(src->as_register(), as_Address(to_addr));
 877       break;
 878     }
 879 
 880     case T_CHAR:    // fall through
 881     case T_SHORT:
 882       __ strh(src->as_register(), as_Address(to_addr));
 883       break;
 884 
 885     default:
 886       ShouldNotReachHere();
 887   }
 888   if (info != NULL) {
 889     add_debug_info_for_null_check(null_check_here, info);
 890   }
 891 }
 892 
 893 
 894 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
 895   precond(src->is_stack() && dest->is_register());
 896 
 897   uint const c_sz32 = sizeof(uint32_t);
 898   uint const c_sz64 = sizeof(uint64_t);
 899 
 900   if (dest->is_single_cpu()) {
 901     int index = src->single_stack_ix();
 902     if (is_reference_type(type)) {
 903       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 904       __ verify_oop(dest->as_register());
 905     } else if (type == T_METADATA || type == T_ADDRESS) {
 906       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 907     } else {
 908       __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 909     }
 910 
 911   } else if (dest->is_double_cpu()) {
 912     int index = src->double_stack_ix();
 913     Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 914     __ ldr(dest->as_register_lo(), src_addr_LO);
 915 
 916   } else if (dest->is_single_fpu()) {
 917     int index = src->single_stack_ix();
 918     __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 919 
 920   } else if (dest->is_double_fpu()) {
 921     int index = src->double_stack_ix();
 922     __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 923 
 924   } else {
 925     ShouldNotReachHere();
 926   }
 927 }
 928 
 929 
 930 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 931   address target = NULL;
 932   relocInfo::relocType reloc_type = relocInfo::none;
 933 
 934   switch (patching_id(info)) {
 935   case PatchingStub::access_field_id:
 936     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 937     reloc_type = relocInfo::section_word_type;
 938     break;
 939   case PatchingStub::load_klass_id:
 940     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 941     reloc_type = relocInfo::metadata_type;
 942     break;
 943   case PatchingStub::load_mirror_id:
 944     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 945     reloc_type = relocInfo::oop_type;
 946     break;
 947   case PatchingStub::load_appendix_id:
 948     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 949     reloc_type = relocInfo::oop_type;
 950     break;
 951   default: ShouldNotReachHere();
 952   }
 953 
 954   __ far_call(RuntimeAddress(target));
 955   add_call_info_here(info);
 956 }
 957 
 958 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 959 
 960   LIR_Opr temp;
 961   if (type == T_LONG || type == T_DOUBLE)
 962     temp = FrameMap::rscratch1_long_opr;
 963   else
 964     temp = FrameMap::rscratch1_opr;
 965 
 966   stack2reg(src, temp, src->type());
 967   reg2stack(temp, dest, dest->type(), false);
 968 }
 969 
 970 
 971 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
 972   LIR_Address* addr = src->as_address_ptr();
 973   LIR_Address* from_addr = src->as_address_ptr();
 974 
 975   if (addr->base()->type() == T_OBJECT || addr->base()->type() == T_PRIMITIVE_OBJECT) {
 976     __ verify_oop(addr->base()->as_pointer_register());
 977   }
 978 
 979   if (patch_code != lir_patch_none) {
 980     deoptimize_trap(info);
 981     return;
 982   }
 983 
 984   if (info != NULL) {
 985     add_debug_info_for_null_check_here(info);
 986   }
 987   int null_check_here = code_offset();
 988   switch (type) {
 989     case T_FLOAT: {
 990       __ ldrs(dest->as_float_reg(), as_Address(from_addr));
 991       break;
 992     }
 993 
 994     case T_DOUBLE: {
 995       __ ldrd(dest->as_double_reg(), as_Address(from_addr));
 996       break;
 997     }
 998 
 999     case T_PRIMITIVE_OBJECT: // fall through
1000     case T_ARRAY:   // fall through
1001     case T_OBJECT:  // fall through
1002       if (UseCompressedOops && !wide) {
1003         __ ldrw(dest->as_register(), as_Address(from_addr));
1004       } else {
1005          __ ldr(dest->as_register(), as_Address(from_addr));
1006       }
1007       break;
1008     case T_METADATA:
1009       // We get here to store a method pointer to the stack to pass to
1010       // a dtrace runtime call. This can't work on 64 bit with
1011       // compressed klass ptrs: T_METADATA can be a compressed klass
1012       // ptr or a 64 bit method pointer.
1013       ShouldNotReachHere();
1014       __ ldr(dest->as_register(), as_Address(from_addr));
1015       break;
1016     case T_ADDRESS:
1017       __ ldr(dest->as_register(), as_Address(from_addr));
1018       break;
1019     case T_INT:
1020       __ ldrw(dest->as_register(), as_Address(from_addr));
1021       break;
1022 
1023     case T_LONG: {
1024       __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1025       break;
1026     }
1027 
1028     case T_BYTE:
1029       __ ldrsb(dest->as_register(), as_Address(from_addr));
1030       break;
1031     case T_BOOLEAN: {
1032       __ ldrb(dest->as_register(), as_Address(from_addr));
1033       break;
1034     }
1035 
1036     case T_CHAR:
1037       __ ldrh(dest->as_register(), as_Address(from_addr));
1038       break;
1039     case T_SHORT:
1040       __ ldrsh(dest->as_register(), as_Address(from_addr));
1041       break;
1042 
1043     default:
1044       ShouldNotReachHere();
1045   }
1046 
1047   if (is_reference_type(type)) {
1048     if (UseCompressedOops && !wide) {
1049       __ decode_heap_oop(dest->as_register());
1050     }
1051 
1052     if (!UseZGC) {
1053       // Load barrier has not yet been applied, so ZGC can't verify the oop here
1054       __ verify_oop(dest->as_register());
1055     }
1056   }
1057 }
1058 
1059 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
1060   assert(dst->is_cpu_register(), "must be");
1061   assert(dst->type() == src->type(), "must be");
1062 
1063   if (src->is_cpu_register()) {
1064     reg2reg(src, dst);
1065   } else if (src->is_stack()) {
1066     stack2reg(src, dst, dst->type());
1067   } else if (src->is_constant()) {
1068     const2reg(src, dst, lir_patch_none, NULL);
1069   } else {
1070     ShouldNotReachHere();
1071   }
1072 }
1073 
1074 int LIR_Assembler::array_element_size(BasicType type) const {
1075   int elem_size = type2aelembytes(type);
1076   return exact_log2(elem_size);
1077 }
1078 
1079 
1080 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1081   switch (op->code()) {
1082   case lir_idiv:
1083   case lir_irem:
1084     arithmetic_idiv(op->code(),
1085                     op->in_opr1(),
1086                     op->in_opr2(),
1087                     op->in_opr3(),
1088                     op->result_opr(),
1089                     op->info());
1090     break;
1091   case lir_fmad:
1092     __ fmaddd(op->result_opr()->as_double_reg(),
1093               op->in_opr1()->as_double_reg(),
1094               op->in_opr2()->as_double_reg(),
1095               op->in_opr3()->as_double_reg());
1096     break;
1097   case lir_fmaf:
1098     __ fmadds(op->result_opr()->as_float_reg(),
1099               op->in_opr1()->as_float_reg(),
1100               op->in_opr2()->as_float_reg(),
1101               op->in_opr3()->as_float_reg());
1102     break;
1103   default:      ShouldNotReachHere(); break;
1104   }
1105 }
1106 
1107 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1108 #ifdef ASSERT
1109   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1110   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1111   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1112 #endif
1113 
1114   if (op->cond() == lir_cond_always) {
1115     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1116     __ b(*(op->label()));
1117   } else {
1118     Assembler::Condition acond;
1119     if (op->code() == lir_cond_float_branch) {
1120       bool is_unordered = (op->ublock() == op->block());
1121       // Assembler::EQ does not permit unordered branches, so we add
1122       // another branch here.  Likewise, Assembler::NE does not permit
1123       // ordered branches.
1124       if ((is_unordered && op->cond() == lir_cond_equal)
1125           || (!is_unordered && op->cond() == lir_cond_notEqual))
1126         __ br(Assembler::VS, *(op->ublock()->label()));
1127       switch(op->cond()) {
1128       case lir_cond_equal:        acond = Assembler::EQ; break;
1129       case lir_cond_notEqual:     acond = Assembler::NE; break;
1130       case lir_cond_less:         acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1131       case lir_cond_lessEqual:    acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1132       case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1133       case lir_cond_greater:      acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1134       default:                    ShouldNotReachHere();
1135         acond = Assembler::EQ;  // unreachable
1136       }
1137     } else {
1138       switch (op->cond()) {
1139         case lir_cond_equal:        acond = Assembler::EQ; break;
1140         case lir_cond_notEqual:     acond = Assembler::NE; break;
1141         case lir_cond_less:         acond = Assembler::LT; break;
1142         case lir_cond_lessEqual:    acond = Assembler::LE; break;
1143         case lir_cond_greaterEqual: acond = Assembler::GE; break;
1144         case lir_cond_greater:      acond = Assembler::GT; break;
1145         case lir_cond_belowEqual:   acond = Assembler::LS; break;
1146         case lir_cond_aboveEqual:   acond = Assembler::HS; break;
1147         default:                    ShouldNotReachHere();
1148           acond = Assembler::EQ;  // unreachable
1149       }
1150     }
1151     __ br(acond,*(op->label()));
1152   }
1153 }
1154 
1155 
1156 
1157 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1158   LIR_Opr src  = op->in_opr();
1159   LIR_Opr dest = op->result_opr();
1160 
1161   switch (op->bytecode()) {
1162     case Bytecodes::_i2f:
1163       {
1164         __ scvtfws(dest->as_float_reg(), src->as_register());
1165         break;
1166       }
1167     case Bytecodes::_i2d:
1168       {
1169         __ scvtfwd(dest->as_double_reg(), src->as_register());
1170         break;
1171       }
1172     case Bytecodes::_l2d:
1173       {
1174         __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1175         break;
1176       }
1177     case Bytecodes::_l2f:
1178       {
1179         __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1180         break;
1181       }
1182     case Bytecodes::_f2d:
1183       {
1184         __ fcvts(dest->as_double_reg(), src->as_float_reg());
1185         break;
1186       }
1187     case Bytecodes::_d2f:
1188       {
1189         __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1190         break;
1191       }
1192     case Bytecodes::_i2c:
1193       {
1194         __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1195         break;
1196       }
1197     case Bytecodes::_i2l:
1198       {
1199         __ sxtw(dest->as_register_lo(), src->as_register());
1200         break;
1201       }
1202     case Bytecodes::_i2s:
1203       {
1204         __ sxth(dest->as_register(), src->as_register());
1205         break;
1206       }
1207     case Bytecodes::_i2b:
1208       {
1209         __ sxtb(dest->as_register(), src->as_register());
1210         break;
1211       }
1212     case Bytecodes::_l2i:
1213       {
1214         _masm->block_comment("FIXME: This could be a no-op");
1215         __ uxtw(dest->as_register(), src->as_register_lo());
1216         break;
1217       }
1218     case Bytecodes::_d2l:
1219       {
1220         __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1221         break;
1222       }
1223     case Bytecodes::_f2i:
1224       {
1225         __ fcvtzsw(dest->as_register(), src->as_float_reg());
1226         break;
1227       }
1228     case Bytecodes::_f2l:
1229       {
1230         __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1231         break;
1232       }
1233     case Bytecodes::_d2i:
1234       {
1235         __ fcvtzdw(dest->as_register(), src->as_double_reg());
1236         break;
1237       }
1238     default: ShouldNotReachHere();
1239   }
1240 }
1241 
1242 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1243   if (op->init_check()) {
1244     __ ldrb(rscratch1, Address(op->klass()->as_register(),
1245                                InstanceKlass::init_state_offset()));
1246     __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1247     add_debug_info_for_null_check_here(op->stub()->info());
1248     __ br(Assembler::NE, *op->stub()->entry());
1249   }
1250   __ allocate_object(op->obj()->as_register(),
1251                      op->tmp1()->as_register(),
1252                      op->tmp2()->as_register(),
1253                      op->header_size(),
1254                      op->object_size(),
1255                      op->klass()->as_register(),
1256                      *op->stub()->entry());
1257   __ bind(*op->stub()->continuation());
1258 }
1259 
1260 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1261   Register len =  op->len()->as_register();
1262   __ uxtw(len, len);
1263 
1264   if (UseSlowPath || op->type() == T_PRIMITIVE_OBJECT ||
1265       (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1266       (!UseFastNewTypeArray   && !is_reference_type(op->type()))) {
1267     __ b(*op->stub()->entry());
1268   } else {
1269     Register tmp1 = op->tmp1()->as_register();
1270     Register tmp2 = op->tmp2()->as_register();
1271     Register tmp3 = op->tmp3()->as_register();
1272     if (len == tmp1) {
1273       tmp1 = tmp3;
1274     } else if (len == tmp2) {
1275       tmp2 = tmp3;
1276     } else if (len == tmp3) {
1277       // everything is ok
1278     } else {
1279       __ mov(tmp3, len);
1280     }
1281     __ allocate_array(op->obj()->as_register(),
1282                       len,
1283                       tmp1,
1284                       tmp2,
1285                       arrayOopDesc::header_size(op->type()),
1286                       array_element_size(op->type()),
1287                       op->klass()->as_register(),
1288                       *op->stub()->entry());
1289   }
1290   __ bind(*op->stub()->continuation());
1291 }
1292 
1293 void LIR_Assembler::type_profile_helper(Register mdo,
1294                                         ciMethodData *md, ciProfileData *data,
1295                                         Register recv, Label* update_done) {
1296   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1297     Label next_test;
1298     // See if the receiver is receiver[n].
1299     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1300     __ ldr(rscratch1, Address(rscratch2));
1301     __ cmp(recv, rscratch1);
1302     __ br(Assembler::NE, next_test);
1303     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1304     __ addptr(data_addr, DataLayout::counter_increment);
1305     __ b(*update_done);
1306     __ bind(next_test);
1307   }
1308 
1309   // Didn't find receiver; find next empty slot and fill it in
1310   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1311     Label next_test;
1312     __ lea(rscratch2,
1313            Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1314     Address recv_addr(rscratch2);
1315     __ ldr(rscratch1, recv_addr);
1316     __ cbnz(rscratch1, next_test);
1317     __ str(recv, recv_addr);
1318     __ mov(rscratch1, DataLayout::counter_increment);
1319     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1320     __ str(rscratch1, Address(rscratch2));
1321     __ b(*update_done);
1322     __ bind(next_test);
1323   }
1324 }
1325 
1326 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1327   // we always need a stub for the failure case.
1328   CodeStub* stub = op->stub();
1329   Register obj = op->object()->as_register();
1330   Register k_RInfo = op->tmp1()->as_register();
1331   Register klass_RInfo = op->tmp2()->as_register();
1332   Register dst = op->result_opr()->as_register();
1333   ciKlass* k = op->klass();
1334   Register Rtmp1 = noreg;
1335 
1336   // check if it needs to be profiled
1337   ciMethodData* md;
1338   ciProfileData* data;
1339 
1340   const bool should_profile = op->should_profile();
1341 
1342   if (should_profile) {
1343     ciMethod* method = op->profiled_method();
1344     assert(method != NULL, "Should have method");
1345     int bci = op->profiled_bci();
1346     md = method->method_data_or_null();
1347     assert(md != NULL, "Sanity");
1348     data = md->bci_to_data(bci);
1349     assert(data != NULL,                "need data for type check");
1350     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1351   }
1352   Label profile_cast_success, profile_cast_failure;
1353   Label *success_target = should_profile ? &profile_cast_success : success;
1354   Label *failure_target = should_profile ? &profile_cast_failure : failure;
1355 
1356   if (obj == k_RInfo) {
1357     k_RInfo = dst;
1358   } else if (obj == klass_RInfo) {
1359     klass_RInfo = dst;
1360   }
1361   if (k->is_loaded() && !UseCompressedClassPointers) {
1362     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1363   } else {
1364     Rtmp1 = op->tmp3()->as_register();
1365     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1366   }
1367 
1368   assert_different_registers(obj, k_RInfo, klass_RInfo);
1369 
1370   if (op->need_null_check()) {
1371     if (should_profile) {
1372       Label not_null;
1373       __ cbnz(obj, not_null);
1374       // Object is null; update MDO and exit
1375       Register mdo  = klass_RInfo;
1376       __ mov_metadata(mdo, md->constant_encoding());
1377       Address data_addr
1378         = __ form_address(rscratch2, mdo,
1379                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1380                           0);
1381       __ ldrb(rscratch1, data_addr);
1382       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1383       __ strb(rscratch1, data_addr);
1384       __ b(*obj_is_null);
1385       __ bind(not_null);
1386     } else {
1387       __ cbz(obj, *obj_is_null);
1388     }
1389   }
1390 
1391   if (!k->is_loaded()) {
1392     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1393   } else {
1394     __ mov_metadata(k_RInfo, k->constant_encoding());
1395   }
1396   __ verify_oop(obj);
1397 
1398   if (op->fast_check()) {
1399     // get object class
1400     // not a safepoint as obj null check happens earlier
1401     __ load_klass(rscratch1, obj);
1402     __ cmp( rscratch1, k_RInfo);
1403 
1404     __ br(Assembler::NE, *failure_target);
1405     // successful cast, fall through to profile or jump
1406   } else {
1407     // get object class
1408     // not a safepoint as obj null check happens earlier
1409     __ load_klass(klass_RInfo, obj);
1410     if (k->is_loaded()) {
1411       // See if we get an immediate positive hit
1412       __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1413       __ cmp(k_RInfo, rscratch1);
1414       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1415         __ br(Assembler::NE, *failure_target);
1416         // successful cast, fall through to profile or jump
1417       } else {
1418         // See if we get an immediate positive hit
1419         __ br(Assembler::EQ, *success_target);
1420         // check for self
1421         __ cmp(klass_RInfo, k_RInfo);
1422         __ br(Assembler::EQ, *success_target);
1423 
1424         __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1425         __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1426         __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1427         // result is a boolean
1428         __ cbzw(klass_RInfo, *failure_target);
1429         // successful cast, fall through to profile or jump
1430       }
1431     } else {
1432       // perform the fast part of the checking logic
1433       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1434       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1435       __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1436       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1437       __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1438       // result is a boolean
1439       __ cbz(k_RInfo, *failure_target);
1440       // successful cast, fall through to profile or jump
1441     }
1442   }
1443   if (should_profile) {
1444     Register mdo  = klass_RInfo, recv = k_RInfo;
1445     __ bind(profile_cast_success);
1446     __ mov_metadata(mdo, md->constant_encoding());
1447     __ load_klass(recv, obj);
1448     Label update_done;
1449     type_profile_helper(mdo, md, data, recv, success);
1450     __ b(*success);
1451 
1452     __ bind(profile_cast_failure);
1453     __ mov_metadata(mdo, md->constant_encoding());
1454     Address counter_addr
1455       = __ form_address(rscratch2, mdo,
1456                         md->byte_offset_of_slot(data, CounterData::count_offset()),
1457                         0);
1458     __ ldr(rscratch1, counter_addr);
1459     __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1460     __ str(rscratch1, counter_addr);
1461     __ b(*failure);
1462   }
1463   __ b(*success);
1464 }
1465 
1466 
1467 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1468   const bool should_profile = op->should_profile();
1469 
1470   LIR_Code code = op->code();
1471   if (code == lir_store_check) {
1472     Register value = op->object()->as_register();
1473     Register array = op->array()->as_register();
1474     Register k_RInfo = op->tmp1()->as_register();
1475     Register klass_RInfo = op->tmp2()->as_register();
1476     Register Rtmp1 = op->tmp3()->as_register();
1477 
1478     CodeStub* stub = op->stub();
1479 
1480     // check if it needs to be profiled
1481     ciMethodData* md;
1482     ciProfileData* data;
1483 
1484     if (should_profile) {
1485       ciMethod* method = op->profiled_method();
1486       assert(method != NULL, "Should have method");
1487       int bci = op->profiled_bci();
1488       md = method->method_data_or_null();
1489       assert(md != NULL, "Sanity");
1490       data = md->bci_to_data(bci);
1491       assert(data != NULL,                "need data for type check");
1492       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1493     }
1494     Label profile_cast_success, profile_cast_failure, done;
1495     Label *success_target = should_profile ? &profile_cast_success : &done;
1496     Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1497 
1498     if (should_profile) {
1499       Label not_null;
1500       __ cbnz(value, not_null);
1501       // Object is null; update MDO and exit
1502       Register mdo  = klass_RInfo;
1503       __ mov_metadata(mdo, md->constant_encoding());
1504       Address data_addr
1505         = __ form_address(rscratch2, mdo,
1506                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1507                           0);
1508       __ ldrb(rscratch1, data_addr);
1509       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1510       __ strb(rscratch1, data_addr);
1511       __ b(done);
1512       __ bind(not_null);
1513     } else {
1514       __ cbz(value, done);
1515     }
1516 
1517     add_debug_info_for_null_check_here(op->info_for_exception());
1518     __ load_klass(k_RInfo, array);
1519     __ load_klass(klass_RInfo, value);
1520 
1521     // get instance klass (it's already uncompressed)
1522     __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1523     // perform the fast part of the checking logic
1524     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1525     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1526     __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1527     __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1528     __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1529     // result is a boolean
1530     __ cbzw(k_RInfo, *failure_target);
1531     // fall through to the success case
1532 
1533     if (should_profile) {
1534       Register mdo  = klass_RInfo, recv = k_RInfo;
1535       __ bind(profile_cast_success);
1536       __ mov_metadata(mdo, md->constant_encoding());
1537       __ load_klass(recv, value);
1538       Label update_done;
1539       type_profile_helper(mdo, md, data, recv, &done);
1540       __ b(done);
1541 
1542       __ bind(profile_cast_failure);
1543       __ mov_metadata(mdo, md->constant_encoding());
1544       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1545       __ lea(rscratch2, counter_addr);
1546       __ ldr(rscratch1, Address(rscratch2));
1547       __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1548       __ str(rscratch1, Address(rscratch2));
1549       __ b(*stub->entry());
1550     }
1551 
1552     __ bind(done);
1553   } else if (code == lir_checkcast) {
1554     Register obj = op->object()->as_register();
1555     Register dst = op->result_opr()->as_register();
1556     Label success;
1557     emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1558     __ bind(success);
1559     if (dst != obj) {
1560       __ mov(dst, obj);
1561     }
1562   } else if (code == lir_instanceof) {
1563     Register obj = op->object()->as_register();
1564     Register dst = op->result_opr()->as_register();
1565     Label success, failure, done;
1566     emit_typecheck_helper(op, &success, &failure, &failure);
1567     __ bind(failure);
1568     __ mov(dst, zr);
1569     __ b(done);
1570     __ bind(success);
1571     __ mov(dst, 1);
1572     __ bind(done);
1573   } else {
1574     ShouldNotReachHere();
1575   }
1576 }
1577 
1578 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1579   // We are loading/storing from/to an array that *may* be flattened (the
1580   // declared type is Object[], abstract[], interface[] or VT.ref[]).
1581   // If this array is flattened, take the slow path.
1582 
1583   Register klass = op->tmp()->as_register();
1584   if (UseArrayMarkWordCheck) {
1585     __ test_flattened_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1586   } else {
1587     __ load_klass(klass, op->array()->as_register());
1588     __ ldrw(klass, Address(klass, Klass::layout_helper_offset()));
1589     __ tst(klass, Klass::_lh_array_tag_flat_value_bit_inplace);
1590     __ br(Assembler::NE, *op->stub()->entry());
1591   }
1592   if (!op->value()->is_illegal()) {
1593     // The array is not flattened, but it might be null-free. If we are storing
1594     // a null into a null-free array, take the slow path (which will throw NPE).
1595     Label skip;
1596     __ cbnz(op->value()->as_register(), skip);
1597     if (UseArrayMarkWordCheck) {
1598       __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1599     } else {
1600       __ tst(klass, Klass::_lh_null_free_array_bit_inplace);
1601       __ br(Assembler::NE, *op->stub()->entry());
1602     }
1603     __ bind(skip);
1604   }
1605 }
1606 
1607 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1608   // We are storing into an array that *may* be null-free (the declared type is
1609   // Object[], abstract[], interface[] or VT.ref[]).
1610   if (UseArrayMarkWordCheck) {
1611     Label test_mark_word;
1612     Register tmp = op->tmp()->as_register();
1613     __ ldr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
1614     __ tst(tmp, markWord::unlocked_value);
1615     __ br(Assembler::NE, test_mark_word);
1616     __ load_prototype_header(tmp, op->array()->as_register());
1617     __ bind(test_mark_word);
1618     __ tst(tmp, markWord::null_free_array_bit_in_place);
1619   } else {
1620     Register klass = op->tmp()->as_register();
1621     __ load_klass(klass, op->array()->as_register());
1622     __ ldr(klass, Address(klass, Klass::layout_helper_offset()));
1623     __ tst(klass, Klass::_lh_null_free_array_bit_inplace);
1624   }
1625 }
1626 
1627 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1628   Label L_oops_equal;
1629   Label L_oops_not_equal;
1630   Label L_end;
1631 
1632   Register left  = op->left()->as_register();
1633   Register right = op->right()->as_register();
1634 
1635   __ cmp(left, right);
1636   __ br(Assembler::EQ, L_oops_equal);
1637 
1638   // (1) Null check -- if one of the operands is null, the other must not be null (because
1639   //     the two references are not equal), so they are not substitutable,
1640   //     FIXME: do null check only if the operand is nullable
1641   {
1642     __ cbz(left, L_oops_not_equal);
1643     __ cbz(right, L_oops_not_equal);
1644   }
1645 
1646   ciKlass* left_klass = op->left_klass();
1647   ciKlass* right_klass = op->right_klass();
1648 
1649   // (2) Inline type check -- if either of the operands is not a inline type,
1650   //     they are not substitutable. We do this only if we are not sure that the
1651   //     operands are inline type
1652   if ((left_klass == NULL || right_klass == NULL) ||// The klass is still unloaded, or came from a Phi node.
1653       !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
1654     Register tmp1  = op->tmp1()->as_register();
1655     __ mov(tmp1, markWord::inline_type_pattern);
1656     __ ldr(rscratch1, Address(left, oopDesc::mark_offset_in_bytes()));
1657     __ andr(tmp1, tmp1, rscratch1);
1658     __ ldr(rscratch1, Address(right, oopDesc::mark_offset_in_bytes()));
1659     __ andr(tmp1, tmp1, rscratch1);
1660     __ cmp(tmp1, (u1)markWord::inline_type_pattern);
1661     __ br(Assembler::NE, L_oops_not_equal);
1662   }
1663 
1664   // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
1665   if (left_klass != NULL && left_klass->is_inlinetype() && left_klass == right_klass) {
1666     // No need to load klass -- the operands are statically known to be the same inline klass.
1667     __ b(*op->stub()->entry());
1668   } else {
1669     Register left_klass_op = op->left_klass_op()->as_register();
1670     Register right_klass_op = op->right_klass_op()->as_register();
1671 
1672     if (UseCompressedClassPointers) {
1673       __ ldrw(left_klass_op,  Address(left,  oopDesc::klass_offset_in_bytes()));
1674       __ ldrw(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1675       __ cmpw(left_klass_op, right_klass_op);
1676     } else {
1677       __ ldr(left_klass_op,  Address(left,  oopDesc::klass_offset_in_bytes()));
1678       __ ldr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1679       __ cmp(left_klass_op, right_klass_op);
1680     }
1681 
1682     __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check
1683     // fall through to L_oops_not_equal
1684   }
1685 
1686   __ bind(L_oops_not_equal);
1687   move(op->not_equal_result(), op->result_opr());
1688   __ b(L_end);
1689 
1690   __ bind(L_oops_equal);
1691   move(op->equal_result(), op->result_opr());
1692   __ b(L_end);
1693 
1694   // We've returned from the stub. R0 contains 0x0 IFF the two
1695   // operands are not substitutable. (Don't compare against 0x1 in case the
1696   // C compiler is naughty)
1697   __ bind(*op->stub()->continuation());
1698   __ cbz(r0, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1699   move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
1700   // fall-through
1701   __ bind(L_end);
1702 }
1703 
1704 
1705 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1706   __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1707   __ cset(rscratch1, Assembler::NE);
1708   __ membar(__ AnyAny);
1709 }
1710 
1711 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1712   __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1713   __ cset(rscratch1, Assembler::NE);
1714   __ membar(__ AnyAny);
1715 }
1716 
1717 
1718 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1719   assert(VM_Version::supports_cx8(), "wrong machine");
1720   Register addr;
1721   if (op->addr()->is_register()) {
1722     addr = as_reg(op->addr());
1723   } else {
1724     assert(op->addr()->is_address(), "what else?");
1725     LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1726     assert(addr_ptr->disp() == 0, "need 0 disp");
1727     assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1728     addr = as_reg(addr_ptr->base());
1729   }
1730   Register newval = as_reg(op->new_value());
1731   Register cmpval = as_reg(op->cmp_value());
1732 
1733   if (op->code() == lir_cas_obj) {
1734     if (UseCompressedOops) {
1735       Register t1 = op->tmp1()->as_register();
1736       assert(op->tmp1()->is_valid(), "must be");
1737       __ encode_heap_oop(t1, cmpval);
1738       cmpval = t1;
1739       __ encode_heap_oop(rscratch2, newval);
1740       newval = rscratch2;
1741       casw(addr, newval, cmpval);
1742     } else {
1743       casl(addr, newval, cmpval);
1744     }
1745   } else if (op->code() == lir_cas_int) {
1746     casw(addr, newval, cmpval);
1747   } else {
1748     casl(addr, newval, cmpval);
1749   }
1750 }
1751 
1752 
1753 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1754 
1755   Assembler::Condition acond, ncond;
1756   switch (condition) {
1757   case lir_cond_equal:        acond = Assembler::EQ; ncond = Assembler::NE; break;
1758   case lir_cond_notEqual:     acond = Assembler::NE; ncond = Assembler::EQ; break;
1759   case lir_cond_less:         acond = Assembler::LT; ncond = Assembler::GE; break;
1760   case lir_cond_lessEqual:    acond = Assembler::LE; ncond = Assembler::GT; break;
1761   case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1762   case lir_cond_greater:      acond = Assembler::GT; ncond = Assembler::LE; break;
1763   case lir_cond_belowEqual:
1764   case lir_cond_aboveEqual:
1765   default:                    ShouldNotReachHere();
1766     acond = Assembler::EQ; ncond = Assembler::NE;  // unreachable
1767   }
1768 
1769   assert(result->is_single_cpu() || result->is_double_cpu(),
1770          "expect single register for result");
1771   if (opr1->is_constant() && opr2->is_constant()
1772       && opr1->type() == T_INT && opr2->type() == T_INT) {
1773     jint val1 = opr1->as_jint();
1774     jint val2 = opr2->as_jint();
1775     if (val1 == 0 && val2 == 1) {
1776       __ cset(result->as_register(), ncond);
1777       return;
1778     } else if (val1 == 1 && val2 == 0) {
1779       __ cset(result->as_register(), acond);
1780       return;
1781     }
1782   }
1783 
1784   if (opr1->is_constant() && opr2->is_constant()
1785       && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1786     jlong val1 = opr1->as_jlong();
1787     jlong val2 = opr2->as_jlong();
1788     if (val1 == 0 && val2 == 1) {
1789       __ cset(result->as_register_lo(), ncond);
1790       return;
1791     } else if (val1 == 1 && val2 == 0) {
1792       __ cset(result->as_register_lo(), acond);
1793       return;
1794     }
1795   }
1796 
1797   if (opr1->is_stack()) {
1798     stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1799     opr1 = FrameMap::rscratch1_opr;
1800   } else if (opr1->is_constant()) {
1801     LIR_Opr tmp
1802       = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1803     const2reg(opr1, tmp, lir_patch_none, NULL);
1804     opr1 = tmp;
1805   }
1806 
1807   if (opr2->is_stack()) {
1808     stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1809     opr2 = FrameMap::rscratch2_opr;
1810   } else if (opr2->is_constant()) {
1811     LIR_Opr tmp
1812       = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1813     const2reg(opr2, tmp, lir_patch_none, NULL);
1814     opr2 = tmp;
1815   }
1816 
1817   if (result->type() == T_LONG)
1818     __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1819   else
1820     __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1821 }
1822 
1823 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1824   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1825 
1826   if (left->is_single_cpu()) {
1827     Register lreg = left->as_register();
1828     Register dreg = as_reg(dest);
1829 
1830     if (right->is_single_cpu()) {
1831       // cpu register - cpu register
1832 
1833       assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1834              "should be");
1835       Register rreg = right->as_register();
1836       switch (code) {
1837       case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1838       case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1839       case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1840       default:      ShouldNotReachHere();
1841       }
1842 
1843     } else if (right->is_double_cpu()) {
1844       Register rreg = right->as_register_lo();
1845       // single_cpu + double_cpu: can happen with obj+long
1846       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1847       switch (code) {
1848       case lir_add: __ add(dreg, lreg, rreg); break;
1849       case lir_sub: __ sub(dreg, lreg, rreg); break;
1850       default: ShouldNotReachHere();
1851       }
1852     } else if (right->is_constant()) {
1853       // cpu register - constant
1854       jlong c;
1855 
1856       // FIXME.  This is fugly: we really need to factor all this logic.
1857       switch(right->type()) {
1858       case T_LONG:
1859         c = right->as_constant_ptr()->as_jlong();
1860         break;
1861       case T_INT:
1862       case T_ADDRESS:
1863         c = right->as_constant_ptr()->as_jint();
1864         break;
1865       default:
1866         ShouldNotReachHere();
1867         c = 0;  // unreachable
1868         break;
1869       }
1870 
1871       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1872       if (c == 0 && dreg == lreg) {
1873         COMMENT("effective nop elided");
1874         return;
1875       }
1876       switch(left->type()) {
1877       case T_INT:
1878         switch (code) {
1879         case lir_add: __ addw(dreg, lreg, c); break;
1880         case lir_sub: __ subw(dreg, lreg, c); break;
1881         default: ShouldNotReachHere();
1882         }
1883         break;
1884       case T_OBJECT:
1885       case T_ADDRESS:
1886         switch (code) {
1887         case lir_add: __ add(dreg, lreg, c); break;
1888         case lir_sub: __ sub(dreg, lreg, c); break;
1889         default: ShouldNotReachHere();
1890         }
1891         break;
1892       default:
1893         ShouldNotReachHere();
1894       }
1895     } else {
1896       ShouldNotReachHere();
1897     }
1898 
1899   } else if (left->is_double_cpu()) {
1900     Register lreg_lo = left->as_register_lo();
1901 
1902     if (right->is_double_cpu()) {
1903       // cpu register - cpu register
1904       Register rreg_lo = right->as_register_lo();
1905       switch (code) {
1906       case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1907       case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1908       case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1909       case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1910       case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1911       default:
1912         ShouldNotReachHere();
1913       }
1914 
1915     } else if (right->is_constant()) {
1916       jlong c = right->as_constant_ptr()->as_jlong();
1917       Register dreg = as_reg(dest);
1918       switch (code) {
1919         case lir_add:
1920         case lir_sub:
1921           if (c == 0 && dreg == lreg_lo) {
1922             COMMENT("effective nop elided");
1923             return;
1924           }
1925           code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1926           break;
1927         case lir_div:
1928           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1929           if (c == 1) {
1930             // move lreg_lo to dreg if divisor is 1
1931             __ mov(dreg, lreg_lo);
1932           } else {
1933             unsigned int shift = log2i_exact(c);
1934             // use rscratch1 as intermediate result register
1935             __ asr(rscratch1, lreg_lo, 63);
1936             __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1937             __ asr(dreg, rscratch1, shift);
1938           }
1939           break;
1940         case lir_rem:
1941           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1942           if (c == 1) {
1943             // move 0 to dreg if divisor is 1
1944             __ mov(dreg, zr);
1945           } else {
1946             // use rscratch1 as intermediate result register
1947             __ negs(rscratch1, lreg_lo);
1948             __ andr(dreg, lreg_lo, c - 1);
1949             __ andr(rscratch1, rscratch1, c - 1);
1950             __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1951           }
1952           break;
1953         default:
1954           ShouldNotReachHere();
1955       }
1956     } else {
1957       ShouldNotReachHere();
1958     }
1959   } else if (left->is_single_fpu()) {
1960     assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1961     switch (code) {
1962     case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1963     case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1964     case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1965     case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1966     default:
1967       ShouldNotReachHere();
1968     }
1969   } else if (left->is_double_fpu()) {
1970     if (right->is_double_fpu()) {
1971       // fpu register - fpu register
1972       switch (code) {
1973       case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1974       case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1975       case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1976       case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1977       default:
1978         ShouldNotReachHere();
1979       }
1980     } else {
1981       if (right->is_constant()) {
1982         ShouldNotReachHere();
1983       }
1984       ShouldNotReachHere();
1985     }
1986   } else if (left->is_single_stack() || left->is_address()) {
1987     assert(left == dest, "left and dest must be equal");
1988     ShouldNotReachHere();
1989   } else {
1990     ShouldNotReachHere();
1991   }
1992 }
1993 
1994 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1995 
1996 
1997 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1998   switch(code) {
1999   case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
2000   case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
2001   default      : ShouldNotReachHere();
2002   }
2003 }
2004 
2005 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2006 
2007   assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
2008   Register Rleft = left->is_single_cpu() ? left->as_register() :
2009                                            left->as_register_lo();
2010    if (dst->is_single_cpu()) {
2011      Register Rdst = dst->as_register();
2012      if (right->is_constant()) {
2013        switch (code) {
2014          case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
2015          case lir_logic_or:  __ orrw (Rdst, Rleft, right->as_jint()); break;
2016          case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
2017          default: ShouldNotReachHere(); break;
2018        }
2019      } else {
2020        Register Rright = right->is_single_cpu() ? right->as_register() :
2021                                                   right->as_register_lo();
2022        switch (code) {
2023          case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
2024          case lir_logic_or:  __ orrw (Rdst, Rleft, Rright); break;
2025          case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
2026          default: ShouldNotReachHere(); break;
2027        }
2028      }
2029    } else {
2030      Register Rdst = dst->as_register_lo();
2031      if (right->is_constant()) {
2032        switch (code) {
2033          case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
2034          case lir_logic_or:  __ orr (Rdst, Rleft, right->as_jlong()); break;
2035          case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
2036          default: ShouldNotReachHere(); break;
2037        }
2038      } else {
2039        Register Rright = right->is_single_cpu() ? right->as_register() :
2040                                                   right->as_register_lo();
2041        switch (code) {
2042          case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
2043          case lir_logic_or:  __ orr (Rdst, Rleft, Rright); break;
2044          case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
2045          default: ShouldNotReachHere(); break;
2046        }
2047      }
2048    }
2049 }
2050 
2051 
2052 
2053 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
2054 
2055   // opcode check
2056   assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
2057   bool is_irem = (code == lir_irem);
2058 
2059   // operand check
2060   assert(left->is_single_cpu(),   "left must be register");
2061   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
2062   assert(result->is_single_cpu(), "result must be register");
2063   Register lreg = left->as_register();
2064   Register dreg = result->as_register();
2065 
2066   // power-of-2 constant check and codegen
2067   if (right->is_constant()) {
2068     int c = right->as_constant_ptr()->as_jint();
2069     assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
2070     if (is_irem) {
2071       if (c == 1) {
2072         // move 0 to dreg if divisor is 1
2073         __ movw(dreg, zr);
2074       } else {
2075         // use rscratch1 as intermediate result register
2076         __ negsw(rscratch1, lreg);
2077         __ andw(dreg, lreg, c - 1);
2078         __ andw(rscratch1, rscratch1, c - 1);
2079         __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
2080       }
2081     } else {
2082       if (c == 1) {
2083         // move lreg to dreg if divisor is 1
2084         __ movw(dreg, lreg);
2085       } else {
2086         unsigned int shift = exact_log2(c);
2087         // use rscratch1 as intermediate result register
2088         __ asrw(rscratch1, lreg, 31);
2089         __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
2090         __ asrw(dreg, rscratch1, shift);
2091       }
2092     }
2093   } else {
2094     Register rreg = right->as_register();
2095     __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
2096   }
2097 }
2098 
2099 
2100 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2101   if (opr1->is_constant() && opr2->is_single_cpu()) {
2102     // tableswitch
2103     Register reg = as_reg(opr2);
2104     struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
2105     __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
2106   } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
2107     Register reg1 = as_reg(opr1);
2108     if (opr2->is_single_cpu()) {
2109       // cpu register - cpu register
2110       Register reg2 = opr2->as_register();
2111       if (is_reference_type(opr1->type())) {
2112         __ cmpoop(reg1, reg2);
2113       } else {
2114         assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2115         __ cmpw(reg1, reg2);
2116       }
2117       return;
2118     }
2119     if (opr2->is_double_cpu()) {
2120       // cpu register - cpu register
2121       Register reg2 = opr2->as_register_lo();
2122       __ cmp(reg1, reg2);
2123       return;
2124     }
2125 
2126     if (opr2->is_constant()) {
2127       bool is_32bit = false; // width of register operand
2128       jlong imm;
2129 
2130       switch(opr2->type()) {
2131       case T_INT:
2132         imm = opr2->as_constant_ptr()->as_jint();
2133         is_32bit = true;
2134         break;
2135       case T_LONG:
2136         imm = opr2->as_constant_ptr()->as_jlong();
2137         break;
2138       case T_ADDRESS:
2139         imm = opr2->as_constant_ptr()->as_jint();
2140         break;
2141       case T_METADATA:
2142         imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
2143         break;
2144       case T_PRIMITIVE_OBJECT:
2145       case T_OBJECT:
2146       case T_ARRAY:
2147         jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
2148         __ cmpoop(reg1, rscratch1);
2149         return;
2150       default:
2151         ShouldNotReachHere();
2152         imm = 0;  // unreachable
2153         break;
2154       }
2155 
2156       if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
2157         if (is_32bit)
2158           __ cmpw(reg1, imm);
2159         else
2160           __ subs(zr, reg1, imm);
2161         return;
2162       } else {
2163         __ mov(rscratch1, imm);
2164         if (is_32bit)
2165           __ cmpw(reg1, rscratch1);
2166         else
2167           __ cmp(reg1, rscratch1);
2168         return;
2169       }
2170     } else
2171       ShouldNotReachHere();
2172   } else if (opr1->is_single_fpu()) {
2173     FloatRegister reg1 = opr1->as_float_reg();
2174     assert(opr2->is_single_fpu(), "expect single float register");
2175     FloatRegister reg2 = opr2->as_float_reg();
2176     __ fcmps(reg1, reg2);
2177   } else if (opr1->is_double_fpu()) {
2178     FloatRegister reg1 = opr1->as_double_reg();
2179     assert(opr2->is_double_fpu(), "expect double float register");
2180     FloatRegister reg2 = opr2->as_double_reg();
2181     __ fcmpd(reg1, reg2);
2182   } else {
2183     ShouldNotReachHere();
2184   }
2185 }
2186 
2187 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2188   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2189     bool is_unordered_less = (code == lir_ucmp_fd2i);
2190     if (left->is_single_fpu()) {
2191       __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2192     } else if (left->is_double_fpu()) {
2193       __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2194     } else {
2195       ShouldNotReachHere();
2196     }
2197   } else if (code == lir_cmp_l2i) {
2198     Label done;
2199     __ cmp(left->as_register_lo(), right->as_register_lo());
2200     __ mov(dst->as_register(), (uint64_t)-1L);
2201     __ br(Assembler::LT, done);
2202     __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2203     __ bind(done);
2204   } else {
2205     ShouldNotReachHere();
2206   }
2207 }
2208 
2209 
2210 void LIR_Assembler::align_call(LIR_Code code) {  }
2211 
2212 
2213 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2214   address call = __ trampoline_call(Address(op->addr(), rtype));
2215   if (call == NULL) {
2216     bailout("trampoline stub overflow");
2217     return;
2218   }
2219   add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2220 }
2221 
2222 
2223 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2224   address call = __ ic_call(op->addr());
2225   if (call == NULL) {
2226     bailout("trampoline stub overflow");
2227     return;
2228   }
2229   add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2230 }
2231 
2232 void LIR_Assembler::emit_static_call_stub() {
2233   address call_pc = __ pc();
2234   address stub = __ start_a_stub(call_stub_size());
2235   if (stub == NULL) {
2236     bailout("static call stub overflow");
2237     return;
2238   }
2239 
2240   int start = __ offset();
2241 
2242   __ relocate(static_stub_Relocation::spec(call_pc));
2243   __ emit_static_call_stub();
2244 
2245   assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size()
2246         <= call_stub_size(), "stub too big");
2247   __ end_a_stub();
2248 }
2249 
2250 
2251 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2252   assert(exceptionOop->as_register() == r0, "must match");
2253   assert(exceptionPC->as_register() == r3, "must match");
2254 
2255   // exception object is not added to oop map by LinearScan
2256   // (LinearScan assumes that no oops are in fixed registers)
2257   info->add_register_oop(exceptionOop);
2258   Runtime1::StubID unwind_id;
2259 
2260   // get current pc information
2261   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2262   if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2263     // As no instructions have been generated yet for this LIR node it's
2264     // possible that an oop map already exists for the current offset.
2265     // In that case insert an dummy NOP here to ensure all oop map PCs
2266     // are unique. See JDK-8237483.
2267     __ nop();
2268   }
2269   int pc_for_athrow_offset = __ offset();
2270   InternalAddress pc_for_athrow(__ pc());
2271   __ adr(exceptionPC->as_register(), pc_for_athrow);
2272   add_call_info(pc_for_athrow_offset, info); // for exception handler
2273 
2274   __ verify_not_null_oop(r0);
2275   // search an exception handler (r0: exception oop, r3: throwing pc)
2276   if (compilation()->has_fpu_code()) {
2277     unwind_id = Runtime1::handle_exception_id;
2278   } else {
2279     unwind_id = Runtime1::handle_exception_nofpu_id;
2280   }
2281   __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2282 
2283   // FIXME: enough room for two byte trap   ????
2284   __ nop();
2285 }
2286 
2287 
2288 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2289   assert(exceptionOop->as_register() == r0, "must match");
2290 
2291   __ b(_unwind_handler_entry);
2292 }
2293 
2294 
2295 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2296   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2297   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2298 
2299   switch (left->type()) {
2300     case T_INT: {
2301       switch (code) {
2302       case lir_shl:  __ lslvw (dreg, lreg, count->as_register()); break;
2303       case lir_shr:  __ asrvw (dreg, lreg, count->as_register()); break;
2304       case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2305       default:
2306         ShouldNotReachHere();
2307         break;
2308       }
2309       break;
2310     case T_LONG:
2311     case T_PRIMITIVE_OBJECT:
2312     case T_ADDRESS:
2313     case T_OBJECT:
2314       switch (code) {
2315       case lir_shl:  __ lslv (dreg, lreg, count->as_register()); break;
2316       case lir_shr:  __ asrv (dreg, lreg, count->as_register()); break;
2317       case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2318       default:
2319         ShouldNotReachHere();
2320         break;
2321       }
2322       break;
2323     default:
2324       ShouldNotReachHere();
2325       break;
2326     }
2327   }
2328 }
2329 
2330 
2331 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2332   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2333   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2334 
2335   switch (left->type()) {
2336     case T_INT: {
2337       switch (code) {
2338       case lir_shl:  __ lslw (dreg, lreg, count); break;
2339       case lir_shr:  __ asrw (dreg, lreg, count); break;
2340       case lir_ushr: __ lsrw (dreg, lreg, count); break;
2341       default:
2342         ShouldNotReachHere();
2343         break;
2344       }
2345       break;
2346     case T_LONG:
2347     case T_ADDRESS:
2348     case T_PRIMITIVE_OBJECT:
2349     case T_OBJECT:
2350       switch (code) {
2351       case lir_shl:  __ lsl (dreg, lreg, count); break;
2352       case lir_shr:  __ asr (dreg, lreg, count); break;
2353       case lir_ushr: __ lsr (dreg, lreg, count); break;
2354       default:
2355         ShouldNotReachHere();
2356         break;
2357       }
2358       break;
2359     default:
2360       ShouldNotReachHere();
2361       break;
2362     }
2363   }
2364 }
2365 
2366 
2367 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2368   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2369   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2370   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2371   __ str (r, Address(sp, offset_from_rsp_in_bytes));
2372 }
2373 
2374 
2375 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
2376   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2377   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2378   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2379   __ mov (rscratch1, c);
2380   __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2381 }
2382 
2383 
2384 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
2385   ShouldNotReachHere();
2386   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2387   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2388   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2389   __ lea(rscratch1, __ constant_oop_address(o));
2390   __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2391 }
2392 
2393 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
2394   if (null_check) {
2395     __ cbz(obj, *slow_path->entry());
2396   }
2397   if (UseArrayMarkWordCheck) {
2398     if (is_dest) {
2399       __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
2400     } else {
2401       __ test_flattened_array_oop(obj, tmp, *slow_path->entry());
2402     }
2403   } else {
2404     __ load_klass(tmp, obj);
2405     __ ldr(tmp, Address(tmp, Klass::layout_helper_offset()));
2406     if (is_dest) {
2407       // Take the slow path if it's a null_free destination array, in case the source array contains NULLs.
2408       __ tst(tmp, Klass::_lh_null_free_array_bit_inplace);
2409     } else {
2410       __ tst(tmp, Klass::_lh_array_tag_flat_value_bit_inplace);
2411     }
2412     __ br(Assembler::NE, *slow_path->entry());
2413   }
2414 }
2415 
2416 // This code replaces a call to arraycopy; no exception may
2417 // be thrown in this code, they must be thrown in the System.arraycopy
2418 // activation frame; we could save some checks if this would not be the case
2419 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2420   ciArrayKlass* default_type = op->expected_type();
2421   Register src = op->src()->as_register();
2422   Register dst = op->dst()->as_register();
2423   Register src_pos = op->src_pos()->as_register();
2424   Register dst_pos = op->dst_pos()->as_register();
2425   Register length  = op->length()->as_register();
2426   Register tmp = op->tmp()->as_register();
2427 
2428   CodeStub* stub = op->stub();
2429   int flags = op->flags();
2430   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2431   if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2432 
2433   if (flags & LIR_OpArrayCopy::always_slow_path) {
2434     __ b(*stub->entry());
2435     __ bind(*stub->continuation());
2436     return;
2437   }
2438 
2439   // if we don't know anything, just go through the generic arraycopy
2440   if (default_type == NULL // || basic_type == T_OBJECT
2441       ) {
2442     Label done;
2443     assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2444 
2445     // Save the arguments in case the generic arraycopy fails and we
2446     // have to fall back to the JNI stub
2447     __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2448     __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2449     __ str(src,              Address(sp, 4*BytesPerWord));
2450 
2451     address copyfunc_addr = StubRoutines::generic_arraycopy();
2452     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2453 
2454     // The arguments are in java calling convention so we shift them
2455     // to C convention
2456     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2457     __ mov(c_rarg0, j_rarg0);
2458     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2459     __ mov(c_rarg1, j_rarg1);
2460     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2461     __ mov(c_rarg2, j_rarg2);
2462     assert_different_registers(c_rarg3, j_rarg4);
2463     __ mov(c_rarg3, j_rarg3);
2464     __ mov(c_rarg4, j_rarg4);
2465 #ifndef PRODUCT
2466     if (PrintC1Statistics) {
2467       __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2468     }
2469 #endif
2470     __ far_call(RuntimeAddress(copyfunc_addr));
2471 
2472     __ cbz(r0, *stub->continuation());
2473 
2474     // Reload values from the stack so they are where the stub
2475     // expects them.
2476     __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2477     __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2478     __ ldr(src,              Address(sp, 4*BytesPerWord));
2479 
2480     // r0 is -1^K where K == partial copied count
2481     __ eonw(rscratch1, r0, zr);
2482     // adjust length down and src/end pos up by partial copied count
2483     __ subw(length, length, rscratch1);
2484     __ addw(src_pos, src_pos, rscratch1);
2485     __ addw(dst_pos, dst_pos, rscratch1);
2486     __ b(*stub->entry());
2487 
2488     __ bind(*stub->continuation());
2489     return;
2490   }
2491 
2492   // Handle inline type arrays
2493   if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
2494     arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
2495   }
2496 
2497   if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
2498     arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
2499   }
2500 
2501   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2502 
2503   int elem_size = type2aelembytes(basic_type);
2504   int scale = exact_log2(elem_size);
2505 
2506   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2507   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2508   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2509   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2510 
2511   // test for NULL
2512   if (flags & LIR_OpArrayCopy::src_null_check) {
2513     __ cbz(src, *stub->entry());
2514   }
2515   if (flags & LIR_OpArrayCopy::dst_null_check) {
2516     __ cbz(dst, *stub->entry());
2517   }
2518 
2519   // If the compiler was not able to prove that exact type of the source or the destination
2520   // of the arraycopy is an array type, check at runtime if the source or the destination is
2521   // an instance type.
2522   if (flags & LIR_OpArrayCopy::type_check) {
2523     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2524       __ load_klass(tmp, dst);
2525       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2526       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2527       __ br(Assembler::GE, *stub->entry());
2528     }
2529 
2530     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2531       __ load_klass(tmp, src);
2532       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2533       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2534       __ br(Assembler::GE, *stub->entry());
2535     }
2536   }
2537 
2538   // check if negative
2539   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2540     __ cmpw(src_pos, 0);
2541     __ br(Assembler::LT, *stub->entry());
2542   }
2543   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2544     __ cmpw(dst_pos, 0);
2545     __ br(Assembler::LT, *stub->entry());
2546   }
2547 
2548   if (flags & LIR_OpArrayCopy::length_positive_check) {
2549     __ cmpw(length, 0);
2550     __ br(Assembler::LT, *stub->entry());
2551   }
2552 
2553   if (flags & LIR_OpArrayCopy::src_range_check) {
2554     __ addw(tmp, src_pos, length);
2555     __ ldrw(rscratch1, src_length_addr);
2556     __ cmpw(tmp, rscratch1);
2557     __ br(Assembler::HI, *stub->entry());
2558   }
2559   if (flags & LIR_OpArrayCopy::dst_range_check) {
2560     __ addw(tmp, dst_pos, length);
2561     __ ldrw(rscratch1, dst_length_addr);
2562     __ cmpw(tmp, rscratch1);
2563     __ br(Assembler::HI, *stub->entry());
2564   }
2565 
2566   if (flags & LIR_OpArrayCopy::type_check) {
2567     // We don't know the array types are compatible
2568     if (basic_type != T_OBJECT) {
2569       // Simple test for basic type arrays
2570       if (UseCompressedClassPointers) {
2571         __ ldrw(tmp, src_klass_addr);
2572         __ ldrw(rscratch1, dst_klass_addr);
2573         __ cmpw(tmp, rscratch1);
2574       } else {
2575         __ ldr(tmp, src_klass_addr);
2576         __ ldr(rscratch1, dst_klass_addr);
2577         __ cmp(tmp, rscratch1);
2578       }
2579       __ br(Assembler::NE, *stub->entry());
2580     } else {
2581       // For object arrays, if src is a sub class of dst then we can
2582       // safely do the copy.
2583       Label cont, slow;
2584 
2585 #define PUSH(r1, r2)                                    \
2586       stp(r1, r2, __ pre(sp, -2 * wordSize));
2587 
2588 #define POP(r1, r2)                                     \
2589       ldp(r1, r2, __ post(sp, 2 * wordSize));
2590 
2591       __ PUSH(src, dst);
2592 
2593       __ load_klass(src, src);
2594       __ load_klass(dst, dst);
2595 
2596       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2597 
2598       __ PUSH(src, dst);
2599       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2600       __ POP(src, dst);
2601 
2602       __ cbnz(src, cont);
2603 
2604       __ bind(slow);
2605       __ POP(src, dst);
2606 
2607       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2608       if (copyfunc_addr != NULL) { // use stub if available
2609         // src is not a sub class of dst so we have to do a
2610         // per-element check.
2611 
2612         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2613         if ((flags & mask) != mask) {
2614           // Check that at least both of them object arrays.
2615           assert(flags & mask, "one of the two should be known to be an object array");
2616 
2617           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2618             __ load_klass(tmp, src);
2619           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2620             __ load_klass(tmp, dst);
2621           }
2622           int lh_offset = in_bytes(Klass::layout_helper_offset());
2623           Address klass_lh_addr(tmp, lh_offset);
2624           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2625           __ ldrw(rscratch1, klass_lh_addr);
2626           __ mov(rscratch2, objArray_lh);
2627           __ eorw(rscratch1, rscratch1, rscratch2);
2628           __ cbnzw(rscratch1, *stub->entry());
2629         }
2630 
2631        // Spill because stubs can use any register they like and it's
2632        // easier to restore just those that we care about.
2633         __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2634         __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2635         __ str(src,              Address(sp, 4*BytesPerWord));
2636 
2637         __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2638         __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2639         assert_different_registers(c_rarg0, dst, dst_pos, length);
2640         __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2641         __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2642         assert_different_registers(c_rarg1, dst, length);
2643         __ uxtw(c_rarg2, length);
2644         assert_different_registers(c_rarg2, dst);
2645 
2646         __ load_klass(c_rarg4, dst);
2647         __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2648         __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2649         __ far_call(RuntimeAddress(copyfunc_addr));
2650 
2651 #ifndef PRODUCT
2652         if (PrintC1Statistics) {
2653           Label failed;
2654           __ cbnz(r0, failed);
2655           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2656           __ bind(failed);
2657         }
2658 #endif
2659 
2660         __ cbz(r0, *stub->continuation());
2661 
2662 #ifndef PRODUCT
2663         if (PrintC1Statistics) {
2664           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2665         }
2666 #endif
2667         assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2668 
2669         // Restore previously spilled arguments
2670         __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2671         __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2672         __ ldr(src,              Address(sp, 4*BytesPerWord));
2673 
2674         // return value is -1^K where K is partial copied count
2675         __ eonw(rscratch1, r0, zr);
2676         // adjust length down and src/end pos up by partial copied count
2677         __ subw(length, length, rscratch1);
2678         __ addw(src_pos, src_pos, rscratch1);
2679         __ addw(dst_pos, dst_pos, rscratch1);
2680       }
2681 
2682       __ b(*stub->entry());
2683 
2684       __ bind(cont);
2685       __ POP(src, dst);
2686     }
2687   }
2688 
2689 #ifdef ASSERT
2690   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2691     // Sanity check the known type with the incoming class.  For the
2692     // primitive case the types must match exactly with src.klass and
2693     // dst.klass each exactly matching the default type.  For the
2694     // object array case, if no type check is needed then either the
2695     // dst type is exactly the expected type and the src type is a
2696     // subtype which we can't check or src is the same array as dst
2697     // but not necessarily exactly of type default_type.
2698     Label known_ok, halt;
2699     __ mov_metadata(tmp, default_type->constant_encoding());
2700     if (UseCompressedClassPointers) {
2701       __ encode_klass_not_null(tmp);
2702     }
2703 
2704     if (basic_type != T_OBJECT) {
2705 
2706       if (UseCompressedClassPointers) {
2707         __ ldrw(rscratch1, dst_klass_addr);
2708         __ cmpw(tmp, rscratch1);
2709       } else {
2710         __ ldr(rscratch1, dst_klass_addr);
2711         __ cmp(tmp, rscratch1);
2712       }
2713       __ br(Assembler::NE, halt);
2714       if (UseCompressedClassPointers) {
2715         __ ldrw(rscratch1, src_klass_addr);
2716         __ cmpw(tmp, rscratch1);
2717       } else {
2718         __ ldr(rscratch1, src_klass_addr);
2719         __ cmp(tmp, rscratch1);
2720       }
2721       __ br(Assembler::EQ, known_ok);
2722     } else {
2723       if (UseCompressedClassPointers) {
2724         __ ldrw(rscratch1, dst_klass_addr);
2725         __ cmpw(tmp, rscratch1);
2726       } else {
2727         __ ldr(rscratch1, dst_klass_addr);
2728         __ cmp(tmp, rscratch1);
2729       }
2730       __ br(Assembler::EQ, known_ok);
2731       __ cmp(src, dst);
2732       __ br(Assembler::EQ, known_ok);
2733     }
2734     __ bind(halt);
2735     __ stop("incorrect type information in arraycopy");
2736     __ bind(known_ok);
2737   }
2738 #endif
2739 
2740 #ifndef PRODUCT
2741   if (PrintC1Statistics) {
2742     __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2743   }
2744 #endif
2745 
2746   __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2747   __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2748   assert_different_registers(c_rarg0, dst, dst_pos, length);
2749   __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2750   __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2751   assert_different_registers(c_rarg1, dst, length);
2752   __ uxtw(c_rarg2, length);
2753   assert_different_registers(c_rarg2, dst);
2754 
2755   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2756   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2757   const char *name;
2758   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2759 
2760  CodeBlob *cb = CodeCache::find_blob(entry);
2761  if (cb) {
2762    __ far_call(RuntimeAddress(entry));
2763  } else {
2764    __ call_VM_leaf(entry, 3);
2765  }
2766 
2767   __ bind(*stub->continuation());
2768 }
2769 
2770 
2771 
2772 
2773 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2774   Register obj = op->obj_opr()->as_register();  // may not be an oop
2775   Register hdr = op->hdr_opr()->as_register();
2776   Register lock = op->lock_opr()->as_register();
2777   if (UseHeavyMonitors) {
2778     __ b(*op->stub()->entry());
2779   } else if (op->code() == lir_lock) {
2780     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2781     // add debug info for NullPointerException only if one is possible
2782     int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry());
2783     if (op->info() != NULL) {
2784       add_debug_info_for_null_check(null_check_offset, op->info());
2785     }
2786     // done
2787   } else if (op->code() == lir_unlock) {
2788     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2789     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2790   } else {
2791     Unimplemented();
2792   }
2793   __ bind(*op->stub()->continuation());
2794 }
2795 
2796 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2797   Register obj = op->obj()->as_pointer_register();
2798   Register result = op->result_opr()->as_pointer_register();
2799 
2800   CodeEmitInfo* info = op->info();
2801   if (info != NULL) {
2802     add_debug_info_for_null_check_here(info);
2803   }
2804 
2805   if (UseCompressedClassPointers) {
2806     __ ldrw(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2807     __ decode_klass_not_null(result);
2808   } else {
2809     __ ldr(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2810   }
2811 }
2812 
2813 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2814   ciMethod* method = op->profiled_method();
2815   int bci          = op->profiled_bci();
2816   ciMethod* callee = op->profiled_callee();
2817 
2818   // Update counter for all call types
2819   ciMethodData* md = method->method_data_or_null();
2820   assert(md != NULL, "Sanity");
2821   ciProfileData* data = md->bci_to_data(bci);
2822   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2823   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2824   Register mdo  = op->mdo()->as_register();
2825   __ mov_metadata(mdo, md->constant_encoding());
2826   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2827   // Perform additional virtual call profiling for invokevirtual and
2828   // invokeinterface bytecodes
2829   if (op->should_profile_receiver_type()) {
2830     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2831     Register recv = op->recv()->as_register();
2832     assert_different_registers(mdo, recv);
2833     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2834     ciKlass* known_klass = op->known_holder();
2835     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2836       // We know the type that will be seen at this call site; we can
2837       // statically update the MethodData* rather than needing to do
2838       // dynamic tests on the receiver type
2839 
2840       // NOTE: we should probably put a lock around this search to
2841       // avoid collisions by concurrent compilations
2842       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2843       uint i;
2844       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2845         ciKlass* receiver = vc_data->receiver(i);
2846         if (known_klass->equals(receiver)) {
2847           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2848           __ addptr(data_addr, DataLayout::counter_increment);
2849           return;
2850         }
2851       }
2852 
2853       // Receiver type not found in profile data; select an empty slot
2854 
2855       // Note that this is less efficient than it should be because it
2856       // always does a write to the receiver part of the
2857       // VirtualCallData rather than just the first time
2858       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2859         ciKlass* receiver = vc_data->receiver(i);
2860         if (receiver == NULL) {
2861           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2862           __ mov_metadata(rscratch1, known_klass->constant_encoding());
2863           __ lea(rscratch2, recv_addr);
2864           __ str(rscratch1, Address(rscratch2));
2865           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2866           __ addptr(data_addr, DataLayout::counter_increment);
2867           return;
2868         }
2869       }
2870     } else {
2871       __ load_klass(recv, recv);
2872       Label update_done;
2873       type_profile_helper(mdo, md, data, recv, &update_done);
2874       // Receiver did not match any saved receiver and there is no empty row for it.
2875       // Increment total counter to indicate polymorphic case.
2876       __ addptr(counter_addr, DataLayout::counter_increment);
2877 
2878       __ bind(update_done);
2879     }
2880   } else {
2881     // Static call
2882     __ addptr(counter_addr, DataLayout::counter_increment);
2883   }
2884 }
2885 
2886 
2887 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2888   Unimplemented();
2889 }
2890 
2891 
2892 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2893   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2894 }
2895 
2896 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2897   assert(op->crc()->is_single_cpu(),  "crc must be register");
2898   assert(op->val()->is_single_cpu(),  "byte value must be register");
2899   assert(op->result_opr()->is_single_cpu(), "result must be register");
2900   Register crc = op->crc()->as_register();
2901   Register val = op->val()->as_register();
2902   Register res = op->result_opr()->as_register();
2903 
2904   assert_different_registers(val, crc, res);
2905   uint64_t offset;
2906   __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2907   if (offset) __ add(res, res, offset);
2908 
2909   __ mvnw(crc, crc); // ~crc
2910   __ update_byte_crc32(crc, val, res);
2911   __ mvnw(res, crc); // ~crc
2912 }
2913 
2914 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2915   COMMENT("emit_profile_type {");
2916   Register obj = op->obj()->as_register();
2917   Register tmp = op->tmp()->as_pointer_register();
2918   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2919   ciKlass* exact_klass = op->exact_klass();
2920   intptr_t current_klass = op->current_klass();
2921   bool not_null = op->not_null();
2922   bool no_conflict = op->no_conflict();
2923 
2924   Label update, next, none;
2925 
2926   bool do_null = !not_null;
2927   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2928   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2929 
2930   assert(do_null || do_update, "why are we here?");
2931   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2932   assert(mdo_addr.base() != rscratch1, "wrong register");
2933 
2934   __ verify_oop(obj);
2935 
2936   if (tmp != obj) {
2937     __ mov(tmp, obj);
2938   }
2939   if (do_null) {
2940     __ cbnz(tmp, update);
2941     if (!TypeEntries::was_null_seen(current_klass)) {
2942       __ ldr(rscratch2, mdo_addr);
2943       __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2944       __ str(rscratch2, mdo_addr);
2945     }
2946     if (do_update) {
2947 #ifndef ASSERT
2948       __ b(next);
2949     }
2950 #else
2951       __ b(next);
2952     }
2953   } else {
2954     __ cbnz(tmp, update);
2955     __ stop("unexpected null obj");
2956 #endif
2957   }
2958 
2959   __ bind(update);
2960 
2961   if (do_update) {
2962 #ifdef ASSERT
2963     if (exact_klass != NULL) {
2964       Label ok;
2965       __ load_klass(tmp, tmp);
2966       __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2967       __ eor(rscratch1, tmp, rscratch1);
2968       __ cbz(rscratch1, ok);
2969       __ stop("exact klass and actual klass differ");
2970       __ bind(ok);
2971     }
2972 #endif
2973     if (!no_conflict) {
2974       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2975         if (exact_klass != NULL) {
2976           __ mov_metadata(tmp, exact_klass->constant_encoding());
2977         } else {
2978           __ load_klass(tmp, tmp);
2979         }
2980 
2981         __ ldr(rscratch2, mdo_addr);
2982         __ eor(tmp, tmp, rscratch2);
2983         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2984         // klass seen before, nothing to do. The unknown bit may have been
2985         // set already but no need to check.
2986         __ cbz(rscratch1, next);
2987 
2988         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2989 
2990         if (TypeEntries::is_type_none(current_klass)) {
2991           __ cbz(rscratch2, none);
2992           __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2993           __ br(Assembler::EQ, none);
2994           // There is a chance that the checks above (re-reading profiling
2995           // data from memory) fail if another thread has just set the
2996           // profiling to this obj's klass
2997           __ dmb(Assembler::ISHLD);
2998           __ ldr(rscratch2, mdo_addr);
2999           __ eor(tmp, tmp, rscratch2);
3000           __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
3001           __ cbz(rscratch1, next);
3002         }
3003       } else {
3004         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3005                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3006 
3007         __ ldr(tmp, mdo_addr);
3008         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
3009       }
3010 
3011       // different than before. Cannot keep accurate profile.
3012       __ ldr(rscratch2, mdo_addr);
3013       __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
3014       __ str(rscratch2, mdo_addr);
3015 
3016       if (TypeEntries::is_type_none(current_klass)) {
3017         __ b(next);
3018 
3019         __ bind(none);
3020         // first time here. Set profile type.
3021         __ str(tmp, mdo_addr);
3022       }
3023     } else {
3024       // There's a single possible klass at this profile point
3025       assert(exact_klass != NULL, "should be");
3026       if (TypeEntries::is_type_none(current_klass)) {
3027         __ mov_metadata(tmp, exact_klass->constant_encoding());
3028         __ ldr(rscratch2, mdo_addr);
3029         __ eor(tmp, tmp, rscratch2);
3030         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
3031         __ cbz(rscratch1, next);
3032 #ifdef ASSERT
3033         {
3034           Label ok;
3035           __ ldr(rscratch1, mdo_addr);
3036           __ cbz(rscratch1, ok);
3037           __ cmp(rscratch1, (u1)TypeEntries::null_seen);
3038           __ br(Assembler::EQ, ok);
3039           // may have been set by another thread
3040           __ dmb(Assembler::ISHLD);
3041           __ mov_metadata(rscratch1, exact_klass->constant_encoding());
3042           __ ldr(rscratch2, mdo_addr);
3043           __ eor(rscratch2, rscratch1, rscratch2);
3044           __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
3045           __ cbz(rscratch2, ok);
3046 
3047           __ stop("unexpected profiling mismatch");
3048           __ bind(ok);
3049         }
3050 #endif
3051         // first time here. Set profile type.
3052         __ str(tmp, mdo_addr);
3053       } else {
3054         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3055                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3056 
3057         __ ldr(tmp, mdo_addr);
3058         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
3059 
3060         __ orr(tmp, tmp, TypeEntries::type_unknown);
3061         __ str(tmp, mdo_addr);
3062         // FIXME: Write barrier needed here?
3063       }
3064     }
3065 
3066     __ bind(next);
3067   }
3068   COMMENT("} emit_profile_type");
3069 }
3070 
3071 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3072   Register obj = op->obj()->as_register();
3073   Register tmp = op->tmp()->as_pointer_register();
3074   bool not_null = op->not_null();
3075   int flag = op->flag();
3076 
3077   Label not_inline_type;
3078   if (!not_null) {
3079     __ cbz(obj, not_inline_type);
3080   }
3081 
3082   __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
3083 
3084   Address mdo_addr = as_Address(op->mdp()->as_address_ptr(), rscratch2);
3085   __ ldrb(rscratch1, mdo_addr);
3086   __ orr(rscratch1, rscratch1, flag);
3087   __ strb(rscratch1, mdo_addr);
3088 
3089   __ bind(not_inline_type);
3090 }
3091 
3092 void LIR_Assembler::align_backward_branch_target() {
3093 }
3094 
3095 
3096 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3097   // tmp must be unused
3098   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3099 
3100   if (left->is_single_cpu()) {
3101     assert(dest->is_single_cpu(), "expect single result reg");
3102     __ negw(dest->as_register(), left->as_register());
3103   } else if (left->is_double_cpu()) {
3104     assert(dest->is_double_cpu(), "expect double result reg");
3105     __ neg(dest->as_register_lo(), left->as_register_lo());
3106   } else if (left->is_single_fpu()) {
3107     assert(dest->is_single_fpu(), "expect single float result reg");
3108     __ fnegs(dest->as_float_reg(), left->as_float_reg());
3109   } else {
3110     assert(left->is_double_fpu(), "expect double float operand reg");
3111     assert(dest->is_double_fpu(), "expect double float result reg");
3112     __ fnegd(dest->as_double_reg(), left->as_double_reg());
3113   }
3114 }
3115 
3116 
3117 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3118   if (patch_code != lir_patch_none) {
3119     deoptimize_trap(info);
3120     return;
3121   }
3122 
3123   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
3124 }
3125 
3126 
3127 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3128   assert(!tmp->is_valid(), "don't need temporary");
3129 
3130   CodeBlob *cb = CodeCache::find_blob(dest);
3131   if (cb) {
3132     __ far_call(RuntimeAddress(dest));
3133   } else {
3134     __ mov(rscratch1, RuntimeAddress(dest));
3135     __ blr(rscratch1);
3136   }
3137 
3138   if (info != NULL) {
3139     add_call_info_here(info);
3140   }
3141 }
3142 
3143 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3144   if (dest->is_address() || src->is_address()) {
3145     move_op(src, dest, type, lir_patch_none, info,
3146             /*pop_fpu_stack*/false, /*wide*/false);
3147   } else {
3148     ShouldNotReachHere();
3149   }
3150 }
3151 
3152 #ifdef ASSERT
3153 // emit run-time assertion
3154 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3155   assert(op->code() == lir_assert, "must be");
3156 
3157   if (op->in_opr1()->is_valid()) {
3158     assert(op->in_opr2()->is_valid(), "both operands must be valid");
3159     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3160   } else {
3161     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3162     assert(op->condition() == lir_cond_always, "no other conditions allowed");
3163   }
3164 
3165   Label ok;
3166   if (op->condition() != lir_cond_always) {
3167     Assembler::Condition acond = Assembler::AL;
3168     switch (op->condition()) {
3169       case lir_cond_equal:        acond = Assembler::EQ;  break;
3170       case lir_cond_notEqual:     acond = Assembler::NE;  break;
3171       case lir_cond_less:         acond = Assembler::LT;  break;
3172       case lir_cond_lessEqual:    acond = Assembler::LE;  break;
3173       case lir_cond_greaterEqual: acond = Assembler::GE;  break;
3174       case lir_cond_greater:      acond = Assembler::GT;  break;
3175       case lir_cond_belowEqual:   acond = Assembler::LS;  break;
3176       case lir_cond_aboveEqual:   acond = Assembler::HS;  break;
3177       default:                    ShouldNotReachHere();
3178     }
3179     __ br(acond, ok);
3180   }
3181   if (op->halt()) {
3182     const char* str = __ code_string(op->msg());
3183     __ stop(str);
3184   } else {
3185     breakpoint();
3186   }
3187   __ bind(ok);
3188 }
3189 #endif
3190 
3191 #ifndef PRODUCT
3192 #define COMMENT(x)   do { __ block_comment(x); } while (0)
3193 #else
3194 #define COMMENT(x)
3195 #endif
3196 
3197 void LIR_Assembler::membar() {
3198   COMMENT("membar");
3199   __ membar(MacroAssembler::AnyAny);
3200 }
3201 
3202 void LIR_Assembler::membar_acquire() {
3203   __ membar(Assembler::LoadLoad|Assembler::LoadStore);
3204 }
3205 
3206 void LIR_Assembler::membar_release() {
3207   __ membar(Assembler::LoadStore|Assembler::StoreStore);
3208 }
3209 
3210 void LIR_Assembler::membar_loadload() {
3211   __ membar(Assembler::LoadLoad);
3212 }
3213 
3214 void LIR_Assembler::membar_storestore() {
3215   __ membar(MacroAssembler::StoreStore);
3216 }
3217 
3218 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3219 
3220 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3221 
3222 void LIR_Assembler::on_spin_wait() {
3223   __ spin_wait();
3224 }
3225 
3226 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3227   __ mov(result_reg->as_register(), rthread);
3228 }
3229 
3230 void LIR_Assembler::check_orig_pc() {
3231   __ ldr(rscratch2, frame_map()->address_for_orig_pc_addr());
3232   __ cmp(rscratch2, (u1)NULL_WORD);
3233 }
3234 
3235 void LIR_Assembler::peephole(LIR_List *lir) {
3236 #if 0
3237   if (tableswitch_count >= max_tableswitches)
3238     return;
3239 
3240   /*
3241     This finite-state automaton recognizes sequences of compare-and-
3242     branch instructions.  We will turn them into a tableswitch.  You
3243     could argue that C1 really shouldn't be doing this sort of
3244     optimization, but without it the code is really horrible.
3245   */
3246 
3247   enum { start_s, cmp1_s, beq_s, cmp_s } state;
3248   int first_key, last_key = -2147483648;
3249   int next_key = 0;
3250   int start_insn = -1;
3251   int last_insn = -1;
3252   Register reg = noreg;
3253   LIR_Opr reg_opr;
3254   state = start_s;
3255 
3256   LIR_OpList* inst = lir->instructions_list();
3257   for (int i = 0; i < inst->length(); i++) {
3258     LIR_Op* op = inst->at(i);
3259     switch (state) {
3260     case start_s:
3261       first_key = -1;
3262       start_insn = i;
3263       switch (op->code()) {
3264       case lir_cmp:
3265         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3266         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3267         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3268             && opr2->is_constant()
3269             && opr2->type() == T_INT) {
3270           reg_opr = opr1;
3271           reg = opr1->as_register();
3272           first_key = opr2->as_constant_ptr()->as_jint();
3273           next_key = first_key + 1;
3274           state = cmp_s;
3275           goto next_state;
3276         }
3277         break;
3278       }
3279       break;
3280     case cmp_s:
3281       switch (op->code()) {
3282       case lir_branch:
3283         if (op->as_OpBranch()->cond() == lir_cond_equal) {
3284           state = beq_s;
3285           last_insn = i;
3286           goto next_state;
3287         }
3288       }
3289       state = start_s;
3290       break;
3291     case beq_s:
3292       switch (op->code()) {
3293       case lir_cmp: {
3294         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3295         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3296         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3297             && opr1->as_register() == reg
3298             && opr2->is_constant()
3299             && opr2->type() == T_INT
3300             && opr2->as_constant_ptr()->as_jint() == next_key) {
3301           last_key = next_key;
3302           next_key++;
3303           state = cmp_s;
3304           goto next_state;
3305         }
3306       }
3307       }
3308       last_key = next_key;
3309       state = start_s;
3310       break;
3311     default:
3312       assert(false, "impossible state");
3313     }
3314     if (state == start_s) {
3315       if (first_key < last_key - 5L && reg != noreg) {
3316         {
3317           // printf("found run register %d starting at insn %d low value %d high value %d\n",
3318           //        reg->encoding(),
3319           //        start_insn, first_key, last_key);
3320           //   for (int i = 0; i < inst->length(); i++) {
3321           //     inst->at(i)->print();
3322           //     tty->print("\n");
3323           //   }
3324           //   tty->print("\n");
3325         }
3326 
3327         struct tableswitch *sw = &switches[tableswitch_count];
3328         sw->_insn_index = start_insn, sw->_first_key = first_key,
3329           sw->_last_key = last_key, sw->_reg = reg;
3330         inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3331         {
3332           // Insert the new table of branches
3333           int offset = last_insn;
3334           for (int n = first_key; n < last_key; n++) {
3335             inst->insert_before
3336               (last_insn + 1,
3337                new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3338                                 inst->at(offset)->as_OpBranch()->label()));
3339             offset -= 2, i++;
3340           }
3341         }
3342         // Delete all the old compare-and-branch instructions
3343         for (int n = first_key; n < last_key; n++) {
3344           inst->remove_at(start_insn);
3345           inst->remove_at(start_insn);
3346         }
3347         // Insert the tableswitch instruction
3348         inst->insert_before(start_insn,
3349                             new LIR_Op2(lir_cmp, lir_cond_always,
3350                                         LIR_OprFact::intConst(tableswitch_count),
3351                                         reg_opr));
3352         inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3353         tableswitch_count++;
3354       }
3355       reg = noreg;
3356       last_key = -2147483648;
3357     }
3358   next_state:
3359     ;
3360   }
3361 #endif
3362 }
3363 
3364 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3365   Address addr = as_Address(src->as_address_ptr());
3366   BasicType type = src->type();
3367   bool is_oop = is_reference_type(type);
3368 
3369   void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3370   void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3371 
3372   switch(type) {
3373   case T_INT:
3374     xchg = &MacroAssembler::atomic_xchgalw;
3375     add = &MacroAssembler::atomic_addalw;
3376     break;
3377   case T_LONG:
3378     xchg = &MacroAssembler::atomic_xchgal;
3379     add = &MacroAssembler::atomic_addal;
3380     break;
3381   case T_PRIMITIVE_OBJECT:
3382   case T_OBJECT:
3383   case T_ARRAY:
3384     if (UseCompressedOops) {
3385       xchg = &MacroAssembler::atomic_xchgalw;
3386       add = &MacroAssembler::atomic_addalw;
3387     } else {
3388       xchg = &MacroAssembler::atomic_xchgal;
3389       add = &MacroAssembler::atomic_addal;
3390     }
3391     break;
3392   default:
3393     ShouldNotReachHere();
3394     xchg = &MacroAssembler::atomic_xchgal;
3395     add = &MacroAssembler::atomic_addal; // unreachable
3396   }
3397 
3398   switch (code) {
3399   case lir_xadd:
3400     {
3401       RegisterOrConstant inc;
3402       Register tmp = as_reg(tmp_op);
3403       Register dst = as_reg(dest);
3404       if (data->is_constant()) {
3405         inc = RegisterOrConstant(as_long(data));
3406         assert_different_registers(dst, addr.base(), tmp,
3407                                    rscratch1, rscratch2);
3408       } else {
3409         inc = RegisterOrConstant(as_reg(data));
3410         assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3411                                    rscratch1, rscratch2);
3412       }
3413       __ lea(tmp, addr);
3414       (_masm->*add)(dst, inc, tmp);
3415       break;
3416     }
3417   case lir_xchg:
3418     {
3419       Register tmp = tmp_op->as_register();
3420       Register obj = as_reg(data);
3421       Register dst = as_reg(dest);
3422       if (is_oop && UseCompressedOops) {
3423         __ encode_heap_oop(rscratch2, obj);
3424         obj = rscratch2;
3425       }
3426       assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3427       __ lea(tmp, addr);
3428       (_masm->*xchg)(dst, obj, tmp);
3429       if (is_oop && UseCompressedOops) {
3430         __ decode_heap_oop(dst);
3431       }
3432     }
3433     break;
3434   default:
3435     ShouldNotReachHere();
3436   }
3437   __ membar(__ AnyAny);
3438 }
3439 
3440 #undef __