1 /*
2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInlineKlass.hpp"
37 #include "ci/ciInstance.hpp"
38 #include "code/compiledIC.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "oops/oop.inline.hpp"
44 #include "runtime/frame.inline.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_aarch64.inline.hpp"
49
50
51 #ifndef PRODUCT
52 #define COMMENT(x) do { __ block_comment(x); } while (0)
53 #else
54 #define COMMENT(x)
55 #endif
56
57 NEEDS_CLEANUP // remove this definitions ?
58 const Register SYNC_header = r0; // synchronization header
59 const Register SHIFT_count = r0; // where count for shift operations must be
60
61 #define __ _masm->
62
63
64 static void select_different_registers(Register preserve,
65 Register extra,
66 Register &tmp1,
67 Register &tmp2) {
68 if (tmp1 == preserve) {
69 assert_different_registers(tmp1, tmp2, extra);
70 tmp1 = extra;
71 } else if (tmp2 == preserve) {
72 assert_different_registers(tmp1, tmp2, extra);
73 tmp2 = extra;
74 }
75 assert_different_registers(preserve, tmp1, tmp2);
76 }
77
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2,
84 Register &tmp3) {
85 if (tmp1 == preserve) {
86 assert_different_registers(tmp1, tmp2, tmp3, extra);
87 tmp1 = extra;
88 } else if (tmp2 == preserve) {
89 assert_different_registers(tmp1, tmp2, tmp3, extra);
90 tmp2 = extra;
91 } else if (tmp3 == preserve) {
92 assert_different_registers(tmp1, tmp2, tmp3, extra);
93 tmp3 = extra;
94 }
95 assert_different_registers(preserve, tmp1, tmp2, tmp3);
96 }
97
98
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
100
101
102 LIR_Opr LIR_Assembler::receiverOpr() {
103 return FrameMap::receiver_opr;
104 }
105
106 LIR_Opr LIR_Assembler::osrBufferPointer() {
107 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
108 }
109
110 //--------------fpu register translations-----------------------
111
112
113 address LIR_Assembler::float_constant(float f) {
114 address const_addr = __ float_constant(f);
115 if (const_addr == nullptr) {
116 bailout("const section overflow");
117 return __ code()->consts()->start();
118 } else {
119 return const_addr;
120 }
121 }
122
123
124 address LIR_Assembler::double_constant(double d) {
125 address const_addr = __ double_constant(d);
126 if (const_addr == nullptr) {
127 bailout("const section overflow");
128 return __ code()->consts()->start();
129 } else {
130 return const_addr;
131 }
132 }
133
134 address LIR_Assembler::int_constant(jlong n) {
135 address const_addr = __ long_constant(n);
136 if (const_addr == nullptr) {
137 bailout("const section overflow");
138 return __ code()->consts()->start();
139 } else {
140 return const_addr;
141 }
142 }
143
144 void LIR_Assembler::breakpoint() { Unimplemented(); }
145
146 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
147
148 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
149
150 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
151 //-------------------------------------------
152
153 static Register as_reg(LIR_Opr op) {
154 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
155 }
156
157 static jlong as_long(LIR_Opr data) {
158 jlong result;
159 switch (data->type()) {
160 case T_INT:
161 result = (data->as_jint());
162 break;
163 case T_LONG:
164 result = (data->as_jlong());
165 break;
166 default:
167 ShouldNotReachHere();
168 result = 0; // unreachable
169 }
170 return result;
171 }
172
173 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
174 Register base = addr->base()->as_pointer_register();
175 LIR_Opr opr = addr->index();
176 if (opr->is_cpu_register()) {
177 Register index;
178 if (opr->is_single_cpu())
179 index = opr->as_register();
180 else
181 index = opr->as_register_lo();
182 assert(addr->disp() == 0, "must be");
183 switch(opr->type()) {
184 case T_INT:
185 return Address(base, index, Address::sxtw(addr->scale()));
186 case T_LONG:
187 return Address(base, index, Address::lsl(addr->scale()));
188 default:
189 ShouldNotReachHere();
190 }
191 } else {
192 assert(addr->scale() == 0,
193 "expected for immediate operand, was: %d", addr->scale());
194 ptrdiff_t offset = ptrdiff_t(addr->disp());
195 // NOTE: Does not handle any 16 byte vector access.
196 const uint type_size = type2aelembytes(addr->type(), true);
197 return __ legitimize_address(Address(base, offset), type_size, tmp);
198 }
199 return Address();
200 }
201
202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
203 ShouldNotReachHere();
204 return Address();
205 }
206
207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
208 return as_Address(addr, rscratch1);
209 }
210
211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
212 return as_Address(addr, rscratch1); // Ouch
213 // FIXME: This needs to be much more clever. See x86.
214 }
215
216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
217 // not encodable as a base + (immediate) offset, generate an explicit address
218 // calculation to hold the address in a temporary register.
219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
220 precond(size == 4 || size == 8);
221 Address addr = frame_map()->address_for_slot(index, adjust);
222 precond(addr.getMode() == Address::base_plus_offset);
223 precond(addr.base() == sp);
224 precond(addr.offset() > 0);
225 uint mask = size - 1;
226 assert((addr.offset() & mask) == 0, "scaled offsets only");
227 return __ legitimize_address(addr, size, tmp);
228 }
229
230 void LIR_Assembler::osr_entry() {
231 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
232 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
233 ValueStack* entry_state = osr_entry->state();
234 int number_of_locks = entry_state->locks_size();
235
236 // we jump here if osr happens with the interpreter
237 // state set up to continue at the beginning of the
238 // loop that triggered osr - in particular, we have
239 // the following registers setup:
240 //
241 // r2: osr buffer
242 //
243
244 // build frame
245 ciMethod* m = compilation()->method();
246 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
247
248 // OSR buffer is
249 //
250 // locals[nlocals-1..0]
251 // monitors[0..number_of_locks]
252 //
253 // locals is a direct copy of the interpreter frame so in the osr buffer
254 // so first slot in the local array is the last local from the interpreter
255 // and last slot is local[0] (receiver) from the interpreter
256 //
257 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
258 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
259 // in the interpreter frame (the method lock if a sync method)
260
261 // Initialize monitors in the compiled activation.
262 // r2: pointer to osr buffer
263 //
264 // All other registers are dead at this point and the locals will be
265 // copied into place by code emitted in the IR.
266
267 Register OSR_buf = osrBufferPointer()->as_pointer_register();
268 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
269 int monitor_offset = BytesPerWord * method()->max_locals() +
270 (2 * BytesPerWord) * (number_of_locks - 1);
271 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
272 // the OSR buffer using 2 word entries: first the lock and then
273 // the oop.
274 for (int i = 0; i < number_of_locks; i++) {
275 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
276 #ifdef ASSERT
277 // verify the interpreter's monitor has a non-null object
278 {
279 Label L;
280 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
281 __ cbnz(rscratch1, L);
282 __ stop("locked object is null");
283 __ bind(L);
284 }
285 #endif
286 __ ldr(r19, Address(OSR_buf, slot_offset));
287 __ ldr(r20, Address(OSR_buf, slot_offset + BytesPerWord));
288 __ str(r19, frame_map()->address_for_monitor_lock(i));
289 __ str(r20, frame_map()->address_for_monitor_object(i));
290 }
291 }
292 }
293
294
295 // inline cache check; done before the frame is built.
296 int LIR_Assembler::check_icache() {
297 return __ ic_check(CodeEntryAlignment);
298 }
299
300 void LIR_Assembler::clinit_barrier(ciMethod* method) {
301 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
302 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
303
304 Label L_skip_barrier;
305
306 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
307 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
308 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
309 __ bind(L_skip_barrier);
310 }
311
312 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
313 if (o == nullptr) {
314 __ mov(reg, zr);
315 } else {
316 __ movoop(reg, o);
317 }
318 }
319
320 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
321 address target = nullptr;
322 relocInfo::relocType reloc_type = relocInfo::none;
323
324 switch (patching_id(info)) {
325 case PatchingStub::access_field_id:
326 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
327 reloc_type = relocInfo::section_word_type;
328 break;
329 case PatchingStub::load_klass_id:
330 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
331 reloc_type = relocInfo::metadata_type;
332 break;
333 case PatchingStub::load_mirror_id:
334 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
335 reloc_type = relocInfo::oop_type;
336 break;
337 case PatchingStub::load_appendix_id:
338 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
339 reloc_type = relocInfo::oop_type;
340 break;
341 default: ShouldNotReachHere();
342 }
343
344 __ far_call(RuntimeAddress(target));
345 add_call_info_here(info);
346 }
347
348 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
349 deoptimize_trap(info);
350 }
351
352
353 // This specifies the rsp decrement needed to build the frame
354 int LIR_Assembler::initial_frame_size_in_bytes() const {
355 // if rounding, must let FrameMap know!
356
357 return in_bytes(frame_map()->framesize_in_bytes());
358 }
359
360
361 int LIR_Assembler::emit_exception_handler() {
362 // generate code for exception handler
363 address handler_base = __ start_a_stub(exception_handler_size());
364 if (handler_base == nullptr) {
365 // not enough space left for the handler
366 bailout("exception handler overflow");
367 return -1;
368 }
369
370 int offset = code_offset();
371
372 // the exception oop and pc are in r0, and r3
373 // no other registers need to be preserved, so invalidate them
374 __ invalidate_registers(false, true, true, false, true, true);
375
376 // check that there is really an exception
377 __ verify_not_null_oop(r0);
378
379 // search an exception handler (r0: exception oop, r3: throwing pc)
380 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
381 __ should_not_reach_here();
382 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
383 __ end_a_stub();
384
385 return offset;
386 }
387
388
389 // Emit the code to remove the frame from the stack in the exception
390 // unwind path.
391 int LIR_Assembler::emit_unwind_handler() {
392 #ifndef PRODUCT
393 if (CommentedAssembly) {
394 _masm->block_comment("Unwind handler");
395 }
396 #endif
397
398 int offset = code_offset();
399
400 // Fetch the exception from TLS and clear out exception related thread state
401 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
403 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
404
405 __ bind(_unwind_handler_entry);
406 __ verify_not_null_oop(r0);
407 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
408 __ mov(r19, r0); // Preserve the exception
409 }
410
411 // Perform needed unlocking
412 MonitorExitStub* stub = nullptr;
413 if (method()->is_synchronized()) {
414 monitor_address(0, FrameMap::r0_opr);
415 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
416 if (LockingMode == LM_MONITOR) {
417 __ b(*stub->entry());
418 } else {
419 __ unlock_object(r5, r4, r0, r6, *stub->entry());
420 }
421 __ bind(*stub->continuation());
422 }
423
424 if (compilation()->env()->dtrace_method_probes()) {
425 __ mov(c_rarg0, rthread);
426 __ mov_metadata(c_rarg1, method()->constant_encoding());
427 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
428 }
429
430 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
431 __ mov(r0, r19); // Restore the exception
432 }
433
434 // remove the activation and dispatch to the unwind handler
435 __ block_comment("remove_frame and dispatch to the unwind handler");
436 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
437 __ far_jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
438
439 // Emit the slow path assembly
440 if (stub != nullptr) {
441 stub->emit_code(this);
442 }
443
444 return offset;
445 }
446
447
448 int LIR_Assembler::emit_deopt_handler() {
449 // generate code for exception handler
450 address handler_base = __ start_a_stub(deopt_handler_size());
451 if (handler_base == nullptr) {
452 // not enough space left for the handler
453 bailout("deopt handler overflow");
454 return -1;
455 }
456
457 int offset = code_offset();
458
459 __ adr(lr, pc());
460 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
461 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
462 __ end_a_stub();
463
464 return offset;
465 }
466
467 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
468 _masm->code_section()->relocate(adr, relocInfo::poll_type);
469 int pc_offset = code_offset();
470 flush_debug_info(pc_offset);
471 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
472 if (info->exception_handlers() != nullptr) {
473 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
474 }
475 }
476
477 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
478 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
479
480 if (InlineTypeReturnedAsFields) {
481 // Check if we are returning an non-null inline type and load its fields into registers
482 ciType* return_type = compilation()->method()->return_type();
483 if (return_type->is_inlinetype()) {
484 ciInlineKlass* vk = return_type->as_inline_klass();
485 if (vk->can_be_returned_as_fields()) {
486 address unpack_handler = vk->unpack_handler();
487 assert(unpack_handler != nullptr, "must be");
488 __ far_call(RuntimeAddress(unpack_handler));
489 }
490 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) {
491 Label skip;
492 __ test_oop_is_not_inline_type(r0, rscratch2, skip);
493
494 // Load fields from a buffered value with an inline class specific handler
495 __ load_klass(rscratch1 /*dst*/, r0 /*src*/);
496 __ ldr(rscratch1, Address(rscratch1, InstanceKlass::adr_inlineklass_fixed_block_offset()));
497 __ ldr(rscratch1, Address(rscratch1, InlineKlass::unpack_handler_offset()));
498 // Unpack handler can be null if inline type is not scalarizable in returns
499 __ cbz(rscratch1, skip);
500 __ blr(rscratch1);
501
502 __ bind(skip);
503 }
504 // At this point, r0 points to the value object (for interpreter or C1 caller).
505 // The fields of the object are copied into registers (for C2 caller).
506 }
507
508 // Pop the stack before the safepoint code
509 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
510
511 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
512 __ reserved_stack_check();
513 }
514
515 code_stub->set_safepoint_offset(__ offset());
516 __ relocate(relocInfo::poll_return_type);
517 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
518 __ ret(lr);
519 }
520
521 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
522 return (__ store_inline_type_fields_to_buf(vk, false));
523 }
524
525 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
526 guarantee(info != nullptr, "Shouldn't be null");
527 __ get_polling_page(rscratch1, relocInfo::poll_type);
528 add_debug_info_for_branch(info); // This isn't just debug info:
529 // it's the oop map
530 __ read_polling_page(rscratch1, relocInfo::poll_type);
531 return __ offset();
532 }
533
534
535 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
536 if (from_reg == r31_sp)
537 from_reg = sp;
538 if (to_reg == r31_sp)
539 to_reg = sp;
540 __ mov(to_reg, from_reg);
541 }
542
543 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
544
545
546 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
547 assert(src->is_constant(), "should not call otherwise");
548 assert(dest->is_register(), "should not call otherwise");
549 LIR_Const* c = src->as_constant_ptr();
550
551 switch (c->type()) {
552 case T_INT: {
553 assert(patch_code == lir_patch_none, "no patching handled here");
554 __ movw(dest->as_register(), c->as_jint());
555 break;
556 }
557
558 case T_ADDRESS: {
559 assert(patch_code == lir_patch_none, "no patching handled here");
560 __ mov(dest->as_register(), c->as_jint());
561 break;
562 }
563
564 case T_LONG: {
565 assert(patch_code == lir_patch_none, "no patching handled here");
566 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
567 break;
568 }
569
570 case T_OBJECT: {
571 if (patch_code != lir_patch_none) {
572 jobject2reg_with_patching(dest->as_register(), info);
573 } else {
574 jobject2reg(c->as_jobject(), dest->as_register());
575 }
576 break;
577 }
578
579 case T_METADATA: {
580 if (patch_code != lir_patch_none) {
581 klass2reg_with_patching(dest->as_register(), info);
582 } else {
583 __ mov_metadata(dest->as_register(), c->as_metadata());
584 }
585 break;
586 }
587
588 case T_FLOAT: {
589 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
590 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
591 } else {
592 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
593 __ ldrs(dest->as_float_reg(), Address(rscratch1));
594 }
595 break;
596 }
597
598 case T_DOUBLE: {
599 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
600 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
601 } else {
602 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
603 __ ldrd(dest->as_double_reg(), Address(rscratch1));
604 }
605 break;
606 }
607
608 default:
609 ShouldNotReachHere();
610 }
611 }
612
613 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
614 LIR_Const* c = src->as_constant_ptr();
615 switch (c->type()) {
616 case T_OBJECT:
617 {
618 if (! c->as_jobject())
619 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
620 else {
621 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
622 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
623 }
624 }
625 break;
626 case T_ADDRESS:
627 {
628 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
629 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
630 }
631 case T_INT:
632 case T_FLOAT:
633 {
634 Register reg = zr;
635 if (c->as_jint_bits() == 0)
636 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
637 else {
638 __ movw(rscratch1, c->as_jint_bits());
639 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
640 }
641 }
642 break;
643 case T_LONG:
644 case T_DOUBLE:
645 {
646 Register reg = zr;
647 if (c->as_jlong_bits() == 0)
648 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
649 lo_word_offset_in_bytes));
650 else {
651 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
652 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
653 lo_word_offset_in_bytes));
654 }
655 }
656 break;
657 default:
658 ShouldNotReachHere();
659 }
660 }
661
662 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
663 assert(src->is_constant(), "should not call otherwise");
664 LIR_Const* c = src->as_constant_ptr();
665 LIR_Address* to_addr = dest->as_address_ptr();
666
667 void (Assembler::* insn)(Register Rt, const Address &adr);
668
669 switch (type) {
670 case T_ADDRESS:
671 assert(c->as_jint() == 0, "should be");
672 insn = &Assembler::str;
673 break;
674 case T_LONG:
675 assert(c->as_jlong() == 0, "should be");
676 insn = &Assembler::str;
677 break;
678 case T_INT:
679 assert(c->as_jint() == 0, "should be");
680 insn = &Assembler::strw;
681 break;
682 case T_OBJECT:
683 case T_ARRAY:
684 // Non-null case is not handled on aarch64 but handled on x86
685 // FIXME: do we need to add it here?
686 assert(c->as_jobject() == nullptr, "should be");
687 if (UseCompressedOops && !wide) {
688 insn = &Assembler::strw;
689 } else {
690 insn = &Assembler::str;
691 }
692 break;
693 case T_CHAR:
694 case T_SHORT:
695 assert(c->as_jint() == 0, "should be");
696 insn = &Assembler::strh;
697 break;
698 case T_BOOLEAN:
699 case T_BYTE:
700 assert(c->as_jint() == 0, "should be");
701 insn = &Assembler::strb;
702 break;
703 default:
704 ShouldNotReachHere();
705 insn = &Assembler::str; // unreachable
706 }
707
708 if (info) add_debug_info_for_null_check_here(info);
709 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
710 }
711
712 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
713 assert(src->is_register(), "should not call otherwise");
714 assert(dest->is_register(), "should not call otherwise");
715
716 // move between cpu-registers
717 if (dest->is_single_cpu()) {
718 if (src->type() == T_LONG) {
719 // Can do LONG -> OBJECT
720 move_regs(src->as_register_lo(), dest->as_register());
721 return;
722 }
723 assert(src->is_single_cpu(), "must match");
724 if (src->type() == T_OBJECT) {
725 __ verify_oop(src->as_register());
726 }
727 move_regs(src->as_register(), dest->as_register());
728
729 } else if (dest->is_double_cpu()) {
730 if (is_reference_type(src->type())) {
731 // Surprising to me but we can see move of a long to t_object
732 __ verify_oop(src->as_register());
733 move_regs(src->as_register(), dest->as_register_lo());
734 return;
735 }
736 assert(src->is_double_cpu(), "must match");
737 Register f_lo = src->as_register_lo();
738 Register f_hi = src->as_register_hi();
739 Register t_lo = dest->as_register_lo();
740 Register t_hi = dest->as_register_hi();
741 assert(f_hi == f_lo, "must be same");
742 assert(t_hi == t_lo, "must be same");
743 move_regs(f_lo, t_lo);
744
745 } else if (dest->is_single_fpu()) {
746 __ fmovs(dest->as_float_reg(), src->as_float_reg());
747
748 } else if (dest->is_double_fpu()) {
749 __ fmovd(dest->as_double_reg(), src->as_double_reg());
750
751 } else {
752 ShouldNotReachHere();
753 }
754 }
755
756 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
757 precond(src->is_register() && dest->is_stack());
758
759 uint const c_sz32 = sizeof(uint32_t);
760 uint const c_sz64 = sizeof(uint64_t);
761
762 if (src->is_single_cpu()) {
763 int index = dest->single_stack_ix();
764 if (is_reference_type(type)) {
765 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
766 __ verify_oop(src->as_register());
767 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
768 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
769 } else {
770 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
771 }
772
773 } else if (src->is_double_cpu()) {
774 int index = dest->double_stack_ix();
775 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
776 __ str(src->as_register_lo(), dest_addr_LO);
777
778 } else if (src->is_single_fpu()) {
779 int index = dest->single_stack_ix();
780 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
781
782 } else if (src->is_double_fpu()) {
783 int index = dest->double_stack_ix();
784 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
785
786 } else {
787 ShouldNotReachHere();
788 }
789 }
790
791
792 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
793 LIR_Address* to_addr = dest->as_address_ptr();
794 PatchingStub* patch = nullptr;
795 Register compressed_src = rscratch1;
796
797 if (patch_code != lir_patch_none) {
798 deoptimize_trap(info);
799 return;
800 }
801
802 if (is_reference_type(type)) {
803 __ verify_oop(src->as_register());
804
805 if (UseCompressedOops && !wide) {
806 __ encode_heap_oop(compressed_src, src->as_register());
807 } else {
808 compressed_src = src->as_register();
809 }
810 }
811
812 int null_check_here = code_offset();
813 switch (type) {
814 case T_FLOAT: {
815 __ strs(src->as_float_reg(), as_Address(to_addr));
816 break;
817 }
818
819 case T_DOUBLE: {
820 __ strd(src->as_double_reg(), as_Address(to_addr));
821 break;
822 }
823
824 case T_ARRAY: // fall through
825 case T_OBJECT: // fall through
826 if (UseCompressedOops && !wide) {
827 __ strw(compressed_src, as_Address(to_addr, rscratch2));
828 } else {
829 __ str(compressed_src, as_Address(to_addr));
830 }
831 break;
832 case T_METADATA:
833 // We get here to store a method pointer to the stack to pass to
834 // a dtrace runtime call. This can't work on 64 bit with
835 // compressed klass ptrs: T_METADATA can be a compressed klass
836 // ptr or a 64 bit method pointer.
837 ShouldNotReachHere();
838 __ str(src->as_register(), as_Address(to_addr));
839 break;
840 case T_ADDRESS:
841 __ str(src->as_register(), as_Address(to_addr));
842 break;
843 case T_INT:
844 __ strw(src->as_register(), as_Address(to_addr));
845 break;
846
847 case T_LONG: {
848 __ str(src->as_register_lo(), as_Address_lo(to_addr));
849 break;
850 }
851
852 case T_BYTE: // fall through
853 case T_BOOLEAN: {
854 __ strb(src->as_register(), as_Address(to_addr));
855 break;
856 }
857
858 case T_CHAR: // fall through
859 case T_SHORT:
860 __ strh(src->as_register(), as_Address(to_addr));
861 break;
862
863 default:
864 ShouldNotReachHere();
865 }
866 if (info != nullptr) {
867 add_debug_info_for_null_check(null_check_here, info);
868 }
869 }
870
871
872 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
873 precond(src->is_stack() && dest->is_register());
874
875 uint const c_sz32 = sizeof(uint32_t);
876 uint const c_sz64 = sizeof(uint64_t);
877
878 if (dest->is_single_cpu()) {
879 int index = src->single_stack_ix();
880 if (is_reference_type(type)) {
881 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
882 __ verify_oop(dest->as_register());
883 } else if (type == T_METADATA || type == T_ADDRESS) {
884 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
885 } else {
886 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
887 }
888
889 } else if (dest->is_double_cpu()) {
890 int index = src->double_stack_ix();
891 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
892 __ ldr(dest->as_register_lo(), src_addr_LO);
893
894 } else if (dest->is_single_fpu()) {
895 int index = src->single_stack_ix();
896 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
897
898 } else if (dest->is_double_fpu()) {
899 int index = src->double_stack_ix();
900 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
901
902 } else {
903 ShouldNotReachHere();
904 }
905 }
906
907
908 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
909 address target = nullptr;
910 relocInfo::relocType reloc_type = relocInfo::none;
911
912 switch (patching_id(info)) {
913 case PatchingStub::access_field_id:
914 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
915 reloc_type = relocInfo::section_word_type;
916 break;
917 case PatchingStub::load_klass_id:
918 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
919 reloc_type = relocInfo::metadata_type;
920 break;
921 case PatchingStub::load_mirror_id:
922 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
923 reloc_type = relocInfo::oop_type;
924 break;
925 case PatchingStub::load_appendix_id:
926 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
927 reloc_type = relocInfo::oop_type;
928 break;
929 default: ShouldNotReachHere();
930 }
931
932 __ far_call(RuntimeAddress(target));
933 add_call_info_here(info);
934 }
935
936 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
937
938 LIR_Opr temp;
939 if (type == T_LONG || type == T_DOUBLE)
940 temp = FrameMap::rscratch1_long_opr;
941 else
942 temp = FrameMap::rscratch1_opr;
943
944 stack2reg(src, temp, src->type());
945 reg2stack(temp, dest, dest->type(), false);
946 }
947
948
949 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
950 LIR_Address* addr = src->as_address_ptr();
951 LIR_Address* from_addr = src->as_address_ptr();
952
953 if (addr->base()->type() == T_OBJECT) {
954 __ verify_oop(addr->base()->as_pointer_register());
955 }
956
957 if (patch_code != lir_patch_none) {
958 deoptimize_trap(info);
959 return;
960 }
961
962 if (info != nullptr) {
963 add_debug_info_for_null_check_here(info);
964 }
965 int null_check_here = code_offset();
966 switch (type) {
967 case T_FLOAT: {
968 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
969 break;
970 }
971
972 case T_DOUBLE: {
973 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
974 break;
975 }
976
977 case T_ARRAY: // fall through
978 case T_OBJECT: // fall through
979 if (UseCompressedOops && !wide) {
980 __ ldrw(dest->as_register(), as_Address(from_addr));
981 } else {
982 __ ldr(dest->as_register(), as_Address(from_addr));
983 }
984 break;
985 case T_METADATA:
986 // We get here to store a method pointer to the stack to pass to
987 // a dtrace runtime call. This can't work on 64 bit with
988 // compressed klass ptrs: T_METADATA can be a compressed klass
989 // ptr or a 64 bit method pointer.
990 ShouldNotReachHere();
991 __ ldr(dest->as_register(), as_Address(from_addr));
992 break;
993 case T_ADDRESS:
994 __ ldr(dest->as_register(), as_Address(from_addr));
995 break;
996 case T_INT:
997 __ ldrw(dest->as_register(), as_Address(from_addr));
998 break;
999
1000 case T_LONG: {
1001 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1002 break;
1003 }
1004
1005 case T_BYTE:
1006 __ ldrsb(dest->as_register(), as_Address(from_addr));
1007 break;
1008 case T_BOOLEAN: {
1009 __ ldrb(dest->as_register(), as_Address(from_addr));
1010 break;
1011 }
1012
1013 case T_CHAR:
1014 __ ldrh(dest->as_register(), as_Address(from_addr));
1015 break;
1016 case T_SHORT:
1017 __ ldrsh(dest->as_register(), as_Address(from_addr));
1018 break;
1019
1020 default:
1021 ShouldNotReachHere();
1022 }
1023
1024 if (is_reference_type(type)) {
1025 if (UseCompressedOops && !wide) {
1026 __ decode_heap_oop(dest->as_register());
1027 }
1028
1029 if (!(UseZGC && !ZGenerational)) {
1030 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1031 __ verify_oop(dest->as_register());
1032 }
1033 }
1034 }
1035
1036 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
1037 assert(dst->is_cpu_register(), "must be");
1038 assert(dst->type() == src->type(), "must be");
1039
1040 if (src->is_cpu_register()) {
1041 reg2reg(src, dst);
1042 } else if (src->is_stack()) {
1043 stack2reg(src, dst, dst->type());
1044 } else if (src->is_constant()) {
1045 const2reg(src, dst, lir_patch_none, nullptr);
1046 } else {
1047 ShouldNotReachHere();
1048 }
1049 }
1050
1051 int LIR_Assembler::array_element_size(BasicType type) const {
1052 int elem_size = type2aelembytes(type);
1053 return exact_log2(elem_size);
1054 }
1055
1056
1057 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1058 switch (op->code()) {
1059 case lir_idiv:
1060 case lir_irem:
1061 arithmetic_idiv(op->code(),
1062 op->in_opr1(),
1063 op->in_opr2(),
1064 op->in_opr3(),
1065 op->result_opr(),
1066 op->info());
1067 break;
1068 case lir_fmad:
1069 __ fmaddd(op->result_opr()->as_double_reg(),
1070 op->in_opr1()->as_double_reg(),
1071 op->in_opr2()->as_double_reg(),
1072 op->in_opr3()->as_double_reg());
1073 break;
1074 case lir_fmaf:
1075 __ fmadds(op->result_opr()->as_float_reg(),
1076 op->in_opr1()->as_float_reg(),
1077 op->in_opr2()->as_float_reg(),
1078 op->in_opr3()->as_float_reg());
1079 break;
1080 default: ShouldNotReachHere(); break;
1081 }
1082 }
1083
1084 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1085 #ifdef ASSERT
1086 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1087 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1088 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1089 #endif
1090
1091 if (op->cond() == lir_cond_always) {
1092 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1093 __ b(*(op->label()));
1094 } else {
1095 Assembler::Condition acond;
1096 if (op->code() == lir_cond_float_branch) {
1097 bool is_unordered = (op->ublock() == op->block());
1098 // Assembler::EQ does not permit unordered branches, so we add
1099 // another branch here. Likewise, Assembler::NE does not permit
1100 // ordered branches.
1101 if ((is_unordered && op->cond() == lir_cond_equal)
1102 || (!is_unordered && op->cond() == lir_cond_notEqual))
1103 __ br(Assembler::VS, *(op->ublock()->label()));
1104 switch(op->cond()) {
1105 case lir_cond_equal: acond = Assembler::EQ; break;
1106 case lir_cond_notEqual: acond = Assembler::NE; break;
1107 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1108 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1109 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1110 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1111 default: ShouldNotReachHere();
1112 acond = Assembler::EQ; // unreachable
1113 }
1114 } else {
1115 switch (op->cond()) {
1116 case lir_cond_equal: acond = Assembler::EQ; break;
1117 case lir_cond_notEqual: acond = Assembler::NE; break;
1118 case lir_cond_less: acond = Assembler::LT; break;
1119 case lir_cond_lessEqual: acond = Assembler::LE; break;
1120 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1121 case lir_cond_greater: acond = Assembler::GT; break;
1122 case lir_cond_belowEqual: acond = Assembler::LS; break;
1123 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1124 default: ShouldNotReachHere();
1125 acond = Assembler::EQ; // unreachable
1126 }
1127 }
1128 __ br(acond,*(op->label()));
1129 }
1130 }
1131
1132
1133
1134 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1135 LIR_Opr src = op->in_opr();
1136 LIR_Opr dest = op->result_opr();
1137
1138 switch (op->bytecode()) {
1139 case Bytecodes::_i2f:
1140 {
1141 __ scvtfws(dest->as_float_reg(), src->as_register());
1142 break;
1143 }
1144 case Bytecodes::_i2d:
1145 {
1146 __ scvtfwd(dest->as_double_reg(), src->as_register());
1147 break;
1148 }
1149 case Bytecodes::_l2d:
1150 {
1151 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1152 break;
1153 }
1154 case Bytecodes::_l2f:
1155 {
1156 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1157 break;
1158 }
1159 case Bytecodes::_f2d:
1160 {
1161 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1162 break;
1163 }
1164 case Bytecodes::_d2f:
1165 {
1166 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1167 break;
1168 }
1169 case Bytecodes::_i2c:
1170 {
1171 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1172 break;
1173 }
1174 case Bytecodes::_i2l:
1175 {
1176 __ sxtw(dest->as_register_lo(), src->as_register());
1177 break;
1178 }
1179 case Bytecodes::_i2s:
1180 {
1181 __ sxth(dest->as_register(), src->as_register());
1182 break;
1183 }
1184 case Bytecodes::_i2b:
1185 {
1186 __ sxtb(dest->as_register(), src->as_register());
1187 break;
1188 }
1189 case Bytecodes::_l2i:
1190 {
1191 _masm->block_comment("FIXME: This could be a no-op");
1192 __ uxtw(dest->as_register(), src->as_register_lo());
1193 break;
1194 }
1195 case Bytecodes::_d2l:
1196 {
1197 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1198 break;
1199 }
1200 case Bytecodes::_f2i:
1201 {
1202 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1203 break;
1204 }
1205 case Bytecodes::_f2l:
1206 {
1207 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1208 break;
1209 }
1210 case Bytecodes::_d2i:
1211 {
1212 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1213 break;
1214 }
1215 default: ShouldNotReachHere();
1216 }
1217 }
1218
1219 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1220 if (op->init_check()) {
1221 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1222 __ ldarb(rscratch1, rscratch1);
1223 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1224 add_debug_info_for_null_check_here(op->stub()->info());
1225 __ br(Assembler::NE, *op->stub()->entry());
1226 }
1227 __ allocate_object(op->obj()->as_register(),
1228 op->tmp1()->as_register(),
1229 op->tmp2()->as_register(),
1230 op->header_size(),
1231 op->object_size(),
1232 op->klass()->as_register(),
1233 *op->stub()->entry());
1234 __ bind(*op->stub()->continuation());
1235 }
1236
1237 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1238 Register len = op->len()->as_register();
1239 __ uxtw(len, len);
1240
1241 if (UseSlowPath || op->is_null_free() ||
1242 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1243 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1244 __ b(*op->stub()->entry());
1245 } else {
1246 Register tmp1 = op->tmp1()->as_register();
1247 Register tmp2 = op->tmp2()->as_register();
1248 Register tmp3 = op->tmp3()->as_register();
1249 if (len == tmp1) {
1250 tmp1 = tmp3;
1251 } else if (len == tmp2) {
1252 tmp2 = tmp3;
1253 } else if (len == tmp3) {
1254 // everything is ok
1255 } else {
1256 __ mov(tmp3, len);
1257 }
1258 __ allocate_array(op->obj()->as_register(),
1259 len,
1260 tmp1,
1261 tmp2,
1262 arrayOopDesc::base_offset_in_bytes(op->type()),
1263 array_element_size(op->type()),
1264 op->klass()->as_register(),
1265 *op->stub()->entry(),
1266 op->zero_array());
1267 }
1268 __ bind(*op->stub()->continuation());
1269 }
1270
1271 void LIR_Assembler::type_profile_helper(Register mdo,
1272 ciMethodData *md, ciProfileData *data,
1273 Register recv, Label* update_done) {
1274 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1275 Label next_test;
1276 // See if the receiver is receiver[n].
1277 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1278 __ ldr(rscratch1, Address(rscratch2));
1279 __ cmp(recv, rscratch1);
1280 __ br(Assembler::NE, next_test);
1281 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1282 __ addptr(data_addr, DataLayout::counter_increment);
1283 __ b(*update_done);
1284 __ bind(next_test);
1285 }
1286
1287 // Didn't find receiver; find next empty slot and fill it in
1288 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1289 Label next_test;
1290 __ lea(rscratch2,
1291 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1292 Address recv_addr(rscratch2);
1293 __ ldr(rscratch1, recv_addr);
1294 __ cbnz(rscratch1, next_test);
1295 __ str(recv, recv_addr);
1296 __ mov(rscratch1, DataLayout::counter_increment);
1297 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1298 __ str(rscratch1, Address(rscratch2));
1299 __ b(*update_done);
1300 __ bind(next_test);
1301 }
1302 }
1303
1304 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1305 // we always need a stub for the failure case.
1306 CodeStub* stub = op->stub();
1307 Register obj = op->object()->as_register();
1308 Register k_RInfo = op->tmp1()->as_register();
1309 Register klass_RInfo = op->tmp2()->as_register();
1310 Register dst = op->result_opr()->as_register();
1311 ciKlass* k = op->klass();
1312 Register Rtmp1 = noreg;
1313
1314 // check if it needs to be profiled
1315 ciMethodData* md;
1316 ciProfileData* data;
1317
1318 const bool should_profile = op->should_profile();
1319
1320 if (should_profile) {
1321 ciMethod* method = op->profiled_method();
1322 assert(method != nullptr, "Should have method");
1323 int bci = op->profiled_bci();
1324 md = method->method_data_or_null();
1325 assert(md != nullptr, "Sanity");
1326 data = md->bci_to_data(bci);
1327 assert(data != nullptr, "need data for type check");
1328 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1329 }
1330 Label* success_target = success;
1331 Label* failure_target = failure;
1332
1333 if (obj == k_RInfo) {
1334 k_RInfo = dst;
1335 } else if (obj == klass_RInfo) {
1336 klass_RInfo = dst;
1337 }
1338 if (k->is_loaded() && !UseCompressedClassPointers) {
1339 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1340 } else {
1341 Rtmp1 = op->tmp3()->as_register();
1342 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1343 }
1344
1345 assert_different_registers(obj, k_RInfo, klass_RInfo);
1346
1347 if (op->need_null_check()) {
1348 if (should_profile) {
1349 Register mdo = klass_RInfo;
1350 __ mov_metadata(mdo, md->constant_encoding());
1351 Label not_null;
1352 __ cbnz(obj, not_null);
1353 // Object is null; update MDO and exit
1354 Address data_addr
1355 = __ form_address(rscratch2, mdo,
1356 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1357 0);
1358 __ ldrb(rscratch1, data_addr);
1359 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1360 __ strb(rscratch1, data_addr);
1361 __ b(*obj_is_null);
1362 __ bind(not_null);
1363
1364 Label update_done;
1365 Register recv = k_RInfo;
1366 __ load_klass(recv, obj);
1367 type_profile_helper(mdo, md, data, recv, &update_done);
1368 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1369 __ addptr(counter_addr, DataLayout::counter_increment);
1370
1371 __ bind(update_done);
1372 } else {
1373 __ cbz(obj, *obj_is_null);
1374 }
1375 }
1376
1377 if (!k->is_loaded()) {
1378 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1379 } else {
1380 __ mov_metadata(k_RInfo, k->constant_encoding());
1381 }
1382 __ verify_oop(obj);
1383
1384 if (op->fast_check()) {
1385 // get object class
1386 // not a safepoint as obj null check happens earlier
1387 __ load_klass(rscratch1, obj);
1388 __ cmp( rscratch1, k_RInfo);
1389
1390 __ br(Assembler::NE, *failure_target);
1391 // successful cast, fall through to profile or jump
1392 } else {
1393 // get object class
1394 // not a safepoint as obj null check happens earlier
1395 __ load_klass(klass_RInfo, obj);
1396 if (k->is_loaded()) {
1397 // See if we get an immediate positive hit
1398 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1399 __ cmp(k_RInfo, rscratch1);
1400 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1401 __ br(Assembler::NE, *failure_target);
1402 // successful cast, fall through to profile or jump
1403 } else {
1404 // See if we get an immediate positive hit
1405 __ br(Assembler::EQ, *success_target);
1406 // check for self
1407 __ cmp(klass_RInfo, k_RInfo);
1408 __ br(Assembler::EQ, *success_target);
1409
1410 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1411 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1412 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1413 // result is a boolean
1414 __ cbzw(klass_RInfo, *failure_target);
1415 // successful cast, fall through to profile or jump
1416 }
1417 } else {
1418 // perform the fast part of the checking logic
1419 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1420 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1421 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1422 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1423 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1424 // result is a boolean
1425 __ cbz(k_RInfo, *failure_target);
1426 // successful cast, fall through to profile or jump
1427 }
1428 }
1429 __ b(*success);
1430 }
1431
1432
1433 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1434 const bool should_profile = op->should_profile();
1435
1436 LIR_Code code = op->code();
1437 if (code == lir_store_check) {
1438 Register value = op->object()->as_register();
1439 Register array = op->array()->as_register();
1440 Register k_RInfo = op->tmp1()->as_register();
1441 Register klass_RInfo = op->tmp2()->as_register();
1442 Register Rtmp1 = op->tmp3()->as_register();
1443
1444 CodeStub* stub = op->stub();
1445
1446 // check if it needs to be profiled
1447 ciMethodData* md;
1448 ciProfileData* data;
1449
1450 if (should_profile) {
1451 ciMethod* method = op->profiled_method();
1452 assert(method != nullptr, "Should have method");
1453 int bci = op->profiled_bci();
1454 md = method->method_data_or_null();
1455 assert(md != nullptr, "Sanity");
1456 data = md->bci_to_data(bci);
1457 assert(data != nullptr, "need data for type check");
1458 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1459 }
1460 Label done;
1461 Label* success_target = &done;
1462 Label* failure_target = stub->entry();
1463
1464 if (should_profile) {
1465 Label not_null;
1466 Register mdo = klass_RInfo;
1467 __ mov_metadata(mdo, md->constant_encoding());
1468 __ cbnz(value, not_null);
1469 // Object is null; update MDO and exit
1470 Address data_addr
1471 = __ form_address(rscratch2, mdo,
1472 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1473 0);
1474 __ ldrb(rscratch1, data_addr);
1475 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1476 __ strb(rscratch1, data_addr);
1477 __ b(done);
1478 __ bind(not_null);
1479
1480 Label update_done;
1481 Register recv = k_RInfo;
1482 __ load_klass(recv, value);
1483 type_profile_helper(mdo, md, data, recv, &update_done);
1484 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1485 __ addptr(counter_addr, DataLayout::counter_increment);
1486 __ bind(update_done);
1487 } else {
1488 __ cbz(value, done);
1489 }
1490
1491 add_debug_info_for_null_check_here(op->info_for_exception());
1492 __ load_klass(k_RInfo, array);
1493 __ load_klass(klass_RInfo, value);
1494
1495 // get instance klass (it's already uncompressed)
1496 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1497 // perform the fast part of the checking logic
1498 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1499 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1500 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1501 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1502 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1503 // result is a boolean
1504 __ cbzw(k_RInfo, *failure_target);
1505 // fall through to the success case
1506
1507 __ bind(done);
1508 } else if (code == lir_checkcast) {
1509 Register obj = op->object()->as_register();
1510 Register dst = op->result_opr()->as_register();
1511 Label success;
1512 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1513 __ bind(success);
1514 if (dst != obj) {
1515 __ mov(dst, obj);
1516 }
1517 } else if (code == lir_instanceof) {
1518 Register obj = op->object()->as_register();
1519 Register dst = op->result_opr()->as_register();
1520 Label success, failure, done;
1521 emit_typecheck_helper(op, &success, &failure, &failure);
1522 __ bind(failure);
1523 __ mov(dst, zr);
1524 __ b(done);
1525 __ bind(success);
1526 __ mov(dst, 1);
1527 __ bind(done);
1528 } else {
1529 ShouldNotReachHere();
1530 }
1531 }
1532
1533 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1534 // We are loading/storing from/to an array that *may* be a flat array (the
1535 // declared type is Object[], abstract[], interface[] or VT.ref[]).
1536 // If this array is a flat array, take the slow path.
1537 __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1538 if (!op->value()->is_illegal()) {
1539 // The array is not a flat array, but it might be null-free. If we are storing
1540 // a null into a null-free array, take the slow path (which will throw NPE).
1541 Label skip;
1542 __ cbnz(op->value()->as_register(), skip);
1543 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1544 __ bind(skip);
1545 }
1546 }
1547
1548 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1549 // We are storing into an array that *may* be null-free (the declared type is
1550 // Object[], abstract[], interface[] or VT.ref[]).
1551 Label test_mark_word;
1552 Register tmp = op->tmp()->as_register();
1553 __ ldr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
1554 __ tst(tmp, markWord::unlocked_value);
1555 __ br(Assembler::NE, test_mark_word);
1556 __ load_prototype_header(tmp, op->array()->as_register());
1557 __ bind(test_mark_word);
1558 __ tst(tmp, markWord::null_free_array_bit_in_place);
1559 }
1560
1561 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1562 Label L_oops_equal;
1563 Label L_oops_not_equal;
1564 Label L_end;
1565
1566 Register left = op->left()->as_register();
1567 Register right = op->right()->as_register();
1568
1569 __ cmp(left, right);
1570 __ br(Assembler::EQ, L_oops_equal);
1571
1572 // (1) Null check -- if one of the operands is null, the other must not be null (because
1573 // the two references are not equal), so they are not substitutable,
1574 // FIXME: do null check only if the operand is nullable
1575 {
1576 __ cbz(left, L_oops_not_equal);
1577 __ cbz(right, L_oops_not_equal);
1578 }
1579
1580 ciKlass* left_klass = op->left_klass();
1581 ciKlass* right_klass = op->right_klass();
1582
1583 // (2) Inline type check -- if either of the operands is not a inline type,
1584 // they are not substitutable. We do this only if we are not sure that the
1585 // operands are inline type
1586 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node.
1587 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
1588 Register tmp1 = op->tmp1()->as_register();
1589 __ mov(tmp1, markWord::inline_type_pattern);
1590 __ ldr(rscratch1, Address(left, oopDesc::mark_offset_in_bytes()));
1591 __ andr(tmp1, tmp1, rscratch1);
1592 __ ldr(rscratch1, Address(right, oopDesc::mark_offset_in_bytes()));
1593 __ andr(tmp1, tmp1, rscratch1);
1594 __ cmp(tmp1, (u1)markWord::inline_type_pattern);
1595 __ br(Assembler::NE, L_oops_not_equal);
1596 }
1597
1598 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
1599 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) {
1600 // No need to load klass -- the operands are statically known to be the same inline klass.
1601 __ b(*op->stub()->entry());
1602 } else {
1603 Register left_klass_op = op->left_klass_op()->as_register();
1604 Register right_klass_op = op->right_klass_op()->as_register();
1605
1606 if (UseCompressedClassPointers) {
1607 __ ldrw(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1608 __ ldrw(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1609 __ cmpw(left_klass_op, right_klass_op);
1610 } else {
1611 __ ldr(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1612 __ ldr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1613 __ cmp(left_klass_op, right_klass_op);
1614 }
1615
1616 __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check
1617 // fall through to L_oops_not_equal
1618 }
1619
1620 __ bind(L_oops_not_equal);
1621 move(op->not_equal_result(), op->result_opr());
1622 __ b(L_end);
1623
1624 __ bind(L_oops_equal);
1625 move(op->equal_result(), op->result_opr());
1626 __ b(L_end);
1627
1628 // We've returned from the stub. R0 contains 0x0 IFF the two
1629 // operands are not substitutable. (Don't compare against 0x1 in case the
1630 // C compiler is naughty)
1631 __ bind(*op->stub()->continuation());
1632 __ cbz(r0, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1633 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
1634 // fall-through
1635 __ bind(L_end);
1636 }
1637
1638
1639 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1640 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1641 __ cset(rscratch1, Assembler::NE);
1642 __ membar(__ AnyAny);
1643 }
1644
1645 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1646 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1647 __ cset(rscratch1, Assembler::NE);
1648 __ membar(__ AnyAny);
1649 }
1650
1651
1652 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1653 Register addr;
1654 if (op->addr()->is_register()) {
1655 addr = as_reg(op->addr());
1656 } else {
1657 assert(op->addr()->is_address(), "what else?");
1658 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1659 assert(addr_ptr->disp() == 0, "need 0 disp");
1660 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1661 addr = as_reg(addr_ptr->base());
1662 }
1663 Register newval = as_reg(op->new_value());
1664 Register cmpval = as_reg(op->cmp_value());
1665
1666 if (op->code() == lir_cas_obj) {
1667 if (UseCompressedOops) {
1668 Register t1 = op->tmp1()->as_register();
1669 assert(op->tmp1()->is_valid(), "must be");
1670 __ encode_heap_oop(t1, cmpval);
1671 cmpval = t1;
1672 __ encode_heap_oop(rscratch2, newval);
1673 newval = rscratch2;
1674 casw(addr, newval, cmpval);
1675 } else {
1676 casl(addr, newval, cmpval);
1677 }
1678 } else if (op->code() == lir_cas_int) {
1679 casw(addr, newval, cmpval);
1680 } else {
1681 casl(addr, newval, cmpval);
1682 }
1683 }
1684
1685
1686 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1687 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1688 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1689
1690 Assembler::Condition acond, ncond;
1691 switch (condition) {
1692 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1693 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1694 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1695 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1696 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1697 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1698 case lir_cond_belowEqual:
1699 case lir_cond_aboveEqual:
1700 default: ShouldNotReachHere();
1701 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1702 }
1703
1704 assert(result->is_single_cpu() || result->is_double_cpu(),
1705 "expect single register for result");
1706 if (opr1->is_constant() && opr2->is_constant()
1707 && opr1->type() == T_INT && opr2->type() == T_INT) {
1708 jint val1 = opr1->as_jint();
1709 jint val2 = opr2->as_jint();
1710 if (val1 == 0 && val2 == 1) {
1711 __ cset(result->as_register(), ncond);
1712 return;
1713 } else if (val1 == 1 && val2 == 0) {
1714 __ cset(result->as_register(), acond);
1715 return;
1716 }
1717 }
1718
1719 if (opr1->is_constant() && opr2->is_constant()
1720 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1721 jlong val1 = opr1->as_jlong();
1722 jlong val2 = opr2->as_jlong();
1723 if (val1 == 0 && val2 == 1) {
1724 __ cset(result->as_register_lo(), ncond);
1725 return;
1726 } else if (val1 == 1 && val2 == 0) {
1727 __ cset(result->as_register_lo(), acond);
1728 return;
1729 }
1730 }
1731
1732 if (opr1->is_stack()) {
1733 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1734 opr1 = FrameMap::rscratch1_opr;
1735 } else if (opr1->is_constant()) {
1736 LIR_Opr tmp
1737 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1738 const2reg(opr1, tmp, lir_patch_none, nullptr);
1739 opr1 = tmp;
1740 }
1741
1742 if (opr2->is_stack()) {
1743 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1744 opr2 = FrameMap::rscratch2_opr;
1745 } else if (opr2->is_constant()) {
1746 LIR_Opr tmp
1747 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1748 const2reg(opr2, tmp, lir_patch_none, nullptr);
1749 opr2 = tmp;
1750 }
1751
1752 if (result->type() == T_LONG)
1753 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1754 else
1755 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1756 }
1757
1758 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1759 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1760
1761 if (left->is_single_cpu()) {
1762 Register lreg = left->as_register();
1763 Register dreg = as_reg(dest);
1764
1765 if (right->is_single_cpu()) {
1766 // cpu register - cpu register
1767
1768 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1769 "should be");
1770 Register rreg = right->as_register();
1771 switch (code) {
1772 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1773 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1774 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1775 default: ShouldNotReachHere();
1776 }
1777
1778 } else if (right->is_double_cpu()) {
1779 Register rreg = right->as_register_lo();
1780 // single_cpu + double_cpu: can happen with obj+long
1781 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1782 switch (code) {
1783 case lir_add: __ add(dreg, lreg, rreg); break;
1784 case lir_sub: __ sub(dreg, lreg, rreg); break;
1785 default: ShouldNotReachHere();
1786 }
1787 } else if (right->is_constant()) {
1788 // cpu register - constant
1789 jlong c;
1790
1791 // FIXME. This is fugly: we really need to factor all this logic.
1792 switch(right->type()) {
1793 case T_LONG:
1794 c = right->as_constant_ptr()->as_jlong();
1795 break;
1796 case T_INT:
1797 case T_ADDRESS:
1798 c = right->as_constant_ptr()->as_jint();
1799 break;
1800 default:
1801 ShouldNotReachHere();
1802 c = 0; // unreachable
1803 break;
1804 }
1805
1806 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1807 if (c == 0 && dreg == lreg) {
1808 COMMENT("effective nop elided");
1809 return;
1810 }
1811 switch(left->type()) {
1812 case T_INT:
1813 switch (code) {
1814 case lir_add: __ addw(dreg, lreg, c); break;
1815 case lir_sub: __ subw(dreg, lreg, c); break;
1816 default: ShouldNotReachHere();
1817 }
1818 break;
1819 case T_OBJECT:
1820 case T_ADDRESS:
1821 switch (code) {
1822 case lir_add: __ add(dreg, lreg, c); break;
1823 case lir_sub: __ sub(dreg, lreg, c); break;
1824 default: ShouldNotReachHere();
1825 }
1826 break;
1827 default:
1828 ShouldNotReachHere();
1829 }
1830 } else {
1831 ShouldNotReachHere();
1832 }
1833
1834 } else if (left->is_double_cpu()) {
1835 Register lreg_lo = left->as_register_lo();
1836
1837 if (right->is_double_cpu()) {
1838 // cpu register - cpu register
1839 Register rreg_lo = right->as_register_lo();
1840 switch (code) {
1841 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1842 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1843 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1844 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1845 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1846 default:
1847 ShouldNotReachHere();
1848 }
1849
1850 } else if (right->is_constant()) {
1851 jlong c = right->as_constant_ptr()->as_jlong();
1852 Register dreg = as_reg(dest);
1853 switch (code) {
1854 case lir_add:
1855 case lir_sub:
1856 if (c == 0 && dreg == lreg_lo) {
1857 COMMENT("effective nop elided");
1858 return;
1859 }
1860 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1861 break;
1862 case lir_div:
1863 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1864 if (c == 1) {
1865 // move lreg_lo to dreg if divisor is 1
1866 __ mov(dreg, lreg_lo);
1867 } else {
1868 unsigned int shift = log2i_exact(c);
1869 // use rscratch1 as intermediate result register
1870 __ asr(rscratch1, lreg_lo, 63);
1871 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1872 __ asr(dreg, rscratch1, shift);
1873 }
1874 break;
1875 case lir_rem:
1876 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1877 if (c == 1) {
1878 // move 0 to dreg if divisor is 1
1879 __ mov(dreg, zr);
1880 } else {
1881 // use rscratch1 as intermediate result register
1882 __ negs(rscratch1, lreg_lo);
1883 __ andr(dreg, lreg_lo, c - 1);
1884 __ andr(rscratch1, rscratch1, c - 1);
1885 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1886 }
1887 break;
1888 default:
1889 ShouldNotReachHere();
1890 }
1891 } else {
1892 ShouldNotReachHere();
1893 }
1894 } else if (left->is_single_fpu()) {
1895 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1896 switch (code) {
1897 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1898 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1899 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1900 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1901 default:
1902 ShouldNotReachHere();
1903 }
1904 } else if (left->is_double_fpu()) {
1905 if (right->is_double_fpu()) {
1906 // fpu register - fpu register
1907 switch (code) {
1908 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1909 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1910 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1911 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1912 default:
1913 ShouldNotReachHere();
1914 }
1915 } else {
1916 if (right->is_constant()) {
1917 ShouldNotReachHere();
1918 }
1919 ShouldNotReachHere();
1920 }
1921 } else if (left->is_single_stack() || left->is_address()) {
1922 assert(left == dest, "left and dest must be equal");
1923 ShouldNotReachHere();
1924 } else {
1925 ShouldNotReachHere();
1926 }
1927 }
1928
1929 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1930
1931
1932 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1933 switch(code) {
1934 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1935 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1936 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1937 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1938 default : ShouldNotReachHere();
1939 }
1940 }
1941
1942 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1943
1944 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1945 Register Rleft = left->is_single_cpu() ? left->as_register() :
1946 left->as_register_lo();
1947 if (dst->is_single_cpu()) {
1948 Register Rdst = dst->as_register();
1949 if (right->is_constant()) {
1950 switch (code) {
1951 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1952 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1953 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1954 default: ShouldNotReachHere(); break;
1955 }
1956 } else {
1957 Register Rright = right->is_single_cpu() ? right->as_register() :
1958 right->as_register_lo();
1959 switch (code) {
1960 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1961 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1962 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1963 default: ShouldNotReachHere(); break;
1964 }
1965 }
1966 } else {
1967 Register Rdst = dst->as_register_lo();
1968 if (right->is_constant()) {
1969 switch (code) {
1970 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1971 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1972 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1973 default: ShouldNotReachHere(); break;
1974 }
1975 } else {
1976 Register Rright = right->is_single_cpu() ? right->as_register() :
1977 right->as_register_lo();
1978 switch (code) {
1979 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1980 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1981 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1982 default: ShouldNotReachHere(); break;
1983 }
1984 }
1985 }
1986 }
1987
1988
1989
1990 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1991
1992 // opcode check
1993 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1994 bool is_irem = (code == lir_irem);
1995
1996 // operand check
1997 assert(left->is_single_cpu(), "left must be register");
1998 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1999 assert(result->is_single_cpu(), "result must be register");
2000 Register lreg = left->as_register();
2001 Register dreg = result->as_register();
2002
2003 // power-of-2 constant check and codegen
2004 if (right->is_constant()) {
2005 int c = right->as_constant_ptr()->as_jint();
2006 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
2007 if (is_irem) {
2008 if (c == 1) {
2009 // move 0 to dreg if divisor is 1
2010 __ movw(dreg, zr);
2011 } else {
2012 // use rscratch1 as intermediate result register
2013 __ negsw(rscratch1, lreg);
2014 __ andw(dreg, lreg, c - 1);
2015 __ andw(rscratch1, rscratch1, c - 1);
2016 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
2017 }
2018 } else {
2019 if (c == 1) {
2020 // move lreg to dreg if divisor is 1
2021 __ movw(dreg, lreg);
2022 } else {
2023 unsigned int shift = exact_log2(c);
2024 // use rscratch1 as intermediate result register
2025 __ asrw(rscratch1, lreg, 31);
2026 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
2027 __ asrw(dreg, rscratch1, shift);
2028 }
2029 }
2030 } else {
2031 Register rreg = right->as_register();
2032 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
2033 }
2034 }
2035
2036
2037 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2038 if (opr1->is_constant() && opr2->is_single_cpu()) {
2039 // tableswitch
2040 Register reg = as_reg(opr2);
2041 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
2042 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
2043 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
2044 Register reg1 = as_reg(opr1);
2045 if (opr2->is_single_cpu()) {
2046 // cpu register - cpu register
2047 Register reg2 = opr2->as_register();
2048 if (is_reference_type(opr1->type())) {
2049 __ cmpoop(reg1, reg2);
2050 } else {
2051 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2052 __ cmpw(reg1, reg2);
2053 }
2054 return;
2055 }
2056 if (opr2->is_double_cpu()) {
2057 // cpu register - cpu register
2058 Register reg2 = opr2->as_register_lo();
2059 __ cmp(reg1, reg2);
2060 return;
2061 }
2062
2063 if (opr2->is_constant()) {
2064 bool is_32bit = false; // width of register operand
2065 jlong imm;
2066
2067 switch(opr2->type()) {
2068 case T_INT:
2069 imm = opr2->as_constant_ptr()->as_jint();
2070 is_32bit = true;
2071 break;
2072 case T_LONG:
2073 imm = opr2->as_constant_ptr()->as_jlong();
2074 break;
2075 case T_ADDRESS:
2076 imm = opr2->as_constant_ptr()->as_jint();
2077 break;
2078 case T_METADATA:
2079 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
2080 break;
2081 case T_OBJECT:
2082 case T_ARRAY:
2083 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
2084 __ cmpoop(reg1, rscratch1);
2085 return;
2086 default:
2087 ShouldNotReachHere();
2088 imm = 0; // unreachable
2089 break;
2090 }
2091
2092 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
2093 if (is_32bit)
2094 __ cmpw(reg1, imm);
2095 else
2096 __ subs(zr, reg1, imm);
2097 return;
2098 } else {
2099 __ mov(rscratch1, imm);
2100 if (is_32bit)
2101 __ cmpw(reg1, rscratch1);
2102 else
2103 __ cmp(reg1, rscratch1);
2104 return;
2105 }
2106 } else
2107 ShouldNotReachHere();
2108 } else if (opr1->is_single_fpu()) {
2109 FloatRegister reg1 = opr1->as_float_reg();
2110 assert(opr2->is_single_fpu(), "expect single float register");
2111 FloatRegister reg2 = opr2->as_float_reg();
2112 __ fcmps(reg1, reg2);
2113 } else if (opr1->is_double_fpu()) {
2114 FloatRegister reg1 = opr1->as_double_reg();
2115 assert(opr2->is_double_fpu(), "expect double float register");
2116 FloatRegister reg2 = opr2->as_double_reg();
2117 __ fcmpd(reg1, reg2);
2118 } else {
2119 ShouldNotReachHere();
2120 }
2121 }
2122
2123 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2124 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2125 bool is_unordered_less = (code == lir_ucmp_fd2i);
2126 if (left->is_single_fpu()) {
2127 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2128 } else if (left->is_double_fpu()) {
2129 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2130 } else {
2131 ShouldNotReachHere();
2132 }
2133 } else if (code == lir_cmp_l2i) {
2134 Label done;
2135 __ cmp(left->as_register_lo(), right->as_register_lo());
2136 __ mov(dst->as_register(), (uint64_t)-1L);
2137 __ br(Assembler::LT, done);
2138 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2139 __ bind(done);
2140 } else {
2141 ShouldNotReachHere();
2142 }
2143 }
2144
2145
2146 void LIR_Assembler::align_call(LIR_Code code) { }
2147
2148
2149 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2150 address call = __ trampoline_call(Address(op->addr(), rtype));
2151 if (call == nullptr) {
2152 bailout("trampoline stub overflow");
2153 return;
2154 }
2155 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2156 __ post_call_nop();
2157 }
2158
2159
2160 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2161 address call = __ ic_call(op->addr());
2162 if (call == nullptr) {
2163 bailout("trampoline stub overflow");
2164 return;
2165 }
2166 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2167 __ post_call_nop();
2168 }
2169
2170 void LIR_Assembler::emit_static_call_stub() {
2171 address call_pc = __ pc();
2172 address stub = __ start_a_stub(call_stub_size());
2173 if (stub == nullptr) {
2174 bailout("static call stub overflow");
2175 return;
2176 }
2177
2178 int start = __ offset();
2179
2180 __ relocate(static_stub_Relocation::spec(call_pc));
2181 __ emit_static_call_stub();
2182
2183 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2184 <= call_stub_size(), "stub too big");
2185 __ end_a_stub();
2186 }
2187
2188
2189 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2190 assert(exceptionOop->as_register() == r0, "must match");
2191 assert(exceptionPC->as_register() == r3, "must match");
2192
2193 // exception object is not added to oop map by LinearScan
2194 // (LinearScan assumes that no oops are in fixed registers)
2195 info->add_register_oop(exceptionOop);
2196 C1StubId unwind_id;
2197
2198 // get current pc information
2199 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2200 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2201 // As no instructions have been generated yet for this LIR node it's
2202 // possible that an oop map already exists for the current offset.
2203 // In that case insert an dummy NOP here to ensure all oop map PCs
2204 // are unique. See JDK-8237483.
2205 __ nop();
2206 }
2207 int pc_for_athrow_offset = __ offset();
2208 InternalAddress pc_for_athrow(__ pc());
2209 __ adr(exceptionPC->as_register(), pc_for_athrow);
2210 add_call_info(pc_for_athrow_offset, info); // for exception handler
2211
2212 __ verify_not_null_oop(r0);
2213 // search an exception handler (r0: exception oop, r3: throwing pc)
2214 if (compilation()->has_fpu_code()) {
2215 unwind_id = C1StubId::handle_exception_id;
2216 } else {
2217 unwind_id = C1StubId::handle_exception_nofpu_id;
2218 }
2219 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2220
2221 // FIXME: enough room for two byte trap ????
2222 __ nop();
2223 }
2224
2225
2226 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2227 assert(exceptionOop->as_register() == r0, "must match");
2228
2229 __ b(_unwind_handler_entry);
2230 }
2231
2232
2233 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2234 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2235 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2236
2237 switch (left->type()) {
2238 case T_INT: {
2239 switch (code) {
2240 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2241 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2242 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2243 default:
2244 ShouldNotReachHere();
2245 break;
2246 }
2247 break;
2248 case T_LONG:
2249 case T_ADDRESS:
2250 case T_OBJECT:
2251 switch (code) {
2252 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2253 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2254 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2255 default:
2256 ShouldNotReachHere();
2257 break;
2258 }
2259 break;
2260 default:
2261 ShouldNotReachHere();
2262 break;
2263 }
2264 }
2265 }
2266
2267
2268 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2269 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2270 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2271
2272 switch (left->type()) {
2273 case T_INT: {
2274 switch (code) {
2275 case lir_shl: __ lslw (dreg, lreg, count); break;
2276 case lir_shr: __ asrw (dreg, lreg, count); break;
2277 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2278 default:
2279 ShouldNotReachHere();
2280 break;
2281 }
2282 break;
2283 case T_LONG:
2284 case T_ADDRESS:
2285 case T_OBJECT:
2286 switch (code) {
2287 case lir_shl: __ lsl (dreg, lreg, count); break;
2288 case lir_shr: __ asr (dreg, lreg, count); break;
2289 case lir_ushr: __ lsr (dreg, lreg, count); break;
2290 default:
2291 ShouldNotReachHere();
2292 break;
2293 }
2294 break;
2295 default:
2296 ShouldNotReachHere();
2297 break;
2298 }
2299 }
2300 }
2301
2302
2303 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2304 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2305 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2306 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2307 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2308 }
2309
2310
2311 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2312 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2313 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2314 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2315 __ mov (rscratch1, c);
2316 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2317 }
2318
2319
2320 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2321 ShouldNotReachHere();
2322 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2323 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2324 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2325 __ lea(rscratch1, __ constant_oop_address(o));
2326 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2327 }
2328
2329 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
2330 if (null_check) {
2331 __ cbz(obj, *slow_path->entry());
2332 }
2333 if (is_dest) {
2334 __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
2335 } else {
2336 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2337 }
2338 }
2339
2340 // This code replaces a call to arraycopy; no exception may
2341 // be thrown in this code, they must be thrown in the System.arraycopy
2342 // activation frame; we could save some checks if this would not be the case
2343 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2344 ciArrayKlass* default_type = op->expected_type();
2345 Register src = op->src()->as_register();
2346 Register dst = op->dst()->as_register();
2347 Register src_pos = op->src_pos()->as_register();
2348 Register dst_pos = op->dst_pos()->as_register();
2349 Register length = op->length()->as_register();
2350 Register tmp = op->tmp()->as_register();
2351
2352 CodeStub* stub = op->stub();
2353 int flags = op->flags();
2354 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2355 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2356
2357 if (flags & LIR_OpArrayCopy::always_slow_path) {
2358 __ b(*stub->entry());
2359 __ bind(*stub->continuation());
2360 return;
2361 }
2362
2363 // if we don't know anything, just go through the generic arraycopy
2364 if (default_type == nullptr // || basic_type == T_OBJECT
2365 ) {
2366 Label done;
2367 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2368
2369 // Save the arguments in case the generic arraycopy fails and we
2370 // have to fall back to the JNI stub
2371 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2372 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2373 __ str(src, Address(sp, 4*BytesPerWord));
2374
2375 address copyfunc_addr = StubRoutines::generic_arraycopy();
2376 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2377
2378 // The arguments are in java calling convention so we shift them
2379 // to C convention
2380 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2381 __ mov(c_rarg0, j_rarg0);
2382 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2383 __ mov(c_rarg1, j_rarg1);
2384 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2385 __ mov(c_rarg2, j_rarg2);
2386 assert_different_registers(c_rarg3, j_rarg4);
2387 __ mov(c_rarg3, j_rarg3);
2388 __ mov(c_rarg4, j_rarg4);
2389 #ifndef PRODUCT
2390 if (PrintC1Statistics) {
2391 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2392 }
2393 #endif
2394 __ far_call(RuntimeAddress(copyfunc_addr));
2395
2396 __ cbz(r0, *stub->continuation());
2397
2398 // Reload values from the stack so they are where the stub
2399 // expects them.
2400 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2401 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2402 __ ldr(src, Address(sp, 4*BytesPerWord));
2403
2404 // r0 is -1^K where K == partial copied count
2405 __ eonw(rscratch1, r0, zr);
2406 // adjust length down and src/end pos up by partial copied count
2407 __ subw(length, length, rscratch1);
2408 __ addw(src_pos, src_pos, rscratch1);
2409 __ addw(dst_pos, dst_pos, rscratch1);
2410 __ b(*stub->entry());
2411
2412 __ bind(*stub->continuation());
2413 return;
2414 }
2415
2416 // Handle inline type arrays
2417 if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
2418 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
2419 }
2420
2421 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
2422 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
2423 }
2424
2425 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2426
2427 int elem_size = type2aelembytes(basic_type);
2428 int scale = exact_log2(elem_size);
2429
2430 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2431 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2432 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2433 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2434
2435 // test for null
2436 if (flags & LIR_OpArrayCopy::src_null_check) {
2437 __ cbz(src, *stub->entry());
2438 }
2439 if (flags & LIR_OpArrayCopy::dst_null_check) {
2440 __ cbz(dst, *stub->entry());
2441 }
2442
2443 // If the compiler was not able to prove that exact type of the source or the destination
2444 // of the arraycopy is an array type, check at runtime if the source or the destination is
2445 // an instance type.
2446 if (flags & LIR_OpArrayCopy::type_check) {
2447 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2448 __ load_klass(tmp, dst);
2449 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2450 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2451 __ br(Assembler::GE, *stub->entry());
2452 }
2453
2454 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2455 __ load_klass(tmp, src);
2456 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2457 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2458 __ br(Assembler::GE, *stub->entry());
2459 }
2460 }
2461
2462 // check if negative
2463 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2464 __ cmpw(src_pos, 0);
2465 __ br(Assembler::LT, *stub->entry());
2466 }
2467 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2468 __ cmpw(dst_pos, 0);
2469 __ br(Assembler::LT, *stub->entry());
2470 }
2471
2472 if (flags & LIR_OpArrayCopy::length_positive_check) {
2473 __ cmpw(length, 0);
2474 __ br(Assembler::LT, *stub->entry());
2475 }
2476
2477 if (flags & LIR_OpArrayCopy::src_range_check) {
2478 __ addw(tmp, src_pos, length);
2479 __ ldrw(rscratch1, src_length_addr);
2480 __ cmpw(tmp, rscratch1);
2481 __ br(Assembler::HI, *stub->entry());
2482 }
2483 if (flags & LIR_OpArrayCopy::dst_range_check) {
2484 __ addw(tmp, dst_pos, length);
2485 __ ldrw(rscratch1, dst_length_addr);
2486 __ cmpw(tmp, rscratch1);
2487 __ br(Assembler::HI, *stub->entry());
2488 }
2489
2490 if (flags & LIR_OpArrayCopy::type_check) {
2491 // We don't know the array types are compatible
2492 if (basic_type != T_OBJECT) {
2493 // Simple test for basic type arrays
2494 if (UseCompressedClassPointers) {
2495 __ ldrw(tmp, src_klass_addr);
2496 __ ldrw(rscratch1, dst_klass_addr);
2497 __ cmpw(tmp, rscratch1);
2498 } else {
2499 __ ldr(tmp, src_klass_addr);
2500 __ ldr(rscratch1, dst_klass_addr);
2501 __ cmp(tmp, rscratch1);
2502 }
2503 __ br(Assembler::NE, *stub->entry());
2504 } else {
2505 // For object arrays, if src is a sub class of dst then we can
2506 // safely do the copy.
2507 Label cont, slow;
2508
2509 #define PUSH(r1, r2) \
2510 stp(r1, r2, __ pre(sp, -2 * wordSize));
2511
2512 #define POP(r1, r2) \
2513 ldp(r1, r2, __ post(sp, 2 * wordSize));
2514
2515 __ PUSH(src, dst);
2516
2517 __ load_klass(src, src);
2518 __ load_klass(dst, dst);
2519
2520 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2521
2522 __ PUSH(src, dst);
2523 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
2524 __ POP(src, dst);
2525
2526 __ cbnz(src, cont);
2527
2528 __ bind(slow);
2529 __ POP(src, dst);
2530
2531 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2532 if (copyfunc_addr != nullptr) { // use stub if available
2533 // src is not a sub class of dst so we have to do a
2534 // per-element check.
2535
2536 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2537 if ((flags & mask) != mask) {
2538 // Check that at least both of them object arrays.
2539 assert(flags & mask, "one of the two should be known to be an object array");
2540
2541 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2542 __ load_klass(tmp, src);
2543 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2544 __ load_klass(tmp, dst);
2545 }
2546 int lh_offset = in_bytes(Klass::layout_helper_offset());
2547 Address klass_lh_addr(tmp, lh_offset);
2548 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2549 __ ldrw(rscratch1, klass_lh_addr);
2550 __ mov(rscratch2, objArray_lh);
2551 __ eorw(rscratch1, rscratch1, rscratch2);
2552 __ cbnzw(rscratch1, *stub->entry());
2553 }
2554
2555 // Spill because stubs can use any register they like and it's
2556 // easier to restore just those that we care about.
2557 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2558 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2559 __ str(src, Address(sp, 4*BytesPerWord));
2560
2561 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2562 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2563 assert_different_registers(c_rarg0, dst, dst_pos, length);
2564 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2565 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2566 assert_different_registers(c_rarg1, dst, length);
2567 __ uxtw(c_rarg2, length);
2568 assert_different_registers(c_rarg2, dst);
2569
2570 __ load_klass(c_rarg4, dst);
2571 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2572 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2573 __ far_call(RuntimeAddress(copyfunc_addr));
2574
2575 #ifndef PRODUCT
2576 if (PrintC1Statistics) {
2577 Label failed;
2578 __ cbnz(r0, failed);
2579 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2580 __ bind(failed);
2581 }
2582 #endif
2583
2584 __ cbz(r0, *stub->continuation());
2585
2586 #ifndef PRODUCT
2587 if (PrintC1Statistics) {
2588 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2589 }
2590 #endif
2591 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2592
2593 // Restore previously spilled arguments
2594 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2595 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2596 __ ldr(src, Address(sp, 4*BytesPerWord));
2597
2598 // return value is -1^K where K is partial copied count
2599 __ eonw(rscratch1, r0, zr);
2600 // adjust length down and src/end pos up by partial copied count
2601 __ subw(length, length, rscratch1);
2602 __ addw(src_pos, src_pos, rscratch1);
2603 __ addw(dst_pos, dst_pos, rscratch1);
2604 }
2605
2606 __ b(*stub->entry());
2607
2608 __ bind(cont);
2609 __ POP(src, dst);
2610 }
2611 }
2612
2613 #ifdef ASSERT
2614 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2615 // Sanity check the known type with the incoming class. For the
2616 // primitive case the types must match exactly with src.klass and
2617 // dst.klass each exactly matching the default type. For the
2618 // object array case, if no type check is needed then either the
2619 // dst type is exactly the expected type and the src type is a
2620 // subtype which we can't check or src is the same array as dst
2621 // but not necessarily exactly of type default_type.
2622 Label known_ok, halt;
2623 __ mov_metadata(tmp, default_type->constant_encoding());
2624 if (UseCompressedClassPointers) {
2625 __ encode_klass_not_null(tmp);
2626 }
2627
2628 if (basic_type != T_OBJECT) {
2629
2630 if (UseCompressedClassPointers) {
2631 __ ldrw(rscratch1, dst_klass_addr);
2632 __ cmpw(tmp, rscratch1);
2633 } else {
2634 __ ldr(rscratch1, dst_klass_addr);
2635 __ cmp(tmp, rscratch1);
2636 }
2637 __ br(Assembler::NE, halt);
2638 if (UseCompressedClassPointers) {
2639 __ ldrw(rscratch1, src_klass_addr);
2640 __ cmpw(tmp, rscratch1);
2641 } else {
2642 __ ldr(rscratch1, src_klass_addr);
2643 __ cmp(tmp, rscratch1);
2644 }
2645 __ br(Assembler::EQ, known_ok);
2646 } else {
2647 if (UseCompressedClassPointers) {
2648 __ ldrw(rscratch1, dst_klass_addr);
2649 __ cmpw(tmp, rscratch1);
2650 } else {
2651 __ ldr(rscratch1, dst_klass_addr);
2652 __ cmp(tmp, rscratch1);
2653 }
2654 __ br(Assembler::EQ, known_ok);
2655 __ cmp(src, dst);
2656 __ br(Assembler::EQ, known_ok);
2657 }
2658 __ bind(halt);
2659 __ stop("incorrect type information in arraycopy");
2660 __ bind(known_ok);
2661 }
2662 #endif
2663
2664 #ifndef PRODUCT
2665 if (PrintC1Statistics) {
2666 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2667 }
2668 #endif
2669
2670 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2671 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2672 assert_different_registers(c_rarg0, dst, dst_pos, length);
2673 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2674 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2675 assert_different_registers(c_rarg1, dst, length);
2676 __ uxtw(c_rarg2, length);
2677 assert_different_registers(c_rarg2, dst);
2678
2679 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2680 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2681 const char *name;
2682 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2683
2684 CodeBlob *cb = CodeCache::find_blob(entry);
2685 if (cb) {
2686 __ far_call(RuntimeAddress(entry));
2687 } else {
2688 __ call_VM_leaf(entry, 3);
2689 }
2690
2691 if (stub != nullptr) {
2692 __ bind(*stub->continuation());
2693 }
2694 }
2695
2696
2697
2698
2699 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2700 Register obj = op->obj_opr()->as_register(); // may not be an oop
2701 Register hdr = op->hdr_opr()->as_register();
2702 Register lock = op->lock_opr()->as_register();
2703 Register temp = op->scratch_opr()->as_register();
2704 if (LockingMode == LM_MONITOR) {
2705 if (op->info() != nullptr) {
2706 add_debug_info_for_null_check_here(op->info());
2707 __ null_check(obj, -1);
2708 }
2709 __ b(*op->stub()->entry());
2710 } else if (op->code() == lir_lock) {
2711 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2712 // add debug info for NullPointerException only if one is possible
2713 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2714 if (op->info() != nullptr) {
2715 add_debug_info_for_null_check(null_check_offset, op->info());
2716 }
2717 // done
2718 } else if (op->code() == lir_unlock) {
2719 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2720 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2721 } else {
2722 Unimplemented();
2723 }
2724 __ bind(*op->stub()->continuation());
2725 }
2726
2727 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2728 Register obj = op->obj()->as_pointer_register();
2729 Register result = op->result_opr()->as_pointer_register();
2730
2731 CodeEmitInfo* info = op->info();
2732 if (info != nullptr) {
2733 add_debug_info_for_null_check_here(info);
2734 }
2735
2736 if (UseCompressedClassPointers) {
2737 __ ldrw(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2738 __ decode_klass_not_null(result);
2739 } else {
2740 __ ldr(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2741 }
2742 }
2743
2744 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2745 ciMethod* method = op->profiled_method();
2746 int bci = op->profiled_bci();
2747 ciMethod* callee = op->profiled_callee();
2748
2749 // Update counter for all call types
2750 ciMethodData* md = method->method_data_or_null();
2751 assert(md != nullptr, "Sanity");
2752 ciProfileData* data = md->bci_to_data(bci);
2753 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2754 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2755 Register mdo = op->mdo()->as_register();
2756 __ mov_metadata(mdo, md->constant_encoding());
2757 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2758 // Perform additional virtual call profiling for invokevirtual and
2759 // invokeinterface bytecodes
2760 if (op->should_profile_receiver_type()) {
2761 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2762 Register recv = op->recv()->as_register();
2763 assert_different_registers(mdo, recv);
2764 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2765 ciKlass* known_klass = op->known_holder();
2766 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2767 // We know the type that will be seen at this call site; we can
2768 // statically update the MethodData* rather than needing to do
2769 // dynamic tests on the receiver type
2770
2771 // NOTE: we should probably put a lock around this search to
2772 // avoid collisions by concurrent compilations
2773 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2774 uint i;
2775 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2776 ciKlass* receiver = vc_data->receiver(i);
2777 if (known_klass->equals(receiver)) {
2778 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2779 __ addptr(data_addr, DataLayout::counter_increment);
2780 return;
2781 }
2782 }
2783
2784 // Receiver type not found in profile data; select an empty slot
2785
2786 // Note that this is less efficient than it should be because it
2787 // always does a write to the receiver part of the
2788 // VirtualCallData rather than just the first time
2789 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2790 ciKlass* receiver = vc_data->receiver(i);
2791 if (receiver == nullptr) {
2792 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2793 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2794 __ lea(rscratch2, recv_addr);
2795 __ str(rscratch1, Address(rscratch2));
2796 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2797 __ addptr(data_addr, DataLayout::counter_increment);
2798 return;
2799 }
2800 }
2801 } else {
2802 __ load_klass(recv, recv);
2803 Label update_done;
2804 type_profile_helper(mdo, md, data, recv, &update_done);
2805 // Receiver did not match any saved receiver and there is no empty row for it.
2806 // Increment total counter to indicate polymorphic case.
2807 __ addptr(counter_addr, DataLayout::counter_increment);
2808
2809 __ bind(update_done);
2810 }
2811 } else {
2812 // Static call
2813 __ addptr(counter_addr, DataLayout::counter_increment);
2814 }
2815 }
2816
2817
2818 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2819 Unimplemented();
2820 }
2821
2822
2823 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2824 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2825 }
2826
2827 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2828 assert(op->crc()->is_single_cpu(), "crc must be register");
2829 assert(op->val()->is_single_cpu(), "byte value must be register");
2830 assert(op->result_opr()->is_single_cpu(), "result must be register");
2831 Register crc = op->crc()->as_register();
2832 Register val = op->val()->as_register();
2833 Register res = op->result_opr()->as_register();
2834
2835 assert_different_registers(val, crc, res);
2836 uint64_t offset;
2837 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2838 __ add(res, res, offset);
2839
2840 __ mvnw(crc, crc); // ~crc
2841 __ update_byte_crc32(crc, val, res);
2842 __ mvnw(res, crc); // ~crc
2843 }
2844
2845 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2846 COMMENT("emit_profile_type {");
2847 Register obj = op->obj()->as_register();
2848 Register tmp = op->tmp()->as_pointer_register();
2849 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2850 ciKlass* exact_klass = op->exact_klass();
2851 intptr_t current_klass = op->current_klass();
2852 bool not_null = op->not_null();
2853 bool no_conflict = op->no_conflict();
2854
2855 Label update, next, none;
2856
2857 bool do_null = !not_null;
2858 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2859 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2860
2861 assert(do_null || do_update, "why are we here?");
2862 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2863 assert(mdo_addr.base() != rscratch1, "wrong register");
2864
2865 __ verify_oop(obj);
2866
2867 if (tmp != obj) {
2868 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2869 __ mov(tmp, obj);
2870 } else {
2871 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2872 }
2873 if (do_null) {
2874 __ cbnz(tmp, update);
2875 if (!TypeEntries::was_null_seen(current_klass)) {
2876 __ ldr(rscratch2, mdo_addr);
2877 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2878 __ str(rscratch2, mdo_addr);
2879 }
2880 if (do_update) {
2881 #ifndef ASSERT
2882 __ b(next);
2883 }
2884 #else
2885 __ b(next);
2886 }
2887 } else {
2888 __ cbnz(tmp, update);
2889 __ stop("unexpected null obj");
2890 #endif
2891 }
2892
2893 __ bind(update);
2894
2895 if (do_update) {
2896 #ifdef ASSERT
2897 if (exact_klass != nullptr) {
2898 Label ok;
2899 __ load_klass(tmp, tmp);
2900 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2901 __ eor(rscratch1, tmp, rscratch1);
2902 __ cbz(rscratch1, ok);
2903 __ stop("exact klass and actual klass differ");
2904 __ bind(ok);
2905 }
2906 #endif
2907 if (!no_conflict) {
2908 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2909 if (exact_klass != nullptr) {
2910 __ mov_metadata(tmp, exact_klass->constant_encoding());
2911 } else {
2912 __ load_klass(tmp, tmp);
2913 }
2914
2915 __ ldr(rscratch2, mdo_addr);
2916 __ eor(tmp, tmp, rscratch2);
2917 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2918 // klass seen before, nothing to do. The unknown bit may have been
2919 // set already but no need to check.
2920 __ cbz(rscratch1, next);
2921
2922 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2923
2924 if (TypeEntries::is_type_none(current_klass)) {
2925 __ cbz(rscratch2, none);
2926 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2927 __ br(Assembler::EQ, none);
2928 // There is a chance that the checks above
2929 // fail if another thread has just set the
2930 // profiling to this obj's klass
2931 __ dmb(Assembler::ISHLD);
2932 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2933 __ ldr(rscratch2, mdo_addr);
2934 __ eor(tmp, tmp, rscratch2);
2935 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2936 __ cbz(rscratch1, next);
2937 }
2938 } else {
2939 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2940 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2941
2942 __ ldr(tmp, mdo_addr);
2943 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2944 }
2945
2946 // different than before. Cannot keep accurate profile.
2947 __ ldr(rscratch2, mdo_addr);
2948 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2949 __ str(rscratch2, mdo_addr);
2950
2951 if (TypeEntries::is_type_none(current_klass)) {
2952 __ b(next);
2953
2954 __ bind(none);
2955 // first time here. Set profile type.
2956 __ str(tmp, mdo_addr);
2957 #ifdef ASSERT
2958 __ andr(tmp, tmp, TypeEntries::type_mask);
2959 __ verify_klass_ptr(tmp);
2960 #endif
2961 }
2962 } else {
2963 // There's a single possible klass at this profile point
2964 assert(exact_klass != nullptr, "should be");
2965 if (TypeEntries::is_type_none(current_klass)) {
2966 __ mov_metadata(tmp, exact_klass->constant_encoding());
2967 __ ldr(rscratch2, mdo_addr);
2968 __ eor(tmp, tmp, rscratch2);
2969 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2970 __ cbz(rscratch1, next);
2971 #ifdef ASSERT
2972 {
2973 Label ok;
2974 __ ldr(rscratch1, mdo_addr);
2975 __ cbz(rscratch1, ok);
2976 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2977 __ br(Assembler::EQ, ok);
2978 // may have been set by another thread
2979 __ dmb(Assembler::ISHLD);
2980 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2981 __ ldr(rscratch2, mdo_addr);
2982 __ eor(rscratch2, rscratch1, rscratch2);
2983 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2984 __ cbz(rscratch2, ok);
2985
2986 __ stop("unexpected profiling mismatch");
2987 __ bind(ok);
2988 }
2989 #endif
2990 // first time here. Set profile type.
2991 __ str(tmp, mdo_addr);
2992 #ifdef ASSERT
2993 __ andr(tmp, tmp, TypeEntries::type_mask);
2994 __ verify_klass_ptr(tmp);
2995 #endif
2996 } else {
2997 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2998 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2999
3000 __ ldr(tmp, mdo_addr);
3001 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
3002
3003 __ orr(tmp, tmp, TypeEntries::type_unknown);
3004 __ str(tmp, mdo_addr);
3005 // FIXME: Write barrier needed here?
3006 }
3007 }
3008
3009 __ bind(next);
3010 }
3011 COMMENT("} emit_profile_type");
3012 }
3013
3014 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3015 Register obj = op->obj()->as_register();
3016 Register tmp = op->tmp()->as_pointer_register();
3017 bool not_null = op->not_null();
3018 int flag = op->flag();
3019
3020 Label not_inline_type;
3021 if (!not_null) {
3022 __ cbz(obj, not_inline_type);
3023 }
3024
3025 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
3026
3027 Address mdo_addr = as_Address(op->mdp()->as_address_ptr(), rscratch2);
3028 __ ldrb(rscratch1, mdo_addr);
3029 __ orr(rscratch1, rscratch1, flag);
3030 __ strb(rscratch1, mdo_addr);
3031
3032 __ bind(not_inline_type);
3033 }
3034
3035 void LIR_Assembler::align_backward_branch_target() {
3036 }
3037
3038
3039 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3040 // tmp must be unused
3041 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3042
3043 if (left->is_single_cpu()) {
3044 assert(dest->is_single_cpu(), "expect single result reg");
3045 __ negw(dest->as_register(), left->as_register());
3046 } else if (left->is_double_cpu()) {
3047 assert(dest->is_double_cpu(), "expect double result reg");
3048 __ neg(dest->as_register_lo(), left->as_register_lo());
3049 } else if (left->is_single_fpu()) {
3050 assert(dest->is_single_fpu(), "expect single float result reg");
3051 __ fnegs(dest->as_float_reg(), left->as_float_reg());
3052 } else {
3053 assert(left->is_double_fpu(), "expect double float operand reg");
3054 assert(dest->is_double_fpu(), "expect double float result reg");
3055 __ fnegd(dest->as_double_reg(), left->as_double_reg());
3056 }
3057 }
3058
3059
3060 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3061 if (patch_code != lir_patch_none) {
3062 deoptimize_trap(info);
3063 return;
3064 }
3065
3066 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
3067 }
3068
3069
3070 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3071 assert(!tmp->is_valid(), "don't need temporary");
3072
3073 CodeBlob *cb = CodeCache::find_blob(dest);
3074 if (cb) {
3075 __ far_call(RuntimeAddress(dest));
3076 } else {
3077 __ mov(rscratch1, RuntimeAddress(dest));
3078 __ blr(rscratch1);
3079 }
3080
3081 if (info != nullptr) {
3082 add_call_info_here(info);
3083 }
3084 __ post_call_nop();
3085 }
3086
3087 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3088 if (dest->is_address() || src->is_address()) {
3089 move_op(src, dest, type, lir_patch_none, info,
3090 /*pop_fpu_stack*/false, /*wide*/false);
3091 } else {
3092 ShouldNotReachHere();
3093 }
3094 }
3095
3096 #ifdef ASSERT
3097 // emit run-time assertion
3098 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3099 assert(op->code() == lir_assert, "must be");
3100
3101 if (op->in_opr1()->is_valid()) {
3102 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3103 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3104 } else {
3105 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3106 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3107 }
3108
3109 Label ok;
3110 if (op->condition() != lir_cond_always) {
3111 Assembler::Condition acond = Assembler::AL;
3112 switch (op->condition()) {
3113 case lir_cond_equal: acond = Assembler::EQ; break;
3114 case lir_cond_notEqual: acond = Assembler::NE; break;
3115 case lir_cond_less: acond = Assembler::LT; break;
3116 case lir_cond_lessEqual: acond = Assembler::LE; break;
3117 case lir_cond_greaterEqual: acond = Assembler::GE; break;
3118 case lir_cond_greater: acond = Assembler::GT; break;
3119 case lir_cond_belowEqual: acond = Assembler::LS; break;
3120 case lir_cond_aboveEqual: acond = Assembler::HS; break;
3121 default: ShouldNotReachHere();
3122 }
3123 __ br(acond, ok);
3124 }
3125 if (op->halt()) {
3126 const char* str = __ code_string(op->msg());
3127 __ stop(str);
3128 } else {
3129 breakpoint();
3130 }
3131 __ bind(ok);
3132 }
3133 #endif
3134
3135 #ifndef PRODUCT
3136 #define COMMENT(x) do { __ block_comment(x); } while (0)
3137 #else
3138 #define COMMENT(x)
3139 #endif
3140
3141 void LIR_Assembler::membar() {
3142 COMMENT("membar");
3143 __ membar(MacroAssembler::AnyAny);
3144 }
3145
3146 void LIR_Assembler::membar_acquire() {
3147 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
3148 }
3149
3150 void LIR_Assembler::membar_release() {
3151 __ membar(Assembler::LoadStore|Assembler::StoreStore);
3152 }
3153
3154 void LIR_Assembler::membar_loadload() {
3155 __ membar(Assembler::LoadLoad);
3156 }
3157
3158 void LIR_Assembler::membar_storestore() {
3159 __ membar(MacroAssembler::StoreStore);
3160 }
3161
3162 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3163
3164 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3165
3166 void LIR_Assembler::on_spin_wait() {
3167 __ spin_wait();
3168 }
3169
3170 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3171 __ mov(result_reg->as_register(), rthread);
3172 }
3173
3174 void LIR_Assembler::check_orig_pc() {
3175 __ ldr(rscratch2, frame_map()->address_for_orig_pc_addr());
3176 __ cmp(rscratch2, (u1)NULL_WORD);
3177 }
3178
3179 void LIR_Assembler::peephole(LIR_List *lir) {
3180 #if 0
3181 if (tableswitch_count >= max_tableswitches)
3182 return;
3183
3184 /*
3185 This finite-state automaton recognizes sequences of compare-and-
3186 branch instructions. We will turn them into a tableswitch. You
3187 could argue that C1 really shouldn't be doing this sort of
3188 optimization, but without it the code is really horrible.
3189 */
3190
3191 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3192 int first_key, last_key = -2147483648;
3193 int next_key = 0;
3194 int start_insn = -1;
3195 int last_insn = -1;
3196 Register reg = noreg;
3197 LIR_Opr reg_opr;
3198 state = start_s;
3199
3200 LIR_OpList* inst = lir->instructions_list();
3201 for (int i = 0; i < inst->length(); i++) {
3202 LIR_Op* op = inst->at(i);
3203 switch (state) {
3204 case start_s:
3205 first_key = -1;
3206 start_insn = i;
3207 switch (op->code()) {
3208 case lir_cmp:
3209 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3210 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3211 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3212 && opr2->is_constant()
3213 && opr2->type() == T_INT) {
3214 reg_opr = opr1;
3215 reg = opr1->as_register();
3216 first_key = opr2->as_constant_ptr()->as_jint();
3217 next_key = first_key + 1;
3218 state = cmp_s;
3219 goto next_state;
3220 }
3221 break;
3222 }
3223 break;
3224 case cmp_s:
3225 switch (op->code()) {
3226 case lir_branch:
3227 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3228 state = beq_s;
3229 last_insn = i;
3230 goto next_state;
3231 }
3232 }
3233 state = start_s;
3234 break;
3235 case beq_s:
3236 switch (op->code()) {
3237 case lir_cmp: {
3238 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3239 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3240 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3241 && opr1->as_register() == reg
3242 && opr2->is_constant()
3243 && opr2->type() == T_INT
3244 && opr2->as_constant_ptr()->as_jint() == next_key) {
3245 last_key = next_key;
3246 next_key++;
3247 state = cmp_s;
3248 goto next_state;
3249 }
3250 }
3251 }
3252 last_key = next_key;
3253 state = start_s;
3254 break;
3255 default:
3256 assert(false, "impossible state");
3257 }
3258 if (state == start_s) {
3259 if (first_key < last_key - 5L && reg != noreg) {
3260 {
3261 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3262 // reg->encoding(),
3263 // start_insn, first_key, last_key);
3264 // for (int i = 0; i < inst->length(); i++) {
3265 // inst->at(i)->print();
3266 // tty->print("\n");
3267 // }
3268 // tty->print("\n");
3269 }
3270
3271 struct tableswitch *sw = &switches[tableswitch_count];
3272 sw->_insn_index = start_insn, sw->_first_key = first_key,
3273 sw->_last_key = last_key, sw->_reg = reg;
3274 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3275 {
3276 // Insert the new table of branches
3277 int offset = last_insn;
3278 for (int n = first_key; n < last_key; n++) {
3279 inst->insert_before
3280 (last_insn + 1,
3281 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3282 inst->at(offset)->as_OpBranch()->label()));
3283 offset -= 2, i++;
3284 }
3285 }
3286 // Delete all the old compare-and-branch instructions
3287 for (int n = first_key; n < last_key; n++) {
3288 inst->remove_at(start_insn);
3289 inst->remove_at(start_insn);
3290 }
3291 // Insert the tableswitch instruction
3292 inst->insert_before(start_insn,
3293 new LIR_Op2(lir_cmp, lir_cond_always,
3294 LIR_OprFact::intConst(tableswitch_count),
3295 reg_opr));
3296 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3297 tableswitch_count++;
3298 }
3299 reg = noreg;
3300 last_key = -2147483648;
3301 }
3302 next_state:
3303 ;
3304 }
3305 #endif
3306 }
3307
3308 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3309 Address addr = as_Address(src->as_address_ptr());
3310 BasicType type = src->type();
3311 bool is_oop = is_reference_type(type);
3312
3313 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3314 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3315
3316 switch(type) {
3317 case T_INT:
3318 xchg = &MacroAssembler::atomic_xchgalw;
3319 add = &MacroAssembler::atomic_addalw;
3320 break;
3321 case T_LONG:
3322 xchg = &MacroAssembler::atomic_xchgal;
3323 add = &MacroAssembler::atomic_addal;
3324 break;
3325 case T_OBJECT:
3326 case T_ARRAY:
3327 if (UseCompressedOops) {
3328 xchg = &MacroAssembler::atomic_xchgalw;
3329 add = &MacroAssembler::atomic_addalw;
3330 } else {
3331 xchg = &MacroAssembler::atomic_xchgal;
3332 add = &MacroAssembler::atomic_addal;
3333 }
3334 break;
3335 default:
3336 ShouldNotReachHere();
3337 xchg = &MacroAssembler::atomic_xchgal;
3338 add = &MacroAssembler::atomic_addal; // unreachable
3339 }
3340
3341 switch (code) {
3342 case lir_xadd:
3343 {
3344 RegisterOrConstant inc;
3345 Register tmp = as_reg(tmp_op);
3346 Register dst = as_reg(dest);
3347 if (data->is_constant()) {
3348 inc = RegisterOrConstant(as_long(data));
3349 assert_different_registers(dst, addr.base(), tmp,
3350 rscratch1, rscratch2);
3351 } else {
3352 inc = RegisterOrConstant(as_reg(data));
3353 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3354 rscratch1, rscratch2);
3355 }
3356 __ lea(tmp, addr);
3357 (_masm->*add)(dst, inc, tmp);
3358 break;
3359 }
3360 case lir_xchg:
3361 {
3362 Register tmp = tmp_op->as_register();
3363 Register obj = as_reg(data);
3364 Register dst = as_reg(dest);
3365 if (is_oop && UseCompressedOops) {
3366 __ encode_heap_oop(rscratch2, obj);
3367 obj = rscratch2;
3368 }
3369 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3370 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3371 __ lea(tmp, addr);
3372 (_masm->*xchg)(dst, obj, tmp);
3373 if (is_oop && UseCompressedOops) {
3374 __ decode_heap_oop(dst);
3375 }
3376 }
3377 break;
3378 default:
3379 ShouldNotReachHere();
3380 }
3381 __ membar(__ AnyAny);
3382 }
3383
3384 #undef __