1 /*
2 * Copyright (c) 2000, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * Copyright 2026 Arm Limited and/or its affiliates.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInlineKlass.hpp"
37 #include "ci/ciInstance.hpp"
38 #include "ci/ciObjArrayKlass.hpp"
39 #include "code/aotCodeCache.hpp"
40 #include "code/compiledIC.hpp"
41 #include "gc/shared/collectedHeap.hpp"
42 #include "gc/shared/gc_globals.hpp"
43 #include "nativeInst_aarch64.hpp"
44 #include "oops/objArrayKlass.hpp"
45 #include "oops/oop.inline.hpp"
46 #include "runtime/frame.inline.hpp"
47 #include "runtime/sharedRuntime.hpp"
48 #include "runtime/stubRoutines.hpp"
49 #include "runtime/threadIdentifier.hpp"
50 #include "utilities/powerOfTwo.hpp"
51 #include "vmreg_aarch64.inline.hpp"
52
53
54 #ifndef PRODUCT
55 #define COMMENT(x) do { __ block_comment(x); } while (0)
56 #else
57 #define COMMENT(x)
58 #endif
59
60 NEEDS_CLEANUP // remove this definitions ?
61 const Register SYNC_header = r0; // synchronization header
62 const Register SHIFT_count = r0; // where count for shift operations must be
63
64 #define __ _masm->
65
66
67 static void select_different_registers(Register preserve,
68 Register extra,
69 Register &tmp1,
70 Register &tmp2,
71 Register &tmp3) {
72 if (tmp1 == preserve) {
73 assert_different_registers(tmp1, tmp2, tmp3, extra);
74 tmp1 = extra;
75 } else if (tmp2 == preserve) {
76 assert_different_registers(tmp1, tmp2, tmp3, extra);
77 tmp2 = extra;
78 } else if (tmp3 == preserve) {
79 assert_different_registers(tmp1, tmp2, tmp3, extra);
80 tmp3 = extra;
81 }
82 assert_different_registers(preserve, tmp1, tmp2, tmp3);
83 }
84
85
86 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
87
88
89 LIR_Opr LIR_Assembler::receiverOpr() {
90 return FrameMap::receiver_opr;
91 }
92
93 LIR_Opr LIR_Assembler::osrBufferPointer() {
94 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
95 }
96
97 //--------------fpu register translations-----------------------
98
99
100 address LIR_Assembler::float_constant(float f) {
101 address const_addr = __ float_constant(f);
102 if (const_addr == nullptr) {
103 bailout("const section overflow");
104 return __ code()->consts()->start();
105 } else {
106 return const_addr;
107 }
108 }
109
110
111 address LIR_Assembler::double_constant(double d) {
112 address const_addr = __ double_constant(d);
113 if (const_addr == nullptr) {
114 bailout("const section overflow");
115 return __ code()->consts()->start();
116 } else {
117 return const_addr;
118 }
119 }
120
121 address LIR_Assembler::int_constant(jlong n) {
122 address const_addr = __ long_constant(n);
123 if (const_addr == nullptr) {
124 bailout("const section overflow");
125 return __ code()->consts()->start();
126 } else {
127 return const_addr;
128 }
129 }
130
131 void LIR_Assembler::breakpoint() { Unimplemented(); }
132
133 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
134
135 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
136
137 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
138 //-------------------------------------------
139
140 static Register as_reg(LIR_Opr op) {
141 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
142 }
143
144 static jlong as_long(LIR_Opr data) {
145 jlong result;
146 switch (data->type()) {
147 case T_INT:
148 result = (data->as_jint());
149 break;
150 case T_LONG:
151 result = (data->as_jlong());
152 break;
153 default:
154 ShouldNotReachHere();
155 result = 0; // unreachable
156 }
157 return result;
158 }
159
160 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
161 Register base = addr->base()->as_pointer_register();
162 LIR_Opr opr = addr->index();
163 if (opr->is_cpu_register()) {
164 Register index;
165 if (opr->is_single_cpu())
166 index = opr->as_register();
167 else
168 index = opr->as_register_lo();
169 assert(addr->disp() == 0, "must be");
170 switch(opr->type()) {
171 case T_INT:
172 return Address(base, index, Address::sxtw(addr->scale()));
173 case T_LONG:
174 return Address(base, index, Address::lsl(addr->scale()));
175 default:
176 ShouldNotReachHere();
177 }
178 } else {
179 assert(addr->scale() == 0,
180 "expected for immediate operand, was: %d", addr->scale());
181 ptrdiff_t offset = ptrdiff_t(addr->disp());
182 // NOTE: Does not handle any 16 byte vector access.
183 const uint type_size = type2aelembytes(addr->type(), true);
184 return __ legitimize_address(Address(base, offset), type_size, tmp);
185 }
186 return Address();
187 }
188
189 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
190 ShouldNotReachHere();
191 return Address();
192 }
193
194 Address LIR_Assembler::as_Address(LIR_Address* addr) {
195 return as_Address(addr, rscratch1);
196 }
197
198 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
199 return as_Address(addr, rscratch1); // Ouch
200 // FIXME: This needs to be much more clever. See x86.
201 }
202
203 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
204 // not encodable as a base + (immediate) offset, generate an explicit address
205 // calculation to hold the address in a temporary register.
206 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
207 precond(size == 4 || size == 8);
208 Address addr = frame_map()->address_for_slot(index, adjust);
209 precond(addr.getMode() == Address::base_plus_offset);
210 precond(addr.base() == sp);
211 precond(addr.offset() > 0);
212 uint mask = size - 1;
213 assert((addr.offset() & mask) == 0, "scaled offsets only");
214 return __ legitimize_address(addr, size, tmp);
215 }
216
217 void LIR_Assembler::osr_entry() {
218 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
219 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
220 ValueStack* entry_state = osr_entry->state();
221 int number_of_locks = entry_state->locks_size();
222
223 // we jump here if osr happens with the interpreter
224 // state set up to continue at the beginning of the
225 // loop that triggered osr - in particular, we have
226 // the following registers setup:
227 //
228 // r2: osr buffer
229 //
230
231 // build frame
232 ciMethod* m = compilation()->method();
233 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
234
235 // OSR buffer is
236 //
237 // locals[nlocals-1..0]
238 // monitors[0..number_of_locks]
239 //
240 // locals is a direct copy of the interpreter frame so in the osr buffer
241 // so first slot in the local array is the last local from the interpreter
242 // and last slot is local[0] (receiver) from the interpreter
243 //
244 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
245 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
246 // in the interpreter frame (the method lock if a sync method)
247
248 // Initialize monitors in the compiled activation.
249 // r2: pointer to osr buffer
250 //
251 // All other registers are dead at this point and the locals will be
252 // copied into place by code emitted in the IR.
253
254 Register OSR_buf = osrBufferPointer()->as_pointer_register();
255 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
256 int monitor_offset = BytesPerWord * method()->max_locals() +
257 (2 * BytesPerWord) * (number_of_locks - 1);
258 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
259 // the OSR buffer using 2 word entries: first the lock and then
260 // the oop.
261 for (int i = 0; i < number_of_locks; i++) {
262 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
263 #ifdef ASSERT
264 // verify the interpreter's monitor has a non-null object
265 {
266 Label L;
267 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
268 __ cbnz(rscratch1, L);
269 __ stop("locked object is null");
270 __ bind(L);
271 }
272 #endif
273 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
274 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
275 __ str(r19, frame_map()->address_for_monitor_lock(i));
276 __ str(r20, frame_map()->address_for_monitor_object(i));
277 }
278 }
279 }
280
281
282 // inline cache check; done before the frame is built.
283 int LIR_Assembler::check_icache() {
284 return __ ic_check(CodeEntryAlignment);
285 }
286
287 void LIR_Assembler::clinit_barrier(ciMethod* method) {
288 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
289 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
290
291 Label L_skip_barrier;
292
293 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
294 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
295 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
296 __ bind(L_skip_barrier);
297 }
298
299 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
300 if (o == nullptr) {
301 __ mov(reg, zr);
302 } else {
303 __ movoop(reg, o);
304 }
305 }
306
307 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
308 address target = nullptr;
309 relocInfo::relocType reloc_type = relocInfo::none;
310
311 switch (patching_id(info)) {
312 case PatchingStub::access_field_id:
313 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
314 reloc_type = relocInfo::section_word_type;
315 break;
316 case PatchingStub::load_klass_id:
317 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
318 reloc_type = relocInfo::metadata_type;
319 break;
320 case PatchingStub::load_mirror_id:
321 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
322 reloc_type = relocInfo::oop_type;
323 break;
324 case PatchingStub::load_appendix_id:
325 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
326 reloc_type = relocInfo::oop_type;
327 break;
328 default: ShouldNotReachHere();
329 }
330
331 __ far_call(RuntimeAddress(target));
332 add_call_info_here(info);
333 }
334
335 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
336 deoptimize_trap(info);
337 }
338
339
340 // This specifies the rsp decrement needed to build the frame
341 int LIR_Assembler::initial_frame_size_in_bytes() const {
342 // if rounding, must let FrameMap know!
343
344 return in_bytes(frame_map()->framesize_in_bytes());
345 }
346
347
348 int LIR_Assembler::emit_exception_handler() {
349 // generate code for exception handler
350 address handler_base = __ start_a_stub(exception_handler_size());
351 if (handler_base == nullptr) {
352 // not enough space left for the handler
353 bailout("exception handler overflow");
354 return -1;
355 }
356
357 int offset = code_offset();
358
359 // the exception oop and pc are in r0, and r3
360 // no other registers need to be preserved, so invalidate them
361 __ invalidate_registers(false, true, true, false, true, true);
362
363 // check that there is really an exception
364 __ verify_not_null_oop(r0);
365
366 // search an exception handler (r0: exception oop, r3: throwing pc)
367 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
368 __ should_not_reach_here();
369 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
370 __ end_a_stub();
371
372 return offset;
373 }
374
375
376 // Emit the code to remove the frame from the stack in the exception
377 // unwind path.
378 int LIR_Assembler::emit_unwind_handler() {
379 #ifndef PRODUCT
380 if (CommentedAssembly) {
381 _masm->block_comment("Unwind handler");
382 }
383 #endif
384
385 int offset = code_offset();
386
387 // Fetch the exception from TLS and clear out exception related thread state
388 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
389 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
390 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
391
392 __ bind(_unwind_handler_entry);
393 __ verify_not_null_oop(r0);
394 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
395 __ mov(r19, r0); // Preserve the exception
396 }
397
398 // Perform needed unlocking
399 MonitorExitStub* stub = nullptr;
400 if (method()->is_synchronized()) {
401 monitor_address(0, FrameMap::r0_opr);
402 stub = new MonitorExitStub(FrameMap::r0_opr, 0);
403 __ unlock_object(r5, r4, r0, r6, *stub->entry());
404 __ bind(*stub->continuation());
405 }
406
407 if (compilation()->env()->dtrace_method_probes()) {
408 __ mov(c_rarg0, rthread);
409 __ mov_metadata(c_rarg1, method()->constant_encoding());
410 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
411 }
412
413 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
414 __ mov(r0, r19); // Restore the exception
415 }
416
417 // remove the activation and dispatch to the unwind handler
418 __ block_comment("remove_frame and dispatch to the unwind handler");
419 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
420 __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
421
422 // Emit the slow path assembly
423 if (stub != nullptr) {
424 stub->emit_code(this);
425 }
426
427 return offset;
428 }
429
430
431 int LIR_Assembler::emit_deopt_handler() {
432 // generate code for exception handler
433 address handler_base = __ start_a_stub(deopt_handler_size());
434 if (handler_base == nullptr) {
435 // not enough space left for the handler
436 bailout("deopt handler overflow");
437 return -1;
438 }
439
440 int offset = code_offset();
441
442 Label start;
443 __ bind(start);
444
445 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
446
447 int entry_offset = __ offset();
448 __ b(start);
449
450 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
451 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
452 "out of bounds read in post-call NOP check");
453 __ end_a_stub();
454
455 return entry_offset;
456 }
457
458 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
459 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
460
461 if (InlineTypeReturnedAsFields) {
462 // Check if we are returning a non-null inline type and load its fields into registers
463 ciType* return_type = compilation()->method()->return_type();
464 if (return_type->is_inlinetype()) {
465 ciInlineKlass* vk = return_type->as_inline_klass();
466 if (vk->can_be_returned_as_fields()) {
467 address unpack_handler = vk->unpack_handler();
468 assert(unpack_handler != nullptr, "must be");
469 __ far_call(RuntimeAddress(unpack_handler));
470 }
471 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) {
472 Label skip;
473 Label not_null;
474 __ cbnz(r0, not_null);
475 // Returned value is null, zero all return registers because they may belong to oop fields
476 __ mov(j_rarg1, zr);
477 __ mov(j_rarg2, zr);
478 __ mov(j_rarg3, zr);
479 __ mov(j_rarg4, zr);
480 __ mov(j_rarg5, zr);
481 __ mov(j_rarg6, zr);
482 __ mov(j_rarg7, zr);
483 __ b(skip);
484 __ bind(not_null);
485
486 // Check if we are returning a non-null inline type and load its fields into registers
487 __ test_oop_is_not_inline_type(r0, rscratch2, skip, /* can_be_null= */ false);
488
489 // Load fields from a buffered value with an inline class specific handler
490 __ load_klass(rscratch1 /*dst*/, r0 /*src*/, rscratch2 /*tmp*/);
491 __ ldr(rscratch1, Address(rscratch1, InlineKlass::adr_members_offset()));
492 __ ldr(rscratch1, Address(rscratch1, InlineKlass::unpack_handler_offset()));
493 // Unpack handler can be null if inline type is not scalarizable in returns
494 __ cbz(rscratch1, skip);
495 __ blr(rscratch1);
496
497 __ bind(skip);
498 }
499 // At this point, r0 points to the value object (for interpreter or C1 caller).
500 // The fields of the object are copied into registers (for C2 caller).
501 }
502
503 // Pop the stack before the safepoint code
504 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
505
506 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
507 __ reserved_stack_check();
508 }
509
510 code_stub->set_safepoint_offset(__ offset());
511 __ relocate(relocInfo::poll_return_type);
512 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
513 __ ret(lr);
514 }
515
516 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
517 return (__ store_inline_type_fields_to_buf(vk, false));
518 }
519
520 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
521 guarantee(info != nullptr, "Shouldn't be null");
522 __ get_polling_page(rscratch1, relocInfo::poll_type);
523 add_debug_info_for_branch(info); // This isn't just debug info:
524 // it's the oop map
525 __ read_polling_page(rscratch1, relocInfo::poll_type);
526 return __ offset();
527 }
528
529
530 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
531 if (from_reg == r31_sp)
532 from_reg = sp;
533 if (to_reg == r31_sp)
534 to_reg = sp;
535 __ mov(to_reg, from_reg);
536 }
537
538 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
539
540
541 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
542 assert(src->is_constant(), "should not call otherwise");
543 assert(dest->is_register(), "should not call otherwise");
544 LIR_Const* c = src->as_constant_ptr();
545
546 switch (c->type()) {
547 case T_INT: {
548 assert(patch_code == lir_patch_none, "no patching handled here");
549 __ movw(dest->as_register(), c->as_jint());
550 break;
551 }
552
553 case T_ADDRESS: {
554 assert(patch_code == lir_patch_none, "no patching handled here");
555 __ mov(dest->as_register(), c->as_jint());
556 break;
557 }
558
559 case T_LONG: {
560 assert(patch_code == lir_patch_none, "no patching handled here");
561 #if INCLUDE_CDS
562 if (AOTCodeCache::is_on_for_dump()) {
563 address b = c->as_pointer();
564 if (b == (address)ThreadIdentifier::unsafe_offset()) {
565 __ lea(dest->as_register_lo(), ExternalAddress(b));
566 break;
567 }
568 if (AOTRuntimeConstants::contains(b)) {
569 __ load_aotrc_address(dest->as_register_lo(), b);
570 break;
571 }
572 }
573 #endif
574 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
575 break;
576 }
577
578 case T_OBJECT: {
579 if (patch_code != lir_patch_none) {
580 jobject2reg_with_patching(dest->as_register(), info);
581 } else {
582 jobject2reg(c->as_jobject(), dest->as_register());
583 }
584 break;
585 }
586
587 case T_METADATA: {
588 if (patch_code != lir_patch_none) {
589 klass2reg_with_patching(dest->as_register(), info);
590 } else {
591 __ mov_metadata(dest->as_register(), c->as_metadata());
592 }
593 break;
594 }
595
596 case T_FLOAT: {
597 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
598 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
599 } else {
600 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
601 __ ldrs(dest->as_float_reg(), Address(rscratch1));
602 }
603 break;
604 }
605
606 case T_DOUBLE: {
607 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
608 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
609 } else {
610 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
611 __ ldrd(dest->as_double_reg(), Address(rscratch1));
612 }
613 break;
614 }
615
616 default:
617 ShouldNotReachHere();
618 }
619 }
620
621 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
622 LIR_Const* c = src->as_constant_ptr();
623 switch (c->type()) {
624 case T_OBJECT:
625 {
626 if (! c->as_jobject())
627 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
628 else {
629 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
630 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
631 }
632 }
633 break;
634 case T_ADDRESS:
635 {
636 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
637 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
638 }
639 case T_INT:
640 case T_FLOAT:
641 {
642 Register reg = zr;
643 if (c->as_jint_bits() == 0)
644 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
645 else {
646 __ movw(rscratch1, c->as_jint_bits());
647 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
648 }
649 }
650 break;
651 case T_LONG:
652 case T_DOUBLE:
653 {
654 Register reg = zr;
655 if (c->as_jlong_bits() == 0)
656 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
657 lo_word_offset_in_bytes));
658 else {
659 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
660 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
661 lo_word_offset_in_bytes));
662 }
663 }
664 break;
665 default:
666 ShouldNotReachHere();
667 }
668 }
669
670 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
671 assert(src->is_constant(), "should not call otherwise");
672 LIR_Const* c = src->as_constant_ptr();
673 LIR_Address* to_addr = dest->as_address_ptr();
674
675 void (Assembler::* insn)(Register Rt, const Address &adr);
676
677 switch (type) {
678 case T_ADDRESS:
679 assert(c->as_jint() == 0, "should be");
680 insn = &Assembler::str;
681 break;
682 case T_LONG:
683 assert(c->as_jlong() == 0, "should be");
684 insn = &Assembler::str;
685 break;
686 case T_INT:
687 assert(c->as_jint() == 0, "should be");
688 insn = &Assembler::strw;
689 break;
690 case T_OBJECT:
691 case T_ARRAY:
692 assert(c->as_jobject() == nullptr, "should be");
693 if (UseCompressedOops && !wide) {
694 insn = &Assembler::strw;
695 } else {
696 insn = &Assembler::str;
697 }
698 break;
699 case T_CHAR:
700 case T_SHORT:
701 assert(c->as_jint() == 0, "should be");
702 insn = &Assembler::strh;
703 break;
704 case T_BOOLEAN:
705 case T_BYTE:
706 assert(c->as_jint() == 0, "should be");
707 insn = &Assembler::strb;
708 break;
709 default:
710 ShouldNotReachHere();
711 insn = &Assembler::str; // unreachable
712 }
713
714 if (info) add_debug_info_for_null_check_here(info);
715 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
716 }
717
718 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
719 assert(src->is_register(), "should not call otherwise");
720 assert(dest->is_register(), "should not call otherwise");
721
722 // move between cpu-registers
723 if (dest->is_single_cpu()) {
724 if (src->type() == T_LONG) {
725 // Can do LONG -> OBJECT
726 move_regs(src->as_register_lo(), dest->as_register());
727 return;
728 }
729 assert(src->is_single_cpu(), "must match");
730 if (src->type() == T_OBJECT) {
731 __ verify_oop(src->as_register());
732 }
733 move_regs(src->as_register(), dest->as_register());
734
735 } else if (dest->is_double_cpu()) {
736 if (is_reference_type(src->type())) {
737 // Surprising to me but we can see move of a long to t_object
738 __ verify_oop(src->as_register());
739 move_regs(src->as_register(), dest->as_register_lo());
740 return;
741 }
742 assert(src->is_double_cpu(), "must match");
743 Register f_lo = src->as_register_lo();
744 Register f_hi = src->as_register_hi();
745 Register t_lo = dest->as_register_lo();
746 Register t_hi = dest->as_register_hi();
747 assert(f_hi == f_lo, "must be same");
748 assert(t_hi == t_lo, "must be same");
749 move_regs(f_lo, t_lo);
750
751 } else if (dest->is_single_fpu()) {
752 __ fmovs(dest->as_float_reg(), src->as_float_reg());
753
754 } else if (dest->is_double_fpu()) {
755 __ fmovd(dest->as_double_reg(), src->as_double_reg());
756
757 } else {
758 ShouldNotReachHere();
759 }
760 }
761
762 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
763 precond(src->is_register() && dest->is_stack());
764
765 uint const c_sz32 = sizeof(uint32_t);
766 uint const c_sz64 = sizeof(uint64_t);
767
768 if (src->is_single_cpu()) {
769 int index = dest->single_stack_ix();
770 if (is_reference_type(type)) {
771 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
772 __ verify_oop(src->as_register());
773 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
774 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
775 } else {
776 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
777 }
778
779 } else if (src->is_double_cpu()) {
780 int index = dest->double_stack_ix();
781 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
782 __ str(src->as_register_lo(), dest_addr_LO);
783
784 } else if (src->is_single_fpu()) {
785 int index = dest->single_stack_ix();
786 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
787
788 } else if (src->is_double_fpu()) {
789 int index = dest->double_stack_ix();
790 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
791
792 } else {
793 ShouldNotReachHere();
794 }
795 }
796
797
798 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
799 LIR_Address* to_addr = dest->as_address_ptr();
800 PatchingStub* patch = nullptr;
801 Register compressed_src = rscratch1;
802
803 if (patch_code != lir_patch_none) {
804 deoptimize_trap(info);
805 return;
806 }
807
808 if (is_reference_type(type)) {
809 __ verify_oop(src->as_register());
810
811 if (UseCompressedOops && !wide) {
812 __ encode_heap_oop(compressed_src, src->as_register());
813 } else {
814 compressed_src = src->as_register();
815 }
816 }
817
818 int null_check_here = code_offset();
819 switch (type) {
820 case T_FLOAT: {
821 __ strs(src->as_float_reg(), as_Address(to_addr));
822 break;
823 }
824
825 case T_DOUBLE: {
826 __ strd(src->as_double_reg(), as_Address(to_addr));
827 break;
828 }
829
830 case T_ARRAY: // fall through
831 case T_OBJECT: // fall through
832 if (UseCompressedOops && !wide) {
833 __ strw(compressed_src, as_Address(to_addr, rscratch2));
834 } else {
835 __ str(compressed_src, as_Address(to_addr));
836 }
837 break;
838 case T_METADATA:
839 // We get here to store a method pointer to the stack to pass to
840 // a dtrace runtime call. This can't work on 64 bit with
841 // compressed klass ptrs: T_METADATA can be a compressed klass
842 // ptr or a 64 bit method pointer.
843 ShouldNotReachHere();
844 __ str(src->as_register(), as_Address(to_addr));
845 break;
846 case T_ADDRESS:
847 __ str(src->as_register(), as_Address(to_addr));
848 break;
849 case T_INT:
850 __ strw(src->as_register(), as_Address(to_addr));
851 break;
852
853 case T_LONG: {
854 __ str(src->as_register_lo(), as_Address_lo(to_addr));
855 break;
856 }
857
858 case T_BYTE: // fall through
859 case T_BOOLEAN: {
860 __ strb(src->as_register(), as_Address(to_addr));
861 break;
862 }
863
864 case T_CHAR: // fall through
865 case T_SHORT:
866 __ strh(src->as_register(), as_Address(to_addr));
867 break;
868
869 default:
870 ShouldNotReachHere();
871 }
872 if (info != nullptr) {
873 add_debug_info_for_null_check(null_check_here, info);
874 }
875 }
876
877
878 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
879 precond(src->is_stack() && dest->is_register());
880
881 uint const c_sz32 = sizeof(uint32_t);
882 uint const c_sz64 = sizeof(uint64_t);
883
884 if (dest->is_single_cpu()) {
885 int index = src->single_stack_ix();
886 if (is_reference_type(type)) {
887 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
888 __ verify_oop(dest->as_register());
889 } else if (type == T_METADATA || type == T_ADDRESS) {
890 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
891 } else {
892 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
893 }
894
895 } else if (dest->is_double_cpu()) {
896 int index = src->double_stack_ix();
897 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
898 __ ldr(dest->as_register_lo(), src_addr_LO);
899
900 } else if (dest->is_single_fpu()) {
901 int index = src->single_stack_ix();
902 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
903
904 } else if (dest->is_double_fpu()) {
905 int index = src->double_stack_ix();
906 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
907
908 } else {
909 ShouldNotReachHere();
910 }
911 }
912
913
914 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
915 address target = nullptr;
916 relocInfo::relocType reloc_type = relocInfo::none;
917
918 switch (patching_id(info)) {
919 case PatchingStub::access_field_id:
920 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
921 reloc_type = relocInfo::section_word_type;
922 break;
923 case PatchingStub::load_klass_id:
924 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
925 reloc_type = relocInfo::metadata_type;
926 break;
927 case PatchingStub::load_mirror_id:
928 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
929 reloc_type = relocInfo::oop_type;
930 break;
931 case PatchingStub::load_appendix_id:
932 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
933 reloc_type = relocInfo::oop_type;
934 break;
935 default: ShouldNotReachHere();
936 }
937
938 __ far_call(RuntimeAddress(target));
939 add_call_info_here(info);
940 }
941
942 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
943
944 LIR_Opr temp;
945 if (type == T_LONG || type == T_DOUBLE)
946 temp = FrameMap::rscratch1_long_opr;
947 else
948 temp = FrameMap::rscratch1_opr;
949
950 stack2reg(src, temp, src->type());
951 reg2stack(temp, dest, dest->type());
952 }
953
954 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
955 LIR_PatchCode patch_code, CodeEmitInfo* info,
956 bool wide) {
957 mem2reg(src, dest, type, patch_code, info, wide, false);
958 }
959
960 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
961 LIR_PatchCode patch_code, CodeEmitInfo* info,
962 bool wide, bool is_volatile) {
963 LIR_Address* addr = src->as_address_ptr();
964 LIR_Address* from_addr = src->as_address_ptr();
965
966 if (addr->base()->type() == T_OBJECT) {
967 __ verify_oop(addr->base()->as_pointer_register());
968 }
969
970 if (patch_code != lir_patch_none) {
971 deoptimize_trap(info);
972 return;
973 }
974
975 if (is_volatile) {
976 load_volatile(from_addr, dest, type, info);
977 } else {
978 load_unordered(from_addr, dest, type, wide, info);
979 }
980
981 if (is_reference_type(type)) {
982 if (UseCompressedOops && !wide) {
983 __ decode_heap_oop(dest->as_register());
984 }
985
986 __ verify_oop(dest->as_register());
987 }
988 }
989
990 void LIR_Assembler::load_unordered(LIR_Address *from_addr, LIR_Opr dest,
991 BasicType type, bool wide, CodeEmitInfo* info) {
992 if (info != nullptr) {
993 add_debug_info_for_null_check_here(info);
994 }
995
996 switch (type) {
997 case T_FLOAT: {
998 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
999 break;
1000 }
1001
1002 case T_DOUBLE: {
1003 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
1004 break;
1005 }
1006
1007 case T_ARRAY: // fall through
1008 case T_OBJECT: // fall through
1009 if (UseCompressedOops && !wide) {
1010 __ ldrw(dest->as_register(), as_Address(from_addr));
1011 } else {
1012 __ ldr(dest->as_register(), as_Address(from_addr));
1013 }
1014 break;
1015 case T_METADATA:
1016 // We get here to store a method pointer to the stack to pass to
1017 // a dtrace runtime call. This can't work on 64 bit with
1018 // compressed klass ptrs: T_METADATA can be a compressed klass
1019 // ptr or a 64 bit method pointer.
1020 ShouldNotReachHere();
1021 __ ldr(dest->as_register(), as_Address(from_addr));
1022 break;
1023 case T_ADDRESS:
1024 __ ldr(dest->as_register(), as_Address(from_addr));
1025 break;
1026 case T_INT:
1027 __ ldrw(dest->as_register(), as_Address(from_addr));
1028 break;
1029
1030 case T_LONG: {
1031 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1032 break;
1033 }
1034
1035 case T_BYTE:
1036 __ ldrsb(dest->as_register(), as_Address(from_addr));
1037 break;
1038 case T_BOOLEAN: {
1039 __ ldrb(dest->as_register(), as_Address(from_addr));
1040 break;
1041 }
1042
1043 case T_CHAR:
1044 __ ldrh(dest->as_register(), as_Address(from_addr));
1045 break;
1046 case T_SHORT:
1047 __ ldrsh(dest->as_register(), as_Address(from_addr));
1048 break;
1049
1050 default:
1051 ShouldNotReachHere();
1052 }
1053 }
1054
1055 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
1056 assert(dst->is_cpu_register(), "must be");
1057 assert(dst->type() == src->type(), "must be");
1058
1059 if (src->is_cpu_register()) {
1060 reg2reg(src, dst);
1061 } else if (src->is_stack()) {
1062 stack2reg(src, dst, dst->type());
1063 } else if (src->is_constant()) {
1064 const2reg(src, dst, lir_patch_none, nullptr);
1065 } else {
1066 ShouldNotReachHere();
1067 }
1068 }
1069
1070 void LIR_Assembler::load_volatile(LIR_Address *from_addr, LIR_Opr dest,
1071 BasicType type, CodeEmitInfo* info) {
1072 __ lea(rscratch1, as_Address(from_addr));
1073
1074 Register dest_reg = rscratch2;
1075 if (!is_floating_point_type(type)) {
1076 dest_reg = (dest->is_single_cpu()
1077 ? dest->as_register() : dest->as_register_lo());
1078 }
1079
1080 if (info != nullptr) {
1081 add_debug_info_for_null_check_here(info);
1082 }
1083
1084 // Uses LDAR to ensure memory ordering.
1085 __ load_store_volatile(dest_reg, type, rscratch1, /*is_load*/true);
1086
1087 switch (type) {
1088 // LDAR is unsigned so need to sign-extend for byte and short
1089 case T_BYTE:
1090 __ sxtb(dest_reg, dest_reg);
1091 break;
1092 case T_SHORT:
1093 __ sxth(dest_reg, dest_reg);
1094 break;
1095 // need to move from GPR to FPR after LDAR with FMOV for floating types
1096 case T_FLOAT:
1097 __ fmovs(dest->as_float_reg(), dest_reg);
1098 break;
1099 case T_DOUBLE:
1100 __ fmovd(dest->as_double_reg(), dest_reg);
1101 break;
1102 default:
1103 break;
1104 }
1105 }
1106
1107 int LIR_Assembler::array_element_size(BasicType type) const {
1108 int elem_size = type2aelembytes(type);
1109 return exact_log2(elem_size);
1110 }
1111
1112
1113 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1114 switch (op->code()) {
1115 case lir_idiv:
1116 case lir_irem:
1117 arithmetic_idiv(op->code(),
1118 op->in_opr1(),
1119 op->in_opr2(),
1120 op->in_opr3(),
1121 op->result_opr(),
1122 op->info());
1123 break;
1124 case lir_fmad:
1125 __ fmaddd(op->result_opr()->as_double_reg(),
1126 op->in_opr1()->as_double_reg(),
1127 op->in_opr2()->as_double_reg(),
1128 op->in_opr3()->as_double_reg());
1129 break;
1130 case lir_fmaf:
1131 __ fmadds(op->result_opr()->as_float_reg(),
1132 op->in_opr1()->as_float_reg(),
1133 op->in_opr2()->as_float_reg(),
1134 op->in_opr3()->as_float_reg());
1135 break;
1136 default: ShouldNotReachHere(); break;
1137 }
1138 }
1139
1140 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1141 #ifdef ASSERT
1142 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1143 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1144 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1145 #endif
1146
1147 if (op->cond() == lir_cond_always) {
1148 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1149 __ b(*(op->label()));
1150 } else {
1151 Assembler::Condition acond;
1152 if (op->code() == lir_cond_float_branch) {
1153 bool is_unordered = (op->ublock() == op->block());
1154 // Assembler::EQ does not permit unordered branches, so we add
1155 // another branch here. Likewise, Assembler::NE does not permit
1156 // ordered branches.
1157 if ((is_unordered && op->cond() == lir_cond_equal)
1158 || (!is_unordered && op->cond() == lir_cond_notEqual))
1159 __ br(Assembler::VS, *(op->ublock()->label()));
1160 switch(op->cond()) {
1161 case lir_cond_equal: acond = Assembler::EQ; break;
1162 case lir_cond_notEqual: acond = Assembler::NE; break;
1163 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1164 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1165 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1166 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1167 default: ShouldNotReachHere();
1168 acond = Assembler::EQ; // unreachable
1169 }
1170 } else {
1171 switch (op->cond()) {
1172 case lir_cond_equal: acond = Assembler::EQ; break;
1173 case lir_cond_notEqual: acond = Assembler::NE; break;
1174 case lir_cond_less: acond = Assembler::LT; break;
1175 case lir_cond_lessEqual: acond = Assembler::LE; break;
1176 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1177 case lir_cond_greater: acond = Assembler::GT; break;
1178 case lir_cond_belowEqual: acond = Assembler::LS; break;
1179 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1180 default: ShouldNotReachHere();
1181 acond = Assembler::EQ; // unreachable
1182 }
1183 }
1184 __ br(acond,*(op->label()));
1185 }
1186 }
1187
1188
1189
1190 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1191 LIR_Opr src = op->in_opr();
1192 LIR_Opr dest = op->result_opr();
1193
1194 switch (op->bytecode()) {
1195 case Bytecodes::_i2f:
1196 {
1197 __ scvtfws(dest->as_float_reg(), src->as_register());
1198 break;
1199 }
1200 case Bytecodes::_i2d:
1201 {
1202 __ scvtfwd(dest->as_double_reg(), src->as_register());
1203 break;
1204 }
1205 case Bytecodes::_l2d:
1206 {
1207 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1208 break;
1209 }
1210 case Bytecodes::_l2f:
1211 {
1212 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1213 break;
1214 }
1215 case Bytecodes::_f2d:
1216 {
1217 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1218 break;
1219 }
1220 case Bytecodes::_d2f:
1221 {
1222 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1223 break;
1224 }
1225 case Bytecodes::_i2c:
1226 {
1227 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1228 break;
1229 }
1230 case Bytecodes::_i2l:
1231 {
1232 __ sxtw(dest->as_register_lo(), src->as_register());
1233 break;
1234 }
1235 case Bytecodes::_i2s:
1236 {
1237 __ sxth(dest->as_register(), src->as_register());
1238 break;
1239 }
1240 case Bytecodes::_i2b:
1241 {
1242 __ sxtb(dest->as_register(), src->as_register());
1243 break;
1244 }
1245 case Bytecodes::_l2i:
1246 {
1247 _masm->block_comment("FIXME: This could be a no-op");
1248 __ uxtw(dest->as_register(), src->as_register_lo());
1249 break;
1250 }
1251 case Bytecodes::_d2l:
1252 {
1253 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1254 break;
1255 }
1256 case Bytecodes::_f2i:
1257 {
1258 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1259 break;
1260 }
1261 case Bytecodes::_f2l:
1262 {
1263 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1264 break;
1265 }
1266 case Bytecodes::_d2i:
1267 {
1268 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1269 break;
1270 }
1271 default: ShouldNotReachHere();
1272 }
1273 }
1274
1275 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1276 if (op->init_check()) {
1277 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1278 __ ldarb(rscratch1, rscratch1);
1279 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1280 add_debug_info_for_null_check_here(op->stub()->info());
1281 __ br(Assembler::NE, *op->stub()->entry());
1282 }
1283 __ allocate_object(op->obj()->as_register(),
1284 op->tmp1()->as_register(),
1285 op->tmp2()->as_register(),
1286 op->header_size(),
1287 op->object_size(),
1288 op->klass()->as_register(),
1289 *op->stub()->entry());
1290 __ bind(*op->stub()->continuation());
1291 }
1292
1293 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1294 Register len = op->len()->as_register();
1295 __ uxtw(len, len);
1296
1297 if (UseSlowPath || op->always_slow_path() ||
1298 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1299 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1300 __ b(*op->stub()->entry());
1301 } else {
1302 Register tmp1 = op->tmp1()->as_register();
1303 Register tmp2 = op->tmp2()->as_register();
1304 Register tmp3 = op->tmp3()->as_register();
1305 if (len == tmp1) {
1306 tmp1 = tmp3;
1307 } else if (len == tmp2) {
1308 tmp2 = tmp3;
1309 } else if (len == tmp3) {
1310 // everything is ok
1311 } else {
1312 __ mov(tmp3, len);
1313 }
1314 __ allocate_array(op->obj()->as_register(),
1315 len,
1316 tmp1,
1317 tmp2,
1318 arrayOopDesc::base_offset_in_bytes(op->type()),
1319 array_element_size(op->type()),
1320 op->klass()->as_register(),
1321 *op->stub()->entry(),
1322 op->zero_array());
1323 }
1324 __ bind(*op->stub()->continuation());
1325 }
1326
1327 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md,
1328 ciProfileData *data, Register recv) {
1329
1330 int mdp_offset = md->byte_offset_of_slot(data, in_ByteSize(0));
1331 __ profile_receiver_type(recv, mdo, mdp_offset);
1332 }
1333
1334 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1335 // we always need a stub for the failure case.
1336 CodeStub* stub = op->stub();
1337 Register obj = op->object()->as_register();
1338 Register k_RInfo = op->tmp1()->as_register();
1339 Register klass_RInfo = op->tmp2()->as_register();
1340 Register dst = op->result_opr()->as_register();
1341 ciKlass* k = op->klass();
1342 Register Rtmp1 = noreg;
1343
1344 // check if it needs to be profiled
1345 ciMethodData* md;
1346 ciProfileData* data;
1347
1348 const bool should_profile = op->should_profile();
1349
1350 if (should_profile) {
1351 ciMethod* method = op->profiled_method();
1352 assert(method != nullptr, "Should have method");
1353 int bci = op->profiled_bci();
1354 md = method->method_data_or_null();
1355 assert(md != nullptr, "Sanity");
1356 data = md->bci_to_data(bci);
1357 assert(data != nullptr, "need data for type check");
1358 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1359 }
1360 Label* success_target = success;
1361 Label* failure_target = failure;
1362
1363 if (obj == k_RInfo) {
1364 k_RInfo = dst;
1365 } else if (obj == klass_RInfo) {
1366 klass_RInfo = dst;
1367 }
1368
1369 Rtmp1 = op->tmp3()->as_register();
1370 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1371
1372 assert_different_registers(obj, k_RInfo, klass_RInfo);
1373
1374 if (op->need_null_check()) {
1375 if (should_profile) {
1376 Register mdo = klass_RInfo;
1377 __ mov_metadata(mdo, md->constant_encoding());
1378 Label not_null;
1379 __ cbnz(obj, not_null);
1380 // Object is null; update MDO and exit
1381 Address data_addr
1382 = __ form_address(rscratch2, mdo,
1383 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1384 0);
1385 __ ldrb(rscratch1, data_addr);
1386 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1387 __ strb(rscratch1, data_addr);
1388 __ b(*obj_is_null);
1389 __ bind(not_null);
1390
1391 Register recv = k_RInfo;
1392 __ load_klass(recv, obj, rscratch1);
1393 type_profile_helper(mdo, md, data, recv);
1394 } else {
1395 __ cbz(obj, *obj_is_null);
1396 }
1397 }
1398
1399 if (!k->is_loaded()) {
1400 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1401 } else {
1402 __ mov_metadata(k_RInfo, k->constant_encoding());
1403 }
1404 __ verify_oop(obj);
1405
1406 if (op->fast_check()) {
1407 assert(!k->is_loaded() || !k->is_obj_array_klass(), "Use refined array for a direct pointer comparison");
1408 // get object class
1409 // not a safepoint as obj null check happens earlier
1410 __ load_klass(rscratch2, obj, rscratch1);
1411 __ cmp( rscratch2, k_RInfo);
1412
1413 __ br(Assembler::NE, *failure_target);
1414 // successful cast, fall through to profile or jump
1415 } else {
1416 // get object class
1417 // not a safepoint as obj null check happens earlier
1418 __ load_klass(klass_RInfo, obj, rscratch1);
1419 if (k->is_loaded()) {
1420 // See if we get an immediate positive hit
1421 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1422 __ cmp(k_RInfo, rscratch1);
1423 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1424 __ br(Assembler::NE, *failure_target);
1425 // successful cast, fall through to profile or jump
1426 } else {
1427 // See if we get an immediate positive hit
1428 __ br(Assembler::EQ, *success_target);
1429 // check for self
1430 if (k->is_loaded() && k->is_obj_array_klass()) {
1431 // For a direct pointer comparison, we need the refined array klass pointer
1432 ciKlass* k_refined = ciObjArrayKlass::make(k->as_obj_array_klass()->element_klass());
1433 if (!k_refined->is_loaded()) {
1434 bailout("encountered unloaded_ciobjarrayklass due to out of memory error");
1435 return;
1436 }
1437 __ mov_metadata(rscratch1, k_refined->constant_encoding());
1438 __ cmp(klass_RInfo, rscratch1);
1439 } else {
1440 __ cmp(klass_RInfo, k_RInfo);
1441 }
1442 __ br(Assembler::EQ, *success_target);
1443
1444 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1445 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1446 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1447 // result is a boolean
1448 __ cbzw(klass_RInfo, *failure_target);
1449 // successful cast, fall through to profile or jump
1450 }
1451 } else {
1452 // perform the fast part of the checking logic
1453 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1454 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1455 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1456 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1457 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1458 // result is a boolean
1459 __ cbz(k_RInfo, *failure_target);
1460 // successful cast, fall through to profile or jump
1461 }
1462 }
1463 __ b(*success);
1464 }
1465
1466
1467 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1468 const bool should_profile = op->should_profile();
1469
1470 LIR_Code code = op->code();
1471 if (code == lir_store_check) {
1472 Register value = op->object()->as_register();
1473 Register array = op->array()->as_register();
1474 Register k_RInfo = op->tmp1()->as_register();
1475 Register klass_RInfo = op->tmp2()->as_register();
1476 Register Rtmp1 = op->tmp3()->as_register();
1477
1478 CodeStub* stub = op->stub();
1479
1480 // check if it needs to be profiled
1481 ciMethodData* md;
1482 ciProfileData* data;
1483
1484 if (should_profile) {
1485 ciMethod* method = op->profiled_method();
1486 assert(method != nullptr, "Should have method");
1487 int bci = op->profiled_bci();
1488 md = method->method_data_or_null();
1489 assert(md != nullptr, "Sanity");
1490 data = md->bci_to_data(bci);
1491 assert(data != nullptr, "need data for type check");
1492 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1493 }
1494 Label done;
1495 Label* success_target = &done;
1496 Label* failure_target = stub->entry();
1497
1498 if (should_profile) {
1499 Label not_null;
1500 Register mdo = klass_RInfo;
1501 __ mov_metadata(mdo, md->constant_encoding());
1502 __ cbnz(value, not_null);
1503 // Object is null; update MDO and exit
1504 Address data_addr
1505 = __ form_address(rscratch2, mdo,
1506 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1507 __ ldrb(rscratch1, data_addr);
1508 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1509 __ strb(rscratch1, data_addr);
1510 __ b(done);
1511 __ bind(not_null);
1512
1513 Register recv = k_RInfo;
1514 __ load_klass(recv, value, rscratch1);
1515 type_profile_helper(mdo, md, data, recv);
1516 } else {
1517 __ cbz(value, done);
1518 }
1519
1520 add_debug_info_for_null_check_here(op->info_for_exception());
1521 __ load_klass(k_RInfo, array, rscratch1);
1522 __ load_klass(klass_RInfo, value, rscratch1);
1523
1524 // get instance klass (it's already uncompressed)
1525 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1526 // perform the fast part of the checking logic
1527 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1528 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1529 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1530 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1531 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1532 // result is a boolean
1533 __ cbzw(k_RInfo, *failure_target);
1534 // fall through to the success case
1535
1536 __ bind(done);
1537 } else if (code == lir_checkcast) {
1538 Register obj = op->object()->as_register();
1539 Register dst = op->result_opr()->as_register();
1540 Label success;
1541 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1542 __ bind(success);
1543 if (dst != obj) {
1544 __ mov(dst, obj);
1545 }
1546 } else if (code == lir_instanceof) {
1547 Register obj = op->object()->as_register();
1548 Register dst = op->result_opr()->as_register();
1549 Label success, failure, done;
1550 emit_typecheck_helper(op, &success, &failure, &failure);
1551 __ bind(failure);
1552 __ mov(dst, zr);
1553 __ b(done);
1554 __ bind(success);
1555 __ mov(dst, 1);
1556 __ bind(done);
1557 } else {
1558 ShouldNotReachHere();
1559 }
1560 }
1561
1562 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1563 // We are loading/storing from/to an array that *may* be a flat array (the
1564 // declared type is Object[], abstract[], interface[] or VT.ref[]).
1565 // If this array is a flat array, take the slow path.
1566 __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1567 }
1568
1569 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1570 // We are storing into an array that *may* be null-free (the declared type is
1571 // Object[], abstract[], interface[] or VT.ref[]).
1572 Label test_mark_word;
1573 Register tmp = op->tmp()->as_register();
1574 __ ldr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
1575 __ tst(tmp, markWord::unlocked_value);
1576 __ br(Assembler::NE, test_mark_word);
1577 __ load_prototype_header(tmp, op->array()->as_register());
1578 __ bind(test_mark_word);
1579 __ tst(tmp, markWord::null_free_array_bit_in_place);
1580 }
1581
1582 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1583 Label L_oops_equal;
1584 Label L_oops_not_equal;
1585 Label L_end;
1586
1587 Register left = op->left()->as_register();
1588 Register right = op->right()->as_register();
1589
1590 __ cmp(left, right);
1591 __ br(Assembler::EQ, L_oops_equal);
1592
1593 // (1) Null check -- if one of the operands is null, the other must not be null (because
1594 // the two references are not equal), so they are not substitutable,
1595 __ cbz(left, L_oops_not_equal);
1596 __ cbz(right, L_oops_not_equal);
1597
1598 ciKlass* left_klass = op->left_klass();
1599 ciKlass* right_klass = op->right_klass();
1600
1601 // (2) Inline type check -- if either of the operands is not an inline type,
1602 // they are not substitutable. We do this only if we are not sure that the
1603 // operands are inline type
1604 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node.
1605 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
1606 Register tmp1 = op->tmp1()->as_register();
1607 Register tmp2 = op->tmp2()->as_register();
1608 __ mov(tmp1, markWord::inline_type_pattern);
1609 __ ldr(tmp2, Address(left, oopDesc::mark_offset_in_bytes()));
1610 __ andr(tmp1, tmp1, tmp2);
1611 __ ldr(tmp2, Address(right, oopDesc::mark_offset_in_bytes()));
1612 __ andr(tmp1, tmp1, tmp2);
1613 __ cmp(tmp1, (u1)markWord::inline_type_pattern);
1614 __ br(Assembler::NE, L_oops_not_equal);
1615 }
1616
1617 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
1618 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) {
1619 // No need to load klass -- the operands are statically known to be the same inline klass.
1620 __ b(*op->stub()->entry());
1621 } else {
1622 Register tmp1 = op->tmp1()->as_register();
1623 Register tmp2 = op->tmp2()->as_register();
1624 __ cmp_klasses_from_objects(left, right, tmp1, tmp2);
1625 __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check
1626 // fall through to L_oops_not_equal
1627 }
1628
1629 __ bind(L_oops_not_equal);
1630 move(op->not_equal_result(), op->result_opr());
1631 __ b(L_end);
1632
1633 // We've returned from the stub. R0 contains 0x0 IFF the two
1634 // operands are not substitutable. (Don't compare against 0x1 in case the
1635 // C compiler is naughty)
1636 __ bind(*op->stub()->continuation());
1637 __ cbz(r0, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1638
1639 __ bind(L_oops_equal);
1640 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
1641 // fall-through
1642 __ bind(L_end);
1643 }
1644
1645
1646 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1647 __ cmpxchg(addr, cmpval, newval, Assembler::word, memory_order_seq_cst, rscratch1);
1648 __ cset(rscratch1, Assembler::NE);
1649 }
1650
1651 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1652 __ cmpxchg(addr, cmpval, newval, Assembler::xword, memory_order_seq_cst, rscratch1);
1653 __ cset(rscratch1, Assembler::NE);
1654 }
1655
1656
1657 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1658 Register addr;
1659 if (op->addr()->is_register()) {
1660 addr = as_reg(op->addr());
1661 } else {
1662 assert(op->addr()->is_address(), "what else?");
1663 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1664 assert(addr_ptr->disp() == 0, "need 0 disp");
1665 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1666 addr = as_reg(addr_ptr->base());
1667 }
1668 Register newval = as_reg(op->new_value());
1669 Register cmpval = as_reg(op->cmp_value());
1670
1671 if (op->code() == lir_cas_obj) {
1672 if (UseCompressedOops) {
1673 Register t1 = op->tmp1()->as_register();
1674 assert(op->tmp1()->is_valid(), "must be");
1675 __ encode_heap_oop(t1, cmpval);
1676 cmpval = t1;
1677 __ encode_heap_oop(rscratch2, newval);
1678 newval = rscratch2;
1679 casw(addr, newval, cmpval);
1680 } else {
1681 casl(addr, newval, cmpval);
1682 }
1683 } else if (op->code() == lir_cas_int) {
1684 casw(addr, newval, cmpval);
1685 } else {
1686 casl(addr, newval, cmpval);
1687 }
1688 }
1689
1690
1691 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1692 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1693 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1694
1695 Assembler::Condition acond, ncond;
1696 switch (condition) {
1697 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1698 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1699 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1700 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1701 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1702 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1703 case lir_cond_belowEqual:
1704 case lir_cond_aboveEqual:
1705 default: ShouldNotReachHere();
1706 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1707 }
1708
1709 assert(result->is_single_cpu() || result->is_double_cpu(),
1710 "expect single register for result");
1711 if (opr1->is_constant() && opr2->is_constant()
1712 && opr1->type() == T_INT && opr2->type() == T_INT) {
1713 jint val1 = opr1->as_jint();
1714 jint val2 = opr2->as_jint();
1715 if (val1 == 0 && val2 == 1) {
1716 __ cset(result->as_register(), ncond);
1717 return;
1718 } else if (val1 == 1 && val2 == 0) {
1719 __ cset(result->as_register(), acond);
1720 return;
1721 }
1722 }
1723
1724 if (opr1->is_constant() && opr2->is_constant()
1725 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1726 jlong val1 = opr1->as_jlong();
1727 jlong val2 = opr2->as_jlong();
1728 if (val1 == 0 && val2 == 1) {
1729 __ cset(result->as_register_lo(), ncond);
1730 return;
1731 } else if (val1 == 1 && val2 == 0) {
1732 __ cset(result->as_register_lo(), acond);
1733 return;
1734 }
1735 }
1736
1737 if (opr1->is_stack()) {
1738 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1739 opr1 = FrameMap::rscratch1_opr;
1740 } else if (opr1->is_constant()) {
1741 LIR_Opr tmp
1742 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1743 const2reg(opr1, tmp, lir_patch_none, nullptr);
1744 opr1 = tmp;
1745 }
1746
1747 if (opr2->is_stack()) {
1748 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1749 opr2 = FrameMap::rscratch2_opr;
1750 } else if (opr2->is_constant()) {
1751 LIR_Opr tmp
1752 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1753 const2reg(opr2, tmp, lir_patch_none, nullptr);
1754 opr2 = tmp;
1755 }
1756
1757 if (result->type() == T_LONG)
1758 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1759 else
1760 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1761 }
1762
1763 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1764 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1765
1766 if (left->is_single_cpu()) {
1767 Register lreg = left->as_register();
1768 Register dreg = as_reg(dest);
1769
1770 if (right->is_single_cpu()) {
1771 // cpu register - cpu register
1772
1773 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1774 "should be");
1775 Register rreg = right->as_register();
1776 switch (code) {
1777 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1778 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1779 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1780 default: ShouldNotReachHere();
1781 }
1782
1783 } else if (right->is_double_cpu()) {
1784 Register rreg = right->as_register_lo();
1785 // single_cpu + double_cpu: can happen with obj+long
1786 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1787 switch (code) {
1788 case lir_add: __ add(dreg, lreg, rreg); break;
1789 case lir_sub: __ sub(dreg, lreg, rreg); break;
1790 default: ShouldNotReachHere();
1791 }
1792 } else if (right->is_constant()) {
1793 // cpu register - constant
1794 jlong c;
1795
1796 // FIXME. This is fugly: we really need to factor all this logic.
1797 switch(right->type()) {
1798 case T_LONG:
1799 c = right->as_constant_ptr()->as_jlong();
1800 break;
1801 case T_INT:
1802 case T_ADDRESS:
1803 c = right->as_constant_ptr()->as_jint();
1804 break;
1805 default:
1806 ShouldNotReachHere();
1807 c = 0; // unreachable
1808 break;
1809 }
1810
1811 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1812 if (c == 0 && dreg == lreg) {
1813 COMMENT("effective nop elided");
1814 return;
1815 }
1816 switch(left->type()) {
1817 case T_INT:
1818 switch (code) {
1819 case lir_add: __ addw(dreg, lreg, c); break;
1820 case lir_sub: __ subw(dreg, lreg, c); break;
1821 default: ShouldNotReachHere();
1822 }
1823 break;
1824 case T_OBJECT:
1825 case T_ADDRESS:
1826 switch (code) {
1827 case lir_add: __ add(dreg, lreg, c); break;
1828 case lir_sub: __ sub(dreg, lreg, c); break;
1829 default: ShouldNotReachHere();
1830 }
1831 break;
1832 default:
1833 ShouldNotReachHere();
1834 }
1835 } else {
1836 ShouldNotReachHere();
1837 }
1838
1839 } else if (left->is_double_cpu()) {
1840 Register lreg_lo = left->as_register_lo();
1841
1842 if (right->is_double_cpu()) {
1843 // cpu register - cpu register
1844 Register rreg_lo = right->as_register_lo();
1845 switch (code) {
1846 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1847 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1848 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1849 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1850 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1851 default:
1852 ShouldNotReachHere();
1853 }
1854
1855 } else if (right->is_constant()) {
1856 jlong c = right->as_constant_ptr()->as_jlong();
1857 Register dreg = as_reg(dest);
1858 switch (code) {
1859 case lir_add:
1860 case lir_sub:
1861 if (c == 0 && dreg == lreg_lo) {
1862 COMMENT("effective nop elided");
1863 return;
1864 }
1865 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1866 break;
1867 case lir_div:
1868 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1869 if (c == 1) {
1870 // move lreg_lo to dreg if divisor is 1
1871 __ mov(dreg, lreg_lo);
1872 } else {
1873 unsigned int shift = log2i_exact(c);
1874 // use rscratch1 as intermediate result register
1875 __ asr(rscratch1, lreg_lo, 63);
1876 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1877 __ asr(dreg, rscratch1, shift);
1878 }
1879 break;
1880 case lir_rem:
1881 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1882 if (c == 1) {
1883 // move 0 to dreg if divisor is 1
1884 __ mov(dreg, zr);
1885 } else {
1886 // use rscratch1 as intermediate result register
1887 __ negs(rscratch1, lreg_lo);
1888 __ andr(dreg, lreg_lo, c - 1);
1889 __ andr(rscratch1, rscratch1, c - 1);
1890 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1891 }
1892 break;
1893 default:
1894 ShouldNotReachHere();
1895 }
1896 } else {
1897 ShouldNotReachHere();
1898 }
1899 } else if (left->is_single_fpu()) {
1900 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1901 switch (code) {
1902 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1903 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1904 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1905 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1906 default:
1907 ShouldNotReachHere();
1908 }
1909 } else if (left->is_double_fpu()) {
1910 if (right->is_double_fpu()) {
1911 // fpu register - fpu register
1912 switch (code) {
1913 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1914 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1915 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1916 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1917 default:
1918 ShouldNotReachHere();
1919 }
1920 } else {
1921 if (right->is_constant()) {
1922 ShouldNotReachHere();
1923 }
1924 ShouldNotReachHere();
1925 }
1926 } else if (left->is_single_stack() || left->is_address()) {
1927 assert(left == dest, "left and dest must be equal");
1928 ShouldNotReachHere();
1929 } else {
1930 ShouldNotReachHere();
1931 }
1932 }
1933
1934 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1935 switch(code) {
1936 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1937 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1938 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1939 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1940 default : ShouldNotReachHere();
1941 }
1942 }
1943
1944 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1945
1946 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1947 Register Rleft = left->is_single_cpu() ? left->as_register() :
1948 left->as_register_lo();
1949 if (dst->is_single_cpu()) {
1950 Register Rdst = dst->as_register();
1951 if (right->is_constant()) {
1952 switch (code) {
1953 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1954 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1955 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1956 default: ShouldNotReachHere(); break;
1957 }
1958 } else {
1959 Register Rright = right->is_single_cpu() ? right->as_register() :
1960 right->as_register_lo();
1961 switch (code) {
1962 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1963 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1964 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1965 default: ShouldNotReachHere(); break;
1966 }
1967 }
1968 } else {
1969 Register Rdst = dst->as_register_lo();
1970 if (right->is_constant()) {
1971 switch (code) {
1972 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1973 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1974 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1975 default: ShouldNotReachHere(); break;
1976 }
1977 } else {
1978 Register Rright = right->is_single_cpu() ? right->as_register() :
1979 right->as_register_lo();
1980 switch (code) {
1981 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1982 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1983 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1984 default: ShouldNotReachHere(); break;
1985 }
1986 }
1987 }
1988 }
1989
1990
1991
1992 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1993
1994 // opcode check
1995 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1996 bool is_irem = (code == lir_irem);
1997
1998 // operand check
1999 assert(left->is_single_cpu(), "left must be register");
2000 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2001 assert(result->is_single_cpu(), "result must be register");
2002 Register lreg = left->as_register();
2003 Register dreg = result->as_register();
2004
2005 // power-of-2 constant check and codegen
2006 if (right->is_constant()) {
2007 int c = right->as_constant_ptr()->as_jint();
2008 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
2009 if (is_irem) {
2010 if (c == 1) {
2011 // move 0 to dreg if divisor is 1
2012 __ movw(dreg, zr);
2013 } else {
2014 // use rscratch1 as intermediate result register
2015 __ negsw(rscratch1, lreg);
2016 __ andw(dreg, lreg, c - 1);
2017 __ andw(rscratch1, rscratch1, c - 1);
2018 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
2019 }
2020 } else {
2021 if (c == 1) {
2022 // move lreg to dreg if divisor is 1
2023 __ movw(dreg, lreg);
2024 } else {
2025 unsigned int shift = exact_log2(c);
2026 // use rscratch1 as intermediate result register
2027 __ asrw(rscratch1, lreg, 31);
2028 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
2029 __ asrw(dreg, rscratch1, shift);
2030 }
2031 }
2032 } else {
2033 Register rreg = right->as_register();
2034 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
2035 }
2036 }
2037
2038
2039 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2040 if (opr1->is_constant() && opr2->is_single_cpu()) {
2041 // tableswitch
2042 Register reg = as_reg(opr2);
2043 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
2044 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
2045 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
2046 Register reg1 = as_reg(opr1);
2047 if (opr2->is_single_cpu()) {
2048 // cpu register - cpu register
2049 Register reg2 = opr2->as_register();
2050 if (is_reference_type(opr1->type())) {
2051 __ cmpoop(reg1, reg2);
2052 } else {
2053 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2054 __ cmpw(reg1, reg2);
2055 }
2056 return;
2057 }
2058 if (opr2->is_double_cpu()) {
2059 // cpu register - cpu register
2060 Register reg2 = opr2->as_register_lo();
2061 __ cmp(reg1, reg2);
2062 return;
2063 }
2064
2065 if (opr2->is_constant()) {
2066 bool is_32bit = false; // width of register operand
2067 jlong imm;
2068
2069 switch(opr2->type()) {
2070 case T_INT:
2071 imm = opr2->as_constant_ptr()->as_jint();
2072 is_32bit = true;
2073 break;
2074 case T_LONG:
2075 imm = opr2->as_constant_ptr()->as_jlong();
2076 break;
2077 case T_ADDRESS:
2078 imm = opr2->as_constant_ptr()->as_jint();
2079 break;
2080 case T_METADATA:
2081 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
2082 break;
2083 case T_OBJECT:
2084 case T_ARRAY:
2085 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
2086 __ cmpoop(reg1, rscratch1);
2087 return;
2088 default:
2089 ShouldNotReachHere();
2090 imm = 0; // unreachable
2091 break;
2092 }
2093
2094 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
2095 if (is_32bit)
2096 __ cmpw(reg1, imm);
2097 else
2098 __ subs(zr, reg1, imm);
2099 return;
2100 } else {
2101 __ mov(rscratch1, imm);
2102 if (is_32bit)
2103 __ cmpw(reg1, rscratch1);
2104 else
2105 __ cmp(reg1, rscratch1);
2106 return;
2107 }
2108 } else
2109 ShouldNotReachHere();
2110 } else if (opr1->is_single_fpu()) {
2111 FloatRegister reg1 = opr1->as_float_reg();
2112 assert(opr2->is_single_fpu(), "expect single float register");
2113 FloatRegister reg2 = opr2->as_float_reg();
2114 __ fcmps(reg1, reg2);
2115 } else if (opr1->is_double_fpu()) {
2116 FloatRegister reg1 = opr1->as_double_reg();
2117 assert(opr2->is_double_fpu(), "expect double float register");
2118 FloatRegister reg2 = opr2->as_double_reg();
2119 __ fcmpd(reg1, reg2);
2120 } else {
2121 ShouldNotReachHere();
2122 }
2123 }
2124
2125 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2126 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2127 bool is_unordered_less = (code == lir_ucmp_fd2i);
2128 if (left->is_single_fpu()) {
2129 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2130 } else if (left->is_double_fpu()) {
2131 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2132 } else {
2133 ShouldNotReachHere();
2134 }
2135 } else if (code == lir_cmp_l2i) {
2136 Label done;
2137 __ cmp(left->as_register_lo(), right->as_register_lo());
2138 __ mov(dst->as_register(), (uint64_t)-1L);
2139 __ br(Assembler::LT, done);
2140 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2141 __ bind(done);
2142 } else {
2143 ShouldNotReachHere();
2144 }
2145 }
2146
2147
2148 void LIR_Assembler::align_call(LIR_Code code) { }
2149
2150
2151 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2152 address call = __ trampoline_call(Address(op->addr(), rtype));
2153 if (call == nullptr) {
2154 bailout("trampoline stub overflow");
2155 return;
2156 }
2157 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2158 __ post_call_nop();
2159 }
2160
2161
2162 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2163 address call = __ ic_call(op->addr());
2164 if (call == nullptr) {
2165 bailout("trampoline stub overflow");
2166 return;
2167 }
2168 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2169 __ post_call_nop();
2170 }
2171
2172 void LIR_Assembler::emit_static_call_stub() {
2173 address call_pc = __ pc();
2174 address stub = __ start_a_stub(call_stub_size());
2175 if (stub == nullptr) {
2176 bailout("static call stub overflow");
2177 return;
2178 }
2179
2180 int start = __ offset();
2181
2182 __ relocate(static_stub_Relocation::spec(call_pc));
2183 __ emit_static_call_stub();
2184
2185 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2186 <= call_stub_size(), "stub too big");
2187 __ end_a_stub();
2188 }
2189
2190
2191 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2192 assert(exceptionOop->as_register() == r0, "must match");
2193 assert(exceptionPC->as_register() == r3, "must match");
2194
2195 // exception object is not added to oop map by LinearScan
2196 // (LinearScan assumes that no oops are in fixed registers)
2197 info->add_register_oop(exceptionOop);
2198 StubId unwind_id;
2199
2200 // get current pc information
2201 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2202 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2203 // As no instructions have been generated yet for this LIR node it's
2204 // possible that an oop map already exists for the current offset.
2205 // In that case insert an dummy NOP here to ensure all oop map PCs
2206 // are unique. See JDK-8237483.
2207 __ nop();
2208 }
2209 int pc_for_athrow_offset = __ offset();
2210 InternalAddress pc_for_athrow(__ pc());
2211 __ adr(exceptionPC->as_register(), pc_for_athrow);
2212 add_call_info(pc_for_athrow_offset, info); // for exception handler
2213
2214 __ verify_not_null_oop(r0);
2215 // search an exception handler (r0: exception oop, r3: throwing pc)
2216 if (compilation()->has_fpu_code()) {
2217 unwind_id = StubId::c1_handle_exception_id;
2218 } else {
2219 unwind_id = StubId::c1_handle_exception_nofpu_id;
2220 }
2221 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2222
2223 // FIXME: enough room for two byte trap ????
2224 __ nop();
2225 }
2226
2227
2228 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2229 assert(exceptionOop->as_register() == r0, "must match");
2230
2231 __ b(_unwind_handler_entry);
2232 }
2233
2234
2235 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2236 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2237 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2238
2239 switch (left->type()) {
2240 case T_INT: {
2241 switch (code) {
2242 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2243 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2244 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2245 default:
2246 ShouldNotReachHere();
2247 break;
2248 }
2249 break;
2250 case T_LONG:
2251 case T_ADDRESS:
2252 case T_OBJECT:
2253 switch (code) {
2254 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2255 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2256 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2257 default:
2258 ShouldNotReachHere();
2259 break;
2260 }
2261 break;
2262 default:
2263 ShouldNotReachHere();
2264 break;
2265 }
2266 }
2267 }
2268
2269
2270 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2271 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2272 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2273
2274 switch (left->type()) {
2275 case T_INT: {
2276 switch (code) {
2277 case lir_shl: __ lslw (dreg, lreg, count); break;
2278 case lir_shr: __ asrw (dreg, lreg, count); break;
2279 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2280 default:
2281 ShouldNotReachHere();
2282 break;
2283 }
2284 break;
2285 case T_LONG:
2286 case T_ADDRESS:
2287 case T_OBJECT:
2288 switch (code) {
2289 case lir_shl: __ lsl (dreg, lreg, count); break;
2290 case lir_shr: __ asr (dreg, lreg, count); break;
2291 case lir_ushr: __ lsr (dreg, lreg, count); break;
2292 default:
2293 ShouldNotReachHere();
2294 break;
2295 }
2296 break;
2297 default:
2298 ShouldNotReachHere();
2299 break;
2300 }
2301 }
2302 }
2303
2304
2305 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2306 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2307 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2308 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2309 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2310 }
2311
2312
2313 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2314 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2315 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2316 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2317 __ mov (rscratch1, c);
2318 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2319 }
2320
2321
2322 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2323 ShouldNotReachHere();
2324 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2325 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2326 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2327 __ lea(rscratch1, __ constant_oop_address(o));
2328 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2329 }
2330
2331 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
2332 if (null_check) {
2333 __ cbz(obj, *slow_path->entry());
2334 }
2335 if (is_dest) {
2336 __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
2337 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2338 } else {
2339 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2340 }
2341 }
2342
2343 // This code replaces a call to arraycopy; no exception may
2344 // be thrown in this code, they must be thrown in the System.arraycopy
2345 // activation frame; we could save some checks if this would not be the case
2346 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2347 ciArrayKlass* default_type = op->expected_type();
2348 Register src = op->src()->as_register();
2349 Register dst = op->dst()->as_register();
2350 Register src_pos = op->src_pos()->as_register();
2351 Register dst_pos = op->dst_pos()->as_register();
2352 Register length = op->length()->as_register();
2353 Register tmp = op->tmp()->as_register();
2354
2355 CodeStub* stub = op->stub();
2356 int flags = op->flags();
2357 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2358 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2359
2360 if (flags & LIR_OpArrayCopy::always_slow_path) {
2361 __ b(*stub->entry());
2362 __ bind(*stub->continuation());
2363 return;
2364 }
2365
2366 // if we don't know anything, just go through the generic arraycopy
2367 if (default_type == nullptr // || basic_type == T_OBJECT
2368 ) {
2369 Label done;
2370 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2371
2372 // Save the arguments in case the generic arraycopy fails and we
2373 // have to fall back to the JNI stub
2374 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2375 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2376 __ str(src, Address(sp, 4*BytesPerWord));
2377
2378 address copyfunc_addr = StubRoutines::generic_arraycopy();
2379 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2380
2381 // The arguments are in java calling convention so we shift them
2382 // to C convention
2383 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2384 __ mov(c_rarg0, j_rarg0);
2385 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2386 __ mov(c_rarg1, j_rarg1);
2387 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2388 __ mov(c_rarg2, j_rarg2);
2389 assert_different_registers(c_rarg3, j_rarg4);
2390 __ mov(c_rarg3, j_rarg3);
2391 __ mov(c_rarg4, j_rarg4);
2392 #ifndef PRODUCT
2393 if (PrintC1Statistics) {
2394 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2395 }
2396 #endif
2397 __ far_call(RuntimeAddress(copyfunc_addr));
2398
2399 __ cbz(r0, *stub->continuation());
2400
2401 // Reload values from the stack so they are where the stub
2402 // expects them.
2403 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2404 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2405 __ ldr(src, Address(sp, 4*BytesPerWord));
2406
2407 // r0 is -1^K where K == partial copied count
2408 __ eonw(rscratch1, r0, zr);
2409 // adjust length down and src/end pos up by partial copied count
2410 __ subw(length, length, rscratch1);
2411 __ addw(src_pos, src_pos, rscratch1);
2412 __ addw(dst_pos, dst_pos, rscratch1);
2413 __ b(*stub->entry());
2414
2415 __ bind(*stub->continuation());
2416 return;
2417 }
2418
2419 // Handle inline type arrays
2420 if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
2421 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
2422 }
2423 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
2424 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
2425 }
2426
2427 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2428
2429 int elem_size = type2aelembytes(basic_type);
2430 int scale = exact_log2(elem_size);
2431
2432 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2433 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2434
2435 // test for null
2436 if (flags & LIR_OpArrayCopy::src_null_check) {
2437 __ cbz(src, *stub->entry());
2438 }
2439 if (flags & LIR_OpArrayCopy::dst_null_check) {
2440 __ cbz(dst, *stub->entry());
2441 }
2442
2443 // If the compiler was not able to prove that exact type of the source or the destination
2444 // of the arraycopy is an array type, check at runtime if the source or the destination is
2445 // an instance type.
2446 if (flags & LIR_OpArrayCopy::type_check) {
2447 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2448 __ load_klass(tmp, dst, rscratch1);
2449 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2450 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2451 __ br(Assembler::GE, *stub->entry());
2452 }
2453
2454 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2455 __ load_klass(tmp, src, rscratch1);
2456 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2457 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2458 __ br(Assembler::GE, *stub->entry());
2459 }
2460 }
2461
2462 // check if negative
2463 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2464 __ cmpw(src_pos, 0);
2465 __ br(Assembler::LT, *stub->entry());
2466 }
2467 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2468 __ cmpw(dst_pos, 0);
2469 __ br(Assembler::LT, *stub->entry());
2470 }
2471
2472 if (flags & LIR_OpArrayCopy::length_positive_check) {
2473 __ cmpw(length, 0);
2474 __ br(Assembler::LT, *stub->entry());
2475 }
2476
2477 if (flags & LIR_OpArrayCopy::src_range_check) {
2478 __ addw(tmp, src_pos, length);
2479 __ ldrw(rscratch1, src_length_addr);
2480 __ cmpw(tmp, rscratch1);
2481 __ br(Assembler::HI, *stub->entry());
2482 }
2483 if (flags & LIR_OpArrayCopy::dst_range_check) {
2484 __ addw(tmp, dst_pos, length);
2485 __ ldrw(rscratch1, dst_length_addr);
2486 __ cmpw(tmp, rscratch1);
2487 __ br(Assembler::HI, *stub->entry());
2488 }
2489
2490 if (flags & LIR_OpArrayCopy::type_check) {
2491 // We don't know the array types are compatible
2492 if (basic_type != T_OBJECT) {
2493 // Simple test for basic type arrays
2494 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2495 __ br(Assembler::NE, *stub->entry());
2496 } else {
2497 // For object arrays, if src is a sub class of dst then we can
2498 // safely do the copy.
2499 Label cont, slow;
2500
2501 #define PUSH(r1, r2) \
2502 stp(r1, r2, __ pre(sp, -2 * wordSize));
2503
2504 #define POP(r1, r2) \
2505 ldp(r1, r2, __ post(sp, 2 * wordSize));
2506
2507 __ PUSH(src, dst);
2508
2509 __ load_klass(src, src, rscratch1);
2510 __ load_klass(dst, dst, rscratch1);
2511
2512 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2513
2514 __ PUSH(src, dst);
2515 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2516 __ POP(src, dst);
2517
2518 __ cbnz(src, cont);
2519
2520 __ bind(slow);
2521 __ POP(src, dst);
2522
2523 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2524 if (copyfunc_addr != nullptr) { // use stub if available
2525 // src is not a sub class of dst so we have to do a
2526 // per-element check.
2527
2528 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2529 if ((flags & mask) != mask) {
2530 // Check that at least both of them object arrays.
2531 assert(flags & mask, "one of the two should be known to be an object array");
2532
2533 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2534 __ load_klass(tmp, src, rscratch1);
2535 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2536 __ load_klass(tmp, dst, rscratch1);
2537 }
2538 int lh_offset = in_bytes(Klass::layout_helper_offset());
2539 Address klass_lh_addr(tmp, lh_offset);
2540 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2541 __ ldrw(rscratch1, klass_lh_addr);
2542 __ mov(rscratch2, objArray_lh);
2543 __ eorw(rscratch1, rscratch1, rscratch2);
2544 __ cbnzw(rscratch1, *stub->entry());
2545 }
2546
2547 // Spill because stubs can use any register they like and it's
2548 // easier to restore just those that we care about.
2549 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2550 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2551 __ str(src, Address(sp, 4*BytesPerWord));
2552
2553 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2554 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2555 assert_different_registers(c_rarg0, dst, dst_pos, length);
2556 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2557 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2558 assert_different_registers(c_rarg1, dst, length);
2559 __ uxtw(c_rarg2, length);
2560 assert_different_registers(c_rarg2, dst);
2561
2562 __ load_klass(c_rarg4, dst, rscratch1);
2563 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2564 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2565 __ far_call(RuntimeAddress(copyfunc_addr));
2566
2567 #ifndef PRODUCT
2568 if (PrintC1Statistics) {
2569 Label failed;
2570 __ cbnz(r0, failed);
2571 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2572 __ bind(failed);
2573 }
2574 #endif
2575
2576 __ cbz(r0, *stub->continuation());
2577
2578 #ifndef PRODUCT
2579 if (PrintC1Statistics) {
2580 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2581 }
2582 #endif
2583 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2584
2585 // Restore previously spilled arguments
2586 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2587 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2588 __ ldr(src, Address(sp, 4*BytesPerWord));
2589
2590 // return value is -1^K where K is partial copied count
2591 __ eonw(rscratch1, r0, zr);
2592 // adjust length down and src/end pos up by partial copied count
2593 __ subw(length, length, rscratch1);
2594 __ addw(src_pos, src_pos, rscratch1);
2595 __ addw(dst_pos, dst_pos, rscratch1);
2596 }
2597
2598 __ b(*stub->entry());
2599
2600 __ bind(cont);
2601 __ POP(src, dst);
2602 }
2603 }
2604
2605 #ifdef ASSERT
2606 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2607 // Sanity check the known type with the incoming class. For the
2608 // primitive case the types must match exactly with src.klass and
2609 // dst.klass each exactly matching the default type. For the
2610 // object array case, if no type check is needed then either the
2611 // dst type is exactly the expected type and the src type is a
2612 // subtype which we can't check or src is the same array as dst
2613 // but not necessarily exactly of type default_type.
2614 Label known_ok, halt;
2615 __ mov_metadata(tmp, default_type->constant_encoding());
2616
2617 if (basic_type != T_OBJECT) {
2618 __ cmp_klass(dst, tmp, rscratch1, rscratch2);
2619 __ br(Assembler::NE, halt);
2620 __ cmp_klass(src, tmp, rscratch1, rscratch2);
2621 __ br(Assembler::EQ, known_ok);
2622 } else {
2623 __ cmp_klass(dst, tmp, rscratch1, rscratch2);
2624 __ br(Assembler::EQ, known_ok);
2625 __ cmp(src, dst);
2626 __ br(Assembler::EQ, known_ok);
2627 }
2628 __ bind(halt);
2629 __ stop("incorrect type information in arraycopy");
2630 __ bind(known_ok);
2631 }
2632 #endif
2633
2634 #ifndef PRODUCT
2635 if (PrintC1Statistics) {
2636 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2637 }
2638 #endif
2639
2640 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2641 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2642 assert_different_registers(c_rarg0, dst, dst_pos, length);
2643 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2644 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2645 assert_different_registers(c_rarg1, dst, length);
2646 __ uxtw(c_rarg2, length);
2647 assert_different_registers(c_rarg2, dst);
2648
2649 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2650 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2651 const char *name;
2652 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2653
2654 CodeBlob *cb = CodeCache::find_blob(entry);
2655 if (cb) {
2656 __ far_call(RuntimeAddress(entry));
2657 } else {
2658 __ call_VM_leaf(entry, 3);
2659 }
2660
2661 if (stub != nullptr) {
2662 __ bind(*stub->continuation());
2663 }
2664 }
2665
2666
2667
2668
2669 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2670 Register obj = op->obj_opr()->as_register(); // may not be an oop
2671 Register hdr = op->hdr_opr()->as_register();
2672 Register lock = op->lock_opr()->as_register();
2673 Register temp = op->scratch_opr()->as_register();
2674 if (op->code() == lir_lock) {
2675 // add debug info for NullPointerException only if one is possible
2676 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2677 if (op->info() != nullptr) {
2678 add_debug_info_for_null_check(null_check_offset, op->info());
2679 }
2680 // done
2681 } else if (op->code() == lir_unlock) {
2682 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2683 } else {
2684 Unimplemented();
2685 }
2686 __ bind(*op->stub()->continuation());
2687 }
2688
2689 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2690 Register obj = op->obj()->as_pointer_register();
2691 Register result = op->result_opr()->as_pointer_register();
2692
2693 CodeEmitInfo* info = op->info();
2694 if (info != nullptr) {
2695 add_debug_info_for_null_check_here(info);
2696 }
2697
2698 __ load_klass(result, obj, rscratch1);
2699 }
2700
2701 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2702 ciMethod* method = op->profiled_method();
2703 int bci = op->profiled_bci();
2704 ciMethod* callee = op->profiled_callee();
2705
2706 // Update counter for all call types
2707 ciMethodData* md = method->method_data_or_null();
2708 assert(md != nullptr, "Sanity");
2709 ciProfileData* data = md->bci_to_data(bci);
2710 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2711 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2712 Register mdo = op->mdo()->as_register();
2713 __ mov_metadata(mdo, md->constant_encoding());
2714 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2715 // Perform additional virtual call profiling for invokevirtual and
2716 // invokeinterface bytecodes
2717 if (op->should_profile_receiver_type()) {
2718 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2719 Register recv = op->recv()->as_register();
2720 assert_different_registers(mdo, recv);
2721 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2722 ciKlass* known_klass = op->known_holder();
2723 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2724 // We know the type that will be seen at this call site; we can
2725 // statically update the MethodData* rather than needing to do
2726 // dynamic tests on the receiver type.
2727 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2728 for (uint i = 0; i < VirtualCallData::row_limit(); i++) {
2729 ciKlass* receiver = vc_data->receiver(i);
2730 if (known_klass->equals(receiver)) {
2731 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2732 __ addptr(data_addr, DataLayout::counter_increment);
2733 return;
2734 }
2735 }
2736 // Receiver type is not found in profile data.
2737 // Fall back to runtime helper to handle the rest at runtime.
2738 __ mov_metadata(recv, known_klass->constant_encoding());
2739 } else {
2740 __ load_klass(recv, recv, rscratch1);
2741 }
2742 type_profile_helper(mdo, md, data, recv);
2743 } else {
2744 // Static call
2745 __ addptr(counter_addr, DataLayout::counter_increment);
2746 }
2747 }
2748
2749
2750 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2751 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2752 }
2753
2754 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2755 assert(op->crc()->is_single_cpu(), "crc must be register");
2756 assert(op->val()->is_single_cpu(), "byte value must be register");
2757 assert(op->result_opr()->is_single_cpu(), "result must be register");
2758 Register crc = op->crc()->as_register();
2759 Register val = op->val()->as_register();
2760 Register res = op->result_opr()->as_register();
2761
2762 assert_different_registers(val, crc, res);
2763 uint64_t offset;
2764 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2765 __ add(res, res, offset);
2766
2767 __ mvnw(crc, crc); // ~crc
2768 __ update_byte_crc32(crc, val, res);
2769 __ mvnw(res, crc); // ~crc
2770 }
2771
2772 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2773 COMMENT("emit_profile_type {");
2774 Register obj = op->obj()->as_register();
2775 Register tmp = op->tmp()->as_pointer_register();
2776 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2777 ciKlass* exact_klass = op->exact_klass();
2778 intptr_t current_klass = op->current_klass();
2779 bool not_null = op->not_null();
2780 bool no_conflict = op->no_conflict();
2781
2782 Label update, next, none;
2783
2784 bool do_null = !not_null;
2785 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2786 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2787
2788 assert(do_null || do_update, "why are we here?");
2789 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2790 assert(mdo_addr.base() != rscratch1, "wrong register");
2791
2792 __ verify_oop(obj);
2793
2794 if (tmp != obj) {
2795 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2796 __ mov(tmp, obj);
2797 } else {
2798 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2799 }
2800 if (do_null) {
2801 __ cbnz(tmp, update);
2802 if (!TypeEntries::was_null_seen(current_klass)) {
2803 __ ldr(rscratch2, mdo_addr);
2804 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2805 __ str(rscratch2, mdo_addr);
2806 }
2807 if (do_update) {
2808 #ifndef ASSERT
2809 __ b(next);
2810 }
2811 #else
2812 __ b(next);
2813 }
2814 } else {
2815 __ cbnz(tmp, update);
2816 __ stop("unexpected null obj");
2817 #endif
2818 }
2819
2820 __ bind(update);
2821
2822 if (do_update) {
2823 #ifdef ASSERT
2824 if (exact_klass != nullptr) {
2825 Label ok;
2826 __ load_klass(tmp, tmp, rscratch1);
2827 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2828 __ eor(rscratch1, tmp, rscratch1);
2829 __ cbz(rscratch1, ok);
2830 __ stop("exact klass and actual klass differ");
2831 __ bind(ok);
2832 }
2833 #endif
2834 if (!no_conflict) {
2835 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2836 if (exact_klass != nullptr) {
2837 __ mov_metadata(tmp, exact_klass->constant_encoding());
2838 } else {
2839 __ load_klass(tmp, tmp, rscratch1);
2840 }
2841
2842 __ ldr(rscratch2, mdo_addr);
2843 __ eor(tmp, tmp, rscratch2);
2844 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2845 // klass seen before, nothing to do. The unknown bit may have been
2846 // set already but no need to check.
2847 __ cbz(rscratch1, next);
2848
2849 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2850
2851 if (TypeEntries::is_type_none(current_klass)) {
2852 __ cbz(rscratch2, none);
2853 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2854 __ br(Assembler::EQ, none);
2855 // There is a chance that the checks above
2856 // fail if another thread has just set the
2857 // profiling to this obj's klass
2858 __ dmb(Assembler::ISHLD);
2859 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2860 __ ldr(rscratch2, mdo_addr);
2861 __ eor(tmp, tmp, rscratch2);
2862 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2863 __ cbz(rscratch1, next);
2864 }
2865 } else {
2866 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2867 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2868
2869 __ ldr(tmp, mdo_addr);
2870 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2871 }
2872
2873 // different than before. Cannot keep accurate profile.
2874 __ ldr(rscratch2, mdo_addr);
2875 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2876 __ str(rscratch2, mdo_addr);
2877
2878 if (TypeEntries::is_type_none(current_klass)) {
2879 __ b(next);
2880
2881 __ bind(none);
2882 // first time here. Set profile type.
2883 __ str(tmp, mdo_addr);
2884 #ifdef ASSERT
2885 __ andr(tmp, tmp, TypeEntries::type_mask);
2886 __ verify_klass_ptr(tmp);
2887 #endif
2888 }
2889 } else {
2890 // There's a single possible klass at this profile point
2891 assert(exact_klass != nullptr, "should be");
2892 if (TypeEntries::is_type_none(current_klass)) {
2893 __ mov_metadata(tmp, exact_klass->constant_encoding());
2894 __ ldr(rscratch2, mdo_addr);
2895 __ eor(tmp, tmp, rscratch2);
2896 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2897 __ cbz(rscratch1, next);
2898 #ifdef ASSERT
2899 {
2900 Label ok;
2901 __ ldr(rscratch1, mdo_addr);
2902 __ cbz(rscratch1, ok);
2903 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2904 __ br(Assembler::EQ, ok);
2905 // may have been set by another thread
2906 __ dmb(Assembler::ISHLD);
2907 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2908 __ ldr(rscratch2, mdo_addr);
2909 __ eor(rscratch2, rscratch1, rscratch2);
2910 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2911 __ cbz(rscratch2, ok);
2912
2913 __ stop("unexpected profiling mismatch");
2914 __ bind(ok);
2915 }
2916 #endif
2917 // first time here. Set profile type.
2918 __ str(tmp, mdo_addr);
2919 #ifdef ASSERT
2920 __ andr(tmp, tmp, TypeEntries::type_mask);
2921 __ verify_klass_ptr(tmp);
2922 #endif
2923 } else {
2924 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2925 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2926
2927 __ ldr(tmp, mdo_addr);
2928 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2929
2930 __ orr(tmp, tmp, TypeEntries::type_unknown);
2931 __ str(tmp, mdo_addr);
2932 // FIXME: Write barrier needed here?
2933 }
2934 }
2935
2936 __ bind(next);
2937 }
2938 COMMENT("} emit_profile_type");
2939 }
2940
2941 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
2942 Register obj = op->obj()->as_register();
2943 Register tmp = op->tmp()->as_pointer_register();
2944 bool not_null = op->not_null();
2945 int flag = op->flag();
2946
2947 Label not_inline_type;
2948 if (!not_null) {
2949 __ cbz(obj, not_inline_type);
2950 }
2951
2952 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
2953
2954 Address mdo_addr = as_Address(op->mdp()->as_address_ptr(), rscratch2);
2955 __ ldrb(rscratch1, mdo_addr);
2956 __ orr(rscratch1, rscratch1, flag);
2957 __ strb(rscratch1, mdo_addr);
2958
2959 __ bind(not_inline_type);
2960 }
2961
2962 void LIR_Assembler::align_backward_branch_target() {
2963 }
2964
2965
2966 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2967 // tmp must be unused
2968 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2969
2970 if (left->is_single_cpu()) {
2971 assert(dest->is_single_cpu(), "expect single result reg");
2972 __ negw(dest->as_register(), left->as_register());
2973 } else if (left->is_double_cpu()) {
2974 assert(dest->is_double_cpu(), "expect double result reg");
2975 __ neg(dest->as_register_lo(), left->as_register_lo());
2976 } else if (left->is_single_fpu()) {
2977 assert(dest->is_single_fpu(), "expect single float result reg");
2978 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2979 } else {
2980 assert(left->is_double_fpu(), "expect double float operand reg");
2981 assert(dest->is_double_fpu(), "expect double float result reg");
2982 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2983 }
2984 }
2985
2986
2987 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2988 if (patch_code != lir_patch_none) {
2989 deoptimize_trap(info);
2990 return;
2991 }
2992
2993 __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
2994 }
2995
2996
2997 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2998 assert(!tmp->is_valid(), "don't need temporary");
2999
3000 CodeBlob *cb = CodeCache::find_blob(dest);
3001 if (cb) {
3002 __ far_call(RuntimeAddress(dest));
3003 } else {
3004 __ mov(rscratch1, RuntimeAddress(dest));
3005 __ blr(rscratch1);
3006 }
3007
3008 if (info != nullptr) {
3009 add_call_info_here(info);
3010 }
3011 __ post_call_nop();
3012 }
3013
3014 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3015 if (src->is_address()) {
3016 mem2reg(src, dest, type, lir_patch_none, info, /*wide*/false, /*is_volatile*/true);
3017 } else if (dest->is_address()) {
3018 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
3019 } else {
3020 ShouldNotReachHere();
3021 }
3022 }
3023
3024 #ifdef ASSERT
3025 // emit run-time assertion
3026 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3027 assert(op->code() == lir_assert, "must be");
3028
3029 if (op->in_opr1()->is_valid()) {
3030 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3031 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3032 } else {
3033 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3034 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3035 }
3036
3037 Label ok;
3038 if (op->condition() != lir_cond_always) {
3039 Assembler::Condition acond = Assembler::AL;
3040 switch (op->condition()) {
3041 case lir_cond_equal: acond = Assembler::EQ; break;
3042 case lir_cond_notEqual: acond = Assembler::NE; break;
3043 case lir_cond_less: acond = Assembler::LT; break;
3044 case lir_cond_lessEqual: acond = Assembler::LE; break;
3045 case lir_cond_greaterEqual: acond = Assembler::GE; break;
3046 case lir_cond_greater: acond = Assembler::GT; break;
3047 case lir_cond_belowEqual: acond = Assembler::LS; break;
3048 case lir_cond_aboveEqual: acond = Assembler::HS; break;
3049 default: ShouldNotReachHere();
3050 }
3051 __ br(acond, ok);
3052 }
3053 if (op->halt()) {
3054 const char* str = __ code_string(op->msg());
3055 __ stop(str);
3056 } else {
3057 breakpoint();
3058 }
3059 __ bind(ok);
3060 }
3061 #endif
3062
3063 #ifndef PRODUCT
3064 #define COMMENT(x) do { __ block_comment(x); } while (0)
3065 #else
3066 #define COMMENT(x)
3067 #endif
3068
3069 void LIR_Assembler::membar() {
3070 COMMENT("membar");
3071 __ membar(MacroAssembler::AnyAny);
3072 }
3073
3074 void LIR_Assembler::membar_acquire() {
3075 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
3076 }
3077
3078 void LIR_Assembler::membar_release() {
3079 __ membar(Assembler::LoadStore|Assembler::StoreStore);
3080 }
3081
3082 void LIR_Assembler::membar_loadload() {
3083 __ membar(Assembler::LoadLoad);
3084 }
3085
3086 void LIR_Assembler::membar_storestore() {
3087 __ membar(MacroAssembler::StoreStore);
3088 }
3089
3090 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3091
3092 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3093
3094 void LIR_Assembler::on_spin_wait() {
3095 __ spin_wait();
3096 }
3097
3098 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3099 __ mov(result_reg->as_register(), rthread);
3100 }
3101
3102 void LIR_Assembler::check_orig_pc() {
3103 __ ldr(rscratch2, frame_map()->address_for_orig_pc_addr());
3104 __ cmp(rscratch2, (u1)NULL_WORD);
3105 }
3106
3107 void LIR_Assembler::peephole(LIR_List *lir) {
3108 #if 0
3109 if (tableswitch_count >= max_tableswitches)
3110 return;
3111
3112 /*
3113 This finite-state automaton recognizes sequences of compare-and-
3114 branch instructions. We will turn them into a tableswitch. You
3115 could argue that C1 really shouldn't be doing this sort of
3116 optimization, but without it the code is really horrible.
3117 */
3118
3119 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3120 int first_key, last_key = -2147483648;
3121 int next_key = 0;
3122 int start_insn = -1;
3123 int last_insn = -1;
3124 Register reg = noreg;
3125 LIR_Opr reg_opr;
3126 state = start_s;
3127
3128 LIR_OpList* inst = lir->instructions_list();
3129 for (int i = 0; i < inst->length(); i++) {
3130 LIR_Op* op = inst->at(i);
3131 switch (state) {
3132 case start_s:
3133 first_key = -1;
3134 start_insn = i;
3135 switch (op->code()) {
3136 case lir_cmp:
3137 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3138 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3139 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3140 && opr2->is_constant()
3141 && opr2->type() == T_INT) {
3142 reg_opr = opr1;
3143 reg = opr1->as_register();
3144 first_key = opr2->as_constant_ptr()->as_jint();
3145 next_key = first_key + 1;
3146 state = cmp_s;
3147 goto next_state;
3148 }
3149 break;
3150 }
3151 break;
3152 case cmp_s:
3153 switch (op->code()) {
3154 case lir_branch:
3155 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3156 state = beq_s;
3157 last_insn = i;
3158 goto next_state;
3159 }
3160 }
3161 state = start_s;
3162 break;
3163 case beq_s:
3164 switch (op->code()) {
3165 case lir_cmp: {
3166 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3167 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3168 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3169 && opr1->as_register() == reg
3170 && opr2->is_constant()
3171 && opr2->type() == T_INT
3172 && opr2->as_constant_ptr()->as_jint() == next_key) {
3173 last_key = next_key;
3174 next_key++;
3175 state = cmp_s;
3176 goto next_state;
3177 }
3178 }
3179 }
3180 last_key = next_key;
3181 state = start_s;
3182 break;
3183 default:
3184 assert(false, "impossible state");
3185 }
3186 if (state == start_s) {
3187 if (first_key < last_key - 5L && reg != noreg) {
3188 {
3189 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3190 // reg->encoding(),
3191 // start_insn, first_key, last_key);
3192 // for (int i = 0; i < inst->length(); i++) {
3193 // inst->at(i)->print();
3194 // tty->print("\n");
3195 // }
3196 // tty->print("\n");
3197 }
3198
3199 struct tableswitch *sw = &switches[tableswitch_count];
3200 sw->_insn_index = start_insn, sw->_first_key = first_key,
3201 sw->_last_key = last_key, sw->_reg = reg;
3202 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3203 {
3204 // Insert the new table of branches
3205 int offset = last_insn;
3206 for (int n = first_key; n < last_key; n++) {
3207 inst->insert_before
3208 (last_insn + 1,
3209 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3210 inst->at(offset)->as_OpBranch()->label()));
3211 offset -= 2, i++;
3212 }
3213 }
3214 // Delete all the old compare-and-branch instructions
3215 for (int n = first_key; n < last_key; n++) {
3216 inst->remove_at(start_insn);
3217 inst->remove_at(start_insn);
3218 }
3219 // Insert the tableswitch instruction
3220 inst->insert_before(start_insn,
3221 new LIR_Op2(lir_cmp, lir_cond_always,
3222 LIR_OprFact::intConst(tableswitch_count),
3223 reg_opr));
3224 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3225 tableswitch_count++;
3226 }
3227 reg = noreg;
3228 last_key = -2147483648;
3229 }
3230 next_state:
3231 ;
3232 }
3233 #endif
3234 }
3235
3236 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3237 Address addr = as_Address(src->as_address_ptr());
3238 BasicType type = src->type();
3239 bool is_oop = is_reference_type(type);
3240
3241 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3242 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3243
3244 switch(type) {
3245 case T_INT:
3246 xchg = &MacroAssembler::atomic_xchgalw;
3247 add = &MacroAssembler::atomic_addalw;
3248 break;
3249 case T_LONG:
3250 xchg = &MacroAssembler::atomic_xchgal;
3251 add = &MacroAssembler::atomic_addal;
3252 break;
3253 case T_OBJECT:
3254 case T_ARRAY:
3255 if (UseCompressedOops) {
3256 xchg = &MacroAssembler::atomic_xchgalw;
3257 add = &MacroAssembler::atomic_addalw;
3258 } else {
3259 xchg = &MacroAssembler::atomic_xchgal;
3260 add = &MacroAssembler::atomic_addal;
3261 }
3262 break;
3263 default:
3264 ShouldNotReachHere();
3265 xchg = &MacroAssembler::atomic_xchgal;
3266 add = &MacroAssembler::atomic_addal; // unreachable
3267 }
3268
3269 switch (code) {
3270 case lir_xadd:
3271 {
3272 RegisterOrConstant inc;
3273 Register tmp = as_reg(tmp_op);
3274 Register dst = as_reg(dest);
3275 if (data->is_constant()) {
3276 inc = RegisterOrConstant(as_long(data));
3277 assert_different_registers(dst, addr.base(), tmp,
3278 rscratch1, rscratch2);
3279 } else {
3280 inc = RegisterOrConstant(as_reg(data));
3281 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3282 rscratch1, rscratch2);
3283 }
3284 __ lea(tmp, addr);
3285 (_masm->*add)(dst, inc, tmp);
3286 break;
3287 }
3288 case lir_xchg:
3289 {
3290 Register tmp = tmp_op->as_register();
3291 Register obj = as_reg(data);
3292 Register dst = as_reg(dest);
3293 if (is_oop && UseCompressedOops) {
3294 __ encode_heap_oop(rscratch2, obj);
3295 obj = rscratch2;
3296 }
3297 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3298 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3299 __ lea(tmp, addr);
3300 (_masm->*xchg)(dst, obj, tmp);
3301 if (is_oop && UseCompressedOops) {
3302 __ decode_heap_oop(dst);
3303 }
3304 }
3305 break;
3306 default:
3307 ShouldNotReachHere();
3308 }
3309 }
3310
3311 #undef __