1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInlineKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "code/compiledIC.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_aarch64.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "oops/oop.inline.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "runtime/stubRoutines.hpp"
46 #include "utilities/powerOfTwo.hpp"
47 #include "vmreg_aarch64.inline.hpp"
48
49
50 #ifndef PRODUCT
51 #define COMMENT(x) do { __ block_comment(x); } while (0)
52 #else
53 #define COMMENT(x)
54 #endif
55
56 NEEDS_CLEANUP // remove this definitions ?
57 const Register SYNC_header = r0; // synchronization header
58 const Register SHIFT_count = r0; // where count for shift operations must be
59
60 #define __ _masm->
61
62
63 static void select_different_registers(Register preserve,
64 Register extra,
65 Register &tmp1,
66 Register &tmp2) {
67 if (tmp1 == preserve) {
68 assert_different_registers(tmp1, tmp2, extra);
69 tmp1 = extra;
70 } else if (tmp2 == preserve) {
71 assert_different_registers(tmp1, tmp2, extra);
72 tmp2 = extra;
73 }
74 assert_different_registers(preserve, tmp1, tmp2);
75 }
76
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2,
83 Register &tmp3) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, tmp3, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, tmp3, extra);
89 tmp2 = extra;
90 } else if (tmp3 == preserve) {
91 assert_different_registers(tmp1, tmp2, tmp3, extra);
92 tmp3 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2, tmp3);
95 }
96
97
98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
99
100
101 LIR_Opr LIR_Assembler::receiverOpr() {
102 return FrameMap::receiver_opr;
103 }
104
105 LIR_Opr LIR_Assembler::osrBufferPointer() {
106 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
107 }
108
109 //--------------fpu register translations-----------------------
110
111
112 address LIR_Assembler::float_constant(float f) {
113 address const_addr = __ float_constant(f);
114 if (const_addr == nullptr) {
115 bailout("const section overflow");
116 return __ code()->consts()->start();
117 } else {
118 return const_addr;
119 }
120 }
121
122
123 address LIR_Assembler::double_constant(double d) {
124 address const_addr = __ double_constant(d);
125 if (const_addr == nullptr) {
126 bailout("const section overflow");
127 return __ code()->consts()->start();
128 } else {
129 return const_addr;
130 }
131 }
132
133 address LIR_Assembler::int_constant(jlong n) {
134 address const_addr = __ long_constant(n);
135 if (const_addr == nullptr) {
136 bailout("const section overflow");
137 return __ code()->consts()->start();
138 } else {
139 return const_addr;
140 }
141 }
142
143 void LIR_Assembler::breakpoint() { Unimplemented(); }
144
145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
146
147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
148
149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
150 //-------------------------------------------
151
152 static Register as_reg(LIR_Opr op) {
153 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
154 }
155
156 static jlong as_long(LIR_Opr data) {
157 jlong result;
158 switch (data->type()) {
159 case T_INT:
160 result = (data->as_jint());
161 break;
162 case T_LONG:
163 result = (data->as_jlong());
164 break;
165 default:
166 ShouldNotReachHere();
167 result = 0; // unreachable
168 }
169 return result;
170 }
171
172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
173 Register base = addr->base()->as_pointer_register();
174 LIR_Opr opr = addr->index();
175 if (opr->is_cpu_register()) {
176 Register index;
177 if (opr->is_single_cpu())
178 index = opr->as_register();
179 else
180 index = opr->as_register_lo();
181 assert(addr->disp() == 0, "must be");
182 switch(opr->type()) {
183 case T_INT:
184 return Address(base, index, Address::sxtw(addr->scale()));
185 case T_LONG:
186 return Address(base, index, Address::lsl(addr->scale()));
187 default:
188 ShouldNotReachHere();
189 }
190 } else {
191 assert(addr->scale() == 0,
192 "expected for immediate operand, was: %d", addr->scale());
193 ptrdiff_t offset = ptrdiff_t(addr->disp());
194 // NOTE: Does not handle any 16 byte vector access.
195 const uint type_size = type2aelembytes(addr->type(), true);
196 return __ legitimize_address(Address(base, offset), type_size, tmp);
197 }
198 return Address();
199 }
200
201 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
202 ShouldNotReachHere();
203 return Address();
204 }
205
206 Address LIR_Assembler::as_Address(LIR_Address* addr) {
207 return as_Address(addr, rscratch1);
208 }
209
210 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
211 return as_Address(addr, rscratch1); // Ouch
212 // FIXME: This needs to be much more clever. See x86.
213 }
214
215 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
216 // not encodable as a base + (immediate) offset, generate an explicit address
217 // calculation to hold the address in a temporary register.
218 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
219 precond(size == 4 || size == 8);
220 Address addr = frame_map()->address_for_slot(index, adjust);
221 precond(addr.getMode() == Address::base_plus_offset);
222 precond(addr.base() == sp);
223 precond(addr.offset() > 0);
224 uint mask = size - 1;
225 assert((addr.offset() & mask) == 0, "scaled offsets only");
226 return __ legitimize_address(addr, size, tmp);
227 }
228
229 void LIR_Assembler::osr_entry() {
230 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
231 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
232 ValueStack* entry_state = osr_entry->state();
233 int number_of_locks = entry_state->locks_size();
234
235 // we jump here if osr happens with the interpreter
236 // state set up to continue at the beginning of the
237 // loop that triggered osr - in particular, we have
238 // the following registers setup:
239 //
240 // r2: osr buffer
241 //
242
243 // build frame
244 ciMethod* m = compilation()->method();
245 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
246
247 // OSR buffer is
248 //
249 // locals[nlocals-1..0]
250 // monitors[0..number_of_locks]
251 //
252 // locals is a direct copy of the interpreter frame so in the osr buffer
253 // so first slot in the local array is the last local from the interpreter
254 // and last slot is local[0] (receiver) from the interpreter
255 //
256 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
257 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
258 // in the interpreter frame (the method lock if a sync method)
259
260 // Initialize monitors in the compiled activation.
261 // r2: pointer to osr buffer
262 //
263 // All other registers are dead at this point and the locals will be
264 // copied into place by code emitted in the IR.
265
266 Register OSR_buf = osrBufferPointer()->as_pointer_register();
267 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
268 int monitor_offset = BytesPerWord * method()->max_locals() +
269 (2 * BytesPerWord) * (number_of_locks - 1);
270 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
271 // the OSR buffer using 2 word entries: first the lock and then
272 // the oop.
273 for (int i = 0; i < number_of_locks; i++) {
274 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
275 #ifdef ASSERT
276 // verify the interpreter's monitor has a non-null object
277 {
278 Label L;
279 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
280 __ cbnz(rscratch1, L);
281 __ stop("locked object is null");
282 __ bind(L);
283 }
284 #endif
285 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
286 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
287 __ str(r19, frame_map()->address_for_monitor_lock(i));
288 __ str(r20, frame_map()->address_for_monitor_object(i));
289 }
290 }
291 }
292
293
294 // inline cache check; done before the frame is built.
295 int LIR_Assembler::check_icache() {
296 return __ ic_check(CodeEntryAlignment);
297 }
298
299 void LIR_Assembler::clinit_barrier(ciMethod* method) {
300 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
301 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
302
303 Label L_skip_barrier;
304
305 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
306 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
307 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
308 __ bind(L_skip_barrier);
309 }
310
311 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
312 if (o == nullptr) {
313 __ mov(reg, zr);
314 } else {
315 __ movoop(reg, o);
316 }
317 }
318
319 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
320 address target = nullptr;
321 relocInfo::relocType reloc_type = relocInfo::none;
322
323 switch (patching_id(info)) {
324 case PatchingStub::access_field_id:
325 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
326 reloc_type = relocInfo::section_word_type;
327 break;
328 case PatchingStub::load_klass_id:
329 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
330 reloc_type = relocInfo::metadata_type;
331 break;
332 case PatchingStub::load_mirror_id:
333 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
334 reloc_type = relocInfo::oop_type;
335 break;
336 case PatchingStub::load_appendix_id:
337 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
338 reloc_type = relocInfo::oop_type;
339 break;
340 default: ShouldNotReachHere();
341 }
342
343 __ far_call(RuntimeAddress(target));
344 add_call_info_here(info);
345 }
346
347 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
348 deoptimize_trap(info);
349 }
350
351
352 // This specifies the rsp decrement needed to build the frame
353 int LIR_Assembler::initial_frame_size_in_bytes() const {
354 // if rounding, must let FrameMap know!
355
356 return in_bytes(frame_map()->framesize_in_bytes());
357 }
358
359
360 int LIR_Assembler::emit_exception_handler() {
361 // generate code for exception handler
362 address handler_base = __ start_a_stub(exception_handler_size());
363 if (handler_base == nullptr) {
364 // not enough space left for the handler
365 bailout("exception handler overflow");
366 return -1;
367 }
368
369 int offset = code_offset();
370
371 // the exception oop and pc are in r0, and r3
372 // no other registers need to be preserved, so invalidate them
373 __ invalidate_registers(false, true, true, false, true, true);
374
375 // check that there is really an exception
376 __ verify_not_null_oop(r0);
377
378 // search an exception handler (r0: exception oop, r3: throwing pc)
379 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
380 __ should_not_reach_here();
381 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
382 __ end_a_stub();
383
384 return offset;
385 }
386
387
388 // Emit the code to remove the frame from the stack in the exception
389 // unwind path.
390 int LIR_Assembler::emit_unwind_handler() {
391 #ifndef PRODUCT
392 if (CommentedAssembly) {
393 _masm->block_comment("Unwind handler");
394 }
395 #endif
396
397 int offset = code_offset();
398
399 // Fetch the exception from TLS and clear out exception related thread state
400 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
401 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
403
404 __ bind(_unwind_handler_entry);
405 __ verify_not_null_oop(r0);
406 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
407 __ mov(r19, r0); // Preserve the exception
408 }
409
410 // Perform needed unlocking
411 MonitorExitStub* stub = nullptr;
412 if (method()->is_synchronized()) {
413 monitor_address(0, FrameMap::r0_opr);
414 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
415 if (LockingMode == LM_MONITOR) {
416 __ b(*stub->entry());
417 } else {
418 __ unlock_object(r5, r4, r0, r6, *stub->entry());
419 }
420 __ bind(*stub->continuation());
421 }
422
423 if (compilation()->env()->dtrace_method_probes()) {
424 __ mov(c_rarg0, rthread);
425 __ mov_metadata(c_rarg1, method()->constant_encoding());
426 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
427 }
428
429 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
430 __ mov(r0, r19); // Restore the exception
431 }
432
433 // remove the activation and dispatch to the unwind handler
434 __ block_comment("remove_frame and dispatch to the unwind handler");
435 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
436 __ far_jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
437
438 // Emit the slow path assembly
439 if (stub != nullptr) {
440 stub->emit_code(this);
441 }
442
443 return offset;
444 }
445
446
447 int LIR_Assembler::emit_deopt_handler() {
448 // generate code for exception handler
449 address handler_base = __ start_a_stub(deopt_handler_size());
450 if (handler_base == nullptr) {
451 // not enough space left for the handler
452 bailout("deopt handler overflow");
453 return -1;
454 }
455
456 int offset = code_offset();
457
458 __ adr(lr, pc());
459 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
460 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
461 __ end_a_stub();
462
463 return offset;
464 }
465
466 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
467 _masm->code_section()->relocate(adr, relocInfo::poll_type);
468 int pc_offset = code_offset();
469 flush_debug_info(pc_offset);
470 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
471 if (info->exception_handlers() != nullptr) {
472 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
473 }
474 }
475
476 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
477 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
478
479 if (InlineTypeReturnedAsFields) {
480 // Check if we are returning an non-null inline type and load its fields into registers
481 ciType* return_type = compilation()->method()->return_type();
482 if (return_type->is_inlinetype()) {
483 ciInlineKlass* vk = return_type->as_inline_klass();
484 if (vk->can_be_returned_as_fields()) {
485 address unpack_handler = vk->unpack_handler();
486 assert(unpack_handler != nullptr, "must be");
487 __ far_call(RuntimeAddress(unpack_handler));
488 }
489 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) {
490 Label skip;
491 Label not_null;
492 __ cbnz(r0, not_null);
493 // Returned value is null, zero all return registers because they may belong to oop fields
494 __ mov(j_rarg1, zr);
495 __ mov(j_rarg2, zr);
496 __ mov(j_rarg3, zr);
497 __ mov(j_rarg4, zr);
498 __ mov(j_rarg5, zr);
499 __ mov(j_rarg6, zr);
500 __ mov(j_rarg7, zr);
501 __ b(skip);
502 __ bind(not_null);
503
504 // Check if we are returning an non-null inline type and load its fields into registers
505 __ test_oop_is_not_inline_type(r0, rscratch2, skip, /* can_be_null= */ false);
506
507 // Load fields from a buffered value with an inline class specific handler
508 __ load_klass(rscratch1 /*dst*/, r0 /*src*/);
509 __ ldr(rscratch1, Address(rscratch1, InstanceKlass::adr_inlineklass_fixed_block_offset()));
510 __ ldr(rscratch1, Address(rscratch1, InlineKlass::unpack_handler_offset()));
511 // Unpack handler can be null if inline type is not scalarizable in returns
512 __ cbz(rscratch1, skip);
513 __ blr(rscratch1);
514
515 __ bind(skip);
516 }
517 // At this point, r0 points to the value object (for interpreter or C1 caller).
518 // The fields of the object are copied into registers (for C2 caller).
519 }
520
521 // Pop the stack before the safepoint code
522 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
523
524 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
525 __ reserved_stack_check();
526 }
527
528 code_stub->set_safepoint_offset(__ offset());
529 __ relocate(relocInfo::poll_return_type);
530 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
531 __ ret(lr);
532 }
533
534 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
535 return (__ store_inline_type_fields_to_buf(vk, false));
536 }
537
538 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
539 guarantee(info != nullptr, "Shouldn't be null");
540 __ get_polling_page(rscratch1, relocInfo::poll_type);
541 add_debug_info_for_branch(info); // This isn't just debug info:
542 // it's the oop map
543 __ read_polling_page(rscratch1, relocInfo::poll_type);
544 return __ offset();
545 }
546
547
548 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
549 if (from_reg == r31_sp)
550 from_reg = sp;
551 if (to_reg == r31_sp)
552 to_reg = sp;
553 __ mov(to_reg, from_reg);
554 }
555
556 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
557
558
559 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
560 assert(src->is_constant(), "should not call otherwise");
561 assert(dest->is_register(), "should not call otherwise");
562 LIR_Const* c = src->as_constant_ptr();
563
564 switch (c->type()) {
565 case T_INT: {
566 assert(patch_code == lir_patch_none, "no patching handled here");
567 __ movw(dest->as_register(), c->as_jint());
568 break;
569 }
570
571 case T_ADDRESS: {
572 assert(patch_code == lir_patch_none, "no patching handled here");
573 __ mov(dest->as_register(), c->as_jint());
574 break;
575 }
576
577 case T_LONG: {
578 assert(patch_code == lir_patch_none, "no patching handled here");
579 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
580 break;
581 }
582
583 case T_OBJECT: {
584 if (patch_code != lir_patch_none) {
585 jobject2reg_with_patching(dest->as_register(), info);
586 } else {
587 jobject2reg(c->as_jobject(), dest->as_register());
588 }
589 break;
590 }
591
592 case T_METADATA: {
593 if (patch_code != lir_patch_none) {
594 klass2reg_with_patching(dest->as_register(), info);
595 } else {
596 __ mov_metadata(dest->as_register(), c->as_metadata());
597 }
598 break;
599 }
600
601 case T_FLOAT: {
602 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
603 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
604 } else {
605 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
606 __ ldrs(dest->as_float_reg(), Address(rscratch1));
607 }
608 break;
609 }
610
611 case T_DOUBLE: {
612 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
613 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
614 } else {
615 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
616 __ ldrd(dest->as_double_reg(), Address(rscratch1));
617 }
618 break;
619 }
620
621 default:
622 ShouldNotReachHere();
623 }
624 }
625
626 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
627 LIR_Const* c = src->as_constant_ptr();
628 switch (c->type()) {
629 case T_OBJECT:
630 {
631 if (! c->as_jobject())
632 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
633 else {
634 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
635 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
636 }
637 }
638 break;
639 case T_ADDRESS:
640 {
641 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
642 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
643 }
644 case T_INT:
645 case T_FLOAT:
646 {
647 Register reg = zr;
648 if (c->as_jint_bits() == 0)
649 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
650 else {
651 __ movw(rscratch1, c->as_jint_bits());
652 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
653 }
654 }
655 break;
656 case T_LONG:
657 case T_DOUBLE:
658 {
659 Register reg = zr;
660 if (c->as_jlong_bits() == 0)
661 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
662 lo_word_offset_in_bytes));
663 else {
664 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
665 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
666 lo_word_offset_in_bytes));
667 }
668 }
669 break;
670 default:
671 ShouldNotReachHere();
672 }
673 }
674
675 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
676 assert(src->is_constant(), "should not call otherwise");
677 LIR_Const* c = src->as_constant_ptr();
678 LIR_Address* to_addr = dest->as_address_ptr();
679
680 void (Assembler::* insn)(Register Rt, const Address &adr);
681
682 switch (type) {
683 case T_ADDRESS:
684 assert(c->as_jint() == 0, "should be");
685 insn = &Assembler::str;
686 break;
687 case T_LONG:
688 assert(c->as_jlong() == 0, "should be");
689 insn = &Assembler::str;
690 break;
691 case T_INT:
692 assert(c->as_jint() == 0, "should be");
693 insn = &Assembler::strw;
694 break;
695 case T_OBJECT:
696 case T_ARRAY:
697 // Non-null case is not handled on aarch64 but handled on x86
698 // FIXME: do we need to add it here?
699 assert(c->as_jobject() == nullptr, "should be");
700 if (UseCompressedOops && !wide) {
701 insn = &Assembler::strw;
702 } else {
703 insn = &Assembler::str;
704 }
705 break;
706 case T_CHAR:
707 case T_SHORT:
708 assert(c->as_jint() == 0, "should be");
709 insn = &Assembler::strh;
710 break;
711 case T_BOOLEAN:
712 case T_BYTE:
713 assert(c->as_jint() == 0, "should be");
714 insn = &Assembler::strb;
715 break;
716 default:
717 ShouldNotReachHere();
718 insn = &Assembler::str; // unreachable
719 }
720
721 if (info) add_debug_info_for_null_check_here(info);
722 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
723 }
724
725 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
726 assert(src->is_register(), "should not call otherwise");
727 assert(dest->is_register(), "should not call otherwise");
728
729 // move between cpu-registers
730 if (dest->is_single_cpu()) {
731 if (src->type() == T_LONG) {
732 // Can do LONG -> OBJECT
733 move_regs(src->as_register_lo(), dest->as_register());
734 return;
735 }
736 assert(src->is_single_cpu(), "must match");
737 if (src->type() == T_OBJECT) {
738 __ verify_oop(src->as_register());
739 }
740 move_regs(src->as_register(), dest->as_register());
741
742 } else if (dest->is_double_cpu()) {
743 if (is_reference_type(src->type())) {
744 // Surprising to me but we can see move of a long to t_object
745 __ verify_oop(src->as_register());
746 move_regs(src->as_register(), dest->as_register_lo());
747 return;
748 }
749 assert(src->is_double_cpu(), "must match");
750 Register f_lo = src->as_register_lo();
751 Register f_hi = src->as_register_hi();
752 Register t_lo = dest->as_register_lo();
753 Register t_hi = dest->as_register_hi();
754 assert(f_hi == f_lo, "must be same");
755 assert(t_hi == t_lo, "must be same");
756 move_regs(f_lo, t_lo);
757
758 } else if (dest->is_single_fpu()) {
759 __ fmovs(dest->as_float_reg(), src->as_float_reg());
760
761 } else if (dest->is_double_fpu()) {
762 __ fmovd(dest->as_double_reg(), src->as_double_reg());
763
764 } else {
765 ShouldNotReachHere();
766 }
767 }
768
769 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
770 precond(src->is_register() && dest->is_stack());
771
772 uint const c_sz32 = sizeof(uint32_t);
773 uint const c_sz64 = sizeof(uint64_t);
774
775 if (src->is_single_cpu()) {
776 int index = dest->single_stack_ix();
777 if (is_reference_type(type)) {
778 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
779 __ verify_oop(src->as_register());
780 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
781 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
782 } else {
783 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
784 }
785
786 } else if (src->is_double_cpu()) {
787 int index = dest->double_stack_ix();
788 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
789 __ str(src->as_register_lo(), dest_addr_LO);
790
791 } else if (src->is_single_fpu()) {
792 int index = dest->single_stack_ix();
793 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
794
795 } else if (src->is_double_fpu()) {
796 int index = dest->double_stack_ix();
797 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
798
799 } else {
800 ShouldNotReachHere();
801 }
802 }
803
804
805 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
806 LIR_Address* to_addr = dest->as_address_ptr();
807 PatchingStub* patch = nullptr;
808 Register compressed_src = rscratch1;
809
810 if (patch_code != lir_patch_none) {
811 deoptimize_trap(info);
812 return;
813 }
814
815 if (is_reference_type(type)) {
816 __ verify_oop(src->as_register());
817
818 if (UseCompressedOops && !wide) {
819 __ encode_heap_oop(compressed_src, src->as_register());
820 } else {
821 compressed_src = src->as_register();
822 }
823 }
824
825 int null_check_here = code_offset();
826 switch (type) {
827 case T_FLOAT: {
828 __ strs(src->as_float_reg(), as_Address(to_addr));
829 break;
830 }
831
832 case T_DOUBLE: {
833 __ strd(src->as_double_reg(), as_Address(to_addr));
834 break;
835 }
836
837 case T_ARRAY: // fall through
838 case T_OBJECT: // fall through
839 if (UseCompressedOops && !wide) {
840 __ strw(compressed_src, as_Address(to_addr, rscratch2));
841 } else {
842 __ str(compressed_src, as_Address(to_addr));
843 }
844 break;
845 case T_METADATA:
846 // We get here to store a method pointer to the stack to pass to
847 // a dtrace runtime call. This can't work on 64 bit with
848 // compressed klass ptrs: T_METADATA can be a compressed klass
849 // ptr or a 64 bit method pointer.
850 ShouldNotReachHere();
851 __ str(src->as_register(), as_Address(to_addr));
852 break;
853 case T_ADDRESS:
854 __ str(src->as_register(), as_Address(to_addr));
855 break;
856 case T_INT:
857 __ strw(src->as_register(), as_Address(to_addr));
858 break;
859
860 case T_LONG: {
861 __ str(src->as_register_lo(), as_Address_lo(to_addr));
862 break;
863 }
864
865 case T_BYTE: // fall through
866 case T_BOOLEAN: {
867 __ strb(src->as_register(), as_Address(to_addr));
868 break;
869 }
870
871 case T_CHAR: // fall through
872 case T_SHORT:
873 __ strh(src->as_register(), as_Address(to_addr));
874 break;
875
876 default:
877 ShouldNotReachHere();
878 }
879 if (info != nullptr) {
880 add_debug_info_for_null_check(null_check_here, info);
881 }
882 }
883
884
885 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
886 precond(src->is_stack() && dest->is_register());
887
888 uint const c_sz32 = sizeof(uint32_t);
889 uint const c_sz64 = sizeof(uint64_t);
890
891 if (dest->is_single_cpu()) {
892 int index = src->single_stack_ix();
893 if (is_reference_type(type)) {
894 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
895 __ verify_oop(dest->as_register());
896 } else if (type == T_METADATA || type == T_ADDRESS) {
897 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
898 } else {
899 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
900 }
901
902 } else if (dest->is_double_cpu()) {
903 int index = src->double_stack_ix();
904 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
905 __ ldr(dest->as_register_lo(), src_addr_LO);
906
907 } else if (dest->is_single_fpu()) {
908 int index = src->single_stack_ix();
909 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
910
911 } else if (dest->is_double_fpu()) {
912 int index = src->double_stack_ix();
913 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
914
915 } else {
916 ShouldNotReachHere();
917 }
918 }
919
920
921 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
922 address target = nullptr;
923 relocInfo::relocType reloc_type = relocInfo::none;
924
925 switch (patching_id(info)) {
926 case PatchingStub::access_field_id:
927 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
928 reloc_type = relocInfo::section_word_type;
929 break;
930 case PatchingStub::load_klass_id:
931 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
932 reloc_type = relocInfo::metadata_type;
933 break;
934 case PatchingStub::load_mirror_id:
935 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
936 reloc_type = relocInfo::oop_type;
937 break;
938 case PatchingStub::load_appendix_id:
939 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
940 reloc_type = relocInfo::oop_type;
941 break;
942 default: ShouldNotReachHere();
943 }
944
945 __ far_call(RuntimeAddress(target));
946 add_call_info_here(info);
947 }
948
949 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
950
951 LIR_Opr temp;
952 if (type == T_LONG || type == T_DOUBLE)
953 temp = FrameMap::rscratch1_long_opr;
954 else
955 temp = FrameMap::rscratch1_opr;
956
957 stack2reg(src, temp, src->type());
958 reg2stack(temp, dest, dest->type());
959 }
960
961
962 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
963 LIR_Address* addr = src->as_address_ptr();
964 LIR_Address* from_addr = src->as_address_ptr();
965
966 if (addr->base()->type() == T_OBJECT) {
967 __ verify_oop(addr->base()->as_pointer_register());
968 }
969
970 if (patch_code != lir_patch_none) {
971 deoptimize_trap(info);
972 return;
973 }
974
975 if (info != nullptr) {
976 add_debug_info_for_null_check_here(info);
977 }
978 int null_check_here = code_offset();
979 switch (type) {
980 case T_FLOAT: {
981 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
982 break;
983 }
984
985 case T_DOUBLE: {
986 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
987 break;
988 }
989
990 case T_ARRAY: // fall through
991 case T_OBJECT: // fall through
992 if (UseCompressedOops && !wide) {
993 __ ldrw(dest->as_register(), as_Address(from_addr));
994 } else {
995 __ ldr(dest->as_register(), as_Address(from_addr));
996 }
997 break;
998 case T_METADATA:
999 // We get here to store a method pointer to the stack to pass to
1000 // a dtrace runtime call. This can't work on 64 bit with
1001 // compressed klass ptrs: T_METADATA can be a compressed klass
1002 // ptr or a 64 bit method pointer.
1003 ShouldNotReachHere();
1004 __ ldr(dest->as_register(), as_Address(from_addr));
1005 break;
1006 case T_ADDRESS:
1007 __ ldr(dest->as_register(), as_Address(from_addr));
1008 break;
1009 case T_INT:
1010 __ ldrw(dest->as_register(), as_Address(from_addr));
1011 break;
1012
1013 case T_LONG: {
1014 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1015 break;
1016 }
1017
1018 case T_BYTE:
1019 __ ldrsb(dest->as_register(), as_Address(from_addr));
1020 break;
1021 case T_BOOLEAN: {
1022 __ ldrb(dest->as_register(), as_Address(from_addr));
1023 break;
1024 }
1025
1026 case T_CHAR:
1027 __ ldrh(dest->as_register(), as_Address(from_addr));
1028 break;
1029 case T_SHORT:
1030 __ ldrsh(dest->as_register(), as_Address(from_addr));
1031 break;
1032
1033 default:
1034 ShouldNotReachHere();
1035 }
1036
1037 if (is_reference_type(type)) {
1038 if (UseCompressedOops && !wide) {
1039 __ decode_heap_oop(dest->as_register());
1040 }
1041
1042 __ verify_oop(dest->as_register());
1043 }
1044 }
1045
1046 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
1047 assert(dst->is_cpu_register(), "must be");
1048 assert(dst->type() == src->type(), "must be");
1049
1050 if (src->is_cpu_register()) {
1051 reg2reg(src, dst);
1052 } else if (src->is_stack()) {
1053 stack2reg(src, dst, dst->type());
1054 } else if (src->is_constant()) {
1055 const2reg(src, dst, lir_patch_none, nullptr);
1056 } else {
1057 ShouldNotReachHere();
1058 }
1059 }
1060
1061 int LIR_Assembler::array_element_size(BasicType type) const {
1062 int elem_size = type2aelembytes(type);
1063 return exact_log2(elem_size);
1064 }
1065
1066
1067 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1068 switch (op->code()) {
1069 case lir_idiv:
1070 case lir_irem:
1071 arithmetic_idiv(op->code(),
1072 op->in_opr1(),
1073 op->in_opr2(),
1074 op->in_opr3(),
1075 op->result_opr(),
1076 op->info());
1077 break;
1078 case lir_fmad:
1079 __ fmaddd(op->result_opr()->as_double_reg(),
1080 op->in_opr1()->as_double_reg(),
1081 op->in_opr2()->as_double_reg(),
1082 op->in_opr3()->as_double_reg());
1083 break;
1084 case lir_fmaf:
1085 __ fmadds(op->result_opr()->as_float_reg(),
1086 op->in_opr1()->as_float_reg(),
1087 op->in_opr2()->as_float_reg(),
1088 op->in_opr3()->as_float_reg());
1089 break;
1090 default: ShouldNotReachHere(); break;
1091 }
1092 }
1093
1094 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1095 #ifdef ASSERT
1096 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1097 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1098 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1099 #endif
1100
1101 if (op->cond() == lir_cond_always) {
1102 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1103 __ b(*(op->label()));
1104 } else {
1105 Assembler::Condition acond;
1106 if (op->code() == lir_cond_float_branch) {
1107 bool is_unordered = (op->ublock() == op->block());
1108 // Assembler::EQ does not permit unordered branches, so we add
1109 // another branch here. Likewise, Assembler::NE does not permit
1110 // ordered branches.
1111 if ((is_unordered && op->cond() == lir_cond_equal)
1112 || (!is_unordered && op->cond() == lir_cond_notEqual))
1113 __ br(Assembler::VS, *(op->ublock()->label()));
1114 switch(op->cond()) {
1115 case lir_cond_equal: acond = Assembler::EQ; break;
1116 case lir_cond_notEqual: acond = Assembler::NE; break;
1117 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1118 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1119 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1120 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1121 default: ShouldNotReachHere();
1122 acond = Assembler::EQ; // unreachable
1123 }
1124 } else {
1125 switch (op->cond()) {
1126 case lir_cond_equal: acond = Assembler::EQ; break;
1127 case lir_cond_notEqual: acond = Assembler::NE; break;
1128 case lir_cond_less: acond = Assembler::LT; break;
1129 case lir_cond_lessEqual: acond = Assembler::LE; break;
1130 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1131 case lir_cond_greater: acond = Assembler::GT; break;
1132 case lir_cond_belowEqual: acond = Assembler::LS; break;
1133 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1134 default: ShouldNotReachHere();
1135 acond = Assembler::EQ; // unreachable
1136 }
1137 }
1138 __ br(acond,*(op->label()));
1139 }
1140 }
1141
1142
1143
1144 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1145 LIR_Opr src = op->in_opr();
1146 LIR_Opr dest = op->result_opr();
1147
1148 switch (op->bytecode()) {
1149 case Bytecodes::_i2f:
1150 {
1151 __ scvtfws(dest->as_float_reg(), src->as_register());
1152 break;
1153 }
1154 case Bytecodes::_i2d:
1155 {
1156 __ scvtfwd(dest->as_double_reg(), src->as_register());
1157 break;
1158 }
1159 case Bytecodes::_l2d:
1160 {
1161 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1162 break;
1163 }
1164 case Bytecodes::_l2f:
1165 {
1166 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1167 break;
1168 }
1169 case Bytecodes::_f2d:
1170 {
1171 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1172 break;
1173 }
1174 case Bytecodes::_d2f:
1175 {
1176 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1177 break;
1178 }
1179 case Bytecodes::_i2c:
1180 {
1181 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1182 break;
1183 }
1184 case Bytecodes::_i2l:
1185 {
1186 __ sxtw(dest->as_register_lo(), src->as_register());
1187 break;
1188 }
1189 case Bytecodes::_i2s:
1190 {
1191 __ sxth(dest->as_register(), src->as_register());
1192 break;
1193 }
1194 case Bytecodes::_i2b:
1195 {
1196 __ sxtb(dest->as_register(), src->as_register());
1197 break;
1198 }
1199 case Bytecodes::_l2i:
1200 {
1201 _masm->block_comment("FIXME: This could be a no-op");
1202 __ uxtw(dest->as_register(), src->as_register_lo());
1203 break;
1204 }
1205 case Bytecodes::_d2l:
1206 {
1207 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1208 break;
1209 }
1210 case Bytecodes::_f2i:
1211 {
1212 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1213 break;
1214 }
1215 case Bytecodes::_f2l:
1216 {
1217 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1218 break;
1219 }
1220 case Bytecodes::_d2i:
1221 {
1222 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1223 break;
1224 }
1225 default: ShouldNotReachHere();
1226 }
1227 }
1228
1229 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1230 if (op->init_check()) {
1231 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1232 __ ldarb(rscratch1, rscratch1);
1233 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1234 add_debug_info_for_null_check_here(op->stub()->info());
1235 __ br(Assembler::NE, *op->stub()->entry());
1236 }
1237 __ allocate_object(op->obj()->as_register(),
1238 op->tmp1()->as_register(),
1239 op->tmp2()->as_register(),
1240 op->header_size(),
1241 op->object_size(),
1242 op->klass()->as_register(),
1243 *op->stub()->entry());
1244 __ bind(*op->stub()->continuation());
1245 }
1246
1247 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1248 Register len = op->len()->as_register();
1249 __ uxtw(len, len);
1250
1251 if (UseSlowPath || op->is_null_free() ||
1252 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1253 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1254 __ b(*op->stub()->entry());
1255 } else {
1256 Register tmp1 = op->tmp1()->as_register();
1257 Register tmp2 = op->tmp2()->as_register();
1258 Register tmp3 = op->tmp3()->as_register();
1259 if (len == tmp1) {
1260 tmp1 = tmp3;
1261 } else if (len == tmp2) {
1262 tmp2 = tmp3;
1263 } else if (len == tmp3) {
1264 // everything is ok
1265 } else {
1266 __ mov(tmp3, len);
1267 }
1268 __ allocate_array(op->obj()->as_register(),
1269 len,
1270 tmp1,
1271 tmp2,
1272 arrayOopDesc::base_offset_in_bytes(op->type()),
1273 array_element_size(op->type()),
1274 op->klass()->as_register(),
1275 *op->stub()->entry(),
1276 op->zero_array());
1277 }
1278 __ bind(*op->stub()->continuation());
1279 }
1280
1281 void LIR_Assembler::type_profile_helper(Register mdo,
1282 ciMethodData *md, ciProfileData *data,
1283 Register recv, Label* update_done) {
1284
1285 // Given a profile data offset, generate an Address which points to
1286 // the corresponding slot in mdo->data().
1287 // Clobbers rscratch2.
1288 auto slot_at = [=](ByteSize offset) -> Address {
1289 return __ form_address(rscratch2, mdo,
1290 md->byte_offset_of_slot(data, offset),
1291 LogBytesPerWord);
1292 };
1293
1294 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1295 Label next_test;
1296 // See if the receiver is receiver[n].
1297 __ ldr(rscratch1, slot_at(ReceiverTypeData::receiver_offset(i)));
1298 __ cmp(recv, rscratch1);
1299 __ br(Assembler::NE, next_test);
1300 __ addptr(slot_at(ReceiverTypeData::receiver_count_offset(i)),
1301 DataLayout::counter_increment);
1302 __ b(*update_done);
1303 __ bind(next_test);
1304 }
1305
1306 // Didn't find receiver; find next empty slot and fill it in
1307 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1308 Label next_test;
1309 Address recv_addr(slot_at(ReceiverTypeData::receiver_offset(i)));
1310 __ ldr(rscratch1, recv_addr);
1311 __ cbnz(rscratch1, next_test);
1312 __ str(recv, recv_addr);
1313 __ mov(rscratch1, DataLayout::counter_increment);
1314 __ str(rscratch1, slot_at(ReceiverTypeData::receiver_count_offset(i)));
1315 __ b(*update_done);
1316 __ bind(next_test);
1317 }
1318 }
1319
1320 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1321 // we always need a stub for the failure case.
1322 CodeStub* stub = op->stub();
1323 Register obj = op->object()->as_register();
1324 Register k_RInfo = op->tmp1()->as_register();
1325 Register klass_RInfo = op->tmp2()->as_register();
1326 Register dst = op->result_opr()->as_register();
1327 ciKlass* k = op->klass();
1328 Register Rtmp1 = noreg;
1329
1330 // check if it needs to be profiled
1331 ciMethodData* md;
1332 ciProfileData* data;
1333
1334 const bool should_profile = op->should_profile();
1335
1336 if (should_profile) {
1337 ciMethod* method = op->profiled_method();
1338 assert(method != nullptr, "Should have method");
1339 int bci = op->profiled_bci();
1340 md = method->method_data_or_null();
1341 assert(md != nullptr, "Sanity");
1342 data = md->bci_to_data(bci);
1343 assert(data != nullptr, "need data for type check");
1344 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1345 }
1346 Label* success_target = success;
1347 Label* failure_target = failure;
1348
1349 if (obj == k_RInfo) {
1350 k_RInfo = dst;
1351 } else if (obj == klass_RInfo) {
1352 klass_RInfo = dst;
1353 }
1354 if (k->is_loaded() && !UseCompressedClassPointers) {
1355 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1356 } else {
1357 Rtmp1 = op->tmp3()->as_register();
1358 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1359 }
1360
1361 assert_different_registers(obj, k_RInfo, klass_RInfo);
1362
1363 if (op->need_null_check()) {
1364 if (should_profile) {
1365 Register mdo = klass_RInfo;
1366 __ mov_metadata(mdo, md->constant_encoding());
1367 Label not_null;
1368 __ cbnz(obj, not_null);
1369 // Object is null; update MDO and exit
1370 Address data_addr
1371 = __ form_address(rscratch2, mdo,
1372 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1373 0);
1374 __ ldrb(rscratch1, data_addr);
1375 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1376 __ strb(rscratch1, data_addr);
1377 __ b(*obj_is_null);
1378 __ bind(not_null);
1379
1380 Label update_done;
1381 Register recv = k_RInfo;
1382 __ load_klass(recv, obj);
1383 type_profile_helper(mdo, md, data, recv, &update_done);
1384 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1385 __ addptr(counter_addr, DataLayout::counter_increment);
1386
1387 __ bind(update_done);
1388 } else {
1389 __ cbz(obj, *obj_is_null);
1390 }
1391 }
1392
1393 if (!k->is_loaded()) {
1394 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1395 } else {
1396 __ mov_metadata(k_RInfo, k->constant_encoding());
1397 }
1398 __ verify_oop(obj);
1399
1400 if (op->fast_check()) {
1401 // get object class
1402 // not a safepoint as obj null check happens earlier
1403 __ load_klass(rscratch1, obj);
1404 __ cmp( rscratch1, k_RInfo);
1405
1406 __ br(Assembler::NE, *failure_target);
1407 // successful cast, fall through to profile or jump
1408 } else {
1409 // get object class
1410 // not a safepoint as obj null check happens earlier
1411 __ load_klass(klass_RInfo, obj);
1412 if (k->is_loaded()) {
1413 // See if we get an immediate positive hit
1414 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1415 __ cmp(k_RInfo, rscratch1);
1416 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1417 __ br(Assembler::NE, *failure_target);
1418 // successful cast, fall through to profile or jump
1419 } else {
1420 // See if we get an immediate positive hit
1421 __ br(Assembler::EQ, *success_target);
1422 // check for self
1423 __ cmp(klass_RInfo, k_RInfo);
1424 __ br(Assembler::EQ, *success_target);
1425
1426 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1427 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1428 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1429 // result is a boolean
1430 __ cbzw(klass_RInfo, *failure_target);
1431 // successful cast, fall through to profile or jump
1432 }
1433 } else {
1434 // perform the fast part of the checking logic
1435 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1436 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1437 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1438 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1439 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1440 // result is a boolean
1441 __ cbz(k_RInfo, *failure_target);
1442 // successful cast, fall through to profile or jump
1443 }
1444 }
1445 __ b(*success);
1446 }
1447
1448
1449 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1450 const bool should_profile = op->should_profile();
1451
1452 LIR_Code code = op->code();
1453 if (code == lir_store_check) {
1454 Register value = op->object()->as_register();
1455 Register array = op->array()->as_register();
1456 Register k_RInfo = op->tmp1()->as_register();
1457 Register klass_RInfo = op->tmp2()->as_register();
1458 Register Rtmp1 = op->tmp3()->as_register();
1459
1460 CodeStub* stub = op->stub();
1461
1462 // check if it needs to be profiled
1463 ciMethodData* md;
1464 ciProfileData* data;
1465
1466 if (should_profile) {
1467 ciMethod* method = op->profiled_method();
1468 assert(method != nullptr, "Should have method");
1469 int bci = op->profiled_bci();
1470 md = method->method_data_or_null();
1471 assert(md != nullptr, "Sanity");
1472 data = md->bci_to_data(bci);
1473 assert(data != nullptr, "need data for type check");
1474 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1475 }
1476 Label done;
1477 Label* success_target = &done;
1478 Label* failure_target = stub->entry();
1479
1480 if (should_profile) {
1481 Label not_null;
1482 Register mdo = klass_RInfo;
1483 __ mov_metadata(mdo, md->constant_encoding());
1484 __ cbnz(value, not_null);
1485 // Object is null; update MDO and exit
1486 Address data_addr
1487 = __ form_address(rscratch2, mdo,
1488 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1489 __ ldrb(rscratch1, data_addr);
1490 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1491 __ strb(rscratch1, data_addr);
1492 __ b(done);
1493 __ bind(not_null);
1494
1495 Label update_done;
1496 Register recv = k_RInfo;
1497 __ load_klass(recv, value);
1498 type_profile_helper(mdo, md, data, recv, &update_done);
1499 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1500 __ addptr(counter_addr, DataLayout::counter_increment);
1501 __ bind(update_done);
1502 } else {
1503 __ cbz(value, done);
1504 }
1505
1506 add_debug_info_for_null_check_here(op->info_for_exception());
1507 __ load_klass(k_RInfo, array);
1508 __ load_klass(klass_RInfo, value);
1509
1510 // get instance klass (it's already uncompressed)
1511 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1512 // perform the fast part of the checking logic
1513 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1514 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1515 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1516 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1517 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1518 // result is a boolean
1519 __ cbzw(k_RInfo, *failure_target);
1520 // fall through to the success case
1521
1522 __ bind(done);
1523 } else if (code == lir_checkcast) {
1524 Register obj = op->object()->as_register();
1525 Register dst = op->result_opr()->as_register();
1526 Label success;
1527 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1528 __ bind(success);
1529 if (dst != obj) {
1530 __ mov(dst, obj);
1531 }
1532 } else if (code == lir_instanceof) {
1533 Register obj = op->object()->as_register();
1534 Register dst = op->result_opr()->as_register();
1535 Label success, failure, done;
1536 emit_typecheck_helper(op, &success, &failure, &failure);
1537 __ bind(failure);
1538 __ mov(dst, zr);
1539 __ b(done);
1540 __ bind(success);
1541 __ mov(dst, 1);
1542 __ bind(done);
1543 } else {
1544 ShouldNotReachHere();
1545 }
1546 }
1547
1548 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1549 // We are loading/storing from/to an array that *may* be a flat array (the
1550 // declared type is Object[], abstract[], interface[] or VT.ref[]).
1551 // If this array is a flat array, take the slow path.
1552 __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1553 if (!op->value()->is_illegal()) {
1554 // The array is not a flat array, but it might be null-free. If we are storing
1555 // a null into a null-free array, take the slow path (which will throw NPE).
1556 Label skip;
1557 __ cbnz(op->value()->as_register(), skip);
1558 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1559 __ bind(skip);
1560 }
1561 }
1562
1563 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1564 // We are storing into an array that *may* be null-free (the declared type is
1565 // Object[], abstract[], interface[] or VT.ref[]).
1566 Label test_mark_word;
1567 Register tmp = op->tmp()->as_register();
1568 __ ldr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
1569 __ tst(tmp, markWord::unlocked_value);
1570 __ br(Assembler::NE, test_mark_word);
1571 __ load_prototype_header(tmp, op->array()->as_register());
1572 __ bind(test_mark_word);
1573 __ tst(tmp, markWord::null_free_array_bit_in_place);
1574 }
1575
1576 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1577 Label L_oops_equal;
1578 Label L_oops_not_equal;
1579 Label L_end;
1580
1581 Register left = op->left()->as_register();
1582 Register right = op->right()->as_register();
1583
1584 __ cmp(left, right);
1585 __ br(Assembler::EQ, L_oops_equal);
1586
1587 // (1) Null check -- if one of the operands is null, the other must not be null (because
1588 // the two references are not equal), so they are not substitutable,
1589 // FIXME: do null check only if the operand is nullable
1590 {
1591 __ cbz(left, L_oops_not_equal);
1592 __ cbz(right, L_oops_not_equal);
1593 }
1594
1595 ciKlass* left_klass = op->left_klass();
1596 ciKlass* right_klass = op->right_klass();
1597
1598 // (2) Inline type check -- if either of the operands is not a inline type,
1599 // they are not substitutable. We do this only if we are not sure that the
1600 // operands are inline type
1601 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node.
1602 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
1603 Register tmp1 = op->tmp1()->as_register();
1604 __ mov(tmp1, markWord::inline_type_pattern);
1605 __ ldr(rscratch1, Address(left, oopDesc::mark_offset_in_bytes()));
1606 __ andr(tmp1, tmp1, rscratch1);
1607 __ ldr(rscratch1, Address(right, oopDesc::mark_offset_in_bytes()));
1608 __ andr(tmp1, tmp1, rscratch1);
1609 __ cmp(tmp1, (u1)markWord::inline_type_pattern);
1610 __ br(Assembler::NE, L_oops_not_equal);
1611 }
1612
1613 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
1614 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) {
1615 // No need to load klass -- the operands are statically known to be the same inline klass.
1616 __ b(*op->stub()->entry());
1617 } else {
1618 Register left_klass_op = op->left_klass_op()->as_register();
1619 Register right_klass_op = op->right_klass_op()->as_register();
1620
1621 if (UseCompressedClassPointers) {
1622 __ ldrw(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1623 __ ldrw(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1624 __ cmpw(left_klass_op, right_klass_op);
1625 } else {
1626 __ ldr(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1627 __ ldr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1628 __ cmp(left_klass_op, right_klass_op);
1629 }
1630
1631 __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check
1632 // fall through to L_oops_not_equal
1633 }
1634
1635 __ bind(L_oops_not_equal);
1636 move(op->not_equal_result(), op->result_opr());
1637 __ b(L_end);
1638
1639 __ bind(L_oops_equal);
1640 move(op->equal_result(), op->result_opr());
1641 __ b(L_end);
1642
1643 // We've returned from the stub. R0 contains 0x0 IFF the two
1644 // operands are not substitutable. (Don't compare against 0x1 in case the
1645 // C compiler is naughty)
1646 __ bind(*op->stub()->continuation());
1647 __ cbz(r0, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1648 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
1649 // fall-through
1650 __ bind(L_end);
1651 }
1652
1653
1654 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1655 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1656 __ cset(rscratch1, Assembler::NE);
1657 __ membar(__ AnyAny);
1658 }
1659
1660 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1661 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1662 __ cset(rscratch1, Assembler::NE);
1663 __ membar(__ AnyAny);
1664 }
1665
1666
1667 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1668 Register addr;
1669 if (op->addr()->is_register()) {
1670 addr = as_reg(op->addr());
1671 } else {
1672 assert(op->addr()->is_address(), "what else?");
1673 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1674 assert(addr_ptr->disp() == 0, "need 0 disp");
1675 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1676 addr = as_reg(addr_ptr->base());
1677 }
1678 Register newval = as_reg(op->new_value());
1679 Register cmpval = as_reg(op->cmp_value());
1680
1681 if (op->code() == lir_cas_obj) {
1682 if (UseCompressedOops) {
1683 Register t1 = op->tmp1()->as_register();
1684 assert(op->tmp1()->is_valid(), "must be");
1685 __ encode_heap_oop(t1, cmpval);
1686 cmpval = t1;
1687 __ encode_heap_oop(rscratch2, newval);
1688 newval = rscratch2;
1689 casw(addr, newval, cmpval);
1690 } else {
1691 casl(addr, newval, cmpval);
1692 }
1693 } else if (op->code() == lir_cas_int) {
1694 casw(addr, newval, cmpval);
1695 } else {
1696 casl(addr, newval, cmpval);
1697 }
1698 }
1699
1700
1701 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1702 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1703 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1704
1705 Assembler::Condition acond, ncond;
1706 switch (condition) {
1707 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1708 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1709 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1710 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1711 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1712 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1713 case lir_cond_belowEqual:
1714 case lir_cond_aboveEqual:
1715 default: ShouldNotReachHere();
1716 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1717 }
1718
1719 assert(result->is_single_cpu() || result->is_double_cpu(),
1720 "expect single register for result");
1721 if (opr1->is_constant() && opr2->is_constant()
1722 && opr1->type() == T_INT && opr2->type() == T_INT) {
1723 jint val1 = opr1->as_jint();
1724 jint val2 = opr2->as_jint();
1725 if (val1 == 0 && val2 == 1) {
1726 __ cset(result->as_register(), ncond);
1727 return;
1728 } else if (val1 == 1 && val2 == 0) {
1729 __ cset(result->as_register(), acond);
1730 return;
1731 }
1732 }
1733
1734 if (opr1->is_constant() && opr2->is_constant()
1735 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1736 jlong val1 = opr1->as_jlong();
1737 jlong val2 = opr2->as_jlong();
1738 if (val1 == 0 && val2 == 1) {
1739 __ cset(result->as_register_lo(), ncond);
1740 return;
1741 } else if (val1 == 1 && val2 == 0) {
1742 __ cset(result->as_register_lo(), acond);
1743 return;
1744 }
1745 }
1746
1747 if (opr1->is_stack()) {
1748 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1749 opr1 = FrameMap::rscratch1_opr;
1750 } else if (opr1->is_constant()) {
1751 LIR_Opr tmp
1752 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1753 const2reg(opr1, tmp, lir_patch_none, nullptr);
1754 opr1 = tmp;
1755 }
1756
1757 if (opr2->is_stack()) {
1758 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1759 opr2 = FrameMap::rscratch2_opr;
1760 } else if (opr2->is_constant()) {
1761 LIR_Opr tmp
1762 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1763 const2reg(opr2, tmp, lir_patch_none, nullptr);
1764 opr2 = tmp;
1765 }
1766
1767 if (result->type() == T_LONG)
1768 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1769 else
1770 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1771 }
1772
1773 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1774 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1775
1776 if (left->is_single_cpu()) {
1777 Register lreg = left->as_register();
1778 Register dreg = as_reg(dest);
1779
1780 if (right->is_single_cpu()) {
1781 // cpu register - cpu register
1782
1783 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1784 "should be");
1785 Register rreg = right->as_register();
1786 switch (code) {
1787 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1788 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1789 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1790 default: ShouldNotReachHere();
1791 }
1792
1793 } else if (right->is_double_cpu()) {
1794 Register rreg = right->as_register_lo();
1795 // single_cpu + double_cpu: can happen with obj+long
1796 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1797 switch (code) {
1798 case lir_add: __ add(dreg, lreg, rreg); break;
1799 case lir_sub: __ sub(dreg, lreg, rreg); break;
1800 default: ShouldNotReachHere();
1801 }
1802 } else if (right->is_constant()) {
1803 // cpu register - constant
1804 jlong c;
1805
1806 // FIXME. This is fugly: we really need to factor all this logic.
1807 switch(right->type()) {
1808 case T_LONG:
1809 c = right->as_constant_ptr()->as_jlong();
1810 break;
1811 case T_INT:
1812 case T_ADDRESS:
1813 c = right->as_constant_ptr()->as_jint();
1814 break;
1815 default:
1816 ShouldNotReachHere();
1817 c = 0; // unreachable
1818 break;
1819 }
1820
1821 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1822 if (c == 0 && dreg == lreg) {
1823 COMMENT("effective nop elided");
1824 return;
1825 }
1826 switch(left->type()) {
1827 case T_INT:
1828 switch (code) {
1829 case lir_add: __ addw(dreg, lreg, c); break;
1830 case lir_sub: __ subw(dreg, lreg, c); break;
1831 default: ShouldNotReachHere();
1832 }
1833 break;
1834 case T_OBJECT:
1835 case T_ADDRESS:
1836 switch (code) {
1837 case lir_add: __ add(dreg, lreg, c); break;
1838 case lir_sub: __ sub(dreg, lreg, c); break;
1839 default: ShouldNotReachHere();
1840 }
1841 break;
1842 default:
1843 ShouldNotReachHere();
1844 }
1845 } else {
1846 ShouldNotReachHere();
1847 }
1848
1849 } else if (left->is_double_cpu()) {
1850 Register lreg_lo = left->as_register_lo();
1851
1852 if (right->is_double_cpu()) {
1853 // cpu register - cpu register
1854 Register rreg_lo = right->as_register_lo();
1855 switch (code) {
1856 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1857 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1858 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1859 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1860 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1861 default:
1862 ShouldNotReachHere();
1863 }
1864
1865 } else if (right->is_constant()) {
1866 jlong c = right->as_constant_ptr()->as_jlong();
1867 Register dreg = as_reg(dest);
1868 switch (code) {
1869 case lir_add:
1870 case lir_sub:
1871 if (c == 0 && dreg == lreg_lo) {
1872 COMMENT("effective nop elided");
1873 return;
1874 }
1875 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1876 break;
1877 case lir_div:
1878 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1879 if (c == 1) {
1880 // move lreg_lo to dreg if divisor is 1
1881 __ mov(dreg, lreg_lo);
1882 } else {
1883 unsigned int shift = log2i_exact(c);
1884 // use rscratch1 as intermediate result register
1885 __ asr(rscratch1, lreg_lo, 63);
1886 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1887 __ asr(dreg, rscratch1, shift);
1888 }
1889 break;
1890 case lir_rem:
1891 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1892 if (c == 1) {
1893 // move 0 to dreg if divisor is 1
1894 __ mov(dreg, zr);
1895 } else {
1896 // use rscratch1 as intermediate result register
1897 __ negs(rscratch1, lreg_lo);
1898 __ andr(dreg, lreg_lo, c - 1);
1899 __ andr(rscratch1, rscratch1, c - 1);
1900 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1901 }
1902 break;
1903 default:
1904 ShouldNotReachHere();
1905 }
1906 } else {
1907 ShouldNotReachHere();
1908 }
1909 } else if (left->is_single_fpu()) {
1910 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1911 switch (code) {
1912 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1913 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1914 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1915 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1916 default:
1917 ShouldNotReachHere();
1918 }
1919 } else if (left->is_double_fpu()) {
1920 if (right->is_double_fpu()) {
1921 // fpu register - fpu register
1922 switch (code) {
1923 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1924 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1925 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1926 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1927 default:
1928 ShouldNotReachHere();
1929 }
1930 } else {
1931 if (right->is_constant()) {
1932 ShouldNotReachHere();
1933 }
1934 ShouldNotReachHere();
1935 }
1936 } else if (left->is_single_stack() || left->is_address()) {
1937 assert(left == dest, "left and dest must be equal");
1938 ShouldNotReachHere();
1939 } else {
1940 ShouldNotReachHere();
1941 }
1942 }
1943
1944 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1945 switch(code) {
1946 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1947 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1948 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1949 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1950 default : ShouldNotReachHere();
1951 }
1952 }
1953
1954 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1955
1956 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1957 Register Rleft = left->is_single_cpu() ? left->as_register() :
1958 left->as_register_lo();
1959 if (dst->is_single_cpu()) {
1960 Register Rdst = dst->as_register();
1961 if (right->is_constant()) {
1962 switch (code) {
1963 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1964 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1965 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1966 default: ShouldNotReachHere(); break;
1967 }
1968 } else {
1969 Register Rright = right->is_single_cpu() ? right->as_register() :
1970 right->as_register_lo();
1971 switch (code) {
1972 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1973 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1974 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1975 default: ShouldNotReachHere(); break;
1976 }
1977 }
1978 } else {
1979 Register Rdst = dst->as_register_lo();
1980 if (right->is_constant()) {
1981 switch (code) {
1982 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1983 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1984 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1985 default: ShouldNotReachHere(); break;
1986 }
1987 } else {
1988 Register Rright = right->is_single_cpu() ? right->as_register() :
1989 right->as_register_lo();
1990 switch (code) {
1991 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1992 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1993 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1994 default: ShouldNotReachHere(); break;
1995 }
1996 }
1997 }
1998 }
1999
2000
2001
2002 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
2003
2004 // opcode check
2005 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
2006 bool is_irem = (code == lir_irem);
2007
2008 // operand check
2009 assert(left->is_single_cpu(), "left must be register");
2010 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2011 assert(result->is_single_cpu(), "result must be register");
2012 Register lreg = left->as_register();
2013 Register dreg = result->as_register();
2014
2015 // power-of-2 constant check and codegen
2016 if (right->is_constant()) {
2017 int c = right->as_constant_ptr()->as_jint();
2018 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
2019 if (is_irem) {
2020 if (c == 1) {
2021 // move 0 to dreg if divisor is 1
2022 __ movw(dreg, zr);
2023 } else {
2024 // use rscratch1 as intermediate result register
2025 __ negsw(rscratch1, lreg);
2026 __ andw(dreg, lreg, c - 1);
2027 __ andw(rscratch1, rscratch1, c - 1);
2028 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
2029 }
2030 } else {
2031 if (c == 1) {
2032 // move lreg to dreg if divisor is 1
2033 __ movw(dreg, lreg);
2034 } else {
2035 unsigned int shift = exact_log2(c);
2036 // use rscratch1 as intermediate result register
2037 __ asrw(rscratch1, lreg, 31);
2038 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
2039 __ asrw(dreg, rscratch1, shift);
2040 }
2041 }
2042 } else {
2043 Register rreg = right->as_register();
2044 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
2045 }
2046 }
2047
2048
2049 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2050 if (opr1->is_constant() && opr2->is_single_cpu()) {
2051 // tableswitch
2052 Register reg = as_reg(opr2);
2053 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
2054 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
2055 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
2056 Register reg1 = as_reg(opr1);
2057 if (opr2->is_single_cpu()) {
2058 // cpu register - cpu register
2059 Register reg2 = opr2->as_register();
2060 if (is_reference_type(opr1->type())) {
2061 __ cmpoop(reg1, reg2);
2062 } else {
2063 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2064 __ cmpw(reg1, reg2);
2065 }
2066 return;
2067 }
2068 if (opr2->is_double_cpu()) {
2069 // cpu register - cpu register
2070 Register reg2 = opr2->as_register_lo();
2071 __ cmp(reg1, reg2);
2072 return;
2073 }
2074
2075 if (opr2->is_constant()) {
2076 bool is_32bit = false; // width of register operand
2077 jlong imm;
2078
2079 switch(opr2->type()) {
2080 case T_INT:
2081 imm = opr2->as_constant_ptr()->as_jint();
2082 is_32bit = true;
2083 break;
2084 case T_LONG:
2085 imm = opr2->as_constant_ptr()->as_jlong();
2086 break;
2087 case T_ADDRESS:
2088 imm = opr2->as_constant_ptr()->as_jint();
2089 break;
2090 case T_METADATA:
2091 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
2092 break;
2093 case T_OBJECT:
2094 case T_ARRAY:
2095 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
2096 __ cmpoop(reg1, rscratch1);
2097 return;
2098 default:
2099 ShouldNotReachHere();
2100 imm = 0; // unreachable
2101 break;
2102 }
2103
2104 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
2105 if (is_32bit)
2106 __ cmpw(reg1, imm);
2107 else
2108 __ subs(zr, reg1, imm);
2109 return;
2110 } else {
2111 __ mov(rscratch1, imm);
2112 if (is_32bit)
2113 __ cmpw(reg1, rscratch1);
2114 else
2115 __ cmp(reg1, rscratch1);
2116 return;
2117 }
2118 } else
2119 ShouldNotReachHere();
2120 } else if (opr1->is_single_fpu()) {
2121 FloatRegister reg1 = opr1->as_float_reg();
2122 assert(opr2->is_single_fpu(), "expect single float register");
2123 FloatRegister reg2 = opr2->as_float_reg();
2124 __ fcmps(reg1, reg2);
2125 } else if (opr1->is_double_fpu()) {
2126 FloatRegister reg1 = opr1->as_double_reg();
2127 assert(opr2->is_double_fpu(), "expect double float register");
2128 FloatRegister reg2 = opr2->as_double_reg();
2129 __ fcmpd(reg1, reg2);
2130 } else {
2131 ShouldNotReachHere();
2132 }
2133 }
2134
2135 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2136 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2137 bool is_unordered_less = (code == lir_ucmp_fd2i);
2138 if (left->is_single_fpu()) {
2139 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2140 } else if (left->is_double_fpu()) {
2141 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2142 } else {
2143 ShouldNotReachHere();
2144 }
2145 } else if (code == lir_cmp_l2i) {
2146 Label done;
2147 __ cmp(left->as_register_lo(), right->as_register_lo());
2148 __ mov(dst->as_register(), (uint64_t)-1L);
2149 __ br(Assembler::LT, done);
2150 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2151 __ bind(done);
2152 } else {
2153 ShouldNotReachHere();
2154 }
2155 }
2156
2157
2158 void LIR_Assembler::align_call(LIR_Code code) { }
2159
2160
2161 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2162 address call = __ trampoline_call(Address(op->addr(), rtype));
2163 if (call == nullptr) {
2164 bailout("trampoline stub overflow");
2165 return;
2166 }
2167 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2168 __ post_call_nop();
2169 }
2170
2171
2172 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2173 address call = __ ic_call(op->addr());
2174 if (call == nullptr) {
2175 bailout("trampoline stub overflow");
2176 return;
2177 }
2178 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2179 __ post_call_nop();
2180 }
2181
2182 void LIR_Assembler::emit_static_call_stub() {
2183 address call_pc = __ pc();
2184 address stub = __ start_a_stub(call_stub_size());
2185 if (stub == nullptr) {
2186 bailout("static call stub overflow");
2187 return;
2188 }
2189
2190 int start = __ offset();
2191
2192 __ relocate(static_stub_Relocation::spec(call_pc));
2193 __ emit_static_call_stub();
2194
2195 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2196 <= call_stub_size(), "stub too big");
2197 __ end_a_stub();
2198 }
2199
2200
2201 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2202 assert(exceptionOop->as_register() == r0, "must match");
2203 assert(exceptionPC->as_register() == r3, "must match");
2204
2205 // exception object is not added to oop map by LinearScan
2206 // (LinearScan assumes that no oops are in fixed registers)
2207 info->add_register_oop(exceptionOop);
2208 C1StubId unwind_id;
2209
2210 // get current pc information
2211 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2212 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2213 // As no instructions have been generated yet for this LIR node it's
2214 // possible that an oop map already exists for the current offset.
2215 // In that case insert an dummy NOP here to ensure all oop map PCs
2216 // are unique. See JDK-8237483.
2217 __ nop();
2218 }
2219 int pc_for_athrow_offset = __ offset();
2220 InternalAddress pc_for_athrow(__ pc());
2221 __ adr(exceptionPC->as_register(), pc_for_athrow);
2222 add_call_info(pc_for_athrow_offset, info); // for exception handler
2223
2224 __ verify_not_null_oop(r0);
2225 // search an exception handler (r0: exception oop, r3: throwing pc)
2226 if (compilation()->has_fpu_code()) {
2227 unwind_id = C1StubId::handle_exception_id;
2228 } else {
2229 unwind_id = C1StubId::handle_exception_nofpu_id;
2230 }
2231 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2232
2233 // FIXME: enough room for two byte trap ????
2234 __ nop();
2235 }
2236
2237
2238 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2239 assert(exceptionOop->as_register() == r0, "must match");
2240
2241 __ b(_unwind_handler_entry);
2242 }
2243
2244
2245 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2246 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2247 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2248
2249 switch (left->type()) {
2250 case T_INT: {
2251 switch (code) {
2252 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2253 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2254 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2255 default:
2256 ShouldNotReachHere();
2257 break;
2258 }
2259 break;
2260 case T_LONG:
2261 case T_ADDRESS:
2262 case T_OBJECT:
2263 switch (code) {
2264 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2265 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2266 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2267 default:
2268 ShouldNotReachHere();
2269 break;
2270 }
2271 break;
2272 default:
2273 ShouldNotReachHere();
2274 break;
2275 }
2276 }
2277 }
2278
2279
2280 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2281 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2282 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2283
2284 switch (left->type()) {
2285 case T_INT: {
2286 switch (code) {
2287 case lir_shl: __ lslw (dreg, lreg, count); break;
2288 case lir_shr: __ asrw (dreg, lreg, count); break;
2289 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2290 default:
2291 ShouldNotReachHere();
2292 break;
2293 }
2294 break;
2295 case T_LONG:
2296 case T_ADDRESS:
2297 case T_OBJECT:
2298 switch (code) {
2299 case lir_shl: __ lsl (dreg, lreg, count); break;
2300 case lir_shr: __ asr (dreg, lreg, count); break;
2301 case lir_ushr: __ lsr (dreg, lreg, count); break;
2302 default:
2303 ShouldNotReachHere();
2304 break;
2305 }
2306 break;
2307 default:
2308 ShouldNotReachHere();
2309 break;
2310 }
2311 }
2312 }
2313
2314
2315 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2316 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2317 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2318 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2319 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2320 }
2321
2322
2323 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2324 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2325 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2326 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2327 __ mov (rscratch1, c);
2328 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2329 }
2330
2331
2332 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2333 ShouldNotReachHere();
2334 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2335 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2336 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2337 __ lea(rscratch1, __ constant_oop_address(o));
2338 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2339 }
2340
2341 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
2342 if (null_check) {
2343 __ cbz(obj, *slow_path->entry());
2344 }
2345 if (is_dest) {
2346 __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
2347 // TODO 8350865 Flat no longer implies null-free, so we need to check for flat dest. Can we do better here?
2348 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2349 } else {
2350 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2351 }
2352 }
2353
2354 // This code replaces a call to arraycopy; no exception may
2355 // be thrown in this code, they must be thrown in the System.arraycopy
2356 // activation frame; we could save some checks if this would not be the case
2357 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2358 ciArrayKlass* default_type = op->expected_type();
2359 Register src = op->src()->as_register();
2360 Register dst = op->dst()->as_register();
2361 Register src_pos = op->src_pos()->as_register();
2362 Register dst_pos = op->dst_pos()->as_register();
2363 Register length = op->length()->as_register();
2364 Register tmp = op->tmp()->as_register();
2365
2366 CodeStub* stub = op->stub();
2367 int flags = op->flags();
2368 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2369 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2370
2371 if (flags & LIR_OpArrayCopy::always_slow_path) {
2372 __ b(*stub->entry());
2373 __ bind(*stub->continuation());
2374 return;
2375 }
2376
2377 // if we don't know anything, just go through the generic arraycopy
2378 if (default_type == nullptr // || basic_type == T_OBJECT
2379 ) {
2380 Label done;
2381 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2382
2383 // Save the arguments in case the generic arraycopy fails and we
2384 // have to fall back to the JNI stub
2385 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2386 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2387 __ str(src, Address(sp, 4*BytesPerWord));
2388
2389 address copyfunc_addr = StubRoutines::generic_arraycopy();
2390 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2391
2392 // The arguments are in java calling convention so we shift them
2393 // to C convention
2394 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2395 __ mov(c_rarg0, j_rarg0);
2396 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2397 __ mov(c_rarg1, j_rarg1);
2398 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2399 __ mov(c_rarg2, j_rarg2);
2400 assert_different_registers(c_rarg3, j_rarg4);
2401 __ mov(c_rarg3, j_rarg3);
2402 __ mov(c_rarg4, j_rarg4);
2403 #ifndef PRODUCT
2404 if (PrintC1Statistics) {
2405 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2406 }
2407 #endif
2408 __ far_call(RuntimeAddress(copyfunc_addr));
2409
2410 __ cbz(r0, *stub->continuation());
2411
2412 // Reload values from the stack so they are where the stub
2413 // expects them.
2414 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2415 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2416 __ ldr(src, Address(sp, 4*BytesPerWord));
2417
2418 // r0 is -1^K where K == partial copied count
2419 __ eonw(rscratch1, r0, zr);
2420 // adjust length down and src/end pos up by partial copied count
2421 __ subw(length, length, rscratch1);
2422 __ addw(src_pos, src_pos, rscratch1);
2423 __ addw(dst_pos, dst_pos, rscratch1);
2424 __ b(*stub->entry());
2425
2426 __ bind(*stub->continuation());
2427 return;
2428 }
2429
2430 // Handle inline type arrays
2431 if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
2432 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
2433 }
2434 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
2435 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
2436 }
2437
2438 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2439
2440 int elem_size = type2aelembytes(basic_type);
2441 int scale = exact_log2(elem_size);
2442
2443 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2444 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2445
2446 // test for null
2447 if (flags & LIR_OpArrayCopy::src_null_check) {
2448 __ cbz(src, *stub->entry());
2449 }
2450 if (flags & LIR_OpArrayCopy::dst_null_check) {
2451 __ cbz(dst, *stub->entry());
2452 }
2453
2454 // If the compiler was not able to prove that exact type of the source or the destination
2455 // of the arraycopy is an array type, check at runtime if the source or the destination is
2456 // an instance type.
2457 if (flags & LIR_OpArrayCopy::type_check) {
2458 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2459 __ load_klass(tmp, dst);
2460 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2461 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2462 __ br(Assembler::GE, *stub->entry());
2463 }
2464
2465 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2466 __ load_klass(tmp, src);
2467 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2468 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2469 __ br(Assembler::GE, *stub->entry());
2470 }
2471 }
2472
2473 // check if negative
2474 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2475 __ cmpw(src_pos, 0);
2476 __ br(Assembler::LT, *stub->entry());
2477 }
2478 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2479 __ cmpw(dst_pos, 0);
2480 __ br(Assembler::LT, *stub->entry());
2481 }
2482
2483 if (flags & LIR_OpArrayCopy::length_positive_check) {
2484 __ cmpw(length, 0);
2485 __ br(Assembler::LT, *stub->entry());
2486 }
2487
2488 if (flags & LIR_OpArrayCopy::src_range_check) {
2489 __ addw(tmp, src_pos, length);
2490 __ ldrw(rscratch1, src_length_addr);
2491 __ cmpw(tmp, rscratch1);
2492 __ br(Assembler::HI, *stub->entry());
2493 }
2494 if (flags & LIR_OpArrayCopy::dst_range_check) {
2495 __ addw(tmp, dst_pos, length);
2496 __ ldrw(rscratch1, dst_length_addr);
2497 __ cmpw(tmp, rscratch1);
2498 __ br(Assembler::HI, *stub->entry());
2499 }
2500
2501 if (flags & LIR_OpArrayCopy::type_check) {
2502 // We don't know the array types are compatible
2503 if (basic_type != T_OBJECT) {
2504 // Simple test for basic type arrays
2505 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2506 __ br(Assembler::NE, *stub->entry());
2507 } else {
2508 // For object arrays, if src is a sub class of dst then we can
2509 // safely do the copy.
2510 Label cont, slow;
2511
2512 #define PUSH(r1, r2) \
2513 stp(r1, r2, __ pre(sp, -2 * wordSize));
2514
2515 #define POP(r1, r2) \
2516 ldp(r1, r2, __ post(sp, 2 * wordSize));
2517
2518 __ PUSH(src, dst);
2519
2520 __ load_klass(src, src);
2521 __ load_klass(dst, dst);
2522
2523 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2524
2525 __ PUSH(src, dst);
2526 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
2527 __ POP(src, dst);
2528
2529 __ cbnz(src, cont);
2530
2531 __ bind(slow);
2532 __ POP(src, dst);
2533
2534 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2535 if (copyfunc_addr != nullptr) { // use stub if available
2536 // src is not a sub class of dst so we have to do a
2537 // per-element check.
2538
2539 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2540 if ((flags & mask) != mask) {
2541 // Check that at least both of them object arrays.
2542 assert(flags & mask, "one of the two should be known to be an object array");
2543
2544 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2545 __ load_klass(tmp, src);
2546 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2547 __ load_klass(tmp, dst);
2548 }
2549 int lh_offset = in_bytes(Klass::layout_helper_offset());
2550 Address klass_lh_addr(tmp, lh_offset);
2551 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2552 __ ldrw(rscratch1, klass_lh_addr);
2553 __ mov(rscratch2, objArray_lh);
2554 __ eorw(rscratch1, rscratch1, rscratch2);
2555 __ cbnzw(rscratch1, *stub->entry());
2556 }
2557
2558 // Spill because stubs can use any register they like and it's
2559 // easier to restore just those that we care about.
2560 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2561 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2562 __ str(src, Address(sp, 4*BytesPerWord));
2563
2564 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2565 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2566 assert_different_registers(c_rarg0, dst, dst_pos, length);
2567 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2568 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2569 assert_different_registers(c_rarg1, dst, length);
2570 __ uxtw(c_rarg2, length);
2571 assert_different_registers(c_rarg2, dst);
2572
2573 __ load_klass(c_rarg4, dst);
2574 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2575 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2576 __ far_call(RuntimeAddress(copyfunc_addr));
2577
2578 #ifndef PRODUCT
2579 if (PrintC1Statistics) {
2580 Label failed;
2581 __ cbnz(r0, failed);
2582 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2583 __ bind(failed);
2584 }
2585 #endif
2586
2587 __ cbz(r0, *stub->continuation());
2588
2589 #ifndef PRODUCT
2590 if (PrintC1Statistics) {
2591 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2592 }
2593 #endif
2594 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2595
2596 // Restore previously spilled arguments
2597 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2598 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2599 __ ldr(src, Address(sp, 4*BytesPerWord));
2600
2601 // return value is -1^K where K is partial copied count
2602 __ eonw(rscratch1, r0, zr);
2603 // adjust length down and src/end pos up by partial copied count
2604 __ subw(length, length, rscratch1);
2605 __ addw(src_pos, src_pos, rscratch1);
2606 __ addw(dst_pos, dst_pos, rscratch1);
2607 }
2608
2609 __ b(*stub->entry());
2610
2611 __ bind(cont);
2612 __ POP(src, dst);
2613 }
2614 }
2615
2616 #ifdef ASSERT
2617 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2618 // Sanity check the known type with the incoming class. For the
2619 // primitive case the types must match exactly with src.klass and
2620 // dst.klass each exactly matching the default type. For the
2621 // object array case, if no type check is needed then either the
2622 // dst type is exactly the expected type and the src type is a
2623 // subtype which we can't check or src is the same array as dst
2624 // but not necessarily exactly of type default_type.
2625 Label known_ok, halt;
2626 __ mov_metadata(tmp, default_type->constant_encoding());
2627
2628 if (basic_type != T_OBJECT) {
2629 __ cmp_klass(dst, tmp, rscratch1);
2630 __ br(Assembler::NE, halt);
2631 __ cmp_klass(src, tmp, rscratch1);
2632 __ br(Assembler::EQ, known_ok);
2633 } else {
2634 __ cmp_klass(dst, tmp, rscratch1);
2635 __ br(Assembler::EQ, known_ok);
2636 __ cmp(src, dst);
2637 __ br(Assembler::EQ, known_ok);
2638 }
2639 __ bind(halt);
2640 __ stop("incorrect type information in arraycopy");
2641 __ bind(known_ok);
2642 }
2643 #endif
2644
2645 #ifndef PRODUCT
2646 if (PrintC1Statistics) {
2647 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2648 }
2649 #endif
2650
2651 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2652 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2653 assert_different_registers(c_rarg0, dst, dst_pos, length);
2654 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2655 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2656 assert_different_registers(c_rarg1, dst, length);
2657 __ uxtw(c_rarg2, length);
2658 assert_different_registers(c_rarg2, dst);
2659
2660 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2661 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2662 const char *name;
2663 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2664
2665 CodeBlob *cb = CodeCache::find_blob(entry);
2666 if (cb) {
2667 __ far_call(RuntimeAddress(entry));
2668 } else {
2669 __ call_VM_leaf(entry, 3);
2670 }
2671
2672 if (stub != nullptr) {
2673 __ bind(*stub->continuation());
2674 }
2675 }
2676
2677
2678
2679
2680 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2681 Register obj = op->obj_opr()->as_register(); // may not be an oop
2682 Register hdr = op->hdr_opr()->as_register();
2683 Register lock = op->lock_opr()->as_register();
2684 Register temp = op->scratch_opr()->as_register();
2685 if (LockingMode == LM_MONITOR) {
2686 if (op->info() != nullptr) {
2687 add_debug_info_for_null_check_here(op->info());
2688 __ null_check(obj, -1);
2689 }
2690 __ b(*op->stub()->entry());
2691 } else if (op->code() == lir_lock) {
2692 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2693 // add debug info for NullPointerException only if one is possible
2694 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2695 if (op->info() != nullptr) {
2696 add_debug_info_for_null_check(null_check_offset, op->info());
2697 }
2698 // done
2699 } else if (op->code() == lir_unlock) {
2700 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2701 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2702 } else {
2703 Unimplemented();
2704 }
2705 __ bind(*op->stub()->continuation());
2706 }
2707
2708 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2709 Register obj = op->obj()->as_pointer_register();
2710 Register result = op->result_opr()->as_pointer_register();
2711
2712 CodeEmitInfo* info = op->info();
2713 if (info != nullptr) {
2714 add_debug_info_for_null_check_here(info);
2715 }
2716
2717 __ load_klass(result, obj);
2718 }
2719
2720 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2721 ciMethod* method = op->profiled_method();
2722 int bci = op->profiled_bci();
2723 ciMethod* callee = op->profiled_callee();
2724
2725 // Update counter for all call types
2726 ciMethodData* md = method->method_data_or_null();
2727 assert(md != nullptr, "Sanity");
2728 ciProfileData* data = md->bci_to_data(bci);
2729 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2730 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2731 Register mdo = op->mdo()->as_register();
2732 __ mov_metadata(mdo, md->constant_encoding());
2733 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2734 // Perform additional virtual call profiling for invokevirtual and
2735 // invokeinterface bytecodes
2736 if (op->should_profile_receiver_type()) {
2737 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2738 Register recv = op->recv()->as_register();
2739 assert_different_registers(mdo, recv);
2740 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2741 ciKlass* known_klass = op->known_holder();
2742 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2743 // We know the type that will be seen at this call site; we can
2744 // statically update the MethodData* rather than needing to do
2745 // dynamic tests on the receiver type
2746
2747 // NOTE: we should probably put a lock around this search to
2748 // avoid collisions by concurrent compilations
2749 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2750 uint i;
2751 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2752 ciKlass* receiver = vc_data->receiver(i);
2753 if (known_klass->equals(receiver)) {
2754 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2755 __ addptr(data_addr, DataLayout::counter_increment);
2756 return;
2757 }
2758 }
2759
2760 // Receiver type not found in profile data; select an empty slot
2761
2762 // Note that this is less efficient than it should be because it
2763 // always does a write to the receiver part of the
2764 // VirtualCallData rather than just the first time
2765 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2766 ciKlass* receiver = vc_data->receiver(i);
2767 if (receiver == nullptr) {
2768 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2769 Address recv_addr =
2770 __ form_address(rscratch2, mdo,
2771 md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)),
2772 LogBytesPerWord);
2773 __ str(rscratch1, recv_addr);
2774 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2775 __ addptr(data_addr, DataLayout::counter_increment);
2776 return;
2777 }
2778 }
2779 } else {
2780 __ load_klass(recv, recv);
2781 Label update_done;
2782 type_profile_helper(mdo, md, data, recv, &update_done);
2783 // Receiver did not match any saved receiver and there is no empty row for it.
2784 // Increment total counter to indicate polymorphic case.
2785 __ addptr(counter_addr, DataLayout::counter_increment);
2786
2787 __ bind(update_done);
2788 }
2789 } else {
2790 // Static call
2791 __ addptr(counter_addr, DataLayout::counter_increment);
2792 }
2793 }
2794
2795
2796 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2797 Unimplemented();
2798 }
2799
2800
2801 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2802 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2803 }
2804
2805 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2806 assert(op->crc()->is_single_cpu(), "crc must be register");
2807 assert(op->val()->is_single_cpu(), "byte value must be register");
2808 assert(op->result_opr()->is_single_cpu(), "result must be register");
2809 Register crc = op->crc()->as_register();
2810 Register val = op->val()->as_register();
2811 Register res = op->result_opr()->as_register();
2812
2813 assert_different_registers(val, crc, res);
2814 uint64_t offset;
2815 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2816 __ add(res, res, offset);
2817
2818 __ mvnw(crc, crc); // ~crc
2819 __ update_byte_crc32(crc, val, res);
2820 __ mvnw(res, crc); // ~crc
2821 }
2822
2823 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2824 COMMENT("emit_profile_type {");
2825 Register obj = op->obj()->as_register();
2826 Register tmp = op->tmp()->as_pointer_register();
2827 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2828 ciKlass* exact_klass = op->exact_klass();
2829 intptr_t current_klass = op->current_klass();
2830 bool not_null = op->not_null();
2831 bool no_conflict = op->no_conflict();
2832
2833 Label update, next, none;
2834
2835 bool do_null = !not_null;
2836 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2837 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2838
2839 assert(do_null || do_update, "why are we here?");
2840 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2841 assert(mdo_addr.base() != rscratch1, "wrong register");
2842
2843 __ verify_oop(obj);
2844
2845 if (tmp != obj) {
2846 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2847 __ mov(tmp, obj);
2848 } else {
2849 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2850 }
2851 if (do_null) {
2852 __ cbnz(tmp, update);
2853 if (!TypeEntries::was_null_seen(current_klass)) {
2854 __ ldr(rscratch2, mdo_addr);
2855 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2856 __ str(rscratch2, mdo_addr);
2857 }
2858 if (do_update) {
2859 #ifndef ASSERT
2860 __ b(next);
2861 }
2862 #else
2863 __ b(next);
2864 }
2865 } else {
2866 __ cbnz(tmp, update);
2867 __ stop("unexpected null obj");
2868 #endif
2869 }
2870
2871 __ bind(update);
2872
2873 if (do_update) {
2874 #ifdef ASSERT
2875 if (exact_klass != nullptr) {
2876 Label ok;
2877 __ load_klass(tmp, tmp);
2878 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2879 __ eor(rscratch1, tmp, rscratch1);
2880 __ cbz(rscratch1, ok);
2881 __ stop("exact klass and actual klass differ");
2882 __ bind(ok);
2883 }
2884 #endif
2885 if (!no_conflict) {
2886 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2887 if (exact_klass != nullptr) {
2888 __ mov_metadata(tmp, exact_klass->constant_encoding());
2889 } else {
2890 __ load_klass(tmp, tmp);
2891 }
2892
2893 __ ldr(rscratch2, mdo_addr);
2894 __ eor(tmp, tmp, rscratch2);
2895 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2896 // klass seen before, nothing to do. The unknown bit may have been
2897 // set already but no need to check.
2898 __ cbz(rscratch1, next);
2899
2900 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2901
2902 if (TypeEntries::is_type_none(current_klass)) {
2903 __ cbz(rscratch2, none);
2904 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2905 __ br(Assembler::EQ, none);
2906 // There is a chance that the checks above
2907 // fail if another thread has just set the
2908 // profiling to this obj's klass
2909 __ dmb(Assembler::ISHLD);
2910 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2911 __ ldr(rscratch2, mdo_addr);
2912 __ eor(tmp, tmp, rscratch2);
2913 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2914 __ cbz(rscratch1, next);
2915 }
2916 } else {
2917 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2918 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2919
2920 __ ldr(tmp, mdo_addr);
2921 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2922 }
2923
2924 // different than before. Cannot keep accurate profile.
2925 __ ldr(rscratch2, mdo_addr);
2926 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2927 __ str(rscratch2, mdo_addr);
2928
2929 if (TypeEntries::is_type_none(current_klass)) {
2930 __ b(next);
2931
2932 __ bind(none);
2933 // first time here. Set profile type.
2934 __ str(tmp, mdo_addr);
2935 #ifdef ASSERT
2936 __ andr(tmp, tmp, TypeEntries::type_mask);
2937 __ verify_klass_ptr(tmp);
2938 #endif
2939 }
2940 } else {
2941 // There's a single possible klass at this profile point
2942 assert(exact_klass != nullptr, "should be");
2943 if (TypeEntries::is_type_none(current_klass)) {
2944 __ mov_metadata(tmp, exact_klass->constant_encoding());
2945 __ ldr(rscratch2, mdo_addr);
2946 __ eor(tmp, tmp, rscratch2);
2947 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2948 __ cbz(rscratch1, next);
2949 #ifdef ASSERT
2950 {
2951 Label ok;
2952 __ ldr(rscratch1, mdo_addr);
2953 __ cbz(rscratch1, ok);
2954 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2955 __ br(Assembler::EQ, ok);
2956 // may have been set by another thread
2957 __ dmb(Assembler::ISHLD);
2958 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2959 __ ldr(rscratch2, mdo_addr);
2960 __ eor(rscratch2, rscratch1, rscratch2);
2961 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2962 __ cbz(rscratch2, ok);
2963
2964 __ stop("unexpected profiling mismatch");
2965 __ bind(ok);
2966 }
2967 #endif
2968 // first time here. Set profile type.
2969 __ str(tmp, mdo_addr);
2970 #ifdef ASSERT
2971 __ andr(tmp, tmp, TypeEntries::type_mask);
2972 __ verify_klass_ptr(tmp);
2973 #endif
2974 } else {
2975 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2976 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2977
2978 __ ldr(tmp, mdo_addr);
2979 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2980
2981 __ orr(tmp, tmp, TypeEntries::type_unknown);
2982 __ str(tmp, mdo_addr);
2983 // FIXME: Write barrier needed here?
2984 }
2985 }
2986
2987 __ bind(next);
2988 }
2989 COMMENT("} emit_profile_type");
2990 }
2991
2992 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
2993 Register obj = op->obj()->as_register();
2994 Register tmp = op->tmp()->as_pointer_register();
2995 bool not_null = op->not_null();
2996 int flag = op->flag();
2997
2998 Label not_inline_type;
2999 if (!not_null) {
3000 __ cbz(obj, not_inline_type);
3001 }
3002
3003 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
3004
3005 Address mdo_addr = as_Address(op->mdp()->as_address_ptr(), rscratch2);
3006 __ ldrb(rscratch1, mdo_addr);
3007 __ orr(rscratch1, rscratch1, flag);
3008 __ strb(rscratch1, mdo_addr);
3009
3010 __ bind(not_inline_type);
3011 }
3012
3013 void LIR_Assembler::align_backward_branch_target() {
3014 }
3015
3016
3017 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3018 // tmp must be unused
3019 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3020
3021 if (left->is_single_cpu()) {
3022 assert(dest->is_single_cpu(), "expect single result reg");
3023 __ negw(dest->as_register(), left->as_register());
3024 } else if (left->is_double_cpu()) {
3025 assert(dest->is_double_cpu(), "expect double result reg");
3026 __ neg(dest->as_register_lo(), left->as_register_lo());
3027 } else if (left->is_single_fpu()) {
3028 assert(dest->is_single_fpu(), "expect single float result reg");
3029 __ fnegs(dest->as_float_reg(), left->as_float_reg());
3030 } else {
3031 assert(left->is_double_fpu(), "expect double float operand reg");
3032 assert(dest->is_double_fpu(), "expect double float result reg");
3033 __ fnegd(dest->as_double_reg(), left->as_double_reg());
3034 }
3035 }
3036
3037
3038 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3039 if (patch_code != lir_patch_none) {
3040 deoptimize_trap(info);
3041 return;
3042 }
3043
3044 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
3045 }
3046
3047
3048 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3049 assert(!tmp->is_valid(), "don't need temporary");
3050
3051 CodeBlob *cb = CodeCache::find_blob(dest);
3052 if (cb) {
3053 __ far_call(RuntimeAddress(dest));
3054 } else {
3055 __ mov(rscratch1, RuntimeAddress(dest));
3056 __ blr(rscratch1);
3057 }
3058
3059 if (info != nullptr) {
3060 add_call_info_here(info);
3061 }
3062 __ post_call_nop();
3063 }
3064
3065 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3066 if (dest->is_address() || src->is_address()) {
3067 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
3068 } else {
3069 ShouldNotReachHere();
3070 }
3071 }
3072
3073 #ifdef ASSERT
3074 // emit run-time assertion
3075 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3076 assert(op->code() == lir_assert, "must be");
3077
3078 if (op->in_opr1()->is_valid()) {
3079 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3080 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3081 } else {
3082 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3083 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3084 }
3085
3086 Label ok;
3087 if (op->condition() != lir_cond_always) {
3088 Assembler::Condition acond = Assembler::AL;
3089 switch (op->condition()) {
3090 case lir_cond_equal: acond = Assembler::EQ; break;
3091 case lir_cond_notEqual: acond = Assembler::NE; break;
3092 case lir_cond_less: acond = Assembler::LT; break;
3093 case lir_cond_lessEqual: acond = Assembler::LE; break;
3094 case lir_cond_greaterEqual: acond = Assembler::GE; break;
3095 case lir_cond_greater: acond = Assembler::GT; break;
3096 case lir_cond_belowEqual: acond = Assembler::LS; break;
3097 case lir_cond_aboveEqual: acond = Assembler::HS; break;
3098 default: ShouldNotReachHere();
3099 }
3100 __ br(acond, ok);
3101 }
3102 if (op->halt()) {
3103 const char* str = __ code_string(op->msg());
3104 __ stop(str);
3105 } else {
3106 breakpoint();
3107 }
3108 __ bind(ok);
3109 }
3110 #endif
3111
3112 #ifndef PRODUCT
3113 #define COMMENT(x) do { __ block_comment(x); } while (0)
3114 #else
3115 #define COMMENT(x)
3116 #endif
3117
3118 void LIR_Assembler::membar() {
3119 COMMENT("membar");
3120 __ membar(MacroAssembler::AnyAny);
3121 }
3122
3123 void LIR_Assembler::membar_acquire() {
3124 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
3125 }
3126
3127 void LIR_Assembler::membar_release() {
3128 __ membar(Assembler::LoadStore|Assembler::StoreStore);
3129 }
3130
3131 void LIR_Assembler::membar_loadload() {
3132 __ membar(Assembler::LoadLoad);
3133 }
3134
3135 void LIR_Assembler::membar_storestore() {
3136 __ membar(MacroAssembler::StoreStore);
3137 }
3138
3139 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3140
3141 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3142
3143 void LIR_Assembler::on_spin_wait() {
3144 __ spin_wait();
3145 }
3146
3147 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3148 __ mov(result_reg->as_register(), rthread);
3149 }
3150
3151 void LIR_Assembler::check_orig_pc() {
3152 __ ldr(rscratch2, frame_map()->address_for_orig_pc_addr());
3153 __ cmp(rscratch2, (u1)NULL_WORD);
3154 }
3155
3156 void LIR_Assembler::peephole(LIR_List *lir) {
3157 #if 0
3158 if (tableswitch_count >= max_tableswitches)
3159 return;
3160
3161 /*
3162 This finite-state automaton recognizes sequences of compare-and-
3163 branch instructions. We will turn them into a tableswitch. You
3164 could argue that C1 really shouldn't be doing this sort of
3165 optimization, but without it the code is really horrible.
3166 */
3167
3168 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3169 int first_key, last_key = -2147483648;
3170 int next_key = 0;
3171 int start_insn = -1;
3172 int last_insn = -1;
3173 Register reg = noreg;
3174 LIR_Opr reg_opr;
3175 state = start_s;
3176
3177 LIR_OpList* inst = lir->instructions_list();
3178 for (int i = 0; i < inst->length(); i++) {
3179 LIR_Op* op = inst->at(i);
3180 switch (state) {
3181 case start_s:
3182 first_key = -1;
3183 start_insn = i;
3184 switch (op->code()) {
3185 case lir_cmp:
3186 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3187 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3188 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3189 && opr2->is_constant()
3190 && opr2->type() == T_INT) {
3191 reg_opr = opr1;
3192 reg = opr1->as_register();
3193 first_key = opr2->as_constant_ptr()->as_jint();
3194 next_key = first_key + 1;
3195 state = cmp_s;
3196 goto next_state;
3197 }
3198 break;
3199 }
3200 break;
3201 case cmp_s:
3202 switch (op->code()) {
3203 case lir_branch:
3204 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3205 state = beq_s;
3206 last_insn = i;
3207 goto next_state;
3208 }
3209 }
3210 state = start_s;
3211 break;
3212 case beq_s:
3213 switch (op->code()) {
3214 case lir_cmp: {
3215 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3216 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3217 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3218 && opr1->as_register() == reg
3219 && opr2->is_constant()
3220 && opr2->type() == T_INT
3221 && opr2->as_constant_ptr()->as_jint() == next_key) {
3222 last_key = next_key;
3223 next_key++;
3224 state = cmp_s;
3225 goto next_state;
3226 }
3227 }
3228 }
3229 last_key = next_key;
3230 state = start_s;
3231 break;
3232 default:
3233 assert(false, "impossible state");
3234 }
3235 if (state == start_s) {
3236 if (first_key < last_key - 5L && reg != noreg) {
3237 {
3238 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3239 // reg->encoding(),
3240 // start_insn, first_key, last_key);
3241 // for (int i = 0; i < inst->length(); i++) {
3242 // inst->at(i)->print();
3243 // tty->print("\n");
3244 // }
3245 // tty->print("\n");
3246 }
3247
3248 struct tableswitch *sw = &switches[tableswitch_count];
3249 sw->_insn_index = start_insn, sw->_first_key = first_key,
3250 sw->_last_key = last_key, sw->_reg = reg;
3251 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3252 {
3253 // Insert the new table of branches
3254 int offset = last_insn;
3255 for (int n = first_key; n < last_key; n++) {
3256 inst->insert_before
3257 (last_insn + 1,
3258 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3259 inst->at(offset)->as_OpBranch()->label()));
3260 offset -= 2, i++;
3261 }
3262 }
3263 // Delete all the old compare-and-branch instructions
3264 for (int n = first_key; n < last_key; n++) {
3265 inst->remove_at(start_insn);
3266 inst->remove_at(start_insn);
3267 }
3268 // Insert the tableswitch instruction
3269 inst->insert_before(start_insn,
3270 new LIR_Op2(lir_cmp, lir_cond_always,
3271 LIR_OprFact::intConst(tableswitch_count),
3272 reg_opr));
3273 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3274 tableswitch_count++;
3275 }
3276 reg = noreg;
3277 last_key = -2147483648;
3278 }
3279 next_state:
3280 ;
3281 }
3282 #endif
3283 }
3284
3285 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3286 Address addr = as_Address(src->as_address_ptr());
3287 BasicType type = src->type();
3288 bool is_oop = is_reference_type(type);
3289
3290 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3291 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3292
3293 switch(type) {
3294 case T_INT:
3295 xchg = &MacroAssembler::atomic_xchgalw;
3296 add = &MacroAssembler::atomic_addalw;
3297 break;
3298 case T_LONG:
3299 xchg = &MacroAssembler::atomic_xchgal;
3300 add = &MacroAssembler::atomic_addal;
3301 break;
3302 case T_OBJECT:
3303 case T_ARRAY:
3304 if (UseCompressedOops) {
3305 xchg = &MacroAssembler::atomic_xchgalw;
3306 add = &MacroAssembler::atomic_addalw;
3307 } else {
3308 xchg = &MacroAssembler::atomic_xchgal;
3309 add = &MacroAssembler::atomic_addal;
3310 }
3311 break;
3312 default:
3313 ShouldNotReachHere();
3314 xchg = &MacroAssembler::atomic_xchgal;
3315 add = &MacroAssembler::atomic_addal; // unreachable
3316 }
3317
3318 switch (code) {
3319 case lir_xadd:
3320 {
3321 RegisterOrConstant inc;
3322 Register tmp = as_reg(tmp_op);
3323 Register dst = as_reg(dest);
3324 if (data->is_constant()) {
3325 inc = RegisterOrConstant(as_long(data));
3326 assert_different_registers(dst, addr.base(), tmp,
3327 rscratch1, rscratch2);
3328 } else {
3329 inc = RegisterOrConstant(as_reg(data));
3330 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3331 rscratch1, rscratch2);
3332 }
3333 __ lea(tmp, addr);
3334 (_masm->*add)(dst, inc, tmp);
3335 break;
3336 }
3337 case lir_xchg:
3338 {
3339 Register tmp = tmp_op->as_register();
3340 Register obj = as_reg(data);
3341 Register dst = as_reg(dest);
3342 if (is_oop && UseCompressedOops) {
3343 __ encode_heap_oop(rscratch2, obj);
3344 obj = rscratch2;
3345 }
3346 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3347 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3348 __ lea(tmp, addr);
3349 (_masm->*xchg)(dst, obj, tmp);
3350 if (is_oop && UseCompressedOops) {
3351 __ decode_heap_oop(dst);
3352 }
3353 }
3354 break;
3355 default:
3356 ShouldNotReachHere();
3357 }
3358 __ membar(__ AnyAny);
3359 }
3360
3361 #undef __