1 /*
2 * Copyright (c) 2000, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * Copyright 2026 Arm Limited and/or its affiliates.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInlineKlass.hpp"
37 #include "ci/ciInstance.hpp"
38 #include "ci/ciObjArrayKlass.hpp"
39 #include "code/aotCodeCache.hpp"
40 #include "code/compiledIC.hpp"
41 #include "gc/shared/collectedHeap.hpp"
42 #include "gc/shared/gc_globals.hpp"
43 #include "nativeInst_aarch64.hpp"
44 #include "oops/objArrayKlass.hpp"
45 #include "oops/oop.inline.hpp"
46 #include "runtime/frame.inline.hpp"
47 #include "runtime/sharedRuntime.hpp"
48 #include "runtime/stubRoutines.hpp"
49 #include "runtime/threadIdentifier.hpp"
50 #include "utilities/powerOfTwo.hpp"
51 #include "vmreg_aarch64.inline.hpp"
52
53
54 #ifndef PRODUCT
55 #define COMMENT(x) do { __ block_comment(x); } while (0)
56 #else
57 #define COMMENT(x)
58 #endif
59
60 NEEDS_CLEANUP // remove this definitions ?
61 const Register SYNC_header = r0; // synchronization header
62 const Register SHIFT_count = r0; // where count for shift operations must be
63
64 #define __ _masm->
65
66
67 static void select_different_registers(Register preserve,
68 Register extra,
69 Register &tmp1,
70 Register &tmp2,
71 Register &tmp3) {
72 if (tmp1 == preserve) {
73 assert_different_registers(tmp1, tmp2, tmp3, extra);
74 tmp1 = extra;
75 } else if (tmp2 == preserve) {
76 assert_different_registers(tmp1, tmp2, tmp3, extra);
77 tmp2 = extra;
78 } else if (tmp3 == preserve) {
79 assert_different_registers(tmp1, tmp2, tmp3, extra);
80 tmp3 = extra;
81 }
82 assert_different_registers(preserve, tmp1, tmp2, tmp3);
83 }
84
85
86 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
87
88
89 LIR_Opr LIR_Assembler::receiverOpr() {
90 return FrameMap::receiver_opr;
91 }
92
93 LIR_Opr LIR_Assembler::osrBufferPointer() {
94 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
95 }
96
97 //--------------fpu register translations-----------------------
98
99
100 address LIR_Assembler::float_constant(float f) {
101 address const_addr = __ float_constant(f);
102 if (const_addr == nullptr) {
103 bailout("const section overflow");
104 return __ code()->consts()->start();
105 } else {
106 return const_addr;
107 }
108 }
109
110
111 address LIR_Assembler::double_constant(double d) {
112 address const_addr = __ double_constant(d);
113 if (const_addr == nullptr) {
114 bailout("const section overflow");
115 return __ code()->consts()->start();
116 } else {
117 return const_addr;
118 }
119 }
120
121 address LIR_Assembler::int_constant(jlong n) {
122 address const_addr = __ long_constant(n);
123 if (const_addr == nullptr) {
124 bailout("const section overflow");
125 return __ code()->consts()->start();
126 } else {
127 return const_addr;
128 }
129 }
130
131 void LIR_Assembler::breakpoint() { Unimplemented(); }
132
133 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
134
135 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
136
137 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
138 //-------------------------------------------
139
140 static Register as_reg(LIR_Opr op) {
141 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
142 }
143
144 static jlong as_long(LIR_Opr data) {
145 jlong result;
146 switch (data->type()) {
147 case T_INT:
148 result = (data->as_jint());
149 break;
150 case T_LONG:
151 result = (data->as_jlong());
152 break;
153 default:
154 ShouldNotReachHere();
155 result = 0; // unreachable
156 }
157 return result;
158 }
159
160 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
161 Register base = addr->base()->as_pointer_register();
162 LIR_Opr opr = addr->index();
163 if (opr->is_cpu_register()) {
164 Register index;
165 if (opr->is_single_cpu())
166 index = opr->as_register();
167 else
168 index = opr->as_register_lo();
169 assert(addr->disp() == 0, "must be");
170 switch(opr->type()) {
171 case T_INT:
172 return Address(base, index, Address::sxtw(addr->scale()));
173 case T_LONG:
174 return Address(base, index, Address::lsl(addr->scale()));
175 default:
176 ShouldNotReachHere();
177 }
178 } else {
179 assert(addr->scale() == 0,
180 "expected for immediate operand, was: %d", addr->scale());
181 ptrdiff_t offset = ptrdiff_t(addr->disp());
182 // NOTE: Does not handle any 16 byte vector access.
183 const uint type_size = type2aelembytes(addr->type(), true);
184 return __ legitimize_address(Address(base, offset), type_size, tmp);
185 }
186 return Address();
187 }
188
189 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
190 ShouldNotReachHere();
191 return Address();
192 }
193
194 Address LIR_Assembler::as_Address(LIR_Address* addr) {
195 return as_Address(addr, rscratch1);
196 }
197
198 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
199 return as_Address(addr, rscratch1); // Ouch
200 // FIXME: This needs to be much more clever. See x86.
201 }
202
203 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
204 // not encodable as a base + (immediate) offset, generate an explicit address
205 // calculation to hold the address in a temporary register.
206 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
207 precond(size == 4 || size == 8);
208 Address addr = frame_map()->address_for_slot(index, adjust);
209 precond(addr.getMode() == Address::base_plus_offset);
210 precond(addr.base() == sp);
211 precond(addr.offset() > 0);
212 uint mask = size - 1;
213 assert((addr.offset() & mask) == 0, "scaled offsets only");
214 return __ legitimize_address(addr, size, tmp);
215 }
216
217 void LIR_Assembler::osr_entry() {
218 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
219 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
220 ValueStack* entry_state = osr_entry->state();
221 int number_of_locks = entry_state->locks_size();
222
223 // we jump here if osr happens with the interpreter
224 // state set up to continue at the beginning of the
225 // loop that triggered osr - in particular, we have
226 // the following registers setup:
227 //
228 // r2: osr buffer
229 //
230
231 // build frame
232 ciMethod* m = compilation()->method();
233 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
234
235 // OSR buffer is
236 //
237 // locals[nlocals-1..0]
238 // monitors[0..number_of_locks]
239 //
240 // locals is a direct copy of the interpreter frame so in the osr buffer
241 // so first slot in the local array is the last local from the interpreter
242 // and last slot is local[0] (receiver) from the interpreter
243 //
244 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
245 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
246 // in the interpreter frame (the method lock if a sync method)
247
248 // Initialize monitors in the compiled activation.
249 // r2: pointer to osr buffer
250 //
251 // All other registers are dead at this point and the locals will be
252 // copied into place by code emitted in the IR.
253
254 Register OSR_buf = osrBufferPointer()->as_pointer_register();
255 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
256 int monitor_offset = BytesPerWord * method()->max_locals() +
257 (2 * BytesPerWord) * (number_of_locks - 1);
258 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
259 // the OSR buffer using 2 word entries: first the lock and then
260 // the oop.
261 for (int i = 0; i < number_of_locks; i++) {
262 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
263 #ifdef ASSERT
264 // verify the interpreter's monitor has a non-null object
265 {
266 Label L;
267 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
268 __ cbnz(rscratch1, L);
269 __ stop("locked object is null");
270 __ bind(L);
271 }
272 #endif
273 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
274 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
275 __ str(r19, frame_map()->address_for_monitor_lock(i));
276 __ str(r20, frame_map()->address_for_monitor_object(i));
277 }
278 }
279 }
280
281
282 // inline cache check; done before the frame is built.
283 int LIR_Assembler::check_icache() {
284 return __ ic_check(CodeEntryAlignment);
285 }
286
287 void LIR_Assembler::clinit_barrier(ciMethod* method) {
288 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
289 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
290
291 Label L_skip_barrier;
292
293 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
294 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
295 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
296 __ bind(L_skip_barrier);
297 }
298
299 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
300 if (o == nullptr) {
301 __ mov(reg, zr);
302 } else {
303 __ movoop(reg, o);
304 }
305 }
306
307 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
308 address target = nullptr;
309 relocInfo::relocType reloc_type = relocInfo::none;
310
311 switch (patching_id(info)) {
312 case PatchingStub::access_field_id:
313 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
314 reloc_type = relocInfo::section_word_type;
315 break;
316 case PatchingStub::load_klass_id:
317 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
318 reloc_type = relocInfo::metadata_type;
319 break;
320 case PatchingStub::load_mirror_id:
321 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
322 reloc_type = relocInfo::oop_type;
323 break;
324 case PatchingStub::load_appendix_id:
325 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
326 reloc_type = relocInfo::oop_type;
327 break;
328 default: ShouldNotReachHere();
329 }
330
331 __ far_call(RuntimeAddress(target));
332 add_call_info_here(info);
333 }
334
335 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
336 deoptimize_trap(info);
337 }
338
339
340 // This specifies the rsp decrement needed to build the frame
341 int LIR_Assembler::initial_frame_size_in_bytes() const {
342 // if rounding, must let FrameMap know!
343
344 return in_bytes(frame_map()->framesize_in_bytes());
345 }
346
347
348 int LIR_Assembler::emit_exception_handler() {
349 // generate code for exception handler
350 address handler_base = __ start_a_stub(exception_handler_size());
351 if (handler_base == nullptr) {
352 // not enough space left for the handler
353 bailout("exception handler overflow");
354 return -1;
355 }
356
357 int offset = code_offset();
358
359 // the exception oop and pc are in r0, and r3
360 // no other registers need to be preserved, so invalidate them
361 __ invalidate_registers(false, true, true, false, true, true);
362
363 // check that there is really an exception
364 __ verify_not_null_oop(r0);
365
366 // search an exception handler (r0: exception oop, r3: throwing pc)
367 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
368 __ should_not_reach_here();
369 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
370 __ end_a_stub();
371
372 return offset;
373 }
374
375
376 // Emit the code to remove the frame from the stack in the exception
377 // unwind path.
378 int LIR_Assembler::emit_unwind_handler() {
379 #ifndef PRODUCT
380 if (CommentedAssembly) {
381 _masm->block_comment("Unwind handler");
382 }
383 #endif
384
385 int offset = code_offset();
386
387 // Fetch the exception from TLS and clear out exception related thread state
388 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
389 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
390 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
391
392 __ bind(_unwind_handler_entry);
393 __ verify_not_null_oop(r0);
394 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
395 __ mov(r19, r0); // Preserve the exception
396 }
397
398 // Perform needed unlocking
399 MonitorExitStub* stub = nullptr;
400 if (method()->is_synchronized()) {
401 monitor_address(0, FrameMap::r0_opr);
402 stub = new MonitorExitStub(FrameMap::r0_opr, 0);
403 __ unlock_object(r5, r4, r0, r6, *stub->entry());
404 __ bind(*stub->continuation());
405 }
406
407 if (compilation()->env()->dtrace_method_probes()) {
408 __ mov(c_rarg0, rthread);
409 __ mov_metadata(c_rarg1, method()->constant_encoding());
410 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
411 }
412
413 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
414 __ mov(r0, r19); // Restore the exception
415 }
416
417 // remove the activation and dispatch to the unwind handler
418 __ block_comment("remove_frame and dispatch to the unwind handler");
419 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
420 __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
421
422 // Emit the slow path assembly
423 if (stub != nullptr) {
424 stub->emit_code(this);
425 }
426
427 return offset;
428 }
429
430
431 int LIR_Assembler::emit_deopt_handler() {
432 // generate code for exception handler
433 address handler_base = __ start_a_stub(deopt_handler_size());
434 if (handler_base == nullptr) {
435 // not enough space left for the handler
436 bailout("deopt handler overflow");
437 return -1;
438 }
439
440 int offset = code_offset();
441
442 Label start;
443 __ bind(start);
444
445 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
446
447 int entry_offset = __ offset();
448 __ b(start);
449
450 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
451 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
452 "out of bounds read in post-call NOP check");
453 __ end_a_stub();
454
455 return entry_offset;
456 }
457
458 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
459 _masm->code_section()->relocate(adr, relocInfo::poll_type);
460 int pc_offset = code_offset();
461 flush_debug_info(pc_offset);
462 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
463 if (info->exception_handlers() != nullptr) {
464 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
465 }
466 }
467
468 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
469 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
470
471 if (InlineTypeReturnedAsFields) {
472 // Check if we are returning an non-null inline type and load its fields into registers
473 ciType* return_type = compilation()->method()->return_type();
474 if (return_type->is_inlinetype()) {
475 ciInlineKlass* vk = return_type->as_inline_klass();
476 if (vk->can_be_returned_as_fields()) {
477 address unpack_handler = vk->unpack_handler();
478 assert(unpack_handler != nullptr, "must be");
479 __ far_call(RuntimeAddress(unpack_handler));
480 }
481 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) {
482 Label skip;
483 Label not_null;
484 __ cbnz(r0, not_null);
485 // Returned value is null, zero all return registers because they may belong to oop fields
486 __ mov(j_rarg1, zr);
487 __ mov(j_rarg2, zr);
488 __ mov(j_rarg3, zr);
489 __ mov(j_rarg4, zr);
490 __ mov(j_rarg5, zr);
491 __ mov(j_rarg6, zr);
492 __ mov(j_rarg7, zr);
493 __ b(skip);
494 __ bind(not_null);
495
496 // Check if we are returning an non-null inline type and load its fields into registers
497 __ test_oop_is_not_inline_type(r0, rscratch2, skip, /* can_be_null= */ false);
498
499 // Load fields from a buffered value with an inline class specific handler
500 __ load_klass(rscratch1 /*dst*/, r0 /*src*/);
501 __ ldr(rscratch1, Address(rscratch1, InlineKlass::adr_members_offset()));
502 __ ldr(rscratch1, Address(rscratch1, InlineKlass::unpack_handler_offset()));
503 // Unpack handler can be null if inline type is not scalarizable in returns
504 __ cbz(rscratch1, skip);
505 __ blr(rscratch1);
506
507 __ bind(skip);
508 }
509 // At this point, r0 points to the value object (for interpreter or C1 caller).
510 // The fields of the object are copied into registers (for C2 caller).
511 }
512
513 // Pop the stack before the safepoint code
514 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
515
516 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
517 __ reserved_stack_check();
518 }
519
520 code_stub->set_safepoint_offset(__ offset());
521 __ relocate(relocInfo::poll_return_type);
522 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
523 __ ret(lr);
524 }
525
526 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
527 return (__ store_inline_type_fields_to_buf(vk, false));
528 }
529
530 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
531 guarantee(info != nullptr, "Shouldn't be null");
532 __ get_polling_page(rscratch1, relocInfo::poll_type);
533 add_debug_info_for_branch(info); // This isn't just debug info:
534 // it's the oop map
535 __ read_polling_page(rscratch1, relocInfo::poll_type);
536 return __ offset();
537 }
538
539
540 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
541 if (from_reg == r31_sp)
542 from_reg = sp;
543 if (to_reg == r31_sp)
544 to_reg = sp;
545 __ mov(to_reg, from_reg);
546 }
547
548 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
549
550
551 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
552 assert(src->is_constant(), "should not call otherwise");
553 assert(dest->is_register(), "should not call otherwise");
554 LIR_Const* c = src->as_constant_ptr();
555
556 switch (c->type()) {
557 case T_INT: {
558 assert(patch_code == lir_patch_none, "no patching handled here");
559 __ movw(dest->as_register(), c->as_jint());
560 break;
561 }
562
563 case T_ADDRESS: {
564 assert(patch_code == lir_patch_none, "no patching handled here");
565 __ mov(dest->as_register(), c->as_jint());
566 break;
567 }
568
569 case T_LONG: {
570 assert(patch_code == lir_patch_none, "no patching handled here");
571 #if INCLUDE_CDS
572 if (AOTCodeCache::is_on_for_dump()) {
573 address b = c->as_pointer();
574 if (b == (address)ThreadIdentifier::unsafe_offset()) {
575 __ lea(dest->as_register_lo(), ExternalAddress(b));
576 break;
577 }
578 if (AOTRuntimeConstants::contains(b)) {
579 __ load_aotrc_address(dest->as_register_lo(), b);
580 break;
581 }
582 }
583 #endif
584 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
585 break;
586 }
587
588 case T_OBJECT: {
589 if (patch_code != lir_patch_none) {
590 jobject2reg_with_patching(dest->as_register(), info);
591 } else {
592 jobject2reg(c->as_jobject(), dest->as_register());
593 }
594 break;
595 }
596
597 case T_METADATA: {
598 if (patch_code != lir_patch_none) {
599 klass2reg_with_patching(dest->as_register(), info);
600 } else {
601 __ mov_metadata(dest->as_register(), c->as_metadata());
602 }
603 break;
604 }
605
606 case T_FLOAT: {
607 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
608 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
609 } else {
610 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
611 __ ldrs(dest->as_float_reg(), Address(rscratch1));
612 }
613 break;
614 }
615
616 case T_DOUBLE: {
617 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
618 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
619 } else {
620 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
621 __ ldrd(dest->as_double_reg(), Address(rscratch1));
622 }
623 break;
624 }
625
626 default:
627 ShouldNotReachHere();
628 }
629 }
630
631 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
632 LIR_Const* c = src->as_constant_ptr();
633 switch (c->type()) {
634 case T_OBJECT:
635 {
636 if (! c->as_jobject())
637 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
638 else {
639 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
640 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
641 }
642 }
643 break;
644 case T_ADDRESS:
645 {
646 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
647 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
648 }
649 case T_INT:
650 case T_FLOAT:
651 {
652 Register reg = zr;
653 if (c->as_jint_bits() == 0)
654 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
655 else {
656 __ movw(rscratch1, c->as_jint_bits());
657 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
658 }
659 }
660 break;
661 case T_LONG:
662 case T_DOUBLE:
663 {
664 Register reg = zr;
665 if (c->as_jlong_bits() == 0)
666 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
667 lo_word_offset_in_bytes));
668 else {
669 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
670 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
671 lo_word_offset_in_bytes));
672 }
673 }
674 break;
675 default:
676 ShouldNotReachHere();
677 }
678 }
679
680 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
681 assert(src->is_constant(), "should not call otherwise");
682 LIR_Const* c = src->as_constant_ptr();
683 LIR_Address* to_addr = dest->as_address_ptr();
684
685 void (Assembler::* insn)(Register Rt, const Address &adr);
686
687 switch (type) {
688 case T_ADDRESS:
689 assert(c->as_jint() == 0, "should be");
690 insn = &Assembler::str;
691 break;
692 case T_LONG:
693 assert(c->as_jlong() == 0, "should be");
694 insn = &Assembler::str;
695 break;
696 case T_INT:
697 assert(c->as_jint() == 0, "should be");
698 insn = &Assembler::strw;
699 break;
700 case T_OBJECT:
701 case T_ARRAY:
702 assert(c->as_jobject() == nullptr, "should be");
703 if (UseCompressedOops && !wide) {
704 insn = &Assembler::strw;
705 } else {
706 insn = &Assembler::str;
707 }
708 break;
709 case T_CHAR:
710 case T_SHORT:
711 assert(c->as_jint() == 0, "should be");
712 insn = &Assembler::strh;
713 break;
714 case T_BOOLEAN:
715 case T_BYTE:
716 assert(c->as_jint() == 0, "should be");
717 insn = &Assembler::strb;
718 break;
719 default:
720 ShouldNotReachHere();
721 insn = &Assembler::str; // unreachable
722 }
723
724 if (info) add_debug_info_for_null_check_here(info);
725 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
726 }
727
728 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
729 assert(src->is_register(), "should not call otherwise");
730 assert(dest->is_register(), "should not call otherwise");
731
732 // move between cpu-registers
733 if (dest->is_single_cpu()) {
734 if (src->type() == T_LONG) {
735 // Can do LONG -> OBJECT
736 move_regs(src->as_register_lo(), dest->as_register());
737 return;
738 }
739 assert(src->is_single_cpu(), "must match");
740 if (src->type() == T_OBJECT) {
741 __ verify_oop(src->as_register());
742 }
743 move_regs(src->as_register(), dest->as_register());
744
745 } else if (dest->is_double_cpu()) {
746 if (is_reference_type(src->type())) {
747 // Surprising to me but we can see move of a long to t_object
748 __ verify_oop(src->as_register());
749 move_regs(src->as_register(), dest->as_register_lo());
750 return;
751 }
752 assert(src->is_double_cpu(), "must match");
753 Register f_lo = src->as_register_lo();
754 Register f_hi = src->as_register_hi();
755 Register t_lo = dest->as_register_lo();
756 Register t_hi = dest->as_register_hi();
757 assert(f_hi == f_lo, "must be same");
758 assert(t_hi == t_lo, "must be same");
759 move_regs(f_lo, t_lo);
760
761 } else if (dest->is_single_fpu()) {
762 __ fmovs(dest->as_float_reg(), src->as_float_reg());
763
764 } else if (dest->is_double_fpu()) {
765 __ fmovd(dest->as_double_reg(), src->as_double_reg());
766
767 } else {
768 ShouldNotReachHere();
769 }
770 }
771
772 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
773 precond(src->is_register() && dest->is_stack());
774
775 uint const c_sz32 = sizeof(uint32_t);
776 uint const c_sz64 = sizeof(uint64_t);
777
778 if (src->is_single_cpu()) {
779 int index = dest->single_stack_ix();
780 if (is_reference_type(type)) {
781 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
782 __ verify_oop(src->as_register());
783 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
784 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
785 } else {
786 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
787 }
788
789 } else if (src->is_double_cpu()) {
790 int index = dest->double_stack_ix();
791 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
792 __ str(src->as_register_lo(), dest_addr_LO);
793
794 } else if (src->is_single_fpu()) {
795 int index = dest->single_stack_ix();
796 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
797
798 } else if (src->is_double_fpu()) {
799 int index = dest->double_stack_ix();
800 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
801
802 } else {
803 ShouldNotReachHere();
804 }
805 }
806
807
808 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
809 LIR_Address* to_addr = dest->as_address_ptr();
810 PatchingStub* patch = nullptr;
811 Register compressed_src = rscratch1;
812
813 if (patch_code != lir_patch_none) {
814 deoptimize_trap(info);
815 return;
816 }
817
818 if (is_reference_type(type)) {
819 __ verify_oop(src->as_register());
820
821 if (UseCompressedOops && !wide) {
822 __ encode_heap_oop(compressed_src, src->as_register());
823 } else {
824 compressed_src = src->as_register();
825 }
826 }
827
828 int null_check_here = code_offset();
829 switch (type) {
830 case T_FLOAT: {
831 __ strs(src->as_float_reg(), as_Address(to_addr));
832 break;
833 }
834
835 case T_DOUBLE: {
836 __ strd(src->as_double_reg(), as_Address(to_addr));
837 break;
838 }
839
840 case T_ARRAY: // fall through
841 case T_OBJECT: // fall through
842 if (UseCompressedOops && !wide) {
843 __ strw(compressed_src, as_Address(to_addr, rscratch2));
844 } else {
845 __ str(compressed_src, as_Address(to_addr));
846 }
847 break;
848 case T_METADATA:
849 // We get here to store a method pointer to the stack to pass to
850 // a dtrace runtime call. This can't work on 64 bit with
851 // compressed klass ptrs: T_METADATA can be a compressed klass
852 // ptr or a 64 bit method pointer.
853 ShouldNotReachHere();
854 __ str(src->as_register(), as_Address(to_addr));
855 break;
856 case T_ADDRESS:
857 __ str(src->as_register(), as_Address(to_addr));
858 break;
859 case T_INT:
860 __ strw(src->as_register(), as_Address(to_addr));
861 break;
862
863 case T_LONG: {
864 __ str(src->as_register_lo(), as_Address_lo(to_addr));
865 break;
866 }
867
868 case T_BYTE: // fall through
869 case T_BOOLEAN: {
870 __ strb(src->as_register(), as_Address(to_addr));
871 break;
872 }
873
874 case T_CHAR: // fall through
875 case T_SHORT:
876 __ strh(src->as_register(), as_Address(to_addr));
877 break;
878
879 default:
880 ShouldNotReachHere();
881 }
882 if (info != nullptr) {
883 add_debug_info_for_null_check(null_check_here, info);
884 }
885 }
886
887
888 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
889 precond(src->is_stack() && dest->is_register());
890
891 uint const c_sz32 = sizeof(uint32_t);
892 uint const c_sz64 = sizeof(uint64_t);
893
894 if (dest->is_single_cpu()) {
895 int index = src->single_stack_ix();
896 if (is_reference_type(type)) {
897 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
898 __ verify_oop(dest->as_register());
899 } else if (type == T_METADATA || type == T_ADDRESS) {
900 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
901 } else {
902 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
903 }
904
905 } else if (dest->is_double_cpu()) {
906 int index = src->double_stack_ix();
907 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
908 __ ldr(dest->as_register_lo(), src_addr_LO);
909
910 } else if (dest->is_single_fpu()) {
911 int index = src->single_stack_ix();
912 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
913
914 } else if (dest->is_double_fpu()) {
915 int index = src->double_stack_ix();
916 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
917
918 } else {
919 ShouldNotReachHere();
920 }
921 }
922
923
924 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
925 address target = nullptr;
926 relocInfo::relocType reloc_type = relocInfo::none;
927
928 switch (patching_id(info)) {
929 case PatchingStub::access_field_id:
930 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
931 reloc_type = relocInfo::section_word_type;
932 break;
933 case PatchingStub::load_klass_id:
934 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
935 reloc_type = relocInfo::metadata_type;
936 break;
937 case PatchingStub::load_mirror_id:
938 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
939 reloc_type = relocInfo::oop_type;
940 break;
941 case PatchingStub::load_appendix_id:
942 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
943 reloc_type = relocInfo::oop_type;
944 break;
945 default: ShouldNotReachHere();
946 }
947
948 __ far_call(RuntimeAddress(target));
949 add_call_info_here(info);
950 }
951
952 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
953
954 LIR_Opr temp;
955 if (type == T_LONG || type == T_DOUBLE)
956 temp = FrameMap::rscratch1_long_opr;
957 else
958 temp = FrameMap::rscratch1_opr;
959
960 stack2reg(src, temp, src->type());
961 reg2stack(temp, dest, dest->type());
962 }
963
964 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
965 LIR_PatchCode patch_code, CodeEmitInfo* info,
966 bool wide) {
967 mem2reg(src, dest, type, patch_code, info, wide, false);
968 }
969
970 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
971 LIR_PatchCode patch_code, CodeEmitInfo* info,
972 bool wide, bool is_volatile) {
973 LIR_Address* addr = src->as_address_ptr();
974 LIR_Address* from_addr = src->as_address_ptr();
975
976 if (addr->base()->type() == T_OBJECT) {
977 __ verify_oop(addr->base()->as_pointer_register());
978 }
979
980 if (patch_code != lir_patch_none) {
981 deoptimize_trap(info);
982 return;
983 }
984
985 if (is_volatile) {
986 load_volatile(from_addr, dest, type, info);
987 } else {
988 load_unordered(from_addr, dest, type, wide, info);
989 }
990
991 if (is_reference_type(type)) {
992 if (UseCompressedOops && !wide) {
993 __ decode_heap_oop(dest->as_register());
994 }
995
996 __ verify_oop(dest->as_register());
997 }
998 }
999
1000 void LIR_Assembler::load_unordered(LIR_Address *from_addr, LIR_Opr dest,
1001 BasicType type, bool wide, CodeEmitInfo* info) {
1002 if (info != nullptr) {
1003 add_debug_info_for_null_check_here(info);
1004 }
1005
1006 switch (type) {
1007 case T_FLOAT: {
1008 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
1009 break;
1010 }
1011
1012 case T_DOUBLE: {
1013 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
1014 break;
1015 }
1016
1017 case T_ARRAY: // fall through
1018 case T_OBJECT: // fall through
1019 if (UseCompressedOops && !wide) {
1020 __ ldrw(dest->as_register(), as_Address(from_addr));
1021 } else {
1022 __ ldr(dest->as_register(), as_Address(from_addr));
1023 }
1024 break;
1025 case T_METADATA:
1026 // We get here to store a method pointer to the stack to pass to
1027 // a dtrace runtime call. This can't work on 64 bit with
1028 // compressed klass ptrs: T_METADATA can be a compressed klass
1029 // ptr or a 64 bit method pointer.
1030 ShouldNotReachHere();
1031 __ ldr(dest->as_register(), as_Address(from_addr));
1032 break;
1033 case T_ADDRESS:
1034 __ ldr(dest->as_register(), as_Address(from_addr));
1035 break;
1036 case T_INT:
1037 __ ldrw(dest->as_register(), as_Address(from_addr));
1038 break;
1039
1040 case T_LONG: {
1041 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1042 break;
1043 }
1044
1045 case T_BYTE:
1046 __ ldrsb(dest->as_register(), as_Address(from_addr));
1047 break;
1048 case T_BOOLEAN: {
1049 __ ldrb(dest->as_register(), as_Address(from_addr));
1050 break;
1051 }
1052
1053 case T_CHAR:
1054 __ ldrh(dest->as_register(), as_Address(from_addr));
1055 break;
1056 case T_SHORT:
1057 __ ldrsh(dest->as_register(), as_Address(from_addr));
1058 break;
1059
1060 default:
1061 ShouldNotReachHere();
1062 }
1063 }
1064
1065 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
1066 assert(dst->is_cpu_register(), "must be");
1067 assert(dst->type() == src->type(), "must be");
1068
1069 if (src->is_cpu_register()) {
1070 reg2reg(src, dst);
1071 } else if (src->is_stack()) {
1072 stack2reg(src, dst, dst->type());
1073 } else if (src->is_constant()) {
1074 const2reg(src, dst, lir_patch_none, nullptr);
1075 } else {
1076 ShouldNotReachHere();
1077 }
1078 }
1079
1080 void LIR_Assembler::load_volatile(LIR_Address *from_addr, LIR_Opr dest,
1081 BasicType type, CodeEmitInfo* info) {
1082 __ lea(rscratch1, as_Address(from_addr));
1083
1084 Register dest_reg = rscratch2;
1085 if (!is_floating_point_type(type)) {
1086 dest_reg = (dest->is_single_cpu()
1087 ? dest->as_register() : dest->as_register_lo());
1088 }
1089
1090 if (info != nullptr) {
1091 add_debug_info_for_null_check_here(info);
1092 }
1093
1094 // Uses LDAR to ensure memory ordering.
1095 __ load_store_volatile(dest_reg, type, rscratch1, /*is_load*/true);
1096
1097 switch (type) {
1098 // LDAR is unsigned so need to sign-extend for byte and short
1099 case T_BYTE:
1100 __ sxtb(dest_reg, dest_reg);
1101 break;
1102 case T_SHORT:
1103 __ sxth(dest_reg, dest_reg);
1104 break;
1105 // need to move from GPR to FPR after LDAR with FMOV for floating types
1106 case T_FLOAT:
1107 __ fmovs(dest->as_float_reg(), dest_reg);
1108 break;
1109 case T_DOUBLE:
1110 __ fmovd(dest->as_double_reg(), dest_reg);
1111 break;
1112 default:
1113 break;
1114 }
1115 }
1116
1117 int LIR_Assembler::array_element_size(BasicType type) const {
1118 int elem_size = type2aelembytes(type);
1119 return exact_log2(elem_size);
1120 }
1121
1122
1123 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1124 switch (op->code()) {
1125 case lir_idiv:
1126 case lir_irem:
1127 arithmetic_idiv(op->code(),
1128 op->in_opr1(),
1129 op->in_opr2(),
1130 op->in_opr3(),
1131 op->result_opr(),
1132 op->info());
1133 break;
1134 case lir_fmad:
1135 __ fmaddd(op->result_opr()->as_double_reg(),
1136 op->in_opr1()->as_double_reg(),
1137 op->in_opr2()->as_double_reg(),
1138 op->in_opr3()->as_double_reg());
1139 break;
1140 case lir_fmaf:
1141 __ fmadds(op->result_opr()->as_float_reg(),
1142 op->in_opr1()->as_float_reg(),
1143 op->in_opr2()->as_float_reg(),
1144 op->in_opr3()->as_float_reg());
1145 break;
1146 default: ShouldNotReachHere(); break;
1147 }
1148 }
1149
1150 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1151 #ifdef ASSERT
1152 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1153 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1154 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1155 #endif
1156
1157 if (op->cond() == lir_cond_always) {
1158 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1159 __ b(*(op->label()));
1160 } else {
1161 Assembler::Condition acond;
1162 if (op->code() == lir_cond_float_branch) {
1163 bool is_unordered = (op->ublock() == op->block());
1164 // Assembler::EQ does not permit unordered branches, so we add
1165 // another branch here. Likewise, Assembler::NE does not permit
1166 // ordered branches.
1167 if ((is_unordered && op->cond() == lir_cond_equal)
1168 || (!is_unordered && op->cond() == lir_cond_notEqual))
1169 __ br(Assembler::VS, *(op->ublock()->label()));
1170 switch(op->cond()) {
1171 case lir_cond_equal: acond = Assembler::EQ; break;
1172 case lir_cond_notEqual: acond = Assembler::NE; break;
1173 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1174 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1175 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1176 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1177 default: ShouldNotReachHere();
1178 acond = Assembler::EQ; // unreachable
1179 }
1180 } else {
1181 switch (op->cond()) {
1182 case lir_cond_equal: acond = Assembler::EQ; break;
1183 case lir_cond_notEqual: acond = Assembler::NE; break;
1184 case lir_cond_less: acond = Assembler::LT; break;
1185 case lir_cond_lessEqual: acond = Assembler::LE; break;
1186 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1187 case lir_cond_greater: acond = Assembler::GT; break;
1188 case lir_cond_belowEqual: acond = Assembler::LS; break;
1189 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1190 default: ShouldNotReachHere();
1191 acond = Assembler::EQ; // unreachable
1192 }
1193 }
1194 __ br(acond,*(op->label()));
1195 }
1196 }
1197
1198
1199
1200 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1201 LIR_Opr src = op->in_opr();
1202 LIR_Opr dest = op->result_opr();
1203
1204 switch (op->bytecode()) {
1205 case Bytecodes::_i2f:
1206 {
1207 __ scvtfws(dest->as_float_reg(), src->as_register());
1208 break;
1209 }
1210 case Bytecodes::_i2d:
1211 {
1212 __ scvtfwd(dest->as_double_reg(), src->as_register());
1213 break;
1214 }
1215 case Bytecodes::_l2d:
1216 {
1217 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1218 break;
1219 }
1220 case Bytecodes::_l2f:
1221 {
1222 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1223 break;
1224 }
1225 case Bytecodes::_f2d:
1226 {
1227 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1228 break;
1229 }
1230 case Bytecodes::_d2f:
1231 {
1232 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1233 break;
1234 }
1235 case Bytecodes::_i2c:
1236 {
1237 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1238 break;
1239 }
1240 case Bytecodes::_i2l:
1241 {
1242 __ sxtw(dest->as_register_lo(), src->as_register());
1243 break;
1244 }
1245 case Bytecodes::_i2s:
1246 {
1247 __ sxth(dest->as_register(), src->as_register());
1248 break;
1249 }
1250 case Bytecodes::_i2b:
1251 {
1252 __ sxtb(dest->as_register(), src->as_register());
1253 break;
1254 }
1255 case Bytecodes::_l2i:
1256 {
1257 _masm->block_comment("FIXME: This could be a no-op");
1258 __ uxtw(dest->as_register(), src->as_register_lo());
1259 break;
1260 }
1261 case Bytecodes::_d2l:
1262 {
1263 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1264 break;
1265 }
1266 case Bytecodes::_f2i:
1267 {
1268 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1269 break;
1270 }
1271 case Bytecodes::_f2l:
1272 {
1273 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1274 break;
1275 }
1276 case Bytecodes::_d2i:
1277 {
1278 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1279 break;
1280 }
1281 default: ShouldNotReachHere();
1282 }
1283 }
1284
1285 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1286 if (op->init_check()) {
1287 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1288 __ ldarb(rscratch1, rscratch1);
1289 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1290 add_debug_info_for_null_check_here(op->stub()->info());
1291 __ br(Assembler::NE, *op->stub()->entry());
1292 }
1293 __ allocate_object(op->obj()->as_register(),
1294 op->tmp1()->as_register(),
1295 op->tmp2()->as_register(),
1296 op->header_size(),
1297 op->object_size(),
1298 op->klass()->as_register(),
1299 *op->stub()->entry());
1300 __ bind(*op->stub()->continuation());
1301 }
1302
1303 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1304 Register len = op->len()->as_register();
1305 __ uxtw(len, len);
1306
1307 if (UseSlowPath || op->always_slow_path() ||
1308 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1309 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1310 __ b(*op->stub()->entry());
1311 } else {
1312 Register tmp1 = op->tmp1()->as_register();
1313 Register tmp2 = op->tmp2()->as_register();
1314 Register tmp3 = op->tmp3()->as_register();
1315 if (len == tmp1) {
1316 tmp1 = tmp3;
1317 } else if (len == tmp2) {
1318 tmp2 = tmp3;
1319 } else if (len == tmp3) {
1320 // everything is ok
1321 } else {
1322 __ mov(tmp3, len);
1323 }
1324 __ allocate_array(op->obj()->as_register(),
1325 len,
1326 tmp1,
1327 tmp2,
1328 arrayOopDesc::base_offset_in_bytes(op->type()),
1329 array_element_size(op->type()),
1330 op->klass()->as_register(),
1331 *op->stub()->entry(),
1332 op->zero_array());
1333 }
1334 __ bind(*op->stub()->continuation());
1335 }
1336
1337 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md,
1338 ciProfileData *data, Register recv) {
1339
1340 int mdp_offset = md->byte_offset_of_slot(data, in_ByteSize(0));
1341 __ profile_receiver_type(recv, mdo, mdp_offset);
1342 }
1343
1344 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1345 // we always need a stub for the failure case.
1346 CodeStub* stub = op->stub();
1347 Register obj = op->object()->as_register();
1348 Register k_RInfo = op->tmp1()->as_register();
1349 Register klass_RInfo = op->tmp2()->as_register();
1350 Register dst = op->result_opr()->as_register();
1351 ciKlass* k = op->klass();
1352 Register Rtmp1 = noreg;
1353
1354 // check if it needs to be profiled
1355 ciMethodData* md;
1356 ciProfileData* data;
1357
1358 const bool should_profile = op->should_profile();
1359
1360 if (should_profile) {
1361 ciMethod* method = op->profiled_method();
1362 assert(method != nullptr, "Should have method");
1363 int bci = op->profiled_bci();
1364 md = method->method_data_or_null();
1365 assert(md != nullptr, "Sanity");
1366 data = md->bci_to_data(bci);
1367 assert(data != nullptr, "need data for type check");
1368 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1369 }
1370 Label* success_target = success;
1371 Label* failure_target = failure;
1372
1373 if (obj == k_RInfo) {
1374 k_RInfo = dst;
1375 } else if (obj == klass_RInfo) {
1376 klass_RInfo = dst;
1377 }
1378
1379 Rtmp1 = op->tmp3()->as_register();
1380 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1381
1382 assert_different_registers(obj, k_RInfo, klass_RInfo);
1383
1384 if (op->need_null_check()) {
1385 if (should_profile) {
1386 Register mdo = klass_RInfo;
1387 __ mov_metadata(mdo, md->constant_encoding());
1388 Label not_null;
1389 __ cbnz(obj, not_null);
1390 // Object is null; update MDO and exit
1391 Address data_addr
1392 = __ form_address(rscratch2, mdo,
1393 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1394 0);
1395 __ ldrb(rscratch1, data_addr);
1396 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1397 __ strb(rscratch1, data_addr);
1398 __ b(*obj_is_null);
1399 __ bind(not_null);
1400
1401 Register recv = k_RInfo;
1402 __ load_klass(recv, obj);
1403 type_profile_helper(mdo, md, data, recv);
1404 } else {
1405 __ cbz(obj, *obj_is_null);
1406 }
1407 }
1408
1409 if (!k->is_loaded()) {
1410 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1411 } else {
1412 __ mov_metadata(k_RInfo, k->constant_encoding());
1413 }
1414 __ verify_oop(obj);
1415
1416 if (op->fast_check()) {
1417 assert(!k->is_loaded() || !k->is_obj_array_klass(), "Use refined array for a direct pointer comparison");
1418 // get object class
1419 // not a safepoint as obj null check happens earlier
1420 __ load_klass(rscratch1, obj);
1421 __ cmp( rscratch1, k_RInfo);
1422
1423 __ br(Assembler::NE, *failure_target);
1424 // successful cast, fall through to profile or jump
1425 } else {
1426 // get object class
1427 // not a safepoint as obj null check happens earlier
1428 __ load_klass(klass_RInfo, obj);
1429 if (k->is_loaded()) {
1430 // See if we get an immediate positive hit
1431 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1432 __ cmp(k_RInfo, rscratch1);
1433 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1434 __ br(Assembler::NE, *failure_target);
1435 // successful cast, fall through to profile or jump
1436 } else {
1437 // See if we get an immediate positive hit
1438 __ br(Assembler::EQ, *success_target);
1439 // check for self
1440 if (k->is_loaded() && k->is_obj_array_klass()) {
1441 // For a direct pointer comparison, we need the refined array klass pointer
1442 ciKlass* k_refined = ciObjArrayKlass::make(k->as_obj_array_klass()->element_klass());
1443 __ mov_metadata(rscratch1, k_refined->constant_encoding());
1444 __ cmp(klass_RInfo, rscratch1);
1445 } else {
1446 __ cmp(klass_RInfo, k_RInfo);
1447 }
1448 __ br(Assembler::EQ, *success_target);
1449
1450 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1451 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1452 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1453 // result is a boolean
1454 __ cbzw(klass_RInfo, *failure_target);
1455 // successful cast, fall through to profile or jump
1456 }
1457 } else {
1458 // perform the fast part of the checking logic
1459 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1460 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1461 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1462 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1463 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1464 // result is a boolean
1465 __ cbz(k_RInfo, *failure_target);
1466 // successful cast, fall through to profile or jump
1467 }
1468 }
1469 __ b(*success);
1470 }
1471
1472
1473 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1474 const bool should_profile = op->should_profile();
1475
1476 LIR_Code code = op->code();
1477 if (code == lir_store_check) {
1478 Register value = op->object()->as_register();
1479 Register array = op->array()->as_register();
1480 Register k_RInfo = op->tmp1()->as_register();
1481 Register klass_RInfo = op->tmp2()->as_register();
1482 Register Rtmp1 = op->tmp3()->as_register();
1483
1484 CodeStub* stub = op->stub();
1485
1486 // check if it needs to be profiled
1487 ciMethodData* md;
1488 ciProfileData* data;
1489
1490 if (should_profile) {
1491 ciMethod* method = op->profiled_method();
1492 assert(method != nullptr, "Should have method");
1493 int bci = op->profiled_bci();
1494 md = method->method_data_or_null();
1495 assert(md != nullptr, "Sanity");
1496 data = md->bci_to_data(bci);
1497 assert(data != nullptr, "need data for type check");
1498 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1499 }
1500 Label done;
1501 Label* success_target = &done;
1502 Label* failure_target = stub->entry();
1503
1504 if (should_profile) {
1505 Label not_null;
1506 Register mdo = klass_RInfo;
1507 __ mov_metadata(mdo, md->constant_encoding());
1508 __ cbnz(value, not_null);
1509 // Object is null; update MDO and exit
1510 Address data_addr
1511 = __ form_address(rscratch2, mdo,
1512 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1513 __ ldrb(rscratch1, data_addr);
1514 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1515 __ strb(rscratch1, data_addr);
1516 __ b(done);
1517 __ bind(not_null);
1518
1519 Register recv = k_RInfo;
1520 __ load_klass(recv, value);
1521 type_profile_helper(mdo, md, data, recv);
1522 } else {
1523 __ cbz(value, done);
1524 }
1525
1526 add_debug_info_for_null_check_here(op->info_for_exception());
1527 __ load_klass(k_RInfo, array);
1528 __ load_klass(klass_RInfo, value);
1529
1530 // get instance klass (it's already uncompressed)
1531 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1532 // perform the fast part of the checking logic
1533 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1534 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1535 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1536 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1537 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1538 // result is a boolean
1539 __ cbzw(k_RInfo, *failure_target);
1540 // fall through to the success case
1541
1542 __ bind(done);
1543 } else if (code == lir_checkcast) {
1544 Register obj = op->object()->as_register();
1545 Register dst = op->result_opr()->as_register();
1546 Label success;
1547 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1548 __ bind(success);
1549 if (dst != obj) {
1550 __ mov(dst, obj);
1551 }
1552 } else if (code == lir_instanceof) {
1553 Register obj = op->object()->as_register();
1554 Register dst = op->result_opr()->as_register();
1555 Label success, failure, done;
1556 emit_typecheck_helper(op, &success, &failure, &failure);
1557 __ bind(failure);
1558 __ mov(dst, zr);
1559 __ b(done);
1560 __ bind(success);
1561 __ mov(dst, 1);
1562 __ bind(done);
1563 } else {
1564 ShouldNotReachHere();
1565 }
1566 }
1567
1568 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1569 // We are loading/storing from/to an array that *may* be a flat array (the
1570 // declared type is Object[], abstract[], interface[] or VT.ref[]).
1571 // If this array is a flat array, take the slow path.
1572 __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1573 if (!op->value()->is_illegal()) {
1574 // The array is not a flat array, but it might be null-free. If we are storing
1575 // a null into a null-free array, take the slow path (which will throw NPE).
1576 Label skip;
1577 __ cbnz(op->value()->as_register(), skip);
1578 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1579 __ bind(skip);
1580 }
1581 }
1582
1583 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1584 // We are storing into an array that *may* be null-free (the declared type is
1585 // Object[], abstract[], interface[] or VT.ref[]).
1586 Label test_mark_word;
1587 Register tmp = op->tmp()->as_register();
1588 __ ldr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
1589 __ tst(tmp, markWord::unlocked_value);
1590 __ br(Assembler::NE, test_mark_word);
1591 __ load_prototype_header(tmp, op->array()->as_register());
1592 __ bind(test_mark_word);
1593 __ tst(tmp, markWord::null_free_array_bit_in_place);
1594 }
1595
1596 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1597 Label L_oops_equal;
1598 Label L_oops_not_equal;
1599 Label L_end;
1600
1601 Register left = op->left()->as_register();
1602 Register right = op->right()->as_register();
1603
1604 __ cmp(left, right);
1605 __ br(Assembler::EQ, L_oops_equal);
1606
1607 // (1) Null check -- if one of the operands is null, the other must not be null (because
1608 // the two references are not equal), so they are not substitutable,
1609 __ cbz(left, L_oops_not_equal);
1610 __ cbz(right, L_oops_not_equal);
1611
1612 ciKlass* left_klass = op->left_klass();
1613 ciKlass* right_klass = op->right_klass();
1614
1615 // (2) Inline type check -- if either of the operands is not a inline type,
1616 // they are not substitutable. We do this only if we are not sure that the
1617 // operands are inline type
1618 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node.
1619 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
1620 Register tmp1 = op->tmp1()->as_register();
1621 Register tmp2 = op->tmp2()->as_register();
1622 __ mov(tmp1, markWord::inline_type_pattern);
1623 __ ldr(tmp2, Address(left, oopDesc::mark_offset_in_bytes()));
1624 __ andr(tmp1, tmp1, tmp2);
1625 __ ldr(tmp2, Address(right, oopDesc::mark_offset_in_bytes()));
1626 __ andr(tmp1, tmp1, tmp2);
1627 __ cmp(tmp1, (u1)markWord::inline_type_pattern);
1628 __ br(Assembler::NE, L_oops_not_equal);
1629 }
1630
1631 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
1632 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) {
1633 // No need to load klass -- the operands are statically known to be the same inline klass.
1634 __ b(*op->stub()->entry());
1635 } else {
1636 Register tmp1 = op->tmp1()->as_register();
1637 Register tmp2 = op->tmp2()->as_register();
1638 __ cmp_klasses_from_objects(left, right, tmp1, tmp2);
1639 __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check
1640 // fall through to L_oops_not_equal
1641 }
1642
1643 __ bind(L_oops_not_equal);
1644 move(op->not_equal_result(), op->result_opr());
1645 __ b(L_end);
1646
1647 __ bind(L_oops_equal);
1648 move(op->equal_result(), op->result_opr());
1649 __ b(L_end);
1650
1651 // We've returned from the stub. R0 contains 0x0 IFF the two
1652 // operands are not substitutable. (Don't compare against 0x1 in case the
1653 // C compiler is naughty)
1654 __ bind(*op->stub()->continuation());
1655 __ cbz(r0, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1656 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
1657 // fall-through
1658 __ bind(L_end);
1659 }
1660
1661
1662 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1663 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1664 __ cset(rscratch1, Assembler::NE);
1665 __ membar(__ AnyAny);
1666 }
1667
1668 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1669 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1670 __ cset(rscratch1, Assembler::NE);
1671 __ membar(__ AnyAny);
1672 }
1673
1674
1675 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1676 Register addr;
1677 if (op->addr()->is_register()) {
1678 addr = as_reg(op->addr());
1679 } else {
1680 assert(op->addr()->is_address(), "what else?");
1681 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1682 assert(addr_ptr->disp() == 0, "need 0 disp");
1683 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1684 addr = as_reg(addr_ptr->base());
1685 }
1686 Register newval = as_reg(op->new_value());
1687 Register cmpval = as_reg(op->cmp_value());
1688
1689 if (op->code() == lir_cas_obj) {
1690 if (UseCompressedOops) {
1691 Register t1 = op->tmp1()->as_register();
1692 assert(op->tmp1()->is_valid(), "must be");
1693 __ encode_heap_oop(t1, cmpval);
1694 cmpval = t1;
1695 __ encode_heap_oop(rscratch2, newval);
1696 newval = rscratch2;
1697 casw(addr, newval, cmpval);
1698 } else {
1699 casl(addr, newval, cmpval);
1700 }
1701 } else if (op->code() == lir_cas_int) {
1702 casw(addr, newval, cmpval);
1703 } else {
1704 casl(addr, newval, cmpval);
1705 }
1706 }
1707
1708
1709 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1710 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1711 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1712
1713 Assembler::Condition acond, ncond;
1714 switch (condition) {
1715 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1716 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1717 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1718 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1719 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1720 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1721 case lir_cond_belowEqual:
1722 case lir_cond_aboveEqual:
1723 default: ShouldNotReachHere();
1724 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1725 }
1726
1727 assert(result->is_single_cpu() || result->is_double_cpu(),
1728 "expect single register for result");
1729 if (opr1->is_constant() && opr2->is_constant()
1730 && opr1->type() == T_INT && opr2->type() == T_INT) {
1731 jint val1 = opr1->as_jint();
1732 jint val2 = opr2->as_jint();
1733 if (val1 == 0 && val2 == 1) {
1734 __ cset(result->as_register(), ncond);
1735 return;
1736 } else if (val1 == 1 && val2 == 0) {
1737 __ cset(result->as_register(), acond);
1738 return;
1739 }
1740 }
1741
1742 if (opr1->is_constant() && opr2->is_constant()
1743 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1744 jlong val1 = opr1->as_jlong();
1745 jlong val2 = opr2->as_jlong();
1746 if (val1 == 0 && val2 == 1) {
1747 __ cset(result->as_register_lo(), ncond);
1748 return;
1749 } else if (val1 == 1 && val2 == 0) {
1750 __ cset(result->as_register_lo(), acond);
1751 return;
1752 }
1753 }
1754
1755 if (opr1->is_stack()) {
1756 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1757 opr1 = FrameMap::rscratch1_opr;
1758 } else if (opr1->is_constant()) {
1759 LIR_Opr tmp
1760 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1761 const2reg(opr1, tmp, lir_patch_none, nullptr);
1762 opr1 = tmp;
1763 }
1764
1765 if (opr2->is_stack()) {
1766 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1767 opr2 = FrameMap::rscratch2_opr;
1768 } else if (opr2->is_constant()) {
1769 LIR_Opr tmp
1770 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1771 const2reg(opr2, tmp, lir_patch_none, nullptr);
1772 opr2 = tmp;
1773 }
1774
1775 if (result->type() == T_LONG)
1776 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1777 else
1778 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1779 }
1780
1781 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1782 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1783
1784 if (left->is_single_cpu()) {
1785 Register lreg = left->as_register();
1786 Register dreg = as_reg(dest);
1787
1788 if (right->is_single_cpu()) {
1789 // cpu register - cpu register
1790
1791 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1792 "should be");
1793 Register rreg = right->as_register();
1794 switch (code) {
1795 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1796 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1797 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1798 default: ShouldNotReachHere();
1799 }
1800
1801 } else if (right->is_double_cpu()) {
1802 Register rreg = right->as_register_lo();
1803 // single_cpu + double_cpu: can happen with obj+long
1804 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1805 switch (code) {
1806 case lir_add: __ add(dreg, lreg, rreg); break;
1807 case lir_sub: __ sub(dreg, lreg, rreg); break;
1808 default: ShouldNotReachHere();
1809 }
1810 } else if (right->is_constant()) {
1811 // cpu register - constant
1812 jlong c;
1813
1814 // FIXME. This is fugly: we really need to factor all this logic.
1815 switch(right->type()) {
1816 case T_LONG:
1817 c = right->as_constant_ptr()->as_jlong();
1818 break;
1819 case T_INT:
1820 case T_ADDRESS:
1821 c = right->as_constant_ptr()->as_jint();
1822 break;
1823 default:
1824 ShouldNotReachHere();
1825 c = 0; // unreachable
1826 break;
1827 }
1828
1829 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1830 if (c == 0 && dreg == lreg) {
1831 COMMENT("effective nop elided");
1832 return;
1833 }
1834 switch(left->type()) {
1835 case T_INT:
1836 switch (code) {
1837 case lir_add: __ addw(dreg, lreg, c); break;
1838 case lir_sub: __ subw(dreg, lreg, c); break;
1839 default: ShouldNotReachHere();
1840 }
1841 break;
1842 case T_OBJECT:
1843 case T_ADDRESS:
1844 switch (code) {
1845 case lir_add: __ add(dreg, lreg, c); break;
1846 case lir_sub: __ sub(dreg, lreg, c); break;
1847 default: ShouldNotReachHere();
1848 }
1849 break;
1850 default:
1851 ShouldNotReachHere();
1852 }
1853 } else {
1854 ShouldNotReachHere();
1855 }
1856
1857 } else if (left->is_double_cpu()) {
1858 Register lreg_lo = left->as_register_lo();
1859
1860 if (right->is_double_cpu()) {
1861 // cpu register - cpu register
1862 Register rreg_lo = right->as_register_lo();
1863 switch (code) {
1864 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1865 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1866 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1867 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1868 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1869 default:
1870 ShouldNotReachHere();
1871 }
1872
1873 } else if (right->is_constant()) {
1874 jlong c = right->as_constant_ptr()->as_jlong();
1875 Register dreg = as_reg(dest);
1876 switch (code) {
1877 case lir_add:
1878 case lir_sub:
1879 if (c == 0 && dreg == lreg_lo) {
1880 COMMENT("effective nop elided");
1881 return;
1882 }
1883 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1884 break;
1885 case lir_div:
1886 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1887 if (c == 1) {
1888 // move lreg_lo to dreg if divisor is 1
1889 __ mov(dreg, lreg_lo);
1890 } else {
1891 unsigned int shift = log2i_exact(c);
1892 // use rscratch1 as intermediate result register
1893 __ asr(rscratch1, lreg_lo, 63);
1894 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1895 __ asr(dreg, rscratch1, shift);
1896 }
1897 break;
1898 case lir_rem:
1899 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1900 if (c == 1) {
1901 // move 0 to dreg if divisor is 1
1902 __ mov(dreg, zr);
1903 } else {
1904 // use rscratch1 as intermediate result register
1905 __ negs(rscratch1, lreg_lo);
1906 __ andr(dreg, lreg_lo, c - 1);
1907 __ andr(rscratch1, rscratch1, c - 1);
1908 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1909 }
1910 break;
1911 default:
1912 ShouldNotReachHere();
1913 }
1914 } else {
1915 ShouldNotReachHere();
1916 }
1917 } else if (left->is_single_fpu()) {
1918 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1919 switch (code) {
1920 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1921 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1922 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1923 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1924 default:
1925 ShouldNotReachHere();
1926 }
1927 } else if (left->is_double_fpu()) {
1928 if (right->is_double_fpu()) {
1929 // fpu register - fpu register
1930 switch (code) {
1931 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1932 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1933 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1934 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1935 default:
1936 ShouldNotReachHere();
1937 }
1938 } else {
1939 if (right->is_constant()) {
1940 ShouldNotReachHere();
1941 }
1942 ShouldNotReachHere();
1943 }
1944 } else if (left->is_single_stack() || left->is_address()) {
1945 assert(left == dest, "left and dest must be equal");
1946 ShouldNotReachHere();
1947 } else {
1948 ShouldNotReachHere();
1949 }
1950 }
1951
1952 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1953 switch(code) {
1954 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1955 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1956 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1957 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1958 default : ShouldNotReachHere();
1959 }
1960 }
1961
1962 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1963
1964 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1965 Register Rleft = left->is_single_cpu() ? left->as_register() :
1966 left->as_register_lo();
1967 if (dst->is_single_cpu()) {
1968 Register Rdst = dst->as_register();
1969 if (right->is_constant()) {
1970 switch (code) {
1971 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1972 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1973 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1974 default: ShouldNotReachHere(); break;
1975 }
1976 } else {
1977 Register Rright = right->is_single_cpu() ? right->as_register() :
1978 right->as_register_lo();
1979 switch (code) {
1980 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1981 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1982 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1983 default: ShouldNotReachHere(); break;
1984 }
1985 }
1986 } else {
1987 Register Rdst = dst->as_register_lo();
1988 if (right->is_constant()) {
1989 switch (code) {
1990 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1991 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1992 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1993 default: ShouldNotReachHere(); break;
1994 }
1995 } else {
1996 Register Rright = right->is_single_cpu() ? right->as_register() :
1997 right->as_register_lo();
1998 switch (code) {
1999 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
2000 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
2001 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
2002 default: ShouldNotReachHere(); break;
2003 }
2004 }
2005 }
2006 }
2007
2008
2009
2010 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
2011
2012 // opcode check
2013 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
2014 bool is_irem = (code == lir_irem);
2015
2016 // operand check
2017 assert(left->is_single_cpu(), "left must be register");
2018 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2019 assert(result->is_single_cpu(), "result must be register");
2020 Register lreg = left->as_register();
2021 Register dreg = result->as_register();
2022
2023 // power-of-2 constant check and codegen
2024 if (right->is_constant()) {
2025 int c = right->as_constant_ptr()->as_jint();
2026 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
2027 if (is_irem) {
2028 if (c == 1) {
2029 // move 0 to dreg if divisor is 1
2030 __ movw(dreg, zr);
2031 } else {
2032 // use rscratch1 as intermediate result register
2033 __ negsw(rscratch1, lreg);
2034 __ andw(dreg, lreg, c - 1);
2035 __ andw(rscratch1, rscratch1, c - 1);
2036 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
2037 }
2038 } else {
2039 if (c == 1) {
2040 // move lreg to dreg if divisor is 1
2041 __ movw(dreg, lreg);
2042 } else {
2043 unsigned int shift = exact_log2(c);
2044 // use rscratch1 as intermediate result register
2045 __ asrw(rscratch1, lreg, 31);
2046 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
2047 __ asrw(dreg, rscratch1, shift);
2048 }
2049 }
2050 } else {
2051 Register rreg = right->as_register();
2052 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
2053 }
2054 }
2055
2056
2057 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2058 if (opr1->is_constant() && opr2->is_single_cpu()) {
2059 // tableswitch
2060 Register reg = as_reg(opr2);
2061 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
2062 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
2063 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
2064 Register reg1 = as_reg(opr1);
2065 if (opr2->is_single_cpu()) {
2066 // cpu register - cpu register
2067 Register reg2 = opr2->as_register();
2068 if (is_reference_type(opr1->type())) {
2069 __ cmpoop(reg1, reg2);
2070 } else {
2071 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2072 __ cmpw(reg1, reg2);
2073 }
2074 return;
2075 }
2076 if (opr2->is_double_cpu()) {
2077 // cpu register - cpu register
2078 Register reg2 = opr2->as_register_lo();
2079 __ cmp(reg1, reg2);
2080 return;
2081 }
2082
2083 if (opr2->is_constant()) {
2084 bool is_32bit = false; // width of register operand
2085 jlong imm;
2086
2087 switch(opr2->type()) {
2088 case T_INT:
2089 imm = opr2->as_constant_ptr()->as_jint();
2090 is_32bit = true;
2091 break;
2092 case T_LONG:
2093 imm = opr2->as_constant_ptr()->as_jlong();
2094 break;
2095 case T_ADDRESS:
2096 imm = opr2->as_constant_ptr()->as_jint();
2097 break;
2098 case T_METADATA:
2099 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
2100 break;
2101 case T_OBJECT:
2102 case T_ARRAY:
2103 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
2104 __ cmpoop(reg1, rscratch1);
2105 return;
2106 default:
2107 ShouldNotReachHere();
2108 imm = 0; // unreachable
2109 break;
2110 }
2111
2112 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
2113 if (is_32bit)
2114 __ cmpw(reg1, imm);
2115 else
2116 __ subs(zr, reg1, imm);
2117 return;
2118 } else {
2119 __ mov(rscratch1, imm);
2120 if (is_32bit)
2121 __ cmpw(reg1, rscratch1);
2122 else
2123 __ cmp(reg1, rscratch1);
2124 return;
2125 }
2126 } else
2127 ShouldNotReachHere();
2128 } else if (opr1->is_single_fpu()) {
2129 FloatRegister reg1 = opr1->as_float_reg();
2130 assert(opr2->is_single_fpu(), "expect single float register");
2131 FloatRegister reg2 = opr2->as_float_reg();
2132 __ fcmps(reg1, reg2);
2133 } else if (opr1->is_double_fpu()) {
2134 FloatRegister reg1 = opr1->as_double_reg();
2135 assert(opr2->is_double_fpu(), "expect double float register");
2136 FloatRegister reg2 = opr2->as_double_reg();
2137 __ fcmpd(reg1, reg2);
2138 } else {
2139 ShouldNotReachHere();
2140 }
2141 }
2142
2143 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2144 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2145 bool is_unordered_less = (code == lir_ucmp_fd2i);
2146 if (left->is_single_fpu()) {
2147 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2148 } else if (left->is_double_fpu()) {
2149 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2150 } else {
2151 ShouldNotReachHere();
2152 }
2153 } else if (code == lir_cmp_l2i) {
2154 Label done;
2155 __ cmp(left->as_register_lo(), right->as_register_lo());
2156 __ mov(dst->as_register(), (uint64_t)-1L);
2157 __ br(Assembler::LT, done);
2158 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2159 __ bind(done);
2160 } else {
2161 ShouldNotReachHere();
2162 }
2163 }
2164
2165
2166 void LIR_Assembler::align_call(LIR_Code code) { }
2167
2168
2169 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2170 address call = __ trampoline_call(Address(op->addr(), rtype));
2171 if (call == nullptr) {
2172 bailout("trampoline stub overflow");
2173 return;
2174 }
2175 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2176 __ post_call_nop();
2177 }
2178
2179
2180 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2181 address call = __ ic_call(op->addr());
2182 if (call == nullptr) {
2183 bailout("trampoline stub overflow");
2184 return;
2185 }
2186 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2187 __ post_call_nop();
2188 }
2189
2190 void LIR_Assembler::emit_static_call_stub() {
2191 address call_pc = __ pc();
2192 address stub = __ start_a_stub(call_stub_size());
2193 if (stub == nullptr) {
2194 bailout("static call stub overflow");
2195 return;
2196 }
2197
2198 int start = __ offset();
2199
2200 __ relocate(static_stub_Relocation::spec(call_pc));
2201 __ emit_static_call_stub();
2202
2203 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2204 <= call_stub_size(), "stub too big");
2205 __ end_a_stub();
2206 }
2207
2208
2209 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2210 assert(exceptionOop->as_register() == r0, "must match");
2211 assert(exceptionPC->as_register() == r3, "must match");
2212
2213 // exception object is not added to oop map by LinearScan
2214 // (LinearScan assumes that no oops are in fixed registers)
2215 info->add_register_oop(exceptionOop);
2216 StubId unwind_id;
2217
2218 // get current pc information
2219 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2220 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2221 // As no instructions have been generated yet for this LIR node it's
2222 // possible that an oop map already exists for the current offset.
2223 // In that case insert an dummy NOP here to ensure all oop map PCs
2224 // are unique. See JDK-8237483.
2225 __ nop();
2226 }
2227 int pc_for_athrow_offset = __ offset();
2228 InternalAddress pc_for_athrow(__ pc());
2229 __ adr(exceptionPC->as_register(), pc_for_athrow);
2230 add_call_info(pc_for_athrow_offset, info); // for exception handler
2231
2232 __ verify_not_null_oop(r0);
2233 // search an exception handler (r0: exception oop, r3: throwing pc)
2234 if (compilation()->has_fpu_code()) {
2235 unwind_id = StubId::c1_handle_exception_id;
2236 } else {
2237 unwind_id = StubId::c1_handle_exception_nofpu_id;
2238 }
2239 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2240
2241 // FIXME: enough room for two byte trap ????
2242 __ nop();
2243 }
2244
2245
2246 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2247 assert(exceptionOop->as_register() == r0, "must match");
2248
2249 __ b(_unwind_handler_entry);
2250 }
2251
2252
2253 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2254 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2255 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2256
2257 switch (left->type()) {
2258 case T_INT: {
2259 switch (code) {
2260 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2261 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2262 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2263 default:
2264 ShouldNotReachHere();
2265 break;
2266 }
2267 break;
2268 case T_LONG:
2269 case T_ADDRESS:
2270 case T_OBJECT:
2271 switch (code) {
2272 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2273 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2274 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2275 default:
2276 ShouldNotReachHere();
2277 break;
2278 }
2279 break;
2280 default:
2281 ShouldNotReachHere();
2282 break;
2283 }
2284 }
2285 }
2286
2287
2288 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2289 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2290 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2291
2292 switch (left->type()) {
2293 case T_INT: {
2294 switch (code) {
2295 case lir_shl: __ lslw (dreg, lreg, count); break;
2296 case lir_shr: __ asrw (dreg, lreg, count); break;
2297 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2298 default:
2299 ShouldNotReachHere();
2300 break;
2301 }
2302 break;
2303 case T_LONG:
2304 case T_ADDRESS:
2305 case T_OBJECT:
2306 switch (code) {
2307 case lir_shl: __ lsl (dreg, lreg, count); break;
2308 case lir_shr: __ asr (dreg, lreg, count); break;
2309 case lir_ushr: __ lsr (dreg, lreg, count); break;
2310 default:
2311 ShouldNotReachHere();
2312 break;
2313 }
2314 break;
2315 default:
2316 ShouldNotReachHere();
2317 break;
2318 }
2319 }
2320 }
2321
2322
2323 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2324 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2325 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2326 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2327 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2328 }
2329
2330
2331 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2332 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2333 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2334 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2335 __ mov (rscratch1, c);
2336 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2337 }
2338
2339
2340 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2341 ShouldNotReachHere();
2342 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2343 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2344 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2345 __ lea(rscratch1, __ constant_oop_address(o));
2346 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2347 }
2348
2349 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
2350 if (null_check) {
2351 __ cbz(obj, *slow_path->entry());
2352 }
2353 if (is_dest) {
2354 __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
2355 // TODO 8350865 Flat no longer implies null-free, so we need to check for flat dest. Can we do better here?
2356 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2357 } else {
2358 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2359 }
2360 }
2361
2362 // This code replaces a call to arraycopy; no exception may
2363 // be thrown in this code, they must be thrown in the System.arraycopy
2364 // activation frame; we could save some checks if this would not be the case
2365 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2366 ciArrayKlass* default_type = op->expected_type();
2367 Register src = op->src()->as_register();
2368 Register dst = op->dst()->as_register();
2369 Register src_pos = op->src_pos()->as_register();
2370 Register dst_pos = op->dst_pos()->as_register();
2371 Register length = op->length()->as_register();
2372 Register tmp = op->tmp()->as_register();
2373
2374 CodeStub* stub = op->stub();
2375 int flags = op->flags();
2376 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2377 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2378
2379 if (flags & LIR_OpArrayCopy::always_slow_path) {
2380 __ b(*stub->entry());
2381 __ bind(*stub->continuation());
2382 return;
2383 }
2384
2385 // if we don't know anything, just go through the generic arraycopy
2386 if (default_type == nullptr // || basic_type == T_OBJECT
2387 ) {
2388 Label done;
2389 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2390
2391 // Save the arguments in case the generic arraycopy fails and we
2392 // have to fall back to the JNI stub
2393 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2394 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2395 __ str(src, Address(sp, 4*BytesPerWord));
2396
2397 address copyfunc_addr = StubRoutines::generic_arraycopy();
2398 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2399
2400 // The arguments are in java calling convention so we shift them
2401 // to C convention
2402 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2403 __ mov(c_rarg0, j_rarg0);
2404 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2405 __ mov(c_rarg1, j_rarg1);
2406 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2407 __ mov(c_rarg2, j_rarg2);
2408 assert_different_registers(c_rarg3, j_rarg4);
2409 __ mov(c_rarg3, j_rarg3);
2410 __ mov(c_rarg4, j_rarg4);
2411 #ifndef PRODUCT
2412 if (PrintC1Statistics) {
2413 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2414 }
2415 #endif
2416 __ far_call(RuntimeAddress(copyfunc_addr));
2417
2418 __ cbz(r0, *stub->continuation());
2419
2420 // Reload values from the stack so they are where the stub
2421 // expects them.
2422 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2423 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2424 __ ldr(src, Address(sp, 4*BytesPerWord));
2425
2426 // r0 is -1^K where K == partial copied count
2427 __ eonw(rscratch1, r0, zr);
2428 // adjust length down and src/end pos up by partial copied count
2429 __ subw(length, length, rscratch1);
2430 __ addw(src_pos, src_pos, rscratch1);
2431 __ addw(dst_pos, dst_pos, rscratch1);
2432 __ b(*stub->entry());
2433
2434 __ bind(*stub->continuation());
2435 return;
2436 }
2437
2438 // Handle inline type arrays
2439 if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
2440 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
2441 }
2442 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
2443 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
2444 }
2445
2446 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2447
2448 int elem_size = type2aelembytes(basic_type);
2449 int scale = exact_log2(elem_size);
2450
2451 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2452 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2453
2454 // test for null
2455 if (flags & LIR_OpArrayCopy::src_null_check) {
2456 __ cbz(src, *stub->entry());
2457 }
2458 if (flags & LIR_OpArrayCopy::dst_null_check) {
2459 __ cbz(dst, *stub->entry());
2460 }
2461
2462 // If the compiler was not able to prove that exact type of the source or the destination
2463 // of the arraycopy is an array type, check at runtime if the source or the destination is
2464 // an instance type.
2465 if (flags & LIR_OpArrayCopy::type_check) {
2466 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2467 __ load_klass(tmp, dst);
2468 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2469 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2470 __ br(Assembler::GE, *stub->entry());
2471 }
2472
2473 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2474 __ load_klass(tmp, src);
2475 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2476 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2477 __ br(Assembler::GE, *stub->entry());
2478 }
2479 }
2480
2481 // check if negative
2482 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2483 __ cmpw(src_pos, 0);
2484 __ br(Assembler::LT, *stub->entry());
2485 }
2486 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2487 __ cmpw(dst_pos, 0);
2488 __ br(Assembler::LT, *stub->entry());
2489 }
2490
2491 if (flags & LIR_OpArrayCopy::length_positive_check) {
2492 __ cmpw(length, 0);
2493 __ br(Assembler::LT, *stub->entry());
2494 }
2495
2496 if (flags & LIR_OpArrayCopy::src_range_check) {
2497 __ addw(tmp, src_pos, length);
2498 __ ldrw(rscratch1, src_length_addr);
2499 __ cmpw(tmp, rscratch1);
2500 __ br(Assembler::HI, *stub->entry());
2501 }
2502 if (flags & LIR_OpArrayCopy::dst_range_check) {
2503 __ addw(tmp, dst_pos, length);
2504 __ ldrw(rscratch1, dst_length_addr);
2505 __ cmpw(tmp, rscratch1);
2506 __ br(Assembler::HI, *stub->entry());
2507 }
2508
2509 if (flags & LIR_OpArrayCopy::type_check) {
2510 // We don't know the array types are compatible
2511 if (basic_type != T_OBJECT) {
2512 // Simple test for basic type arrays
2513 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2514 __ br(Assembler::NE, *stub->entry());
2515 } else {
2516 // For object arrays, if src is a sub class of dst then we can
2517 // safely do the copy.
2518 Label cont, slow;
2519
2520 #define PUSH(r1, r2) \
2521 stp(r1, r2, __ pre(sp, -2 * wordSize));
2522
2523 #define POP(r1, r2) \
2524 ldp(r1, r2, __ post(sp, 2 * wordSize));
2525
2526 __ PUSH(src, dst);
2527
2528 __ load_klass(src, src);
2529 __ load_klass(dst, dst);
2530
2531 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2532
2533 __ PUSH(src, dst);
2534 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2535 __ POP(src, dst);
2536
2537 __ cbnz(src, cont);
2538
2539 __ bind(slow);
2540 __ POP(src, dst);
2541
2542 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2543 if (copyfunc_addr != nullptr) { // use stub if available
2544 // src is not a sub class of dst so we have to do a
2545 // per-element check.
2546
2547 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2548 if ((flags & mask) != mask) {
2549 // Check that at least both of them object arrays.
2550 assert(flags & mask, "one of the two should be known to be an object array");
2551
2552 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2553 __ load_klass(tmp, src);
2554 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2555 __ load_klass(tmp, dst);
2556 }
2557 int lh_offset = in_bytes(Klass::layout_helper_offset());
2558 Address klass_lh_addr(tmp, lh_offset);
2559 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2560 __ ldrw(rscratch1, klass_lh_addr);
2561 __ mov(rscratch2, objArray_lh);
2562 __ eorw(rscratch1, rscratch1, rscratch2);
2563 __ cbnzw(rscratch1, *stub->entry());
2564 }
2565
2566 // Spill because stubs can use any register they like and it's
2567 // easier to restore just those that we care about.
2568 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2569 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2570 __ str(src, Address(sp, 4*BytesPerWord));
2571
2572 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2573 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2574 assert_different_registers(c_rarg0, dst, dst_pos, length);
2575 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2576 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2577 assert_different_registers(c_rarg1, dst, length);
2578 __ uxtw(c_rarg2, length);
2579 assert_different_registers(c_rarg2, dst);
2580
2581 __ load_klass(c_rarg4, dst);
2582 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2583 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2584 __ far_call(RuntimeAddress(copyfunc_addr));
2585
2586 #ifndef PRODUCT
2587 if (PrintC1Statistics) {
2588 Label failed;
2589 __ cbnz(r0, failed);
2590 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2591 __ bind(failed);
2592 }
2593 #endif
2594
2595 __ cbz(r0, *stub->continuation());
2596
2597 #ifndef PRODUCT
2598 if (PrintC1Statistics) {
2599 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2600 }
2601 #endif
2602 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2603
2604 // Restore previously spilled arguments
2605 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2606 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2607 __ ldr(src, Address(sp, 4*BytesPerWord));
2608
2609 // return value is -1^K where K is partial copied count
2610 __ eonw(rscratch1, r0, zr);
2611 // adjust length down and src/end pos up by partial copied count
2612 __ subw(length, length, rscratch1);
2613 __ addw(src_pos, src_pos, rscratch1);
2614 __ addw(dst_pos, dst_pos, rscratch1);
2615 }
2616
2617 __ b(*stub->entry());
2618
2619 __ bind(cont);
2620 __ POP(src, dst);
2621 }
2622 }
2623
2624 #ifdef ASSERT
2625 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2626 // Sanity check the known type with the incoming class. For the
2627 // primitive case the types must match exactly with src.klass and
2628 // dst.klass each exactly matching the default type. For the
2629 // object array case, if no type check is needed then either the
2630 // dst type is exactly the expected type and the src type is a
2631 // subtype which we can't check or src is the same array as dst
2632 // but not necessarily exactly of type default_type.
2633 Label known_ok, halt;
2634 __ mov_metadata(tmp, default_type->constant_encoding());
2635
2636 if (basic_type != T_OBJECT) {
2637 __ cmp_klass(dst, tmp, rscratch1);
2638 __ br(Assembler::NE, halt);
2639 __ cmp_klass(src, tmp, rscratch1);
2640 __ br(Assembler::EQ, known_ok);
2641 } else {
2642 __ cmp_klass(dst, tmp, rscratch1);
2643 __ br(Assembler::EQ, known_ok);
2644 __ cmp(src, dst);
2645 __ br(Assembler::EQ, known_ok);
2646 }
2647 __ bind(halt);
2648 __ stop("incorrect type information in arraycopy");
2649 __ bind(known_ok);
2650 }
2651 #endif
2652
2653 #ifndef PRODUCT
2654 if (PrintC1Statistics) {
2655 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2656 }
2657 #endif
2658
2659 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2660 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2661 assert_different_registers(c_rarg0, dst, dst_pos, length);
2662 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2663 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2664 assert_different_registers(c_rarg1, dst, length);
2665 __ uxtw(c_rarg2, length);
2666 assert_different_registers(c_rarg2, dst);
2667
2668 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2669 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2670 const char *name;
2671 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2672
2673 CodeBlob *cb = CodeCache::find_blob(entry);
2674 if (cb) {
2675 __ far_call(RuntimeAddress(entry));
2676 } else {
2677 __ call_VM_leaf(entry, 3);
2678 }
2679
2680 if (stub != nullptr) {
2681 __ bind(*stub->continuation());
2682 }
2683 }
2684
2685
2686
2687
2688 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2689 Register obj = op->obj_opr()->as_register(); // may not be an oop
2690 Register hdr = op->hdr_opr()->as_register();
2691 Register lock = op->lock_opr()->as_register();
2692 Register temp = op->scratch_opr()->as_register();
2693 if (op->code() == lir_lock) {
2694 // add debug info for NullPointerException only if one is possible
2695 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2696 if (op->info() != nullptr) {
2697 add_debug_info_for_null_check(null_check_offset, op->info());
2698 }
2699 // done
2700 } else if (op->code() == lir_unlock) {
2701 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2702 } else {
2703 Unimplemented();
2704 }
2705 __ bind(*op->stub()->continuation());
2706 }
2707
2708 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2709 Register obj = op->obj()->as_pointer_register();
2710 Register result = op->result_opr()->as_pointer_register();
2711
2712 CodeEmitInfo* info = op->info();
2713 if (info != nullptr) {
2714 add_debug_info_for_null_check_here(info);
2715 }
2716
2717 __ load_klass(result, obj);
2718 }
2719
2720 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2721 ciMethod* method = op->profiled_method();
2722 int bci = op->profiled_bci();
2723 ciMethod* callee = op->profiled_callee();
2724
2725 // Update counter for all call types
2726 ciMethodData* md = method->method_data_or_null();
2727 assert(md != nullptr, "Sanity");
2728 ciProfileData* data = md->bci_to_data(bci);
2729 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2730 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2731 Register mdo = op->mdo()->as_register();
2732 __ mov_metadata(mdo, md->constant_encoding());
2733 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2734 // Perform additional virtual call profiling for invokevirtual and
2735 // invokeinterface bytecodes
2736 if (op->should_profile_receiver_type()) {
2737 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2738 Register recv = op->recv()->as_register();
2739 assert_different_registers(mdo, recv);
2740 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2741 ciKlass* known_klass = op->known_holder();
2742 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2743 // We know the type that will be seen at this call site; we can
2744 // statically update the MethodData* rather than needing to do
2745 // dynamic tests on the receiver type.
2746 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2747 for (uint i = 0; i < VirtualCallData::row_limit(); i++) {
2748 ciKlass* receiver = vc_data->receiver(i);
2749 if (known_klass->equals(receiver)) {
2750 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2751 __ addptr(data_addr, DataLayout::counter_increment);
2752 return;
2753 }
2754 }
2755 // Receiver type is not found in profile data.
2756 // Fall back to runtime helper to handle the rest at runtime.
2757 __ mov_metadata(recv, known_klass->constant_encoding());
2758 } else {
2759 __ load_klass(recv, recv);
2760 }
2761 type_profile_helper(mdo, md, data, recv);
2762 } else {
2763 // Static call
2764 __ addptr(counter_addr, DataLayout::counter_increment);
2765 }
2766 }
2767
2768
2769 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2770 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2771 }
2772
2773 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2774 assert(op->crc()->is_single_cpu(), "crc must be register");
2775 assert(op->val()->is_single_cpu(), "byte value must be register");
2776 assert(op->result_opr()->is_single_cpu(), "result must be register");
2777 Register crc = op->crc()->as_register();
2778 Register val = op->val()->as_register();
2779 Register res = op->result_opr()->as_register();
2780
2781 assert_different_registers(val, crc, res);
2782 uint64_t offset;
2783 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2784 __ add(res, res, offset);
2785
2786 __ mvnw(crc, crc); // ~crc
2787 __ update_byte_crc32(crc, val, res);
2788 __ mvnw(res, crc); // ~crc
2789 }
2790
2791 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2792 COMMENT("emit_profile_type {");
2793 Register obj = op->obj()->as_register();
2794 Register tmp = op->tmp()->as_pointer_register();
2795 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2796 ciKlass* exact_klass = op->exact_klass();
2797 intptr_t current_klass = op->current_klass();
2798 bool not_null = op->not_null();
2799 bool no_conflict = op->no_conflict();
2800
2801 Label update, next, none;
2802
2803 bool do_null = !not_null;
2804 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2805 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2806
2807 assert(do_null || do_update, "why are we here?");
2808 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2809 assert(mdo_addr.base() != rscratch1, "wrong register");
2810
2811 __ verify_oop(obj);
2812
2813 if (tmp != obj) {
2814 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2815 __ mov(tmp, obj);
2816 } else {
2817 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2818 }
2819 if (do_null) {
2820 __ cbnz(tmp, update);
2821 if (!TypeEntries::was_null_seen(current_klass)) {
2822 __ ldr(rscratch2, mdo_addr);
2823 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2824 __ str(rscratch2, mdo_addr);
2825 }
2826 if (do_update) {
2827 #ifndef ASSERT
2828 __ b(next);
2829 }
2830 #else
2831 __ b(next);
2832 }
2833 } else {
2834 __ cbnz(tmp, update);
2835 __ stop("unexpected null obj");
2836 #endif
2837 }
2838
2839 __ bind(update);
2840
2841 if (do_update) {
2842 #ifdef ASSERT
2843 if (exact_klass != nullptr) {
2844 Label ok;
2845 __ load_klass(tmp, tmp);
2846 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2847 __ eor(rscratch1, tmp, rscratch1);
2848 __ cbz(rscratch1, ok);
2849 __ stop("exact klass and actual klass differ");
2850 __ bind(ok);
2851 }
2852 #endif
2853 if (!no_conflict) {
2854 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2855 if (exact_klass != nullptr) {
2856 __ mov_metadata(tmp, exact_klass->constant_encoding());
2857 } else {
2858 __ load_klass(tmp, tmp);
2859 }
2860
2861 __ ldr(rscratch2, mdo_addr);
2862 __ eor(tmp, tmp, rscratch2);
2863 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2864 // klass seen before, nothing to do. The unknown bit may have been
2865 // set already but no need to check.
2866 __ cbz(rscratch1, next);
2867
2868 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2869
2870 if (TypeEntries::is_type_none(current_klass)) {
2871 __ cbz(rscratch2, none);
2872 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2873 __ br(Assembler::EQ, none);
2874 // There is a chance that the checks above
2875 // fail if another thread has just set the
2876 // profiling to this obj's klass
2877 __ dmb(Assembler::ISHLD);
2878 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2879 __ ldr(rscratch2, mdo_addr);
2880 __ eor(tmp, tmp, rscratch2);
2881 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2882 __ cbz(rscratch1, next);
2883 }
2884 } else {
2885 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2886 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2887
2888 __ ldr(tmp, mdo_addr);
2889 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2890 }
2891
2892 // different than before. Cannot keep accurate profile.
2893 __ ldr(rscratch2, mdo_addr);
2894 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2895 __ str(rscratch2, mdo_addr);
2896
2897 if (TypeEntries::is_type_none(current_klass)) {
2898 __ b(next);
2899
2900 __ bind(none);
2901 // first time here. Set profile type.
2902 __ str(tmp, mdo_addr);
2903 #ifdef ASSERT
2904 __ andr(tmp, tmp, TypeEntries::type_mask);
2905 __ verify_klass_ptr(tmp);
2906 #endif
2907 }
2908 } else {
2909 // There's a single possible klass at this profile point
2910 assert(exact_klass != nullptr, "should be");
2911 if (TypeEntries::is_type_none(current_klass)) {
2912 __ mov_metadata(tmp, exact_klass->constant_encoding());
2913 __ ldr(rscratch2, mdo_addr);
2914 __ eor(tmp, tmp, rscratch2);
2915 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2916 __ cbz(rscratch1, next);
2917 #ifdef ASSERT
2918 {
2919 Label ok;
2920 __ ldr(rscratch1, mdo_addr);
2921 __ cbz(rscratch1, ok);
2922 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2923 __ br(Assembler::EQ, ok);
2924 // may have been set by another thread
2925 __ dmb(Assembler::ISHLD);
2926 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2927 __ ldr(rscratch2, mdo_addr);
2928 __ eor(rscratch2, rscratch1, rscratch2);
2929 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2930 __ cbz(rscratch2, ok);
2931
2932 __ stop("unexpected profiling mismatch");
2933 __ bind(ok);
2934 }
2935 #endif
2936 // first time here. Set profile type.
2937 __ str(tmp, mdo_addr);
2938 #ifdef ASSERT
2939 __ andr(tmp, tmp, TypeEntries::type_mask);
2940 __ verify_klass_ptr(tmp);
2941 #endif
2942 } else {
2943 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2944 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2945
2946 __ ldr(tmp, mdo_addr);
2947 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2948
2949 __ orr(tmp, tmp, TypeEntries::type_unknown);
2950 __ str(tmp, mdo_addr);
2951 // FIXME: Write barrier needed here?
2952 }
2953 }
2954
2955 __ bind(next);
2956 }
2957 COMMENT("} emit_profile_type");
2958 }
2959
2960 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
2961 Register obj = op->obj()->as_register();
2962 Register tmp = op->tmp()->as_pointer_register();
2963 bool not_null = op->not_null();
2964 int flag = op->flag();
2965
2966 Label not_inline_type;
2967 if (!not_null) {
2968 __ cbz(obj, not_inline_type);
2969 }
2970
2971 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
2972
2973 Address mdo_addr = as_Address(op->mdp()->as_address_ptr(), rscratch2);
2974 __ ldrb(rscratch1, mdo_addr);
2975 __ orr(rscratch1, rscratch1, flag);
2976 __ strb(rscratch1, mdo_addr);
2977
2978 __ bind(not_inline_type);
2979 }
2980
2981 void LIR_Assembler::align_backward_branch_target() {
2982 }
2983
2984
2985 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2986 // tmp must be unused
2987 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2988
2989 if (left->is_single_cpu()) {
2990 assert(dest->is_single_cpu(), "expect single result reg");
2991 __ negw(dest->as_register(), left->as_register());
2992 } else if (left->is_double_cpu()) {
2993 assert(dest->is_double_cpu(), "expect double result reg");
2994 __ neg(dest->as_register_lo(), left->as_register_lo());
2995 } else if (left->is_single_fpu()) {
2996 assert(dest->is_single_fpu(), "expect single float result reg");
2997 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2998 } else {
2999 assert(left->is_double_fpu(), "expect double float operand reg");
3000 assert(dest->is_double_fpu(), "expect double float result reg");
3001 __ fnegd(dest->as_double_reg(), left->as_double_reg());
3002 }
3003 }
3004
3005
3006 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3007 if (patch_code != lir_patch_none) {
3008 deoptimize_trap(info);
3009 return;
3010 }
3011
3012 __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
3013 }
3014
3015
3016 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3017 assert(!tmp->is_valid(), "don't need temporary");
3018
3019 CodeBlob *cb = CodeCache::find_blob(dest);
3020 if (cb) {
3021 __ far_call(RuntimeAddress(dest));
3022 } else {
3023 __ mov(rscratch1, RuntimeAddress(dest));
3024 __ blr(rscratch1);
3025 }
3026
3027 if (info != nullptr) {
3028 add_call_info_here(info);
3029 }
3030 __ post_call_nop();
3031 }
3032
3033 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3034 if (src->is_address()) {
3035 mem2reg(src, dest, type, lir_patch_none, info, /*wide*/false, /*is_volatile*/true);
3036 } else if (dest->is_address()) {
3037 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
3038 } else {
3039 ShouldNotReachHere();
3040 }
3041 }
3042
3043 #ifdef ASSERT
3044 // emit run-time assertion
3045 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3046 assert(op->code() == lir_assert, "must be");
3047
3048 if (op->in_opr1()->is_valid()) {
3049 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3050 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3051 } else {
3052 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3053 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3054 }
3055
3056 Label ok;
3057 if (op->condition() != lir_cond_always) {
3058 Assembler::Condition acond = Assembler::AL;
3059 switch (op->condition()) {
3060 case lir_cond_equal: acond = Assembler::EQ; break;
3061 case lir_cond_notEqual: acond = Assembler::NE; break;
3062 case lir_cond_less: acond = Assembler::LT; break;
3063 case lir_cond_lessEqual: acond = Assembler::LE; break;
3064 case lir_cond_greaterEqual: acond = Assembler::GE; break;
3065 case lir_cond_greater: acond = Assembler::GT; break;
3066 case lir_cond_belowEqual: acond = Assembler::LS; break;
3067 case lir_cond_aboveEqual: acond = Assembler::HS; break;
3068 default: ShouldNotReachHere();
3069 }
3070 __ br(acond, ok);
3071 }
3072 if (op->halt()) {
3073 const char* str = __ code_string(op->msg());
3074 __ stop(str);
3075 } else {
3076 breakpoint();
3077 }
3078 __ bind(ok);
3079 }
3080 #endif
3081
3082 #ifndef PRODUCT
3083 #define COMMENT(x) do { __ block_comment(x); } while (0)
3084 #else
3085 #define COMMENT(x)
3086 #endif
3087
3088 void LIR_Assembler::membar() {
3089 COMMENT("membar");
3090 __ membar(MacroAssembler::AnyAny);
3091 }
3092
3093 void LIR_Assembler::membar_acquire() {
3094 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
3095 }
3096
3097 void LIR_Assembler::membar_release() {
3098 __ membar(Assembler::LoadStore|Assembler::StoreStore);
3099 }
3100
3101 void LIR_Assembler::membar_loadload() {
3102 __ membar(Assembler::LoadLoad);
3103 }
3104
3105 void LIR_Assembler::membar_storestore() {
3106 __ membar(MacroAssembler::StoreStore);
3107 }
3108
3109 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3110
3111 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3112
3113 void LIR_Assembler::on_spin_wait() {
3114 __ spin_wait();
3115 }
3116
3117 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3118 __ mov(result_reg->as_register(), rthread);
3119 }
3120
3121 void LIR_Assembler::check_orig_pc() {
3122 __ ldr(rscratch2, frame_map()->address_for_orig_pc_addr());
3123 __ cmp(rscratch2, (u1)NULL_WORD);
3124 }
3125
3126 void LIR_Assembler::peephole(LIR_List *lir) {
3127 #if 0
3128 if (tableswitch_count >= max_tableswitches)
3129 return;
3130
3131 /*
3132 This finite-state automaton recognizes sequences of compare-and-
3133 branch instructions. We will turn them into a tableswitch. You
3134 could argue that C1 really shouldn't be doing this sort of
3135 optimization, but without it the code is really horrible.
3136 */
3137
3138 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3139 int first_key, last_key = -2147483648;
3140 int next_key = 0;
3141 int start_insn = -1;
3142 int last_insn = -1;
3143 Register reg = noreg;
3144 LIR_Opr reg_opr;
3145 state = start_s;
3146
3147 LIR_OpList* inst = lir->instructions_list();
3148 for (int i = 0; i < inst->length(); i++) {
3149 LIR_Op* op = inst->at(i);
3150 switch (state) {
3151 case start_s:
3152 first_key = -1;
3153 start_insn = i;
3154 switch (op->code()) {
3155 case lir_cmp:
3156 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3157 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3158 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3159 && opr2->is_constant()
3160 && opr2->type() == T_INT) {
3161 reg_opr = opr1;
3162 reg = opr1->as_register();
3163 first_key = opr2->as_constant_ptr()->as_jint();
3164 next_key = first_key + 1;
3165 state = cmp_s;
3166 goto next_state;
3167 }
3168 break;
3169 }
3170 break;
3171 case cmp_s:
3172 switch (op->code()) {
3173 case lir_branch:
3174 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3175 state = beq_s;
3176 last_insn = i;
3177 goto next_state;
3178 }
3179 }
3180 state = start_s;
3181 break;
3182 case beq_s:
3183 switch (op->code()) {
3184 case lir_cmp: {
3185 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3186 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3187 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3188 && opr1->as_register() == reg
3189 && opr2->is_constant()
3190 && opr2->type() == T_INT
3191 && opr2->as_constant_ptr()->as_jint() == next_key) {
3192 last_key = next_key;
3193 next_key++;
3194 state = cmp_s;
3195 goto next_state;
3196 }
3197 }
3198 }
3199 last_key = next_key;
3200 state = start_s;
3201 break;
3202 default:
3203 assert(false, "impossible state");
3204 }
3205 if (state == start_s) {
3206 if (first_key < last_key - 5L && reg != noreg) {
3207 {
3208 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3209 // reg->encoding(),
3210 // start_insn, first_key, last_key);
3211 // for (int i = 0; i < inst->length(); i++) {
3212 // inst->at(i)->print();
3213 // tty->print("\n");
3214 // }
3215 // tty->print("\n");
3216 }
3217
3218 struct tableswitch *sw = &switches[tableswitch_count];
3219 sw->_insn_index = start_insn, sw->_first_key = first_key,
3220 sw->_last_key = last_key, sw->_reg = reg;
3221 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3222 {
3223 // Insert the new table of branches
3224 int offset = last_insn;
3225 for (int n = first_key; n < last_key; n++) {
3226 inst->insert_before
3227 (last_insn + 1,
3228 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3229 inst->at(offset)->as_OpBranch()->label()));
3230 offset -= 2, i++;
3231 }
3232 }
3233 // Delete all the old compare-and-branch instructions
3234 for (int n = first_key; n < last_key; n++) {
3235 inst->remove_at(start_insn);
3236 inst->remove_at(start_insn);
3237 }
3238 // Insert the tableswitch instruction
3239 inst->insert_before(start_insn,
3240 new LIR_Op2(lir_cmp, lir_cond_always,
3241 LIR_OprFact::intConst(tableswitch_count),
3242 reg_opr));
3243 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3244 tableswitch_count++;
3245 }
3246 reg = noreg;
3247 last_key = -2147483648;
3248 }
3249 next_state:
3250 ;
3251 }
3252 #endif
3253 }
3254
3255 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3256 Address addr = as_Address(src->as_address_ptr());
3257 BasicType type = src->type();
3258 bool is_oop = is_reference_type(type);
3259
3260 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3261 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3262
3263 switch(type) {
3264 case T_INT:
3265 xchg = &MacroAssembler::atomic_xchgalw;
3266 add = &MacroAssembler::atomic_addalw;
3267 break;
3268 case T_LONG:
3269 xchg = &MacroAssembler::atomic_xchgal;
3270 add = &MacroAssembler::atomic_addal;
3271 break;
3272 case T_OBJECT:
3273 case T_ARRAY:
3274 if (UseCompressedOops) {
3275 xchg = &MacroAssembler::atomic_xchgalw;
3276 add = &MacroAssembler::atomic_addalw;
3277 } else {
3278 xchg = &MacroAssembler::atomic_xchgal;
3279 add = &MacroAssembler::atomic_addal;
3280 }
3281 break;
3282 default:
3283 ShouldNotReachHere();
3284 xchg = &MacroAssembler::atomic_xchgal;
3285 add = &MacroAssembler::atomic_addal; // unreachable
3286 }
3287
3288 switch (code) {
3289 case lir_xadd:
3290 {
3291 RegisterOrConstant inc;
3292 Register tmp = as_reg(tmp_op);
3293 Register dst = as_reg(dest);
3294 if (data->is_constant()) {
3295 inc = RegisterOrConstant(as_long(data));
3296 assert_different_registers(dst, addr.base(), tmp,
3297 rscratch1, rscratch2);
3298 } else {
3299 inc = RegisterOrConstant(as_reg(data));
3300 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3301 rscratch1, rscratch2);
3302 }
3303 __ lea(tmp, addr);
3304 (_masm->*add)(dst, inc, tmp);
3305 break;
3306 }
3307 case lir_xchg:
3308 {
3309 Register tmp = tmp_op->as_register();
3310 Register obj = as_reg(data);
3311 Register dst = as_reg(dest);
3312 if (is_oop && UseCompressedOops) {
3313 __ encode_heap_oop(rscratch2, obj);
3314 obj = rscratch2;
3315 }
3316 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3317 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3318 __ lea(tmp, addr);
3319 (_masm->*xchg)(dst, obj, tmp);
3320 if (is_oop && UseCompressedOops) {
3321 __ decode_heap_oop(dst);
3322 }
3323 }
3324 break;
3325 default:
3326 ShouldNotReachHere();
3327 }
3328 if(!UseLSE) {
3329 __ membar(__ AnyAny);
3330 }
3331 }
3332
3333 #undef __