1 /* 2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "asm/assembler.hpp" 29 #include "c1/c1_CodeStubs.hpp" 30 #include "c1/c1_Compilation.hpp" 31 #include "c1/c1_LIRAssembler.hpp" 32 #include "c1/c1_MacroAssembler.hpp" 33 #include "c1/c1_Runtime1.hpp" 34 #include "c1/c1_ValueStack.hpp" 35 #include "ci/ciArrayKlass.hpp" 36 #include "ci/ciInlineKlass.hpp" 37 #include "ci/ciInstance.hpp" 38 #include "code/compiledIC.hpp" 39 #include "gc/shared/collectedHeap.hpp" 40 #include "gc/shared/gc_globals.hpp" 41 #include "nativeInst_aarch64.hpp" 42 #include "oops/objArrayKlass.hpp" 43 #include "oops/oop.inline.hpp" 44 #include "runtime/frame.inline.hpp" 45 #include "runtime/sharedRuntime.hpp" 46 #include "runtime/stubRoutines.hpp" 47 #include "utilities/powerOfTwo.hpp" 48 #include "vmreg_aarch64.inline.hpp" 49 50 51 #ifndef PRODUCT 52 #define COMMENT(x) do { __ block_comment(x); } while (0) 53 #else 54 #define COMMENT(x) 55 #endif 56 57 NEEDS_CLEANUP // remove this definitions ? 58 const Register SYNC_header = r0; // synchronization header 59 const Register SHIFT_count = r0; // where count for shift operations must be 60 61 #define __ _masm-> 62 63 64 static void select_different_registers(Register preserve, 65 Register extra, 66 Register &tmp1, 67 Register &tmp2) { 68 if (tmp1 == preserve) { 69 assert_different_registers(tmp1, tmp2, extra); 70 tmp1 = extra; 71 } else if (tmp2 == preserve) { 72 assert_different_registers(tmp1, tmp2, extra); 73 tmp2 = extra; 74 } 75 assert_different_registers(preserve, tmp1, tmp2); 76 } 77 78 79 80 static void select_different_registers(Register preserve, 81 Register extra, 82 Register &tmp1, 83 Register &tmp2, 84 Register &tmp3) { 85 if (tmp1 == preserve) { 86 assert_different_registers(tmp1, tmp2, tmp3, extra); 87 tmp1 = extra; 88 } else if (tmp2 == preserve) { 89 assert_different_registers(tmp1, tmp2, tmp3, extra); 90 tmp2 = extra; 91 } else if (tmp3 == preserve) { 92 assert_different_registers(tmp1, tmp2, tmp3, extra); 93 tmp3 = extra; 94 } 95 assert_different_registers(preserve, tmp1, tmp2, tmp3); 96 } 97 98 99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; } 100 101 102 LIR_Opr LIR_Assembler::receiverOpr() { 103 return FrameMap::receiver_opr; 104 } 105 106 LIR_Opr LIR_Assembler::osrBufferPointer() { 107 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 108 } 109 110 //--------------fpu register translations----------------------- 111 112 113 address LIR_Assembler::float_constant(float f) { 114 address const_addr = __ float_constant(f); 115 if (const_addr == nullptr) { 116 bailout("const section overflow"); 117 return __ code()->consts()->start(); 118 } else { 119 return const_addr; 120 } 121 } 122 123 124 address LIR_Assembler::double_constant(double d) { 125 address const_addr = __ double_constant(d); 126 if (const_addr == nullptr) { 127 bailout("const section overflow"); 128 return __ code()->consts()->start(); 129 } else { 130 return const_addr; 131 } 132 } 133 134 address LIR_Assembler::int_constant(jlong n) { 135 address const_addr = __ long_constant(n); 136 if (const_addr == nullptr) { 137 bailout("const section overflow"); 138 return __ code()->consts()->start(); 139 } else { 140 return const_addr; 141 } 142 } 143 144 void LIR_Assembler::breakpoint() { Unimplemented(); } 145 146 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); } 147 148 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); } 149 150 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; } 151 //------------------------------------------- 152 153 static Register as_reg(LIR_Opr op) { 154 return op->is_double_cpu() ? op->as_register_lo() : op->as_register(); 155 } 156 157 static jlong as_long(LIR_Opr data) { 158 jlong result; 159 switch (data->type()) { 160 case T_INT: 161 result = (data->as_jint()); 162 break; 163 case T_LONG: 164 result = (data->as_jlong()); 165 break; 166 default: 167 ShouldNotReachHere(); 168 result = 0; // unreachable 169 } 170 return result; 171 } 172 173 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 174 Register base = addr->base()->as_pointer_register(); 175 LIR_Opr opr = addr->index(); 176 if (opr->is_cpu_register()) { 177 Register index; 178 if (opr->is_single_cpu()) 179 index = opr->as_register(); 180 else 181 index = opr->as_register_lo(); 182 assert(addr->disp() == 0, "must be"); 183 switch(opr->type()) { 184 case T_INT: 185 return Address(base, index, Address::sxtw(addr->scale())); 186 case T_LONG: 187 return Address(base, index, Address::lsl(addr->scale())); 188 default: 189 ShouldNotReachHere(); 190 } 191 } else { 192 assert(addr->scale() == 0, 193 "expected for immediate operand, was: %d", addr->scale()); 194 ptrdiff_t offset = ptrdiff_t(addr->disp()); 195 // NOTE: Does not handle any 16 byte vector access. 196 const uint type_size = type2aelembytes(addr->type(), true); 197 return __ legitimize_address(Address(base, offset), type_size, tmp); 198 } 199 return Address(); 200 } 201 202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 203 ShouldNotReachHere(); 204 return Address(); 205 } 206 207 Address LIR_Assembler::as_Address(LIR_Address* addr) { 208 return as_Address(addr, rscratch1); 209 } 210 211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 212 return as_Address(addr, rscratch1); // Ouch 213 // FIXME: This needs to be much more clever. See x86. 214 } 215 216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is 217 // not encodable as a base + (immediate) offset, generate an explicit address 218 // calculation to hold the address in a temporary register. 219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) { 220 precond(size == 4 || size == 8); 221 Address addr = frame_map()->address_for_slot(index, adjust); 222 precond(addr.getMode() == Address::base_plus_offset); 223 precond(addr.base() == sp); 224 precond(addr.offset() > 0); 225 uint mask = size - 1; 226 assert((addr.offset() & mask) == 0, "scaled offsets only"); 227 return __ legitimize_address(addr, size, tmp); 228 } 229 230 void LIR_Assembler::osr_entry() { 231 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 232 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 233 ValueStack* entry_state = osr_entry->state(); 234 int number_of_locks = entry_state->locks_size(); 235 236 // we jump here if osr happens with the interpreter 237 // state set up to continue at the beginning of the 238 // loop that triggered osr - in particular, we have 239 // the following registers setup: 240 // 241 // r2: osr buffer 242 // 243 244 // build frame 245 ciMethod* m = compilation()->method(); 246 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 247 248 // OSR buffer is 249 // 250 // locals[nlocals-1..0] 251 // monitors[0..number_of_locks] 252 // 253 // locals is a direct copy of the interpreter frame so in the osr buffer 254 // so first slot in the local array is the last local from the interpreter 255 // and last slot is local[0] (receiver) from the interpreter 256 // 257 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 258 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 259 // in the interpreter frame (the method lock if a sync method) 260 261 // Initialize monitors in the compiled activation. 262 // r2: pointer to osr buffer 263 // 264 // All other registers are dead at this point and the locals will be 265 // copied into place by code emitted in the IR. 266 267 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 268 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 269 int monitor_offset = BytesPerWord * method()->max_locals() + 270 (2 * BytesPerWord) * (number_of_locks - 1); 271 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 272 // the OSR buffer using 2 word entries: first the lock and then 273 // the oop. 274 for (int i = 0; i < number_of_locks; i++) { 275 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 276 #ifdef ASSERT 277 // verify the interpreter's monitor has a non-null object 278 { 279 Label L; 280 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 281 __ cbnz(rscratch1, L); 282 __ stop("locked object is null"); 283 __ bind(L); 284 } 285 #endif 286 __ ldr(r19, Address(OSR_buf, slot_offset)); 287 __ ldr(r20, Address(OSR_buf, slot_offset + BytesPerWord)); 288 __ str(r19, frame_map()->address_for_monitor_lock(i)); 289 __ str(r20, frame_map()->address_for_monitor_object(i)); 290 } 291 } 292 } 293 294 295 // inline cache check; done before the frame is built. 296 int LIR_Assembler::check_icache() { 297 return __ ic_check(CodeEntryAlignment); 298 } 299 300 void LIR_Assembler::clinit_barrier(ciMethod* method) { 301 assert(VM_Version::supports_fast_class_init_checks(), "sanity"); 302 assert(!method->holder()->is_not_initialized(), "initialization should have been started"); 303 304 Label L_skip_barrier; 305 306 __ mov_metadata(rscratch2, method->holder()->constant_encoding()); 307 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/); 308 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); 309 __ bind(L_skip_barrier); 310 } 311 312 void LIR_Assembler::jobject2reg(jobject o, Register reg) { 313 if (o == nullptr) { 314 __ mov(reg, zr); 315 } else { 316 __ movoop(reg, o); 317 } 318 } 319 320 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) { 321 address target = nullptr; 322 relocInfo::relocType reloc_type = relocInfo::none; 323 324 switch (patching_id(info)) { 325 case PatchingStub::access_field_id: 326 target = Runtime1::entry_for(Runtime1::access_field_patching_id); 327 reloc_type = relocInfo::section_word_type; 328 break; 329 case PatchingStub::load_klass_id: 330 target = Runtime1::entry_for(Runtime1::load_klass_patching_id); 331 reloc_type = relocInfo::metadata_type; 332 break; 333 case PatchingStub::load_mirror_id: 334 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id); 335 reloc_type = relocInfo::oop_type; 336 break; 337 case PatchingStub::load_appendix_id: 338 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id); 339 reloc_type = relocInfo::oop_type; 340 break; 341 default: ShouldNotReachHere(); 342 } 343 344 __ far_call(RuntimeAddress(target)); 345 add_call_info_here(info); 346 } 347 348 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 349 deoptimize_trap(info); 350 } 351 352 353 // This specifies the rsp decrement needed to build the frame 354 int LIR_Assembler::initial_frame_size_in_bytes() const { 355 // if rounding, must let FrameMap know! 356 357 return in_bytes(frame_map()->framesize_in_bytes()); 358 } 359 360 361 int LIR_Assembler::emit_exception_handler() { 362 // generate code for exception handler 363 address handler_base = __ start_a_stub(exception_handler_size()); 364 if (handler_base == nullptr) { 365 // not enough space left for the handler 366 bailout("exception handler overflow"); 367 return -1; 368 } 369 370 int offset = code_offset(); 371 372 // the exception oop and pc are in r0, and r3 373 // no other registers need to be preserved, so invalidate them 374 __ invalidate_registers(false, true, true, false, true, true); 375 376 // check that there is really an exception 377 __ verify_not_null_oop(r0); 378 379 // search an exception handler (r0: exception oop, r3: throwing pc) 380 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 381 __ should_not_reach_here(); 382 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 383 __ end_a_stub(); 384 385 return offset; 386 } 387 388 389 // Emit the code to remove the frame from the stack in the exception 390 // unwind path. 391 int LIR_Assembler::emit_unwind_handler() { 392 #ifndef PRODUCT 393 if (CommentedAssembly) { 394 _masm->block_comment("Unwind handler"); 395 } 396 #endif 397 398 int offset = code_offset(); 399 400 // Fetch the exception from TLS and clear out exception related thread state 401 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset())); 402 __ str(zr, Address(rthread, JavaThread::exception_oop_offset())); 403 __ str(zr, Address(rthread, JavaThread::exception_pc_offset())); 404 405 __ bind(_unwind_handler_entry); 406 __ verify_not_null_oop(r0); 407 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 408 __ mov(r19, r0); // Preserve the exception 409 } 410 411 // Perform needed unlocking 412 MonitorExitStub* stub = nullptr; 413 if (method()->is_synchronized()) { 414 monitor_address(0, FrameMap::r0_opr); 415 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0); 416 if (LockingMode == LM_MONITOR) { 417 __ b(*stub->entry()); 418 } else { 419 __ unlock_object(r5, r4, r0, r6, *stub->entry()); 420 } 421 __ bind(*stub->continuation()); 422 } 423 424 if (compilation()->env()->dtrace_method_probes()) { 425 __ mov(c_rarg0, rthread); 426 __ mov_metadata(c_rarg1, method()->constant_encoding()); 427 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1); 428 } 429 430 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 431 __ mov(r0, r19); // Restore the exception 432 } 433 434 // remove the activation and dispatch to the unwind handler 435 __ block_comment("remove_frame and dispatch to the unwind handler"); 436 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair()); 437 __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 438 439 // Emit the slow path assembly 440 if (stub != nullptr) { 441 stub->emit_code(this); 442 } 443 444 return offset; 445 } 446 447 448 int LIR_Assembler::emit_deopt_handler() { 449 // generate code for exception handler 450 address handler_base = __ start_a_stub(deopt_handler_size()); 451 if (handler_base == nullptr) { 452 // not enough space left for the handler 453 bailout("deopt handler overflow"); 454 return -1; 455 } 456 457 int offset = code_offset(); 458 459 __ adr(lr, pc()); 460 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 461 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 462 __ end_a_stub(); 463 464 return offset; 465 } 466 467 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) { 468 _masm->code_section()->relocate(adr, relocInfo::poll_type); 469 int pc_offset = code_offset(); 470 flush_debug_info(pc_offset); 471 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset); 472 if (info->exception_handlers() != nullptr) { 473 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers()); 474 } 475 } 476 477 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) { 478 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,"); 479 480 if (InlineTypeReturnedAsFields) { 481 // Check if we are returning an non-null inline type and load its fields into registers 482 ciType* return_type = compilation()->method()->return_type(); 483 if (return_type->is_inlinetype()) { 484 ciInlineKlass* vk = return_type->as_inline_klass(); 485 if (vk->can_be_returned_as_fields()) { 486 address unpack_handler = vk->unpack_handler(); 487 assert(unpack_handler != nullptr, "must be"); 488 __ far_call(RuntimeAddress(unpack_handler)); 489 } 490 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) { 491 Label skip; 492 __ test_oop_is_not_inline_type(r0, rscratch2, skip); 493 494 // Load fields from a buffered value with an inline class specific handler 495 __ load_klass(rscratch1 /*dst*/, r0 /*src*/); 496 __ ldr(rscratch1, Address(rscratch1, InstanceKlass::adr_inlineklass_fixed_block_offset())); 497 __ ldr(rscratch1, Address(rscratch1, InlineKlass::unpack_handler_offset())); 498 // Unpack handler can be null if inline type is not scalarizable in returns 499 __ cbz(rscratch1, skip); 500 __ blr(rscratch1); 501 502 __ bind(skip); 503 } 504 // At this point, r0 points to the value object (for interpreter or C1 caller). 505 // The fields of the object are copied into registers (for C2 caller). 506 } 507 508 // Pop the stack before the safepoint code 509 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair()); 510 511 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 512 __ reserved_stack_check(); 513 } 514 515 code_stub->set_safepoint_offset(__ offset()); 516 __ relocate(relocInfo::poll_return_type); 517 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */); 518 __ ret(lr); 519 } 520 521 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) { 522 return (__ store_inline_type_fields_to_buf(vk, false)); 523 } 524 525 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 526 guarantee(info != nullptr, "Shouldn't be null"); 527 __ get_polling_page(rscratch1, relocInfo::poll_type); 528 add_debug_info_for_branch(info); // This isn't just debug info: 529 // it's the oop map 530 __ read_polling_page(rscratch1, relocInfo::poll_type); 531 return __ offset(); 532 } 533 534 535 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 536 if (from_reg == r31_sp) 537 from_reg = sp; 538 if (to_reg == r31_sp) 539 to_reg = sp; 540 __ mov(to_reg, from_reg); 541 } 542 543 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); } 544 545 546 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 547 assert(src->is_constant(), "should not call otherwise"); 548 assert(dest->is_register(), "should not call otherwise"); 549 LIR_Const* c = src->as_constant_ptr(); 550 551 switch (c->type()) { 552 case T_INT: { 553 assert(patch_code == lir_patch_none, "no patching handled here"); 554 __ movw(dest->as_register(), c->as_jint()); 555 break; 556 } 557 558 case T_ADDRESS: { 559 assert(patch_code == lir_patch_none, "no patching handled here"); 560 __ mov(dest->as_register(), c->as_jint()); 561 break; 562 } 563 564 case T_LONG: { 565 assert(patch_code == lir_patch_none, "no patching handled here"); 566 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong()); 567 break; 568 } 569 570 case T_OBJECT: { 571 if (patch_code != lir_patch_none) { 572 jobject2reg_with_patching(dest->as_register(), info); 573 } else { 574 jobject2reg(c->as_jobject(), dest->as_register()); 575 } 576 break; 577 } 578 579 case T_METADATA: { 580 if (patch_code != lir_patch_none) { 581 klass2reg_with_patching(dest->as_register(), info); 582 } else { 583 __ mov_metadata(dest->as_register(), c->as_metadata()); 584 } 585 break; 586 } 587 588 case T_FLOAT: { 589 if (__ operand_valid_for_float_immediate(c->as_jfloat())) { 590 __ fmovs(dest->as_float_reg(), (c->as_jfloat())); 591 } else { 592 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat()))); 593 __ ldrs(dest->as_float_reg(), Address(rscratch1)); 594 } 595 break; 596 } 597 598 case T_DOUBLE: { 599 if (__ operand_valid_for_float_immediate(c->as_jdouble())) { 600 __ fmovd(dest->as_double_reg(), (c->as_jdouble())); 601 } else { 602 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble()))); 603 __ ldrd(dest->as_double_reg(), Address(rscratch1)); 604 } 605 break; 606 } 607 608 default: 609 ShouldNotReachHere(); 610 } 611 } 612 613 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 614 LIR_Const* c = src->as_constant_ptr(); 615 switch (c->type()) { 616 case T_OBJECT: 617 { 618 if (! c->as_jobject()) 619 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix())); 620 else { 621 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr); 622 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false); 623 } 624 } 625 break; 626 case T_ADDRESS: 627 { 628 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr); 629 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false); 630 } 631 case T_INT: 632 case T_FLOAT: 633 { 634 Register reg = zr; 635 if (c->as_jint_bits() == 0) 636 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix())); 637 else { 638 __ movw(rscratch1, c->as_jint_bits()); 639 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix())); 640 } 641 } 642 break; 643 case T_LONG: 644 case T_DOUBLE: 645 { 646 Register reg = zr; 647 if (c->as_jlong_bits() == 0) 648 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(), 649 lo_word_offset_in_bytes)); 650 else { 651 __ mov(rscratch1, (intptr_t)c->as_jlong_bits()); 652 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(), 653 lo_word_offset_in_bytes)); 654 } 655 } 656 break; 657 default: 658 ShouldNotReachHere(); 659 } 660 } 661 662 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 663 assert(src->is_constant(), "should not call otherwise"); 664 LIR_Const* c = src->as_constant_ptr(); 665 LIR_Address* to_addr = dest->as_address_ptr(); 666 667 void (Assembler::* insn)(Register Rt, const Address &adr); 668 669 switch (type) { 670 case T_ADDRESS: 671 assert(c->as_jint() == 0, "should be"); 672 insn = &Assembler::str; 673 break; 674 case T_LONG: 675 assert(c->as_jlong() == 0, "should be"); 676 insn = &Assembler::str; 677 break; 678 case T_INT: 679 assert(c->as_jint() == 0, "should be"); 680 insn = &Assembler::strw; 681 break; 682 case T_OBJECT: 683 case T_ARRAY: 684 // Non-null case is not handled on aarch64 but handled on x86 685 // FIXME: do we need to add it here? 686 assert(c->as_jobject() == 0, "should be"); 687 if (UseCompressedOops && !wide) { 688 insn = &Assembler::strw; 689 } else { 690 insn = &Assembler::str; 691 } 692 break; 693 case T_CHAR: 694 case T_SHORT: 695 assert(c->as_jint() == 0, "should be"); 696 insn = &Assembler::strh; 697 break; 698 case T_BOOLEAN: 699 case T_BYTE: 700 assert(c->as_jint() == 0, "should be"); 701 insn = &Assembler::strb; 702 break; 703 default: 704 ShouldNotReachHere(); 705 insn = &Assembler::str; // unreachable 706 } 707 708 if (info) add_debug_info_for_null_check_here(info); 709 (_masm->*insn)(zr, as_Address(to_addr, rscratch1)); 710 } 711 712 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 713 assert(src->is_register(), "should not call otherwise"); 714 assert(dest->is_register(), "should not call otherwise"); 715 716 // move between cpu-registers 717 if (dest->is_single_cpu()) { 718 if (src->type() == T_LONG) { 719 // Can do LONG -> OBJECT 720 move_regs(src->as_register_lo(), dest->as_register()); 721 return; 722 } 723 assert(src->is_single_cpu(), "must match"); 724 if (src->type() == T_OBJECT) { 725 __ verify_oop(src->as_register()); 726 } 727 move_regs(src->as_register(), dest->as_register()); 728 729 } else if (dest->is_double_cpu()) { 730 if (is_reference_type(src->type())) { 731 // Surprising to me but we can see move of a long to t_object 732 __ verify_oop(src->as_register()); 733 move_regs(src->as_register(), dest->as_register_lo()); 734 return; 735 } 736 assert(src->is_double_cpu(), "must match"); 737 Register f_lo = src->as_register_lo(); 738 Register f_hi = src->as_register_hi(); 739 Register t_lo = dest->as_register_lo(); 740 Register t_hi = dest->as_register_hi(); 741 assert(f_hi == f_lo, "must be same"); 742 assert(t_hi == t_lo, "must be same"); 743 move_regs(f_lo, t_lo); 744 745 } else if (dest->is_single_fpu()) { 746 __ fmovs(dest->as_float_reg(), src->as_float_reg()); 747 748 } else if (dest->is_double_fpu()) { 749 __ fmovd(dest->as_double_reg(), src->as_double_reg()); 750 751 } else { 752 ShouldNotReachHere(); 753 } 754 } 755 756 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 757 precond(src->is_register() && dest->is_stack()); 758 759 uint const c_sz32 = sizeof(uint32_t); 760 uint const c_sz64 = sizeof(uint64_t); 761 762 if (src->is_single_cpu()) { 763 int index = dest->single_stack_ix(); 764 if (is_reference_type(type)) { 765 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 766 __ verify_oop(src->as_register()); 767 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) { 768 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 769 } else { 770 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1)); 771 } 772 773 } else if (src->is_double_cpu()) { 774 int index = dest->double_stack_ix(); 775 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes); 776 __ str(src->as_register_lo(), dest_addr_LO); 777 778 } else if (src->is_single_fpu()) { 779 int index = dest->single_stack_ix(); 780 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1)); 781 782 } else if (src->is_double_fpu()) { 783 int index = dest->double_stack_ix(); 784 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1)); 785 786 } else { 787 ShouldNotReachHere(); 788 } 789 } 790 791 792 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) { 793 LIR_Address* to_addr = dest->as_address_ptr(); 794 PatchingStub* patch = nullptr; 795 Register compressed_src = rscratch1; 796 797 if (patch_code != lir_patch_none) { 798 deoptimize_trap(info); 799 return; 800 } 801 802 if (is_reference_type(type)) { 803 __ verify_oop(src->as_register()); 804 805 if (UseCompressedOops && !wide) { 806 __ encode_heap_oop(compressed_src, src->as_register()); 807 } else { 808 compressed_src = src->as_register(); 809 } 810 } 811 812 int null_check_here = code_offset(); 813 switch (type) { 814 case T_FLOAT: { 815 __ strs(src->as_float_reg(), as_Address(to_addr)); 816 break; 817 } 818 819 case T_DOUBLE: { 820 __ strd(src->as_double_reg(), as_Address(to_addr)); 821 break; 822 } 823 824 case T_ARRAY: // fall through 825 case T_OBJECT: // fall through 826 if (UseCompressedOops && !wide) { 827 __ strw(compressed_src, as_Address(to_addr, rscratch2)); 828 } else { 829 __ str(compressed_src, as_Address(to_addr)); 830 } 831 break; 832 case T_METADATA: 833 // We get here to store a method pointer to the stack to pass to 834 // a dtrace runtime call. This can't work on 64 bit with 835 // compressed klass ptrs: T_METADATA can be a compressed klass 836 // ptr or a 64 bit method pointer. 837 ShouldNotReachHere(); 838 __ str(src->as_register(), as_Address(to_addr)); 839 break; 840 case T_ADDRESS: 841 __ str(src->as_register(), as_Address(to_addr)); 842 break; 843 case T_INT: 844 __ strw(src->as_register(), as_Address(to_addr)); 845 break; 846 847 case T_LONG: { 848 __ str(src->as_register_lo(), as_Address_lo(to_addr)); 849 break; 850 } 851 852 case T_BYTE: // fall through 853 case T_BOOLEAN: { 854 __ strb(src->as_register(), as_Address(to_addr)); 855 break; 856 } 857 858 case T_CHAR: // fall through 859 case T_SHORT: 860 __ strh(src->as_register(), as_Address(to_addr)); 861 break; 862 863 default: 864 ShouldNotReachHere(); 865 } 866 if (info != nullptr) { 867 add_debug_info_for_null_check(null_check_here, info); 868 } 869 } 870 871 872 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 873 precond(src->is_stack() && dest->is_register()); 874 875 uint const c_sz32 = sizeof(uint32_t); 876 uint const c_sz64 = sizeof(uint64_t); 877 878 if (dest->is_single_cpu()) { 879 int index = src->single_stack_ix(); 880 if (is_reference_type(type)) { 881 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 882 __ verify_oop(dest->as_register()); 883 } else if (type == T_METADATA || type == T_ADDRESS) { 884 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 885 } else { 886 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1)); 887 } 888 889 } else if (dest->is_double_cpu()) { 890 int index = src->double_stack_ix(); 891 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes); 892 __ ldr(dest->as_register_lo(), src_addr_LO); 893 894 } else if (dest->is_single_fpu()) { 895 int index = src->single_stack_ix(); 896 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1)); 897 898 } else if (dest->is_double_fpu()) { 899 int index = src->double_stack_ix(); 900 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1)); 901 902 } else { 903 ShouldNotReachHere(); 904 } 905 } 906 907 908 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 909 address target = nullptr; 910 relocInfo::relocType reloc_type = relocInfo::none; 911 912 switch (patching_id(info)) { 913 case PatchingStub::access_field_id: 914 target = Runtime1::entry_for(Runtime1::access_field_patching_id); 915 reloc_type = relocInfo::section_word_type; 916 break; 917 case PatchingStub::load_klass_id: 918 target = Runtime1::entry_for(Runtime1::load_klass_patching_id); 919 reloc_type = relocInfo::metadata_type; 920 break; 921 case PatchingStub::load_mirror_id: 922 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id); 923 reloc_type = relocInfo::oop_type; 924 break; 925 case PatchingStub::load_appendix_id: 926 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id); 927 reloc_type = relocInfo::oop_type; 928 break; 929 default: ShouldNotReachHere(); 930 } 931 932 __ far_call(RuntimeAddress(target)); 933 add_call_info_here(info); 934 } 935 936 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 937 938 LIR_Opr temp; 939 if (type == T_LONG || type == T_DOUBLE) 940 temp = FrameMap::rscratch1_long_opr; 941 else 942 temp = FrameMap::rscratch1_opr; 943 944 stack2reg(src, temp, src->type()); 945 reg2stack(temp, dest, dest->type(), false); 946 } 947 948 949 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { 950 LIR_Address* addr = src->as_address_ptr(); 951 LIR_Address* from_addr = src->as_address_ptr(); 952 953 if (addr->base()->type() == T_OBJECT) { 954 __ verify_oop(addr->base()->as_pointer_register()); 955 } 956 957 if (patch_code != lir_patch_none) { 958 deoptimize_trap(info); 959 return; 960 } 961 962 if (info != nullptr) { 963 add_debug_info_for_null_check_here(info); 964 } 965 int null_check_here = code_offset(); 966 switch (type) { 967 case T_FLOAT: { 968 __ ldrs(dest->as_float_reg(), as_Address(from_addr)); 969 break; 970 } 971 972 case T_DOUBLE: { 973 __ ldrd(dest->as_double_reg(), as_Address(from_addr)); 974 break; 975 } 976 977 case T_ARRAY: // fall through 978 case T_OBJECT: // fall through 979 if (UseCompressedOops && !wide) { 980 __ ldrw(dest->as_register(), as_Address(from_addr)); 981 } else { 982 __ ldr(dest->as_register(), as_Address(from_addr)); 983 } 984 break; 985 case T_METADATA: 986 // We get here to store a method pointer to the stack to pass to 987 // a dtrace runtime call. This can't work on 64 bit with 988 // compressed klass ptrs: T_METADATA can be a compressed klass 989 // ptr or a 64 bit method pointer. 990 ShouldNotReachHere(); 991 __ ldr(dest->as_register(), as_Address(from_addr)); 992 break; 993 case T_ADDRESS: 994 __ ldr(dest->as_register(), as_Address(from_addr)); 995 break; 996 case T_INT: 997 __ ldrw(dest->as_register(), as_Address(from_addr)); 998 break; 999 1000 case T_LONG: { 1001 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr)); 1002 break; 1003 } 1004 1005 case T_BYTE: 1006 __ ldrsb(dest->as_register(), as_Address(from_addr)); 1007 break; 1008 case T_BOOLEAN: { 1009 __ ldrb(dest->as_register(), as_Address(from_addr)); 1010 break; 1011 } 1012 1013 case T_CHAR: 1014 __ ldrh(dest->as_register(), as_Address(from_addr)); 1015 break; 1016 case T_SHORT: 1017 __ ldrsh(dest->as_register(), as_Address(from_addr)); 1018 break; 1019 1020 default: 1021 ShouldNotReachHere(); 1022 } 1023 1024 if (is_reference_type(type)) { 1025 if (UseCompressedOops && !wide) { 1026 __ decode_heap_oop(dest->as_register()); 1027 } 1028 1029 if (!(UseZGC && !ZGenerational)) { 1030 // Load barrier has not yet been applied, so ZGC can't verify the oop here 1031 __ verify_oop(dest->as_register()); 1032 } 1033 } 1034 } 1035 1036 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) { 1037 assert(dst->is_cpu_register(), "must be"); 1038 assert(dst->type() == src->type(), "must be"); 1039 1040 if (src->is_cpu_register()) { 1041 reg2reg(src, dst); 1042 } else if (src->is_stack()) { 1043 stack2reg(src, dst, dst->type()); 1044 } else if (src->is_constant()) { 1045 const2reg(src, dst, lir_patch_none, nullptr); 1046 } else { 1047 ShouldNotReachHere(); 1048 } 1049 } 1050 1051 int LIR_Assembler::array_element_size(BasicType type) const { 1052 int elem_size = type2aelembytes(type); 1053 return exact_log2(elem_size); 1054 } 1055 1056 1057 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1058 switch (op->code()) { 1059 case lir_idiv: 1060 case lir_irem: 1061 arithmetic_idiv(op->code(), 1062 op->in_opr1(), 1063 op->in_opr2(), 1064 op->in_opr3(), 1065 op->result_opr(), 1066 op->info()); 1067 break; 1068 case lir_fmad: 1069 __ fmaddd(op->result_opr()->as_double_reg(), 1070 op->in_opr1()->as_double_reg(), 1071 op->in_opr2()->as_double_reg(), 1072 op->in_opr3()->as_double_reg()); 1073 break; 1074 case lir_fmaf: 1075 __ fmadds(op->result_opr()->as_float_reg(), 1076 op->in_opr1()->as_float_reg(), 1077 op->in_opr2()->as_float_reg(), 1078 op->in_opr3()->as_float_reg()); 1079 break; 1080 default: ShouldNotReachHere(); break; 1081 } 1082 } 1083 1084 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1085 #ifdef ASSERT 1086 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label"); 1087 if (op->block() != nullptr) _branch_target_blocks.append(op->block()); 1088 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock()); 1089 #endif 1090 1091 if (op->cond() == lir_cond_always) { 1092 if (op->info() != nullptr) add_debug_info_for_branch(op->info()); 1093 __ b(*(op->label())); 1094 } else { 1095 Assembler::Condition acond; 1096 if (op->code() == lir_cond_float_branch) { 1097 bool is_unordered = (op->ublock() == op->block()); 1098 // Assembler::EQ does not permit unordered branches, so we add 1099 // another branch here. Likewise, Assembler::NE does not permit 1100 // ordered branches. 1101 if ((is_unordered && op->cond() == lir_cond_equal) 1102 || (!is_unordered && op->cond() == lir_cond_notEqual)) 1103 __ br(Assembler::VS, *(op->ublock()->label())); 1104 switch(op->cond()) { 1105 case lir_cond_equal: acond = Assembler::EQ; break; 1106 case lir_cond_notEqual: acond = Assembler::NE; break; 1107 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break; 1108 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break; 1109 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break; 1110 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break; 1111 default: ShouldNotReachHere(); 1112 acond = Assembler::EQ; // unreachable 1113 } 1114 } else { 1115 switch (op->cond()) { 1116 case lir_cond_equal: acond = Assembler::EQ; break; 1117 case lir_cond_notEqual: acond = Assembler::NE; break; 1118 case lir_cond_less: acond = Assembler::LT; break; 1119 case lir_cond_lessEqual: acond = Assembler::LE; break; 1120 case lir_cond_greaterEqual: acond = Assembler::GE; break; 1121 case lir_cond_greater: acond = Assembler::GT; break; 1122 case lir_cond_belowEqual: acond = Assembler::LS; break; 1123 case lir_cond_aboveEqual: acond = Assembler::HS; break; 1124 default: ShouldNotReachHere(); 1125 acond = Assembler::EQ; // unreachable 1126 } 1127 } 1128 __ br(acond,*(op->label())); 1129 } 1130 } 1131 1132 1133 1134 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1135 LIR_Opr src = op->in_opr(); 1136 LIR_Opr dest = op->result_opr(); 1137 1138 switch (op->bytecode()) { 1139 case Bytecodes::_i2f: 1140 { 1141 __ scvtfws(dest->as_float_reg(), src->as_register()); 1142 break; 1143 } 1144 case Bytecodes::_i2d: 1145 { 1146 __ scvtfwd(dest->as_double_reg(), src->as_register()); 1147 break; 1148 } 1149 case Bytecodes::_l2d: 1150 { 1151 __ scvtfd(dest->as_double_reg(), src->as_register_lo()); 1152 break; 1153 } 1154 case Bytecodes::_l2f: 1155 { 1156 __ scvtfs(dest->as_float_reg(), src->as_register_lo()); 1157 break; 1158 } 1159 case Bytecodes::_f2d: 1160 { 1161 __ fcvts(dest->as_double_reg(), src->as_float_reg()); 1162 break; 1163 } 1164 case Bytecodes::_d2f: 1165 { 1166 __ fcvtd(dest->as_float_reg(), src->as_double_reg()); 1167 break; 1168 } 1169 case Bytecodes::_i2c: 1170 { 1171 __ ubfx(dest->as_register(), src->as_register(), 0, 16); 1172 break; 1173 } 1174 case Bytecodes::_i2l: 1175 { 1176 __ sxtw(dest->as_register_lo(), src->as_register()); 1177 break; 1178 } 1179 case Bytecodes::_i2s: 1180 { 1181 __ sxth(dest->as_register(), src->as_register()); 1182 break; 1183 } 1184 case Bytecodes::_i2b: 1185 { 1186 __ sxtb(dest->as_register(), src->as_register()); 1187 break; 1188 } 1189 case Bytecodes::_l2i: 1190 { 1191 _masm->block_comment("FIXME: This could be a no-op"); 1192 __ uxtw(dest->as_register(), src->as_register_lo()); 1193 break; 1194 } 1195 case Bytecodes::_d2l: 1196 { 1197 __ fcvtzd(dest->as_register_lo(), src->as_double_reg()); 1198 break; 1199 } 1200 case Bytecodes::_f2i: 1201 { 1202 __ fcvtzsw(dest->as_register(), src->as_float_reg()); 1203 break; 1204 } 1205 case Bytecodes::_f2l: 1206 { 1207 __ fcvtzs(dest->as_register_lo(), src->as_float_reg()); 1208 break; 1209 } 1210 case Bytecodes::_d2i: 1211 { 1212 __ fcvtzdw(dest->as_register(), src->as_double_reg()); 1213 break; 1214 } 1215 default: ShouldNotReachHere(); 1216 } 1217 } 1218 1219 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1220 if (op->init_check()) { 1221 __ ldrb(rscratch1, Address(op->klass()->as_register(), 1222 InstanceKlass::init_state_offset())); 1223 __ cmpw(rscratch1, InstanceKlass::fully_initialized); 1224 add_debug_info_for_null_check_here(op->stub()->info()); 1225 __ br(Assembler::NE, *op->stub()->entry()); 1226 } 1227 __ allocate_object(op->obj()->as_register(), 1228 op->tmp1()->as_register(), 1229 op->tmp2()->as_register(), 1230 op->header_size(), 1231 op->object_size(), 1232 op->klass()->as_register(), 1233 *op->stub()->entry()); 1234 __ bind(*op->stub()->continuation()); 1235 } 1236 1237 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1238 Register len = op->len()->as_register(); 1239 __ uxtw(len, len); 1240 1241 if (UseSlowPath || op->is_null_free() || 1242 (!UseFastNewObjectArray && is_reference_type(op->type())) || 1243 (!UseFastNewTypeArray && !is_reference_type(op->type()))) { 1244 __ b(*op->stub()->entry()); 1245 } else { 1246 Register tmp1 = op->tmp1()->as_register(); 1247 Register tmp2 = op->tmp2()->as_register(); 1248 Register tmp3 = op->tmp3()->as_register(); 1249 if (len == tmp1) { 1250 tmp1 = tmp3; 1251 } else if (len == tmp2) { 1252 tmp2 = tmp3; 1253 } else if (len == tmp3) { 1254 // everything is ok 1255 } else { 1256 __ mov(tmp3, len); 1257 } 1258 __ allocate_array(op->obj()->as_register(), 1259 len, 1260 tmp1, 1261 tmp2, 1262 arrayOopDesc::base_offset_in_bytes(op->type()), 1263 array_element_size(op->type()), 1264 op->klass()->as_register(), 1265 *op->stub()->entry()); 1266 } 1267 __ bind(*op->stub()->continuation()); 1268 } 1269 1270 void LIR_Assembler::type_profile_helper(Register mdo, 1271 ciMethodData *md, ciProfileData *data, 1272 Register recv, Label* update_done) { 1273 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1274 Label next_test; 1275 // See if the receiver is receiver[n]. 1276 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1277 __ ldr(rscratch1, Address(rscratch2)); 1278 __ cmp(recv, rscratch1); 1279 __ br(Assembler::NE, next_test); 1280 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1281 __ addptr(data_addr, DataLayout::counter_increment); 1282 __ b(*update_done); 1283 __ bind(next_test); 1284 } 1285 1286 // Didn't find receiver; find next empty slot and fill it in 1287 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1288 Label next_test; 1289 __ lea(rscratch2, 1290 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1291 Address recv_addr(rscratch2); 1292 __ ldr(rscratch1, recv_addr); 1293 __ cbnz(rscratch1, next_test); 1294 __ str(recv, recv_addr); 1295 __ mov(rscratch1, DataLayout::counter_increment); 1296 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)))); 1297 __ str(rscratch1, Address(rscratch2)); 1298 __ b(*update_done); 1299 __ bind(next_test); 1300 } 1301 } 1302 1303 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1304 // we always need a stub for the failure case. 1305 CodeStub* stub = op->stub(); 1306 Register obj = op->object()->as_register(); 1307 Register k_RInfo = op->tmp1()->as_register(); 1308 Register klass_RInfo = op->tmp2()->as_register(); 1309 Register dst = op->result_opr()->as_register(); 1310 ciKlass* k = op->klass(); 1311 Register Rtmp1 = noreg; 1312 1313 // check if it needs to be profiled 1314 ciMethodData* md; 1315 ciProfileData* data; 1316 1317 const bool should_profile = op->should_profile(); 1318 1319 if (should_profile) { 1320 ciMethod* method = op->profiled_method(); 1321 assert(method != nullptr, "Should have method"); 1322 int bci = op->profiled_bci(); 1323 md = method->method_data_or_null(); 1324 assert(md != nullptr, "Sanity"); 1325 data = md->bci_to_data(bci); 1326 assert(data != nullptr, "need data for type check"); 1327 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1328 } 1329 Label* success_target = success; 1330 Label* failure_target = failure; 1331 1332 if (obj == k_RInfo) { 1333 k_RInfo = dst; 1334 } else if (obj == klass_RInfo) { 1335 klass_RInfo = dst; 1336 } 1337 if (k->is_loaded() && !UseCompressedClassPointers) { 1338 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1339 } else { 1340 Rtmp1 = op->tmp3()->as_register(); 1341 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1342 } 1343 1344 assert_different_registers(obj, k_RInfo, klass_RInfo); 1345 1346 if (op->need_null_check()) { 1347 if (should_profile) { 1348 Register mdo = klass_RInfo; 1349 __ mov_metadata(mdo, md->constant_encoding()); 1350 Label not_null; 1351 __ cbnz(obj, not_null); 1352 // Object is null; update MDO and exit 1353 Address data_addr 1354 = __ form_address(rscratch2, mdo, 1355 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 1356 0); 1357 __ ldrb(rscratch1, data_addr); 1358 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant()); 1359 __ strb(rscratch1, data_addr); 1360 __ b(*obj_is_null); 1361 __ bind(not_null); 1362 1363 Label update_done; 1364 Register recv = k_RInfo; 1365 __ load_klass(recv, obj); 1366 type_profile_helper(mdo, md, data, recv, &update_done); 1367 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1368 __ addptr(counter_addr, DataLayout::counter_increment); 1369 1370 __ bind(update_done); 1371 } else { 1372 __ cbz(obj, *obj_is_null); 1373 } 1374 } 1375 1376 if (!k->is_loaded()) { 1377 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1378 } else { 1379 __ mov_metadata(k_RInfo, k->constant_encoding()); 1380 } 1381 __ verify_oop(obj); 1382 1383 if (op->fast_check()) { 1384 // get object class 1385 // not a safepoint as obj null check happens earlier 1386 __ load_klass(rscratch1, obj); 1387 __ cmp( rscratch1, k_RInfo); 1388 1389 __ br(Assembler::NE, *failure_target); 1390 // successful cast, fall through to profile or jump 1391 } else { 1392 // get object class 1393 // not a safepoint as obj null check happens earlier 1394 __ load_klass(klass_RInfo, obj); 1395 if (k->is_loaded()) { 1396 // See if we get an immediate positive hit 1397 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset()))); 1398 __ cmp(k_RInfo, rscratch1); 1399 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1400 __ br(Assembler::NE, *failure_target); 1401 // successful cast, fall through to profile or jump 1402 } else { 1403 // See if we get an immediate positive hit 1404 __ br(Assembler::EQ, *success_target); 1405 // check for self 1406 __ cmp(klass_RInfo, k_RInfo); 1407 __ br(Assembler::EQ, *success_target); 1408 1409 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); 1410 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1411 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize))); 1412 // result is a boolean 1413 __ cbzw(klass_RInfo, *failure_target); 1414 // successful cast, fall through to profile or jump 1415 } 1416 } else { 1417 // perform the fast part of the checking logic 1418 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr); 1419 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1420 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); 1421 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1422 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize))); 1423 // result is a boolean 1424 __ cbz(k_RInfo, *failure_target); 1425 // successful cast, fall through to profile or jump 1426 } 1427 } 1428 __ b(*success); 1429 } 1430 1431 1432 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1433 const bool should_profile = op->should_profile(); 1434 1435 LIR_Code code = op->code(); 1436 if (code == lir_store_check) { 1437 Register value = op->object()->as_register(); 1438 Register array = op->array()->as_register(); 1439 Register k_RInfo = op->tmp1()->as_register(); 1440 Register klass_RInfo = op->tmp2()->as_register(); 1441 Register Rtmp1 = op->tmp3()->as_register(); 1442 1443 CodeStub* stub = op->stub(); 1444 1445 // check if it needs to be profiled 1446 ciMethodData* md; 1447 ciProfileData* data; 1448 1449 if (should_profile) { 1450 ciMethod* method = op->profiled_method(); 1451 assert(method != nullptr, "Should have method"); 1452 int bci = op->profiled_bci(); 1453 md = method->method_data_or_null(); 1454 assert(md != nullptr, "Sanity"); 1455 data = md->bci_to_data(bci); 1456 assert(data != nullptr, "need data for type check"); 1457 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1458 } 1459 Label done; 1460 Label* success_target = &done; 1461 Label* failure_target = stub->entry(); 1462 1463 if (should_profile) { 1464 Label not_null; 1465 Register mdo = klass_RInfo; 1466 __ mov_metadata(mdo, md->constant_encoding()); 1467 __ cbnz(value, not_null); 1468 // Object is null; update MDO and exit 1469 Address data_addr 1470 = __ form_address(rscratch2, mdo, 1471 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 1472 0); 1473 __ ldrb(rscratch1, data_addr); 1474 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant()); 1475 __ strb(rscratch1, data_addr); 1476 __ b(done); 1477 __ bind(not_null); 1478 1479 Label update_done; 1480 Register recv = k_RInfo; 1481 __ load_klass(recv, value); 1482 type_profile_helper(mdo, md, data, recv, &update_done); 1483 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1484 __ addptr(counter_addr, DataLayout::counter_increment); 1485 __ bind(update_done); 1486 } else { 1487 __ cbz(value, done); 1488 } 1489 1490 add_debug_info_for_null_check_here(op->info_for_exception()); 1491 __ load_klass(k_RInfo, array); 1492 __ load_klass(klass_RInfo, value); 1493 1494 // get instance klass (it's already uncompressed) 1495 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1496 // perform the fast part of the checking logic 1497 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr); 1498 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1499 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); 1500 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1501 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize))); 1502 // result is a boolean 1503 __ cbzw(k_RInfo, *failure_target); 1504 // fall through to the success case 1505 1506 __ bind(done); 1507 } else if (code == lir_checkcast) { 1508 Register obj = op->object()->as_register(); 1509 Register dst = op->result_opr()->as_register(); 1510 Label success; 1511 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1512 __ bind(success); 1513 if (dst != obj) { 1514 __ mov(dst, obj); 1515 } 1516 } else if (code == lir_instanceof) { 1517 Register obj = op->object()->as_register(); 1518 Register dst = op->result_opr()->as_register(); 1519 Label success, failure, done; 1520 emit_typecheck_helper(op, &success, &failure, &failure); 1521 __ bind(failure); 1522 __ mov(dst, zr); 1523 __ b(done); 1524 __ bind(success); 1525 __ mov(dst, 1); 1526 __ bind(done); 1527 } else { 1528 ShouldNotReachHere(); 1529 } 1530 } 1531 1532 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) { 1533 // We are loading/storing from/to an array that *may* be a flat array (the 1534 // declared type is Object[], abstract[], interface[] or VT.ref[]). 1535 // If this array is a flat array, take the slow path. 1536 __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry()); 1537 if (!op->value()->is_illegal()) { 1538 // The array is not a flat array, but it might be null-free. If we are storing 1539 // a null into a null-free array, take the slow path (which will throw NPE). 1540 Label skip; 1541 __ cbnz(op->value()->as_register(), skip); 1542 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry()); 1543 __ bind(skip); 1544 } 1545 } 1546 1547 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) { 1548 // We are storing into an array that *may* be null-free (the declared type is 1549 // Object[], abstract[], interface[] or VT.ref[]). 1550 Label test_mark_word; 1551 Register tmp = op->tmp()->as_register(); 1552 __ ldr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes())); 1553 __ tst(tmp, markWord::unlocked_value); 1554 __ br(Assembler::NE, test_mark_word); 1555 __ load_prototype_header(tmp, op->array()->as_register()); 1556 __ bind(test_mark_word); 1557 __ tst(tmp, markWord::null_free_array_bit_in_place); 1558 } 1559 1560 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) { 1561 Label L_oops_equal; 1562 Label L_oops_not_equal; 1563 Label L_end; 1564 1565 Register left = op->left()->as_register(); 1566 Register right = op->right()->as_register(); 1567 1568 __ cmp(left, right); 1569 __ br(Assembler::EQ, L_oops_equal); 1570 1571 // (1) Null check -- if one of the operands is null, the other must not be null (because 1572 // the two references are not equal), so they are not substitutable, 1573 // FIXME: do null check only if the operand is nullable 1574 { 1575 __ cbz(left, L_oops_not_equal); 1576 __ cbz(right, L_oops_not_equal); 1577 } 1578 1579 ciKlass* left_klass = op->left_klass(); 1580 ciKlass* right_klass = op->right_klass(); 1581 1582 // (2) Inline type check -- if either of the operands is not a inline type, 1583 // they are not substitutable. We do this only if we are not sure that the 1584 // operands are inline type 1585 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node. 1586 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) { 1587 Register tmp1 = op->tmp1()->as_register(); 1588 __ mov(tmp1, markWord::inline_type_pattern); 1589 __ ldr(rscratch1, Address(left, oopDesc::mark_offset_in_bytes())); 1590 __ andr(tmp1, tmp1, rscratch1); 1591 __ ldr(rscratch1, Address(right, oopDesc::mark_offset_in_bytes())); 1592 __ andr(tmp1, tmp1, rscratch1); 1593 __ cmp(tmp1, (u1)markWord::inline_type_pattern); 1594 __ br(Assembler::NE, L_oops_not_equal); 1595 } 1596 1597 // (3) Same klass check: if the operands are of different klasses, they are not substitutable. 1598 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) { 1599 // No need to load klass -- the operands are statically known to be the same inline klass. 1600 __ b(*op->stub()->entry()); 1601 } else { 1602 Register left_klass_op = op->left_klass_op()->as_register(); 1603 Register right_klass_op = op->right_klass_op()->as_register(); 1604 1605 if (UseCompressedClassPointers) { 1606 __ ldrw(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes())); 1607 __ ldrw(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes())); 1608 __ cmpw(left_klass_op, right_klass_op); 1609 } else { 1610 __ ldr(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes())); 1611 __ ldr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes())); 1612 __ cmp(left_klass_op, right_klass_op); 1613 } 1614 1615 __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check 1616 // fall through to L_oops_not_equal 1617 } 1618 1619 __ bind(L_oops_not_equal); 1620 move(op->not_equal_result(), op->result_opr()); 1621 __ b(L_end); 1622 1623 __ bind(L_oops_equal); 1624 move(op->equal_result(), op->result_opr()); 1625 __ b(L_end); 1626 1627 // We've returned from the stub. R0 contains 0x0 IFF the two 1628 // operands are not substitutable. (Don't compare against 0x1 in case the 1629 // C compiler is naughty) 1630 __ bind(*op->stub()->continuation()); 1631 __ cbz(r0, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal 1632 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal 1633 // fall-through 1634 __ bind(L_end); 1635 } 1636 1637 1638 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) { 1639 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1); 1640 __ cset(rscratch1, Assembler::NE); 1641 __ membar(__ AnyAny); 1642 } 1643 1644 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) { 1645 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1); 1646 __ cset(rscratch1, Assembler::NE); 1647 __ membar(__ AnyAny); 1648 } 1649 1650 1651 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1652 Register addr; 1653 if (op->addr()->is_register()) { 1654 addr = as_reg(op->addr()); 1655 } else { 1656 assert(op->addr()->is_address(), "what else?"); 1657 LIR_Address* addr_ptr = op->addr()->as_address_ptr(); 1658 assert(addr_ptr->disp() == 0, "need 0 disp"); 1659 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index"); 1660 addr = as_reg(addr_ptr->base()); 1661 } 1662 Register newval = as_reg(op->new_value()); 1663 Register cmpval = as_reg(op->cmp_value()); 1664 1665 if (op->code() == lir_cas_obj) { 1666 if (UseCompressedOops) { 1667 Register t1 = op->tmp1()->as_register(); 1668 assert(op->tmp1()->is_valid(), "must be"); 1669 __ encode_heap_oop(t1, cmpval); 1670 cmpval = t1; 1671 __ encode_heap_oop(rscratch2, newval); 1672 newval = rscratch2; 1673 casw(addr, newval, cmpval); 1674 } else { 1675 casl(addr, newval, cmpval); 1676 } 1677 } else if (op->code() == lir_cas_int) { 1678 casw(addr, newval, cmpval); 1679 } else { 1680 casl(addr, newval, cmpval); 1681 } 1682 } 1683 1684 1685 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type, 1686 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) { 1687 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64"); 1688 1689 Assembler::Condition acond, ncond; 1690 switch (condition) { 1691 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break; 1692 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break; 1693 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break; 1694 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break; 1695 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break; 1696 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break; 1697 case lir_cond_belowEqual: 1698 case lir_cond_aboveEqual: 1699 default: ShouldNotReachHere(); 1700 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable 1701 } 1702 1703 assert(result->is_single_cpu() || result->is_double_cpu(), 1704 "expect single register for result"); 1705 if (opr1->is_constant() && opr2->is_constant() 1706 && opr1->type() == T_INT && opr2->type() == T_INT) { 1707 jint val1 = opr1->as_jint(); 1708 jint val2 = opr2->as_jint(); 1709 if (val1 == 0 && val2 == 1) { 1710 __ cset(result->as_register(), ncond); 1711 return; 1712 } else if (val1 == 1 && val2 == 0) { 1713 __ cset(result->as_register(), acond); 1714 return; 1715 } 1716 } 1717 1718 if (opr1->is_constant() && opr2->is_constant() 1719 && opr1->type() == T_LONG && opr2->type() == T_LONG) { 1720 jlong val1 = opr1->as_jlong(); 1721 jlong val2 = opr2->as_jlong(); 1722 if (val1 == 0 && val2 == 1) { 1723 __ cset(result->as_register_lo(), ncond); 1724 return; 1725 } else if (val1 == 1 && val2 == 0) { 1726 __ cset(result->as_register_lo(), acond); 1727 return; 1728 } 1729 } 1730 1731 if (opr1->is_stack()) { 1732 stack2reg(opr1, FrameMap::rscratch1_opr, result->type()); 1733 opr1 = FrameMap::rscratch1_opr; 1734 } else if (opr1->is_constant()) { 1735 LIR_Opr tmp 1736 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr; 1737 const2reg(opr1, tmp, lir_patch_none, nullptr); 1738 opr1 = tmp; 1739 } 1740 1741 if (opr2->is_stack()) { 1742 stack2reg(opr2, FrameMap::rscratch2_opr, result->type()); 1743 opr2 = FrameMap::rscratch2_opr; 1744 } else if (opr2->is_constant()) { 1745 LIR_Opr tmp 1746 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr; 1747 const2reg(opr2, tmp, lir_patch_none, nullptr); 1748 opr2 = tmp; 1749 } 1750 1751 if (result->type() == T_LONG) 1752 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond); 1753 else 1754 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond); 1755 } 1756 1757 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 1758 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 1759 1760 if (left->is_single_cpu()) { 1761 Register lreg = left->as_register(); 1762 Register dreg = as_reg(dest); 1763 1764 if (right->is_single_cpu()) { 1765 // cpu register - cpu register 1766 1767 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT, 1768 "should be"); 1769 Register rreg = right->as_register(); 1770 switch (code) { 1771 case lir_add: __ addw (dest->as_register(), lreg, rreg); break; 1772 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break; 1773 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break; 1774 default: ShouldNotReachHere(); 1775 } 1776 1777 } else if (right->is_double_cpu()) { 1778 Register rreg = right->as_register_lo(); 1779 // single_cpu + double_cpu: can happen with obj+long 1780 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op"); 1781 switch (code) { 1782 case lir_add: __ add(dreg, lreg, rreg); break; 1783 case lir_sub: __ sub(dreg, lreg, rreg); break; 1784 default: ShouldNotReachHere(); 1785 } 1786 } else if (right->is_constant()) { 1787 // cpu register - constant 1788 jlong c; 1789 1790 // FIXME. This is fugly: we really need to factor all this logic. 1791 switch(right->type()) { 1792 case T_LONG: 1793 c = right->as_constant_ptr()->as_jlong(); 1794 break; 1795 case T_INT: 1796 case T_ADDRESS: 1797 c = right->as_constant_ptr()->as_jint(); 1798 break; 1799 default: 1800 ShouldNotReachHere(); 1801 c = 0; // unreachable 1802 break; 1803 } 1804 1805 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op"); 1806 if (c == 0 && dreg == lreg) { 1807 COMMENT("effective nop elided"); 1808 return; 1809 } 1810 switch(left->type()) { 1811 case T_INT: 1812 switch (code) { 1813 case lir_add: __ addw(dreg, lreg, c); break; 1814 case lir_sub: __ subw(dreg, lreg, c); break; 1815 default: ShouldNotReachHere(); 1816 } 1817 break; 1818 case T_OBJECT: 1819 case T_ADDRESS: 1820 switch (code) { 1821 case lir_add: __ add(dreg, lreg, c); break; 1822 case lir_sub: __ sub(dreg, lreg, c); break; 1823 default: ShouldNotReachHere(); 1824 } 1825 break; 1826 default: 1827 ShouldNotReachHere(); 1828 } 1829 } else { 1830 ShouldNotReachHere(); 1831 } 1832 1833 } else if (left->is_double_cpu()) { 1834 Register lreg_lo = left->as_register_lo(); 1835 1836 if (right->is_double_cpu()) { 1837 // cpu register - cpu register 1838 Register rreg_lo = right->as_register_lo(); 1839 switch (code) { 1840 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break; 1841 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break; 1842 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break; 1843 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break; 1844 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break; 1845 default: 1846 ShouldNotReachHere(); 1847 } 1848 1849 } else if (right->is_constant()) { 1850 jlong c = right->as_constant_ptr()->as_jlong(); 1851 Register dreg = as_reg(dest); 1852 switch (code) { 1853 case lir_add: 1854 case lir_sub: 1855 if (c == 0 && dreg == lreg_lo) { 1856 COMMENT("effective nop elided"); 1857 return; 1858 } 1859 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c); 1860 break; 1861 case lir_div: 1862 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant"); 1863 if (c == 1) { 1864 // move lreg_lo to dreg if divisor is 1 1865 __ mov(dreg, lreg_lo); 1866 } else { 1867 unsigned int shift = log2i_exact(c); 1868 // use rscratch1 as intermediate result register 1869 __ asr(rscratch1, lreg_lo, 63); 1870 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift); 1871 __ asr(dreg, rscratch1, shift); 1872 } 1873 break; 1874 case lir_rem: 1875 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant"); 1876 if (c == 1) { 1877 // move 0 to dreg if divisor is 1 1878 __ mov(dreg, zr); 1879 } else { 1880 // use rscratch1 as intermediate result register 1881 __ negs(rscratch1, lreg_lo); 1882 __ andr(dreg, lreg_lo, c - 1); 1883 __ andr(rscratch1, rscratch1, c - 1); 1884 __ csneg(dreg, dreg, rscratch1, Assembler::MI); 1885 } 1886 break; 1887 default: 1888 ShouldNotReachHere(); 1889 } 1890 } else { 1891 ShouldNotReachHere(); 1892 } 1893 } else if (left->is_single_fpu()) { 1894 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register"); 1895 switch (code) { 1896 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1897 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1898 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1899 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1900 default: 1901 ShouldNotReachHere(); 1902 } 1903 } else if (left->is_double_fpu()) { 1904 if (right->is_double_fpu()) { 1905 // fpu register - fpu register 1906 switch (code) { 1907 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1908 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1909 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1910 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1911 default: 1912 ShouldNotReachHere(); 1913 } 1914 } else { 1915 if (right->is_constant()) { 1916 ShouldNotReachHere(); 1917 } 1918 ShouldNotReachHere(); 1919 } 1920 } else if (left->is_single_stack() || left->is_address()) { 1921 assert(left == dest, "left and dest must be equal"); 1922 ShouldNotReachHere(); 1923 } else { 1924 ShouldNotReachHere(); 1925 } 1926 } 1927 1928 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); } 1929 1930 1931 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) { 1932 switch(code) { 1933 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break; 1934 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break; 1935 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break; 1936 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break; 1937 default : ShouldNotReachHere(); 1938 } 1939 } 1940 1941 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 1942 1943 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register"); 1944 Register Rleft = left->is_single_cpu() ? left->as_register() : 1945 left->as_register_lo(); 1946 if (dst->is_single_cpu()) { 1947 Register Rdst = dst->as_register(); 1948 if (right->is_constant()) { 1949 switch (code) { 1950 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break; 1951 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break; 1952 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break; 1953 default: ShouldNotReachHere(); break; 1954 } 1955 } else { 1956 Register Rright = right->is_single_cpu() ? right->as_register() : 1957 right->as_register_lo(); 1958 switch (code) { 1959 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break; 1960 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break; 1961 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break; 1962 default: ShouldNotReachHere(); break; 1963 } 1964 } 1965 } else { 1966 Register Rdst = dst->as_register_lo(); 1967 if (right->is_constant()) { 1968 switch (code) { 1969 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break; 1970 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break; 1971 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break; 1972 default: ShouldNotReachHere(); break; 1973 } 1974 } else { 1975 Register Rright = right->is_single_cpu() ? right->as_register() : 1976 right->as_register_lo(); 1977 switch (code) { 1978 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break; 1979 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break; 1980 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break; 1981 default: ShouldNotReachHere(); break; 1982 } 1983 } 1984 } 1985 } 1986 1987 1988 1989 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) { 1990 1991 // opcode check 1992 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem"); 1993 bool is_irem = (code == lir_irem); 1994 1995 // operand check 1996 assert(left->is_single_cpu(), "left must be register"); 1997 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 1998 assert(result->is_single_cpu(), "result must be register"); 1999 Register lreg = left->as_register(); 2000 Register dreg = result->as_register(); 2001 2002 // power-of-2 constant check and codegen 2003 if (right->is_constant()) { 2004 int c = right->as_constant_ptr()->as_jint(); 2005 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant"); 2006 if (is_irem) { 2007 if (c == 1) { 2008 // move 0 to dreg if divisor is 1 2009 __ movw(dreg, zr); 2010 } else { 2011 // use rscratch1 as intermediate result register 2012 __ negsw(rscratch1, lreg); 2013 __ andw(dreg, lreg, c - 1); 2014 __ andw(rscratch1, rscratch1, c - 1); 2015 __ csnegw(dreg, dreg, rscratch1, Assembler::MI); 2016 } 2017 } else { 2018 if (c == 1) { 2019 // move lreg to dreg if divisor is 1 2020 __ movw(dreg, lreg); 2021 } else { 2022 unsigned int shift = exact_log2(c); 2023 // use rscratch1 as intermediate result register 2024 __ asrw(rscratch1, lreg, 31); 2025 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift); 2026 __ asrw(dreg, rscratch1, shift); 2027 } 2028 } 2029 } else { 2030 Register rreg = right->as_register(); 2031 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1); 2032 } 2033 } 2034 2035 2036 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2037 if (opr1->is_constant() && opr2->is_single_cpu()) { 2038 // tableswitch 2039 Register reg = as_reg(opr2); 2040 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()]; 2041 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after); 2042 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) { 2043 Register reg1 = as_reg(opr1); 2044 if (opr2->is_single_cpu()) { 2045 // cpu register - cpu register 2046 Register reg2 = opr2->as_register(); 2047 if (is_reference_type(opr1->type())) { 2048 __ cmpoop(reg1, reg2); 2049 } else { 2050 assert(!is_reference_type(opr2->type()), "cmp int, oop?"); 2051 __ cmpw(reg1, reg2); 2052 } 2053 return; 2054 } 2055 if (opr2->is_double_cpu()) { 2056 // cpu register - cpu register 2057 Register reg2 = opr2->as_register_lo(); 2058 __ cmp(reg1, reg2); 2059 return; 2060 } 2061 2062 if (opr2->is_constant()) { 2063 bool is_32bit = false; // width of register operand 2064 jlong imm; 2065 2066 switch(opr2->type()) { 2067 case T_INT: 2068 imm = opr2->as_constant_ptr()->as_jint(); 2069 is_32bit = true; 2070 break; 2071 case T_LONG: 2072 imm = opr2->as_constant_ptr()->as_jlong(); 2073 break; 2074 case T_ADDRESS: 2075 imm = opr2->as_constant_ptr()->as_jint(); 2076 break; 2077 case T_METADATA: 2078 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata()); 2079 break; 2080 case T_OBJECT: 2081 case T_ARRAY: 2082 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1); 2083 __ cmpoop(reg1, rscratch1); 2084 return; 2085 default: 2086 ShouldNotReachHere(); 2087 imm = 0; // unreachable 2088 break; 2089 } 2090 2091 if (Assembler::operand_valid_for_add_sub_immediate(imm)) { 2092 if (is_32bit) 2093 __ cmpw(reg1, imm); 2094 else 2095 __ subs(zr, reg1, imm); 2096 return; 2097 } else { 2098 __ mov(rscratch1, imm); 2099 if (is_32bit) 2100 __ cmpw(reg1, rscratch1); 2101 else 2102 __ cmp(reg1, rscratch1); 2103 return; 2104 } 2105 } else 2106 ShouldNotReachHere(); 2107 } else if (opr1->is_single_fpu()) { 2108 FloatRegister reg1 = opr1->as_float_reg(); 2109 assert(opr2->is_single_fpu(), "expect single float register"); 2110 FloatRegister reg2 = opr2->as_float_reg(); 2111 __ fcmps(reg1, reg2); 2112 } else if (opr1->is_double_fpu()) { 2113 FloatRegister reg1 = opr1->as_double_reg(); 2114 assert(opr2->is_double_fpu(), "expect double float register"); 2115 FloatRegister reg2 = opr2->as_double_reg(); 2116 __ fcmpd(reg1, reg2); 2117 } else { 2118 ShouldNotReachHere(); 2119 } 2120 } 2121 2122 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ 2123 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2124 bool is_unordered_less = (code == lir_ucmp_fd2i); 2125 if (left->is_single_fpu()) { 2126 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); 2127 } else if (left->is_double_fpu()) { 2128 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); 2129 } else { 2130 ShouldNotReachHere(); 2131 } 2132 } else if (code == lir_cmp_l2i) { 2133 Label done; 2134 __ cmp(left->as_register_lo(), right->as_register_lo()); 2135 __ mov(dst->as_register(), (uint64_t)-1L); 2136 __ br(Assembler::LT, done); 2137 __ csinc(dst->as_register(), zr, zr, Assembler::EQ); 2138 __ bind(done); 2139 } else { 2140 ShouldNotReachHere(); 2141 } 2142 } 2143 2144 2145 void LIR_Assembler::align_call(LIR_Code code) { } 2146 2147 2148 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2149 address call = __ trampoline_call(Address(op->addr(), rtype)); 2150 if (call == nullptr) { 2151 bailout("trampoline stub overflow"); 2152 return; 2153 } 2154 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields()); 2155 __ post_call_nop(); 2156 } 2157 2158 2159 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2160 address call = __ ic_call(op->addr()); 2161 if (call == nullptr) { 2162 bailout("trampoline stub overflow"); 2163 return; 2164 } 2165 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields()); 2166 __ post_call_nop(); 2167 } 2168 2169 void LIR_Assembler::emit_static_call_stub() { 2170 address call_pc = __ pc(); 2171 address stub = __ start_a_stub(call_stub_size()); 2172 if (stub == nullptr) { 2173 bailout("static call stub overflow"); 2174 return; 2175 } 2176 2177 int start = __ offset(); 2178 2179 __ relocate(static_stub_Relocation::spec(call_pc)); 2180 __ emit_static_call_stub(); 2181 2182 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size() 2183 <= call_stub_size(), "stub too big"); 2184 __ end_a_stub(); 2185 } 2186 2187 2188 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2189 assert(exceptionOop->as_register() == r0, "must match"); 2190 assert(exceptionPC->as_register() == r3, "must match"); 2191 2192 // exception object is not added to oop map by LinearScan 2193 // (LinearScan assumes that no oops are in fixed registers) 2194 info->add_register_oop(exceptionOop); 2195 Runtime1::StubID unwind_id; 2196 2197 // get current pc information 2198 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2199 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) { 2200 // As no instructions have been generated yet for this LIR node it's 2201 // possible that an oop map already exists for the current offset. 2202 // In that case insert an dummy NOP here to ensure all oop map PCs 2203 // are unique. See JDK-8237483. 2204 __ nop(); 2205 } 2206 int pc_for_athrow_offset = __ offset(); 2207 InternalAddress pc_for_athrow(__ pc()); 2208 __ adr(exceptionPC->as_register(), pc_for_athrow); 2209 add_call_info(pc_for_athrow_offset, info); // for exception handler 2210 2211 __ verify_not_null_oop(r0); 2212 // search an exception handler (r0: exception oop, r3: throwing pc) 2213 if (compilation()->has_fpu_code()) { 2214 unwind_id = Runtime1::handle_exception_id; 2215 } else { 2216 unwind_id = Runtime1::handle_exception_nofpu_id; 2217 } 2218 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2219 2220 // FIXME: enough room for two byte trap ???? 2221 __ nop(); 2222 } 2223 2224 2225 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2226 assert(exceptionOop->as_register() == r0, "must match"); 2227 2228 __ b(_unwind_handler_entry); 2229 } 2230 2231 2232 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2233 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo(); 2234 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo(); 2235 2236 switch (left->type()) { 2237 case T_INT: { 2238 switch (code) { 2239 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break; 2240 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break; 2241 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break; 2242 default: 2243 ShouldNotReachHere(); 2244 break; 2245 } 2246 break; 2247 case T_LONG: 2248 case T_ADDRESS: 2249 case T_OBJECT: 2250 switch (code) { 2251 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break; 2252 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break; 2253 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break; 2254 default: 2255 ShouldNotReachHere(); 2256 break; 2257 } 2258 break; 2259 default: 2260 ShouldNotReachHere(); 2261 break; 2262 } 2263 } 2264 } 2265 2266 2267 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2268 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo(); 2269 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo(); 2270 2271 switch (left->type()) { 2272 case T_INT: { 2273 switch (code) { 2274 case lir_shl: __ lslw (dreg, lreg, count); break; 2275 case lir_shr: __ asrw (dreg, lreg, count); break; 2276 case lir_ushr: __ lsrw (dreg, lreg, count); break; 2277 default: 2278 ShouldNotReachHere(); 2279 break; 2280 } 2281 break; 2282 case T_LONG: 2283 case T_ADDRESS: 2284 case T_OBJECT: 2285 switch (code) { 2286 case lir_shl: __ lsl (dreg, lreg, count); break; 2287 case lir_shr: __ asr (dreg, lreg, count); break; 2288 case lir_ushr: __ lsr (dreg, lreg, count); break; 2289 default: 2290 ShouldNotReachHere(); 2291 break; 2292 } 2293 break; 2294 default: 2295 ShouldNotReachHere(); 2296 break; 2297 } 2298 } 2299 } 2300 2301 2302 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 2303 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2304 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2305 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2306 __ str (r, Address(sp, offset_from_rsp_in_bytes)); 2307 } 2308 2309 2310 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 2311 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2312 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2313 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2314 __ mov (rscratch1, c); 2315 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes)); 2316 } 2317 2318 2319 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 2320 ShouldNotReachHere(); 2321 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2322 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2323 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2324 __ lea(rscratch1, __ constant_oop_address(o)); 2325 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes)); 2326 } 2327 2328 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) { 2329 if (null_check) { 2330 __ cbz(obj, *slow_path->entry()); 2331 } 2332 if (is_dest) { 2333 __ test_null_free_array_oop(obj, tmp, *slow_path->entry()); 2334 } else { 2335 __ test_flat_array_oop(obj, tmp, *slow_path->entry()); 2336 } 2337 } 2338 2339 // This code replaces a call to arraycopy; no exception may 2340 // be thrown in this code, they must be thrown in the System.arraycopy 2341 // activation frame; we could save some checks if this would not be the case 2342 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 2343 ciArrayKlass* default_type = op->expected_type(); 2344 Register src = op->src()->as_register(); 2345 Register dst = op->dst()->as_register(); 2346 Register src_pos = op->src_pos()->as_register(); 2347 Register dst_pos = op->dst_pos()->as_register(); 2348 Register length = op->length()->as_register(); 2349 Register tmp = op->tmp()->as_register(); 2350 2351 CodeStub* stub = op->stub(); 2352 int flags = op->flags(); 2353 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL; 2354 if (is_reference_type(basic_type)) basic_type = T_OBJECT; 2355 2356 if (flags & LIR_OpArrayCopy::always_slow_path) { 2357 __ b(*stub->entry()); 2358 __ bind(*stub->continuation()); 2359 return; 2360 } 2361 2362 // if we don't know anything, just go through the generic arraycopy 2363 if (default_type == nullptr // || basic_type == T_OBJECT 2364 ) { 2365 Label done; 2366 assert(src == r1 && src_pos == r2, "mismatch in calling convention"); 2367 2368 // Save the arguments in case the generic arraycopy fails and we 2369 // have to fall back to the JNI stub 2370 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2371 __ stp(length, src_pos, Address(sp, 2*BytesPerWord)); 2372 __ str(src, Address(sp, 4*BytesPerWord)); 2373 2374 address copyfunc_addr = StubRoutines::generic_arraycopy(); 2375 assert(copyfunc_addr != nullptr, "generic arraycopy stub required"); 2376 2377 // The arguments are in java calling convention so we shift them 2378 // to C convention 2379 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 2380 __ mov(c_rarg0, j_rarg0); 2381 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 2382 __ mov(c_rarg1, j_rarg1); 2383 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 2384 __ mov(c_rarg2, j_rarg2); 2385 assert_different_registers(c_rarg3, j_rarg4); 2386 __ mov(c_rarg3, j_rarg3); 2387 __ mov(c_rarg4, j_rarg4); 2388 #ifndef PRODUCT 2389 if (PrintC1Statistics) { 2390 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 2391 } 2392 #endif 2393 __ far_call(RuntimeAddress(copyfunc_addr)); 2394 2395 __ cbz(r0, *stub->continuation()); 2396 2397 // Reload values from the stack so they are where the stub 2398 // expects them. 2399 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2400 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord)); 2401 __ ldr(src, Address(sp, 4*BytesPerWord)); 2402 2403 // r0 is -1^K where K == partial copied count 2404 __ eonw(rscratch1, r0, zr); 2405 // adjust length down and src/end pos up by partial copied count 2406 __ subw(length, length, rscratch1); 2407 __ addw(src_pos, src_pos, rscratch1); 2408 __ addw(dst_pos, dst_pos, rscratch1); 2409 __ b(*stub->entry()); 2410 2411 __ bind(*stub->continuation()); 2412 return; 2413 } 2414 2415 // Handle inline type arrays 2416 if (flags & LIR_OpArrayCopy::src_inlinetype_check) { 2417 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check)); 2418 } 2419 2420 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) { 2421 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check)); 2422 } 2423 2424 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 2425 2426 int elem_size = type2aelembytes(basic_type); 2427 int scale = exact_log2(elem_size); 2428 2429 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 2430 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 2431 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 2432 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 2433 2434 // test for null 2435 if (flags & LIR_OpArrayCopy::src_null_check) { 2436 __ cbz(src, *stub->entry()); 2437 } 2438 if (flags & LIR_OpArrayCopy::dst_null_check) { 2439 __ cbz(dst, *stub->entry()); 2440 } 2441 2442 // If the compiler was not able to prove that exact type of the source or the destination 2443 // of the arraycopy is an array type, check at runtime if the source or the destination is 2444 // an instance type. 2445 if (flags & LIR_OpArrayCopy::type_check) { 2446 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) { 2447 __ load_klass(tmp, dst); 2448 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset()))); 2449 __ cmpw(rscratch1, Klass::_lh_neutral_value); 2450 __ br(Assembler::GE, *stub->entry()); 2451 } 2452 2453 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) { 2454 __ load_klass(tmp, src); 2455 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset()))); 2456 __ cmpw(rscratch1, Klass::_lh_neutral_value); 2457 __ br(Assembler::GE, *stub->entry()); 2458 } 2459 } 2460 2461 // check if negative 2462 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 2463 __ cmpw(src_pos, 0); 2464 __ br(Assembler::LT, *stub->entry()); 2465 } 2466 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 2467 __ cmpw(dst_pos, 0); 2468 __ br(Assembler::LT, *stub->entry()); 2469 } 2470 2471 if (flags & LIR_OpArrayCopy::length_positive_check) { 2472 __ cmpw(length, 0); 2473 __ br(Assembler::LT, *stub->entry()); 2474 } 2475 2476 if (flags & LIR_OpArrayCopy::src_range_check) { 2477 __ addw(tmp, src_pos, length); 2478 __ ldrw(rscratch1, src_length_addr); 2479 __ cmpw(tmp, rscratch1); 2480 __ br(Assembler::HI, *stub->entry()); 2481 } 2482 if (flags & LIR_OpArrayCopy::dst_range_check) { 2483 __ addw(tmp, dst_pos, length); 2484 __ ldrw(rscratch1, dst_length_addr); 2485 __ cmpw(tmp, rscratch1); 2486 __ br(Assembler::HI, *stub->entry()); 2487 } 2488 2489 if (flags & LIR_OpArrayCopy::type_check) { 2490 // We don't know the array types are compatible 2491 if (basic_type != T_OBJECT) { 2492 // Simple test for basic type arrays 2493 if (UseCompressedClassPointers) { 2494 __ ldrw(tmp, src_klass_addr); 2495 __ ldrw(rscratch1, dst_klass_addr); 2496 __ cmpw(tmp, rscratch1); 2497 } else { 2498 __ ldr(tmp, src_klass_addr); 2499 __ ldr(rscratch1, dst_klass_addr); 2500 __ cmp(tmp, rscratch1); 2501 } 2502 __ br(Assembler::NE, *stub->entry()); 2503 } else { 2504 // For object arrays, if src is a sub class of dst then we can 2505 // safely do the copy. 2506 Label cont, slow; 2507 2508 #define PUSH(r1, r2) \ 2509 stp(r1, r2, __ pre(sp, -2 * wordSize)); 2510 2511 #define POP(r1, r2) \ 2512 ldp(r1, r2, __ post(sp, 2 * wordSize)); 2513 2514 __ PUSH(src, dst); 2515 2516 __ load_klass(src, src); 2517 __ load_klass(dst, dst); 2518 2519 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr); 2520 2521 __ PUSH(src, dst); 2522 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 2523 __ POP(src, dst); 2524 2525 __ cbnz(src, cont); 2526 2527 __ bind(slow); 2528 __ POP(src, dst); 2529 2530 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 2531 if (copyfunc_addr != nullptr) { // use stub if available 2532 // src is not a sub class of dst so we have to do a 2533 // per-element check. 2534 2535 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 2536 if ((flags & mask) != mask) { 2537 // Check that at least both of them object arrays. 2538 assert(flags & mask, "one of the two should be known to be an object array"); 2539 2540 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2541 __ load_klass(tmp, src); 2542 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2543 __ load_klass(tmp, dst); 2544 } 2545 int lh_offset = in_bytes(Klass::layout_helper_offset()); 2546 Address klass_lh_addr(tmp, lh_offset); 2547 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 2548 __ ldrw(rscratch1, klass_lh_addr); 2549 __ mov(rscratch2, objArray_lh); 2550 __ eorw(rscratch1, rscratch1, rscratch2); 2551 __ cbnzw(rscratch1, *stub->entry()); 2552 } 2553 2554 // Spill because stubs can use any register they like and it's 2555 // easier to restore just those that we care about. 2556 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2557 __ stp(length, src_pos, Address(sp, 2*BytesPerWord)); 2558 __ str(src, Address(sp, 4*BytesPerWord)); 2559 2560 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale))); 2561 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type)); 2562 assert_different_registers(c_rarg0, dst, dst_pos, length); 2563 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale))); 2564 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type)); 2565 assert_different_registers(c_rarg1, dst, length); 2566 __ uxtw(c_rarg2, length); 2567 assert_different_registers(c_rarg2, dst); 2568 2569 __ load_klass(c_rarg4, dst); 2570 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 2571 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 2572 __ far_call(RuntimeAddress(copyfunc_addr)); 2573 2574 #ifndef PRODUCT 2575 if (PrintC1Statistics) { 2576 Label failed; 2577 __ cbnz(r0, failed); 2578 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 2579 __ bind(failed); 2580 } 2581 #endif 2582 2583 __ cbz(r0, *stub->continuation()); 2584 2585 #ifndef PRODUCT 2586 if (PrintC1Statistics) { 2587 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 2588 } 2589 #endif 2590 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1); 2591 2592 // Restore previously spilled arguments 2593 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2594 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord)); 2595 __ ldr(src, Address(sp, 4*BytesPerWord)); 2596 2597 // return value is -1^K where K is partial copied count 2598 __ eonw(rscratch1, r0, zr); 2599 // adjust length down and src/end pos up by partial copied count 2600 __ subw(length, length, rscratch1); 2601 __ addw(src_pos, src_pos, rscratch1); 2602 __ addw(dst_pos, dst_pos, rscratch1); 2603 } 2604 2605 __ b(*stub->entry()); 2606 2607 __ bind(cont); 2608 __ POP(src, dst); 2609 } 2610 } 2611 2612 #ifdef ASSERT 2613 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2614 // Sanity check the known type with the incoming class. For the 2615 // primitive case the types must match exactly with src.klass and 2616 // dst.klass each exactly matching the default type. For the 2617 // object array case, if no type check is needed then either the 2618 // dst type is exactly the expected type and the src type is a 2619 // subtype which we can't check or src is the same array as dst 2620 // but not necessarily exactly of type default_type. 2621 Label known_ok, halt; 2622 __ mov_metadata(tmp, default_type->constant_encoding()); 2623 if (UseCompressedClassPointers) { 2624 __ encode_klass_not_null(tmp); 2625 } 2626 2627 if (basic_type != T_OBJECT) { 2628 2629 if (UseCompressedClassPointers) { 2630 __ ldrw(rscratch1, dst_klass_addr); 2631 __ cmpw(tmp, rscratch1); 2632 } else { 2633 __ ldr(rscratch1, dst_klass_addr); 2634 __ cmp(tmp, rscratch1); 2635 } 2636 __ br(Assembler::NE, halt); 2637 if (UseCompressedClassPointers) { 2638 __ ldrw(rscratch1, src_klass_addr); 2639 __ cmpw(tmp, rscratch1); 2640 } else { 2641 __ ldr(rscratch1, src_klass_addr); 2642 __ cmp(tmp, rscratch1); 2643 } 2644 __ br(Assembler::EQ, known_ok); 2645 } else { 2646 if (UseCompressedClassPointers) { 2647 __ ldrw(rscratch1, dst_klass_addr); 2648 __ cmpw(tmp, rscratch1); 2649 } else { 2650 __ ldr(rscratch1, dst_klass_addr); 2651 __ cmp(tmp, rscratch1); 2652 } 2653 __ br(Assembler::EQ, known_ok); 2654 __ cmp(src, dst); 2655 __ br(Assembler::EQ, known_ok); 2656 } 2657 __ bind(halt); 2658 __ stop("incorrect type information in arraycopy"); 2659 __ bind(known_ok); 2660 } 2661 #endif 2662 2663 #ifndef PRODUCT 2664 if (PrintC1Statistics) { 2665 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 2666 } 2667 #endif 2668 2669 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale))); 2670 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type)); 2671 assert_different_registers(c_rarg0, dst, dst_pos, length); 2672 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale))); 2673 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type)); 2674 assert_different_registers(c_rarg1, dst, length); 2675 __ uxtw(c_rarg2, length); 2676 assert_different_registers(c_rarg2, dst); 2677 2678 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 2679 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 2680 const char *name; 2681 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 2682 2683 CodeBlob *cb = CodeCache::find_blob(entry); 2684 if (cb) { 2685 __ far_call(RuntimeAddress(entry)); 2686 } else { 2687 __ call_VM_leaf(entry, 3); 2688 } 2689 2690 __ bind(*stub->continuation()); 2691 } 2692 2693 2694 2695 2696 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2697 Register obj = op->obj_opr()->as_register(); // may not be an oop 2698 Register hdr = op->hdr_opr()->as_register(); 2699 Register lock = op->lock_opr()->as_register(); 2700 Register temp = op->scratch_opr()->as_register(); 2701 if (LockingMode == LM_MONITOR) { 2702 if (op->info() != nullptr) { 2703 add_debug_info_for_null_check_here(op->info()); 2704 __ null_check(obj, -1); 2705 } 2706 __ b(*op->stub()->entry()); 2707 } else if (op->code() == lir_lock) { 2708 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2709 // add debug info for NullPointerException only if one is possible 2710 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry()); 2711 if (op->info() != nullptr) { 2712 add_debug_info_for_null_check(null_check_offset, op->info()); 2713 } 2714 // done 2715 } else if (op->code() == lir_unlock) { 2716 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2717 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry()); 2718 } else { 2719 Unimplemented(); 2720 } 2721 __ bind(*op->stub()->continuation()); 2722 } 2723 2724 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) { 2725 Register obj = op->obj()->as_pointer_register(); 2726 Register result = op->result_opr()->as_pointer_register(); 2727 2728 CodeEmitInfo* info = op->info(); 2729 if (info != nullptr) { 2730 add_debug_info_for_null_check_here(info); 2731 } 2732 2733 if (UseCompressedClassPointers) { 2734 __ ldrw(result, Address (obj, oopDesc::klass_offset_in_bytes())); 2735 __ decode_klass_not_null(result); 2736 } else { 2737 __ ldr(result, Address (obj, oopDesc::klass_offset_in_bytes())); 2738 } 2739 } 2740 2741 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2742 ciMethod* method = op->profiled_method(); 2743 int bci = op->profiled_bci(); 2744 ciMethod* callee = op->profiled_callee(); 2745 2746 // Update counter for all call types 2747 ciMethodData* md = method->method_data_or_null(); 2748 assert(md != nullptr, "Sanity"); 2749 ciProfileData* data = md->bci_to_data(bci); 2750 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls"); 2751 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2752 Register mdo = op->mdo()->as_register(); 2753 __ mov_metadata(mdo, md->constant_encoding()); 2754 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 2755 // Perform additional virtual call profiling for invokevirtual and 2756 // invokeinterface bytecodes 2757 if (op->should_profile_receiver_type()) { 2758 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 2759 Register recv = op->recv()->as_register(); 2760 assert_different_registers(mdo, recv); 2761 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 2762 ciKlass* known_klass = op->known_holder(); 2763 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) { 2764 // We know the type that will be seen at this call site; we can 2765 // statically update the MethodData* rather than needing to do 2766 // dynamic tests on the receiver type 2767 2768 // NOTE: we should probably put a lock around this search to 2769 // avoid collisions by concurrent compilations 2770 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 2771 uint i; 2772 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2773 ciKlass* receiver = vc_data->receiver(i); 2774 if (known_klass->equals(receiver)) { 2775 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 2776 __ addptr(data_addr, DataLayout::counter_increment); 2777 return; 2778 } 2779 } 2780 2781 // Receiver type not found in profile data; select an empty slot 2782 2783 // Note that this is less efficient than it should be because it 2784 // always does a write to the receiver part of the 2785 // VirtualCallData rather than just the first time 2786 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2787 ciKlass* receiver = vc_data->receiver(i); 2788 if (receiver == nullptr) { 2789 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 2790 __ mov_metadata(rscratch1, known_klass->constant_encoding()); 2791 __ lea(rscratch2, recv_addr); 2792 __ str(rscratch1, Address(rscratch2)); 2793 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 2794 __ addptr(data_addr, DataLayout::counter_increment); 2795 return; 2796 } 2797 } 2798 } else { 2799 __ load_klass(recv, recv); 2800 Label update_done; 2801 type_profile_helper(mdo, md, data, recv, &update_done); 2802 // Receiver did not match any saved receiver and there is no empty row for it. 2803 // Increment total counter to indicate polymorphic case. 2804 __ addptr(counter_addr, DataLayout::counter_increment); 2805 2806 __ bind(update_done); 2807 } 2808 } else { 2809 // Static call 2810 __ addptr(counter_addr, DataLayout::counter_increment); 2811 } 2812 } 2813 2814 2815 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 2816 Unimplemented(); 2817 } 2818 2819 2820 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 2821 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 2822 } 2823 2824 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 2825 assert(op->crc()->is_single_cpu(), "crc must be register"); 2826 assert(op->val()->is_single_cpu(), "byte value must be register"); 2827 assert(op->result_opr()->is_single_cpu(), "result must be register"); 2828 Register crc = op->crc()->as_register(); 2829 Register val = op->val()->as_register(); 2830 Register res = op->result_opr()->as_register(); 2831 2832 assert_different_registers(val, crc, res); 2833 uint64_t offset; 2834 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset); 2835 __ add(res, res, offset); 2836 2837 __ mvnw(crc, crc); // ~crc 2838 __ update_byte_crc32(crc, val, res); 2839 __ mvnw(res, crc); // ~crc 2840 } 2841 2842 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 2843 COMMENT("emit_profile_type {"); 2844 Register obj = op->obj()->as_register(); 2845 Register tmp = op->tmp()->as_pointer_register(); 2846 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 2847 ciKlass* exact_klass = op->exact_klass(); 2848 intptr_t current_klass = op->current_klass(); 2849 bool not_null = op->not_null(); 2850 bool no_conflict = op->no_conflict(); 2851 2852 Label update, next, none; 2853 2854 bool do_null = !not_null; 2855 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 2856 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 2857 2858 assert(do_null || do_update, "why are we here?"); 2859 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 2860 assert(mdo_addr.base() != rscratch1, "wrong register"); 2861 2862 __ verify_oop(obj); 2863 2864 if (tmp != obj) { 2865 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index()); 2866 __ mov(tmp, obj); 2867 } else { 2868 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index()); 2869 } 2870 if (do_null) { 2871 __ cbnz(tmp, update); 2872 if (!TypeEntries::was_null_seen(current_klass)) { 2873 __ ldr(rscratch2, mdo_addr); 2874 __ orr(rscratch2, rscratch2, TypeEntries::null_seen); 2875 __ str(rscratch2, mdo_addr); 2876 } 2877 if (do_update) { 2878 #ifndef ASSERT 2879 __ b(next); 2880 } 2881 #else 2882 __ b(next); 2883 } 2884 } else { 2885 __ cbnz(tmp, update); 2886 __ stop("unexpected null obj"); 2887 #endif 2888 } 2889 2890 __ bind(update); 2891 2892 if (do_update) { 2893 #ifdef ASSERT 2894 if (exact_klass != nullptr) { 2895 Label ok; 2896 __ load_klass(tmp, tmp); 2897 __ mov_metadata(rscratch1, exact_klass->constant_encoding()); 2898 __ eor(rscratch1, tmp, rscratch1); 2899 __ cbz(rscratch1, ok); 2900 __ stop("exact klass and actual klass differ"); 2901 __ bind(ok); 2902 } 2903 #endif 2904 if (!no_conflict) { 2905 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) { 2906 if (exact_klass != nullptr) { 2907 __ mov_metadata(tmp, exact_klass->constant_encoding()); 2908 } else { 2909 __ load_klass(tmp, tmp); 2910 } 2911 2912 __ ldr(rscratch2, mdo_addr); 2913 __ eor(tmp, tmp, rscratch2); 2914 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask); 2915 // klass seen before, nothing to do. The unknown bit may have been 2916 // set already but no need to check. 2917 __ cbz(rscratch1, next); 2918 2919 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore. 2920 2921 if (TypeEntries::is_type_none(current_klass)) { 2922 __ cbz(rscratch2, none); 2923 __ cmp(rscratch2, (u1)TypeEntries::null_seen); 2924 __ br(Assembler::EQ, none); 2925 // There is a chance that the checks above 2926 // fail if another thread has just set the 2927 // profiling to this obj's klass 2928 __ dmb(Assembler::ISHLD); 2929 __ eor(tmp, tmp, rscratch2); // get back original value before XOR 2930 __ ldr(rscratch2, mdo_addr); 2931 __ eor(tmp, tmp, rscratch2); 2932 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask); 2933 __ cbz(rscratch1, next); 2934 } 2935 } else { 2936 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr && 2937 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 2938 2939 __ ldr(tmp, mdo_addr); 2940 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore. 2941 } 2942 2943 // different than before. Cannot keep accurate profile. 2944 __ ldr(rscratch2, mdo_addr); 2945 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown); 2946 __ str(rscratch2, mdo_addr); 2947 2948 if (TypeEntries::is_type_none(current_klass)) { 2949 __ b(next); 2950 2951 __ bind(none); 2952 // first time here. Set profile type. 2953 __ str(tmp, mdo_addr); 2954 #ifdef ASSERT 2955 __ andr(tmp, tmp, TypeEntries::type_mask); 2956 __ verify_klass_ptr(tmp); 2957 #endif 2958 } 2959 } else { 2960 // There's a single possible klass at this profile point 2961 assert(exact_klass != nullptr, "should be"); 2962 if (TypeEntries::is_type_none(current_klass)) { 2963 __ mov_metadata(tmp, exact_klass->constant_encoding()); 2964 __ ldr(rscratch2, mdo_addr); 2965 __ eor(tmp, tmp, rscratch2); 2966 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask); 2967 __ cbz(rscratch1, next); 2968 #ifdef ASSERT 2969 { 2970 Label ok; 2971 __ ldr(rscratch1, mdo_addr); 2972 __ cbz(rscratch1, ok); 2973 __ cmp(rscratch1, (u1)TypeEntries::null_seen); 2974 __ br(Assembler::EQ, ok); 2975 // may have been set by another thread 2976 __ dmb(Assembler::ISHLD); 2977 __ mov_metadata(rscratch1, exact_klass->constant_encoding()); 2978 __ ldr(rscratch2, mdo_addr); 2979 __ eor(rscratch2, rscratch1, rscratch2); 2980 __ andr(rscratch2, rscratch2, TypeEntries::type_mask); 2981 __ cbz(rscratch2, ok); 2982 2983 __ stop("unexpected profiling mismatch"); 2984 __ bind(ok); 2985 } 2986 #endif 2987 // first time here. Set profile type. 2988 __ str(tmp, mdo_addr); 2989 #ifdef ASSERT 2990 __ andr(tmp, tmp, TypeEntries::type_mask); 2991 __ verify_klass_ptr(tmp); 2992 #endif 2993 } else { 2994 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr && 2995 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 2996 2997 __ ldr(tmp, mdo_addr); 2998 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore. 2999 3000 __ orr(tmp, tmp, TypeEntries::type_unknown); 3001 __ str(tmp, mdo_addr); 3002 // FIXME: Write barrier needed here? 3003 } 3004 } 3005 3006 __ bind(next); 3007 } 3008 COMMENT("} emit_profile_type"); 3009 } 3010 3011 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) { 3012 Register obj = op->obj()->as_register(); 3013 Register tmp = op->tmp()->as_pointer_register(); 3014 bool not_null = op->not_null(); 3015 int flag = op->flag(); 3016 3017 Label not_inline_type; 3018 if (!not_null) { 3019 __ cbz(obj, not_inline_type); 3020 } 3021 3022 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type); 3023 3024 Address mdo_addr = as_Address(op->mdp()->as_address_ptr(), rscratch2); 3025 __ ldrb(rscratch1, mdo_addr); 3026 __ orr(rscratch1, rscratch1, flag); 3027 __ strb(rscratch1, mdo_addr); 3028 3029 __ bind(not_inline_type); 3030 } 3031 3032 void LIR_Assembler::align_backward_branch_target() { 3033 } 3034 3035 3036 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) { 3037 // tmp must be unused 3038 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 3039 3040 if (left->is_single_cpu()) { 3041 assert(dest->is_single_cpu(), "expect single result reg"); 3042 __ negw(dest->as_register(), left->as_register()); 3043 } else if (left->is_double_cpu()) { 3044 assert(dest->is_double_cpu(), "expect double result reg"); 3045 __ neg(dest->as_register_lo(), left->as_register_lo()); 3046 } else if (left->is_single_fpu()) { 3047 assert(dest->is_single_fpu(), "expect single float result reg"); 3048 __ fnegs(dest->as_float_reg(), left->as_float_reg()); 3049 } else { 3050 assert(left->is_double_fpu(), "expect double float operand reg"); 3051 assert(dest->is_double_fpu(), "expect double float result reg"); 3052 __ fnegd(dest->as_double_reg(), left->as_double_reg()); 3053 } 3054 } 3055 3056 3057 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 3058 if (patch_code != lir_patch_none) { 3059 deoptimize_trap(info); 3060 return; 3061 } 3062 3063 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr())); 3064 } 3065 3066 3067 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3068 assert(!tmp->is_valid(), "don't need temporary"); 3069 3070 CodeBlob *cb = CodeCache::find_blob(dest); 3071 if (cb) { 3072 __ far_call(RuntimeAddress(dest)); 3073 } else { 3074 __ mov(rscratch1, RuntimeAddress(dest)); 3075 __ blr(rscratch1); 3076 } 3077 3078 if (info != nullptr) { 3079 add_call_info_here(info); 3080 } 3081 __ post_call_nop(); 3082 } 3083 3084 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3085 if (dest->is_address() || src->is_address()) { 3086 move_op(src, dest, type, lir_patch_none, info, 3087 /*pop_fpu_stack*/false, /*wide*/false); 3088 } else { 3089 ShouldNotReachHere(); 3090 } 3091 } 3092 3093 #ifdef ASSERT 3094 // emit run-time assertion 3095 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3096 assert(op->code() == lir_assert, "must be"); 3097 3098 if (op->in_opr1()->is_valid()) { 3099 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3100 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3101 } else { 3102 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3103 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3104 } 3105 3106 Label ok; 3107 if (op->condition() != lir_cond_always) { 3108 Assembler::Condition acond = Assembler::AL; 3109 switch (op->condition()) { 3110 case lir_cond_equal: acond = Assembler::EQ; break; 3111 case lir_cond_notEqual: acond = Assembler::NE; break; 3112 case lir_cond_less: acond = Assembler::LT; break; 3113 case lir_cond_lessEqual: acond = Assembler::LE; break; 3114 case lir_cond_greaterEqual: acond = Assembler::GE; break; 3115 case lir_cond_greater: acond = Assembler::GT; break; 3116 case lir_cond_belowEqual: acond = Assembler::LS; break; 3117 case lir_cond_aboveEqual: acond = Assembler::HS; break; 3118 default: ShouldNotReachHere(); 3119 } 3120 __ br(acond, ok); 3121 } 3122 if (op->halt()) { 3123 const char* str = __ code_string(op->msg()); 3124 __ stop(str); 3125 } else { 3126 breakpoint(); 3127 } 3128 __ bind(ok); 3129 } 3130 #endif 3131 3132 #ifndef PRODUCT 3133 #define COMMENT(x) do { __ block_comment(x); } while (0) 3134 #else 3135 #define COMMENT(x) 3136 #endif 3137 3138 void LIR_Assembler::membar() { 3139 COMMENT("membar"); 3140 __ membar(MacroAssembler::AnyAny); 3141 } 3142 3143 void LIR_Assembler::membar_acquire() { 3144 __ membar(Assembler::LoadLoad|Assembler::LoadStore); 3145 } 3146 3147 void LIR_Assembler::membar_release() { 3148 __ membar(Assembler::LoadStore|Assembler::StoreStore); 3149 } 3150 3151 void LIR_Assembler::membar_loadload() { 3152 __ membar(Assembler::LoadLoad); 3153 } 3154 3155 void LIR_Assembler::membar_storestore() { 3156 __ membar(MacroAssembler::StoreStore); 3157 } 3158 3159 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); } 3160 3161 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); } 3162 3163 void LIR_Assembler::on_spin_wait() { 3164 __ spin_wait(); 3165 } 3166 3167 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3168 __ mov(result_reg->as_register(), rthread); 3169 } 3170 3171 void LIR_Assembler::check_orig_pc() { 3172 __ ldr(rscratch2, frame_map()->address_for_orig_pc_addr()); 3173 __ cmp(rscratch2, (u1)NULL_WORD); 3174 } 3175 3176 void LIR_Assembler::peephole(LIR_List *lir) { 3177 #if 0 3178 if (tableswitch_count >= max_tableswitches) 3179 return; 3180 3181 /* 3182 This finite-state automaton recognizes sequences of compare-and- 3183 branch instructions. We will turn them into a tableswitch. You 3184 could argue that C1 really shouldn't be doing this sort of 3185 optimization, but without it the code is really horrible. 3186 */ 3187 3188 enum { start_s, cmp1_s, beq_s, cmp_s } state; 3189 int first_key, last_key = -2147483648; 3190 int next_key = 0; 3191 int start_insn = -1; 3192 int last_insn = -1; 3193 Register reg = noreg; 3194 LIR_Opr reg_opr; 3195 state = start_s; 3196 3197 LIR_OpList* inst = lir->instructions_list(); 3198 for (int i = 0; i < inst->length(); i++) { 3199 LIR_Op* op = inst->at(i); 3200 switch (state) { 3201 case start_s: 3202 first_key = -1; 3203 start_insn = i; 3204 switch (op->code()) { 3205 case lir_cmp: 3206 LIR_Opr opr1 = op->as_Op2()->in_opr1(); 3207 LIR_Opr opr2 = op->as_Op2()->in_opr2(); 3208 if (opr1->is_cpu_register() && opr1->is_single_cpu() 3209 && opr2->is_constant() 3210 && opr2->type() == T_INT) { 3211 reg_opr = opr1; 3212 reg = opr1->as_register(); 3213 first_key = opr2->as_constant_ptr()->as_jint(); 3214 next_key = first_key + 1; 3215 state = cmp_s; 3216 goto next_state; 3217 } 3218 break; 3219 } 3220 break; 3221 case cmp_s: 3222 switch (op->code()) { 3223 case lir_branch: 3224 if (op->as_OpBranch()->cond() == lir_cond_equal) { 3225 state = beq_s; 3226 last_insn = i; 3227 goto next_state; 3228 } 3229 } 3230 state = start_s; 3231 break; 3232 case beq_s: 3233 switch (op->code()) { 3234 case lir_cmp: { 3235 LIR_Opr opr1 = op->as_Op2()->in_opr1(); 3236 LIR_Opr opr2 = op->as_Op2()->in_opr2(); 3237 if (opr1->is_cpu_register() && opr1->is_single_cpu() 3238 && opr1->as_register() == reg 3239 && opr2->is_constant() 3240 && opr2->type() == T_INT 3241 && opr2->as_constant_ptr()->as_jint() == next_key) { 3242 last_key = next_key; 3243 next_key++; 3244 state = cmp_s; 3245 goto next_state; 3246 } 3247 } 3248 } 3249 last_key = next_key; 3250 state = start_s; 3251 break; 3252 default: 3253 assert(false, "impossible state"); 3254 } 3255 if (state == start_s) { 3256 if (first_key < last_key - 5L && reg != noreg) { 3257 { 3258 // printf("found run register %d starting at insn %d low value %d high value %d\n", 3259 // reg->encoding(), 3260 // start_insn, first_key, last_key); 3261 // for (int i = 0; i < inst->length(); i++) { 3262 // inst->at(i)->print(); 3263 // tty->print("\n"); 3264 // } 3265 // tty->print("\n"); 3266 } 3267 3268 struct tableswitch *sw = &switches[tableswitch_count]; 3269 sw->_insn_index = start_insn, sw->_first_key = first_key, 3270 sw->_last_key = last_key, sw->_reg = reg; 3271 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after)); 3272 { 3273 // Insert the new table of branches 3274 int offset = last_insn; 3275 for (int n = first_key; n < last_key; n++) { 3276 inst->insert_before 3277 (last_insn + 1, 3278 new LIR_OpBranch(lir_cond_always, T_ILLEGAL, 3279 inst->at(offset)->as_OpBranch()->label())); 3280 offset -= 2, i++; 3281 } 3282 } 3283 // Delete all the old compare-and-branch instructions 3284 for (int n = first_key; n < last_key; n++) { 3285 inst->remove_at(start_insn); 3286 inst->remove_at(start_insn); 3287 } 3288 // Insert the tableswitch instruction 3289 inst->insert_before(start_insn, 3290 new LIR_Op2(lir_cmp, lir_cond_always, 3291 LIR_OprFact::intConst(tableswitch_count), 3292 reg_opr)); 3293 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches)); 3294 tableswitch_count++; 3295 } 3296 reg = noreg; 3297 last_key = -2147483648; 3298 } 3299 next_state: 3300 ; 3301 } 3302 #endif 3303 } 3304 3305 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) { 3306 Address addr = as_Address(src->as_address_ptr()); 3307 BasicType type = src->type(); 3308 bool is_oop = is_reference_type(type); 3309 3310 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr); 3311 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr); 3312 3313 switch(type) { 3314 case T_INT: 3315 xchg = &MacroAssembler::atomic_xchgalw; 3316 add = &MacroAssembler::atomic_addalw; 3317 break; 3318 case T_LONG: 3319 xchg = &MacroAssembler::atomic_xchgal; 3320 add = &MacroAssembler::atomic_addal; 3321 break; 3322 case T_OBJECT: 3323 case T_ARRAY: 3324 if (UseCompressedOops) { 3325 xchg = &MacroAssembler::atomic_xchgalw; 3326 add = &MacroAssembler::atomic_addalw; 3327 } else { 3328 xchg = &MacroAssembler::atomic_xchgal; 3329 add = &MacroAssembler::atomic_addal; 3330 } 3331 break; 3332 default: 3333 ShouldNotReachHere(); 3334 xchg = &MacroAssembler::atomic_xchgal; 3335 add = &MacroAssembler::atomic_addal; // unreachable 3336 } 3337 3338 switch (code) { 3339 case lir_xadd: 3340 { 3341 RegisterOrConstant inc; 3342 Register tmp = as_reg(tmp_op); 3343 Register dst = as_reg(dest); 3344 if (data->is_constant()) { 3345 inc = RegisterOrConstant(as_long(data)); 3346 assert_different_registers(dst, addr.base(), tmp, 3347 rscratch1, rscratch2); 3348 } else { 3349 inc = RegisterOrConstant(as_reg(data)); 3350 assert_different_registers(inc.as_register(), dst, addr.base(), tmp, 3351 rscratch1, rscratch2); 3352 } 3353 __ lea(tmp, addr); 3354 (_masm->*add)(dst, inc, tmp); 3355 break; 3356 } 3357 case lir_xchg: 3358 { 3359 Register tmp = tmp_op->as_register(); 3360 Register obj = as_reg(data); 3361 Register dst = as_reg(dest); 3362 if (is_oop && UseCompressedOops) { 3363 __ encode_heap_oop(rscratch2, obj); 3364 obj = rscratch2; 3365 } 3366 assert_different_registers(obj, addr.base(), tmp, rscratch1); 3367 assert_different_registers(dst, addr.base(), tmp, rscratch1); 3368 __ lea(tmp, addr); 3369 (_masm->*xchg)(dst, obj, tmp); 3370 if (is_oop && UseCompressedOops) { 3371 __ decode_heap_oop(dst); 3372 } 3373 } 3374 break; 3375 default: 3376 ShouldNotReachHere(); 3377 } 3378 __ membar(__ AnyAny); 3379 } 3380 3381 #undef __