1 /*
2 * Copyright (c) 2000, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * Copyright 2026 Arm Limited and/or its affiliates.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "code/aotCodeCache.hpp"
38 #include "code/compiledIC.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "runtime/stubRoutines.hpp"
46 #include "runtime/threadIdentifier.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_aarch64.inline.hpp"
49
50
51 #ifndef PRODUCT
52 #define COMMENT(x) do { __ block_comment(x); } while (0)
53 #else
54 #define COMMENT(x)
55 #endif
56
57 NEEDS_CLEANUP // remove this definitions ?
58 const Register SYNC_header = r0; // synchronization header
59 const Register SHIFT_count = r0; // where count for shift operations must be
60
61 #define __ _masm->
62
63
64 static void select_different_registers(Register preserve,
65 Register extra,
66 Register &tmp1,
67 Register &tmp2,
68 Register &tmp3) {
69 if (tmp1 == preserve) {
70 assert_different_registers(tmp1, tmp2, tmp3, extra);
71 tmp1 = extra;
72 } else if (tmp2 == preserve) {
73 assert_different_registers(tmp1, tmp2, tmp3, extra);
74 tmp2 = extra;
75 } else if (tmp3 == preserve) {
76 assert_different_registers(tmp1, tmp2, tmp3, extra);
77 tmp3 = extra;
78 }
79 assert_different_registers(preserve, tmp1, tmp2, tmp3);
80 }
81
82
83 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
84
85
86 LIR_Opr LIR_Assembler::receiverOpr() {
87 return FrameMap::receiver_opr;
88 }
89
90 LIR_Opr LIR_Assembler::osrBufferPointer() {
91 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
92 }
93
94 //--------------fpu register translations-----------------------
95
96
97 address LIR_Assembler::float_constant(float f) {
98 address const_addr = __ float_constant(f);
99 if (const_addr == nullptr) {
100 bailout("const section overflow");
101 return __ code()->consts()->start();
102 } else {
103 return const_addr;
104 }
105 }
106
107
108 address LIR_Assembler::double_constant(double d) {
109 address const_addr = __ double_constant(d);
110 if (const_addr == nullptr) {
111 bailout("const section overflow");
112 return __ code()->consts()->start();
113 } else {
114 return const_addr;
115 }
116 }
117
118 address LIR_Assembler::int_constant(jlong n) {
119 address const_addr = __ long_constant(n);
120 if (const_addr == nullptr) {
121 bailout("const section overflow");
122 return __ code()->consts()->start();
123 } else {
124 return const_addr;
125 }
126 }
127
128 void LIR_Assembler::breakpoint() { Unimplemented(); }
129
130 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
131
132 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
133
134 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
135 //-------------------------------------------
136
137 static Register as_reg(LIR_Opr op) {
138 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
139 }
140
141 static jlong as_long(LIR_Opr data) {
142 jlong result;
143 switch (data->type()) {
144 case T_INT:
145 result = (data->as_jint());
146 break;
147 case T_LONG:
148 result = (data->as_jlong());
149 break;
150 default:
151 ShouldNotReachHere();
152 result = 0; // unreachable
153 }
154 return result;
155 }
156
157 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
158 Register base = addr->base()->as_pointer_register();
159 LIR_Opr opr = addr->index();
160 if (opr->is_cpu_register()) {
161 Register index;
162 if (opr->is_single_cpu())
163 index = opr->as_register();
164 else
165 index = opr->as_register_lo();
166 assert(addr->disp() == 0, "must be");
167 switch(opr->type()) {
168 case T_INT:
169 return Address(base, index, Address::sxtw(addr->scale()));
170 case T_LONG:
171 return Address(base, index, Address::lsl(addr->scale()));
172 default:
173 ShouldNotReachHere();
174 }
175 } else {
176 assert(addr->scale() == 0,
177 "expected for immediate operand, was: %d", addr->scale());
178 ptrdiff_t offset = ptrdiff_t(addr->disp());
179 // NOTE: Does not handle any 16 byte vector access.
180 const uint type_size = type2aelembytes(addr->type(), true);
181 return __ legitimize_address(Address(base, offset), type_size, tmp);
182 }
183 return Address();
184 }
185
186 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
187 ShouldNotReachHere();
188 return Address();
189 }
190
191 Address LIR_Assembler::as_Address(LIR_Address* addr) {
192 return as_Address(addr, rscratch1);
193 }
194
195 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
196 return as_Address(addr, rscratch1); // Ouch
197 // FIXME: This needs to be much more clever. See x86.
198 }
199
200 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
201 // not encodable as a base + (immediate) offset, generate an explicit address
202 // calculation to hold the address in a temporary register.
203 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
204 precond(size == 4 || size == 8);
205 Address addr = frame_map()->address_for_slot(index, adjust);
206 precond(addr.getMode() == Address::base_plus_offset);
207 precond(addr.base() == sp);
208 precond(addr.offset() > 0);
209 uint mask = size - 1;
210 assert((addr.offset() & mask) == 0, "scaled offsets only");
211 return __ legitimize_address(addr, size, tmp);
212 }
213
214 void LIR_Assembler::osr_entry() {
215 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
216 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
217 ValueStack* entry_state = osr_entry->state();
218 int number_of_locks = entry_state->locks_size();
219
220 // we jump here if osr happens with the interpreter
221 // state set up to continue at the beginning of the
222 // loop that triggered osr - in particular, we have
223 // the following registers setup:
224 //
225 // r2: osr buffer
226 //
227
228 // build frame
229 ciMethod* m = compilation()->method();
230 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
231
232 // OSR buffer is
233 //
234 // locals[nlocals-1..0]
235 // monitors[0..number_of_locks]
236 //
237 // locals is a direct copy of the interpreter frame so in the osr buffer
238 // so first slot in the local array is the last local from the interpreter
239 // and last slot is local[0] (receiver) from the interpreter
240 //
241 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
242 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
243 // in the interpreter frame (the method lock if a sync method)
244
245 // Initialize monitors in the compiled activation.
246 // r2: pointer to osr buffer
247 //
248 // All other registers are dead at this point and the locals will be
249 // copied into place by code emitted in the IR.
250
251 Register OSR_buf = osrBufferPointer()->as_pointer_register();
252 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
253 int monitor_offset = BytesPerWord * method()->max_locals() +
254 (2 * BytesPerWord) * (number_of_locks - 1);
255 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
256 // the OSR buffer using 2 word entries: first the lock and then
257 // the oop.
258 for (int i = 0; i < number_of_locks; i++) {
259 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
260 #ifdef ASSERT
261 // verify the interpreter's monitor has a non-null object
262 {
263 Label L;
264 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
265 __ cbnz(rscratch1, L);
266 __ stop("locked object is null");
267 __ bind(L);
268 }
269 #endif
270 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
271 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
272 __ str(r19, frame_map()->address_for_monitor_lock(i));
273 __ str(r20, frame_map()->address_for_monitor_object(i));
274 }
275 }
276 }
277
278
279 // inline cache check; done before the frame is built.
280 int LIR_Assembler::check_icache() {
281 return __ ic_check(CodeEntryAlignment);
282 }
283
284 void LIR_Assembler::clinit_barrier(ciMethod* method) {
285 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
286 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
287
288 Label L_skip_barrier;
289
290 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
291 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
292 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
293 __ bind(L_skip_barrier);
294 }
295
296 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
297 if (o == nullptr) {
298 __ mov(reg, zr);
299 } else {
300 __ movoop(reg, o);
301 }
302 }
303
304 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
305 address target = nullptr;
306 relocInfo::relocType reloc_type = relocInfo::none;
307
308 switch (patching_id(info)) {
309 case PatchingStub::access_field_id:
310 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
311 reloc_type = relocInfo::section_word_type;
312 break;
313 case PatchingStub::load_klass_id:
314 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
315 reloc_type = relocInfo::metadata_type;
316 break;
317 case PatchingStub::load_mirror_id:
318 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
319 reloc_type = relocInfo::oop_type;
320 break;
321 case PatchingStub::load_appendix_id:
322 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
323 reloc_type = relocInfo::oop_type;
324 break;
325 default: ShouldNotReachHere();
326 }
327
328 __ far_call(RuntimeAddress(target));
329 add_call_info_here(info);
330 }
331
332 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
333 deoptimize_trap(info);
334 }
335
336
337 // This specifies the rsp decrement needed to build the frame
338 int LIR_Assembler::initial_frame_size_in_bytes() const {
339 // if rounding, must let FrameMap know!
340
341 return in_bytes(frame_map()->framesize_in_bytes());
342 }
343
344
345 int LIR_Assembler::emit_exception_handler() {
346 // generate code for exception handler
347 address handler_base = __ start_a_stub(exception_handler_size());
348 if (handler_base == nullptr) {
349 // not enough space left for the handler
350 bailout("exception handler overflow");
351 return -1;
352 }
353
354 int offset = code_offset();
355
356 // the exception oop and pc are in r0, and r3
357 // no other registers need to be preserved, so invalidate them
358 __ invalidate_registers(false, true, true, false, true, true);
359
360 // check that there is really an exception
361 __ verify_not_null_oop(r0);
362
363 // search an exception handler (r0: exception oop, r3: throwing pc)
364 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
365 __ should_not_reach_here();
366 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
367 __ end_a_stub();
368
369 return offset;
370 }
371
372
373 // Emit the code to remove the frame from the stack in the exception
374 // unwind path.
375 int LIR_Assembler::emit_unwind_handler() {
376 #ifndef PRODUCT
377 if (CommentedAssembly) {
378 _masm->block_comment("Unwind handler");
379 }
380 #endif
381
382 int offset = code_offset();
383
384 // Fetch the exception from TLS and clear out exception related thread state
385 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
386 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
387 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
388
389 __ bind(_unwind_handler_entry);
390 __ verify_not_null_oop(r0);
391 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
392 __ mov(r19, r0); // Preserve the exception
393 }
394
395 // Perform needed unlocking
396 MonitorExitStub* stub = nullptr;
397 if (method()->is_synchronized()) {
398 monitor_address(0, FrameMap::r0_opr);
399 stub = new MonitorExitStub(FrameMap::r0_opr, 0);
400 __ unlock_object(r5, r4, r0, r6, *stub->entry());
401 __ bind(*stub->continuation());
402 }
403
404 if (compilation()->env()->dtrace_method_probes()) {
405 __ mov(c_rarg0, rthread);
406 __ mov_metadata(c_rarg1, method()->constant_encoding());
407 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
408 }
409
410 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
411 __ mov(r0, r19); // Restore the exception
412 }
413
414 // remove the activation and dispatch to the unwind handler
415 __ block_comment("remove_frame and dispatch to the unwind handler");
416 __ remove_frame(initial_frame_size_in_bytes());
417 __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
418
419 // Emit the slow path assembly
420 if (stub != nullptr) {
421 stub->emit_code(this);
422 }
423
424 return offset;
425 }
426
427
428 int LIR_Assembler::emit_deopt_handler() {
429 // generate code for exception handler
430 address handler_base = __ start_a_stub(deopt_handler_size());
431 if (handler_base == nullptr) {
432 // not enough space left for the handler
433 bailout("deopt handler overflow");
434 return -1;
435 }
436
437 int offset = code_offset();
438
439 Label start;
440 __ bind(start);
441
442 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
443
444 int entry_offset = __ offset();
445 __ b(start);
446
447 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
448 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
449 "out of bounds read in post-call NOP check");
450 __ end_a_stub();
451
452 return entry_offset;
453 }
454
455 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
456 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
457
458 // Pop the stack before the safepoint code
459 __ remove_frame(initial_frame_size_in_bytes());
460
461 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
462 __ reserved_stack_check();
463 }
464
465 code_stub->set_safepoint_offset(__ offset());
466 __ relocate(relocInfo::poll_return_type);
467 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
468 __ ret(lr);
469 }
470
471 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
472 guarantee(info != nullptr, "Shouldn't be null");
473 __ get_polling_page(rscratch1, relocInfo::poll_type);
474 add_debug_info_for_branch(info); // This isn't just debug info:
475 // it's the oop map
476 __ read_polling_page(rscratch1, relocInfo::poll_type);
477 return __ offset();
478 }
479
480
481 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
482 if (from_reg == r31_sp)
483 from_reg = sp;
484 if (to_reg == r31_sp)
485 to_reg = sp;
486 __ mov(to_reg, from_reg);
487 }
488
489 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
490
491
492 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
493 assert(src->is_constant(), "should not call otherwise");
494 assert(dest->is_register(), "should not call otherwise");
495 LIR_Const* c = src->as_constant_ptr();
496
497 switch (c->type()) {
498 case T_INT: {
499 assert(patch_code == lir_patch_none, "no patching handled here");
500 __ movw(dest->as_register(), c->as_jint());
501 break;
502 }
503
504 case T_ADDRESS: {
505 assert(patch_code == lir_patch_none, "no patching handled here");
506 __ mov(dest->as_register(), c->as_jint());
507 break;
508 }
509
510 case T_LONG: {
511 assert(patch_code == lir_patch_none, "no patching handled here");
512 #if INCLUDE_CDS
513 if (AOTCodeCache::is_on_for_dump()) {
514 address b = c->as_pointer();
515 if (b == (address)ThreadIdentifier::unsafe_offset()) {
516 __ lea(dest->as_register_lo(), ExternalAddress(b));
517 break;
518 }
519 if (AOTRuntimeConstants::contains(b)) {
520 __ load_aotrc_address(dest->as_register_lo(), b);
521 break;
522 }
523 }
524 #endif
525 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
526 break;
527 }
528
529 case T_OBJECT: {
530 if (patch_code == lir_patch_none) {
531 jobject2reg(c->as_jobject(), dest->as_register());
532 } else {
533 jobject2reg_with_patching(dest->as_register(), info);
534 }
535 break;
536 }
537
538 case T_METADATA: {
539 if (patch_code != lir_patch_none) {
540 klass2reg_with_patching(dest->as_register(), info);
541 } else {
542 __ mov_metadata(dest->as_register(), c->as_metadata());
543 }
544 break;
545 }
546
547 case T_FLOAT: {
548 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
549 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
550 } else {
551 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
552 __ ldrs(dest->as_float_reg(), Address(rscratch1));
553 }
554 break;
555 }
556
557 case T_DOUBLE: {
558 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
559 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
560 } else {
561 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
562 __ ldrd(dest->as_double_reg(), Address(rscratch1));
563 }
564 break;
565 }
566
567 default:
568 ShouldNotReachHere();
569 }
570 }
571
572 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
573 LIR_Const* c = src->as_constant_ptr();
574 switch (c->type()) {
575 case T_OBJECT:
576 {
577 if (! c->as_jobject())
578 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
579 else {
580 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
581 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
582 }
583 }
584 break;
585 case T_ADDRESS:
586 {
587 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
588 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
589 }
590 case T_INT:
591 case T_FLOAT:
592 {
593 Register reg = zr;
594 if (c->as_jint_bits() == 0)
595 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
596 else {
597 __ movw(rscratch1, c->as_jint_bits());
598 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
599 }
600 }
601 break;
602 case T_LONG:
603 case T_DOUBLE:
604 {
605 Register reg = zr;
606 if (c->as_jlong_bits() == 0)
607 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
608 lo_word_offset_in_bytes));
609 else {
610 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
611 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
612 lo_word_offset_in_bytes));
613 }
614 }
615 break;
616 default:
617 ShouldNotReachHere();
618 }
619 }
620
621 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
622 assert(src->is_constant(), "should not call otherwise");
623 LIR_Const* c = src->as_constant_ptr();
624 LIR_Address* to_addr = dest->as_address_ptr();
625
626 void (Assembler::* insn)(Register Rt, const Address &adr);
627
628 switch (type) {
629 case T_ADDRESS:
630 assert(c->as_jint() == 0, "should be");
631 insn = &Assembler::str;
632 break;
633 case T_LONG:
634 assert(c->as_jlong() == 0, "should be");
635 insn = &Assembler::str;
636 break;
637 case T_INT:
638 assert(c->as_jint() == 0, "should be");
639 insn = &Assembler::strw;
640 break;
641 case T_OBJECT:
642 case T_ARRAY:
643 assert(c->as_jobject() == nullptr, "should be");
644 if (UseCompressedOops && !wide) {
645 insn = &Assembler::strw;
646 } else {
647 insn = &Assembler::str;
648 }
649 break;
650 case T_CHAR:
651 case T_SHORT:
652 assert(c->as_jint() == 0, "should be");
653 insn = &Assembler::strh;
654 break;
655 case T_BOOLEAN:
656 case T_BYTE:
657 assert(c->as_jint() == 0, "should be");
658 insn = &Assembler::strb;
659 break;
660 default:
661 ShouldNotReachHere();
662 insn = &Assembler::str; // unreachable
663 }
664
665 if (info) add_debug_info_for_null_check_here(info);
666 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
667 }
668
669 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
670 assert(src->is_register(), "should not call otherwise");
671 assert(dest->is_register(), "should not call otherwise");
672
673 // move between cpu-registers
674 if (dest->is_single_cpu()) {
675 if (src->type() == T_LONG) {
676 // Can do LONG -> OBJECT
677 move_regs(src->as_register_lo(), dest->as_register());
678 return;
679 }
680 assert(src->is_single_cpu(), "must match");
681 if (src->type() == T_OBJECT) {
682 __ verify_oop(src->as_register());
683 }
684 move_regs(src->as_register(), dest->as_register());
685
686 } else if (dest->is_double_cpu()) {
687 if (is_reference_type(src->type())) {
688 // Surprising to me but we can see move of a long to t_object
689 __ verify_oop(src->as_register());
690 move_regs(src->as_register(), dest->as_register_lo());
691 return;
692 }
693 assert(src->is_double_cpu(), "must match");
694 Register f_lo = src->as_register_lo();
695 Register f_hi = src->as_register_hi();
696 Register t_lo = dest->as_register_lo();
697 Register t_hi = dest->as_register_hi();
698 assert(f_hi == f_lo, "must be same");
699 assert(t_hi == t_lo, "must be same");
700 move_regs(f_lo, t_lo);
701
702 } else if (dest->is_single_fpu()) {
703 __ fmovs(dest->as_float_reg(), src->as_float_reg());
704
705 } else if (dest->is_double_fpu()) {
706 __ fmovd(dest->as_double_reg(), src->as_double_reg());
707
708 } else {
709 ShouldNotReachHere();
710 }
711 }
712
713 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
714 precond(src->is_register() && dest->is_stack());
715
716 uint const c_sz32 = sizeof(uint32_t);
717 uint const c_sz64 = sizeof(uint64_t);
718
719 if (src->is_single_cpu()) {
720 int index = dest->single_stack_ix();
721 if (is_reference_type(type)) {
722 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
723 __ verify_oop(src->as_register());
724 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
725 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
726 } else {
727 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
728 }
729
730 } else if (src->is_double_cpu()) {
731 int index = dest->double_stack_ix();
732 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
733 __ str(src->as_register_lo(), dest_addr_LO);
734
735 } else if (src->is_single_fpu()) {
736 int index = dest->single_stack_ix();
737 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
738
739 } else if (src->is_double_fpu()) {
740 int index = dest->double_stack_ix();
741 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
742
743 } else {
744 ShouldNotReachHere();
745 }
746 }
747
748
749 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
750 LIR_Address* to_addr = dest->as_address_ptr();
751 PatchingStub* patch = nullptr;
752 Register compressed_src = rscratch1;
753
754 if (patch_code != lir_patch_none) {
755 deoptimize_trap(info);
756 return;
757 }
758
759 if (is_reference_type(type)) {
760 __ verify_oop(src->as_register());
761
762 if (UseCompressedOops && !wide) {
763 __ encode_heap_oop(compressed_src, src->as_register());
764 } else {
765 compressed_src = src->as_register();
766 }
767 }
768
769 int null_check_here = code_offset();
770 switch (type) {
771 case T_FLOAT: {
772 __ strs(src->as_float_reg(), as_Address(to_addr));
773 break;
774 }
775
776 case T_DOUBLE: {
777 __ strd(src->as_double_reg(), as_Address(to_addr));
778 break;
779 }
780
781 case T_ARRAY: // fall through
782 case T_OBJECT: // fall through
783 if (UseCompressedOops && !wide) {
784 __ strw(compressed_src, as_Address(to_addr, rscratch2));
785 } else {
786 __ str(compressed_src, as_Address(to_addr));
787 }
788 break;
789 case T_METADATA:
790 // We get here to store a method pointer to the stack to pass to
791 // a dtrace runtime call. This can't work on 64 bit with
792 // compressed klass ptrs: T_METADATA can be a compressed klass
793 // ptr or a 64 bit method pointer.
794 ShouldNotReachHere();
795 __ str(src->as_register(), as_Address(to_addr));
796 break;
797 case T_ADDRESS:
798 __ str(src->as_register(), as_Address(to_addr));
799 break;
800 case T_INT:
801 __ strw(src->as_register(), as_Address(to_addr));
802 break;
803
804 case T_LONG: {
805 __ str(src->as_register_lo(), as_Address_lo(to_addr));
806 break;
807 }
808
809 case T_BYTE: // fall through
810 case T_BOOLEAN: {
811 __ strb(src->as_register(), as_Address(to_addr));
812 break;
813 }
814
815 case T_CHAR: // fall through
816 case T_SHORT:
817 __ strh(src->as_register(), as_Address(to_addr));
818 break;
819
820 default:
821 ShouldNotReachHere();
822 }
823 if (info != nullptr) {
824 add_debug_info_for_null_check(null_check_here, info);
825 }
826 }
827
828
829 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
830 precond(src->is_stack() && dest->is_register());
831
832 uint const c_sz32 = sizeof(uint32_t);
833 uint const c_sz64 = sizeof(uint64_t);
834
835 if (dest->is_single_cpu()) {
836 int index = src->single_stack_ix();
837 if (is_reference_type(type)) {
838 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
839 __ verify_oop(dest->as_register());
840 } else if (type == T_METADATA || type == T_ADDRESS) {
841 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
842 } else {
843 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
844 }
845
846 } else if (dest->is_double_cpu()) {
847 int index = src->double_stack_ix();
848 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
849 __ ldr(dest->as_register_lo(), src_addr_LO);
850
851 } else if (dest->is_single_fpu()) {
852 int index = src->single_stack_ix();
853 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
854
855 } else if (dest->is_double_fpu()) {
856 int index = src->double_stack_ix();
857 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
858
859 } else {
860 ShouldNotReachHere();
861 }
862 }
863
864
865 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
866 address target = nullptr;
867 relocInfo::relocType reloc_type = relocInfo::none;
868
869 switch (patching_id(info)) {
870 case PatchingStub::access_field_id:
871 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
872 reloc_type = relocInfo::section_word_type;
873 break;
874 case PatchingStub::load_klass_id:
875 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
876 reloc_type = relocInfo::metadata_type;
877 break;
878 case PatchingStub::load_mirror_id:
879 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
880 reloc_type = relocInfo::oop_type;
881 break;
882 case PatchingStub::load_appendix_id:
883 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
884 reloc_type = relocInfo::oop_type;
885 break;
886 default: ShouldNotReachHere();
887 }
888
889 __ far_call(RuntimeAddress(target));
890 add_call_info_here(info);
891 }
892
893 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
894
895 LIR_Opr temp;
896 if (type == T_LONG || type == T_DOUBLE)
897 temp = FrameMap::rscratch1_long_opr;
898 else
899 temp = FrameMap::rscratch1_opr;
900
901 stack2reg(src, temp, src->type());
902 reg2stack(temp, dest, dest->type());
903 }
904
905 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
906 LIR_PatchCode patch_code, CodeEmitInfo* info,
907 bool wide) {
908 mem2reg(src, dest, type, patch_code, info, wide, false);
909 }
910
911 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
912 LIR_PatchCode patch_code, CodeEmitInfo* info,
913 bool wide, bool is_volatile) {
914 LIR_Address* addr = src->as_address_ptr();
915 LIR_Address* from_addr = src->as_address_ptr();
916
917 if (addr->base()->type() == T_OBJECT) {
918 __ verify_oop(addr->base()->as_pointer_register());
919 }
920
921 if (patch_code != lir_patch_none) {
922 deoptimize_trap(info);
923 return;
924 }
925
926 if (is_volatile) {
927 load_volatile(from_addr, dest, type, info);
928 } else {
929 load_unordered(from_addr, dest, type, wide, info);
930 }
931
932 if (is_reference_type(type)) {
933 if (UseCompressedOops && !wide) {
934 __ decode_heap_oop(dest->as_register());
935 }
936
937 __ verify_oop(dest->as_register());
938 }
939 }
940
941 void LIR_Assembler::load_unordered(LIR_Address *from_addr, LIR_Opr dest,
942 BasicType type, bool wide, CodeEmitInfo* info) {
943 if (info != nullptr) {
944 add_debug_info_for_null_check_here(info);
945 }
946
947 switch (type) {
948 case T_FLOAT: {
949 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
950 break;
951 }
952
953 case T_DOUBLE: {
954 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
955 break;
956 }
957
958 case T_ARRAY: // fall through
959 case T_OBJECT: // fall through
960 if (UseCompressedOops && !wide) {
961 __ ldrw(dest->as_register(), as_Address(from_addr));
962 } else {
963 __ ldr(dest->as_register(), as_Address(from_addr));
964 }
965 break;
966 case T_METADATA:
967 // We get here to store a method pointer to the stack to pass to
968 // a dtrace runtime call. This can't work on 64 bit with
969 // compressed klass ptrs: T_METADATA can be a compressed klass
970 // ptr or a 64 bit method pointer.
971 ShouldNotReachHere();
972 __ ldr(dest->as_register(), as_Address(from_addr));
973 break;
974 case T_ADDRESS:
975 __ ldr(dest->as_register(), as_Address(from_addr));
976 break;
977 case T_INT:
978 __ ldrw(dest->as_register(), as_Address(from_addr));
979 break;
980
981 case T_LONG: {
982 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
983 break;
984 }
985
986 case T_BYTE:
987 __ ldrsb(dest->as_register(), as_Address(from_addr));
988 break;
989 case T_BOOLEAN: {
990 __ ldrb(dest->as_register(), as_Address(from_addr));
991 break;
992 }
993
994 case T_CHAR:
995 __ ldrh(dest->as_register(), as_Address(from_addr));
996 break;
997 case T_SHORT:
998 __ ldrsh(dest->as_register(), as_Address(from_addr));
999 break;
1000
1001 default:
1002 ShouldNotReachHere();
1003 }
1004 }
1005
1006 void LIR_Assembler::load_volatile(LIR_Address *from_addr, LIR_Opr dest,
1007 BasicType type, CodeEmitInfo* info) {
1008 __ lea(rscratch1, as_Address(from_addr));
1009
1010 Register dest_reg = rscratch2;
1011 if (!is_floating_point_type(type)) {
1012 dest_reg = (dest->is_single_cpu()
1013 ? dest->as_register() : dest->as_register_lo());
1014 }
1015
1016 if (info != nullptr) {
1017 add_debug_info_for_null_check_here(info);
1018 }
1019
1020 // Uses LDAR to ensure memory ordering.
1021 __ load_store_volatile(dest_reg, type, rscratch1, /*is_load*/true);
1022
1023 switch (type) {
1024 // LDAR is unsigned so need to sign-extend for byte and short
1025 case T_BYTE:
1026 __ sxtb(dest_reg, dest_reg);
1027 break;
1028 case T_SHORT:
1029 __ sxth(dest_reg, dest_reg);
1030 break;
1031 // need to move from GPR to FPR after LDAR with FMOV for floating types
1032 case T_FLOAT:
1033 __ fmovs(dest->as_float_reg(), dest_reg);
1034 break;
1035 case T_DOUBLE:
1036 __ fmovd(dest->as_double_reg(), dest_reg);
1037 break;
1038 default:
1039 break;
1040 }
1041 }
1042
1043 int LIR_Assembler::array_element_size(BasicType type) const {
1044 int elem_size = type2aelembytes(type);
1045 return exact_log2(elem_size);
1046 }
1047
1048
1049 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1050 switch (op->code()) {
1051 case lir_idiv:
1052 case lir_irem:
1053 arithmetic_idiv(op->code(),
1054 op->in_opr1(),
1055 op->in_opr2(),
1056 op->in_opr3(),
1057 op->result_opr(),
1058 op->info());
1059 break;
1060 case lir_fmad:
1061 __ fmaddd(op->result_opr()->as_double_reg(),
1062 op->in_opr1()->as_double_reg(),
1063 op->in_opr2()->as_double_reg(),
1064 op->in_opr3()->as_double_reg());
1065 break;
1066 case lir_fmaf:
1067 __ fmadds(op->result_opr()->as_float_reg(),
1068 op->in_opr1()->as_float_reg(),
1069 op->in_opr2()->as_float_reg(),
1070 op->in_opr3()->as_float_reg());
1071 break;
1072 default: ShouldNotReachHere(); break;
1073 }
1074 }
1075
1076 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1077 #ifdef ASSERT
1078 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1079 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1080 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1081 #endif
1082
1083 if (op->cond() == lir_cond_always) {
1084 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1085 __ b(*(op->label()));
1086 } else {
1087 Assembler::Condition acond;
1088 if (op->code() == lir_cond_float_branch) {
1089 bool is_unordered = (op->ublock() == op->block());
1090 // Assembler::EQ does not permit unordered branches, so we add
1091 // another branch here. Likewise, Assembler::NE does not permit
1092 // ordered branches.
1093 if ((is_unordered && op->cond() == lir_cond_equal)
1094 || (!is_unordered && op->cond() == lir_cond_notEqual))
1095 __ br(Assembler::VS, *(op->ublock()->label()));
1096 switch(op->cond()) {
1097 case lir_cond_equal: acond = Assembler::EQ; break;
1098 case lir_cond_notEqual: acond = Assembler::NE; break;
1099 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1100 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1101 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1102 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1103 default: ShouldNotReachHere();
1104 acond = Assembler::EQ; // unreachable
1105 }
1106 } else {
1107 switch (op->cond()) {
1108 case lir_cond_equal: acond = Assembler::EQ; break;
1109 case lir_cond_notEqual: acond = Assembler::NE; break;
1110 case lir_cond_less: acond = Assembler::LT; break;
1111 case lir_cond_lessEqual: acond = Assembler::LE; break;
1112 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1113 case lir_cond_greater: acond = Assembler::GT; break;
1114 case lir_cond_belowEqual: acond = Assembler::LS; break;
1115 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1116 default: ShouldNotReachHere();
1117 acond = Assembler::EQ; // unreachable
1118 }
1119 }
1120 __ br(acond,*(op->label()));
1121 }
1122 }
1123
1124
1125
1126 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1127 LIR_Opr src = op->in_opr();
1128 LIR_Opr dest = op->result_opr();
1129
1130 switch (op->bytecode()) {
1131 case Bytecodes::_i2f:
1132 {
1133 __ scvtfws(dest->as_float_reg(), src->as_register());
1134 break;
1135 }
1136 case Bytecodes::_i2d:
1137 {
1138 __ scvtfwd(dest->as_double_reg(), src->as_register());
1139 break;
1140 }
1141 case Bytecodes::_l2d:
1142 {
1143 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1144 break;
1145 }
1146 case Bytecodes::_l2f:
1147 {
1148 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1149 break;
1150 }
1151 case Bytecodes::_f2d:
1152 {
1153 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1154 break;
1155 }
1156 case Bytecodes::_d2f:
1157 {
1158 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1159 break;
1160 }
1161 case Bytecodes::_i2c:
1162 {
1163 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1164 break;
1165 }
1166 case Bytecodes::_i2l:
1167 {
1168 __ sxtw(dest->as_register_lo(), src->as_register());
1169 break;
1170 }
1171 case Bytecodes::_i2s:
1172 {
1173 __ sxth(dest->as_register(), src->as_register());
1174 break;
1175 }
1176 case Bytecodes::_i2b:
1177 {
1178 __ sxtb(dest->as_register(), src->as_register());
1179 break;
1180 }
1181 case Bytecodes::_l2i:
1182 {
1183 _masm->block_comment("FIXME: This could be a no-op");
1184 __ uxtw(dest->as_register(), src->as_register_lo());
1185 break;
1186 }
1187 case Bytecodes::_d2l:
1188 {
1189 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1190 break;
1191 }
1192 case Bytecodes::_f2i:
1193 {
1194 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1195 break;
1196 }
1197 case Bytecodes::_f2l:
1198 {
1199 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1200 break;
1201 }
1202 case Bytecodes::_d2i:
1203 {
1204 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1205 break;
1206 }
1207 default: ShouldNotReachHere();
1208 }
1209 }
1210
1211 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1212 if (op->init_check()) {
1213 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1214 __ ldarb(rscratch1, rscratch1);
1215 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1216 add_debug_info_for_null_check_here(op->stub()->info());
1217 __ br(Assembler::NE, *op->stub()->entry());
1218 }
1219 __ allocate_object(op->obj()->as_register(),
1220 op->tmp1()->as_register(),
1221 op->tmp2()->as_register(),
1222 op->header_size(),
1223 op->object_size(),
1224 op->klass()->as_register(),
1225 *op->stub()->entry());
1226 __ bind(*op->stub()->continuation());
1227 }
1228
1229 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1230 Register len = op->len()->as_register();
1231 __ uxtw(len, len);
1232
1233 if (UseSlowPath ||
1234 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1235 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1236 __ b(*op->stub()->entry());
1237 } else {
1238 Register tmp1 = op->tmp1()->as_register();
1239 Register tmp2 = op->tmp2()->as_register();
1240 Register tmp3 = op->tmp3()->as_register();
1241 if (len == tmp1) {
1242 tmp1 = tmp3;
1243 } else if (len == tmp2) {
1244 tmp2 = tmp3;
1245 } else if (len == tmp3) {
1246 // everything is ok
1247 } else {
1248 __ mov(tmp3, len);
1249 }
1250 __ allocate_array(op->obj()->as_register(),
1251 len,
1252 tmp1,
1253 tmp2,
1254 arrayOopDesc::base_offset_in_bytes(op->type()),
1255 array_element_size(op->type()),
1256 op->klass()->as_register(),
1257 *op->stub()->entry(),
1258 op->zero_array());
1259 }
1260 __ bind(*op->stub()->continuation());
1261 }
1262
1263 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md,
1264 ciProfileData *data, Register recv) {
1265
1266 int mdp_offset = md->byte_offset_of_slot(data, in_ByteSize(0));
1267 __ profile_receiver_type(recv, mdo, mdp_offset);
1268 }
1269
1270 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1271 // we always need a stub for the failure case.
1272 CodeStub* stub = op->stub();
1273 Register obj = op->object()->as_register();
1274 Register k_RInfo = op->tmp1()->as_register();
1275 Register klass_RInfo = op->tmp2()->as_register();
1276 Register dst = op->result_opr()->as_register();
1277 ciKlass* k = op->klass();
1278 Register Rtmp1 = noreg;
1279
1280 // check if it needs to be profiled
1281 ciMethodData* md;
1282 ciProfileData* data;
1283
1284 const bool should_profile = op->should_profile();
1285
1286 if (should_profile) {
1287 ciMethod* method = op->profiled_method();
1288 assert(method != nullptr, "Should have method");
1289 int bci = op->profiled_bci();
1290 md = method->method_data_or_null();
1291 assert(md != nullptr, "Sanity");
1292 data = md->bci_to_data(bci);
1293 assert(data != nullptr, "need data for type check");
1294 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1295 }
1296 Label* success_target = success;
1297 Label* failure_target = failure;
1298
1299 if (obj == k_RInfo) {
1300 k_RInfo = dst;
1301 } else if (obj == klass_RInfo) {
1302 klass_RInfo = dst;
1303 }
1304
1305 Rtmp1 = op->tmp3()->as_register();
1306 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1307
1308 assert_different_registers(obj, k_RInfo, klass_RInfo);
1309
1310 if (should_profile) {
1311 Register mdo = klass_RInfo;
1312 __ mov_metadata(mdo, md->constant_encoding());
1313 Label not_null;
1314 __ cbnz(obj, not_null);
1315 // Object is null; update MDO and exit
1316 Address data_addr
1317 = __ form_address(rscratch2, mdo,
1318 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1319 0);
1320 __ ldrb(rscratch1, data_addr);
1321 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1322 __ strb(rscratch1, data_addr);
1323 __ b(*obj_is_null);
1324 __ bind(not_null);
1325
1326 Register recv = k_RInfo;
1327 __ load_klass(recv, obj);
1328 type_profile_helper(mdo, md, data, recv);
1329 } else {
1330 __ cbz(obj, *obj_is_null);
1331 }
1332
1333 if (!k->is_loaded()) {
1334 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1335 } else {
1336 __ mov_metadata(k_RInfo, k->constant_encoding());
1337 }
1338 __ verify_oop(obj);
1339
1340 if (op->fast_check()) {
1341 // get object class
1342 // not a safepoint as obj null check happens earlier
1343 __ load_klass(rscratch1, obj);
1344 __ cmp( rscratch1, k_RInfo);
1345
1346 __ br(Assembler::NE, *failure_target);
1347 // successful cast, fall through to profile or jump
1348 } else {
1349 // get object class
1350 // not a safepoint as obj null check happens earlier
1351 __ load_klass(klass_RInfo, obj);
1352 if (k->is_loaded()) {
1353 // See if we get an immediate positive hit
1354 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1355 __ cmp(k_RInfo, rscratch1);
1356 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1357 __ br(Assembler::NE, *failure_target);
1358 // successful cast, fall through to profile or jump
1359 } else {
1360 // See if we get an immediate positive hit
1361 __ br(Assembler::EQ, *success_target);
1362 // check for self
1363 __ cmp(klass_RInfo, k_RInfo);
1364 __ br(Assembler::EQ, *success_target);
1365
1366 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1367 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1368 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1369 // result is a boolean
1370 __ cbzw(klass_RInfo, *failure_target);
1371 // successful cast, fall through to profile or jump
1372 }
1373 } else {
1374 // perform the fast part of the checking logic
1375 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1376 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1377 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1378 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1379 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1380 // result is a boolean
1381 __ cbz(k_RInfo, *failure_target);
1382 // successful cast, fall through to profile or jump
1383 }
1384 }
1385 __ b(*success);
1386 }
1387
1388
1389 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1390 const bool should_profile = op->should_profile();
1391
1392 LIR_Code code = op->code();
1393 if (code == lir_store_check) {
1394 Register value = op->object()->as_register();
1395 Register array = op->array()->as_register();
1396 Register k_RInfo = op->tmp1()->as_register();
1397 Register klass_RInfo = op->tmp2()->as_register();
1398 Register Rtmp1 = op->tmp3()->as_register();
1399
1400 CodeStub* stub = op->stub();
1401
1402 // check if it needs to be profiled
1403 ciMethodData* md;
1404 ciProfileData* data;
1405
1406 if (should_profile) {
1407 ciMethod* method = op->profiled_method();
1408 assert(method != nullptr, "Should have method");
1409 int bci = op->profiled_bci();
1410 md = method->method_data_or_null();
1411 assert(md != nullptr, "Sanity");
1412 data = md->bci_to_data(bci);
1413 assert(data != nullptr, "need data for type check");
1414 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1415 }
1416 Label done;
1417 Label* success_target = &done;
1418 Label* failure_target = stub->entry();
1419
1420 if (should_profile) {
1421 Label not_null;
1422 Register mdo = klass_RInfo;
1423 __ mov_metadata(mdo, md->constant_encoding());
1424 __ cbnz(value, not_null);
1425 // Object is null; update MDO and exit
1426 Address data_addr
1427 = __ form_address(rscratch2, mdo,
1428 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1429 __ ldrb(rscratch1, data_addr);
1430 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1431 __ strb(rscratch1, data_addr);
1432 __ b(done);
1433 __ bind(not_null);
1434
1435 Register recv = k_RInfo;
1436 __ load_klass(recv, value);
1437 type_profile_helper(mdo, md, data, recv);
1438 } else {
1439 __ cbz(value, done);
1440 }
1441
1442 add_debug_info_for_null_check_here(op->info_for_exception());
1443 __ load_klass(k_RInfo, array);
1444 __ load_klass(klass_RInfo, value);
1445
1446 // get instance klass (it's already uncompressed)
1447 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1448 // perform the fast part of the checking logic
1449 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1450 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1451 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1452 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1453 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1454 // result is a boolean
1455 __ cbzw(k_RInfo, *failure_target);
1456 // fall through to the success case
1457
1458 __ bind(done);
1459 } else if (code == lir_checkcast) {
1460 Register obj = op->object()->as_register();
1461 Register dst = op->result_opr()->as_register();
1462 Label success;
1463 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1464 __ bind(success);
1465 if (dst != obj) {
1466 __ mov(dst, obj);
1467 }
1468 } else if (code == lir_instanceof) {
1469 Register obj = op->object()->as_register();
1470 Register dst = op->result_opr()->as_register();
1471 Label success, failure, done;
1472 emit_typecheck_helper(op, &success, &failure, &failure);
1473 __ bind(failure);
1474 __ mov(dst, zr);
1475 __ b(done);
1476 __ bind(success);
1477 __ mov(dst, 1);
1478 __ bind(done);
1479 } else {
1480 ShouldNotReachHere();
1481 }
1482 }
1483
1484 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1485 __ cmpxchg(addr, cmpval, newval, Assembler::word, memory_order_seq_cst, rscratch1);
1486 __ cset(rscratch1, Assembler::NE);
1487 }
1488
1489 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1490 __ cmpxchg(addr, cmpval, newval, Assembler::xword, memory_order_seq_cst, rscratch1);
1491 __ cset(rscratch1, Assembler::NE);
1492 }
1493
1494
1495 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1496 Register addr;
1497 if (op->addr()->is_register()) {
1498 addr = as_reg(op->addr());
1499 } else {
1500 assert(op->addr()->is_address(), "what else?");
1501 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1502 assert(addr_ptr->disp() == 0, "need 0 disp");
1503 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1504 addr = as_reg(addr_ptr->base());
1505 }
1506 Register newval = as_reg(op->new_value());
1507 Register cmpval = as_reg(op->cmp_value());
1508
1509 if (op->code() == lir_cas_obj) {
1510 if (UseCompressedOops) {
1511 Register t1 = op->tmp1()->as_register();
1512 assert(op->tmp1()->is_valid(), "must be");
1513 __ encode_heap_oop(t1, cmpval);
1514 cmpval = t1;
1515 __ encode_heap_oop(rscratch2, newval);
1516 newval = rscratch2;
1517 casw(addr, newval, cmpval);
1518 } else {
1519 casl(addr, newval, cmpval);
1520 }
1521 } else if (op->code() == lir_cas_int) {
1522 casw(addr, newval, cmpval);
1523 } else {
1524 casl(addr, newval, cmpval);
1525 }
1526 }
1527
1528
1529 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1530 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1531 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1532
1533 Assembler::Condition acond, ncond;
1534 switch (condition) {
1535 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1536 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1537 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1538 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1539 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1540 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1541 case lir_cond_belowEqual:
1542 case lir_cond_aboveEqual:
1543 default: ShouldNotReachHere();
1544 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1545 }
1546
1547 assert(result->is_single_cpu() || result->is_double_cpu(),
1548 "expect single register for result");
1549 if (opr1->is_constant() && opr2->is_constant()
1550 && opr1->type() == T_INT && opr2->type() == T_INT) {
1551 jint val1 = opr1->as_jint();
1552 jint val2 = opr2->as_jint();
1553 if (val1 == 0 && val2 == 1) {
1554 __ cset(result->as_register(), ncond);
1555 return;
1556 } else if (val1 == 1 && val2 == 0) {
1557 __ cset(result->as_register(), acond);
1558 return;
1559 }
1560 }
1561
1562 if (opr1->is_constant() && opr2->is_constant()
1563 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1564 jlong val1 = opr1->as_jlong();
1565 jlong val2 = opr2->as_jlong();
1566 if (val1 == 0 && val2 == 1) {
1567 __ cset(result->as_register_lo(), ncond);
1568 return;
1569 } else if (val1 == 1 && val2 == 0) {
1570 __ cset(result->as_register_lo(), acond);
1571 return;
1572 }
1573 }
1574
1575 if (opr1->is_stack()) {
1576 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1577 opr1 = FrameMap::rscratch1_opr;
1578 } else if (opr1->is_constant()) {
1579 LIR_Opr tmp
1580 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1581 const2reg(opr1, tmp, lir_patch_none, nullptr);
1582 opr1 = tmp;
1583 }
1584
1585 if (opr2->is_stack()) {
1586 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1587 opr2 = FrameMap::rscratch2_opr;
1588 } else if (opr2->is_constant()) {
1589 LIR_Opr tmp
1590 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1591 const2reg(opr2, tmp, lir_patch_none, nullptr);
1592 opr2 = tmp;
1593 }
1594
1595 if (result->type() == T_LONG)
1596 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1597 else
1598 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1599 }
1600
1601 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1602 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1603
1604 if (left->is_single_cpu()) {
1605 Register lreg = left->as_register();
1606 Register dreg = as_reg(dest);
1607
1608 if (right->is_single_cpu()) {
1609 // cpu register - cpu register
1610
1611 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1612 "should be");
1613 Register rreg = right->as_register();
1614 switch (code) {
1615 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1616 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1617 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1618 default: ShouldNotReachHere();
1619 }
1620
1621 } else if (right->is_double_cpu()) {
1622 Register rreg = right->as_register_lo();
1623 // single_cpu + double_cpu: can happen with obj+long
1624 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1625 switch (code) {
1626 case lir_add: __ add(dreg, lreg, rreg); break;
1627 case lir_sub: __ sub(dreg, lreg, rreg); break;
1628 default: ShouldNotReachHere();
1629 }
1630 } else if (right->is_constant()) {
1631 // cpu register - constant
1632 jlong c;
1633
1634 // FIXME. This is fugly: we really need to factor all this logic.
1635 switch(right->type()) {
1636 case T_LONG:
1637 c = right->as_constant_ptr()->as_jlong();
1638 break;
1639 case T_INT:
1640 case T_ADDRESS:
1641 c = right->as_constant_ptr()->as_jint();
1642 break;
1643 default:
1644 ShouldNotReachHere();
1645 c = 0; // unreachable
1646 break;
1647 }
1648
1649 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1650 if (c == 0 && dreg == lreg) {
1651 COMMENT("effective nop elided");
1652 return;
1653 }
1654 switch(left->type()) {
1655 case T_INT:
1656 switch (code) {
1657 case lir_add: __ addw(dreg, lreg, c); break;
1658 case lir_sub: __ subw(dreg, lreg, c); break;
1659 default: ShouldNotReachHere();
1660 }
1661 break;
1662 case T_OBJECT:
1663 case T_ADDRESS:
1664 switch (code) {
1665 case lir_add: __ add(dreg, lreg, c); break;
1666 case lir_sub: __ sub(dreg, lreg, c); break;
1667 default: ShouldNotReachHere();
1668 }
1669 break;
1670 default:
1671 ShouldNotReachHere();
1672 }
1673 } else {
1674 ShouldNotReachHere();
1675 }
1676
1677 } else if (left->is_double_cpu()) {
1678 Register lreg_lo = left->as_register_lo();
1679
1680 if (right->is_double_cpu()) {
1681 // cpu register - cpu register
1682 Register rreg_lo = right->as_register_lo();
1683 switch (code) {
1684 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1685 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1686 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1687 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1688 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1689 default:
1690 ShouldNotReachHere();
1691 }
1692
1693 } else if (right->is_constant()) {
1694 jlong c = right->as_constant_ptr()->as_jlong();
1695 Register dreg = as_reg(dest);
1696 switch (code) {
1697 case lir_add:
1698 case lir_sub:
1699 if (c == 0 && dreg == lreg_lo) {
1700 COMMENT("effective nop elided");
1701 return;
1702 }
1703 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1704 break;
1705 case lir_div:
1706 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1707 if (c == 1) {
1708 // move lreg_lo to dreg if divisor is 1
1709 __ mov(dreg, lreg_lo);
1710 } else {
1711 unsigned int shift = log2i_exact(c);
1712 // use rscratch1 as intermediate result register
1713 __ asr(rscratch1, lreg_lo, 63);
1714 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1715 __ asr(dreg, rscratch1, shift);
1716 }
1717 break;
1718 case lir_rem:
1719 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1720 if (c == 1) {
1721 // move 0 to dreg if divisor is 1
1722 __ mov(dreg, zr);
1723 } else {
1724 // use rscratch1 as intermediate result register
1725 __ negs(rscratch1, lreg_lo);
1726 __ andr(dreg, lreg_lo, c - 1);
1727 __ andr(rscratch1, rscratch1, c - 1);
1728 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1729 }
1730 break;
1731 default:
1732 ShouldNotReachHere();
1733 }
1734 } else {
1735 ShouldNotReachHere();
1736 }
1737 } else if (left->is_single_fpu()) {
1738 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1739 switch (code) {
1740 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1741 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1742 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1743 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1744 default:
1745 ShouldNotReachHere();
1746 }
1747 } else if (left->is_double_fpu()) {
1748 if (right->is_double_fpu()) {
1749 // fpu register - fpu register
1750 switch (code) {
1751 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1752 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1753 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1754 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1755 default:
1756 ShouldNotReachHere();
1757 }
1758 } else {
1759 if (right->is_constant()) {
1760 ShouldNotReachHere();
1761 }
1762 ShouldNotReachHere();
1763 }
1764 } else if (left->is_single_stack() || left->is_address()) {
1765 assert(left == dest, "left and dest must be equal");
1766 ShouldNotReachHere();
1767 } else {
1768 ShouldNotReachHere();
1769 }
1770 }
1771
1772 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1773 switch(code) {
1774 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1775 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1776 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1777 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1778 default : ShouldNotReachHere();
1779 }
1780 }
1781
1782 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1783
1784 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1785 Register Rleft = left->is_single_cpu() ? left->as_register() :
1786 left->as_register_lo();
1787 if (dst->is_single_cpu()) {
1788 Register Rdst = dst->as_register();
1789 if (right->is_constant()) {
1790 switch (code) {
1791 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1792 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1793 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1794 default: ShouldNotReachHere(); break;
1795 }
1796 } else {
1797 Register Rright = right->is_single_cpu() ? right->as_register() :
1798 right->as_register_lo();
1799 switch (code) {
1800 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1801 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1802 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1803 default: ShouldNotReachHere(); break;
1804 }
1805 }
1806 } else {
1807 Register Rdst = dst->as_register_lo();
1808 if (right->is_constant()) {
1809 switch (code) {
1810 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1811 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1812 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1813 default: ShouldNotReachHere(); break;
1814 }
1815 } else {
1816 Register Rright = right->is_single_cpu() ? right->as_register() :
1817 right->as_register_lo();
1818 switch (code) {
1819 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1820 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1821 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1822 default: ShouldNotReachHere(); break;
1823 }
1824 }
1825 }
1826 }
1827
1828
1829
1830 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1831
1832 // opcode check
1833 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1834 bool is_irem = (code == lir_irem);
1835
1836 // operand check
1837 assert(left->is_single_cpu(), "left must be register");
1838 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1839 assert(result->is_single_cpu(), "result must be register");
1840 Register lreg = left->as_register();
1841 Register dreg = result->as_register();
1842
1843 // power-of-2 constant check and codegen
1844 if (right->is_constant()) {
1845 int c = right->as_constant_ptr()->as_jint();
1846 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1847 if (is_irem) {
1848 if (c == 1) {
1849 // move 0 to dreg if divisor is 1
1850 __ movw(dreg, zr);
1851 } else {
1852 // use rscratch1 as intermediate result register
1853 __ negsw(rscratch1, lreg);
1854 __ andw(dreg, lreg, c - 1);
1855 __ andw(rscratch1, rscratch1, c - 1);
1856 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1857 }
1858 } else {
1859 if (c == 1) {
1860 // move lreg to dreg if divisor is 1
1861 __ movw(dreg, lreg);
1862 } else {
1863 unsigned int shift = exact_log2(c);
1864 // use rscratch1 as intermediate result register
1865 __ asrw(rscratch1, lreg, 31);
1866 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1867 __ asrw(dreg, rscratch1, shift);
1868 }
1869 }
1870 } else {
1871 Register rreg = right->as_register();
1872 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1873 }
1874 }
1875
1876
1877 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1878 if (opr1->is_constant() && opr2->is_single_cpu()) {
1879 // tableswitch
1880 Register reg = as_reg(opr2);
1881 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1882 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1883 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1884 Register reg1 = as_reg(opr1);
1885 if (opr2->is_single_cpu()) {
1886 // cpu register - cpu register
1887 Register reg2 = opr2->as_register();
1888 if (is_reference_type(opr1->type())) {
1889 __ cmpoop(reg1, reg2);
1890 } else {
1891 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1892 __ cmpw(reg1, reg2);
1893 }
1894 return;
1895 }
1896 if (opr2->is_double_cpu()) {
1897 // cpu register - cpu register
1898 Register reg2 = opr2->as_register_lo();
1899 __ cmp(reg1, reg2);
1900 return;
1901 }
1902
1903 if (opr2->is_constant()) {
1904 bool is_32bit = false; // width of register operand
1905 jlong imm;
1906
1907 switch(opr2->type()) {
1908 case T_INT:
1909 imm = opr2->as_constant_ptr()->as_jint();
1910 is_32bit = true;
1911 break;
1912 case T_LONG:
1913 imm = opr2->as_constant_ptr()->as_jlong();
1914 break;
1915 case T_ADDRESS:
1916 imm = opr2->as_constant_ptr()->as_jint();
1917 break;
1918 case T_METADATA:
1919 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1920 break;
1921 case T_OBJECT:
1922 case T_ARRAY:
1923 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1924 __ cmpoop(reg1, rscratch1);
1925 return;
1926 default:
1927 ShouldNotReachHere();
1928 imm = 0; // unreachable
1929 break;
1930 }
1931
1932 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1933 if (is_32bit)
1934 __ cmpw(reg1, imm);
1935 else
1936 __ subs(zr, reg1, imm);
1937 return;
1938 } else {
1939 __ mov(rscratch1, imm);
1940 if (is_32bit)
1941 __ cmpw(reg1, rscratch1);
1942 else
1943 __ cmp(reg1, rscratch1);
1944 return;
1945 }
1946 } else
1947 ShouldNotReachHere();
1948 } else if (opr1->is_single_fpu()) {
1949 FloatRegister reg1 = opr1->as_float_reg();
1950 assert(opr2->is_single_fpu(), "expect single float register");
1951 FloatRegister reg2 = opr2->as_float_reg();
1952 __ fcmps(reg1, reg2);
1953 } else if (opr1->is_double_fpu()) {
1954 FloatRegister reg1 = opr1->as_double_reg();
1955 assert(opr2->is_double_fpu(), "expect double float register");
1956 FloatRegister reg2 = opr2->as_double_reg();
1957 __ fcmpd(reg1, reg2);
1958 } else {
1959 ShouldNotReachHere();
1960 }
1961 }
1962
1963 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1964 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1965 bool is_unordered_less = (code == lir_ucmp_fd2i);
1966 if (left->is_single_fpu()) {
1967 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1968 } else if (left->is_double_fpu()) {
1969 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1970 } else {
1971 ShouldNotReachHere();
1972 }
1973 } else if (code == lir_cmp_l2i) {
1974 Label done;
1975 __ cmp(left->as_register_lo(), right->as_register_lo());
1976 __ mov(dst->as_register(), (uint64_t)-1L);
1977 __ br(Assembler::LT, done);
1978 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1979 __ bind(done);
1980 } else {
1981 ShouldNotReachHere();
1982 }
1983 }
1984
1985
1986 void LIR_Assembler::align_call(LIR_Code code) { }
1987
1988
1989 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
1990 address call = __ trampoline_call(Address(op->addr(), rtype));
1991 if (call == nullptr) {
1992 bailout("trampoline stub overflow");
1993 return;
1994 }
1995 add_call_info(code_offset(), op->info());
1996 __ post_call_nop();
1997 }
1998
1999
2000 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2001 address call = __ ic_call(op->addr());
2002 if (call == nullptr) {
2003 bailout("trampoline stub overflow");
2004 return;
2005 }
2006 add_call_info(code_offset(), op->info());
2007 __ post_call_nop();
2008 }
2009
2010 void LIR_Assembler::emit_static_call_stub() {
2011 address call_pc = __ pc();
2012 address stub = __ start_a_stub(call_stub_size());
2013 if (stub == nullptr) {
2014 bailout("static call stub overflow");
2015 return;
2016 }
2017
2018 int start = __ offset();
2019
2020 __ relocate(static_stub_Relocation::spec(call_pc));
2021 __ emit_static_call_stub();
2022
2023 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2024 <= call_stub_size(), "stub too big");
2025 __ end_a_stub();
2026 }
2027
2028
2029 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2030 assert(exceptionOop->as_register() == r0, "must match");
2031 assert(exceptionPC->as_register() == r3, "must match");
2032
2033 // exception object is not added to oop map by LinearScan
2034 // (LinearScan assumes that no oops are in fixed registers)
2035 info->add_register_oop(exceptionOop);
2036 StubId unwind_id;
2037
2038 // get current pc information
2039 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2040 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2041 // As no instructions have been generated yet for this LIR node it's
2042 // possible that an oop map already exists for the current offset.
2043 // In that case insert an dummy NOP here to ensure all oop map PCs
2044 // are unique. See JDK-8237483.
2045 __ nop();
2046 }
2047 int pc_for_athrow_offset = __ offset();
2048 InternalAddress pc_for_athrow(__ pc());
2049 __ adr(exceptionPC->as_register(), pc_for_athrow);
2050 add_call_info(pc_for_athrow_offset, info); // for exception handler
2051
2052 __ verify_not_null_oop(r0);
2053 // search an exception handler (r0: exception oop, r3: throwing pc)
2054 if (compilation()->has_fpu_code()) {
2055 unwind_id = StubId::c1_handle_exception_id;
2056 } else {
2057 unwind_id = StubId::c1_handle_exception_nofpu_id;
2058 }
2059 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2060
2061 // FIXME: enough room for two byte trap ????
2062 __ nop();
2063 }
2064
2065
2066 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2067 assert(exceptionOop->as_register() == r0, "must match");
2068
2069 __ b(_unwind_handler_entry);
2070 }
2071
2072
2073 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2074 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2075 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2076
2077 switch (left->type()) {
2078 case T_INT: {
2079 switch (code) {
2080 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2081 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2082 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2083 default:
2084 ShouldNotReachHere();
2085 break;
2086 }
2087 break;
2088 case T_LONG:
2089 case T_ADDRESS:
2090 case T_OBJECT:
2091 switch (code) {
2092 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2093 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2094 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2095 default:
2096 ShouldNotReachHere();
2097 break;
2098 }
2099 break;
2100 default:
2101 ShouldNotReachHere();
2102 break;
2103 }
2104 }
2105 }
2106
2107
2108 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2109 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2110 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2111
2112 switch (left->type()) {
2113 case T_INT: {
2114 switch (code) {
2115 case lir_shl: __ lslw (dreg, lreg, count); break;
2116 case lir_shr: __ asrw (dreg, lreg, count); break;
2117 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2118 default:
2119 ShouldNotReachHere();
2120 break;
2121 }
2122 break;
2123 case T_LONG:
2124 case T_ADDRESS:
2125 case T_OBJECT:
2126 switch (code) {
2127 case lir_shl: __ lsl (dreg, lreg, count); break;
2128 case lir_shr: __ asr (dreg, lreg, count); break;
2129 case lir_ushr: __ lsr (dreg, lreg, count); break;
2130 default:
2131 ShouldNotReachHere();
2132 break;
2133 }
2134 break;
2135 default:
2136 ShouldNotReachHere();
2137 break;
2138 }
2139 }
2140 }
2141
2142
2143 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2144 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2145 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2146 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2147 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2148 }
2149
2150
2151 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2152 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2153 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2154 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2155 __ mov (rscratch1, c);
2156 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2157 }
2158
2159
2160 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2161 ShouldNotReachHere();
2162 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2163 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2164 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2165 __ lea(rscratch1, __ constant_oop_address(o));
2166 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2167 }
2168
2169
2170 // This code replaces a call to arraycopy; no exception may
2171 // be thrown in this code, they must be thrown in the System.arraycopy
2172 // activation frame; we could save some checks if this would not be the case
2173 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2174 ciArrayKlass* default_type = op->expected_type();
2175 Register src = op->src()->as_register();
2176 Register dst = op->dst()->as_register();
2177 Register src_pos = op->src_pos()->as_register();
2178 Register dst_pos = op->dst_pos()->as_register();
2179 Register length = op->length()->as_register();
2180 Register tmp = op->tmp()->as_register();
2181
2182 CodeStub* stub = op->stub();
2183 int flags = op->flags();
2184 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2185 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2186
2187 // if we don't know anything, just go through the generic arraycopy
2188 if (default_type == nullptr // || basic_type == T_OBJECT
2189 ) {
2190 Label done;
2191 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2192
2193 // Save the arguments in case the generic arraycopy fails and we
2194 // have to fall back to the JNI stub
2195 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2196 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2197 __ str(src, Address(sp, 4*BytesPerWord));
2198
2199 address copyfunc_addr = StubRoutines::generic_arraycopy();
2200 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2201
2202 // The arguments are in java calling convention so we shift them
2203 // to C convention
2204 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2205 __ mov(c_rarg0, j_rarg0);
2206 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2207 __ mov(c_rarg1, j_rarg1);
2208 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2209 __ mov(c_rarg2, j_rarg2);
2210 assert_different_registers(c_rarg3, j_rarg4);
2211 __ mov(c_rarg3, j_rarg3);
2212 __ mov(c_rarg4, j_rarg4);
2213 #ifndef PRODUCT
2214 if (PrintC1Statistics) {
2215 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2216 }
2217 #endif
2218 __ far_call(RuntimeAddress(copyfunc_addr));
2219
2220 __ cbz(r0, *stub->continuation());
2221
2222 // Reload values from the stack so they are where the stub
2223 // expects them.
2224 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2225 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2226 __ ldr(src, Address(sp, 4*BytesPerWord));
2227
2228 // r0 is -1^K where K == partial copied count
2229 __ eonw(rscratch1, r0, zr);
2230 // adjust length down and src/end pos up by partial copied count
2231 __ subw(length, length, rscratch1);
2232 __ addw(src_pos, src_pos, rscratch1);
2233 __ addw(dst_pos, dst_pos, rscratch1);
2234 __ b(*stub->entry());
2235
2236 __ bind(*stub->continuation());
2237 return;
2238 }
2239
2240 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2241
2242 int elem_size = type2aelembytes(basic_type);
2243 int scale = exact_log2(elem_size);
2244
2245 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2246 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2247
2248 // test for null
2249 if (flags & LIR_OpArrayCopy::src_null_check) {
2250 __ cbz(src, *stub->entry());
2251 }
2252 if (flags & LIR_OpArrayCopy::dst_null_check) {
2253 __ cbz(dst, *stub->entry());
2254 }
2255
2256 // If the compiler was not able to prove that exact type of the source or the destination
2257 // of the arraycopy is an array type, check at runtime if the source or the destination is
2258 // an instance type.
2259 if (flags & LIR_OpArrayCopy::type_check) {
2260 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2261 __ load_klass(tmp, dst);
2262 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2263 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2264 __ br(Assembler::GE, *stub->entry());
2265 }
2266
2267 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2268 __ load_klass(tmp, src);
2269 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2270 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2271 __ br(Assembler::GE, *stub->entry());
2272 }
2273 }
2274
2275 // check if negative
2276 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2277 __ cmpw(src_pos, 0);
2278 __ br(Assembler::LT, *stub->entry());
2279 }
2280 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2281 __ cmpw(dst_pos, 0);
2282 __ br(Assembler::LT, *stub->entry());
2283 }
2284
2285 if (flags & LIR_OpArrayCopy::length_positive_check) {
2286 __ cmpw(length, 0);
2287 __ br(Assembler::LT, *stub->entry());
2288 }
2289
2290 if (flags & LIR_OpArrayCopy::src_range_check) {
2291 __ addw(tmp, src_pos, length);
2292 __ ldrw(rscratch1, src_length_addr);
2293 __ cmpw(tmp, rscratch1);
2294 __ br(Assembler::HI, *stub->entry());
2295 }
2296 if (flags & LIR_OpArrayCopy::dst_range_check) {
2297 __ addw(tmp, dst_pos, length);
2298 __ ldrw(rscratch1, dst_length_addr);
2299 __ cmpw(tmp, rscratch1);
2300 __ br(Assembler::HI, *stub->entry());
2301 }
2302
2303 if (flags & LIR_OpArrayCopy::type_check) {
2304 // We don't know the array types are compatible
2305 if (basic_type != T_OBJECT) {
2306 // Simple test for basic type arrays
2307 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2308 __ br(Assembler::NE, *stub->entry());
2309 } else {
2310 // For object arrays, if src is a sub class of dst then we can
2311 // safely do the copy.
2312 Label cont, slow;
2313
2314 #define PUSH(r1, r2) \
2315 stp(r1, r2, __ pre(sp, -2 * wordSize));
2316
2317 #define POP(r1, r2) \
2318 ldp(r1, r2, __ post(sp, 2 * wordSize));
2319
2320 __ PUSH(src, dst);
2321
2322 __ load_klass(src, src);
2323 __ load_klass(dst, dst);
2324
2325 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2326
2327 __ PUSH(src, dst);
2328 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2329 __ POP(src, dst);
2330
2331 __ cbnz(src, cont);
2332
2333 __ bind(slow);
2334 __ POP(src, dst);
2335
2336 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2337 if (copyfunc_addr != nullptr) { // use stub if available
2338 // src is not a sub class of dst so we have to do a
2339 // per-element check.
2340
2341 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2342 if ((flags & mask) != mask) {
2343 // Check that at least both of them object arrays.
2344 assert(flags & mask, "one of the two should be known to be an object array");
2345
2346 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2347 __ load_klass(tmp, src);
2348 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2349 __ load_klass(tmp, dst);
2350 }
2351 int lh_offset = in_bytes(Klass::layout_helper_offset());
2352 Address klass_lh_addr(tmp, lh_offset);
2353 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2354 __ ldrw(rscratch1, klass_lh_addr);
2355 __ mov(rscratch2, objArray_lh);
2356 __ eorw(rscratch1, rscratch1, rscratch2);
2357 __ cbnzw(rscratch1, *stub->entry());
2358 }
2359
2360 // Spill because stubs can use any register they like and it's
2361 // easier to restore just those that we care about.
2362 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2363 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2364 __ str(src, Address(sp, 4*BytesPerWord));
2365
2366 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2367 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2368 assert_different_registers(c_rarg0, dst, dst_pos, length);
2369 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2370 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2371 assert_different_registers(c_rarg1, dst, length);
2372 __ uxtw(c_rarg2, length);
2373 assert_different_registers(c_rarg2, dst);
2374
2375 __ load_klass(c_rarg4, dst);
2376 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2377 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2378 __ far_call(RuntimeAddress(copyfunc_addr));
2379
2380 #ifndef PRODUCT
2381 if (PrintC1Statistics) {
2382 Label failed;
2383 __ cbnz(r0, failed);
2384 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2385 __ bind(failed);
2386 }
2387 #endif
2388
2389 __ cbz(r0, *stub->continuation());
2390
2391 #ifndef PRODUCT
2392 if (PrintC1Statistics) {
2393 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2394 }
2395 #endif
2396 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2397
2398 // Restore previously spilled arguments
2399 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2400 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2401 __ ldr(src, Address(sp, 4*BytesPerWord));
2402
2403 // return value is -1^K where K is partial copied count
2404 __ eonw(rscratch1, r0, zr);
2405 // adjust length down and src/end pos up by partial copied count
2406 __ subw(length, length, rscratch1);
2407 __ addw(src_pos, src_pos, rscratch1);
2408 __ addw(dst_pos, dst_pos, rscratch1);
2409 }
2410
2411 __ b(*stub->entry());
2412
2413 __ bind(cont);
2414 __ POP(src, dst);
2415 }
2416 }
2417
2418 #ifdef ASSERT
2419 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2420 // Sanity check the known type with the incoming class. For the
2421 // primitive case the types must match exactly with src.klass and
2422 // dst.klass each exactly matching the default type. For the
2423 // object array case, if no type check is needed then either the
2424 // dst type is exactly the expected type and the src type is a
2425 // subtype which we can't check or src is the same array as dst
2426 // but not necessarily exactly of type default_type.
2427 Label known_ok, halt;
2428 __ mov_metadata(tmp, default_type->constant_encoding());
2429
2430 if (basic_type != T_OBJECT) {
2431 __ cmp_klass(dst, tmp, rscratch1);
2432 __ br(Assembler::NE, halt);
2433 __ cmp_klass(src, tmp, rscratch1);
2434 __ br(Assembler::EQ, known_ok);
2435 } else {
2436 __ cmp_klass(dst, tmp, rscratch1);
2437 __ br(Assembler::EQ, known_ok);
2438 __ cmp(src, dst);
2439 __ br(Assembler::EQ, known_ok);
2440 }
2441 __ bind(halt);
2442 __ stop("incorrect type information in arraycopy");
2443 __ bind(known_ok);
2444 }
2445 #endif
2446
2447 #ifndef PRODUCT
2448 if (PrintC1Statistics) {
2449 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2450 }
2451 #endif
2452
2453 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2454 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2455 assert_different_registers(c_rarg0, dst, dst_pos, length);
2456 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2457 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2458 assert_different_registers(c_rarg1, dst, length);
2459 __ uxtw(c_rarg2, length);
2460 assert_different_registers(c_rarg2, dst);
2461
2462 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2463 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2464 const char *name;
2465 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2466
2467 CodeBlob *cb = CodeCache::find_blob(entry);
2468 if (cb) {
2469 __ far_call(RuntimeAddress(entry));
2470 } else {
2471 __ call_VM_leaf(entry, 3);
2472 }
2473
2474 if (stub != nullptr) {
2475 __ bind(*stub->continuation());
2476 }
2477 }
2478
2479
2480
2481
2482 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2483 Register obj = op->obj_opr()->as_register(); // may not be an oop
2484 Register hdr = op->hdr_opr()->as_register();
2485 Register lock = op->lock_opr()->as_register();
2486 Register temp = op->scratch_opr()->as_register();
2487 if (op->code() == lir_lock) {
2488 // add debug info for NullPointerException only if one is possible
2489 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2490 if (op->info() != nullptr) {
2491 add_debug_info_for_null_check(null_check_offset, op->info());
2492 }
2493 // done
2494 } else if (op->code() == lir_unlock) {
2495 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2496 } else {
2497 Unimplemented();
2498 }
2499 __ bind(*op->stub()->continuation());
2500 }
2501
2502 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2503 Register obj = op->obj()->as_pointer_register();
2504 Register result = op->result_opr()->as_pointer_register();
2505
2506 CodeEmitInfo* info = op->info();
2507 if (info != nullptr) {
2508 add_debug_info_for_null_check_here(info);
2509 }
2510
2511 __ load_klass(result, obj);
2512 }
2513
2514 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2515 ciMethod* method = op->profiled_method();
2516 int bci = op->profiled_bci();
2517 ciMethod* callee = op->profiled_callee();
2518
2519 // Update counter for all call types
2520 ciMethodData* md = method->method_data_or_null();
2521 assert(md != nullptr, "Sanity");
2522 ciProfileData* data = md->bci_to_data(bci);
2523 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2524 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2525 Register mdo = op->mdo()->as_register();
2526 __ mov_metadata(mdo, md->constant_encoding());
2527 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2528 // Perform additional virtual call profiling for invokevirtual and
2529 // invokeinterface bytecodes
2530 if (op->should_profile_receiver_type()) {
2531 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2532 Register recv = op->recv()->as_register();
2533 assert_different_registers(mdo, recv);
2534 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2535 ciKlass* known_klass = op->known_holder();
2536 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2537 // We know the type that will be seen at this call site; we can
2538 // statically update the MethodData* rather than needing to do
2539 // dynamic tests on the receiver type.
2540 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2541 for (uint i = 0; i < VirtualCallData::row_limit(); i++) {
2542 ciKlass* receiver = vc_data->receiver(i);
2543 if (known_klass->equals(receiver)) {
2544 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2545 __ addptr(data_addr, DataLayout::counter_increment);
2546 return;
2547 }
2548 }
2549 // Receiver type is not found in profile data.
2550 // Fall back to runtime helper to handle the rest at runtime.
2551 __ mov_metadata(recv, known_klass->constant_encoding());
2552 } else {
2553 __ load_klass(recv, recv);
2554 }
2555 type_profile_helper(mdo, md, data, recv);
2556 } else {
2557 // Static call
2558 __ addptr(counter_addr, DataLayout::counter_increment);
2559 }
2560 }
2561
2562
2563 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2564 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2565 }
2566
2567 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2568 assert(op->crc()->is_single_cpu(), "crc must be register");
2569 assert(op->val()->is_single_cpu(), "byte value must be register");
2570 assert(op->result_opr()->is_single_cpu(), "result must be register");
2571 Register crc = op->crc()->as_register();
2572 Register val = op->val()->as_register();
2573 Register res = op->result_opr()->as_register();
2574
2575 assert_different_registers(val, crc, res);
2576 uint64_t offset;
2577 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2578 __ add(res, res, offset);
2579
2580 __ mvnw(crc, crc); // ~crc
2581 __ update_byte_crc32(crc, val, res);
2582 __ mvnw(res, crc); // ~crc
2583 }
2584
2585 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2586 COMMENT("emit_profile_type {");
2587 Register obj = op->obj()->as_register();
2588 Register tmp = op->tmp()->as_pointer_register();
2589 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2590 ciKlass* exact_klass = op->exact_klass();
2591 intptr_t current_klass = op->current_klass();
2592 bool not_null = op->not_null();
2593 bool no_conflict = op->no_conflict();
2594
2595 Label update, next, none;
2596
2597 bool do_null = !not_null;
2598 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2599 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2600
2601 assert(do_null || do_update, "why are we here?");
2602 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2603 assert(mdo_addr.base() != rscratch1, "wrong register");
2604
2605 __ verify_oop(obj);
2606
2607 if (tmp != obj) {
2608 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2609 __ mov(tmp, obj);
2610 } else {
2611 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2612 }
2613 if (do_null) {
2614 __ cbnz(tmp, update);
2615 if (!TypeEntries::was_null_seen(current_klass)) {
2616 __ ldr(rscratch2, mdo_addr);
2617 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2618 __ str(rscratch2, mdo_addr);
2619 }
2620 if (do_update) {
2621 #ifndef ASSERT
2622 __ b(next);
2623 }
2624 #else
2625 __ b(next);
2626 }
2627 } else {
2628 __ cbnz(tmp, update);
2629 __ stop("unexpected null obj");
2630 #endif
2631 }
2632
2633 __ bind(update);
2634
2635 if (do_update) {
2636 #ifdef ASSERT
2637 if (exact_klass != nullptr) {
2638 Label ok;
2639 __ load_klass(tmp, tmp);
2640 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2641 __ eor(rscratch1, tmp, rscratch1);
2642 __ cbz(rscratch1, ok);
2643 __ stop("exact klass and actual klass differ");
2644 __ bind(ok);
2645 }
2646 #endif
2647 if (!no_conflict) {
2648 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2649 if (exact_klass != nullptr) {
2650 __ mov_metadata(tmp, exact_klass->constant_encoding());
2651 } else {
2652 __ load_klass(tmp, tmp);
2653 }
2654
2655 __ ldr(rscratch2, mdo_addr);
2656 __ eor(tmp, tmp, rscratch2);
2657 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2658 // klass seen before, nothing to do. The unknown bit may have been
2659 // set already but no need to check.
2660 __ cbz(rscratch1, next);
2661
2662 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2663
2664 if (TypeEntries::is_type_none(current_klass)) {
2665 __ cbz(rscratch2, none);
2666 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2667 __ br(Assembler::EQ, none);
2668 // There is a chance that the checks above
2669 // fail if another thread has just set the
2670 // profiling to this obj's klass
2671 __ dmb(Assembler::ISHLD);
2672 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2673 __ ldr(rscratch2, mdo_addr);
2674 __ eor(tmp, tmp, rscratch2);
2675 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2676 __ cbz(rscratch1, next);
2677 }
2678 } else {
2679 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2680 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2681
2682 __ ldr(tmp, mdo_addr);
2683 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2684 }
2685
2686 // different than before. Cannot keep accurate profile.
2687 __ ldr(rscratch2, mdo_addr);
2688 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2689 __ str(rscratch2, mdo_addr);
2690
2691 if (TypeEntries::is_type_none(current_klass)) {
2692 __ b(next);
2693
2694 __ bind(none);
2695 // first time here. Set profile type.
2696 __ str(tmp, mdo_addr);
2697 #ifdef ASSERT
2698 __ andr(tmp, tmp, TypeEntries::type_mask);
2699 __ verify_klass_ptr(tmp);
2700 #endif
2701 }
2702 } else {
2703 // There's a single possible klass at this profile point
2704 assert(exact_klass != nullptr, "should be");
2705 if (TypeEntries::is_type_none(current_klass)) {
2706 __ mov_metadata(tmp, exact_klass->constant_encoding());
2707 __ ldr(rscratch2, mdo_addr);
2708 __ eor(tmp, tmp, rscratch2);
2709 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2710 __ cbz(rscratch1, next);
2711 #ifdef ASSERT
2712 {
2713 Label ok;
2714 __ ldr(rscratch1, mdo_addr);
2715 __ cbz(rscratch1, ok);
2716 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2717 __ br(Assembler::EQ, ok);
2718 // may have been set by another thread
2719 __ dmb(Assembler::ISHLD);
2720 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2721 __ ldr(rscratch2, mdo_addr);
2722 __ eor(rscratch2, rscratch1, rscratch2);
2723 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2724 __ cbz(rscratch2, ok);
2725
2726 __ stop("unexpected profiling mismatch");
2727 __ bind(ok);
2728 }
2729 #endif
2730 // first time here. Set profile type.
2731 __ str(tmp, mdo_addr);
2732 #ifdef ASSERT
2733 __ andr(tmp, tmp, TypeEntries::type_mask);
2734 __ verify_klass_ptr(tmp);
2735 #endif
2736 } else {
2737 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2738 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2739
2740 __ ldr(tmp, mdo_addr);
2741 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2742
2743 __ orr(tmp, tmp, TypeEntries::type_unknown);
2744 __ str(tmp, mdo_addr);
2745 // FIXME: Write barrier needed here?
2746 }
2747 }
2748
2749 __ bind(next);
2750 }
2751 COMMENT("} emit_profile_type");
2752 }
2753
2754
2755 void LIR_Assembler::align_backward_branch_target() {
2756 }
2757
2758
2759 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2760 // tmp must be unused
2761 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2762
2763 if (left->is_single_cpu()) {
2764 assert(dest->is_single_cpu(), "expect single result reg");
2765 __ negw(dest->as_register(), left->as_register());
2766 } else if (left->is_double_cpu()) {
2767 assert(dest->is_double_cpu(), "expect double result reg");
2768 __ neg(dest->as_register_lo(), left->as_register_lo());
2769 } else if (left->is_single_fpu()) {
2770 assert(dest->is_single_fpu(), "expect single float result reg");
2771 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2772 } else {
2773 assert(left->is_double_fpu(), "expect double float operand reg");
2774 assert(dest->is_double_fpu(), "expect double float result reg");
2775 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2776 }
2777 }
2778
2779
2780 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2781 if (patch_code != lir_patch_none) {
2782 deoptimize_trap(info);
2783 return;
2784 }
2785
2786 __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
2787 }
2788
2789
2790 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2791 assert(!tmp->is_valid(), "don't need temporary");
2792
2793 CodeBlob *cb = CodeCache::find_blob(dest);
2794 if (cb) {
2795 __ far_call(RuntimeAddress(dest));
2796 } else {
2797 __ mov(rscratch1, RuntimeAddress(dest));
2798 __ blr(rscratch1);
2799 }
2800
2801 if (info != nullptr) {
2802 add_call_info_here(info);
2803 }
2804 __ post_call_nop();
2805 }
2806
2807 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2808 if (src->is_address()) {
2809 mem2reg(src, dest, type, lir_patch_none, info, /*wide*/false, /*is_volatile*/true);
2810 } else if (dest->is_address()) {
2811 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
2812 } else {
2813 ShouldNotReachHere();
2814 }
2815 }
2816
2817 #ifdef ASSERT
2818 // emit run-time assertion
2819 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2820 assert(op->code() == lir_assert, "must be");
2821
2822 if (op->in_opr1()->is_valid()) {
2823 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2824 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2825 } else {
2826 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2827 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2828 }
2829
2830 Label ok;
2831 if (op->condition() != lir_cond_always) {
2832 Assembler::Condition acond = Assembler::AL;
2833 switch (op->condition()) {
2834 case lir_cond_equal: acond = Assembler::EQ; break;
2835 case lir_cond_notEqual: acond = Assembler::NE; break;
2836 case lir_cond_less: acond = Assembler::LT; break;
2837 case lir_cond_lessEqual: acond = Assembler::LE; break;
2838 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2839 case lir_cond_greater: acond = Assembler::GT; break;
2840 case lir_cond_belowEqual: acond = Assembler::LS; break;
2841 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2842 default: ShouldNotReachHere();
2843 }
2844 __ br(acond, ok);
2845 }
2846 if (op->halt()) {
2847 const char* str = __ code_string(op->msg());
2848 __ stop(str);
2849 } else {
2850 breakpoint();
2851 }
2852 __ bind(ok);
2853 }
2854 #endif
2855
2856 #ifndef PRODUCT
2857 #define COMMENT(x) do { __ block_comment(x); } while (0)
2858 #else
2859 #define COMMENT(x)
2860 #endif
2861
2862 void LIR_Assembler::membar() {
2863 COMMENT("membar");
2864 __ membar(MacroAssembler::AnyAny);
2865 }
2866
2867 void LIR_Assembler::membar_acquire() {
2868 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2869 }
2870
2871 void LIR_Assembler::membar_release() {
2872 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2873 }
2874
2875 void LIR_Assembler::membar_loadload() {
2876 __ membar(Assembler::LoadLoad);
2877 }
2878
2879 void LIR_Assembler::membar_storestore() {
2880 __ membar(MacroAssembler::StoreStore);
2881 }
2882
2883 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2884
2885 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2886
2887 void LIR_Assembler::on_spin_wait() {
2888 __ spin_wait();
2889 }
2890
2891 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2892 __ mov(result_reg->as_register(), rthread);
2893 }
2894
2895
2896 void LIR_Assembler::peephole(LIR_List *lir) {
2897 #if 0
2898 if (tableswitch_count >= max_tableswitches)
2899 return;
2900
2901 /*
2902 This finite-state automaton recognizes sequences of compare-and-
2903 branch instructions. We will turn them into a tableswitch. You
2904 could argue that C1 really shouldn't be doing this sort of
2905 optimization, but without it the code is really horrible.
2906 */
2907
2908 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2909 int first_key, last_key = -2147483648;
2910 int next_key = 0;
2911 int start_insn = -1;
2912 int last_insn = -1;
2913 Register reg = noreg;
2914 LIR_Opr reg_opr;
2915 state = start_s;
2916
2917 LIR_OpList* inst = lir->instructions_list();
2918 for (int i = 0; i < inst->length(); i++) {
2919 LIR_Op* op = inst->at(i);
2920 switch (state) {
2921 case start_s:
2922 first_key = -1;
2923 start_insn = i;
2924 switch (op->code()) {
2925 case lir_cmp:
2926 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2927 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2928 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2929 && opr2->is_constant()
2930 && opr2->type() == T_INT) {
2931 reg_opr = opr1;
2932 reg = opr1->as_register();
2933 first_key = opr2->as_constant_ptr()->as_jint();
2934 next_key = first_key + 1;
2935 state = cmp_s;
2936 goto next_state;
2937 }
2938 break;
2939 }
2940 break;
2941 case cmp_s:
2942 switch (op->code()) {
2943 case lir_branch:
2944 if (op->as_OpBranch()->cond() == lir_cond_equal) {
2945 state = beq_s;
2946 last_insn = i;
2947 goto next_state;
2948 }
2949 }
2950 state = start_s;
2951 break;
2952 case beq_s:
2953 switch (op->code()) {
2954 case lir_cmp: {
2955 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2956 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2957 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2958 && opr1->as_register() == reg
2959 && opr2->is_constant()
2960 && opr2->type() == T_INT
2961 && opr2->as_constant_ptr()->as_jint() == next_key) {
2962 last_key = next_key;
2963 next_key++;
2964 state = cmp_s;
2965 goto next_state;
2966 }
2967 }
2968 }
2969 last_key = next_key;
2970 state = start_s;
2971 break;
2972 default:
2973 assert(false, "impossible state");
2974 }
2975 if (state == start_s) {
2976 if (first_key < last_key - 5L && reg != noreg) {
2977 {
2978 // printf("found run register %d starting at insn %d low value %d high value %d\n",
2979 // reg->encoding(),
2980 // start_insn, first_key, last_key);
2981 // for (int i = 0; i < inst->length(); i++) {
2982 // inst->at(i)->print();
2983 // tty->print("\n");
2984 // }
2985 // tty->print("\n");
2986 }
2987
2988 struct tableswitch *sw = &switches[tableswitch_count];
2989 sw->_insn_index = start_insn, sw->_first_key = first_key,
2990 sw->_last_key = last_key, sw->_reg = reg;
2991 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
2992 {
2993 // Insert the new table of branches
2994 int offset = last_insn;
2995 for (int n = first_key; n < last_key; n++) {
2996 inst->insert_before
2997 (last_insn + 1,
2998 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
2999 inst->at(offset)->as_OpBranch()->label()));
3000 offset -= 2, i++;
3001 }
3002 }
3003 // Delete all the old compare-and-branch instructions
3004 for (int n = first_key; n < last_key; n++) {
3005 inst->remove_at(start_insn);
3006 inst->remove_at(start_insn);
3007 }
3008 // Insert the tableswitch instruction
3009 inst->insert_before(start_insn,
3010 new LIR_Op2(lir_cmp, lir_cond_always,
3011 LIR_OprFact::intConst(tableswitch_count),
3012 reg_opr));
3013 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3014 tableswitch_count++;
3015 }
3016 reg = noreg;
3017 last_key = -2147483648;
3018 }
3019 next_state:
3020 ;
3021 }
3022 #endif
3023 }
3024
3025 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3026 Address addr = as_Address(src->as_address_ptr());
3027 BasicType type = src->type();
3028 bool is_oop = is_reference_type(type);
3029
3030 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3031 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3032
3033 switch(type) {
3034 case T_INT:
3035 xchg = &MacroAssembler::atomic_xchgalw;
3036 add = &MacroAssembler::atomic_addalw;
3037 break;
3038 case T_LONG:
3039 xchg = &MacroAssembler::atomic_xchgal;
3040 add = &MacroAssembler::atomic_addal;
3041 break;
3042 case T_OBJECT:
3043 case T_ARRAY:
3044 if (UseCompressedOops) {
3045 xchg = &MacroAssembler::atomic_xchgalw;
3046 add = &MacroAssembler::atomic_addalw;
3047 } else {
3048 xchg = &MacroAssembler::atomic_xchgal;
3049 add = &MacroAssembler::atomic_addal;
3050 }
3051 break;
3052 default:
3053 ShouldNotReachHere();
3054 xchg = &MacroAssembler::atomic_xchgal;
3055 add = &MacroAssembler::atomic_addal; // unreachable
3056 }
3057
3058 switch (code) {
3059 case lir_xadd:
3060 {
3061 RegisterOrConstant inc;
3062 Register tmp = as_reg(tmp_op);
3063 Register dst = as_reg(dest);
3064 if (data->is_constant()) {
3065 inc = RegisterOrConstant(as_long(data));
3066 assert_different_registers(dst, addr.base(), tmp,
3067 rscratch1, rscratch2);
3068 } else {
3069 inc = RegisterOrConstant(as_reg(data));
3070 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3071 rscratch1, rscratch2);
3072 }
3073 __ lea(tmp, addr);
3074 (_masm->*add)(dst, inc, tmp);
3075 break;
3076 }
3077 case lir_xchg:
3078 {
3079 Register tmp = tmp_op->as_register();
3080 Register obj = as_reg(data);
3081 Register dst = as_reg(dest);
3082 if (is_oop && UseCompressedOops) {
3083 __ encode_heap_oop(rscratch2, obj);
3084 obj = rscratch2;
3085 }
3086 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3087 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3088 __ lea(tmp, addr);
3089 (_masm->*xchg)(dst, obj, tmp);
3090 if (is_oop && UseCompressedOops) {
3091 __ decode_heap_oop(dst);
3092 }
3093 }
3094 break;
3095 default:
3096 ShouldNotReachHere();
3097 }
3098 }
3099
3100 #undef __
--- EOF ---