1 /*
   2  * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "asm/assembler.hpp"
  29 #include "c1/c1_CodeStubs.hpp"
  30 #include "c1/c1_Compilation.hpp"
  31 #include "c1/c1_LIRAssembler.hpp"
  32 #include "c1/c1_MacroAssembler.hpp"
  33 #include "c1/c1_Runtime1.hpp"
  34 #include "c1/c1_ValueStack.hpp"
  35 #include "ci/ciArrayKlass.hpp"

  36 #include "ci/ciInstance.hpp"
  37 #include "code/compiledIC.hpp"
  38 #include "gc/shared/collectedHeap.hpp"
  39 #include "gc/shared/gc_globals.hpp"
  40 #include "nativeInst_aarch64.hpp"
  41 #include "oops/objArrayKlass.hpp"

  42 #include "runtime/frame.inline.hpp"
  43 #include "runtime/sharedRuntime.hpp"
  44 #include "runtime/stubRoutines.hpp"
  45 #include "utilities/powerOfTwo.hpp"
  46 #include "vmreg_aarch64.inline.hpp"
  47 
  48 
  49 #ifndef PRODUCT
  50 #define COMMENT(x)   do { __ block_comment(x); } while (0)
  51 #else
  52 #define COMMENT(x)
  53 #endif
  54 
  55 NEEDS_CLEANUP // remove this definitions ?
  56 const Register IC_Klass    = rscratch2;   // where the IC klass is cached
  57 const Register SYNC_header = r0;   // synchronization header
  58 const Register SHIFT_count = r0;   // where count for shift operations must be
  59 
  60 #define __ _masm->
  61 
  62 
  63 static void select_different_registers(Register preserve,
  64                                        Register extra,
  65                                        Register &tmp1,
  66                                        Register &tmp2) {
  67   if (tmp1 == preserve) {
  68     assert_different_registers(tmp1, tmp2, extra);
  69     tmp1 = extra;
  70   } else if (tmp2 == preserve) {
  71     assert_different_registers(tmp1, tmp2, extra);
  72     tmp2 = extra;
  73   }
  74   assert_different_registers(preserve, tmp1, tmp2);
  75 }
  76 
  77 
  78 
  79 static void select_different_registers(Register preserve,
  80                                        Register extra,
  81                                        Register &tmp1,
  82                                        Register &tmp2,
  83                                        Register &tmp3) {
  84   if (tmp1 == preserve) {
  85     assert_different_registers(tmp1, tmp2, tmp3, extra);
  86     tmp1 = extra;
  87   } else if (tmp2 == preserve) {
  88     assert_different_registers(tmp1, tmp2, tmp3, extra);
  89     tmp2 = extra;
  90   } else if (tmp3 == preserve) {
  91     assert_different_registers(tmp1, tmp2, tmp3, extra);
  92     tmp3 = extra;
  93   }
  94   assert_different_registers(preserve, tmp1, tmp2, tmp3);
  95 }
  96 
  97 
  98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
  99 
 100 
 101 LIR_Opr LIR_Assembler::receiverOpr() {
 102   return FrameMap::receiver_opr;
 103 }
 104 
 105 LIR_Opr LIR_Assembler::osrBufferPointer() {
 106   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 107 }
 108 
 109 //--------------fpu register translations-----------------------
 110 
 111 
 112 address LIR_Assembler::float_constant(float f) {
 113   address const_addr = __ float_constant(f);
 114   if (const_addr == NULL) {
 115     bailout("const section overflow");
 116     return __ code()->consts()->start();
 117   } else {
 118     return const_addr;
 119   }
 120 }
 121 
 122 
 123 address LIR_Assembler::double_constant(double d) {
 124   address const_addr = __ double_constant(d);
 125   if (const_addr == NULL) {
 126     bailout("const section overflow");
 127     return __ code()->consts()->start();
 128   } else {
 129     return const_addr;
 130   }
 131 }
 132 
 133 address LIR_Assembler::int_constant(jlong n) {
 134   address const_addr = __ long_constant(n);
 135   if (const_addr == NULL) {
 136     bailout("const section overflow");
 137     return __ code()->consts()->start();
 138   } else {
 139     return const_addr;
 140   }
 141 }
 142 
 143 void LIR_Assembler::breakpoint() { Unimplemented(); }
 144 
 145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
 146 
 147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
 148 
 149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
 150 //-------------------------------------------
 151 
 152 static Register as_reg(LIR_Opr op) {
 153   return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
 154 }
 155 
 156 static jlong as_long(LIR_Opr data) {
 157   jlong result;
 158   switch (data->type()) {
 159   case T_INT:
 160     result = (data->as_jint());
 161     break;
 162   case T_LONG:
 163     result = (data->as_jlong());
 164     break;
 165   default:
 166     ShouldNotReachHere();
 167     result = 0;  // unreachable
 168   }
 169   return result;
 170 }
 171 
 172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 173   Register base = addr->base()->as_pointer_register();
 174   LIR_Opr opr = addr->index();
 175   if (opr->is_cpu_register()) {
 176     Register index;
 177     if (opr->is_single_cpu())
 178       index = opr->as_register();
 179     else
 180       index = opr->as_register_lo();
 181     assert(addr->disp() == 0, "must be");
 182     switch(opr->type()) {
 183       case T_INT:
 184         return Address(base, index, Address::sxtw(addr->scale()));
 185       case T_LONG:
 186         return Address(base, index, Address::lsl(addr->scale()));
 187       default:
 188         ShouldNotReachHere();
 189       }
 190   } else  {
 191     intptr_t addr_offset = intptr_t(addr->disp());
 192     if (Address::offset_ok_for_immed(addr_offset, addr->scale()))
 193       return Address(base, addr_offset, Address::lsl(addr->scale()));
 194     else {
 195       __ mov(tmp, addr_offset);
 196       return Address(base, tmp, Address::lsl(addr->scale()));
 197     }
 198   }
 199   return Address();
 200 }
 201 
 202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 203   ShouldNotReachHere();
 204   return Address();
 205 }
 206 
 207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 208   return as_Address(addr, rscratch1);
 209 }
 210 
 211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 212   return as_Address(addr, rscratch1);  // Ouch
 213   // FIXME: This needs to be much more clever.  See x86.
 214 }
 215 
 216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
 217 // not encodable as a base + (immediate) offset, generate an explicit address
 218 // calculation to hold the address in a temporary register.
 219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
 220   precond(size == 4 || size == 8);
 221   Address addr = frame_map()->address_for_slot(index, adjust);
 222   precond(addr.getMode() == Address::base_plus_offset);
 223   precond(addr.base() == sp);
 224   precond(addr.offset() > 0);
 225   uint mask = size - 1;
 226   assert((addr.offset() & mask) == 0, "scaled offsets only");
 227   return __ legitimize_address(addr, size, tmp);
 228 }
 229 
 230 void LIR_Assembler::osr_entry() {
 231   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 232   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 233   ValueStack* entry_state = osr_entry->state();
 234   int number_of_locks = entry_state->locks_size();
 235 
 236   // we jump here if osr happens with the interpreter
 237   // state set up to continue at the beginning of the
 238   // loop that triggered osr - in particular, we have
 239   // the following registers setup:
 240   //
 241   // r2: osr buffer
 242   //
 243 
 244   // build frame
 245   ciMethod* m = compilation()->method();
 246   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 247 
 248   // OSR buffer is
 249   //
 250   // locals[nlocals-1..0]
 251   // monitors[0..number_of_locks]
 252   //
 253   // locals is a direct copy of the interpreter frame so in the osr buffer
 254   // so first slot in the local array is the last local from the interpreter
 255   // and last slot is local[0] (receiver) from the interpreter
 256   //
 257   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 258   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 259   // in the interpreter frame (the method lock if a sync method)
 260 
 261   // Initialize monitors in the compiled activation.
 262   //   r2: pointer to osr buffer
 263   //
 264   // All other registers are dead at this point and the locals will be
 265   // copied into place by code emitted in the IR.
 266 
 267   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 268   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 269     int monitor_offset = BytesPerWord * method()->max_locals() +
 270       (2 * BytesPerWord) * (number_of_locks - 1);
 271     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 272     // the OSR buffer using 2 word entries: first the lock and then
 273     // the oop.
 274     for (int i = 0; i < number_of_locks; i++) {
 275       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 276 #ifdef ASSERT
 277       // verify the interpreter's monitor has a non-null object
 278       {
 279         Label L;
 280         __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 281         __ cbnz(rscratch1, L);
 282         __ stop("locked object is NULL");
 283         __ bind(L);
 284       }
 285 #endif
 286       __ ldr(r19, Address(OSR_buf, slot_offset + 0));
 287       __ str(r19, frame_map()->address_for_monitor_lock(i));
 288       __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 289       __ str(r19, frame_map()->address_for_monitor_object(i));
 290     }
 291   }
 292 }
 293 
 294 
 295 // inline cache check; done before the frame is built.
 296 int LIR_Assembler::check_icache() {
 297   Register receiver = FrameMap::receiver_opr->as_register();
 298   Register ic_klass = IC_Klass;
 299   int start_offset = __ offset();
 300   __ inline_cache_check(receiver, ic_klass);
 301 
 302   // if icache check fails, then jump to runtime routine
 303   // Note: RECEIVER must still contain the receiver!
 304   Label dont;
 305   __ br(Assembler::EQ, dont);
 306   __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 307 
 308   // We align the verified entry point unless the method body
 309   // (including its inline cache check) will fit in a single 64-byte
 310   // icache line.
 311   if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
 312     // force alignment after the cache check.
 313     __ align(CodeEntryAlignment);
 314   }
 315 
 316   __ bind(dont);
 317   return start_offset;
 318 }
 319 
 320 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 321   assert(VM_Version::supports_fast_class_init_checks(), "sanity");
 322   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
 323 
 324   Label L_skip_barrier;
 325 
 326   __ mov_metadata(rscratch2, method->holder()->constant_encoding());
 327   __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
 328   __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 329   __ bind(L_skip_barrier);
 330 }
 331 
 332 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 333   if (o == NULL) {
 334     __ mov(reg, zr);
 335   } else {
 336     __ movoop(reg, o, /*immediate*/true);
 337   }
 338 }
 339 
 340 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
 341   address target = NULL;
 342   relocInfo::relocType reloc_type = relocInfo::none;
 343 
 344   switch (patching_id(info)) {
 345   case PatchingStub::access_field_id:
 346     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 347     reloc_type = relocInfo::section_word_type;
 348     break;
 349   case PatchingStub::load_klass_id:
 350     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 351     reloc_type = relocInfo::metadata_type;
 352     break;
 353   case PatchingStub::load_mirror_id:
 354     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 355     reloc_type = relocInfo::oop_type;
 356     break;
 357   case PatchingStub::load_appendix_id:
 358     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 359     reloc_type = relocInfo::oop_type;
 360     break;
 361   default: ShouldNotReachHere();
 362   }
 363 
 364   __ far_call(RuntimeAddress(target));
 365   add_call_info_here(info);
 366 }
 367 
 368 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 369   deoptimize_trap(info);
 370 }
 371 
 372 
 373 // This specifies the rsp decrement needed to build the frame
 374 int LIR_Assembler::initial_frame_size_in_bytes() const {
 375   // if rounding, must let FrameMap know!
 376 
 377   return in_bytes(frame_map()->framesize_in_bytes());
 378 }
 379 
 380 
 381 int LIR_Assembler::emit_exception_handler() {
 382   // if the last instruction is a call (typically to do a throw which
 383   // is coming at the end after block reordering) the return address
 384   // must still point into the code area in order to avoid assertion
 385   // failures when searching for the corresponding bci => add a nop
 386   // (was bug 5/14/1999 - gri)
 387   __ nop();
 388 
 389   // generate code for exception handler
 390   address handler_base = __ start_a_stub(exception_handler_size());
 391   if (handler_base == NULL) {
 392     // not enough space left for the handler
 393     bailout("exception handler overflow");
 394     return -1;
 395   }
 396 
 397   int offset = code_offset();
 398 
 399   // the exception oop and pc are in r0, and r3
 400   // no other registers need to be preserved, so invalidate them
 401   __ invalidate_registers(false, true, true, false, true, true);
 402 
 403   // check that there is really an exception
 404   __ verify_not_null_oop(r0);
 405 
 406   // search an exception handler (r0: exception oop, r3: throwing pc)
 407   __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));  __ should_not_reach_here();
 408   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 409   __ end_a_stub();
 410 
 411   return offset;
 412 }
 413 
 414 
 415 // Emit the code to remove the frame from the stack in the exception
 416 // unwind path.
 417 int LIR_Assembler::emit_unwind_handler() {
 418 #ifndef PRODUCT
 419   if (CommentedAssembly) {
 420     _masm->block_comment("Unwind handler");
 421   }
 422 #endif
 423 
 424   int offset = code_offset();
 425 
 426   // Fetch the exception from TLS and clear out exception related thread state
 427   __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
 428   __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
 429   __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
 430 
 431   __ bind(_unwind_handler_entry);
 432   __ verify_not_null_oop(r0);
 433   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 434     __ mov(r19, r0);  // Preserve the exception
 435   }
 436 
 437   // Preform needed unlocking
 438   MonitorExitStub* stub = NULL;
 439   if (method()->is_synchronized()) {
 440     monitor_address(0, FrameMap::r0_opr);
 441     stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
 442     __ unlock_object(r5, r4, r0, *stub->entry());
 443     __ bind(*stub->continuation());
 444   }
 445 
 446   if (compilation()->env()->dtrace_method_probes()) {
 447     __ mov(c_rarg0, rthread);
 448     __ mov_metadata(c_rarg1, method()->constant_encoding());
 449     __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
 450   }
 451 
 452   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 453     __ mov(r0, r19);  // Restore the exception
 454   }
 455 
 456   // remove the activation and dispatch to the unwind handler
 457   __ block_comment("remove_frame and dispatch to the unwind handler");
 458   __ remove_frame(initial_frame_size_in_bytes());
 459   __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 460 
 461   // Emit the slow path assembly
 462   if (stub != NULL) {
 463     stub->emit_code(this);
 464   }
 465 
 466   return offset;
 467 }
 468 
 469 
 470 int LIR_Assembler::emit_deopt_handler() {
 471   // if the last instruction is a call (typically to do a throw which
 472   // is coming at the end after block reordering) the return address
 473   // must still point into the code area in order to avoid assertion
 474   // failures when searching for the corresponding bci => add a nop
 475   // (was bug 5/14/1999 - gri)
 476   __ nop();
 477 
 478   // generate code for exception handler
 479   address handler_base = __ start_a_stub(deopt_handler_size());
 480   if (handler_base == NULL) {
 481     // not enough space left for the handler
 482     bailout("deopt handler overflow");
 483     return -1;
 484   }
 485 
 486   int offset = code_offset();
 487 
 488   __ adr(lr, pc());
 489   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 490   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 491   __ end_a_stub();
 492 
 493   return offset;
 494 }
 495 
 496 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
 497   _masm->code_section()->relocate(adr, relocInfo::poll_type);
 498   int pc_offset = code_offset();
 499   flush_debug_info(pc_offset);
 500   info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
 501   if (info->exception_handlers() != NULL) {
 502     compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
 503   }
 504 }
 505 
 506 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
 507   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
 508 












 509   // Pop the stack before the safepoint code
 510   __ remove_frame(initial_frame_size_in_bytes());
 511 
 512   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 513     __ reserved_stack_check();
 514   }
 515 
 516   code_stub->set_safepoint_offset(__ offset());
 517   __ relocate(relocInfo::poll_return_type);
 518   __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
 519   __ ret(lr);
 520 }
 521 




 522 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 523   guarantee(info != NULL, "Shouldn't be NULL");
 524   __ get_polling_page(rscratch1, relocInfo::poll_type);
 525   add_debug_info_for_branch(info);  // This isn't just debug info:
 526                                     // it's the oop map
 527   __ read_polling_page(rscratch1, relocInfo::poll_type);
 528   return __ offset();
 529 }
 530 
 531 
 532 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 533   if (from_reg == r31_sp)
 534     from_reg = sp;
 535   if (to_reg == r31_sp)
 536     to_reg = sp;
 537   __ mov(to_reg, from_reg);
 538 }
 539 
 540 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
 541 
 542 
 543 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 544   assert(src->is_constant(), "should not call otherwise");
 545   assert(dest->is_register(), "should not call otherwise");
 546   LIR_Const* c = src->as_constant_ptr();
 547 
 548   switch (c->type()) {
 549     case T_INT: {
 550       assert(patch_code == lir_patch_none, "no patching handled here");
 551       __ movw(dest->as_register(), c->as_jint());
 552       break;
 553     }
 554 
 555     case T_ADDRESS: {
 556       assert(patch_code == lir_patch_none, "no patching handled here");
 557       __ mov(dest->as_register(), c->as_jint());
 558       break;
 559     }
 560 
 561     case T_LONG: {
 562       assert(patch_code == lir_patch_none, "no patching handled here");
 563       __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
 564       break;
 565     }
 566 

 567     case T_OBJECT: {
 568         if (patch_code == lir_patch_none) {
 569           jobject2reg(c->as_jobject(), dest->as_register());
 570         } else {
 571           jobject2reg_with_patching(dest->as_register(), info);


 572         }
 573       break;
 574     }
 575 
 576     case T_METADATA: {
 577       if (patch_code != lir_patch_none) {
 578         klass2reg_with_patching(dest->as_register(), info);
 579       } else {
 580         __ mov_metadata(dest->as_register(), c->as_metadata());
 581       }
 582       break;
 583     }
 584 
 585     case T_FLOAT: {
 586       if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
 587         __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
 588       } else {
 589         __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
 590         __ ldrs(dest->as_float_reg(), Address(rscratch1));
 591       }
 592       break;
 593     }
 594 
 595     case T_DOUBLE: {
 596       if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
 597         __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
 598       } else {
 599         __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
 600         __ ldrd(dest->as_double_reg(), Address(rscratch1));
 601       }
 602       break;
 603     }
 604 
 605     default:
 606       ShouldNotReachHere();
 607   }
 608 }
 609 
 610 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 611   LIR_Const* c = src->as_constant_ptr();
 612   switch (c->type()) {

 613   case T_OBJECT:
 614     {
 615       if (! c->as_jobject())
 616         __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 617       else {
 618         const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 619         reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 620       }
 621     }
 622     break;
 623   case T_ADDRESS:
 624     {
 625       const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 626       reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 627     }
 628   case T_INT:
 629   case T_FLOAT:
 630     {
 631       Register reg = zr;
 632       if (c->as_jint_bits() == 0)
 633         __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 634       else {
 635         __ movw(rscratch1, c->as_jint_bits());
 636         __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
 637       }
 638     }
 639     break;
 640   case T_LONG:
 641   case T_DOUBLE:
 642     {
 643       Register reg = zr;
 644       if (c->as_jlong_bits() == 0)
 645         __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
 646                                                  lo_word_offset_in_bytes));
 647       else {
 648         __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
 649         __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
 650                                                         lo_word_offset_in_bytes));
 651       }
 652     }
 653     break;
 654   default:
 655     ShouldNotReachHere();
 656   }
 657 }
 658 
 659 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 660   assert(src->is_constant(), "should not call otherwise");
 661   LIR_Const* c = src->as_constant_ptr();
 662   LIR_Address* to_addr = dest->as_address_ptr();
 663 
 664   void (Assembler::* insn)(Register Rt, const Address &adr);
 665 
 666   switch (type) {
 667   case T_ADDRESS:
 668     assert(c->as_jint() == 0, "should be");
 669     insn = &Assembler::str;
 670     break;
 671   case T_LONG:
 672     assert(c->as_jlong() == 0, "should be");
 673     insn = &Assembler::str;
 674     break;
 675   case T_INT:
 676     assert(c->as_jint() == 0, "should be");
 677     insn = &Assembler::strw;
 678     break;

 679   case T_OBJECT:
 680   case T_ARRAY:


 681     assert(c->as_jobject() == 0, "should be");
 682     if (UseCompressedOops && !wide) {
 683       insn = &Assembler::strw;
 684     } else {
 685       insn = &Assembler::str;
 686     }
 687     break;
 688   case T_CHAR:
 689   case T_SHORT:
 690     assert(c->as_jint() == 0, "should be");
 691     insn = &Assembler::strh;
 692     break;
 693   case T_BOOLEAN:
 694   case T_BYTE:
 695     assert(c->as_jint() == 0, "should be");
 696     insn = &Assembler::strb;
 697     break;
 698   default:
 699     ShouldNotReachHere();
 700     insn = &Assembler::str;  // unreachable
 701   }
 702 
 703   if (info) add_debug_info_for_null_check_here(info);
 704   (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
 705 }
 706 
 707 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 708   assert(src->is_register(), "should not call otherwise");
 709   assert(dest->is_register(), "should not call otherwise");
 710 
 711   // move between cpu-registers
 712   if (dest->is_single_cpu()) {
 713     if (src->type() == T_LONG) {
 714       // Can do LONG -> OBJECT
 715       move_regs(src->as_register_lo(), dest->as_register());
 716       return;
 717     }
 718     assert(src->is_single_cpu(), "must match");
 719     if (src->type() == T_OBJECT) {
 720       __ verify_oop(src->as_register());
 721     }
 722     move_regs(src->as_register(), dest->as_register());
 723 
 724   } else if (dest->is_double_cpu()) {
 725     if (is_reference_type(src->type())) {
 726       // Surprising to me but we can see move of a long to t_object
 727       __ verify_oop(src->as_register());
 728       move_regs(src->as_register(), dest->as_register_lo());
 729       return;
 730     }
 731     assert(src->is_double_cpu(), "must match");
 732     Register f_lo = src->as_register_lo();
 733     Register f_hi = src->as_register_hi();
 734     Register t_lo = dest->as_register_lo();
 735     Register t_hi = dest->as_register_hi();
 736     assert(f_hi == f_lo, "must be same");
 737     assert(t_hi == t_lo, "must be same");
 738     move_regs(f_lo, t_lo);
 739 
 740   } else if (dest->is_single_fpu()) {
 741     __ fmovs(dest->as_float_reg(), src->as_float_reg());
 742 
 743   } else if (dest->is_double_fpu()) {
 744     __ fmovd(dest->as_double_reg(), src->as_double_reg());
 745 
 746   } else {
 747     ShouldNotReachHere();
 748   }
 749 }
 750 
 751 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 752   precond(src->is_register() && dest->is_stack());
 753 
 754   uint const c_sz32 = sizeof(uint32_t);
 755   uint const c_sz64 = sizeof(uint64_t);
 756 
 757   if (src->is_single_cpu()) {
 758     int index = dest->single_stack_ix();
 759     if (is_reference_type(type)) {
 760       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 761       __ verify_oop(src->as_register());
 762     } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
 763       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 764     } else {
 765       __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 766     }
 767 
 768   } else if (src->is_double_cpu()) {
 769     int index = dest->double_stack_ix();
 770     Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 771     __ str(src->as_register_lo(), dest_addr_LO);
 772 
 773   } else if (src->is_single_fpu()) {
 774     int index = dest->single_stack_ix();
 775     __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 776 
 777   } else if (src->is_double_fpu()) {
 778     int index = dest->double_stack_ix();
 779     __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 780 
 781   } else {
 782     ShouldNotReachHere();
 783   }
 784 }
 785 
 786 
 787 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
 788   LIR_Address* to_addr = dest->as_address_ptr();
 789   PatchingStub* patch = NULL;
 790   Register compressed_src = rscratch1;
 791 
 792   if (patch_code != lir_patch_none) {
 793     deoptimize_trap(info);
 794     return;
 795   }
 796 
 797   if (is_reference_type(type)) {
 798     __ verify_oop(src->as_register());
 799 
 800     if (UseCompressedOops && !wide) {
 801       __ encode_heap_oop(compressed_src, src->as_register());
 802     } else {
 803       compressed_src = src->as_register();
 804     }
 805   }
 806 
 807   int null_check_here = code_offset();
 808   switch (type) {
 809     case T_FLOAT: {
 810       __ strs(src->as_float_reg(), as_Address(to_addr));
 811       break;
 812     }
 813 
 814     case T_DOUBLE: {
 815       __ strd(src->as_double_reg(), as_Address(to_addr));
 816       break;
 817     }
 818 

 819     case T_ARRAY:   // fall through
 820     case T_OBJECT:  // fall through
 821       if (UseCompressedOops && !wide) {
 822         __ strw(compressed_src, as_Address(to_addr, rscratch2));
 823       } else {
 824          __ str(compressed_src, as_Address(to_addr));
 825       }
 826       break;
 827     case T_METADATA:
 828       // We get here to store a method pointer to the stack to pass to
 829       // a dtrace runtime call. This can't work on 64 bit with
 830       // compressed klass ptrs: T_METADATA can be a compressed klass
 831       // ptr or a 64 bit method pointer.
 832       ShouldNotReachHere();
 833       __ str(src->as_register(), as_Address(to_addr));
 834       break;
 835     case T_ADDRESS:
 836       __ str(src->as_register(), as_Address(to_addr));
 837       break;
 838     case T_INT:
 839       __ strw(src->as_register(), as_Address(to_addr));
 840       break;
 841 
 842     case T_LONG: {
 843       __ str(src->as_register_lo(), as_Address_lo(to_addr));
 844       break;
 845     }
 846 
 847     case T_BYTE:    // fall through
 848     case T_BOOLEAN: {
 849       __ strb(src->as_register(), as_Address(to_addr));
 850       break;
 851     }
 852 
 853     case T_CHAR:    // fall through
 854     case T_SHORT:
 855       __ strh(src->as_register(), as_Address(to_addr));
 856       break;
 857 
 858     default:
 859       ShouldNotReachHere();
 860   }
 861   if (info != NULL) {
 862     add_debug_info_for_null_check(null_check_here, info);
 863   }
 864 }
 865 
 866 
 867 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
 868   precond(src->is_stack() && dest->is_register());
 869 
 870   uint const c_sz32 = sizeof(uint32_t);
 871   uint const c_sz64 = sizeof(uint64_t);
 872 
 873   if (dest->is_single_cpu()) {
 874     int index = src->single_stack_ix();
 875     if (is_reference_type(type)) {
 876       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 877       __ verify_oop(dest->as_register());
 878     } else if (type == T_METADATA || type == T_ADDRESS) {
 879       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 880     } else {
 881       __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 882     }
 883 
 884   } else if (dest->is_double_cpu()) {
 885     int index = src->double_stack_ix();
 886     Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 887     __ ldr(dest->as_register_lo(), src_addr_LO);
 888 
 889   } else if (dest->is_single_fpu()) {
 890     int index = src->single_stack_ix();
 891     __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 892 
 893   } else if (dest->is_double_fpu()) {
 894     int index = src->double_stack_ix();
 895     __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 896 
 897   } else {
 898     ShouldNotReachHere();
 899   }
 900 }
 901 
 902 
 903 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 904   address target = NULL;
 905   relocInfo::relocType reloc_type = relocInfo::none;
 906 
 907   switch (patching_id(info)) {
 908   case PatchingStub::access_field_id:
 909     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 910     reloc_type = relocInfo::section_word_type;
 911     break;
 912   case PatchingStub::load_klass_id:
 913     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 914     reloc_type = relocInfo::metadata_type;
 915     break;
 916   case PatchingStub::load_mirror_id:
 917     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 918     reloc_type = relocInfo::oop_type;
 919     break;
 920   case PatchingStub::load_appendix_id:
 921     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 922     reloc_type = relocInfo::oop_type;
 923     break;
 924   default: ShouldNotReachHere();
 925   }
 926 
 927   __ far_call(RuntimeAddress(target));
 928   add_call_info_here(info);
 929 }
 930 
 931 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 932 
 933   LIR_Opr temp;
 934   if (type == T_LONG || type == T_DOUBLE)
 935     temp = FrameMap::rscratch1_long_opr;
 936   else
 937     temp = FrameMap::rscratch1_opr;
 938 
 939   stack2reg(src, temp, src->type());
 940   reg2stack(temp, dest, dest->type(), false);
 941 }
 942 
 943 
 944 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
 945   LIR_Address* addr = src->as_address_ptr();
 946   LIR_Address* from_addr = src->as_address_ptr();
 947 
 948   if (addr->base()->type() == T_OBJECT) {
 949     __ verify_oop(addr->base()->as_pointer_register());
 950   }
 951 
 952   if (patch_code != lir_patch_none) {
 953     deoptimize_trap(info);
 954     return;
 955   }
 956 
 957   if (info != NULL) {
 958     add_debug_info_for_null_check_here(info);
 959   }
 960   int null_check_here = code_offset();
 961   switch (type) {
 962     case T_FLOAT: {
 963       __ ldrs(dest->as_float_reg(), as_Address(from_addr));
 964       break;
 965     }
 966 
 967     case T_DOUBLE: {
 968       __ ldrd(dest->as_double_reg(), as_Address(from_addr));
 969       break;
 970     }
 971 

 972     case T_ARRAY:   // fall through
 973     case T_OBJECT:  // fall through
 974       if (UseCompressedOops && !wide) {
 975         __ ldrw(dest->as_register(), as_Address(from_addr));
 976       } else {
 977          __ ldr(dest->as_register(), as_Address(from_addr));
 978       }
 979       break;
 980     case T_METADATA:
 981       // We get here to store a method pointer to the stack to pass to
 982       // a dtrace runtime call. This can't work on 64 bit with
 983       // compressed klass ptrs: T_METADATA can be a compressed klass
 984       // ptr or a 64 bit method pointer.
 985       ShouldNotReachHere();
 986       __ ldr(dest->as_register(), as_Address(from_addr));
 987       break;
 988     case T_ADDRESS:
 989       // FIXME: OMG this is a horrible kludge.  Any offset from an
 990       // address that matches klass_offset_in_bytes() will be loaded
 991       // as a word, not a long.
 992       if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
 993         __ ldrw(dest->as_register(), as_Address(from_addr));
 994       } else {
 995         __ ldr(dest->as_register(), as_Address(from_addr));
 996       }
 997       break;
 998     case T_INT:
 999       __ ldrw(dest->as_register(), as_Address(from_addr));
1000       break;
1001 
1002     case T_LONG: {
1003       __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1004       break;
1005     }
1006 
1007     case T_BYTE:
1008       __ ldrsb(dest->as_register(), as_Address(from_addr));
1009       break;
1010     case T_BOOLEAN: {
1011       __ ldrb(dest->as_register(), as_Address(from_addr));
1012       break;
1013     }
1014 
1015     case T_CHAR:
1016       __ ldrh(dest->as_register(), as_Address(from_addr));
1017       break;
1018     case T_SHORT:
1019       __ ldrsh(dest->as_register(), as_Address(from_addr));
1020       break;
1021 
1022     default:
1023       ShouldNotReachHere();
1024   }
1025 
1026   if (is_reference_type(type)) {
1027     if (UseCompressedOops && !wide) {
1028       __ decode_heap_oop(dest->as_register());
1029     }
1030 
1031     if (!UseZGC) {
1032       // Load barrier has not yet been applied, so ZGC can't verify the oop here
1033       __ verify_oop(dest->as_register());
1034     }
1035   } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1036     if (UseCompressedClassPointers) {
1037       __ decode_klass_not_null(dest->as_register());
1038     }
1039   }
1040 }
1041 














1042 
1043 int LIR_Assembler::array_element_size(BasicType type) const {
1044   int elem_size = type2aelembytes(type);
1045   return exact_log2(elem_size);
1046 }
1047 
1048 
1049 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1050   switch (op->code()) {
1051   case lir_idiv:
1052   case lir_irem:
1053     arithmetic_idiv(op->code(),
1054                     op->in_opr1(),
1055                     op->in_opr2(),
1056                     op->in_opr3(),
1057                     op->result_opr(),
1058                     op->info());
1059     break;
1060   case lir_fmad:
1061     __ fmaddd(op->result_opr()->as_double_reg(),
1062               op->in_opr1()->as_double_reg(),
1063               op->in_opr2()->as_double_reg(),
1064               op->in_opr3()->as_double_reg());
1065     break;
1066   case lir_fmaf:
1067     __ fmadds(op->result_opr()->as_float_reg(),
1068               op->in_opr1()->as_float_reg(),
1069               op->in_opr2()->as_float_reg(),
1070               op->in_opr3()->as_float_reg());
1071     break;
1072   default:      ShouldNotReachHere(); break;
1073   }
1074 }
1075 
1076 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1077 #ifdef ASSERT
1078   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1079   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1080   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1081 #endif
1082 
1083   if (op->cond() == lir_cond_always) {
1084     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1085     __ b(*(op->label()));
1086   } else {
1087     Assembler::Condition acond;
1088     if (op->code() == lir_cond_float_branch) {
1089       bool is_unordered = (op->ublock() == op->block());
1090       // Assembler::EQ does not permit unordered branches, so we add
1091       // another branch here.  Likewise, Assembler::NE does not permit
1092       // ordered branches.
1093       if ((is_unordered && op->cond() == lir_cond_equal)
1094           || (!is_unordered && op->cond() == lir_cond_notEqual))
1095         __ br(Assembler::VS, *(op->ublock()->label()));
1096       switch(op->cond()) {
1097       case lir_cond_equal:        acond = Assembler::EQ; break;
1098       case lir_cond_notEqual:     acond = Assembler::NE; break;
1099       case lir_cond_less:         acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1100       case lir_cond_lessEqual:    acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1101       case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1102       case lir_cond_greater:      acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1103       default:                    ShouldNotReachHere();
1104         acond = Assembler::EQ;  // unreachable
1105       }
1106     } else {
1107       switch (op->cond()) {
1108         case lir_cond_equal:        acond = Assembler::EQ; break;
1109         case lir_cond_notEqual:     acond = Assembler::NE; break;
1110         case lir_cond_less:         acond = Assembler::LT; break;
1111         case lir_cond_lessEqual:    acond = Assembler::LE; break;
1112         case lir_cond_greaterEqual: acond = Assembler::GE; break;
1113         case lir_cond_greater:      acond = Assembler::GT; break;
1114         case lir_cond_belowEqual:   acond = Assembler::LS; break;
1115         case lir_cond_aboveEqual:   acond = Assembler::HS; break;
1116         default:                    ShouldNotReachHere();
1117           acond = Assembler::EQ;  // unreachable
1118       }
1119     }
1120     __ br(acond,*(op->label()));
1121   }
1122 }
1123 
1124 
1125 
1126 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1127   LIR_Opr src  = op->in_opr();
1128   LIR_Opr dest = op->result_opr();
1129 
1130   switch (op->bytecode()) {
1131     case Bytecodes::_i2f:
1132       {
1133         __ scvtfws(dest->as_float_reg(), src->as_register());
1134         break;
1135       }
1136     case Bytecodes::_i2d:
1137       {
1138         __ scvtfwd(dest->as_double_reg(), src->as_register());
1139         break;
1140       }
1141     case Bytecodes::_l2d:
1142       {
1143         __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1144         break;
1145       }
1146     case Bytecodes::_l2f:
1147       {
1148         __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1149         break;
1150       }
1151     case Bytecodes::_f2d:
1152       {
1153         __ fcvts(dest->as_double_reg(), src->as_float_reg());
1154         break;
1155       }
1156     case Bytecodes::_d2f:
1157       {
1158         __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1159         break;
1160       }
1161     case Bytecodes::_i2c:
1162       {
1163         __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1164         break;
1165       }
1166     case Bytecodes::_i2l:
1167       {
1168         __ sxtw(dest->as_register_lo(), src->as_register());
1169         break;
1170       }
1171     case Bytecodes::_i2s:
1172       {
1173         __ sxth(dest->as_register(), src->as_register());
1174         break;
1175       }
1176     case Bytecodes::_i2b:
1177       {
1178         __ sxtb(dest->as_register(), src->as_register());
1179         break;
1180       }
1181     case Bytecodes::_l2i:
1182       {
1183         _masm->block_comment("FIXME: This could be a no-op");
1184         __ uxtw(dest->as_register(), src->as_register_lo());
1185         break;
1186       }
1187     case Bytecodes::_d2l:
1188       {
1189         __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1190         break;
1191       }
1192     case Bytecodes::_f2i:
1193       {
1194         __ fcvtzsw(dest->as_register(), src->as_float_reg());
1195         break;
1196       }
1197     case Bytecodes::_f2l:
1198       {
1199         __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1200         break;
1201       }
1202     case Bytecodes::_d2i:
1203       {
1204         __ fcvtzdw(dest->as_register(), src->as_double_reg());
1205         break;
1206       }
1207     default: ShouldNotReachHere();
1208   }
1209 }
1210 
1211 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1212   if (op->init_check()) {
1213     __ ldrb(rscratch1, Address(op->klass()->as_register(),
1214                                InstanceKlass::init_state_offset()));
1215     __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1216     add_debug_info_for_null_check_here(op->stub()->info());
1217     __ br(Assembler::NE, *op->stub()->entry());
1218   }
1219   __ allocate_object(op->obj()->as_register(),
1220                      op->tmp1()->as_register(),
1221                      op->tmp2()->as_register(),
1222                      op->header_size(),
1223                      op->object_size(),
1224                      op->klass()->as_register(),
1225                      *op->stub()->entry());
1226   __ bind(*op->stub()->continuation());
1227 }
1228 
1229 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1230   Register len =  op->len()->as_register();
1231   __ uxtw(len, len);
1232 
1233   if (UseSlowPath ||
1234       (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1235       (!UseFastNewTypeArray   && !is_reference_type(op->type()))) {
1236     __ b(*op->stub()->entry());
1237   } else {
1238     Register tmp1 = op->tmp1()->as_register();
1239     Register tmp2 = op->tmp2()->as_register();
1240     Register tmp3 = op->tmp3()->as_register();
1241     if (len == tmp1) {
1242       tmp1 = tmp3;
1243     } else if (len == tmp2) {
1244       tmp2 = tmp3;
1245     } else if (len == tmp3) {
1246       // everything is ok
1247     } else {
1248       __ mov(tmp3, len);
1249     }
1250     __ allocate_array(op->obj()->as_register(),
1251                       len,
1252                       tmp1,
1253                       tmp2,
1254                       arrayOopDesc::header_size(op->type()),
1255                       array_element_size(op->type()),
1256                       op->klass()->as_register(),
1257                       *op->stub()->entry());
1258   }
1259   __ bind(*op->stub()->continuation());
1260 }
1261 
1262 void LIR_Assembler::type_profile_helper(Register mdo,
1263                                         ciMethodData *md, ciProfileData *data,
1264                                         Register recv, Label* update_done) {
1265   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1266     Label next_test;
1267     // See if the receiver is receiver[n].
1268     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1269     __ ldr(rscratch1, Address(rscratch2));
1270     __ cmp(recv, rscratch1);
1271     __ br(Assembler::NE, next_test);
1272     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1273     __ addptr(data_addr, DataLayout::counter_increment);
1274     __ b(*update_done);
1275     __ bind(next_test);
1276   }
1277 
1278   // Didn't find receiver; find next empty slot and fill it in
1279   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1280     Label next_test;
1281     __ lea(rscratch2,
1282            Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1283     Address recv_addr(rscratch2);
1284     __ ldr(rscratch1, recv_addr);
1285     __ cbnz(rscratch1, next_test);
1286     __ str(recv, recv_addr);
1287     __ mov(rscratch1, DataLayout::counter_increment);
1288     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1289     __ str(rscratch1, Address(rscratch2));
1290     __ b(*update_done);
1291     __ bind(next_test);
1292   }
1293 }
1294 
1295 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1296   // we always need a stub for the failure case.
1297   CodeStub* stub = op->stub();
1298   Register obj = op->object()->as_register();
1299   Register k_RInfo = op->tmp1()->as_register();
1300   Register klass_RInfo = op->tmp2()->as_register();
1301   Register dst = op->result_opr()->as_register();
1302   ciKlass* k = op->klass();
1303   Register Rtmp1 = noreg;
1304 
1305   // check if it needs to be profiled
1306   ciMethodData* md;
1307   ciProfileData* data;
1308 
1309   const bool should_profile = op->should_profile();
1310 
1311   if (should_profile) {
1312     ciMethod* method = op->profiled_method();
1313     assert(method != NULL, "Should have method");
1314     int bci = op->profiled_bci();
1315     md = method->method_data_or_null();
1316     assert(md != NULL, "Sanity");
1317     data = md->bci_to_data(bci);
1318     assert(data != NULL,                "need data for type check");
1319     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1320   }
1321   Label profile_cast_success, profile_cast_failure;
1322   Label *success_target = should_profile ? &profile_cast_success : success;
1323   Label *failure_target = should_profile ? &profile_cast_failure : failure;
1324 
1325   if (obj == k_RInfo) {
1326     k_RInfo = dst;
1327   } else if (obj == klass_RInfo) {
1328     klass_RInfo = dst;
1329   }
1330   if (k->is_loaded() && !UseCompressedClassPointers) {
1331     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1332   } else {
1333     Rtmp1 = op->tmp3()->as_register();
1334     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1335   }
1336 
1337   assert_different_registers(obj, k_RInfo, klass_RInfo);
1338 

1339     if (should_profile) {
1340       Label not_null;
1341       __ cbnz(obj, not_null);
1342       // Object is null; update MDO and exit
1343       Register mdo  = klass_RInfo;
1344       __ mov_metadata(mdo, md->constant_encoding());
1345       Address data_addr
1346         = __ form_address(rscratch2, mdo,
1347                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1348                           0);
1349       __ ldrb(rscratch1, data_addr);
1350       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1351       __ strb(rscratch1, data_addr);
1352       __ b(*obj_is_null);
1353       __ bind(not_null);
1354     } else {
1355       __ cbz(obj, *obj_is_null);
1356     }

1357 
1358   if (!k->is_loaded()) {
1359     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1360   } else {
1361     __ mov_metadata(k_RInfo, k->constant_encoding());
1362   }
1363   __ verify_oop(obj);
1364 
1365   if (op->fast_check()) {
1366     // get object class
1367     // not a safepoint as obj null check happens earlier
1368     __ load_klass(rscratch1, obj);
1369     __ cmp( rscratch1, k_RInfo);
1370 
1371     __ br(Assembler::NE, *failure_target);
1372     // successful cast, fall through to profile or jump
1373   } else {
1374     // get object class
1375     // not a safepoint as obj null check happens earlier
1376     __ load_klass(klass_RInfo, obj);
1377     if (k->is_loaded()) {
1378       // See if we get an immediate positive hit
1379       __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1380       __ cmp(k_RInfo, rscratch1);
1381       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1382         __ br(Assembler::NE, *failure_target);
1383         // successful cast, fall through to profile or jump
1384       } else {
1385         // See if we get an immediate positive hit
1386         __ br(Assembler::EQ, *success_target);
1387         // check for self
1388         __ cmp(klass_RInfo, k_RInfo);
1389         __ br(Assembler::EQ, *success_target);
1390 
1391         __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1392         __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1393         __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1394         // result is a boolean
1395         __ cbzw(klass_RInfo, *failure_target);
1396         // successful cast, fall through to profile or jump
1397       }
1398     } else {
1399       // perform the fast part of the checking logic
1400       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1401       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1402       __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1403       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1404       __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1405       // result is a boolean
1406       __ cbz(k_RInfo, *failure_target);
1407       // successful cast, fall through to profile or jump
1408     }
1409   }
1410   if (should_profile) {
1411     Register mdo  = klass_RInfo, recv = k_RInfo;
1412     __ bind(profile_cast_success);
1413     __ mov_metadata(mdo, md->constant_encoding());
1414     __ load_klass(recv, obj);
1415     Label update_done;
1416     type_profile_helper(mdo, md, data, recv, success);
1417     __ b(*success);
1418 
1419     __ bind(profile_cast_failure);
1420     __ mov_metadata(mdo, md->constant_encoding());
1421     Address counter_addr
1422       = __ form_address(rscratch2, mdo,
1423                         md->byte_offset_of_slot(data, CounterData::count_offset()),
1424                         0);
1425     __ ldr(rscratch1, counter_addr);
1426     __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1427     __ str(rscratch1, counter_addr);
1428     __ b(*failure);
1429   }
1430   __ b(*success);
1431 }
1432 
1433 
1434 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1435   const bool should_profile = op->should_profile();
1436 
1437   LIR_Code code = op->code();
1438   if (code == lir_store_check) {
1439     Register value = op->object()->as_register();
1440     Register array = op->array()->as_register();
1441     Register k_RInfo = op->tmp1()->as_register();
1442     Register klass_RInfo = op->tmp2()->as_register();
1443     Register Rtmp1 = op->tmp3()->as_register();
1444 
1445     CodeStub* stub = op->stub();
1446 
1447     // check if it needs to be profiled
1448     ciMethodData* md;
1449     ciProfileData* data;
1450 
1451     if (should_profile) {
1452       ciMethod* method = op->profiled_method();
1453       assert(method != NULL, "Should have method");
1454       int bci = op->profiled_bci();
1455       md = method->method_data_or_null();
1456       assert(md != NULL, "Sanity");
1457       data = md->bci_to_data(bci);
1458       assert(data != NULL,                "need data for type check");
1459       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1460     }
1461     Label profile_cast_success, profile_cast_failure, done;
1462     Label *success_target = should_profile ? &profile_cast_success : &done;
1463     Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1464 
1465     if (should_profile) {
1466       Label not_null;
1467       __ cbnz(value, not_null);
1468       // Object is null; update MDO and exit
1469       Register mdo  = klass_RInfo;
1470       __ mov_metadata(mdo, md->constant_encoding());
1471       Address data_addr
1472         = __ form_address(rscratch2, mdo,
1473                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1474                           0);
1475       __ ldrb(rscratch1, data_addr);
1476       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1477       __ strb(rscratch1, data_addr);
1478       __ b(done);
1479       __ bind(not_null);
1480     } else {
1481       __ cbz(value, done);
1482     }
1483 
1484     add_debug_info_for_null_check_here(op->info_for_exception());
1485     __ load_klass(k_RInfo, array);
1486     __ load_klass(klass_RInfo, value);
1487 
1488     // get instance klass (it's already uncompressed)
1489     __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1490     // perform the fast part of the checking logic
1491     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1492     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1493     __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1494     __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1495     __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1496     // result is a boolean
1497     __ cbzw(k_RInfo, *failure_target);
1498     // fall through to the success case
1499 
1500     if (should_profile) {
1501       Register mdo  = klass_RInfo, recv = k_RInfo;
1502       __ bind(profile_cast_success);
1503       __ mov_metadata(mdo, md->constant_encoding());
1504       __ load_klass(recv, value);
1505       Label update_done;
1506       type_profile_helper(mdo, md, data, recv, &done);
1507       __ b(done);
1508 
1509       __ bind(profile_cast_failure);
1510       __ mov_metadata(mdo, md->constant_encoding());
1511       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1512       __ lea(rscratch2, counter_addr);
1513       __ ldr(rscratch1, Address(rscratch2));
1514       __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1515       __ str(rscratch1, Address(rscratch2));
1516       __ b(*stub->entry());
1517     }
1518 
1519     __ bind(done);
1520   } else if (code == lir_checkcast) {
1521     Register obj = op->object()->as_register();
1522     Register dst = op->result_opr()->as_register();
1523     Label success;
1524     emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1525     __ bind(success);
1526     if (dst != obj) {
1527       __ mov(dst, obj);
1528     }
1529   } else if (code == lir_instanceof) {
1530     Register obj = op->object()->as_register();
1531     Register dst = op->result_opr()->as_register();
1532     Label success, failure, done;
1533     emit_typecheck_helper(op, &success, &failure, &failure);
1534     __ bind(failure);
1535     __ mov(dst, zr);
1536     __ b(done);
1537     __ bind(success);
1538     __ mov(dst, 1);
1539     __ bind(done);
1540   } else {
1541     ShouldNotReachHere();
1542   }
1543 }
1544 































































































































1545 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1546   __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1547   __ cset(rscratch1, Assembler::NE);
1548   __ membar(__ AnyAny);
1549 }
1550 
1551 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1552   __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1553   __ cset(rscratch1, Assembler::NE);
1554   __ membar(__ AnyAny);
1555 }
1556 
1557 
1558 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1559   assert(VM_Version::supports_cx8(), "wrong machine");
1560   Register addr;
1561   if (op->addr()->is_register()) {
1562     addr = as_reg(op->addr());
1563   } else {
1564     assert(op->addr()->is_address(), "what else?");
1565     LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1566     assert(addr_ptr->disp() == 0, "need 0 disp");
1567     assert(addr_ptr->index() == LIR_OprDesc::illegalOpr(), "need 0 index");
1568     addr = as_reg(addr_ptr->base());
1569   }
1570   Register newval = as_reg(op->new_value());
1571   Register cmpval = as_reg(op->cmp_value());
1572 
1573   if (op->code() == lir_cas_obj) {
1574     if (UseCompressedOops) {
1575       Register t1 = op->tmp1()->as_register();
1576       assert(op->tmp1()->is_valid(), "must be");
1577       __ encode_heap_oop(t1, cmpval);
1578       cmpval = t1;
1579       __ encode_heap_oop(rscratch2, newval);
1580       newval = rscratch2;
1581       casw(addr, newval, cmpval);
1582     } else {
1583       casl(addr, newval, cmpval);
1584     }
1585   } else if (op->code() == lir_cas_int) {
1586     casw(addr, newval, cmpval);
1587   } else {
1588     casl(addr, newval, cmpval);
1589   }
1590 }
1591 
1592 
1593 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1594 
1595   Assembler::Condition acond, ncond;
1596   switch (condition) {
1597   case lir_cond_equal:        acond = Assembler::EQ; ncond = Assembler::NE; break;
1598   case lir_cond_notEqual:     acond = Assembler::NE; ncond = Assembler::EQ; break;
1599   case lir_cond_less:         acond = Assembler::LT; ncond = Assembler::GE; break;
1600   case lir_cond_lessEqual:    acond = Assembler::LE; ncond = Assembler::GT; break;
1601   case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1602   case lir_cond_greater:      acond = Assembler::GT; ncond = Assembler::LE; break;
1603   case lir_cond_belowEqual:
1604   case lir_cond_aboveEqual:
1605   default:                    ShouldNotReachHere();
1606     acond = Assembler::EQ; ncond = Assembler::NE;  // unreachable
1607   }
1608 
1609   assert(result->is_single_cpu() || result->is_double_cpu(),
1610          "expect single register for result");
1611   if (opr1->is_constant() && opr2->is_constant()
1612       && opr1->type() == T_INT && opr2->type() == T_INT) {
1613     jint val1 = opr1->as_jint();
1614     jint val2 = opr2->as_jint();
1615     if (val1 == 0 && val2 == 1) {
1616       __ cset(result->as_register(), ncond);
1617       return;
1618     } else if (val1 == 1 && val2 == 0) {
1619       __ cset(result->as_register(), acond);
1620       return;
1621     }
1622   }
1623 
1624   if (opr1->is_constant() && opr2->is_constant()
1625       && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1626     jlong val1 = opr1->as_jlong();
1627     jlong val2 = opr2->as_jlong();
1628     if (val1 == 0 && val2 == 1) {
1629       __ cset(result->as_register_lo(), ncond);
1630       return;
1631     } else if (val1 == 1 && val2 == 0) {
1632       __ cset(result->as_register_lo(), acond);
1633       return;
1634     }
1635   }
1636 
1637   if (opr1->is_stack()) {
1638     stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1639     opr1 = FrameMap::rscratch1_opr;
1640   } else if (opr1->is_constant()) {
1641     LIR_Opr tmp
1642       = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1643     const2reg(opr1, tmp, lir_patch_none, NULL);
1644     opr1 = tmp;
1645   }
1646 
1647   if (opr2->is_stack()) {
1648     stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1649     opr2 = FrameMap::rscratch2_opr;
1650   } else if (opr2->is_constant()) {
1651     LIR_Opr tmp
1652       = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1653     const2reg(opr2, tmp, lir_patch_none, NULL);
1654     opr2 = tmp;
1655   }
1656 
1657   if (result->type() == T_LONG)
1658     __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1659   else
1660     __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1661 }
1662 
1663 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1664   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1665 
1666   if (left->is_single_cpu()) {
1667     Register lreg = left->as_register();
1668     Register dreg = as_reg(dest);
1669 
1670     if (right->is_single_cpu()) {
1671       // cpu register - cpu register
1672 
1673       assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1674              "should be");
1675       Register rreg = right->as_register();
1676       switch (code) {
1677       case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1678       case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1679       case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1680       default:      ShouldNotReachHere();
1681       }
1682 
1683     } else if (right->is_double_cpu()) {
1684       Register rreg = right->as_register_lo();
1685       // single_cpu + double_cpu: can happen with obj+long
1686       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1687       switch (code) {
1688       case lir_add: __ add(dreg, lreg, rreg); break;
1689       case lir_sub: __ sub(dreg, lreg, rreg); break;
1690       default: ShouldNotReachHere();
1691       }
1692     } else if (right->is_constant()) {
1693       // cpu register - constant
1694       jlong c;
1695 
1696       // FIXME.  This is fugly: we really need to factor all this logic.
1697       switch(right->type()) {
1698       case T_LONG:
1699         c = right->as_constant_ptr()->as_jlong();
1700         break;
1701       case T_INT:
1702       case T_ADDRESS:
1703         c = right->as_constant_ptr()->as_jint();
1704         break;
1705       default:
1706         ShouldNotReachHere();
1707         c = 0;  // unreachable
1708         break;
1709       }
1710 
1711       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1712       if (c == 0 && dreg == lreg) {
1713         COMMENT("effective nop elided");
1714         return;
1715       }
1716       switch(left->type()) {
1717       case T_INT:
1718         switch (code) {
1719         case lir_add: __ addw(dreg, lreg, c); break;
1720         case lir_sub: __ subw(dreg, lreg, c); break;
1721         default: ShouldNotReachHere();
1722         }
1723         break;
1724       case T_OBJECT:
1725       case T_ADDRESS:
1726         switch (code) {
1727         case lir_add: __ add(dreg, lreg, c); break;
1728         case lir_sub: __ sub(dreg, lreg, c); break;
1729         default: ShouldNotReachHere();
1730         }
1731         break;
1732       default:
1733         ShouldNotReachHere();
1734       }
1735     } else {
1736       ShouldNotReachHere();
1737     }
1738 
1739   } else if (left->is_double_cpu()) {
1740     Register lreg_lo = left->as_register_lo();
1741 
1742     if (right->is_double_cpu()) {
1743       // cpu register - cpu register
1744       Register rreg_lo = right->as_register_lo();
1745       switch (code) {
1746       case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1747       case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1748       case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1749       case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1750       case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1751       default:
1752         ShouldNotReachHere();
1753       }
1754 
1755     } else if (right->is_constant()) {
1756       jlong c = right->as_constant_ptr()->as_jlong();
1757       Register dreg = as_reg(dest);
1758       switch (code) {
1759         case lir_add:
1760         case lir_sub:
1761           if (c == 0 && dreg == lreg_lo) {
1762             COMMENT("effective nop elided");
1763             return;
1764           }
1765           code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1766           break;
1767         case lir_div:
1768           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1769           if (c == 1) {
1770             // move lreg_lo to dreg if divisor is 1
1771             __ mov(dreg, lreg_lo);
1772           } else {
1773             unsigned int shift = log2i_exact(c);
1774             // use rscratch1 as intermediate result register
1775             __ asr(rscratch1, lreg_lo, 63);
1776             __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1777             __ asr(dreg, rscratch1, shift);
1778           }
1779           break;
1780         case lir_rem:
1781           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1782           if (c == 1) {
1783             // move 0 to dreg if divisor is 1
1784             __ mov(dreg, zr);
1785           } else {
1786             // use rscratch1 as intermediate result register
1787             __ negs(rscratch1, lreg_lo);
1788             __ andr(dreg, lreg_lo, c - 1);
1789             __ andr(rscratch1, rscratch1, c - 1);
1790             __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1791           }
1792           break;
1793         default:
1794           ShouldNotReachHere();
1795       }
1796     } else {
1797       ShouldNotReachHere();
1798     }
1799   } else if (left->is_single_fpu()) {
1800     assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1801     switch (code) {
1802     case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1803     case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1804     case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1805     case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1806     default:
1807       ShouldNotReachHere();
1808     }
1809   } else if (left->is_double_fpu()) {
1810     if (right->is_double_fpu()) {
1811       // fpu register - fpu register
1812       switch (code) {
1813       case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1814       case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1815       case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1816       case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1817       default:
1818         ShouldNotReachHere();
1819       }
1820     } else {
1821       if (right->is_constant()) {
1822         ShouldNotReachHere();
1823       }
1824       ShouldNotReachHere();
1825     }
1826   } else if (left->is_single_stack() || left->is_address()) {
1827     assert(left == dest, "left and dest must be equal");
1828     ShouldNotReachHere();
1829   } else {
1830     ShouldNotReachHere();
1831   }
1832 }
1833 
1834 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1835 
1836 
1837 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1838   switch(code) {
1839   case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1840   case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1841   default      : ShouldNotReachHere();
1842   }
1843 }
1844 
1845 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1846 
1847   assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1848   Register Rleft = left->is_single_cpu() ? left->as_register() :
1849                                            left->as_register_lo();
1850    if (dst->is_single_cpu()) {
1851      Register Rdst = dst->as_register();
1852      if (right->is_constant()) {
1853        switch (code) {
1854          case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1855          case lir_logic_or:  __ orrw (Rdst, Rleft, right->as_jint()); break;
1856          case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1857          default: ShouldNotReachHere(); break;
1858        }
1859      } else {
1860        Register Rright = right->is_single_cpu() ? right->as_register() :
1861                                                   right->as_register_lo();
1862        switch (code) {
1863          case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1864          case lir_logic_or:  __ orrw (Rdst, Rleft, Rright); break;
1865          case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1866          default: ShouldNotReachHere(); break;
1867        }
1868      }
1869    } else {
1870      Register Rdst = dst->as_register_lo();
1871      if (right->is_constant()) {
1872        switch (code) {
1873          case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1874          case lir_logic_or:  __ orr (Rdst, Rleft, right->as_jlong()); break;
1875          case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1876          default: ShouldNotReachHere(); break;
1877        }
1878      } else {
1879        Register Rright = right->is_single_cpu() ? right->as_register() :
1880                                                   right->as_register_lo();
1881        switch (code) {
1882          case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1883          case lir_logic_or:  __ orr (Rdst, Rleft, Rright); break;
1884          case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1885          default: ShouldNotReachHere(); break;
1886        }
1887      }
1888    }
1889 }
1890 
1891 
1892 
1893 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1894 
1895   // opcode check
1896   assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1897   bool is_irem = (code == lir_irem);
1898 
1899   // operand check
1900   assert(left->is_single_cpu(),   "left must be register");
1901   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
1902   assert(result->is_single_cpu(), "result must be register");
1903   Register lreg = left->as_register();
1904   Register dreg = result->as_register();
1905 
1906   // power-of-2 constant check and codegen
1907   if (right->is_constant()) {
1908     int c = right->as_constant_ptr()->as_jint();
1909     assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1910     if (is_irem) {
1911       if (c == 1) {
1912         // move 0 to dreg if divisor is 1
1913         __ movw(dreg, zr);
1914       } else {
1915         // use rscratch1 as intermediate result register
1916         __ negsw(rscratch1, lreg);
1917         __ andw(dreg, lreg, c - 1);
1918         __ andw(rscratch1, rscratch1, c - 1);
1919         __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1920       }
1921     } else {
1922       if (c == 1) {
1923         // move lreg to dreg if divisor is 1
1924         __ movw(dreg, lreg);
1925       } else {
1926         unsigned int shift = exact_log2(c);
1927         // use rscratch1 as intermediate result register
1928         __ asrw(rscratch1, lreg, 31);
1929         __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1930         __ asrw(dreg, rscratch1, shift);
1931       }
1932     }
1933   } else {
1934     Register rreg = right->as_register();
1935     __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1936   }
1937 }
1938 
1939 
1940 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1941   if (opr1->is_constant() && opr2->is_single_cpu()) {
1942     // tableswitch
1943     Register reg = as_reg(opr2);
1944     struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1945     __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1946   } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1947     Register reg1 = as_reg(opr1);
1948     if (opr2->is_single_cpu()) {
1949       // cpu register - cpu register
1950       Register reg2 = opr2->as_register();
1951       if (is_reference_type(opr1->type())) {
1952         __ cmpoop(reg1, reg2);
1953       } else {
1954         assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1955         __ cmpw(reg1, reg2);
1956       }
1957       return;
1958     }
1959     if (opr2->is_double_cpu()) {
1960       // cpu register - cpu register
1961       Register reg2 = opr2->as_register_lo();
1962       __ cmp(reg1, reg2);
1963       return;
1964     }
1965 
1966     if (opr2->is_constant()) {
1967       bool is_32bit = false; // width of register operand
1968       jlong imm;
1969 
1970       switch(opr2->type()) {
1971       case T_INT:
1972         imm = opr2->as_constant_ptr()->as_jint();
1973         is_32bit = true;
1974         break;
1975       case T_LONG:
1976         imm = opr2->as_constant_ptr()->as_jlong();
1977         break;
1978       case T_ADDRESS:
1979         imm = opr2->as_constant_ptr()->as_jint();
1980         break;
1981       case T_METADATA:
1982         imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1983         break;

1984       case T_OBJECT:
1985       case T_ARRAY:
1986         jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1987         __ cmpoop(reg1, rscratch1);
1988         return;
1989       default:
1990         ShouldNotReachHere();
1991         imm = 0;  // unreachable
1992         break;
1993       }
1994 
1995       if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1996         if (is_32bit)
1997           __ cmpw(reg1, imm);
1998         else
1999           __ subs(zr, reg1, imm);
2000         return;
2001       } else {
2002         __ mov(rscratch1, imm);
2003         if (is_32bit)
2004           __ cmpw(reg1, rscratch1);
2005         else
2006           __ cmp(reg1, rscratch1);
2007         return;
2008       }
2009     } else
2010       ShouldNotReachHere();
2011   } else if (opr1->is_single_fpu()) {
2012     FloatRegister reg1 = opr1->as_float_reg();
2013     assert(opr2->is_single_fpu(), "expect single float register");
2014     FloatRegister reg2 = opr2->as_float_reg();
2015     __ fcmps(reg1, reg2);
2016   } else if (opr1->is_double_fpu()) {
2017     FloatRegister reg1 = opr1->as_double_reg();
2018     assert(opr2->is_double_fpu(), "expect double float register");
2019     FloatRegister reg2 = opr2->as_double_reg();
2020     __ fcmpd(reg1, reg2);
2021   } else {
2022     ShouldNotReachHere();
2023   }
2024 }
2025 
2026 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2027   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2028     bool is_unordered_less = (code == lir_ucmp_fd2i);
2029     if (left->is_single_fpu()) {
2030       __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2031     } else if (left->is_double_fpu()) {
2032       __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2033     } else {
2034       ShouldNotReachHere();
2035     }
2036   } else if (code == lir_cmp_l2i) {
2037     Label done;
2038     __ cmp(left->as_register_lo(), right->as_register_lo());
2039     __ mov(dst->as_register(), (uint64_t)-1L);
2040     __ br(Assembler::LT, done);
2041     __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2042     __ bind(done);
2043   } else {
2044     ShouldNotReachHere();
2045   }
2046 }
2047 
2048 
2049 void LIR_Assembler::align_call(LIR_Code code) {  }
2050 
2051 
2052 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2053   address call = __ trampoline_call(Address(op->addr(), rtype));
2054   if (call == NULL) {
2055     bailout("trampoline stub overflow");
2056     return;
2057   }
2058   add_call_info(code_offset(), op->info());
2059 }
2060 
2061 
2062 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2063   address call = __ ic_call(op->addr());
2064   if (call == NULL) {
2065     bailout("trampoline stub overflow");
2066     return;
2067   }
2068   add_call_info(code_offset(), op->info());
2069 }
2070 
2071 void LIR_Assembler::emit_static_call_stub() {
2072   address call_pc = __ pc();
2073   address stub = __ start_a_stub(call_stub_size());
2074   if (stub == NULL) {
2075     bailout("static call stub overflow");
2076     return;
2077   }
2078 
2079   int start = __ offset();
2080 
2081   __ relocate(static_stub_Relocation::spec(call_pc));
2082   __ emit_static_call_stub();
2083 
2084   assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size()
2085         <= call_stub_size(), "stub too big");
2086   __ end_a_stub();
2087 }
2088 
2089 
2090 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2091   assert(exceptionOop->as_register() == r0, "must match");
2092   assert(exceptionPC->as_register() == r3, "must match");
2093 
2094   // exception object is not added to oop map by LinearScan
2095   // (LinearScan assumes that no oops are in fixed registers)
2096   info->add_register_oop(exceptionOop);
2097   Runtime1::StubID unwind_id;
2098 
2099   // get current pc information
2100   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2101   if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2102     // As no instructions have been generated yet for this LIR node it's
2103     // possible that an oop map already exists for the current offset.
2104     // In that case insert an dummy NOP here to ensure all oop map PCs
2105     // are unique. See JDK-8237483.
2106     __ nop();
2107   }
2108   int pc_for_athrow_offset = __ offset();
2109   InternalAddress pc_for_athrow(__ pc());
2110   __ adr(exceptionPC->as_register(), pc_for_athrow);
2111   add_call_info(pc_for_athrow_offset, info); // for exception handler
2112 
2113   __ verify_not_null_oop(r0);
2114   // search an exception handler (r0: exception oop, r3: throwing pc)
2115   if (compilation()->has_fpu_code()) {
2116     unwind_id = Runtime1::handle_exception_id;
2117   } else {
2118     unwind_id = Runtime1::handle_exception_nofpu_id;
2119   }
2120   __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2121 
2122   // FIXME: enough room for two byte trap   ????
2123   __ nop();
2124 }
2125 
2126 
2127 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2128   assert(exceptionOop->as_register() == r0, "must match");
2129 
2130   __ b(_unwind_handler_entry);
2131 }
2132 
2133 
2134 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2135   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2136   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2137 
2138   switch (left->type()) {
2139     case T_INT: {
2140       switch (code) {
2141       case lir_shl:  __ lslvw (dreg, lreg, count->as_register()); break;
2142       case lir_shr:  __ asrvw (dreg, lreg, count->as_register()); break;
2143       case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2144       default:
2145         ShouldNotReachHere();
2146         break;
2147       }
2148       break;
2149     case T_LONG:

2150     case T_ADDRESS:
2151     case T_OBJECT:
2152       switch (code) {
2153       case lir_shl:  __ lslv (dreg, lreg, count->as_register()); break;
2154       case lir_shr:  __ asrv (dreg, lreg, count->as_register()); break;
2155       case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2156       default:
2157         ShouldNotReachHere();
2158         break;
2159       }
2160       break;
2161     default:
2162       ShouldNotReachHere();
2163       break;
2164     }
2165   }
2166 }
2167 
2168 
2169 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2170   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2171   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2172 
2173   switch (left->type()) {
2174     case T_INT: {
2175       switch (code) {
2176       case lir_shl:  __ lslw (dreg, lreg, count); break;
2177       case lir_shr:  __ asrw (dreg, lreg, count); break;
2178       case lir_ushr: __ lsrw (dreg, lreg, count); break;
2179       default:
2180         ShouldNotReachHere();
2181         break;
2182       }
2183       break;
2184     case T_LONG:
2185     case T_ADDRESS:

2186     case T_OBJECT:
2187       switch (code) {
2188       case lir_shl:  __ lsl (dreg, lreg, count); break;
2189       case lir_shr:  __ asr (dreg, lreg, count); break;
2190       case lir_ushr: __ lsr (dreg, lreg, count); break;
2191       default:
2192         ShouldNotReachHere();
2193         break;
2194       }
2195       break;
2196     default:
2197       ShouldNotReachHere();
2198       break;
2199     }
2200   }
2201 }
2202 
2203 
2204 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2205   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2206   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2207   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2208   __ str (r, Address(sp, offset_from_rsp_in_bytes));
2209 }
2210 
2211 
2212 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
2213   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2214   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2215   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2216   __ mov (rscratch1, c);
2217   __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2218 }
2219 
2220 
2221 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
2222   ShouldNotReachHere();
2223   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2224   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2225   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2226   __ lea(rscratch1, __ constant_oop_address(o));
2227   __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2228 }
2229 






















2230 
2231 // This code replaces a call to arraycopy; no exception may
2232 // be thrown in this code, they must be thrown in the System.arraycopy
2233 // activation frame; we could save some checks if this would not be the case
2234 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2235   ciArrayKlass* default_type = op->expected_type();
2236   Register src = op->src()->as_register();
2237   Register dst = op->dst()->as_register();
2238   Register src_pos = op->src_pos()->as_register();
2239   Register dst_pos = op->dst_pos()->as_register();
2240   Register length  = op->length()->as_register();
2241   Register tmp = op->tmp()->as_register();
2242 
2243   CodeStub* stub = op->stub();
2244   int flags = op->flags();
2245   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2246   if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2247 






2248   // if we don't know anything, just go through the generic arraycopy
2249   if (default_type == NULL // || basic_type == T_OBJECT
2250       ) {
2251     Label done;
2252     assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2253 
2254     // Save the arguments in case the generic arraycopy fails and we
2255     // have to fall back to the JNI stub
2256     __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2257     __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2258     __ str(src,              Address(sp, 4*BytesPerWord));
2259 
2260     address copyfunc_addr = StubRoutines::generic_arraycopy();
2261     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2262 
2263     // The arguments are in java calling convention so we shift them
2264     // to C convention
2265     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2266     __ mov(c_rarg0, j_rarg0);
2267     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2268     __ mov(c_rarg1, j_rarg1);
2269     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2270     __ mov(c_rarg2, j_rarg2);
2271     assert_different_registers(c_rarg3, j_rarg4);
2272     __ mov(c_rarg3, j_rarg3);
2273     __ mov(c_rarg4, j_rarg4);
2274 #ifndef PRODUCT
2275     if (PrintC1Statistics) {
2276       __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2277     }
2278 #endif
2279     __ far_call(RuntimeAddress(copyfunc_addr));
2280 
2281     __ cbz(r0, *stub->continuation());
2282 
2283     // Reload values from the stack so they are where the stub
2284     // expects them.
2285     __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2286     __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2287     __ ldr(src,              Address(sp, 4*BytesPerWord));
2288 
2289     // r0 is -1^K where K == partial copied count
2290     __ eonw(rscratch1, r0, zr);
2291     // adjust length down and src/end pos up by partial copied count
2292     __ subw(length, length, rscratch1);
2293     __ addw(src_pos, src_pos, rscratch1);
2294     __ addw(dst_pos, dst_pos, rscratch1);
2295     __ b(*stub->entry());
2296 
2297     __ bind(*stub->continuation());
2298     return;
2299   }
2300 









2301   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2302 
2303   int elem_size = type2aelembytes(basic_type);
2304   int scale = exact_log2(elem_size);
2305 
2306   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2307   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2308   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2309   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2310 
2311   // test for NULL
2312   if (flags & LIR_OpArrayCopy::src_null_check) {
2313     __ cbz(src, *stub->entry());
2314   }
2315   if (flags & LIR_OpArrayCopy::dst_null_check) {
2316     __ cbz(dst, *stub->entry());
2317   }
2318 
2319   // If the compiler was not able to prove that exact type of the source or the destination
2320   // of the arraycopy is an array type, check at runtime if the source or the destination is
2321   // an instance type.
2322   if (flags & LIR_OpArrayCopy::type_check) {
2323     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2324       __ load_klass(tmp, dst);
2325       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2326       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2327       __ br(Assembler::GE, *stub->entry());
2328     }
2329 
2330     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2331       __ load_klass(tmp, src);
2332       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2333       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2334       __ br(Assembler::GE, *stub->entry());
2335     }
2336   }
2337 
2338   // check if negative
2339   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2340     __ cmpw(src_pos, 0);
2341     __ br(Assembler::LT, *stub->entry());
2342   }
2343   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2344     __ cmpw(dst_pos, 0);
2345     __ br(Assembler::LT, *stub->entry());
2346   }
2347 
2348   if (flags & LIR_OpArrayCopy::length_positive_check) {
2349     __ cmpw(length, 0);
2350     __ br(Assembler::LT, *stub->entry());
2351   }
2352 
2353   if (flags & LIR_OpArrayCopy::src_range_check) {
2354     __ addw(tmp, src_pos, length);
2355     __ ldrw(rscratch1, src_length_addr);
2356     __ cmpw(tmp, rscratch1);
2357     __ br(Assembler::HI, *stub->entry());
2358   }
2359   if (flags & LIR_OpArrayCopy::dst_range_check) {
2360     __ addw(tmp, dst_pos, length);
2361     __ ldrw(rscratch1, dst_length_addr);
2362     __ cmpw(tmp, rscratch1);
2363     __ br(Assembler::HI, *stub->entry());
2364   }
2365 
2366   if (flags & LIR_OpArrayCopy::type_check) {
2367     // We don't know the array types are compatible
2368     if (basic_type != T_OBJECT) {
2369       // Simple test for basic type arrays
2370       if (UseCompressedClassPointers) {
2371         __ ldrw(tmp, src_klass_addr);
2372         __ ldrw(rscratch1, dst_klass_addr);
2373         __ cmpw(tmp, rscratch1);
2374       } else {
2375         __ ldr(tmp, src_klass_addr);
2376         __ ldr(rscratch1, dst_klass_addr);
2377         __ cmp(tmp, rscratch1);
2378       }
2379       __ br(Assembler::NE, *stub->entry());
2380     } else {
2381       // For object arrays, if src is a sub class of dst then we can
2382       // safely do the copy.
2383       Label cont, slow;
2384 
2385 #define PUSH(r1, r2)                                    \
2386       stp(r1, r2, __ pre(sp, -2 * wordSize));
2387 
2388 #define POP(r1, r2)                                     \
2389       ldp(r1, r2, __ post(sp, 2 * wordSize));
2390 
2391       __ PUSH(src, dst);
2392 
2393       __ load_klass(src, src);
2394       __ load_klass(dst, dst);
2395 
2396       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2397 
2398       __ PUSH(src, dst);
2399       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2400       __ POP(src, dst);
2401 
2402       __ cbnz(src, cont);
2403 
2404       __ bind(slow);
2405       __ POP(src, dst);
2406 
2407       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2408       if (copyfunc_addr != NULL) { // use stub if available
2409         // src is not a sub class of dst so we have to do a
2410         // per-element check.
2411 
2412         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2413         if ((flags & mask) != mask) {
2414           // Check that at least both of them object arrays.
2415           assert(flags & mask, "one of the two should be known to be an object array");
2416 
2417           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2418             __ load_klass(tmp, src);
2419           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2420             __ load_klass(tmp, dst);
2421           }
2422           int lh_offset = in_bytes(Klass::layout_helper_offset());
2423           Address klass_lh_addr(tmp, lh_offset);
2424           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2425           __ ldrw(rscratch1, klass_lh_addr);
2426           __ mov(rscratch2, objArray_lh);
2427           __ eorw(rscratch1, rscratch1, rscratch2);
2428           __ cbnzw(rscratch1, *stub->entry());
2429         }
2430 
2431        // Spill because stubs can use any register they like and it's
2432        // easier to restore just those that we care about.
2433         __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2434         __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2435         __ str(src,              Address(sp, 4*BytesPerWord));
2436 
2437         __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2438         __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2439         assert_different_registers(c_rarg0, dst, dst_pos, length);
2440         __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2441         __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2442         assert_different_registers(c_rarg1, dst, length);
2443         __ uxtw(c_rarg2, length);
2444         assert_different_registers(c_rarg2, dst);
2445 
2446         __ load_klass(c_rarg4, dst);
2447         __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2448         __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2449         __ far_call(RuntimeAddress(copyfunc_addr));
2450 
2451 #ifndef PRODUCT
2452         if (PrintC1Statistics) {
2453           Label failed;
2454           __ cbnz(r0, failed);
2455           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2456           __ bind(failed);
2457         }
2458 #endif
2459 
2460         __ cbz(r0, *stub->continuation());
2461 
2462 #ifndef PRODUCT
2463         if (PrintC1Statistics) {
2464           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2465         }
2466 #endif
2467         assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2468 
2469         // Restore previously spilled arguments
2470         __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2471         __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2472         __ ldr(src,              Address(sp, 4*BytesPerWord));
2473 
2474         // return value is -1^K where K is partial copied count
2475         __ eonw(rscratch1, r0, zr);
2476         // adjust length down and src/end pos up by partial copied count
2477         __ subw(length, length, rscratch1);
2478         __ addw(src_pos, src_pos, rscratch1);
2479         __ addw(dst_pos, dst_pos, rscratch1);
2480       }
2481 
2482       __ b(*stub->entry());
2483 
2484       __ bind(cont);
2485       __ POP(src, dst);
2486     }
2487   }
2488 
2489 #ifdef ASSERT
2490   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2491     // Sanity check the known type with the incoming class.  For the
2492     // primitive case the types must match exactly with src.klass and
2493     // dst.klass each exactly matching the default type.  For the
2494     // object array case, if no type check is needed then either the
2495     // dst type is exactly the expected type and the src type is a
2496     // subtype which we can't check or src is the same array as dst
2497     // but not necessarily exactly of type default_type.
2498     Label known_ok, halt;
2499     __ mov_metadata(tmp, default_type->constant_encoding());
2500     if (UseCompressedClassPointers) {
2501       __ encode_klass_not_null(tmp);
2502     }
2503 
2504     if (basic_type != T_OBJECT) {
2505 
2506       if (UseCompressedClassPointers) {
2507         __ ldrw(rscratch1, dst_klass_addr);
2508         __ cmpw(tmp, rscratch1);
2509       } else {
2510         __ ldr(rscratch1, dst_klass_addr);
2511         __ cmp(tmp, rscratch1);
2512       }
2513       __ br(Assembler::NE, halt);
2514       if (UseCompressedClassPointers) {
2515         __ ldrw(rscratch1, src_klass_addr);
2516         __ cmpw(tmp, rscratch1);
2517       } else {
2518         __ ldr(rscratch1, src_klass_addr);
2519         __ cmp(tmp, rscratch1);
2520       }
2521       __ br(Assembler::EQ, known_ok);
2522     } else {
2523       if (UseCompressedClassPointers) {
2524         __ ldrw(rscratch1, dst_klass_addr);
2525         __ cmpw(tmp, rscratch1);
2526       } else {
2527         __ ldr(rscratch1, dst_klass_addr);
2528         __ cmp(tmp, rscratch1);
2529       }
2530       __ br(Assembler::EQ, known_ok);
2531       __ cmp(src, dst);
2532       __ br(Assembler::EQ, known_ok);
2533     }
2534     __ bind(halt);
2535     __ stop("incorrect type information in arraycopy");
2536     __ bind(known_ok);
2537   }
2538 #endif
2539 
2540 #ifndef PRODUCT
2541   if (PrintC1Statistics) {
2542     __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2543   }
2544 #endif
2545 
2546   __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2547   __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2548   assert_different_registers(c_rarg0, dst, dst_pos, length);
2549   __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2550   __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2551   assert_different_registers(c_rarg1, dst, length);
2552   __ uxtw(c_rarg2, length);
2553   assert_different_registers(c_rarg2, dst);
2554 
2555   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2556   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2557   const char *name;
2558   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2559 
2560  CodeBlob *cb = CodeCache::find_blob(entry);
2561  if (cb) {
2562    __ far_call(RuntimeAddress(entry));
2563  } else {
2564    __ call_VM_leaf(entry, 3);
2565  }
2566 
2567   __ bind(*stub->continuation());
2568 }
2569 
2570 
2571 
2572 
2573 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2574   Register obj = op->obj_opr()->as_register();  // may not be an oop
2575   Register hdr = op->hdr_opr()->as_register();
2576   Register lock = op->lock_opr()->as_register();
2577   if (!UseFastLocking) {
2578     __ b(*op->stub()->entry());
2579   } else if (op->code() == lir_lock) {
2580     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2581     // add debug info for NullPointerException only if one is possible
2582     int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry());
2583     if (op->info() != NULL) {
2584       add_debug_info_for_null_check(null_check_offset, op->info());
2585     }
2586     // done
2587   } else if (op->code() == lir_unlock) {
2588     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2589     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2590   } else {
2591     Unimplemented();
2592   }
2593   __ bind(*op->stub()->continuation());
2594 }
2595 
2596 
2597 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2598   ciMethod* method = op->profiled_method();
2599   int bci          = op->profiled_bci();
2600   ciMethod* callee = op->profiled_callee();
2601 
2602   // Update counter for all call types
2603   ciMethodData* md = method->method_data_or_null();
2604   assert(md != NULL, "Sanity");
2605   ciProfileData* data = md->bci_to_data(bci);
2606   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2607   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2608   Register mdo  = op->mdo()->as_register();
2609   __ mov_metadata(mdo, md->constant_encoding());
2610   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2611   // Perform additional virtual call profiling for invokevirtual and
2612   // invokeinterface bytecodes
2613   if (op->should_profile_receiver_type()) {
2614     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2615     Register recv = op->recv()->as_register();
2616     assert_different_registers(mdo, recv);
2617     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2618     ciKlass* known_klass = op->known_holder();
2619     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2620       // We know the type that will be seen at this call site; we can
2621       // statically update the MethodData* rather than needing to do
2622       // dynamic tests on the receiver type
2623 
2624       // NOTE: we should probably put a lock around this search to
2625       // avoid collisions by concurrent compilations
2626       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2627       uint i;
2628       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2629         ciKlass* receiver = vc_data->receiver(i);
2630         if (known_klass->equals(receiver)) {
2631           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2632           __ addptr(data_addr, DataLayout::counter_increment);
2633           return;
2634         }
2635       }
2636 
2637       // Receiver type not found in profile data; select an empty slot
2638 
2639       // Note that this is less efficient than it should be because it
2640       // always does a write to the receiver part of the
2641       // VirtualCallData rather than just the first time
2642       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2643         ciKlass* receiver = vc_data->receiver(i);
2644         if (receiver == NULL) {
2645           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2646           __ mov_metadata(rscratch1, known_klass->constant_encoding());
2647           __ lea(rscratch2, recv_addr);
2648           __ str(rscratch1, Address(rscratch2));
2649           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2650           __ addptr(data_addr, DataLayout::counter_increment);
2651           return;
2652         }
2653       }
2654     } else {
2655       __ load_klass(recv, recv);
2656       Label update_done;
2657       type_profile_helper(mdo, md, data, recv, &update_done);
2658       // Receiver did not match any saved receiver and there is no empty row for it.
2659       // Increment total counter to indicate polymorphic case.
2660       __ addptr(counter_addr, DataLayout::counter_increment);
2661 
2662       __ bind(update_done);
2663     }
2664   } else {
2665     // Static call
2666     __ addptr(counter_addr, DataLayout::counter_increment);
2667   }
2668 }
2669 
2670 
2671 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2672   Unimplemented();
2673 }
2674 
2675 
2676 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2677   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2678 }
2679 
2680 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2681   assert(op->crc()->is_single_cpu(),  "crc must be register");
2682   assert(op->val()->is_single_cpu(),  "byte value must be register");
2683   assert(op->result_opr()->is_single_cpu(), "result must be register");
2684   Register crc = op->crc()->as_register();
2685   Register val = op->val()->as_register();
2686   Register res = op->result_opr()->as_register();
2687 
2688   assert_different_registers(val, crc, res);
2689   uint64_t offset;
2690   __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2691   if (offset) __ add(res, res, offset);
2692 
2693   __ mvnw(crc, crc); // ~crc
2694   __ update_byte_crc32(crc, val, res);
2695   __ mvnw(res, crc); // ~crc
2696 }
2697 
2698 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2699   COMMENT("emit_profile_type {");
2700   Register obj = op->obj()->as_register();
2701   Register tmp = op->tmp()->as_pointer_register();
2702   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2703   ciKlass* exact_klass = op->exact_klass();
2704   intptr_t current_klass = op->current_klass();
2705   bool not_null = op->not_null();
2706   bool no_conflict = op->no_conflict();
2707 
2708   Label update, next, none;
2709 
2710   bool do_null = !not_null;
2711   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2712   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2713 
2714   assert(do_null || do_update, "why are we here?");
2715   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2716   assert(mdo_addr.base() != rscratch1, "wrong register");
2717 
2718   __ verify_oop(obj);
2719 
2720   if (tmp != obj) {
2721     __ mov(tmp, obj);
2722   }
2723   if (do_null) {
2724     __ cbnz(tmp, update);
2725     if (!TypeEntries::was_null_seen(current_klass)) {
2726       __ ldr(rscratch2, mdo_addr);
2727       __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2728       __ str(rscratch2, mdo_addr);
2729     }
2730     if (do_update) {
2731 #ifndef ASSERT
2732       __ b(next);
2733     }
2734 #else
2735       __ b(next);
2736     }
2737   } else {
2738     __ cbnz(tmp, update);
2739     __ stop("unexpected null obj");
2740 #endif
2741   }
2742 
2743   __ bind(update);
2744 
2745   if (do_update) {
2746 #ifdef ASSERT
2747     if (exact_klass != NULL) {
2748       Label ok;
2749       __ load_klass(tmp, tmp);
2750       __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2751       __ eor(rscratch1, tmp, rscratch1);
2752       __ cbz(rscratch1, ok);
2753       __ stop("exact klass and actual klass differ");
2754       __ bind(ok);
2755     }
2756 #endif
2757     if (!no_conflict) {
2758       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2759         if (exact_klass != NULL) {
2760           __ mov_metadata(tmp, exact_klass->constant_encoding());
2761         } else {
2762           __ load_klass(tmp, tmp);
2763         }
2764 
2765         __ ldr(rscratch2, mdo_addr);
2766         __ eor(tmp, tmp, rscratch2);
2767         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2768         // klass seen before, nothing to do. The unknown bit may have been
2769         // set already but no need to check.
2770         __ cbz(rscratch1, next);
2771 
2772         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2773 
2774         if (TypeEntries::is_type_none(current_klass)) {
2775           __ cbz(rscratch2, none);
2776           __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2777           __ br(Assembler::EQ, none);
2778           // There is a chance that the checks above (re-reading profiling
2779           // data from memory) fail if another thread has just set the
2780           // profiling to this obj's klass
2781           __ dmb(Assembler::ISHLD);
2782           __ ldr(rscratch2, mdo_addr);
2783           __ eor(tmp, tmp, rscratch2);
2784           __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2785           __ cbz(rscratch1, next);
2786         }
2787       } else {
2788         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2789                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2790 
2791         __ ldr(tmp, mdo_addr);
2792         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2793       }
2794 
2795       // different than before. Cannot keep accurate profile.
2796       __ ldr(rscratch2, mdo_addr);
2797       __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2798       __ str(rscratch2, mdo_addr);
2799 
2800       if (TypeEntries::is_type_none(current_klass)) {
2801         __ b(next);
2802 
2803         __ bind(none);
2804         // first time here. Set profile type.
2805         __ str(tmp, mdo_addr);
2806       }
2807     } else {
2808       // There's a single possible klass at this profile point
2809       assert(exact_klass != NULL, "should be");
2810       if (TypeEntries::is_type_none(current_klass)) {
2811         __ mov_metadata(tmp, exact_klass->constant_encoding());
2812         __ ldr(rscratch2, mdo_addr);
2813         __ eor(tmp, tmp, rscratch2);
2814         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2815         __ cbz(rscratch1, next);
2816 #ifdef ASSERT
2817         {
2818           Label ok;
2819           __ ldr(rscratch1, mdo_addr);
2820           __ cbz(rscratch1, ok);
2821           __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2822           __ br(Assembler::EQ, ok);
2823           // may have been set by another thread
2824           __ dmb(Assembler::ISHLD);
2825           __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2826           __ ldr(rscratch2, mdo_addr);
2827           __ eor(rscratch2, rscratch1, rscratch2);
2828           __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2829           __ cbz(rscratch2, ok);
2830 
2831           __ stop("unexpected profiling mismatch");
2832           __ bind(ok);
2833         }
2834 #endif
2835         // first time here. Set profile type.
2836         __ str(tmp, mdo_addr);
2837       } else {
2838         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2839                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2840 
2841         __ ldr(tmp, mdo_addr);
2842         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2843 
2844         __ orr(tmp, tmp, TypeEntries::type_unknown);
2845         __ str(tmp, mdo_addr);
2846         // FIXME: Write barrier needed here?
2847       }
2848     }
2849 
2850     __ bind(next);
2851   }
2852   COMMENT("} emit_profile_type");
2853 }
2854 




















2855 
2856 void LIR_Assembler::align_backward_branch_target() {
2857 }
2858 
2859 
2860 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2861   // tmp must be unused
2862   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2863 
2864   if (left->is_single_cpu()) {
2865     assert(dest->is_single_cpu(), "expect single result reg");
2866     __ negw(dest->as_register(), left->as_register());
2867   } else if (left->is_double_cpu()) {
2868     assert(dest->is_double_cpu(), "expect double result reg");
2869     __ neg(dest->as_register_lo(), left->as_register_lo());
2870   } else if (left->is_single_fpu()) {
2871     assert(dest->is_single_fpu(), "expect single float result reg");
2872     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2873   } else {
2874     assert(left->is_double_fpu(), "expect double float operand reg");
2875     assert(dest->is_double_fpu(), "expect double float result reg");
2876     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2877   }
2878 }
2879 
2880 
2881 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2882   if (patch_code != lir_patch_none) {
2883     deoptimize_trap(info);
2884     return;
2885   }
2886 
2887   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2888 }
2889 
2890 
2891 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2892   assert(!tmp->is_valid(), "don't need temporary");
2893 
2894   CodeBlob *cb = CodeCache::find_blob(dest);
2895   if (cb) {
2896     __ far_call(RuntimeAddress(dest));
2897   } else {
2898     __ mov(rscratch1, RuntimeAddress(dest));
2899     __ blr(rscratch1);
2900   }
2901 
2902   if (info != NULL) {
2903     add_call_info_here(info);
2904   }
2905 }
2906 
2907 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2908   if (dest->is_address() || src->is_address()) {
2909     move_op(src, dest, type, lir_patch_none, info,
2910             /*pop_fpu_stack*/false, /*wide*/false);
2911   } else {
2912     ShouldNotReachHere();
2913   }
2914 }
2915 
2916 #ifdef ASSERT
2917 // emit run-time assertion
2918 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2919   assert(op->code() == lir_assert, "must be");
2920 
2921   if (op->in_opr1()->is_valid()) {
2922     assert(op->in_opr2()->is_valid(), "both operands must be valid");
2923     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2924   } else {
2925     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2926     assert(op->condition() == lir_cond_always, "no other conditions allowed");
2927   }
2928 
2929   Label ok;
2930   if (op->condition() != lir_cond_always) {
2931     Assembler::Condition acond = Assembler::AL;
2932     switch (op->condition()) {
2933       case lir_cond_equal:        acond = Assembler::EQ;  break;
2934       case lir_cond_notEqual:     acond = Assembler::NE;  break;
2935       case lir_cond_less:         acond = Assembler::LT;  break;
2936       case lir_cond_lessEqual:    acond = Assembler::LE;  break;
2937       case lir_cond_greaterEqual: acond = Assembler::GE;  break;
2938       case lir_cond_greater:      acond = Assembler::GT;  break;
2939       case lir_cond_belowEqual:   acond = Assembler::LS;  break;
2940       case lir_cond_aboveEqual:   acond = Assembler::HS;  break;
2941       default:                    ShouldNotReachHere();
2942     }
2943     __ br(acond, ok);
2944   }
2945   if (op->halt()) {
2946     const char* str = __ code_string(op->msg());
2947     __ stop(str);
2948   } else {
2949     breakpoint();
2950   }
2951   __ bind(ok);
2952 }
2953 #endif
2954 
2955 #ifndef PRODUCT
2956 #define COMMENT(x)   do { __ block_comment(x); } while (0)
2957 #else
2958 #define COMMENT(x)
2959 #endif
2960 
2961 void LIR_Assembler::membar() {
2962   COMMENT("membar");
2963   __ membar(MacroAssembler::AnyAny);
2964 }
2965 
2966 void LIR_Assembler::membar_acquire() {
2967   __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2968 }
2969 
2970 void LIR_Assembler::membar_release() {
2971   __ membar(Assembler::LoadStore|Assembler::StoreStore);
2972 }
2973 
2974 void LIR_Assembler::membar_loadload() {
2975   __ membar(Assembler::LoadLoad);
2976 }
2977 
2978 void LIR_Assembler::membar_storestore() {
2979   __ membar(MacroAssembler::StoreStore);
2980 }
2981 
2982 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2983 
2984 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2985 
2986 void LIR_Assembler::on_spin_wait() {
2987   Unimplemented();
2988 }
2989 
2990 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2991   __ mov(result_reg->as_register(), rthread);
2992 }
2993 




2994 
2995 void LIR_Assembler::peephole(LIR_List *lir) {
2996 #if 0
2997   if (tableswitch_count >= max_tableswitches)
2998     return;
2999 
3000   /*
3001     This finite-state automaton recognizes sequences of compare-and-
3002     branch instructions.  We will turn them into a tableswitch.  You
3003     could argue that C1 really shouldn't be doing this sort of
3004     optimization, but without it the code is really horrible.
3005   */
3006 
3007   enum { start_s, cmp1_s, beq_s, cmp_s } state;
3008   int first_key, last_key = -2147483648;
3009   int next_key = 0;
3010   int start_insn = -1;
3011   int last_insn = -1;
3012   Register reg = noreg;
3013   LIR_Opr reg_opr;
3014   state = start_s;
3015 
3016   LIR_OpList* inst = lir->instructions_list();
3017   for (int i = 0; i < inst->length(); i++) {
3018     LIR_Op* op = inst->at(i);
3019     switch (state) {
3020     case start_s:
3021       first_key = -1;
3022       start_insn = i;
3023       switch (op->code()) {
3024       case lir_cmp:
3025         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3026         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3027         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3028             && opr2->is_constant()
3029             && opr2->type() == T_INT) {
3030           reg_opr = opr1;
3031           reg = opr1->as_register();
3032           first_key = opr2->as_constant_ptr()->as_jint();
3033           next_key = first_key + 1;
3034           state = cmp_s;
3035           goto next_state;
3036         }
3037         break;
3038       }
3039       break;
3040     case cmp_s:
3041       switch (op->code()) {
3042       case lir_branch:
3043         if (op->as_OpBranch()->cond() == lir_cond_equal) {
3044           state = beq_s;
3045           last_insn = i;
3046           goto next_state;
3047         }
3048       }
3049       state = start_s;
3050       break;
3051     case beq_s:
3052       switch (op->code()) {
3053       case lir_cmp: {
3054         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3055         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3056         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3057             && opr1->as_register() == reg
3058             && opr2->is_constant()
3059             && opr2->type() == T_INT
3060             && opr2->as_constant_ptr()->as_jint() == next_key) {
3061           last_key = next_key;
3062           next_key++;
3063           state = cmp_s;
3064           goto next_state;
3065         }
3066       }
3067       }
3068       last_key = next_key;
3069       state = start_s;
3070       break;
3071     default:
3072       assert(false, "impossible state");
3073     }
3074     if (state == start_s) {
3075       if (first_key < last_key - 5L && reg != noreg) {
3076         {
3077           // printf("found run register %d starting at insn %d low value %d high value %d\n",
3078           //        reg->encoding(),
3079           //        start_insn, first_key, last_key);
3080           //   for (int i = 0; i < inst->length(); i++) {
3081           //     inst->at(i)->print();
3082           //     tty->print("\n");
3083           //   }
3084           //   tty->print("\n");
3085         }
3086 
3087         struct tableswitch *sw = &switches[tableswitch_count];
3088         sw->_insn_index = start_insn, sw->_first_key = first_key,
3089           sw->_last_key = last_key, sw->_reg = reg;
3090         inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3091         {
3092           // Insert the new table of branches
3093           int offset = last_insn;
3094           for (int n = first_key; n < last_key; n++) {
3095             inst->insert_before
3096               (last_insn + 1,
3097                new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3098                                 inst->at(offset)->as_OpBranch()->label()));
3099             offset -= 2, i++;
3100           }
3101         }
3102         // Delete all the old compare-and-branch instructions
3103         for (int n = first_key; n < last_key; n++) {
3104           inst->remove_at(start_insn);
3105           inst->remove_at(start_insn);
3106         }
3107         // Insert the tableswitch instruction
3108         inst->insert_before(start_insn,
3109                             new LIR_Op2(lir_cmp, lir_cond_always,
3110                                         LIR_OprFact::intConst(tableswitch_count),
3111                                         reg_opr));
3112         inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3113         tableswitch_count++;
3114       }
3115       reg = noreg;
3116       last_key = -2147483648;
3117     }
3118   next_state:
3119     ;
3120   }
3121 #endif
3122 }
3123 
3124 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3125   Address addr = as_Address(src->as_address_ptr());
3126   BasicType type = src->type();
3127   bool is_oop = is_reference_type(type);
3128 
3129   void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3130   void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3131 
3132   switch(type) {
3133   case T_INT:
3134     xchg = &MacroAssembler::atomic_xchgalw;
3135     add = &MacroAssembler::atomic_addalw;
3136     break;
3137   case T_LONG:
3138     xchg = &MacroAssembler::atomic_xchgal;
3139     add = &MacroAssembler::atomic_addal;
3140     break;

3141   case T_OBJECT:
3142   case T_ARRAY:
3143     if (UseCompressedOops) {
3144       xchg = &MacroAssembler::atomic_xchgalw;
3145       add = &MacroAssembler::atomic_addalw;
3146     } else {
3147       xchg = &MacroAssembler::atomic_xchgal;
3148       add = &MacroAssembler::atomic_addal;
3149     }
3150     break;
3151   default:
3152     ShouldNotReachHere();
3153     xchg = &MacroAssembler::atomic_xchgal;
3154     add = &MacroAssembler::atomic_addal; // unreachable
3155   }
3156 
3157   switch (code) {
3158   case lir_xadd:
3159     {
3160       RegisterOrConstant inc;
3161       Register tmp = as_reg(tmp_op);
3162       Register dst = as_reg(dest);
3163       if (data->is_constant()) {
3164         inc = RegisterOrConstant(as_long(data));
3165         assert_different_registers(dst, addr.base(), tmp,
3166                                    rscratch1, rscratch2);
3167       } else {
3168         inc = RegisterOrConstant(as_reg(data));
3169         assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3170                                    rscratch1, rscratch2);
3171       }
3172       __ lea(tmp, addr);
3173       (_masm->*add)(dst, inc, tmp);
3174       break;
3175     }
3176   case lir_xchg:
3177     {
3178       Register tmp = tmp_op->as_register();
3179       Register obj = as_reg(data);
3180       Register dst = as_reg(dest);
3181       if (is_oop && UseCompressedOops) {
3182         __ encode_heap_oop(rscratch2, obj);
3183         obj = rscratch2;
3184       }
3185       assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3186       __ lea(tmp, addr);
3187       (_masm->*xchg)(dst, obj, tmp);
3188       if (is_oop && UseCompressedOops) {
3189         __ decode_heap_oop(dst);
3190       }
3191     }
3192     break;
3193   default:
3194     ShouldNotReachHere();
3195   }
3196   __ membar(__ AnyAny);
3197 }
3198 
3199 #undef __
--- EOF ---