1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "code/compiledIC.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/gc_globals.hpp"
39 #include "nativeInst_aarch64.hpp"
40 #include "oops/objArrayKlass.hpp"
41 #include "runtime/frame.inline.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "runtime/stubRoutines.hpp"
44 #include "utilities/powerOfTwo.hpp"
45 #include "vmreg_aarch64.inline.hpp"
46
47
48 #ifndef PRODUCT
49 #define COMMENT(x) do { __ block_comment(x); } while (0)
50 #else
51 #define COMMENT(x)
52 #endif
53
54 NEEDS_CLEANUP // remove this definitions ?
55 const Register SYNC_header = r0; // synchronization header
56 const Register SHIFT_count = r0; // where count for shift operations must be
57
58 #define __ _masm->
59
60
61 static void select_different_registers(Register preserve,
62 Register extra,
63 Register &tmp1,
64 Register &tmp2) {
65 if (tmp1 == preserve) {
66 assert_different_registers(tmp1, tmp2, extra);
67 tmp1 = extra;
68 } else if (tmp2 == preserve) {
69 assert_different_registers(tmp1, tmp2, extra);
70 tmp2 = extra;
71 }
72 assert_different_registers(preserve, tmp1, tmp2);
73 }
74
75
76
77 static void select_different_registers(Register preserve,
78 Register extra,
79 Register &tmp1,
80 Register &tmp2,
81 Register &tmp3) {
82 if (tmp1 == preserve) {
83 assert_different_registers(tmp1, tmp2, tmp3, extra);
84 tmp1 = extra;
85 } else if (tmp2 == preserve) {
86 assert_different_registers(tmp1, tmp2, tmp3, extra);
87 tmp2 = extra;
88 } else if (tmp3 == preserve) {
89 assert_different_registers(tmp1, tmp2, tmp3, extra);
90 tmp3 = extra;
91 }
92 assert_different_registers(preserve, tmp1, tmp2, tmp3);
93 }
94
95
96 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
97
98
99 LIR_Opr LIR_Assembler::receiverOpr() {
100 return FrameMap::receiver_opr;
101 }
102
103 LIR_Opr LIR_Assembler::osrBufferPointer() {
104 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
105 }
106
107 //--------------fpu register translations-----------------------
108
109
110 address LIR_Assembler::float_constant(float f) {
111 address const_addr = __ float_constant(f);
112 if (const_addr == nullptr) {
113 bailout("const section overflow");
114 return __ code()->consts()->start();
115 } else {
116 return const_addr;
117 }
118 }
119
120
121 address LIR_Assembler::double_constant(double d) {
122 address const_addr = __ double_constant(d);
123 if (const_addr == nullptr) {
124 bailout("const section overflow");
125 return __ code()->consts()->start();
126 } else {
127 return const_addr;
128 }
129 }
130
131 address LIR_Assembler::int_constant(jlong n) {
132 address const_addr = __ long_constant(n);
133 if (const_addr == nullptr) {
134 bailout("const section overflow");
135 return __ code()->consts()->start();
136 } else {
137 return const_addr;
138 }
139 }
140
141 void LIR_Assembler::breakpoint() { Unimplemented(); }
142
143 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
144
145 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
146
147 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
148 //-------------------------------------------
149
150 static Register as_reg(LIR_Opr op) {
151 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
152 }
153
154 static jlong as_long(LIR_Opr data) {
155 jlong result;
156 switch (data->type()) {
157 case T_INT:
158 result = (data->as_jint());
159 break;
160 case T_LONG:
161 result = (data->as_jlong());
162 break;
163 default:
164 ShouldNotReachHere();
165 result = 0; // unreachable
166 }
167 return result;
168 }
169
170 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
171 Register base = addr->base()->as_pointer_register();
172 LIR_Opr opr = addr->index();
173 if (opr->is_cpu_register()) {
174 Register index;
175 if (opr->is_single_cpu())
176 index = opr->as_register();
177 else
178 index = opr->as_register_lo();
179 assert(addr->disp() == 0, "must be");
180 switch(opr->type()) {
181 case T_INT:
182 return Address(base, index, Address::sxtw(addr->scale()));
183 case T_LONG:
184 return Address(base, index, Address::lsl(addr->scale()));
185 default:
186 ShouldNotReachHere();
187 }
188 } else {
189 assert(addr->scale() == 0,
190 "expected for immediate operand, was: %d", addr->scale());
191 ptrdiff_t offset = ptrdiff_t(addr->disp());
192 // NOTE: Does not handle any 16 byte vector access.
193 const uint type_size = type2aelembytes(addr->type(), true);
194 return __ legitimize_address(Address(base, offset), type_size, tmp);
195 }
196 return Address();
197 }
198
199 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
200 ShouldNotReachHere();
201 return Address();
202 }
203
204 Address LIR_Assembler::as_Address(LIR_Address* addr) {
205 return as_Address(addr, rscratch1);
206 }
207
208 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
209 return as_Address(addr, rscratch1); // Ouch
210 // FIXME: This needs to be much more clever. See x86.
211 }
212
213 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
214 // not encodable as a base + (immediate) offset, generate an explicit address
215 // calculation to hold the address in a temporary register.
216 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
217 precond(size == 4 || size == 8);
218 Address addr = frame_map()->address_for_slot(index, adjust);
219 precond(addr.getMode() == Address::base_plus_offset);
220 precond(addr.base() == sp);
221 precond(addr.offset() > 0);
222 uint mask = size - 1;
223 assert((addr.offset() & mask) == 0, "scaled offsets only");
224 return __ legitimize_address(addr, size, tmp);
225 }
226
227 void LIR_Assembler::osr_entry() {
228 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
229 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
230 ValueStack* entry_state = osr_entry->state();
231 int number_of_locks = entry_state->locks_size();
232
233 // we jump here if osr happens with the interpreter
234 // state set up to continue at the beginning of the
235 // loop that triggered osr - in particular, we have
236 // the following registers setup:
237 //
238 // r2: osr buffer
239 //
240
241 // build frame
242 ciMethod* m = compilation()->method();
243 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
244
245 // OSR buffer is
246 //
247 // locals[nlocals-1..0]
248 // monitors[0..number_of_locks]
249 //
250 // locals is a direct copy of the interpreter frame so in the osr buffer
251 // so first slot in the local array is the last local from the interpreter
252 // and last slot is local[0] (receiver) from the interpreter
253 //
254 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
255 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
256 // in the interpreter frame (the method lock if a sync method)
257
258 // Initialize monitors in the compiled activation.
259 // r2: pointer to osr buffer
260 //
261 // All other registers are dead at this point and the locals will be
262 // copied into place by code emitted in the IR.
263
264 Register OSR_buf = osrBufferPointer()->as_pointer_register();
265 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
266 int monitor_offset = BytesPerWord * method()->max_locals() +
267 (2 * BytesPerWord) * (number_of_locks - 1);
268 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
269 // the OSR buffer using 2 word entries: first the lock and then
270 // the oop.
271 for (int i = 0; i < number_of_locks; i++) {
272 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
273 #ifdef ASSERT
274 // verify the interpreter's monitor has a non-null object
275 {
276 Label L;
277 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
278 __ cbnz(rscratch1, L);
279 __ stop("locked object is null");
280 __ bind(L);
281 }
282 #endif
283 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
284 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
285 __ str(r19, frame_map()->address_for_monitor_lock(i));
286 __ str(r20, frame_map()->address_for_monitor_object(i));
287 }
288 }
289 }
290
291
292 // inline cache check; done before the frame is built.
293 int LIR_Assembler::check_icache() {
294 return __ ic_check(CodeEntryAlignment);
295 }
296
297 void LIR_Assembler::clinit_barrier(ciMethod* method) {
298 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
299 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
300
301 Label L_skip_barrier;
302
303 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
304 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
305 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
306 __ bind(L_skip_barrier);
307 }
308
309 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
310 if (o == nullptr) {
311 __ mov(reg, zr);
312 } else {
313 __ movoop(reg, o);
314 }
315 }
316
317 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
318 address target = nullptr;
319 relocInfo::relocType reloc_type = relocInfo::none;
320
321 switch (patching_id(info)) {
322 case PatchingStub::access_field_id:
323 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
324 reloc_type = relocInfo::section_word_type;
325 break;
326 case PatchingStub::load_klass_id:
327 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
328 reloc_type = relocInfo::metadata_type;
329 break;
330 case PatchingStub::load_mirror_id:
331 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
332 reloc_type = relocInfo::oop_type;
333 break;
334 case PatchingStub::load_appendix_id:
335 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
336 reloc_type = relocInfo::oop_type;
337 break;
338 default: ShouldNotReachHere();
339 }
340
341 __ far_call(RuntimeAddress(target));
342 add_call_info_here(info);
343 }
344
345 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
346 deoptimize_trap(info);
347 }
348
349
350 // This specifies the rsp decrement needed to build the frame
351 int LIR_Assembler::initial_frame_size_in_bytes() const {
352 // if rounding, must let FrameMap know!
353
354 return in_bytes(frame_map()->framesize_in_bytes());
355 }
356
357
358 int LIR_Assembler::emit_exception_handler() {
359 // generate code for exception handler
360 address handler_base = __ start_a_stub(exception_handler_size());
361 if (handler_base == nullptr) {
362 // not enough space left for the handler
363 bailout("exception handler overflow");
364 return -1;
365 }
366
367 int offset = code_offset();
368
369 // the exception oop and pc are in r0, and r3
370 // no other registers need to be preserved, so invalidate them
371 __ invalidate_registers(false, true, true, false, true, true);
372
373 // check that there is really an exception
374 __ verify_not_null_oop(r0);
375
376 // search an exception handler (r0: exception oop, r3: throwing pc)
377 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
378 __ should_not_reach_here();
379 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
380 __ end_a_stub();
381
382 return offset;
383 }
384
385
386 // Emit the code to remove the frame from the stack in the exception
387 // unwind path.
388 int LIR_Assembler::emit_unwind_handler() {
389 #ifndef PRODUCT
390 if (CommentedAssembly) {
391 _masm->block_comment("Unwind handler");
392 }
393 #endif
394
395 int offset = code_offset();
396
397 // Fetch the exception from TLS and clear out exception related thread state
398 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
399 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
400 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
401
402 __ bind(_unwind_handler_entry);
403 __ verify_not_null_oop(r0);
404 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
405 __ mov(r19, r0); // Preserve the exception
406 }
407
408 // Perform needed unlocking
409 MonitorExitStub* stub = nullptr;
410 if (method()->is_synchronized()) {
411 monitor_address(0, FrameMap::r0_opr);
412 stub = new MonitorExitStub(FrameMap::r0_opr, 0);
413 __ unlock_object(r5, r4, r0, r6, *stub->entry());
414 __ bind(*stub->continuation());
415 }
416
417 if (compilation()->env()->dtrace_method_probes()) {
418 __ mov(c_rarg0, rthread);
419 __ mov_metadata(c_rarg1, method()->constant_encoding());
420 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
421 }
422
423 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
424 __ mov(r0, r19); // Restore the exception
425 }
426
427 // remove the activation and dispatch to the unwind handler
428 __ block_comment("remove_frame and dispatch to the unwind handler");
429 __ remove_frame(initial_frame_size_in_bytes());
430 __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
431
432 // Emit the slow path assembly
433 if (stub != nullptr) {
434 stub->emit_code(this);
435 }
436
437 return offset;
438 }
439
440
441 int LIR_Assembler::emit_deopt_handler() {
442 // generate code for exception handler
443 address handler_base = __ start_a_stub(deopt_handler_size());
444 if (handler_base == nullptr) {
445 // not enough space left for the handler
446 bailout("deopt handler overflow");
447 return -1;
448 }
449
450 int offset = code_offset();
451
452 Label start;
453 __ bind(start);
454
455 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
456
457 int entry_offset = __ offset();
458 __ b(start);
459
460 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
461 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
462 "out of bounds read in post-call NOP check");
463 __ end_a_stub();
464
465 return entry_offset;
466 }
467
468 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
469 _masm->code_section()->relocate(adr, relocInfo::poll_type);
470 int pc_offset = code_offset();
471 flush_debug_info(pc_offset);
472 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
473 if (info->exception_handlers() != nullptr) {
474 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
475 }
476 }
477
478 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
479 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
480
481 // Pop the stack before the safepoint code
482 __ remove_frame(initial_frame_size_in_bytes());
483
484 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
485 __ reserved_stack_check();
486 }
487
488 code_stub->set_safepoint_offset(__ offset());
489 __ relocate(relocInfo::poll_return_type);
490 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
491 __ ret(lr);
492 }
493
494 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
495 guarantee(info != nullptr, "Shouldn't be null");
496 __ get_polling_page(rscratch1, relocInfo::poll_type);
497 add_debug_info_for_branch(info); // This isn't just debug info:
498 // it's the oop map
499 __ read_polling_page(rscratch1, relocInfo::poll_type);
500 return __ offset();
501 }
502
503
504 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
505 if (from_reg == r31_sp)
506 from_reg = sp;
507 if (to_reg == r31_sp)
508 to_reg = sp;
509 __ mov(to_reg, from_reg);
510 }
511
512 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
513
514
515 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
516 assert(src->is_constant(), "should not call otherwise");
517 assert(dest->is_register(), "should not call otherwise");
518 LIR_Const* c = src->as_constant_ptr();
519
520 switch (c->type()) {
521 case T_INT: {
522 assert(patch_code == lir_patch_none, "no patching handled here");
523 __ movw(dest->as_register(), c->as_jint());
524 break;
525 }
526
527 case T_ADDRESS: {
528 assert(patch_code == lir_patch_none, "no patching handled here");
529 __ mov(dest->as_register(), c->as_jint());
530 break;
531 }
532
533 case T_LONG: {
534 assert(patch_code == lir_patch_none, "no patching handled here");
535 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
536 break;
537 }
538
539 case T_OBJECT: {
540 if (patch_code == lir_patch_none) {
541 jobject2reg(c->as_jobject(), dest->as_register());
542 } else {
543 jobject2reg_with_patching(dest->as_register(), info);
544 }
545 break;
546 }
547
548 case T_METADATA: {
549 if (patch_code != lir_patch_none) {
550 klass2reg_with_patching(dest->as_register(), info);
551 } else {
552 __ mov_metadata(dest->as_register(), c->as_metadata());
553 }
554 break;
555 }
556
557 case T_FLOAT: {
558 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
559 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
560 } else {
561 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
562 __ ldrs(dest->as_float_reg(), Address(rscratch1));
563 }
564 break;
565 }
566
567 case T_DOUBLE: {
568 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
569 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
570 } else {
571 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
572 __ ldrd(dest->as_double_reg(), Address(rscratch1));
573 }
574 break;
575 }
576
577 default:
578 ShouldNotReachHere();
579 }
580 }
581
582 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
583 LIR_Const* c = src->as_constant_ptr();
584 switch (c->type()) {
585 case T_OBJECT:
586 {
587 if (! c->as_jobject())
588 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
589 else {
590 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
591 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
592 }
593 }
594 break;
595 case T_ADDRESS:
596 {
597 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
598 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
599 }
600 case T_INT:
601 case T_FLOAT:
602 {
603 Register reg = zr;
604 if (c->as_jint_bits() == 0)
605 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
606 else {
607 __ movw(rscratch1, c->as_jint_bits());
608 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
609 }
610 }
611 break;
612 case T_LONG:
613 case T_DOUBLE:
614 {
615 Register reg = zr;
616 if (c->as_jlong_bits() == 0)
617 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
618 lo_word_offset_in_bytes));
619 else {
620 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
621 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
622 lo_word_offset_in_bytes));
623 }
624 }
625 break;
626 default:
627 ShouldNotReachHere();
628 }
629 }
630
631 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
632 assert(src->is_constant(), "should not call otherwise");
633 LIR_Const* c = src->as_constant_ptr();
634 LIR_Address* to_addr = dest->as_address_ptr();
635
636 void (Assembler::* insn)(Register Rt, const Address &adr);
637
638 switch (type) {
639 case T_ADDRESS:
640 assert(c->as_jint() == 0, "should be");
641 insn = &Assembler::str;
642 break;
643 case T_LONG:
644 assert(c->as_jlong() == 0, "should be");
645 insn = &Assembler::str;
646 break;
647 case T_INT:
648 assert(c->as_jint() == 0, "should be");
649 insn = &Assembler::strw;
650 break;
651 case T_OBJECT:
652 case T_ARRAY:
653 assert(c->as_jobject() == nullptr, "should be");
654 if (UseCompressedOops && !wide) {
655 insn = &Assembler::strw;
656 } else {
657 insn = &Assembler::str;
658 }
659 break;
660 case T_CHAR:
661 case T_SHORT:
662 assert(c->as_jint() == 0, "should be");
663 insn = &Assembler::strh;
664 break;
665 case T_BOOLEAN:
666 case T_BYTE:
667 assert(c->as_jint() == 0, "should be");
668 insn = &Assembler::strb;
669 break;
670 default:
671 ShouldNotReachHere();
672 insn = &Assembler::str; // unreachable
673 }
674
675 if (info) add_debug_info_for_null_check_here(info);
676 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
677 }
678
679 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
680 assert(src->is_register(), "should not call otherwise");
681 assert(dest->is_register(), "should not call otherwise");
682
683 // move between cpu-registers
684 if (dest->is_single_cpu()) {
685 if (src->type() == T_LONG) {
686 // Can do LONG -> OBJECT
687 move_regs(src->as_register_lo(), dest->as_register());
688 return;
689 }
690 assert(src->is_single_cpu(), "must match");
691 if (src->type() == T_OBJECT) {
692 __ verify_oop(src->as_register());
693 }
694 move_regs(src->as_register(), dest->as_register());
695
696 } else if (dest->is_double_cpu()) {
697 if (is_reference_type(src->type())) {
698 // Surprising to me but we can see move of a long to t_object
699 __ verify_oop(src->as_register());
700 move_regs(src->as_register(), dest->as_register_lo());
701 return;
702 }
703 assert(src->is_double_cpu(), "must match");
704 Register f_lo = src->as_register_lo();
705 Register f_hi = src->as_register_hi();
706 Register t_lo = dest->as_register_lo();
707 Register t_hi = dest->as_register_hi();
708 assert(f_hi == f_lo, "must be same");
709 assert(t_hi == t_lo, "must be same");
710 move_regs(f_lo, t_lo);
711
712 } else if (dest->is_single_fpu()) {
713 __ fmovs(dest->as_float_reg(), src->as_float_reg());
714
715 } else if (dest->is_double_fpu()) {
716 __ fmovd(dest->as_double_reg(), src->as_double_reg());
717
718 } else {
719 ShouldNotReachHere();
720 }
721 }
722
723 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
724 precond(src->is_register() && dest->is_stack());
725
726 uint const c_sz32 = sizeof(uint32_t);
727 uint const c_sz64 = sizeof(uint64_t);
728
729 if (src->is_single_cpu()) {
730 int index = dest->single_stack_ix();
731 if (is_reference_type(type)) {
732 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
733 __ verify_oop(src->as_register());
734 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
735 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
736 } else {
737 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
738 }
739
740 } else if (src->is_double_cpu()) {
741 int index = dest->double_stack_ix();
742 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
743 __ str(src->as_register_lo(), dest_addr_LO);
744
745 } else if (src->is_single_fpu()) {
746 int index = dest->single_stack_ix();
747 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
748
749 } else if (src->is_double_fpu()) {
750 int index = dest->double_stack_ix();
751 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
752
753 } else {
754 ShouldNotReachHere();
755 }
756 }
757
758
759 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
760 LIR_Address* to_addr = dest->as_address_ptr();
761 PatchingStub* patch = nullptr;
762 Register compressed_src = rscratch1;
763
764 if (patch_code != lir_patch_none) {
765 deoptimize_trap(info);
766 return;
767 }
768
769 if (is_reference_type(type)) {
770 __ verify_oop(src->as_register());
771
772 if (UseCompressedOops && !wide) {
773 __ encode_heap_oop(compressed_src, src->as_register());
774 } else {
775 compressed_src = src->as_register();
776 }
777 }
778
779 int null_check_here = code_offset();
780 switch (type) {
781 case T_FLOAT: {
782 __ strs(src->as_float_reg(), as_Address(to_addr));
783 break;
784 }
785
786 case T_DOUBLE: {
787 __ strd(src->as_double_reg(), as_Address(to_addr));
788 break;
789 }
790
791 case T_ARRAY: // fall through
792 case T_OBJECT: // fall through
793 if (UseCompressedOops && !wide) {
794 __ strw(compressed_src, as_Address(to_addr, rscratch2));
795 } else {
796 __ str(compressed_src, as_Address(to_addr));
797 }
798 break;
799 case T_METADATA:
800 // We get here to store a method pointer to the stack to pass to
801 // a dtrace runtime call. This can't work on 64 bit with
802 // compressed klass ptrs: T_METADATA can be a compressed klass
803 // ptr or a 64 bit method pointer.
804 ShouldNotReachHere();
805 __ str(src->as_register(), as_Address(to_addr));
806 break;
807 case T_ADDRESS:
808 __ str(src->as_register(), as_Address(to_addr));
809 break;
810 case T_INT:
811 __ strw(src->as_register(), as_Address(to_addr));
812 break;
813
814 case T_LONG: {
815 __ str(src->as_register_lo(), as_Address_lo(to_addr));
816 break;
817 }
818
819 case T_BYTE: // fall through
820 case T_BOOLEAN: {
821 __ strb(src->as_register(), as_Address(to_addr));
822 break;
823 }
824
825 case T_CHAR: // fall through
826 case T_SHORT:
827 __ strh(src->as_register(), as_Address(to_addr));
828 break;
829
830 default:
831 ShouldNotReachHere();
832 }
833 if (info != nullptr) {
834 add_debug_info_for_null_check(null_check_here, info);
835 }
836 }
837
838
839 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
840 precond(src->is_stack() && dest->is_register());
841
842 uint const c_sz32 = sizeof(uint32_t);
843 uint const c_sz64 = sizeof(uint64_t);
844
845 if (dest->is_single_cpu()) {
846 int index = src->single_stack_ix();
847 if (is_reference_type(type)) {
848 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
849 __ verify_oop(dest->as_register());
850 } else if (type == T_METADATA || type == T_ADDRESS) {
851 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
852 } else {
853 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
854 }
855
856 } else if (dest->is_double_cpu()) {
857 int index = src->double_stack_ix();
858 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
859 __ ldr(dest->as_register_lo(), src_addr_LO);
860
861 } else if (dest->is_single_fpu()) {
862 int index = src->single_stack_ix();
863 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
864
865 } else if (dest->is_double_fpu()) {
866 int index = src->double_stack_ix();
867 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
868
869 } else {
870 ShouldNotReachHere();
871 }
872 }
873
874
875 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
876 address target = nullptr;
877 relocInfo::relocType reloc_type = relocInfo::none;
878
879 switch (patching_id(info)) {
880 case PatchingStub::access_field_id:
881 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
882 reloc_type = relocInfo::section_word_type;
883 break;
884 case PatchingStub::load_klass_id:
885 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
886 reloc_type = relocInfo::metadata_type;
887 break;
888 case PatchingStub::load_mirror_id:
889 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
890 reloc_type = relocInfo::oop_type;
891 break;
892 case PatchingStub::load_appendix_id:
893 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
894 reloc_type = relocInfo::oop_type;
895 break;
896 default: ShouldNotReachHere();
897 }
898
899 __ far_call(RuntimeAddress(target));
900 add_call_info_here(info);
901 }
902
903 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
904
905 LIR_Opr temp;
906 if (type == T_LONG || type == T_DOUBLE)
907 temp = FrameMap::rscratch1_long_opr;
908 else
909 temp = FrameMap::rscratch1_opr;
910
911 stack2reg(src, temp, src->type());
912 reg2stack(temp, dest, dest->type());
913 }
914
915
916 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
917 LIR_Address* addr = src->as_address_ptr();
918 LIR_Address* from_addr = src->as_address_ptr();
919
920 if (addr->base()->type() == T_OBJECT) {
921 __ verify_oop(addr->base()->as_pointer_register());
922 }
923
924 if (patch_code != lir_patch_none) {
925 deoptimize_trap(info);
926 return;
927 }
928
929 if (info != nullptr) {
930 add_debug_info_for_null_check_here(info);
931 }
932 int null_check_here = code_offset();
933 switch (type) {
934 case T_FLOAT: {
935 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
936 break;
937 }
938
939 case T_DOUBLE: {
940 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
941 break;
942 }
943
944 case T_ARRAY: // fall through
945 case T_OBJECT: // fall through
946 if (UseCompressedOops && !wide) {
947 __ ldrw(dest->as_register(), as_Address(from_addr));
948 } else {
949 __ ldr(dest->as_register(), as_Address(from_addr));
950 }
951 break;
952 case T_METADATA:
953 // We get here to store a method pointer to the stack to pass to
954 // a dtrace runtime call. This can't work on 64 bit with
955 // compressed klass ptrs: T_METADATA can be a compressed klass
956 // ptr or a 64 bit method pointer.
957 ShouldNotReachHere();
958 __ ldr(dest->as_register(), as_Address(from_addr));
959 break;
960 case T_ADDRESS:
961 __ ldr(dest->as_register(), as_Address(from_addr));
962 break;
963 case T_INT:
964 __ ldrw(dest->as_register(), as_Address(from_addr));
965 break;
966
967 case T_LONG: {
968 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
969 break;
970 }
971
972 case T_BYTE:
973 __ ldrsb(dest->as_register(), as_Address(from_addr));
974 break;
975 case T_BOOLEAN: {
976 __ ldrb(dest->as_register(), as_Address(from_addr));
977 break;
978 }
979
980 case T_CHAR:
981 __ ldrh(dest->as_register(), as_Address(from_addr));
982 break;
983 case T_SHORT:
984 __ ldrsh(dest->as_register(), as_Address(from_addr));
985 break;
986
987 default:
988 ShouldNotReachHere();
989 }
990
991 if (is_reference_type(type)) {
992 if (UseCompressedOops && !wide) {
993 __ decode_heap_oop(dest->as_register());
994 }
995
996 __ verify_oop(dest->as_register());
997 }
998 }
999
1000
1001 int LIR_Assembler::array_element_size(BasicType type) const {
1002 int elem_size = type2aelembytes(type);
1003 return exact_log2(elem_size);
1004 }
1005
1006
1007 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1008 switch (op->code()) {
1009 case lir_idiv:
1010 case lir_irem:
1011 arithmetic_idiv(op->code(),
1012 op->in_opr1(),
1013 op->in_opr2(),
1014 op->in_opr3(),
1015 op->result_opr(),
1016 op->info());
1017 break;
1018 case lir_fmad:
1019 __ fmaddd(op->result_opr()->as_double_reg(),
1020 op->in_opr1()->as_double_reg(),
1021 op->in_opr2()->as_double_reg(),
1022 op->in_opr3()->as_double_reg());
1023 break;
1024 case lir_fmaf:
1025 __ fmadds(op->result_opr()->as_float_reg(),
1026 op->in_opr1()->as_float_reg(),
1027 op->in_opr2()->as_float_reg(),
1028 op->in_opr3()->as_float_reg());
1029 break;
1030 default: ShouldNotReachHere(); break;
1031 }
1032 }
1033
1034 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1035 #ifdef ASSERT
1036 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1037 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1038 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1039 #endif
1040
1041 if (op->cond() == lir_cond_always) {
1042 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1043 __ b(*(op->label()));
1044 } else {
1045 Assembler::Condition acond;
1046 if (op->code() == lir_cond_float_branch) {
1047 bool is_unordered = (op->ublock() == op->block());
1048 // Assembler::EQ does not permit unordered branches, so we add
1049 // another branch here. Likewise, Assembler::NE does not permit
1050 // ordered branches.
1051 if ((is_unordered && op->cond() == lir_cond_equal)
1052 || (!is_unordered && op->cond() == lir_cond_notEqual))
1053 __ br(Assembler::VS, *(op->ublock()->label()));
1054 switch(op->cond()) {
1055 case lir_cond_equal: acond = Assembler::EQ; break;
1056 case lir_cond_notEqual: acond = Assembler::NE; break;
1057 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1058 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1059 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1060 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1061 default: ShouldNotReachHere();
1062 acond = Assembler::EQ; // unreachable
1063 }
1064 } else {
1065 switch (op->cond()) {
1066 case lir_cond_equal: acond = Assembler::EQ; break;
1067 case lir_cond_notEqual: acond = Assembler::NE; break;
1068 case lir_cond_less: acond = Assembler::LT; break;
1069 case lir_cond_lessEqual: acond = Assembler::LE; break;
1070 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1071 case lir_cond_greater: acond = Assembler::GT; break;
1072 case lir_cond_belowEqual: acond = Assembler::LS; break;
1073 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1074 default: ShouldNotReachHere();
1075 acond = Assembler::EQ; // unreachable
1076 }
1077 }
1078 __ br(acond,*(op->label()));
1079 }
1080 }
1081
1082
1083
1084 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1085 LIR_Opr src = op->in_opr();
1086 LIR_Opr dest = op->result_opr();
1087
1088 switch (op->bytecode()) {
1089 case Bytecodes::_i2f:
1090 {
1091 __ scvtfws(dest->as_float_reg(), src->as_register());
1092 break;
1093 }
1094 case Bytecodes::_i2d:
1095 {
1096 __ scvtfwd(dest->as_double_reg(), src->as_register());
1097 break;
1098 }
1099 case Bytecodes::_l2d:
1100 {
1101 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1102 break;
1103 }
1104 case Bytecodes::_l2f:
1105 {
1106 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1107 break;
1108 }
1109 case Bytecodes::_f2d:
1110 {
1111 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1112 break;
1113 }
1114 case Bytecodes::_d2f:
1115 {
1116 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1117 break;
1118 }
1119 case Bytecodes::_i2c:
1120 {
1121 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1122 break;
1123 }
1124 case Bytecodes::_i2l:
1125 {
1126 __ sxtw(dest->as_register_lo(), src->as_register());
1127 break;
1128 }
1129 case Bytecodes::_i2s:
1130 {
1131 __ sxth(dest->as_register(), src->as_register());
1132 break;
1133 }
1134 case Bytecodes::_i2b:
1135 {
1136 __ sxtb(dest->as_register(), src->as_register());
1137 break;
1138 }
1139 case Bytecodes::_l2i:
1140 {
1141 _masm->block_comment("FIXME: This could be a no-op");
1142 __ uxtw(dest->as_register(), src->as_register_lo());
1143 break;
1144 }
1145 case Bytecodes::_d2l:
1146 {
1147 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1148 break;
1149 }
1150 case Bytecodes::_f2i:
1151 {
1152 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1153 break;
1154 }
1155 case Bytecodes::_f2l:
1156 {
1157 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1158 break;
1159 }
1160 case Bytecodes::_d2i:
1161 {
1162 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1163 break;
1164 }
1165 default: ShouldNotReachHere();
1166 }
1167 }
1168
1169 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1170 if (op->init_check()) {
1171 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1172 __ ldarb(rscratch1, rscratch1);
1173 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1174 add_debug_info_for_null_check_here(op->stub()->info());
1175 __ br(Assembler::NE, *op->stub()->entry());
1176 }
1177 __ allocate_object(op->obj()->as_register(),
1178 op->tmp1()->as_register(),
1179 op->tmp2()->as_register(),
1180 op->header_size(),
1181 op->object_size(),
1182 op->klass()->as_register(),
1183 *op->stub()->entry());
1184 __ bind(*op->stub()->continuation());
1185 }
1186
1187 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1188 Register len = op->len()->as_register();
1189 __ uxtw(len, len);
1190
1191 if (UseSlowPath ||
1192 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1193 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1194 __ b(*op->stub()->entry());
1195 } else {
1196 Register tmp1 = op->tmp1()->as_register();
1197 Register tmp2 = op->tmp2()->as_register();
1198 Register tmp3 = op->tmp3()->as_register();
1199 if (len == tmp1) {
1200 tmp1 = tmp3;
1201 } else if (len == tmp2) {
1202 tmp2 = tmp3;
1203 } else if (len == tmp3) {
1204 // everything is ok
1205 } else {
1206 __ mov(tmp3, len);
1207 }
1208 __ allocate_array(op->obj()->as_register(),
1209 len,
1210 tmp1,
1211 tmp2,
1212 arrayOopDesc::base_offset_in_bytes(op->type()),
1213 array_element_size(op->type()),
1214 op->klass()->as_register(),
1215 *op->stub()->entry(),
1216 op->zero_array());
1217 }
1218 __ bind(*op->stub()->continuation());
1219 }
1220
1221 void LIR_Assembler::type_profile_helper(Register mdo,
1222 ciMethodData *md, ciProfileData *data,
1223 Register recv, Label* update_done) {
1224
1225 // Given a profile data offset, generate an Address which points to
1226 // the corresponding slot in mdo->data().
1227 // Clobbers rscratch2.
1228 auto slot_at = [=](ByteSize offset) -> Address {
1229 return __ form_address(rscratch2, mdo,
1230 md->byte_offset_of_slot(data, offset),
1231 LogBytesPerWord);
1232 };
1233
1234 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1235 Label next_test;
1236 // See if the receiver is receiver[n].
1237 __ ldr(rscratch1, slot_at(ReceiverTypeData::receiver_offset(i)));
1238 __ cmp(recv, rscratch1);
1239 __ br(Assembler::NE, next_test);
1240 __ addptr(slot_at(ReceiverTypeData::receiver_count_offset(i)),
1241 DataLayout::counter_increment);
1242 __ b(*update_done);
1243 __ bind(next_test);
1244 }
1245
1246 // Didn't find receiver; find next empty slot and fill it in
1247 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1248 Label next_test;
1249 Address recv_addr(slot_at(ReceiverTypeData::receiver_offset(i)));
1250 __ ldr(rscratch1, recv_addr);
1251 __ cbnz(rscratch1, next_test);
1252 __ str(recv, recv_addr);
1253 __ mov(rscratch1, DataLayout::counter_increment);
1254 __ str(rscratch1, slot_at(ReceiverTypeData::receiver_count_offset(i)));
1255 __ b(*update_done);
1256 __ bind(next_test);
1257 }
1258 }
1259
1260 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1261 // we always need a stub for the failure case.
1262 CodeStub* stub = op->stub();
1263 Register obj = op->object()->as_register();
1264 Register k_RInfo = op->tmp1()->as_register();
1265 Register klass_RInfo = op->tmp2()->as_register();
1266 Register dst = op->result_opr()->as_register();
1267 ciKlass* k = op->klass();
1268 Register Rtmp1 = noreg;
1269
1270 // check if it needs to be profiled
1271 ciMethodData* md;
1272 ciProfileData* data;
1273
1274 const bool should_profile = op->should_profile();
1275
1276 if (should_profile) {
1277 ciMethod* method = op->profiled_method();
1278 assert(method != nullptr, "Should have method");
1279 int bci = op->profiled_bci();
1280 md = method->method_data_or_null();
1281 assert(md != nullptr, "Sanity");
1282 data = md->bci_to_data(bci);
1283 assert(data != nullptr, "need data for type check");
1284 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1285 }
1286 Label* success_target = success;
1287 Label* failure_target = failure;
1288
1289 if (obj == k_RInfo) {
1290 k_RInfo = dst;
1291 } else if (obj == klass_RInfo) {
1292 klass_RInfo = dst;
1293 }
1294 if (k->is_loaded() && !UseCompressedClassPointers) {
1295 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1296 } else {
1297 Rtmp1 = op->tmp3()->as_register();
1298 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1299 }
1300
1301 assert_different_registers(obj, k_RInfo, klass_RInfo);
1302
1303 if (should_profile) {
1304 Register mdo = klass_RInfo;
1305 __ mov_metadata(mdo, md->constant_encoding());
1306 Label not_null;
1307 __ cbnz(obj, not_null);
1308 // Object is null; update MDO and exit
1309 Address data_addr
1310 = __ form_address(rscratch2, mdo,
1311 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1312 0);
1313 __ ldrb(rscratch1, data_addr);
1314 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1315 __ strb(rscratch1, data_addr);
1316 __ b(*obj_is_null);
1317 __ bind(not_null);
1318
1319 Label update_done;
1320 Register recv = k_RInfo;
1321 __ load_klass(recv, obj);
1322 type_profile_helper(mdo, md, data, recv, &update_done);
1323 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1324 __ addptr(counter_addr, DataLayout::counter_increment);
1325
1326 __ bind(update_done);
1327 } else {
1328 __ cbz(obj, *obj_is_null);
1329 }
1330
1331 if (!k->is_loaded()) {
1332 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1333 } else {
1334 __ mov_metadata(k_RInfo, k->constant_encoding());
1335 }
1336 __ verify_oop(obj);
1337
1338 if (op->fast_check()) {
1339 // get object class
1340 // not a safepoint as obj null check happens earlier
1341 __ load_klass(rscratch1, obj);
1342 __ cmp( rscratch1, k_RInfo);
1343
1344 __ br(Assembler::NE, *failure_target);
1345 // successful cast, fall through to profile or jump
1346 } else {
1347 // get object class
1348 // not a safepoint as obj null check happens earlier
1349 __ load_klass(klass_RInfo, obj);
1350 if (k->is_loaded()) {
1351 // See if we get an immediate positive hit
1352 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1353 __ cmp(k_RInfo, rscratch1);
1354 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1355 __ br(Assembler::NE, *failure_target);
1356 // successful cast, fall through to profile or jump
1357 } else {
1358 // See if we get an immediate positive hit
1359 __ br(Assembler::EQ, *success_target);
1360 // check for self
1361 __ cmp(klass_RInfo, k_RInfo);
1362 __ br(Assembler::EQ, *success_target);
1363
1364 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1365 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1366 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1367 // result is a boolean
1368 __ cbzw(klass_RInfo, *failure_target);
1369 // successful cast, fall through to profile or jump
1370 }
1371 } else {
1372 // perform the fast part of the checking logic
1373 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1374 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1375 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1376 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1377 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1378 // result is a boolean
1379 __ cbz(k_RInfo, *failure_target);
1380 // successful cast, fall through to profile or jump
1381 }
1382 }
1383 __ b(*success);
1384 }
1385
1386
1387 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1388 const bool should_profile = op->should_profile();
1389
1390 LIR_Code code = op->code();
1391 if (code == lir_store_check) {
1392 Register value = op->object()->as_register();
1393 Register array = op->array()->as_register();
1394 Register k_RInfo = op->tmp1()->as_register();
1395 Register klass_RInfo = op->tmp2()->as_register();
1396 Register Rtmp1 = op->tmp3()->as_register();
1397
1398 CodeStub* stub = op->stub();
1399
1400 // check if it needs to be profiled
1401 ciMethodData* md;
1402 ciProfileData* data;
1403
1404 if (should_profile) {
1405 ciMethod* method = op->profiled_method();
1406 assert(method != nullptr, "Should have method");
1407 int bci = op->profiled_bci();
1408 md = method->method_data_or_null();
1409 assert(md != nullptr, "Sanity");
1410 data = md->bci_to_data(bci);
1411 assert(data != nullptr, "need data for type check");
1412 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1413 }
1414 Label done;
1415 Label* success_target = &done;
1416 Label* failure_target = stub->entry();
1417
1418 if (should_profile) {
1419 Label not_null;
1420 Register mdo = klass_RInfo;
1421 __ mov_metadata(mdo, md->constant_encoding());
1422 __ cbnz(value, not_null);
1423 // Object is null; update MDO and exit
1424 Address data_addr
1425 = __ form_address(rscratch2, mdo,
1426 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1427 __ ldrb(rscratch1, data_addr);
1428 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1429 __ strb(rscratch1, data_addr);
1430 __ b(done);
1431 __ bind(not_null);
1432
1433 Label update_done;
1434 Register recv = k_RInfo;
1435 __ load_klass(recv, value);
1436 type_profile_helper(mdo, md, data, recv, &update_done);
1437 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1438 __ addptr(counter_addr, DataLayout::counter_increment);
1439 __ bind(update_done);
1440 } else {
1441 __ cbz(value, done);
1442 }
1443
1444 add_debug_info_for_null_check_here(op->info_for_exception());
1445 __ load_klass(k_RInfo, array);
1446 __ load_klass(klass_RInfo, value);
1447
1448 // get instance klass (it's already uncompressed)
1449 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1450 // perform the fast part of the checking logic
1451 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1452 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1453 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1454 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1455 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1456 // result is a boolean
1457 __ cbzw(k_RInfo, *failure_target);
1458 // fall through to the success case
1459
1460 __ bind(done);
1461 } else if (code == lir_checkcast) {
1462 Register obj = op->object()->as_register();
1463 Register dst = op->result_opr()->as_register();
1464 Label success;
1465 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1466 __ bind(success);
1467 if (dst != obj) {
1468 __ mov(dst, obj);
1469 }
1470 } else if (code == lir_instanceof) {
1471 Register obj = op->object()->as_register();
1472 Register dst = op->result_opr()->as_register();
1473 Label success, failure, done;
1474 emit_typecheck_helper(op, &success, &failure, &failure);
1475 __ bind(failure);
1476 __ mov(dst, zr);
1477 __ b(done);
1478 __ bind(success);
1479 __ mov(dst, 1);
1480 __ bind(done);
1481 } else {
1482 ShouldNotReachHere();
1483 }
1484 }
1485
1486 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1487 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1488 __ cset(rscratch1, Assembler::NE);
1489 __ membar(__ AnyAny);
1490 }
1491
1492 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1493 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1494 __ cset(rscratch1, Assembler::NE);
1495 __ membar(__ AnyAny);
1496 }
1497
1498
1499 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1500 Register addr;
1501 if (op->addr()->is_register()) {
1502 addr = as_reg(op->addr());
1503 } else {
1504 assert(op->addr()->is_address(), "what else?");
1505 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1506 assert(addr_ptr->disp() == 0, "need 0 disp");
1507 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1508 addr = as_reg(addr_ptr->base());
1509 }
1510 Register newval = as_reg(op->new_value());
1511 Register cmpval = as_reg(op->cmp_value());
1512
1513 if (op->code() == lir_cas_obj) {
1514 if (UseCompressedOops) {
1515 Register t1 = op->tmp1()->as_register();
1516 assert(op->tmp1()->is_valid(), "must be");
1517 __ encode_heap_oop(t1, cmpval);
1518 cmpval = t1;
1519 __ encode_heap_oop(rscratch2, newval);
1520 newval = rscratch2;
1521 casw(addr, newval, cmpval);
1522 } else {
1523 casl(addr, newval, cmpval);
1524 }
1525 } else if (op->code() == lir_cas_int) {
1526 casw(addr, newval, cmpval);
1527 } else {
1528 casl(addr, newval, cmpval);
1529 }
1530 }
1531
1532
1533 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1534 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1535 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1536
1537 Assembler::Condition acond, ncond;
1538 switch (condition) {
1539 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1540 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1541 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1542 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1543 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1544 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1545 case lir_cond_belowEqual:
1546 case lir_cond_aboveEqual:
1547 default: ShouldNotReachHere();
1548 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1549 }
1550
1551 assert(result->is_single_cpu() || result->is_double_cpu(),
1552 "expect single register for result");
1553 if (opr1->is_constant() && opr2->is_constant()
1554 && opr1->type() == T_INT && opr2->type() == T_INT) {
1555 jint val1 = opr1->as_jint();
1556 jint val2 = opr2->as_jint();
1557 if (val1 == 0 && val2 == 1) {
1558 __ cset(result->as_register(), ncond);
1559 return;
1560 } else if (val1 == 1 && val2 == 0) {
1561 __ cset(result->as_register(), acond);
1562 return;
1563 }
1564 }
1565
1566 if (opr1->is_constant() && opr2->is_constant()
1567 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1568 jlong val1 = opr1->as_jlong();
1569 jlong val2 = opr2->as_jlong();
1570 if (val1 == 0 && val2 == 1) {
1571 __ cset(result->as_register_lo(), ncond);
1572 return;
1573 } else if (val1 == 1 && val2 == 0) {
1574 __ cset(result->as_register_lo(), acond);
1575 return;
1576 }
1577 }
1578
1579 if (opr1->is_stack()) {
1580 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1581 opr1 = FrameMap::rscratch1_opr;
1582 } else if (opr1->is_constant()) {
1583 LIR_Opr tmp
1584 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1585 const2reg(opr1, tmp, lir_patch_none, nullptr);
1586 opr1 = tmp;
1587 }
1588
1589 if (opr2->is_stack()) {
1590 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1591 opr2 = FrameMap::rscratch2_opr;
1592 } else if (opr2->is_constant()) {
1593 LIR_Opr tmp
1594 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1595 const2reg(opr2, tmp, lir_patch_none, nullptr);
1596 opr2 = tmp;
1597 }
1598
1599 if (result->type() == T_LONG)
1600 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1601 else
1602 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1603 }
1604
1605 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1606 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1607
1608 if (left->is_single_cpu()) {
1609 Register lreg = left->as_register();
1610 Register dreg = as_reg(dest);
1611
1612 if (right->is_single_cpu()) {
1613 // cpu register - cpu register
1614
1615 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1616 "should be");
1617 Register rreg = right->as_register();
1618 switch (code) {
1619 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1620 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1621 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1622 default: ShouldNotReachHere();
1623 }
1624
1625 } else if (right->is_double_cpu()) {
1626 Register rreg = right->as_register_lo();
1627 // single_cpu + double_cpu: can happen with obj+long
1628 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1629 switch (code) {
1630 case lir_add: __ add(dreg, lreg, rreg); break;
1631 case lir_sub: __ sub(dreg, lreg, rreg); break;
1632 default: ShouldNotReachHere();
1633 }
1634 } else if (right->is_constant()) {
1635 // cpu register - constant
1636 jlong c;
1637
1638 // FIXME. This is fugly: we really need to factor all this logic.
1639 switch(right->type()) {
1640 case T_LONG:
1641 c = right->as_constant_ptr()->as_jlong();
1642 break;
1643 case T_INT:
1644 case T_ADDRESS:
1645 c = right->as_constant_ptr()->as_jint();
1646 break;
1647 default:
1648 ShouldNotReachHere();
1649 c = 0; // unreachable
1650 break;
1651 }
1652
1653 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1654 if (c == 0 && dreg == lreg) {
1655 COMMENT("effective nop elided");
1656 return;
1657 }
1658 switch(left->type()) {
1659 case T_INT:
1660 switch (code) {
1661 case lir_add: __ addw(dreg, lreg, c); break;
1662 case lir_sub: __ subw(dreg, lreg, c); break;
1663 default: ShouldNotReachHere();
1664 }
1665 break;
1666 case T_OBJECT:
1667 case T_ADDRESS:
1668 switch (code) {
1669 case lir_add: __ add(dreg, lreg, c); break;
1670 case lir_sub: __ sub(dreg, lreg, c); break;
1671 default: ShouldNotReachHere();
1672 }
1673 break;
1674 default:
1675 ShouldNotReachHere();
1676 }
1677 } else {
1678 ShouldNotReachHere();
1679 }
1680
1681 } else if (left->is_double_cpu()) {
1682 Register lreg_lo = left->as_register_lo();
1683
1684 if (right->is_double_cpu()) {
1685 // cpu register - cpu register
1686 Register rreg_lo = right->as_register_lo();
1687 switch (code) {
1688 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1689 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1690 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1691 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1692 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1693 default:
1694 ShouldNotReachHere();
1695 }
1696
1697 } else if (right->is_constant()) {
1698 jlong c = right->as_constant_ptr()->as_jlong();
1699 Register dreg = as_reg(dest);
1700 switch (code) {
1701 case lir_add:
1702 case lir_sub:
1703 if (c == 0 && dreg == lreg_lo) {
1704 COMMENT("effective nop elided");
1705 return;
1706 }
1707 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1708 break;
1709 case lir_div:
1710 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1711 if (c == 1) {
1712 // move lreg_lo to dreg if divisor is 1
1713 __ mov(dreg, lreg_lo);
1714 } else {
1715 unsigned int shift = log2i_exact(c);
1716 // use rscratch1 as intermediate result register
1717 __ asr(rscratch1, lreg_lo, 63);
1718 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1719 __ asr(dreg, rscratch1, shift);
1720 }
1721 break;
1722 case lir_rem:
1723 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1724 if (c == 1) {
1725 // move 0 to dreg if divisor is 1
1726 __ mov(dreg, zr);
1727 } else {
1728 // use rscratch1 as intermediate result register
1729 __ negs(rscratch1, lreg_lo);
1730 __ andr(dreg, lreg_lo, c - 1);
1731 __ andr(rscratch1, rscratch1, c - 1);
1732 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1733 }
1734 break;
1735 default:
1736 ShouldNotReachHere();
1737 }
1738 } else {
1739 ShouldNotReachHere();
1740 }
1741 } else if (left->is_single_fpu()) {
1742 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1743 switch (code) {
1744 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1745 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1746 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1747 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1748 default:
1749 ShouldNotReachHere();
1750 }
1751 } else if (left->is_double_fpu()) {
1752 if (right->is_double_fpu()) {
1753 // fpu register - fpu register
1754 switch (code) {
1755 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1756 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1757 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1758 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1759 default:
1760 ShouldNotReachHere();
1761 }
1762 } else {
1763 if (right->is_constant()) {
1764 ShouldNotReachHere();
1765 }
1766 ShouldNotReachHere();
1767 }
1768 } else if (left->is_single_stack() || left->is_address()) {
1769 assert(left == dest, "left and dest must be equal");
1770 ShouldNotReachHere();
1771 } else {
1772 ShouldNotReachHere();
1773 }
1774 }
1775
1776 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1777 switch(code) {
1778 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1779 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1780 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1781 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1782 default : ShouldNotReachHere();
1783 }
1784 }
1785
1786 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1787
1788 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1789 Register Rleft = left->is_single_cpu() ? left->as_register() :
1790 left->as_register_lo();
1791 if (dst->is_single_cpu()) {
1792 Register Rdst = dst->as_register();
1793 if (right->is_constant()) {
1794 switch (code) {
1795 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1796 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1797 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1798 default: ShouldNotReachHere(); break;
1799 }
1800 } else {
1801 Register Rright = right->is_single_cpu() ? right->as_register() :
1802 right->as_register_lo();
1803 switch (code) {
1804 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1805 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1806 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1807 default: ShouldNotReachHere(); break;
1808 }
1809 }
1810 } else {
1811 Register Rdst = dst->as_register_lo();
1812 if (right->is_constant()) {
1813 switch (code) {
1814 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1815 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1816 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1817 default: ShouldNotReachHere(); break;
1818 }
1819 } else {
1820 Register Rright = right->is_single_cpu() ? right->as_register() :
1821 right->as_register_lo();
1822 switch (code) {
1823 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1824 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1825 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1826 default: ShouldNotReachHere(); break;
1827 }
1828 }
1829 }
1830 }
1831
1832
1833
1834 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1835
1836 // opcode check
1837 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1838 bool is_irem = (code == lir_irem);
1839
1840 // operand check
1841 assert(left->is_single_cpu(), "left must be register");
1842 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1843 assert(result->is_single_cpu(), "result must be register");
1844 Register lreg = left->as_register();
1845 Register dreg = result->as_register();
1846
1847 // power-of-2 constant check and codegen
1848 if (right->is_constant()) {
1849 int c = right->as_constant_ptr()->as_jint();
1850 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1851 if (is_irem) {
1852 if (c == 1) {
1853 // move 0 to dreg if divisor is 1
1854 __ movw(dreg, zr);
1855 } else {
1856 // use rscratch1 as intermediate result register
1857 __ negsw(rscratch1, lreg);
1858 __ andw(dreg, lreg, c - 1);
1859 __ andw(rscratch1, rscratch1, c - 1);
1860 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1861 }
1862 } else {
1863 if (c == 1) {
1864 // move lreg to dreg if divisor is 1
1865 __ movw(dreg, lreg);
1866 } else {
1867 unsigned int shift = exact_log2(c);
1868 // use rscratch1 as intermediate result register
1869 __ asrw(rscratch1, lreg, 31);
1870 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1871 __ asrw(dreg, rscratch1, shift);
1872 }
1873 }
1874 } else {
1875 Register rreg = right->as_register();
1876 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1877 }
1878 }
1879
1880
1881 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1882 if (opr1->is_constant() && opr2->is_single_cpu()) {
1883 // tableswitch
1884 Register reg = as_reg(opr2);
1885 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1886 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1887 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1888 Register reg1 = as_reg(opr1);
1889 if (opr2->is_single_cpu()) {
1890 // cpu register - cpu register
1891 Register reg2 = opr2->as_register();
1892 if (is_reference_type(opr1->type())) {
1893 __ cmpoop(reg1, reg2);
1894 } else {
1895 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1896 __ cmpw(reg1, reg2);
1897 }
1898 return;
1899 }
1900 if (opr2->is_double_cpu()) {
1901 // cpu register - cpu register
1902 Register reg2 = opr2->as_register_lo();
1903 __ cmp(reg1, reg2);
1904 return;
1905 }
1906
1907 if (opr2->is_constant()) {
1908 bool is_32bit = false; // width of register operand
1909 jlong imm;
1910
1911 switch(opr2->type()) {
1912 case T_INT:
1913 imm = opr2->as_constant_ptr()->as_jint();
1914 is_32bit = true;
1915 break;
1916 case T_LONG:
1917 imm = opr2->as_constant_ptr()->as_jlong();
1918 break;
1919 case T_ADDRESS:
1920 imm = opr2->as_constant_ptr()->as_jint();
1921 break;
1922 case T_METADATA:
1923 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1924 break;
1925 case T_OBJECT:
1926 case T_ARRAY:
1927 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1928 __ cmpoop(reg1, rscratch1);
1929 return;
1930 default:
1931 ShouldNotReachHere();
1932 imm = 0; // unreachable
1933 break;
1934 }
1935
1936 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1937 if (is_32bit)
1938 __ cmpw(reg1, imm);
1939 else
1940 __ subs(zr, reg1, imm);
1941 return;
1942 } else {
1943 __ mov(rscratch1, imm);
1944 if (is_32bit)
1945 __ cmpw(reg1, rscratch1);
1946 else
1947 __ cmp(reg1, rscratch1);
1948 return;
1949 }
1950 } else
1951 ShouldNotReachHere();
1952 } else if (opr1->is_single_fpu()) {
1953 FloatRegister reg1 = opr1->as_float_reg();
1954 assert(opr2->is_single_fpu(), "expect single float register");
1955 FloatRegister reg2 = opr2->as_float_reg();
1956 __ fcmps(reg1, reg2);
1957 } else if (opr1->is_double_fpu()) {
1958 FloatRegister reg1 = opr1->as_double_reg();
1959 assert(opr2->is_double_fpu(), "expect double float register");
1960 FloatRegister reg2 = opr2->as_double_reg();
1961 __ fcmpd(reg1, reg2);
1962 } else {
1963 ShouldNotReachHere();
1964 }
1965 }
1966
1967 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1968 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1969 bool is_unordered_less = (code == lir_ucmp_fd2i);
1970 if (left->is_single_fpu()) {
1971 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1972 } else if (left->is_double_fpu()) {
1973 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1974 } else {
1975 ShouldNotReachHere();
1976 }
1977 } else if (code == lir_cmp_l2i) {
1978 Label done;
1979 __ cmp(left->as_register_lo(), right->as_register_lo());
1980 __ mov(dst->as_register(), (uint64_t)-1L);
1981 __ br(Assembler::LT, done);
1982 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1983 __ bind(done);
1984 } else {
1985 ShouldNotReachHere();
1986 }
1987 }
1988
1989
1990 void LIR_Assembler::align_call(LIR_Code code) { }
1991
1992
1993 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
1994 address call = __ trampoline_call(Address(op->addr(), rtype));
1995 if (call == nullptr) {
1996 bailout("trampoline stub overflow");
1997 return;
1998 }
1999 add_call_info(code_offset(), op->info());
2000 __ post_call_nop();
2001 }
2002
2003
2004 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2005 address call = __ ic_call(op->addr());
2006 if (call == nullptr) {
2007 bailout("trampoline stub overflow");
2008 return;
2009 }
2010 add_call_info(code_offset(), op->info());
2011 __ post_call_nop();
2012 }
2013
2014 void LIR_Assembler::emit_static_call_stub() {
2015 address call_pc = __ pc();
2016 address stub = __ start_a_stub(call_stub_size());
2017 if (stub == nullptr) {
2018 bailout("static call stub overflow");
2019 return;
2020 }
2021
2022 int start = __ offset();
2023
2024 __ relocate(static_stub_Relocation::spec(call_pc));
2025 __ emit_static_call_stub();
2026
2027 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2028 <= call_stub_size(), "stub too big");
2029 __ end_a_stub();
2030 }
2031
2032
2033 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2034 assert(exceptionOop->as_register() == r0, "must match");
2035 assert(exceptionPC->as_register() == r3, "must match");
2036
2037 // exception object is not added to oop map by LinearScan
2038 // (LinearScan assumes that no oops are in fixed registers)
2039 info->add_register_oop(exceptionOop);
2040 StubId unwind_id;
2041
2042 // get current pc information
2043 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2044 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2045 // As no instructions have been generated yet for this LIR node it's
2046 // possible that an oop map already exists for the current offset.
2047 // In that case insert an dummy NOP here to ensure all oop map PCs
2048 // are unique. See JDK-8237483.
2049 __ nop();
2050 }
2051 int pc_for_athrow_offset = __ offset();
2052 InternalAddress pc_for_athrow(__ pc());
2053 __ adr(exceptionPC->as_register(), pc_for_athrow);
2054 add_call_info(pc_for_athrow_offset, info); // for exception handler
2055
2056 __ verify_not_null_oop(r0);
2057 // search an exception handler (r0: exception oop, r3: throwing pc)
2058 if (compilation()->has_fpu_code()) {
2059 unwind_id = StubId::c1_handle_exception_id;
2060 } else {
2061 unwind_id = StubId::c1_handle_exception_nofpu_id;
2062 }
2063 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2064
2065 // FIXME: enough room for two byte trap ????
2066 __ nop();
2067 }
2068
2069
2070 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2071 assert(exceptionOop->as_register() == r0, "must match");
2072
2073 __ b(_unwind_handler_entry);
2074 }
2075
2076
2077 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2078 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2079 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2080
2081 switch (left->type()) {
2082 case T_INT: {
2083 switch (code) {
2084 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2085 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2086 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2087 default:
2088 ShouldNotReachHere();
2089 break;
2090 }
2091 break;
2092 case T_LONG:
2093 case T_ADDRESS:
2094 case T_OBJECT:
2095 switch (code) {
2096 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2097 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2098 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2099 default:
2100 ShouldNotReachHere();
2101 break;
2102 }
2103 break;
2104 default:
2105 ShouldNotReachHere();
2106 break;
2107 }
2108 }
2109 }
2110
2111
2112 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2113 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2114 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2115
2116 switch (left->type()) {
2117 case T_INT: {
2118 switch (code) {
2119 case lir_shl: __ lslw (dreg, lreg, count); break;
2120 case lir_shr: __ asrw (dreg, lreg, count); break;
2121 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2122 default:
2123 ShouldNotReachHere();
2124 break;
2125 }
2126 break;
2127 case T_LONG:
2128 case T_ADDRESS:
2129 case T_OBJECT:
2130 switch (code) {
2131 case lir_shl: __ lsl (dreg, lreg, count); break;
2132 case lir_shr: __ asr (dreg, lreg, count); break;
2133 case lir_ushr: __ lsr (dreg, lreg, count); break;
2134 default:
2135 ShouldNotReachHere();
2136 break;
2137 }
2138 break;
2139 default:
2140 ShouldNotReachHere();
2141 break;
2142 }
2143 }
2144 }
2145
2146
2147 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2148 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2149 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2150 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2151 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2152 }
2153
2154
2155 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2156 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2157 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2158 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2159 __ mov (rscratch1, c);
2160 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2161 }
2162
2163
2164 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2165 ShouldNotReachHere();
2166 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2167 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2168 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2169 __ lea(rscratch1, __ constant_oop_address(o));
2170 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2171 }
2172
2173
2174 // This code replaces a call to arraycopy; no exception may
2175 // be thrown in this code, they must be thrown in the System.arraycopy
2176 // activation frame; we could save some checks if this would not be the case
2177 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2178 ciArrayKlass* default_type = op->expected_type();
2179 Register src = op->src()->as_register();
2180 Register dst = op->dst()->as_register();
2181 Register src_pos = op->src_pos()->as_register();
2182 Register dst_pos = op->dst_pos()->as_register();
2183 Register length = op->length()->as_register();
2184 Register tmp = op->tmp()->as_register();
2185
2186 CodeStub* stub = op->stub();
2187 int flags = op->flags();
2188 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2189 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2190
2191 // if we don't know anything, just go through the generic arraycopy
2192 if (default_type == nullptr // || basic_type == T_OBJECT
2193 ) {
2194 Label done;
2195 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2196
2197 // Save the arguments in case the generic arraycopy fails and we
2198 // have to fall back to the JNI stub
2199 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2200 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2201 __ str(src, Address(sp, 4*BytesPerWord));
2202
2203 address copyfunc_addr = StubRoutines::generic_arraycopy();
2204 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2205
2206 // The arguments are in java calling convention so we shift them
2207 // to C convention
2208 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2209 __ mov(c_rarg0, j_rarg0);
2210 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2211 __ mov(c_rarg1, j_rarg1);
2212 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2213 __ mov(c_rarg2, j_rarg2);
2214 assert_different_registers(c_rarg3, j_rarg4);
2215 __ mov(c_rarg3, j_rarg3);
2216 __ mov(c_rarg4, j_rarg4);
2217 #ifndef PRODUCT
2218 if (PrintC1Statistics) {
2219 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2220 }
2221 #endif
2222 __ far_call(RuntimeAddress(copyfunc_addr));
2223
2224 __ cbz(r0, *stub->continuation());
2225
2226 // Reload values from the stack so they are where the stub
2227 // expects them.
2228 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2229 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2230 __ ldr(src, Address(sp, 4*BytesPerWord));
2231
2232 // r0 is -1^K where K == partial copied count
2233 __ eonw(rscratch1, r0, zr);
2234 // adjust length down and src/end pos up by partial copied count
2235 __ subw(length, length, rscratch1);
2236 __ addw(src_pos, src_pos, rscratch1);
2237 __ addw(dst_pos, dst_pos, rscratch1);
2238 __ b(*stub->entry());
2239
2240 __ bind(*stub->continuation());
2241 return;
2242 }
2243
2244 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2245
2246 int elem_size = type2aelembytes(basic_type);
2247 int scale = exact_log2(elem_size);
2248
2249 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2250 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2251
2252 // test for null
2253 if (flags & LIR_OpArrayCopy::src_null_check) {
2254 __ cbz(src, *stub->entry());
2255 }
2256 if (flags & LIR_OpArrayCopy::dst_null_check) {
2257 __ cbz(dst, *stub->entry());
2258 }
2259
2260 // If the compiler was not able to prove that exact type of the source or the destination
2261 // of the arraycopy is an array type, check at runtime if the source or the destination is
2262 // an instance type.
2263 if (flags & LIR_OpArrayCopy::type_check) {
2264 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2265 __ load_klass(tmp, dst);
2266 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2267 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2268 __ br(Assembler::GE, *stub->entry());
2269 }
2270
2271 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2272 __ load_klass(tmp, src);
2273 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2274 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2275 __ br(Assembler::GE, *stub->entry());
2276 }
2277 }
2278
2279 // check if negative
2280 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2281 __ cmpw(src_pos, 0);
2282 __ br(Assembler::LT, *stub->entry());
2283 }
2284 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2285 __ cmpw(dst_pos, 0);
2286 __ br(Assembler::LT, *stub->entry());
2287 }
2288
2289 if (flags & LIR_OpArrayCopy::length_positive_check) {
2290 __ cmpw(length, 0);
2291 __ br(Assembler::LT, *stub->entry());
2292 }
2293
2294 if (flags & LIR_OpArrayCopy::src_range_check) {
2295 __ addw(tmp, src_pos, length);
2296 __ ldrw(rscratch1, src_length_addr);
2297 __ cmpw(tmp, rscratch1);
2298 __ br(Assembler::HI, *stub->entry());
2299 }
2300 if (flags & LIR_OpArrayCopy::dst_range_check) {
2301 __ addw(tmp, dst_pos, length);
2302 __ ldrw(rscratch1, dst_length_addr);
2303 __ cmpw(tmp, rscratch1);
2304 __ br(Assembler::HI, *stub->entry());
2305 }
2306
2307 if (flags & LIR_OpArrayCopy::type_check) {
2308 // We don't know the array types are compatible
2309 if (basic_type != T_OBJECT) {
2310 // Simple test for basic type arrays
2311 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2312 __ br(Assembler::NE, *stub->entry());
2313 } else {
2314 // For object arrays, if src is a sub class of dst then we can
2315 // safely do the copy.
2316 Label cont, slow;
2317
2318 #define PUSH(r1, r2) \
2319 stp(r1, r2, __ pre(sp, -2 * wordSize));
2320
2321 #define POP(r1, r2) \
2322 ldp(r1, r2, __ post(sp, 2 * wordSize));
2323
2324 __ PUSH(src, dst);
2325
2326 __ load_klass(src, src);
2327 __ load_klass(dst, dst);
2328
2329 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2330
2331 __ PUSH(src, dst);
2332 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2333 __ POP(src, dst);
2334
2335 __ cbnz(src, cont);
2336
2337 __ bind(slow);
2338 __ POP(src, dst);
2339
2340 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2341 if (copyfunc_addr != nullptr) { // use stub if available
2342 // src is not a sub class of dst so we have to do a
2343 // per-element check.
2344
2345 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2346 if ((flags & mask) != mask) {
2347 // Check that at least both of them object arrays.
2348 assert(flags & mask, "one of the two should be known to be an object array");
2349
2350 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2351 __ load_klass(tmp, src);
2352 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2353 __ load_klass(tmp, dst);
2354 }
2355 int lh_offset = in_bytes(Klass::layout_helper_offset());
2356 Address klass_lh_addr(tmp, lh_offset);
2357 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2358 __ ldrw(rscratch1, klass_lh_addr);
2359 __ mov(rscratch2, objArray_lh);
2360 __ eorw(rscratch1, rscratch1, rscratch2);
2361 __ cbnzw(rscratch1, *stub->entry());
2362 }
2363
2364 // Spill because stubs can use any register they like and it's
2365 // easier to restore just those that we care about.
2366 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2367 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2368 __ str(src, Address(sp, 4*BytesPerWord));
2369
2370 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2371 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2372 assert_different_registers(c_rarg0, dst, dst_pos, length);
2373 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2374 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2375 assert_different_registers(c_rarg1, dst, length);
2376 __ uxtw(c_rarg2, length);
2377 assert_different_registers(c_rarg2, dst);
2378
2379 __ load_klass(c_rarg4, dst);
2380 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2381 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2382 __ far_call(RuntimeAddress(copyfunc_addr));
2383
2384 #ifndef PRODUCT
2385 if (PrintC1Statistics) {
2386 Label failed;
2387 __ cbnz(r0, failed);
2388 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2389 __ bind(failed);
2390 }
2391 #endif
2392
2393 __ cbz(r0, *stub->continuation());
2394
2395 #ifndef PRODUCT
2396 if (PrintC1Statistics) {
2397 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2398 }
2399 #endif
2400 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2401
2402 // Restore previously spilled arguments
2403 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2404 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2405 __ ldr(src, Address(sp, 4*BytesPerWord));
2406
2407 // return value is -1^K where K is partial copied count
2408 __ eonw(rscratch1, r0, zr);
2409 // adjust length down and src/end pos up by partial copied count
2410 __ subw(length, length, rscratch1);
2411 __ addw(src_pos, src_pos, rscratch1);
2412 __ addw(dst_pos, dst_pos, rscratch1);
2413 }
2414
2415 __ b(*stub->entry());
2416
2417 __ bind(cont);
2418 __ POP(src, dst);
2419 }
2420 }
2421
2422 #ifdef ASSERT
2423 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2424 // Sanity check the known type with the incoming class. For the
2425 // primitive case the types must match exactly with src.klass and
2426 // dst.klass each exactly matching the default type. For the
2427 // object array case, if no type check is needed then either the
2428 // dst type is exactly the expected type and the src type is a
2429 // subtype which we can't check or src is the same array as dst
2430 // but not necessarily exactly of type default_type.
2431 Label known_ok, halt;
2432 __ mov_metadata(tmp, default_type->constant_encoding());
2433
2434 if (basic_type != T_OBJECT) {
2435 __ cmp_klass(dst, tmp, rscratch1);
2436 __ br(Assembler::NE, halt);
2437 __ cmp_klass(src, tmp, rscratch1);
2438 __ br(Assembler::EQ, known_ok);
2439 } else {
2440 __ cmp_klass(dst, tmp, rscratch1);
2441 __ br(Assembler::EQ, known_ok);
2442 __ cmp(src, dst);
2443 __ br(Assembler::EQ, known_ok);
2444 }
2445 __ bind(halt);
2446 __ stop("incorrect type information in arraycopy");
2447 __ bind(known_ok);
2448 }
2449 #endif
2450
2451 #ifndef PRODUCT
2452 if (PrintC1Statistics) {
2453 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2454 }
2455 #endif
2456
2457 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2458 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2459 assert_different_registers(c_rarg0, dst, dst_pos, length);
2460 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2461 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2462 assert_different_registers(c_rarg1, dst, length);
2463 __ uxtw(c_rarg2, length);
2464 assert_different_registers(c_rarg2, dst);
2465
2466 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2467 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2468 const char *name;
2469 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2470
2471 CodeBlob *cb = CodeCache::find_blob(entry);
2472 if (cb) {
2473 __ far_call(RuntimeAddress(entry));
2474 } else {
2475 __ call_VM_leaf(entry, 3);
2476 }
2477
2478 if (stub != nullptr) {
2479 __ bind(*stub->continuation());
2480 }
2481 }
2482
2483
2484
2485
2486 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2487 Register obj = op->obj_opr()->as_register(); // may not be an oop
2488 Register hdr = op->hdr_opr()->as_register();
2489 Register lock = op->lock_opr()->as_register();
2490 Register temp = op->scratch_opr()->as_register();
2491 if (op->code() == lir_lock) {
2492 // add debug info for NullPointerException only if one is possible
2493 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2494 if (op->info() != nullptr) {
2495 add_debug_info_for_null_check(null_check_offset, op->info());
2496 }
2497 // done
2498 } else if (op->code() == lir_unlock) {
2499 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2500 } else {
2501 Unimplemented();
2502 }
2503 __ bind(*op->stub()->continuation());
2504 }
2505
2506 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2507 Register obj = op->obj()->as_pointer_register();
2508 Register result = op->result_opr()->as_pointer_register();
2509
2510 CodeEmitInfo* info = op->info();
2511 if (info != nullptr) {
2512 add_debug_info_for_null_check_here(info);
2513 }
2514
2515 __ load_klass(result, obj);
2516 }
2517
2518 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2519 ciMethod* method = op->profiled_method();
2520 int bci = op->profiled_bci();
2521 ciMethod* callee = op->profiled_callee();
2522
2523 // Update counter for all call types
2524 ciMethodData* md = method->method_data_or_null();
2525 assert(md != nullptr, "Sanity");
2526 ciProfileData* data = md->bci_to_data(bci);
2527 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2528 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2529 Register mdo = op->mdo()->as_register();
2530 __ mov_metadata(mdo, md->constant_encoding());
2531 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2532 // Perform additional virtual call profiling for invokevirtual and
2533 // invokeinterface bytecodes
2534 if (op->should_profile_receiver_type()) {
2535 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2536 Register recv = op->recv()->as_register();
2537 assert_different_registers(mdo, recv);
2538 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2539 ciKlass* known_klass = op->known_holder();
2540 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2541 // We know the type that will be seen at this call site; we can
2542 // statically update the MethodData* rather than needing to do
2543 // dynamic tests on the receiver type
2544
2545 // NOTE: we should probably put a lock around this search to
2546 // avoid collisions by concurrent compilations
2547 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2548 uint i;
2549 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2550 ciKlass* receiver = vc_data->receiver(i);
2551 if (known_klass->equals(receiver)) {
2552 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2553 __ addptr(data_addr, DataLayout::counter_increment);
2554 return;
2555 }
2556 }
2557
2558 // Receiver type not found in profile data; select an empty slot
2559
2560 // Note that this is less efficient than it should be because it
2561 // always does a write to the receiver part of the
2562 // VirtualCallData rather than just the first time
2563 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2564 ciKlass* receiver = vc_data->receiver(i);
2565 if (receiver == nullptr) {
2566 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2567 Address recv_addr =
2568 __ form_address(rscratch2, mdo,
2569 md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)),
2570 LogBytesPerWord);
2571 __ str(rscratch1, recv_addr);
2572 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2573 __ addptr(data_addr, DataLayout::counter_increment);
2574 return;
2575 }
2576 }
2577 } else {
2578 __ load_klass(recv, recv);
2579 Label update_done;
2580 type_profile_helper(mdo, md, data, recv, &update_done);
2581 // Receiver did not match any saved receiver and there is no empty row for it.
2582 // Increment total counter to indicate polymorphic case.
2583 __ addptr(counter_addr, DataLayout::counter_increment);
2584
2585 __ bind(update_done);
2586 }
2587 } else {
2588 // Static call
2589 __ addptr(counter_addr, DataLayout::counter_increment);
2590 }
2591 }
2592
2593
2594 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2595 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2596 }
2597
2598 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2599 assert(op->crc()->is_single_cpu(), "crc must be register");
2600 assert(op->val()->is_single_cpu(), "byte value must be register");
2601 assert(op->result_opr()->is_single_cpu(), "result must be register");
2602 Register crc = op->crc()->as_register();
2603 Register val = op->val()->as_register();
2604 Register res = op->result_opr()->as_register();
2605
2606 assert_different_registers(val, crc, res);
2607 uint64_t offset;
2608 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2609 __ add(res, res, offset);
2610
2611 __ mvnw(crc, crc); // ~crc
2612 __ update_byte_crc32(crc, val, res);
2613 __ mvnw(res, crc); // ~crc
2614 }
2615
2616 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2617 COMMENT("emit_profile_type {");
2618 Register obj = op->obj()->as_register();
2619 Register tmp = op->tmp()->as_pointer_register();
2620 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2621 ciKlass* exact_klass = op->exact_klass();
2622 intptr_t current_klass = op->current_klass();
2623 bool not_null = op->not_null();
2624 bool no_conflict = op->no_conflict();
2625
2626 Label update, next, none;
2627
2628 bool do_null = !not_null;
2629 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2630 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2631
2632 assert(do_null || do_update, "why are we here?");
2633 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2634 assert(mdo_addr.base() != rscratch1, "wrong register");
2635
2636 __ verify_oop(obj);
2637
2638 if (tmp != obj) {
2639 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2640 __ mov(tmp, obj);
2641 } else {
2642 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2643 }
2644 if (do_null) {
2645 __ cbnz(tmp, update);
2646 if (!TypeEntries::was_null_seen(current_klass)) {
2647 __ ldr(rscratch2, mdo_addr);
2648 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2649 __ str(rscratch2, mdo_addr);
2650 }
2651 if (do_update) {
2652 #ifndef ASSERT
2653 __ b(next);
2654 }
2655 #else
2656 __ b(next);
2657 }
2658 } else {
2659 __ cbnz(tmp, update);
2660 __ stop("unexpected null obj");
2661 #endif
2662 }
2663
2664 __ bind(update);
2665
2666 if (do_update) {
2667 #ifdef ASSERT
2668 if (exact_klass != nullptr) {
2669 Label ok;
2670 __ load_klass(tmp, tmp);
2671 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2672 __ eor(rscratch1, tmp, rscratch1);
2673 __ cbz(rscratch1, ok);
2674 __ stop("exact klass and actual klass differ");
2675 __ bind(ok);
2676 }
2677 #endif
2678 if (!no_conflict) {
2679 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2680 if (exact_klass != nullptr) {
2681 __ mov_metadata(tmp, exact_klass->constant_encoding());
2682 } else {
2683 __ load_klass(tmp, tmp);
2684 }
2685
2686 __ ldr(rscratch2, mdo_addr);
2687 __ eor(tmp, tmp, rscratch2);
2688 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2689 // klass seen before, nothing to do. The unknown bit may have been
2690 // set already but no need to check.
2691 __ cbz(rscratch1, next);
2692
2693 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2694
2695 if (TypeEntries::is_type_none(current_klass)) {
2696 __ cbz(rscratch2, none);
2697 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2698 __ br(Assembler::EQ, none);
2699 // There is a chance that the checks above
2700 // fail if another thread has just set the
2701 // profiling to this obj's klass
2702 __ dmb(Assembler::ISHLD);
2703 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2704 __ ldr(rscratch2, mdo_addr);
2705 __ eor(tmp, tmp, rscratch2);
2706 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2707 __ cbz(rscratch1, next);
2708 }
2709 } else {
2710 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2711 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2712
2713 __ ldr(tmp, mdo_addr);
2714 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2715 }
2716
2717 // different than before. Cannot keep accurate profile.
2718 __ ldr(rscratch2, mdo_addr);
2719 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2720 __ str(rscratch2, mdo_addr);
2721
2722 if (TypeEntries::is_type_none(current_klass)) {
2723 __ b(next);
2724
2725 __ bind(none);
2726 // first time here. Set profile type.
2727 __ str(tmp, mdo_addr);
2728 #ifdef ASSERT
2729 __ andr(tmp, tmp, TypeEntries::type_mask);
2730 __ verify_klass_ptr(tmp);
2731 #endif
2732 }
2733 } else {
2734 // There's a single possible klass at this profile point
2735 assert(exact_klass != nullptr, "should be");
2736 if (TypeEntries::is_type_none(current_klass)) {
2737 __ mov_metadata(tmp, exact_klass->constant_encoding());
2738 __ ldr(rscratch2, mdo_addr);
2739 __ eor(tmp, tmp, rscratch2);
2740 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2741 __ cbz(rscratch1, next);
2742 #ifdef ASSERT
2743 {
2744 Label ok;
2745 __ ldr(rscratch1, mdo_addr);
2746 __ cbz(rscratch1, ok);
2747 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2748 __ br(Assembler::EQ, ok);
2749 // may have been set by another thread
2750 __ dmb(Assembler::ISHLD);
2751 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2752 __ ldr(rscratch2, mdo_addr);
2753 __ eor(rscratch2, rscratch1, rscratch2);
2754 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2755 __ cbz(rscratch2, ok);
2756
2757 __ stop("unexpected profiling mismatch");
2758 __ bind(ok);
2759 }
2760 #endif
2761 // first time here. Set profile type.
2762 __ str(tmp, mdo_addr);
2763 #ifdef ASSERT
2764 __ andr(tmp, tmp, TypeEntries::type_mask);
2765 __ verify_klass_ptr(tmp);
2766 #endif
2767 } else {
2768 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2769 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2770
2771 __ ldr(tmp, mdo_addr);
2772 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2773
2774 __ orr(tmp, tmp, TypeEntries::type_unknown);
2775 __ str(tmp, mdo_addr);
2776 // FIXME: Write barrier needed here?
2777 }
2778 }
2779
2780 __ bind(next);
2781 }
2782 COMMENT("} emit_profile_type");
2783 }
2784
2785
2786 void LIR_Assembler::align_backward_branch_target() {
2787 }
2788
2789
2790 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2791 // tmp must be unused
2792 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2793
2794 if (left->is_single_cpu()) {
2795 assert(dest->is_single_cpu(), "expect single result reg");
2796 __ negw(dest->as_register(), left->as_register());
2797 } else if (left->is_double_cpu()) {
2798 assert(dest->is_double_cpu(), "expect double result reg");
2799 __ neg(dest->as_register_lo(), left->as_register_lo());
2800 } else if (left->is_single_fpu()) {
2801 assert(dest->is_single_fpu(), "expect single float result reg");
2802 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2803 } else {
2804 assert(left->is_double_fpu(), "expect double float operand reg");
2805 assert(dest->is_double_fpu(), "expect double float result reg");
2806 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2807 }
2808 }
2809
2810
2811 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2812 if (patch_code != lir_patch_none) {
2813 deoptimize_trap(info);
2814 return;
2815 }
2816
2817 __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
2818 }
2819
2820
2821 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2822 assert(!tmp->is_valid(), "don't need temporary");
2823
2824 CodeBlob *cb = CodeCache::find_blob(dest);
2825 if (cb) {
2826 __ far_call(RuntimeAddress(dest));
2827 } else {
2828 __ mov(rscratch1, RuntimeAddress(dest));
2829 __ blr(rscratch1);
2830 }
2831
2832 if (info != nullptr) {
2833 add_call_info_here(info);
2834 }
2835 __ post_call_nop();
2836 }
2837
2838 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2839 if (dest->is_address() || src->is_address()) {
2840 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
2841 } else {
2842 ShouldNotReachHere();
2843 }
2844 }
2845
2846 #ifdef ASSERT
2847 // emit run-time assertion
2848 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2849 assert(op->code() == lir_assert, "must be");
2850
2851 if (op->in_opr1()->is_valid()) {
2852 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2853 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2854 } else {
2855 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2856 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2857 }
2858
2859 Label ok;
2860 if (op->condition() != lir_cond_always) {
2861 Assembler::Condition acond = Assembler::AL;
2862 switch (op->condition()) {
2863 case lir_cond_equal: acond = Assembler::EQ; break;
2864 case lir_cond_notEqual: acond = Assembler::NE; break;
2865 case lir_cond_less: acond = Assembler::LT; break;
2866 case lir_cond_lessEqual: acond = Assembler::LE; break;
2867 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2868 case lir_cond_greater: acond = Assembler::GT; break;
2869 case lir_cond_belowEqual: acond = Assembler::LS; break;
2870 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2871 default: ShouldNotReachHere();
2872 }
2873 __ br(acond, ok);
2874 }
2875 if (op->halt()) {
2876 const char* str = __ code_string(op->msg());
2877 __ stop(str);
2878 } else {
2879 breakpoint();
2880 }
2881 __ bind(ok);
2882 }
2883 #endif
2884
2885 #ifndef PRODUCT
2886 #define COMMENT(x) do { __ block_comment(x); } while (0)
2887 #else
2888 #define COMMENT(x)
2889 #endif
2890
2891 void LIR_Assembler::membar() {
2892 COMMENT("membar");
2893 __ membar(MacroAssembler::AnyAny);
2894 }
2895
2896 void LIR_Assembler::membar_acquire() {
2897 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2898 }
2899
2900 void LIR_Assembler::membar_release() {
2901 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2902 }
2903
2904 void LIR_Assembler::membar_loadload() {
2905 __ membar(Assembler::LoadLoad);
2906 }
2907
2908 void LIR_Assembler::membar_storestore() {
2909 __ membar(MacroAssembler::StoreStore);
2910 }
2911
2912 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2913
2914 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2915
2916 void LIR_Assembler::on_spin_wait() {
2917 __ spin_wait();
2918 }
2919
2920 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2921 __ mov(result_reg->as_register(), rthread);
2922 }
2923
2924
2925 void LIR_Assembler::peephole(LIR_List *lir) {
2926 #if 0
2927 if (tableswitch_count >= max_tableswitches)
2928 return;
2929
2930 /*
2931 This finite-state automaton recognizes sequences of compare-and-
2932 branch instructions. We will turn them into a tableswitch. You
2933 could argue that C1 really shouldn't be doing this sort of
2934 optimization, but without it the code is really horrible.
2935 */
2936
2937 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2938 int first_key, last_key = -2147483648;
2939 int next_key = 0;
2940 int start_insn = -1;
2941 int last_insn = -1;
2942 Register reg = noreg;
2943 LIR_Opr reg_opr;
2944 state = start_s;
2945
2946 LIR_OpList* inst = lir->instructions_list();
2947 for (int i = 0; i < inst->length(); i++) {
2948 LIR_Op* op = inst->at(i);
2949 switch (state) {
2950 case start_s:
2951 first_key = -1;
2952 start_insn = i;
2953 switch (op->code()) {
2954 case lir_cmp:
2955 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2956 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2957 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2958 && opr2->is_constant()
2959 && opr2->type() == T_INT) {
2960 reg_opr = opr1;
2961 reg = opr1->as_register();
2962 first_key = opr2->as_constant_ptr()->as_jint();
2963 next_key = first_key + 1;
2964 state = cmp_s;
2965 goto next_state;
2966 }
2967 break;
2968 }
2969 break;
2970 case cmp_s:
2971 switch (op->code()) {
2972 case lir_branch:
2973 if (op->as_OpBranch()->cond() == lir_cond_equal) {
2974 state = beq_s;
2975 last_insn = i;
2976 goto next_state;
2977 }
2978 }
2979 state = start_s;
2980 break;
2981 case beq_s:
2982 switch (op->code()) {
2983 case lir_cmp: {
2984 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2985 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2986 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2987 && opr1->as_register() == reg
2988 && opr2->is_constant()
2989 && opr2->type() == T_INT
2990 && opr2->as_constant_ptr()->as_jint() == next_key) {
2991 last_key = next_key;
2992 next_key++;
2993 state = cmp_s;
2994 goto next_state;
2995 }
2996 }
2997 }
2998 last_key = next_key;
2999 state = start_s;
3000 break;
3001 default:
3002 assert(false, "impossible state");
3003 }
3004 if (state == start_s) {
3005 if (first_key < last_key - 5L && reg != noreg) {
3006 {
3007 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3008 // reg->encoding(),
3009 // start_insn, first_key, last_key);
3010 // for (int i = 0; i < inst->length(); i++) {
3011 // inst->at(i)->print();
3012 // tty->print("\n");
3013 // }
3014 // tty->print("\n");
3015 }
3016
3017 struct tableswitch *sw = &switches[tableswitch_count];
3018 sw->_insn_index = start_insn, sw->_first_key = first_key,
3019 sw->_last_key = last_key, sw->_reg = reg;
3020 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3021 {
3022 // Insert the new table of branches
3023 int offset = last_insn;
3024 for (int n = first_key; n < last_key; n++) {
3025 inst->insert_before
3026 (last_insn + 1,
3027 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3028 inst->at(offset)->as_OpBranch()->label()));
3029 offset -= 2, i++;
3030 }
3031 }
3032 // Delete all the old compare-and-branch instructions
3033 for (int n = first_key; n < last_key; n++) {
3034 inst->remove_at(start_insn);
3035 inst->remove_at(start_insn);
3036 }
3037 // Insert the tableswitch instruction
3038 inst->insert_before(start_insn,
3039 new LIR_Op2(lir_cmp, lir_cond_always,
3040 LIR_OprFact::intConst(tableswitch_count),
3041 reg_opr));
3042 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3043 tableswitch_count++;
3044 }
3045 reg = noreg;
3046 last_key = -2147483648;
3047 }
3048 next_state:
3049 ;
3050 }
3051 #endif
3052 }
3053
3054 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3055 Address addr = as_Address(src->as_address_ptr());
3056 BasicType type = src->type();
3057 bool is_oop = is_reference_type(type);
3058
3059 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3060 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3061
3062 switch(type) {
3063 case T_INT:
3064 xchg = &MacroAssembler::atomic_xchgalw;
3065 add = &MacroAssembler::atomic_addalw;
3066 break;
3067 case T_LONG:
3068 xchg = &MacroAssembler::atomic_xchgal;
3069 add = &MacroAssembler::atomic_addal;
3070 break;
3071 case T_OBJECT:
3072 case T_ARRAY:
3073 if (UseCompressedOops) {
3074 xchg = &MacroAssembler::atomic_xchgalw;
3075 add = &MacroAssembler::atomic_addalw;
3076 } else {
3077 xchg = &MacroAssembler::atomic_xchgal;
3078 add = &MacroAssembler::atomic_addal;
3079 }
3080 break;
3081 default:
3082 ShouldNotReachHere();
3083 xchg = &MacroAssembler::atomic_xchgal;
3084 add = &MacroAssembler::atomic_addal; // unreachable
3085 }
3086
3087 switch (code) {
3088 case lir_xadd:
3089 {
3090 RegisterOrConstant inc;
3091 Register tmp = as_reg(tmp_op);
3092 Register dst = as_reg(dest);
3093 if (data->is_constant()) {
3094 inc = RegisterOrConstant(as_long(data));
3095 assert_different_registers(dst, addr.base(), tmp,
3096 rscratch1, rscratch2);
3097 } else {
3098 inc = RegisterOrConstant(as_reg(data));
3099 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3100 rscratch1, rscratch2);
3101 }
3102 __ lea(tmp, addr);
3103 (_masm->*add)(dst, inc, tmp);
3104 break;
3105 }
3106 case lir_xchg:
3107 {
3108 Register tmp = tmp_op->as_register();
3109 Register obj = as_reg(data);
3110 Register dst = as_reg(dest);
3111 if (is_oop && UseCompressedOops) {
3112 __ encode_heap_oop(rscratch2, obj);
3113 obj = rscratch2;
3114 }
3115 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3116 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3117 __ lea(tmp, addr);
3118 (_masm->*xchg)(dst, obj, tmp);
3119 if (is_oop && UseCompressedOops) {
3120 __ decode_heap_oop(dst);
3121 }
3122 }
3123 break;
3124 default:
3125 ShouldNotReachHere();
3126 }
3127 if(!UseLSE) {
3128 __ membar(__ AnyAny);
3129 }
3130 }
3131
3132 #undef __
--- EOF ---