1 /*
2 * Copyright (c) 2020, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
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7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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23 */
24
25 #ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
26 #define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
27
28 // C2_MacroAssembler contains high-level macros for C2
29
30 private:
31 // Return true if the phase output is in the scratch emit size mode.
32 virtual bool in_scratch_emit_size() override;
33
34 void neon_reduce_logical_helper(int opc, bool sf, Register Rd, Register Rn, Register Rm,
35 enum shift_kind kind = Assembler::LSL, unsigned shift = 0);
36
37 void select_from_two_vectors_neon(FloatRegister dst, FloatRegister src1,
38 FloatRegister src2, FloatRegister index,
39 FloatRegister tmp, unsigned vector_length_in_bytes);
40
41 void select_from_two_vectors_sve(FloatRegister dst, FloatRegister src1,
42 FloatRegister src2, FloatRegister index,
43 FloatRegister tmp, SIMD_RegVariant T,
44 unsigned vector_length_in_bytes);
45
46 public:
47 // jdk.internal.util.ArraysSupport.vectorizedHashCode
48 address arrays_hashcode(Register ary, Register cnt, Register result, FloatRegister vdata0,
49 FloatRegister vdata1, FloatRegister vdata2, FloatRegister vdata3,
50 FloatRegister vmul0, FloatRegister vmul1, FloatRegister vmul2,
51 FloatRegister vmul3, FloatRegister vpow, FloatRegister vpowm,
52 BasicType eltype);
53
54 // Code used by cmpFastLockLightweight and cmpFastUnlockLightweight mach instructions in .ad file.
55 void fast_lock_lightweight(Register object, Register box, Register t1, Register t2, Register t3);
56 void fast_unlock_lightweight(Register object, Register box, Register t1, Register t2, Register t3);
57
58 void string_compare(Register str1, Register str2,
59 Register cnt1, Register cnt2, Register result,
60 Register tmp1, Register tmp2, FloatRegister vtmp1,
61 FloatRegister vtmp2, FloatRegister vtmp3,
62 PRegister pgtmp1, PRegister pgtmp2, int ae);
63
64 void string_indexof(Register str1, Register str2,
65 Register cnt1, Register cnt2,
66 Register tmp1, Register tmp2,
67 Register tmp3, Register tmp4,
68 Register tmp5, Register tmp6,
69 int int_cnt1, Register result, int ae);
70
71 void string_indexof_char(Register str1, Register cnt1,
72 Register ch, Register result,
73 Register tmp1, Register tmp2, Register tmp3);
74
75 void stringL_indexof_char(Register str1, Register cnt1,
76 Register ch, Register result,
77 Register tmp1, Register tmp2, Register tmp3);
78
79 void string_indexof_char_sve(Register str1, Register cnt1,
80 Register ch, Register result,
81 FloatRegister ztmp1, FloatRegister ztmp2,
82 PRegister pgtmp, PRegister ptmp, bool isL);
83
84 // Compress the least significant bit of each byte to the rightmost and clear
85 // the higher garbage bits.
86 void bytemask_compress(Register dst);
87
88 // Pack the lowest-numbered bit of each mask element in src into a long value
89 // in dst, at most the first 64 lane elements.
90 void sve_vmask_tolong(Register dst, PRegister src, BasicType bt, int lane_cnt,
91 FloatRegister vtmp1, FloatRegister vtmp2);
92
93 // Unpack the mask, a long value in src, into predicate register dst based on the
94 // corresponding data type. Note that dst can support at most 64 lanes.
95 void sve_vmask_fromlong(PRegister dst, Register src, BasicType bt, int lane_cnt,
96 FloatRegister vtmp1, FloatRegister vtmp2);
97
98 // SIMD&FP comparison
99 void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
100 FloatRegister src2, Condition cond, bool isQ);
101
102 void neon_compare_zero(FloatRegister dst, BasicType bt, FloatRegister src,
103 Condition cond, bool isQ);
104
105 void sve_compare(PRegister pd, BasicType bt, PRegister pg,
106 FloatRegister zn, FloatRegister zm, Condition cond);
107
108 void sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, PRegister ptmp);
109
110 // Vector cast
111 void neon_vector_extend(FloatRegister dst, BasicType dst_bt, unsigned dst_vlen_in_bytes,
112 FloatRegister src, BasicType src_bt, bool is_unsigned = false);
113
114 void neon_vector_narrow(FloatRegister dst, BasicType dst_bt,
115 FloatRegister src, BasicType src_bt, unsigned src_vlen_in_bytes);
116
117 void sve_vector_extend(FloatRegister dst, SIMD_RegVariant dst_size,
118 FloatRegister src, SIMD_RegVariant src_size, bool is_unsigned = false);
119
120 void sve_vector_narrow(FloatRegister dst, SIMD_RegVariant dst_size,
121 FloatRegister src, SIMD_RegVariant src_size, FloatRegister tmp);
122
123 void sve_vmaskcast_extend(PRegister dst, PRegister src,
124 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
125
126 void sve_vmaskcast_narrow(PRegister dst, PRegister src, PRegister ptmp,
127 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
128
129 // Vector reduction
130 void neon_reduce_add_integral(Register dst, BasicType bt,
131 Register isrc, FloatRegister vsrc,
132 unsigned vector_length_in_bytes, FloatRegister vtmp);
133
134 void neon_reduce_mul_integral(Register dst, BasicType bt,
135 Register isrc, FloatRegister vsrc,
136 unsigned vector_length_in_bytes,
137 FloatRegister vtmp1, FloatRegister vtmp2);
138
139 void neon_reduce_mul_fp(FloatRegister dst, BasicType bt,
140 FloatRegister fsrc, FloatRegister vsrc,
141 unsigned vector_length_in_bytes, FloatRegister vtmp);
142
143 void neon_reduce_logical(int opc, Register dst, BasicType bt, Register isrc,
144 FloatRegister vsrc, unsigned vector_length_in_bytes);
145
146 void neon_reduce_minmax_integral(int opc, Register dst, BasicType bt,
147 Register isrc, FloatRegister vsrc,
148 unsigned vector_length_in_bytes, FloatRegister vtmp);
149
150 void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
151 FloatRegister src2, PRegister pg, FloatRegister tmp);
152
153 // Set elements of the dst predicate to true for lanes in the range of
154 // [0, lane_cnt), or to false otherwise. The input "lane_cnt" should be
155 // smaller than or equal to the supported max vector length of the basic
156 // type. Clobbers: rscratch1 and the rFlagsReg.
157 void sve_gen_mask_imm(PRegister dst, BasicType bt, uint32_t lane_cnt);
158
159 // Extract a scalar element from an sve vector at position 'idx'.
160 // The input elements in src are expected to be of integral type.
161 void sve_extract_integral(Register dst, BasicType bt, FloatRegister src,
162 int idx, FloatRegister vtmp);
163
164 // java.lang.Math::round intrinsics
165 void vector_round_neon(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
166 FloatRegister tmp2, FloatRegister tmp3,
167 SIMD_Arrangement T);
168 void vector_round_sve(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
169 FloatRegister tmp2, PRegister pgtmp,
170 SIMD_RegVariant T);
171
172 // Pack active elements of src, under the control of mask, into the
173 // lowest-numbered elements of dst. Any remaining elements of dst will
174 // be filled with zero.
175 void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask,
176 FloatRegister vtmp1, FloatRegister vtmp2,
177 FloatRegister vtmp3, FloatRegister vtmp4,
178 PRegister ptmp, PRegister pgtmp);
179
180 void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
181 FloatRegister vtmp1, FloatRegister vtmp2,
182 PRegister pgtmp);
183
184 void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
185
186 void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
187
188 void neon_rearrange_hsd(FloatRegister dst, FloatRegister src, FloatRegister shuffle,
189 FloatRegister tmp, BasicType bt, bool isQ);
190 // java.lang.Math::signum intrinsics
191 void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
192 FloatRegister one, SIMD_Arrangement T);
193
194 void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
195 FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
196
197 void verify_int_in_range(uint idx, const TypeInt* t, Register val, Register tmp);
198 void verify_long_in_range(uint idx, const TypeLong* t, Register val, Register tmp);
199
200 void reconstruct_frame_pointer(Register rtmp);
201
202 // Select from a table of two vectors
203 void select_from_two_vectors(FloatRegister dst, FloatRegister src1, FloatRegister src2,
204 FloatRegister index, FloatRegister tmp, BasicType bt,
205 unsigned vector_length_in_bytes);
206
207 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP