1 /*
2 * Copyright (c) 2020, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
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7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
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23 */
24
25 #ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
26 #define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
27
28 // C2_MacroAssembler contains high-level macros for C2
29
30 private:
31 // Return true if the phase output is in the scratch emit size mode.
32 virtual bool in_scratch_emit_size() override;
33
34 void neon_reduce_logical_helper(int opc, bool sf, Register Rd, Register Rn, Register Rm,
35 enum shift_kind kind = Assembler::LSL, unsigned shift = 0);
36
37 void select_from_two_vectors_neon(FloatRegister dst, FloatRegister src1,
38 FloatRegister src2, FloatRegister index,
39 FloatRegister tmp, unsigned vector_length_in_bytes);
40
41 void select_from_two_vectors_sve(FloatRegister dst, FloatRegister src1,
42 FloatRegister src2, FloatRegister index,
43 FloatRegister tmp, SIMD_RegVariant T,
44 unsigned vector_length_in_bytes);
45
46 public:
47 // jdk.internal.util.ArraysSupport.vectorizedHashCode
48 address arrays_hashcode(Register ary, Register cnt, Register result, FloatRegister vdata0,
49 FloatRegister vdata1, FloatRegister vdata2, FloatRegister vdata3,
50 FloatRegister vmul0, FloatRegister vmul1, FloatRegister vmul2,
51 FloatRegister vmul3, FloatRegister vpow, FloatRegister vpowm,
52 BasicType eltype);
53
54 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
55 void fast_lock(Register object, Register box, Register t1, Register t2, Register t3);
56 void fast_unlock(Register object, Register box, Register t1, Register t2, Register t3);
57
58 void string_compare(Register str1, Register str2,
59 Register cnt1, Register cnt2, Register result,
60 Register tmp1, Register tmp2, FloatRegister vtmp1,
61 FloatRegister vtmp2, FloatRegister vtmp3,
62 PRegister pgtmp1, PRegister pgtmp2, int ae);
63
64 void string_indexof(Register str1, Register str2,
65 Register cnt1, Register cnt2,
66 Register tmp1, Register tmp2,
67 Register tmp3, Register tmp4,
68 Register tmp5, Register tmp6,
69 int int_cnt1, Register result, int ae);
70
71 void string_indexof_char(Register str1, Register cnt1,
72 Register ch, Register result,
73 Register tmp1, Register tmp2, Register tmp3);
74
75 void stringL_indexof_char(Register str1, Register cnt1,
76 Register ch, Register result,
77 Register tmp1, Register tmp2, Register tmp3);
78
79 void string_indexof_char_sve(Register str1, Register cnt1,
80 Register ch, Register result,
81 FloatRegister ztmp1, FloatRegister ztmp2,
82 PRegister pgtmp, PRegister ptmp, bool isL);
83
84 // Compress the least significant bit of each byte to the rightmost and clear
85 // the higher garbage bits.
86 void bytemask_compress(Register dst);
87
88 // Pack the value of each mask element in "src" into a long value in "dst", at most the
89 // first 64 lane elements. The input "src" is a vector of boolean represented as bytes
90 // with 0x00/0x01 as element values. Each lane value from "src" is packed into one bit in
91 // "dst".
92 void sve_vmask_tolong(Register dst, FloatRegister src, FloatRegister vtmp, int lane_cnt);
93
94 void sve2_vmask_tolong(Register dst, FloatRegister src, FloatRegister vtmp1,
95 FloatRegister vtmp2, int lane_cnt);
96
97 // Unpack the mask, a long value in "src", into vector register "dst" with boolean type.
98 // Each bit in "src" is unpacked into one byte lane in "dst". Note that "dst" can support
99 // at most 64 lanes.
100 void sve_vmask_fromlong(FloatRegister dst, Register src, FloatRegister vtmp, int lane_cnt);
101
102 // SIMD&FP comparison
103 void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
104 FloatRegister src2, Condition cond, bool isQ);
105
106 void neon_compare_zero(FloatRegister dst, BasicType bt, FloatRegister src,
107 Condition cond, bool isQ);
108
109 void sve_compare(PRegister pd, BasicType bt, PRegister pg,
110 FloatRegister zn, FloatRegister zm, Condition cond);
111
112 void sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, PRegister ptmp);
113
114 // Vector cast
115 void neon_vector_extend(FloatRegister dst, BasicType dst_bt, unsigned dst_vlen_in_bytes,
116 FloatRegister src, BasicType src_bt, bool is_unsigned = false);
117
118 void neon_vector_narrow(FloatRegister dst, BasicType dst_bt,
119 FloatRegister src, BasicType src_bt, unsigned src_vlen_in_bytes);
120
121 void sve_vector_extend(FloatRegister dst, SIMD_RegVariant dst_size,
122 FloatRegister src, SIMD_RegVariant src_size, bool is_unsigned = false);
123
124 void sve_vector_narrow(FloatRegister dst, SIMD_RegVariant dst_size,
125 FloatRegister src, SIMD_RegVariant src_size, FloatRegister tmp);
126
127 void sve_vmaskcast_extend(PRegister dst, PRegister src,
128 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
129
130 void sve_vmaskcast_narrow(PRegister dst, PRegister src, PRegister ptmp,
131 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
132
133 // Vector reduction
134 void neon_reduce_add_integral(Register dst, BasicType bt,
135 Register isrc, FloatRegister vsrc,
136 unsigned vector_length_in_bytes, FloatRegister vtmp);
137
138 void neon_reduce_mul_integral(Register dst, BasicType bt,
139 Register isrc, FloatRegister vsrc,
140 unsigned vector_length_in_bytes,
141 FloatRegister vtmp1, FloatRegister vtmp2);
142
143 void neon_reduce_mul_fp(FloatRegister dst, BasicType bt,
144 FloatRegister fsrc, FloatRegister vsrc,
145 unsigned vector_length_in_bytes, FloatRegister vtmp);
146
147 void neon_reduce_logical(int opc, Register dst, BasicType bt, Register isrc,
148 FloatRegister vsrc, unsigned vector_length_in_bytes);
149
150 void neon_reduce_minmax_integral(int opc, Register dst, BasicType bt,
151 Register isrc, FloatRegister vsrc,
152 unsigned vector_length_in_bytes, FloatRegister vtmp);
153
154 void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
155 FloatRegister src2, PRegister pg, FloatRegister tmp);
156
157 // Set elements of the dst predicate to true for lanes in the range of
158 // [0, lane_cnt), or to false otherwise. The input "lane_cnt" should be
159 // smaller than or equal to the supported max vector length of the basic
160 // type. Clobbers: rscratch1 and the rFlagsReg.
161 void sve_gen_mask_imm(PRegister dst, BasicType bt, uint32_t lane_cnt);
162
163 // Extract a scalar element from an sve vector at position 'idx'.
164 // The input elements in src are expected to be of integral type.
165 void sve_extract_integral(Register dst, BasicType bt, FloatRegister src,
166 int idx, FloatRegister vtmp);
167
168 // java.lang.Math::round intrinsics
169 void vector_round_neon(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
170 FloatRegister tmp2, FloatRegister tmp3,
171 SIMD_Arrangement T);
172 void vector_round_sve(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
173 FloatRegister tmp2, PRegister pgtmp,
174 SIMD_RegVariant T);
175
176 // Pack active elements of src, under the control of mask, into the
177 // lowest-numbered elements of dst. Any remaining elements of dst will
178 // be filled with zero.
179 void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask,
180 FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3,
181 PRegister ptmp, PRegister pgtmp, unsigned vector_length_in_bytes);
182
183 void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
184 FloatRegister vzr, FloatRegister vtmp,
185 PRegister pgtmp, unsigned vector_length_in_bytes);
186
187 void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
188
189 void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
190
191 void neon_rearrange_hsd(FloatRegister dst, FloatRegister src, FloatRegister shuffle,
192 FloatRegister tmp, BasicType bt, bool isQ);
193 // java.lang.Math::signum intrinsics
194 void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
195 FloatRegister one, SIMD_Arrangement T);
196
197 void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
198 FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
199
200 void verify_int_in_range(uint idx, const TypeInt* t, Register val, Register tmp);
201 void verify_long_in_range(uint idx, const TypeLong* t, Register val, Register tmp);
202
203 void reconstruct_frame_pointer(Register rtmp);
204
205 // Select from a table of two vectors
206 void select_from_two_vectors(FloatRegister dst, FloatRegister src1, FloatRegister src2,
207 FloatRegister index, FloatRegister tmp, BasicType bt,
208 unsigned vector_length_in_bytes);
209
210 void vector_expand_neon(FloatRegister dst, FloatRegister src, FloatRegister mask,
211 FloatRegister tmp1, FloatRegister tmp2, BasicType bt,
212 int vector_length_in_bytes);
213 void vector_expand_sve(FloatRegister dst, FloatRegister src, PRegister pg,
214 FloatRegister tmp1, FloatRegister tmp2, BasicType bt,
215 int vector_length_in_bytes);
216 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP