1 /* 2 * Copyright (c) 2020, 2022, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP 26 #define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP 27 28 // C2_MacroAssembler contains high-level macros for C2 29 30 private: 31 // Return true if the phase output is in the scratch emit size mode. 32 virtual bool in_scratch_emit_size() override; 33 34 void neon_reduce_logical_helper(int opc, bool sf, Register Rd, Register Rn, Register Rm, 35 enum shift_kind kind = Assembler::LSL, unsigned shift = 0); 36 37 public: 38 void entry_barrier(); 39 void emit_entry_barrier_stub(C2EntryBarrierStub* stub); 40 static int entry_barrier_stub_size(); 41 42 void string_compare(Register str1, Register str2, 43 Register cnt1, Register cnt2, Register result, 44 Register tmp1, Register tmp2, FloatRegister vtmp1, 45 FloatRegister vtmp2, FloatRegister vtmp3, 46 PRegister pgtmp1, PRegister pgtmp2, int ae); 47 48 void string_indexof(Register str1, Register str2, 49 Register cnt1, Register cnt2, 50 Register tmp1, Register tmp2, 51 Register tmp3, Register tmp4, 52 Register tmp5, Register tmp6, 53 int int_cnt1, Register result, int ae); 54 55 void string_indexof_char(Register str1, Register cnt1, 56 Register ch, Register result, 57 Register tmp1, Register tmp2, Register tmp3); 58 59 void stringL_indexof_char(Register str1, Register cnt1, 60 Register ch, Register result, 61 Register tmp1, Register tmp2, Register tmp3); 62 63 void string_indexof_char_sve(Register str1, Register cnt1, 64 Register ch, Register result, 65 FloatRegister ztmp1, FloatRegister ztmp2, 66 PRegister pgtmp, PRegister ptmp, bool isL); 67 68 // Compress the least significant bit of each byte to the rightmost and clear 69 // the higher garbage bits. 70 void bytemask_compress(Register dst); 71 72 // Pack the lowest-numbered bit of each mask element in src into a long value 73 // in dst, at most the first 64 lane elements. 74 void sve_vmask_tolong(Register dst, PRegister src, BasicType bt, int lane_cnt, 75 FloatRegister vtmp1, FloatRegister vtmp2); 76 77 // Unpack the mask, a long value in src, into predicate register dst based on the 78 // corresponding data type. Note that dst can support at most 64 lanes. 79 void sve_vmask_fromlong(PRegister dst, Register src, BasicType bt, int lane_cnt, 80 FloatRegister vtmp1, FloatRegister vtmp2); 81 82 // SIMD&FP comparison 83 void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1, 84 FloatRegister src2, int cond, bool isQ); 85 86 void sve_compare(PRegister pd, BasicType bt, PRegister pg, 87 FloatRegister zn, FloatRegister zm, int cond); 88 89 void sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, PRegister ptmp); 90 91 // Vector cast 92 void neon_vector_extend(FloatRegister dst, BasicType dst_bt, unsigned dst_vlen_in_bytes, 93 FloatRegister src, BasicType src_bt); 94 95 void neon_vector_narrow(FloatRegister dst, BasicType dst_bt, 96 FloatRegister src, BasicType src_bt, unsigned src_vlen_in_bytes); 97 98 void sve_vector_extend(FloatRegister dst, SIMD_RegVariant dst_size, 99 FloatRegister src, SIMD_RegVariant src_size); 100 101 void sve_vector_narrow(FloatRegister dst, SIMD_RegVariant dst_size, 102 FloatRegister src, SIMD_RegVariant src_size, FloatRegister tmp); 103 104 void sve_vmaskcast_extend(PRegister dst, PRegister src, 105 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes); 106 107 void sve_vmaskcast_narrow(PRegister dst, PRegister src, 108 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes); 109 110 // Vector reduction 111 void neon_reduce_add_integral(Register dst, BasicType bt, 112 Register isrc, FloatRegister vsrc, 113 unsigned vector_length_in_bytes, FloatRegister vtmp); 114 115 void neon_reduce_mul_integral(Register dst, BasicType bt, 116 Register isrc, FloatRegister vsrc, 117 unsigned vector_length_in_bytes, 118 FloatRegister vtmp1, FloatRegister vtmp2); 119 120 void neon_reduce_mul_fp(FloatRegister dst, BasicType bt, 121 FloatRegister fsrc, FloatRegister vsrc, 122 unsigned vector_length_in_bytes, FloatRegister vtmp); 123 124 void neon_reduce_logical(int opc, Register dst, BasicType bt, Register isrc, 125 FloatRegister vsrc, unsigned vector_length_in_bytes); 126 127 void neon_reduce_minmax_integral(int opc, Register dst, BasicType bt, 128 Register isrc, FloatRegister vsrc, 129 unsigned vector_length_in_bytes, FloatRegister vtmp); 130 131 void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1, 132 FloatRegister src2, PRegister pg, FloatRegister tmp); 133 134 // Set elements of the dst predicate to true for lanes in the range of 135 // [0, lane_cnt), or to false otherwise. The input "lane_cnt" should be 136 // smaller than or equal to the supported max vector length of the basic 137 // type. Clobbers: rscratch1 and the rFlagsReg. 138 void sve_gen_mask_imm(PRegister dst, BasicType bt, uint32_t lane_cnt); 139 140 // Extract a scalar element from an sve vector at position 'idx'. 141 // The input elements in src are expected to be of integral type. 142 void sve_extract_integral(Register dst, BasicType bt, FloatRegister src, 143 int idx, FloatRegister vtmp); 144 145 // java.lang.Math::round intrinsics 146 void vector_round_neon(FloatRegister dst, FloatRegister src, FloatRegister tmp1, 147 FloatRegister tmp2, FloatRegister tmp3, 148 SIMD_Arrangement T); 149 void vector_round_sve(FloatRegister dst, FloatRegister src, FloatRegister tmp1, 150 FloatRegister tmp2, PRegister pgtmp, 151 SIMD_RegVariant T); 152 153 // Pack active elements of src, under the control of mask, into the 154 // lowest-numbered elements of dst. Any remaining elements of dst will 155 // be filled with zero. 156 void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask, 157 FloatRegister vtmp1, FloatRegister vtmp2, 158 FloatRegister vtmp3, FloatRegister vtmp4, 159 PRegister ptmp, PRegister pgtmp); 160 161 void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask, 162 FloatRegister vtmp1, FloatRegister vtmp2, 163 PRegister pgtmp); 164 165 void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ); 166 167 void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ); 168 169 // java.lang.Math::signum intrinsics 170 void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero, 171 FloatRegister one, SIMD_Arrangement T); 172 173 void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero, 174 FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T); 175 176 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP