1 /*
2 * Copyright (c) 2020, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
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7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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23 */
24
25 #ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
26 #define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
27
28 // C2_MacroAssembler contains high-level macros for C2
29
30 private:
31 // Return true if the phase output is in the scratch emit size mode.
32 virtual bool in_scratch_emit_size() override;
33
34 void neon_reduce_logical_helper(int opc, bool sf, Register Rd, Register Rn, Register Rm,
35 enum shift_kind kind = Assembler::LSL, unsigned shift = 0);
36
37 void select_from_two_vectors_neon(FloatRegister dst, FloatRegister src1,
38 FloatRegister src2, FloatRegister index,
39 FloatRegister tmp, unsigned vector_length_in_bytes);
40
41 void select_from_two_vectors_sve(FloatRegister dst, FloatRegister src1,
42 FloatRegister src2, FloatRegister index,
43 FloatRegister tmp, SIMD_RegVariant T,
44 unsigned vector_length_in_bytes);
45
46 public:
47 void entry_barrier();
48
49 // jdk.internal.util.ArraysSupport.vectorizedHashCode
50 address arrays_hashcode(Register ary, Register cnt, Register result, FloatRegister vdata0,
51 FloatRegister vdata1, FloatRegister vdata2, FloatRegister vdata3,
52 FloatRegister vmul0, FloatRegister vmul1, FloatRegister vmul2,
53 FloatRegister vmul3, FloatRegister vpow, FloatRegister vpowm,
54 BasicType eltype);
55
56 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
57 void fast_lock(Register object, Register box, Register t1, Register t2, Register t3);
58 void fast_unlock(Register object, Register box, Register t1, Register t2, Register t3);
59
60 void string_compare(Register str1, Register str2,
61 Register cnt1, Register cnt2, Register result,
62 Register tmp1, Register tmp2, FloatRegister vtmp1,
63 FloatRegister vtmp2, FloatRegister vtmp3,
64 PRegister pgtmp1, PRegister pgtmp2, int ae);
65
66 void string_indexof(Register str1, Register str2,
67 Register cnt1, Register cnt2,
68 Register tmp1, Register tmp2,
69 Register tmp3, Register tmp4,
70 Register tmp5, Register tmp6,
71 int int_cnt1, Register result, int ae);
72
73 void string_indexof_char(Register str1, Register cnt1,
74 Register ch, Register result,
75 Register tmp1, Register tmp2, Register tmp3);
76
77 void stringL_indexof_char(Register str1, Register cnt1,
78 Register ch, Register result,
79 Register tmp1, Register tmp2, Register tmp3);
80
81 void string_indexof_char_sve(Register str1, Register cnt1,
82 Register ch, Register result,
83 FloatRegister ztmp1, FloatRegister ztmp2,
84 PRegister pgtmp, PRegister ptmp, bool isL);
85
86 // Compress the least significant bit of each byte to the rightmost and clear
87 // the higher garbage bits.
88 void bytemask_compress(Register dst);
89
90 // Pack the value of each mask element in "src" into a long value in "dst", at most the
91 // first 64 lane elements. The input "src" is a vector of boolean represented as bytes
92 // with 0x00/0x01 as element values. Each lane value from "src" is packed into one bit in
93 // "dst".
94 void sve_vmask_tolong(Register dst, FloatRegister src, FloatRegister vtmp, int lane_cnt);
95
96 void sve2_vmask_tolong(Register dst, FloatRegister src, FloatRegister vtmp1,
97 FloatRegister vtmp2, int lane_cnt);
98
99 // Unpack the mask, a long value in "src", into vector register "dst" with boolean type.
100 // Each bit in "src" is unpacked into one byte lane in "dst". Note that "dst" can support
101 // at most 64 lanes.
102 void sve_vmask_fromlong(FloatRegister dst, Register src, FloatRegister vtmp, int lane_cnt);
103
104 // SIMD&FP comparison
105 void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
106 FloatRegister src2, Condition cond, bool isQ);
107
108 void neon_compare_zero(FloatRegister dst, BasicType bt, FloatRegister src,
109 Condition cond, bool isQ);
110
111 void sve_compare(PRegister pd, BasicType bt, PRegister pg,
112 FloatRegister zn, FloatRegister zm, Condition cond);
113
114 void sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, PRegister ptmp);
115
116 // Vector cast
117 void neon_vector_extend(FloatRegister dst, BasicType dst_bt, unsigned dst_vlen_in_bytes,
118 FloatRegister src, BasicType src_bt, bool is_unsigned = false);
119
120 void neon_vector_narrow(FloatRegister dst, BasicType dst_bt,
121 FloatRegister src, BasicType src_bt, unsigned src_vlen_in_bytes);
122
123 void sve_vector_extend(FloatRegister dst, SIMD_RegVariant dst_size,
124 FloatRegister src, SIMD_RegVariant src_size, bool is_unsigned = false);
125
126 void sve_vector_narrow(FloatRegister dst, SIMD_RegVariant dst_size,
127 FloatRegister src, SIMD_RegVariant src_size, FloatRegister tmp);
128
129 void sve_vmaskcast_extend(PRegister dst, PRegister src,
130 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
131
132 void sve_vmaskcast_narrow(PRegister dst, PRegister src, PRegister ptmp,
133 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
134
135 // Vector reduction
136 void neon_reduce_add_integral(Register dst, BasicType bt,
137 Register isrc, FloatRegister vsrc,
138 unsigned vector_length_in_bytes, FloatRegister vtmp);
139
140 void neon_reduce_mul_integral(Register dst, BasicType bt,
141 Register isrc, FloatRegister vsrc,
142 unsigned vector_length_in_bytes,
143 FloatRegister vtmp1, FloatRegister vtmp2);
144
145 void neon_reduce_mul_fp(FloatRegister dst, BasicType bt,
146 FloatRegister fsrc, FloatRegister vsrc,
147 unsigned vector_length_in_bytes, FloatRegister vtmp);
148
149 void neon_reduce_logical(int opc, Register dst, BasicType bt, Register isrc,
150 FloatRegister vsrc, unsigned vector_length_in_bytes);
151
152 void neon_reduce_minmax_integral(int opc, Register dst, BasicType bt,
153 Register isrc, FloatRegister vsrc,
154 unsigned vector_length_in_bytes, FloatRegister vtmp);
155
156 void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
157 FloatRegister src2, PRegister pg, FloatRegister tmp);
158
159 // Set elements of the dst predicate to true for lanes in the range of
160 // [0, lane_cnt), or to false otherwise. The input "lane_cnt" should be
161 // smaller than or equal to the supported max vector length of the basic
162 // type. Clobbers: rscratch1 and the rFlagsReg.
163 void sve_gen_mask_imm(PRegister dst, BasicType bt, uint32_t lane_cnt);
164
165 // Extract a scalar element from an sve vector at position 'idx'.
166 // The input elements in src are expected to be of integral type.
167 void sve_extract_integral(Register dst, BasicType bt, FloatRegister src,
168 int idx, FloatRegister vtmp);
169
170 // java.lang.Math::round intrinsics
171 void vector_round_neon(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
172 FloatRegister tmp2, FloatRegister tmp3,
173 SIMD_Arrangement T);
174 void vector_round_sve(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
175 FloatRegister tmp2, PRegister pgtmp,
176 SIMD_RegVariant T);
177
178 // Pack active elements of src, under the control of mask, into the
179 // lowest-numbered elements of dst. Any remaining elements of dst will
180 // be filled with zero.
181 void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask,
182 FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3,
183 PRegister ptmp, PRegister pgtmp, unsigned vector_length_in_bytes);
184
185 void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
186 FloatRegister vzr, FloatRegister vtmp,
187 PRegister pgtmp, unsigned vector_length_in_bytes);
188
189 void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
190
191 void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
192
193 void neon_rearrange_hsd(FloatRegister dst, FloatRegister src, FloatRegister shuffle,
194 FloatRegister tmp, BasicType bt, bool isQ);
195 // java.lang.Math::signum intrinsics
196 void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
197 FloatRegister one, SIMD_Arrangement T);
198
199 void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
200 FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
201
202 void verify_int_in_range(uint idx, const TypeInt* t, Register val, Register tmp);
203 void verify_long_in_range(uint idx, const TypeLong* t, Register val, Register tmp);
204
205 void reconstruct_frame_pointer(Register rtmp);
206
207 // Select from a table of two vectors
208 void select_from_two_vectors(FloatRegister dst, FloatRegister src1, FloatRegister src2,
209 FloatRegister index, FloatRegister tmp, BasicType bt,
210 unsigned vector_length_in_bytes);
211
212 void vector_expand_neon(FloatRegister dst, FloatRegister src, FloatRegister mask,
213 FloatRegister tmp1, FloatRegister tmp2, BasicType bt,
214 int vector_length_in_bytes);
215 void vector_expand_sve(FloatRegister dst, FloatRegister src, PRegister pg,
216 FloatRegister tmp1, FloatRegister tmp2, BasicType bt,
217 int vector_length_in_bytes);
218 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP