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static void write_barrier_post(MacroAssembler* masm,
const MachNode* node,
Register store_addr,
Register new_val,
Register tmp1,
! Register tmp2) {
if (!G1PostBarrierStubC2::needs_barrier(node)) {
return;
}
Assembler::InlineSkippedInstructionsCounter skip_counter(masm);
G1BarrierSetAssembler* g1_asm = static_cast<G1BarrierSetAssembler*>(BarrierSet::barrier_set()->barrier_set_assembler());
G1PostBarrierStubC2* const stub = G1PostBarrierStubC2::create(node);
g1_asm->g1_write_barrier_post_c2(masm, store_addr, new_val, rthread, tmp1, tmp2, stub);
}
%}
// BEGIN This section of the file is automatically generated. Do not edit --------------
// This section is generated from g1_aarch64.m4
static void write_barrier_post(MacroAssembler* masm,
const MachNode* node,
Register store_addr,
Register new_val,
Register tmp1,
! Register tmp2,
+ RegSet preserve = RegSet()) {
if (!G1PostBarrierStubC2::needs_barrier(node)) {
return;
}
Assembler::InlineSkippedInstructionsCounter skip_counter(masm);
G1BarrierSetAssembler* g1_asm = static_cast<G1BarrierSetAssembler*>(BarrierSet::barrier_set()->barrier_set_assembler());
G1PostBarrierStubC2* const stub = G1PostBarrierStubC2::create(node);
+ for (RegSetIterator<Register> reg = preserve.begin(); *reg != noreg; ++reg) {
+ stub->preserve(*reg);
+ }
g1_asm->g1_write_barrier_post_c2(masm, store_addr, new_val, rthread, tmp1, tmp2, stub);
}
%}
+ // TODO 8350865 (same applies to g1StoreLSpecialTwoOops)
+ // - Can we use an unbound register for src?
+ // - Do no set/overwrite barrier data here, also handle G1C2BarrierPostNotNull
+ // - Is the zero-extend really required in all the places?
+ // - Move this into the .m4?
+ instruct g1StoreLSpecialOneOop(indirect mem, iRegL_R11 src, immI off, iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4, rFlagsReg cr)
+ %{
+ predicate(UseG1GC);
+ match(Set mem (StoreLSpecial mem (Binary src off)));
+ effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, KILL cr);
+ ins_cost(INSN_COST);
+ format %{ "str $src, $mem\t# g1StoreLSpecialOneOop" %}
+ ins_encode %{
+ ((MachNode*)this)->set_barrier_data(G1C2BarrierPre | G1C2BarrierPost);
+
+ // Adjust address to point to narrow oop
+ __ add($tmp4$$Register, $mem$$Register, $off$$constant);
+ write_barrier_pre(masm, this,
+ $tmp4$$Register /* obj */,
+ $tmp1$$Register /* pre_val */,
+ $tmp2$$Register /* tmp1 */,
+ $tmp3$$Register /* tmp2 */,
+ RegSet::of($mem$$Register, $src$$Register, $tmp4$$Register) /* preserve */);
+
+ __ str($src$$Register, $mem$$Register);
+
+ // Shift long value to extract the narrow oop field value and zero-extend it
+ __ lsr($src$$Register, $src$$Register, $off$$constant << LogBitsPerByte);
+ __ ubfm($src$$Register, $src$$Register, 0, 31);
+
+ write_barrier_post(masm, this,
+ $tmp4$$Register /* store_addr */,
+ $src$$Register /* new_val */,
+ $tmp2$$Register /* tmp1 */,
+ $tmp3$$Register /* tmp2 */);
+ %}
+ ins_pipe(istore_reg_mem);
+ %}
+
+ instruct g1StoreLSpecialTwoOops(indirect mem, iRegL_R11 src, iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4, rFlagsReg cr)
+ %{
+ predicate(UseG1GC);
+ match(Set mem (StoreLSpecial mem src));
+ effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, KILL cr);
+ ins_cost(INSN_COST);
+ format %{ "str $src, $mem\t# g1StoreLSpecialTwoOops" %}
+ ins_encode %{
+ ((MachNode*)this)->set_barrier_data(G1C2BarrierPre | G1C2BarrierPost);
+
+ write_barrier_pre(masm, this,
+ $mem$$Register /* obj */,
+ $tmp1$$Register /* pre_val */,
+ $tmp2$$Register /* tmp1 */,
+ $tmp3$$Register /* tmp2 */,
+ RegSet::of($mem$$Register, $src$$Register) /* preserve */);
+ // Adjust address to point to the second narrow oop in the long value
+ __ add($tmp4$$Register, $mem$$Register, 4);
+ write_barrier_pre(masm, this,
+ $tmp4$$Register /* obj */,
+ $tmp1$$Register /* pre_val */,
+ $tmp2$$Register /* tmp1 */,
+ $tmp3$$Register /* tmp2 */,
+ RegSet::of($mem$$Register, $src$$Register, $tmp4$$Register) /* preserve */);
+
+ __ str($src$$Register, $mem$$Register);
+
+ // Zero-extend first narrow oop to long
+ __ ubfm($tmp1$$Register, $src$$Register, 0, 31);
+
+ // Shift long value to extract the second narrow oop field value
+ __ lsr($src$$Register, $src$$Register, 32);
+
+ write_barrier_post(masm, this,
+ $mem$$Register /* store_addr */,
+ $tmp1$$Register /* new_val */,
+ $tmp2$$Register /* tmp1 */,
+ $tmp3$$Register /* tmp2 */,
+ RegSet::of($tmp1$$Register, $tmp4$$Register) /* preserve */);
+ write_barrier_post(masm, this,
+ $tmp4$$Register /* store_addr */,
+ $src$$Register /* new_val */,
+ $tmp2$$Register /* tmp1 */,
+ $tmp3$$Register /* tmp2 */);
+ %}
+ ins_pipe(istore_reg_mem);
+ %}
+
+
// BEGIN This section of the file is automatically generated. Do not edit --------------
// This section is generated from g1_aarch64.m4
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