1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "ci/ciEnv.hpp"
29 #include "code/compiledIC.hpp"
30 #include "compiler/compileTask.hpp"
31 #include "compiler/disassembler.hpp"
32 #include "compiler/oopMap.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/cardTableBarrierSet.hpp"
36 #include "gc/shared/cardTable.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/tlab_globals.hpp"
39 #include "interpreter/bytecodeHistogram.hpp"
40 #include "interpreter/interpreter.hpp"
41 #include "interpreter/interpreterRuntime.hpp"
42 #include "jvm.h"
43 #include "memory/resourceArea.hpp"
44 #include "memory/universe.hpp"
45 #include "nativeInst_aarch64.hpp"
46 #include "oops/accessDecorators.hpp"
47 #include "oops/compressedKlass.inline.hpp"
48 #include "oops/compressedOops.inline.hpp"
49 #include "oops/klass.inline.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/icache.hpp"
52 #include "runtime/interfaceSupport.inline.hpp"
53 #include "runtime/javaThread.hpp"
54 #include "runtime/jniHandles.inline.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/globalDefinitions.hpp"
58 #include "utilities/powerOfTwo.hpp"
59 #ifdef COMPILER1
60 #include "c1/c1_LIRAssembler.hpp"
61 #endif
62 #ifdef COMPILER2
63 #include "oops/oop.hpp"
64 #include "opto/compile.hpp"
65 #include "opto/node.hpp"
66 #include "opto/output.hpp"
67 #endif
68
69 #include <sys/types.h>
70
71 #ifdef PRODUCT
72 #define BLOCK_COMMENT(str) /* nothing */
73 #else
74 #define BLOCK_COMMENT(str) block_comment(str)
75 #endif
76 #define STOP(str) stop(str);
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
79 #ifdef ASSERT
80 extern "C" void disnm(intptr_t p);
81 #endif
82 // Target-dependent relocation processing
83 //
84 // Instruction sequences whose target may need to be retrieved or
85 // patched are distinguished by their leading instruction, sorting
86 // them into three main instruction groups and related subgroups.
87 //
88 // 1) Branch, Exception and System (insn count = 1)
89 // 1a) Unconditional branch (immediate):
90 // b/bl imm19
91 // 1b) Compare & branch (immediate):
92 // cbz/cbnz Rt imm19
93 // 1c) Test & branch (immediate):
94 // tbz/tbnz Rt imm14
95 // 1d) Conditional branch (immediate):
96 // b.cond imm19
97 //
98 // 2) Loads and Stores (insn count = 1)
99 // 2a) Load register literal:
100 // ldr Rt imm19
101 //
102 // 3) Data Processing Immediate (insn count = 2 or 3)
103 // 3a) PC-rel. addressing
104 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12
105 // adr/adrp Rx imm21; add Ry Rx #imm12
106 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page]
107 // adr/adrp Rx imm21
108 // adr/adrp Rx imm21; movk Rx #imm16<<32
109 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page
110 // The latter form can only happen when the target is an
111 // ExternalAddress, and (by definition) ExternalAddresses don't
112 // move. Because of that property, there is never any need to
113 // patch the last of the three instructions. However,
114 // MacroAssembler::target_addr_for_insn takes all three
115 // instructions into account and returns the correct address.
116 // 3b) Move wide (immediate)
117 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32;
118 //
119 // A switch on a subset of the instruction's bits provides an
120 // efficient dispatch to these subcases.
121 //
122 // insn[28:26] -> main group ('x' == don't care)
123 // 00x -> UNALLOCATED
124 // 100 -> Data Processing Immediate
125 // 101 -> Branch, Exception and System
126 // x1x -> Loads and Stores
127 //
128 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care).
129 // n.b. in some cases extra bits need to be checked to verify the
130 // instruction is as expected
131 //
132 // 1) ... xx101x Branch, Exception and System
133 // 1a) 00___x Unconditional branch (immediate)
134 // 1b) 01___0 Compare & branch (immediate)
135 // 1c) 01___1 Test & branch (immediate)
136 // 1d) 10___0 Conditional branch (immediate)
137 // other Should not happen
138 //
139 // 2) ... xxx1x0 Loads and Stores
140 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0)
141 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0)
142 // strictly should be 64 bit non-FP/SIMD i.e.
143 // 0101_000 (i.e. requires insn[31:24] == 01011000)
144 //
145 // 3) ... xx100x Data Processing Immediate
146 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0)
147 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01)
148 // strictly should be 64 bit movz #imm16<<0
149 // 110___10100 (i.e. requires insn[31:21] == 11010010100)
150 //
151
152 static uint32_t insn_at(address insn_addr, int n) {
153 return ((uint32_t*)insn_addr)[n];
154 }
155
156 template<typename T>
157 class RelocActions : public AllStatic {
158
159 public:
160
161 static int ALWAYSINLINE run(address insn_addr, address &target) {
162 int instructions = 1;
163 uint32_t insn = insn_at(insn_addr, 0);
164
165 uint32_t dispatch = Instruction_aarch64::extract(insn, 30, 25);
166 switch(dispatch) {
167 case 0b001010:
168 case 0b001011: {
169 instructions = T::unconditionalBranch(insn_addr, target);
170 break;
171 }
172 case 0b101010: // Conditional branch (immediate)
173 case 0b011010: { // Compare & branch (immediate)
174 instructions = T::conditionalBranch(insn_addr, target);
175 break;
176 }
177 case 0b011011: {
178 instructions = T::testAndBranch(insn_addr, target);
179 break;
180 }
181 case 0b001100:
182 case 0b001110:
183 case 0b011100:
184 case 0b011110:
185 case 0b101100:
186 case 0b101110:
187 case 0b111100:
188 case 0b111110: {
189 // load/store
190 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
191 // Load register (literal)
192 instructions = T::loadStore(insn_addr, target);
193 break;
194 } else {
195 // nothing to do
196 assert(target == nullptr, "did not expect to relocate target for polling page load");
197 }
198 break;
199 }
200 case 0b001000:
201 case 0b011000:
202 case 0b101000:
203 case 0b111000: {
204 // adr/adrp
205 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
206 int shift = Instruction_aarch64::extract(insn, 31, 31);
207 if (shift) {
208 uint32_t insn2 = insn_at(insn_addr, 1);
209 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
210 Instruction_aarch64::extract(insn, 4, 0) ==
211 Instruction_aarch64::extract(insn2, 9, 5)) {
212 instructions = T::adrp(insn_addr, target, T::adrpMem);
213 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
214 Instruction_aarch64::extract(insn, 4, 0) ==
215 Instruction_aarch64::extract(insn2, 4, 0)) {
216 instructions = T::adrp(insn_addr, target, T::adrpAdd);
217 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
218 Instruction_aarch64::extract(insn, 4, 0) ==
219 Instruction_aarch64::extract(insn2, 4, 0)) {
220 instructions = T::adrp(insn_addr, target, T::adrpMovk);
221 } else {
222 ShouldNotReachHere();
223 }
224 } else {
225 instructions = T::adr(insn_addr, target);
226 }
227 break;
228 }
229 case 0b001001:
230 case 0b011001:
231 case 0b101001:
232 case 0b111001: {
233 instructions = T::immediate(insn_addr, target);
234 break;
235 }
236 default: {
237 ShouldNotReachHere();
238 }
239 }
240
241 T::verify(insn_addr, target);
242 return instructions * NativeInstruction::instruction_size;
243 }
244 };
245
246 class Patcher : public AllStatic {
247 public:
248 static int unconditionalBranch(address insn_addr, address &target) {
249 intptr_t offset = (target - insn_addr) >> 2;
250 Instruction_aarch64::spatch(insn_addr, 25, 0, offset);
251 return 1;
252 }
253 static int conditionalBranch(address insn_addr, address &target) {
254 intptr_t offset = (target - insn_addr) >> 2;
255 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
256 return 1;
257 }
258 static int testAndBranch(address insn_addr, address &target) {
259 intptr_t offset = (target - insn_addr) >> 2;
260 Instruction_aarch64::spatch(insn_addr, 18, 5, offset);
261 return 1;
262 }
263 static int loadStore(address insn_addr, address &target) {
264 intptr_t offset = (target - insn_addr) >> 2;
265 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
266 return 1;
267 }
268 static int adr(address insn_addr, address &target) {
269 #ifdef ASSERT
270 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
271 #endif
272 // PC-rel. addressing
273 ptrdiff_t offset = target - insn_addr;
274 int offset_lo = offset & 3;
275 offset >>= 2;
276 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
277 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
278 return 1;
279 }
280 template<typename U>
281 static int adrp(address insn_addr, address &target, U inner) {
282 int instructions = 1;
283 #ifdef ASSERT
284 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
285 #endif
286 ptrdiff_t offset = target - insn_addr;
287 instructions = 2;
288 precond(inner != nullptr);
289 // Give the inner reloc a chance to modify the target.
290 address adjusted_target = target;
291 instructions = inner(insn_addr, adjusted_target);
292 uintptr_t pc_page = (uintptr_t)insn_addr >> 12;
293 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12;
294 offset = adr_page - pc_page;
295 int offset_lo = offset & 3;
296 offset >>= 2;
297 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
298 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
299 return instructions;
300 }
301 static int adrpMem(address insn_addr, address &target) {
302 uintptr_t dest = (uintptr_t)target;
303 int offset_lo = dest & 0xfff;
304 uint32_t insn2 = insn_at(insn_addr, 1);
305 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
306 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size);
307 guarantee(((dest >> size) << size) == dest, "misaligned target");
308 return 2;
309 }
310 static int adrpAdd(address insn_addr, address &target) {
311 uintptr_t dest = (uintptr_t)target;
312 int offset_lo = dest & 0xfff;
313 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo);
314 return 2;
315 }
316 static int adrpMovk(address insn_addr, address &target) {
317 uintptr_t dest = uintptr_t(target);
318 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32);
319 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL);
320 target = address(dest);
321 return 2;
322 }
323 static int immediate(address insn_addr, address &target) {
324 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010100, "must be");
325 uint64_t dest = (uint64_t)target;
326 // Move wide constant
327 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
328 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
329 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
330 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
331 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
332 return 3;
333 }
334 static void verify(address insn_addr, address &target) {
335 #ifdef ASSERT
336 address address_is = MacroAssembler::target_addr_for_insn(insn_addr);
337 if (!(address_is == target)) {
338 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target);
339 disnm((intptr_t)insn_addr);
340 assert(address_is == target, "should be");
341 }
342 #endif
343 }
344 };
345
346 // If insn1 and insn2 use the same register to form an address, either
347 // by an offsetted LDR or a simple ADD, return the offset. If the
348 // second instruction is an LDR, the offset may be scaled.
349 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) {
350 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
351 Instruction_aarch64::extract(insn1, 4, 0) ==
352 Instruction_aarch64::extract(insn2, 9, 5)) {
353 // Load/store register (unsigned immediate)
354 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
355 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
356 byte_offset <<= size;
357 return true;
358 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
359 Instruction_aarch64::extract(insn1, 4, 0) ==
360 Instruction_aarch64::extract(insn2, 4, 0)) {
361 // add (immediate)
362 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
363 return true;
364 }
365 return false;
366 }
367
368 class AArch64Decoder : public AllStatic {
369 public:
370
371 static int loadStore(address insn_addr, address &target) {
372 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
373 target = insn_addr + (offset << 2);
374 return 1;
375 }
376 static int unconditionalBranch(address insn_addr, address &target) {
377 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 25, 0);
378 target = insn_addr + (offset << 2);
379 return 1;
380 }
381 static int conditionalBranch(address insn_addr, address &target) {
382 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
383 target = address(((uint64_t)insn_addr + (offset << 2)));
384 return 1;
385 }
386 static int testAndBranch(address insn_addr, address &target) {
387 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 18, 5);
388 target = address(((uint64_t)insn_addr + (offset << 2)));
389 return 1;
390 }
391 static int adr(address insn_addr, address &target) {
392 // PC-rel. addressing
393 uint32_t insn = insn_at(insn_addr, 0);
394 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
395 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
396 target = address((uint64_t)insn_addr + offset);
397 return 1;
398 }
399 template<typename U>
400 static int adrp(address insn_addr, address &target, U inner) {
401 uint32_t insn = insn_at(insn_addr, 0);
402 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
403 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
404 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
405 int shift = 12;
406 offset <<= shift;
407 uint64_t target_page = ((uint64_t)insn_addr) + offset;
408 target_page &= ((uint64_t)-1) << shift;
409 target = address(target_page);
410 precond(inner != nullptr);
411 inner(insn_addr, target);
412 return 2;
413 }
414 static int adrpMem(address insn_addr, address &target) {
415 uint32_t insn2 = insn_at(insn_addr, 1);
416 // Load/store register (unsigned immediate)
417 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
418 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
419 byte_offset <<= size;
420 target += byte_offset;
421 return 2;
422 }
423 static int adrpAdd(address insn_addr, address &target) {
424 uint32_t insn2 = insn_at(insn_addr, 1);
425 // add (immediate)
426 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
427 target += byte_offset;
428 return 2;
429 }
430 static int adrpMovk(address insn_addr, address &target) {
431 uint32_t insn2 = insn_at(insn_addr, 1);
432 uint64_t dest = uint64_t(target);
433 dest = (dest & 0xffff0000ffffffff) |
434 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
435 target = address(dest);
436
437 // We know the destination 4k page. Maybe we have a third
438 // instruction.
439 uint32_t insn = insn_at(insn_addr, 0);
440 uint32_t insn3 = insn_at(insn_addr, 2);
441 ptrdiff_t byte_offset;
442 if (offset_for(insn, insn3, byte_offset)) {
443 target += byte_offset;
444 return 3;
445 } else {
446 return 2;
447 }
448 }
449 static int immediate(address insn_addr, address &target) {
450 uint32_t *insns = (uint32_t *)insn_addr;
451 assert(Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010100, "must be");
452 // Move wide constant: movz, movk, movk. See movptr().
453 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
454 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
455 target = address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5))
456 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
457 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
458 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
459 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
460 return 3;
461 }
462 static void verify(address insn_addr, address &target) {
463 }
464 };
465
466 address MacroAssembler::target_addr_for_insn(address insn_addr) {
467 address target;
468 RelocActions<AArch64Decoder>::run(insn_addr, target);
469 return target;
470 }
471
472 // Patch any kind of instruction; there may be several instructions.
473 // Return the total length (in bytes) of the instructions.
474 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) {
475 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
476 return RelocActions<Patcher>::run(insn_addr, target);
477 }
478
479 int MacroAssembler::patch_oop(address insn_addr, address o) {
480 int instructions;
481 unsigned insn = *(unsigned*)insn_addr;
482 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
483
484 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
485
486 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
487 // narrow OOPs by setting the upper 16 bits in the first
488 // instruction.
489 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
490 // Move narrow OOP
491 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
492 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
493 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
494 instructions = 2;
495 } else {
496 // Move wide OOP
497 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
498 uintptr_t dest = (uintptr_t)o;
499 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
500 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
501 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
502 instructions = 3;
503 }
504 return instructions * NativeInstruction::instruction_size;
505 }
506
507 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
508 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
509 // We encode narrow ones by setting the upper 16 bits in the first
510 // instruction.
511 NativeInstruction *insn = nativeInstruction_at(insn_addr);
512 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
513 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
514
515 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
516
517 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
518 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
519 return 2 * NativeInstruction::instruction_size;
520 }
521
522 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp) {
523 ldr(tmp, Address(rthread, JavaThread::polling_word_offset()));
524 if (at_return) {
525 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
526 // we may safely use the sp instead to perform the stack watermark check.
527 cmp(in_nmethod ? sp : rfp, tmp);
528 br(Assembler::HI, slow_path);
529 } else {
530 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path);
531 }
532 }
533
534 void MacroAssembler::rt_call(address dest, Register tmp) {
535 CodeBlob *cb = CodeCache::find_blob(dest);
536 if (cb) {
537 far_call(RuntimeAddress(dest));
538 } else {
539 lea(tmp, RuntimeAddress(dest));
540 blr(tmp);
541 }
542 }
543
544 void MacroAssembler::push_cont_fastpath(Register java_thread) {
545 if (!Continuations::enabled()) return;
546 Label done;
547 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
548 cmp(sp, rscratch1);
549 br(Assembler::LS, done);
550 mov(rscratch1, sp); // we can't use sp as the source in str
551 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
552 bind(done);
553 }
554
555 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
556 if (!Continuations::enabled()) return;
557 Label done;
558 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
559 cmp(sp, rscratch1);
560 br(Assembler::LO, done);
561 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset()));
562 bind(done);
563 }
564
565 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
566 // we must set sp to zero to clear frame
567 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
568
569 // must clear fp, so that compiled frames are not confused; it is
570 // possible that we need it only for debugging
571 if (clear_fp) {
572 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
573 }
574
575 // Always clear the pc because it could have been set by make_walkable()
576 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
577 }
578
579 // Calls to C land
580 //
581 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
582 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
583 // has to be reset to 0. This is required to allow proper stack traversal.
584 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
585 Register last_java_fp,
586 Register last_java_pc,
587 Register scratch) {
588
589 if (last_java_pc->is_valid()) {
590 str(last_java_pc, Address(rthread,
591 JavaThread::frame_anchor_offset()
592 + JavaFrameAnchor::last_Java_pc_offset()));
593 }
594
595 // determine last_java_sp register
596 if (last_java_sp == sp) {
597 mov(scratch, sp);
598 last_java_sp = scratch;
599 } else if (!last_java_sp->is_valid()) {
600 last_java_sp = esp;
601 }
602
603 // last_java_fp is optional
604 if (last_java_fp->is_valid()) {
605 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
606 }
607
608 // We must set sp last.
609 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
610 }
611
612 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
613 Register last_java_fp,
614 address last_java_pc,
615 Register scratch) {
616 assert(last_java_pc != nullptr, "must provide a valid PC");
617
618 adr(scratch, last_java_pc);
619 str(scratch, Address(rthread,
620 JavaThread::frame_anchor_offset()
621 + JavaFrameAnchor::last_Java_pc_offset()));
622
623 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
624 }
625
626 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
627 Register last_java_fp,
628 Label &L,
629 Register scratch) {
630 if (L.is_bound()) {
631 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
632 } else {
633 InstructionMark im(this);
634 L.add_patch_at(code(), locator());
635 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch);
636 }
637 }
638
639 static inline bool target_needs_far_branch(address addr) {
640 if (AOTCodeCache::is_on_for_dump()) {
641 return true;
642 }
643 // codecache size <= 128M
644 if (!MacroAssembler::far_branches()) {
645 return false;
646 }
647 // codecache size > 240M
648 if (MacroAssembler::codestub_branch_needs_far_jump()) {
649 return true;
650 }
651 // codecache size: 128M..240M
652 return !CodeCache::is_non_nmethod(addr);
653 }
654
655 void MacroAssembler::far_call(Address entry, Register tmp) {
656 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
657 assert(CodeCache::find_blob(entry.target()) != nullptr,
658 "destination of far call not found in code cache");
659 assert(entry.rspec().type() == relocInfo::external_word_type
660 || entry.rspec().type() == relocInfo::runtime_call_type
661 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
662 if (target_needs_far_branch(entry.target())) {
663 uint64_t offset;
664 // We can use ADRP here because we know that the total size of
665 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
666 adrp(tmp, entry, offset);
667 add(tmp, tmp, offset);
668 blr(tmp);
669 } else {
670 bl(entry);
671 }
672 }
673
674 int MacroAssembler::far_jump(Address entry, Register tmp) {
675 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
676 assert(CodeCache::find_blob(entry.target()) != nullptr,
677 "destination of far call not found in code cache");
678 assert(entry.rspec().type() == relocInfo::external_word_type
679 || entry.rspec().type() == relocInfo::runtime_call_type
680 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
681 address start = pc();
682 if (target_needs_far_branch(entry.target())) {
683 uint64_t offset;
684 // We can use ADRP here because we know that the total size of
685 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
686 adrp(tmp, entry, offset);
687 add(tmp, tmp, offset);
688 br(tmp);
689 } else {
690 b(entry);
691 }
692 return pc() - start;
693 }
694
695 void MacroAssembler::reserved_stack_check() {
696 // testing if reserved zone needs to be enabled
697 Label no_reserved_zone_enabling;
698
699 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
700 cmp(sp, rscratch1);
701 br(Assembler::LO, no_reserved_zone_enabling);
702
703 enter(); // LR and FP are live.
704 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)));
705 mov(c_rarg0, rthread);
706 blr(rscratch1);
707 leave();
708
709 // We have already removed our own frame.
710 // throw_delayed_StackOverflowError will think that it's been
711 // called by our caller.
712 lea(rscratch1, RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
713 br(rscratch1);
714 should_not_reach_here();
715
716 bind(no_reserved_zone_enabling);
717 }
718
719 static void pass_arg0(MacroAssembler* masm, Register arg) {
720 if (c_rarg0 != arg ) {
721 masm->mov(c_rarg0, arg);
722 }
723 }
724
725 static void pass_arg1(MacroAssembler* masm, Register arg) {
726 if (c_rarg1 != arg ) {
727 masm->mov(c_rarg1, arg);
728 }
729 }
730
731 static void pass_arg2(MacroAssembler* masm, Register arg) {
732 if (c_rarg2 != arg ) {
733 masm->mov(c_rarg2, arg);
734 }
735 }
736
737 static void pass_arg3(MacroAssembler* masm, Register arg) {
738 if (c_rarg3 != arg ) {
739 masm->mov(c_rarg3, arg);
740 }
741 }
742
743 void MacroAssembler::call_VM_base(Register oop_result,
744 Register java_thread,
745 Register last_java_sp,
746 Label* return_pc,
747 address entry_point,
748 int number_of_arguments,
749 bool check_exceptions) {
750 // determine java_thread register
751 if (!java_thread->is_valid()) {
752 java_thread = rthread;
753 }
754
755 // determine last_java_sp register
756 if (!last_java_sp->is_valid()) {
757 last_java_sp = esp;
758 }
759
760 // debugging support
761 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
762 assert(java_thread == rthread, "unexpected register");
763 #ifdef ASSERT
764 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
765 // if (!TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
766 #endif // ASSERT
767
768 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
769 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
770
771 // push java thread (becomes first argument of C function)
772
773 mov(c_rarg0, java_thread);
774
775 // set last Java frame before call
776 assert(last_java_sp != rfp, "can't use rfp");
777
778 Label l;
779 set_last_Java_frame(last_java_sp, rfp, return_pc != nullptr ? *return_pc : l, rscratch1);
780
781 // do the call, remove parameters
782 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
783
784 // lr could be poisoned with PAC signature during throw_pending_exception
785 // if it was tail-call optimized by compiler, since lr is not callee-saved
786 // reload it with proper value
787 adr(lr, l);
788
789 // reset last Java frame
790 // Only interpreter should have to clear fp
791 reset_last_Java_frame(true);
792
793 // C++ interp handles this in the interpreter
794 check_and_handle_popframe(java_thread);
795 check_and_handle_earlyret(java_thread);
796
797 if (check_exceptions) {
798 // check for pending exceptions (java_thread is set upon return)
799 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
800 Label ok;
801 cbz(rscratch1, ok);
802 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
803 br(rscratch1);
804 bind(ok);
805 }
806
807 // get oop result if there is one and reset the value in the thread
808 if (oop_result->is_valid()) {
809 get_vm_result_oop(oop_result, java_thread);
810 }
811 }
812
813 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
814 call_VM_base(oop_result, noreg, noreg, nullptr, entry_point, number_of_arguments, check_exceptions);
815 }
816
817 // Check the entry target is always reachable from any branch.
818 static bool is_always_within_branch_range(Address entry) {
819 if (AOTCodeCache::is_on_for_dump()) {
820 return false;
821 }
822 const address target = entry.target();
823
824 if (!CodeCache::contains(target)) {
825 // We always use trampolines for callees outside CodeCache.
826 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target");
827 return false;
828 }
829
830 if (!MacroAssembler::far_branches()) {
831 return true;
832 }
833
834 if (entry.rspec().type() == relocInfo::runtime_call_type) {
835 // Runtime calls are calls of a non-compiled method (stubs, adapters).
836 // Non-compiled methods stay forever in CodeCache.
837 // We check whether the longest possible branch is within the branch range.
838 assert(CodeCache::find_blob(target) != nullptr &&
839 !CodeCache::find_blob(target)->is_nmethod(),
840 "runtime call of compiled method");
841 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size;
842 const address left_longest_branch_start = CodeCache::low_bound();
843 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) &&
844 Assembler::reachable_from_branch_at(right_longest_branch_start, target);
845 return is_reachable;
846 }
847
848 return false;
849 }
850
851 // Maybe emit a call via a trampoline. If the code cache is small
852 // trampolines won't be emitted.
853 address MacroAssembler::trampoline_call(Address entry) {
854 assert(entry.rspec().type() == relocInfo::runtime_call_type
855 || entry.rspec().type() == relocInfo::opt_virtual_call_type
856 || entry.rspec().type() == relocInfo::static_call_type
857 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
858
859 address target = entry.target();
860
861 if (!is_always_within_branch_range(entry)) {
862 if (!in_scratch_emit_size()) {
863 // We don't want to emit a trampoline if C2 is generating dummy
864 // code during its branch shortening phase.
865 if (entry.rspec().type() == relocInfo::runtime_call_type) {
866 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs");
867 code()->share_trampoline_for(entry.target(), offset());
868 } else {
869 address stub = emit_trampoline_stub(offset(), target);
870 if (stub == nullptr) {
871 postcond(pc() == badAddress);
872 return nullptr; // CodeCache is full
873 }
874 }
875 }
876 target = pc();
877 }
878
879 address call_pc = pc();
880 relocate(entry.rspec());
881 bl(target);
882
883 postcond(pc() != badAddress);
884 return call_pc;
885 }
886
887 // Emit a trampoline stub for a call to a target which is too far away.
888 //
889 // code sequences:
890 //
891 // call-site:
892 // branch-and-link to <destination> or <trampoline stub>
893 //
894 // Related trampoline stub for this call site in the stub section:
895 // load the call target from the constant pool
896 // branch (LR still points to the call site above)
897
898 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
899 address dest) {
900 // Max stub size: alignment nop, TrampolineStub.
901 address stub = start_a_stub(max_trampoline_stub_size());
902 if (stub == nullptr) {
903 return nullptr; // CodeBuffer::expand failed
904 }
905
906 // Create a trampoline stub relocation which relates this trampoline stub
907 // with the call instruction at insts_call_instruction_offset in the
908 // instructions code-section.
909 align(wordSize);
910 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
911 + insts_call_instruction_offset));
912 const int stub_start_offset = offset();
913
914 // Now, create the trampoline stub's code:
915 // - load the call
916 // - call
917 Label target;
918 ldr(rscratch1, target);
919 br(rscratch1);
920 bind(target);
921 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
922 "should be");
923 emit_int64((int64_t)dest);
924
925 const address stub_start_addr = addr_at(stub_start_offset);
926
927 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
928
929 end_a_stub();
930 return stub_start_addr;
931 }
932
933 int MacroAssembler::max_trampoline_stub_size() {
934 // Max stub size: alignment nop, TrampolineStub.
935 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size;
936 }
937
938 void MacroAssembler::emit_static_call_stub() {
939 // CompiledDirectCall::set_to_interpreted knows the
940 // exact layout of this stub.
941
942 isb();
943 mov_metadata(rmethod, nullptr);
944
945 // Jump to the entry point of the c2i stub.
946 if (codestub_branch_needs_far_jump()) {
947 movptr(rscratch1, 0);
948 br(rscratch1);
949 } else {
950 b(pc());
951 }
952 }
953
954 int MacroAssembler::static_call_stub_size() {
955 if (!codestub_branch_needs_far_jump()) {
956 // isb; movk; movz; movz; b
957 return 5 * NativeInstruction::instruction_size;
958 }
959 // isb; movk; movz; movz; movk; movz; movz; br
960 return 8 * NativeInstruction::instruction_size;
961 }
962
963 void MacroAssembler::c2bool(Register x) {
964 // implements x == 0 ? 0 : 1
965 // note: must only look at least-significant byte of x
966 // since C-style booleans are stored in one byte
967 // only! (was bug)
968 tst(x, 0xff);
969 cset(x, Assembler::NE);
970 }
971
972 address MacroAssembler::ic_call(address entry, jint method_index) {
973 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
974 movptr(rscratch2, (intptr_t)Universe::non_oop_word());
975 return trampoline_call(Address(entry, rh));
976 }
977
978 int MacroAssembler::ic_check_size() {
979 int extra_instructions = UseCompactObjectHeaders ? 1 : 0;
980 if (target_needs_far_branch(CAST_FROM_FN_PTR(address, SharedRuntime::get_ic_miss_stub()))) {
981 return NativeInstruction::instruction_size * (7 + extra_instructions);
982 } else {
983 return NativeInstruction::instruction_size * (5 + extra_instructions);
984 }
985 }
986
987 int MacroAssembler::ic_check(int end_alignment) {
988 Register receiver = j_rarg0;
989 Register data = rscratch2;
990 Register tmp1 = rscratch1;
991 Register tmp2 = r10;
992
993 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
994 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
995 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
996 // before the inline cache check here, and not after
997 align(end_alignment, offset() + ic_check_size());
998
999 int uep_offset = offset();
1000
1001 if (UseCompactObjectHeaders) {
1002 load_narrow_klass_compact(tmp1, receiver);
1003 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1004 cmpw(tmp1, tmp2);
1005 } else {
1006 ldrw(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1007 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1008 cmpw(tmp1, tmp2);
1009 }
1010
1011 Label dont;
1012 br(Assembler::EQ, dont);
1013 far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1014 bind(dont);
1015 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1016
1017 return uep_offset;
1018 }
1019
1020 // Implementation of call_VM versions
1021
1022 void MacroAssembler::call_VM(Register oop_result,
1023 address entry_point,
1024 bool check_exceptions) {
1025 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1026 }
1027
1028 void MacroAssembler::call_VM(Register oop_result,
1029 address entry_point,
1030 Register arg_1,
1031 bool check_exceptions) {
1032 pass_arg1(this, arg_1);
1033 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1034 }
1035
1036 void MacroAssembler::call_VM(Register oop_result,
1037 address entry_point,
1038 Register arg_1,
1039 Register arg_2,
1040 bool check_exceptions) {
1041 assert_different_registers(arg_1, c_rarg2);
1042 pass_arg2(this, arg_2);
1043 pass_arg1(this, arg_1);
1044 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1045 }
1046
1047 void MacroAssembler::call_VM(Register oop_result,
1048 address entry_point,
1049 Register arg_1,
1050 Register arg_2,
1051 Register arg_3,
1052 bool check_exceptions) {
1053 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1054 assert_different_registers(arg_2, c_rarg3);
1055 pass_arg3(this, arg_3);
1056
1057 pass_arg2(this, arg_2);
1058
1059 pass_arg1(this, arg_1);
1060 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1061 }
1062
1063 void MacroAssembler::call_VM(Register oop_result,
1064 Register last_java_sp,
1065 address entry_point,
1066 int number_of_arguments,
1067 bool check_exceptions) {
1068 call_VM_base(oop_result, rthread, last_java_sp, nullptr, entry_point, number_of_arguments, check_exceptions);
1069 }
1070
1071 void MacroAssembler::call_VM(Register oop_result,
1072 Register last_java_sp,
1073 address entry_point,
1074 Register arg_1,
1075 bool check_exceptions) {
1076 pass_arg1(this, arg_1);
1077 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1078 }
1079
1080 void MacroAssembler::call_VM(Register oop_result,
1081 Register last_java_sp,
1082 address entry_point,
1083 Register arg_1,
1084 Register arg_2,
1085 bool check_exceptions) {
1086
1087 assert_different_registers(arg_1, c_rarg2);
1088 pass_arg2(this, arg_2);
1089 pass_arg1(this, arg_1);
1090 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1091 }
1092
1093 void MacroAssembler::call_VM(Register oop_result,
1094 Register last_java_sp,
1095 address entry_point,
1096 Register arg_1,
1097 Register arg_2,
1098 Register arg_3,
1099 bool check_exceptions) {
1100 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1101 assert_different_registers(arg_2, c_rarg3);
1102 pass_arg3(this, arg_3);
1103 pass_arg2(this, arg_2);
1104 pass_arg1(this, arg_1);
1105 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1106 }
1107
1108
1109 void MacroAssembler::get_vm_result_oop(Register oop_result, Register java_thread) {
1110 ldr(oop_result, Address(java_thread, JavaThread::vm_result_oop_offset()));
1111 str(zr, Address(java_thread, JavaThread::vm_result_oop_offset()));
1112 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1113 }
1114
1115 void MacroAssembler::get_vm_result_metadata(Register metadata_result, Register java_thread) {
1116 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1117 str(zr, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1118 }
1119
1120 void MacroAssembler::align(int modulus) {
1121 align(modulus, offset());
1122 }
1123
1124 // Ensure that the code at target bytes offset from the current offset() is aligned
1125 // according to modulus.
1126 void MacroAssembler::align(int modulus, int target) {
1127 int delta = target - offset();
1128 while ((offset() + delta) % modulus != 0) nop();
1129 }
1130
1131 void MacroAssembler::post_call_nop() {
1132 if (!Continuations::enabled()) {
1133 return;
1134 }
1135 InstructionMark im(this);
1136 relocate(post_call_nop_Relocation::spec());
1137 InlineSkippedInstructionsCounter skipCounter(this);
1138 nop();
1139 movk(zr, 0);
1140 movk(zr, 0);
1141 }
1142
1143 // these are no-ops overridden by InterpreterMacroAssembler
1144
1145 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1146
1147 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1148
1149 // Look up the method for a megamorphic invokeinterface call.
1150 // The target method is determined by <intf_klass, itable_index>.
1151 // The receiver klass is in recv_klass.
1152 // On success, the result will be in method_result, and execution falls through.
1153 // On failure, execution transfers to the given label.
1154 void MacroAssembler::lookup_interface_method(Register recv_klass,
1155 Register intf_klass,
1156 RegisterOrConstant itable_index,
1157 Register method_result,
1158 Register scan_temp,
1159 Label& L_no_such_interface,
1160 bool return_method) {
1161 assert_different_registers(recv_klass, intf_klass, scan_temp);
1162 assert_different_registers(method_result, intf_klass, scan_temp);
1163 assert(recv_klass != method_result || !return_method,
1164 "recv_klass can be destroyed when method isn't needed");
1165 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1166 "caller must use same register for non-constant itable index as for method");
1167
1168 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1169 int vtable_base = in_bytes(Klass::vtable_start_offset());
1170 int itentry_off = in_bytes(itableMethodEntry::method_offset());
1171 int scan_step = itableOffsetEntry::size() * wordSize;
1172 int vte_size = vtableEntry::size_in_bytes();
1173 assert(vte_size == wordSize, "else adjust times_vte_scale");
1174
1175 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1176
1177 // Could store the aligned, prescaled offset in the klass.
1178 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
1179 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
1180 add(scan_temp, scan_temp, vtable_base);
1181
1182 if (return_method) {
1183 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1184 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1185 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1186 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
1187 if (itentry_off)
1188 add(recv_klass, recv_klass, itentry_off);
1189 }
1190
1191 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
1192 // if (scan->interface() == intf) {
1193 // result = (klass + scan->offset() + itable_index);
1194 // }
1195 // }
1196 Label search, found_method;
1197
1198 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1199 cmp(intf_klass, method_result);
1200 br(Assembler::EQ, found_method);
1201 bind(search);
1202 // Check that the previous entry is non-null. A null entry means that
1203 // the receiver class doesn't implement the interface, and wasn't the
1204 // same as when the caller was compiled.
1205 cbz(method_result, L_no_such_interface);
1206 if (itableOffsetEntry::interface_offset() != 0) {
1207 add(scan_temp, scan_temp, scan_step);
1208 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1209 } else {
1210 ldr(method_result, Address(pre(scan_temp, scan_step)));
1211 }
1212 cmp(intf_klass, method_result);
1213 br(Assembler::NE, search);
1214
1215 bind(found_method);
1216
1217 // Got a hit.
1218 if (return_method) {
1219 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
1220 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1221 }
1222 }
1223
1224 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
1225 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
1226 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
1227 // The target method is determined by <holder_klass, itable_index>.
1228 // The receiver klass is in recv_klass.
1229 // On success, the result will be in method_result, and execution falls through.
1230 // On failure, execution transfers to the given label.
1231 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
1232 Register holder_klass,
1233 Register resolved_klass,
1234 Register method_result,
1235 Register temp_itbl_klass,
1236 Register scan_temp,
1237 int itable_index,
1238 Label& L_no_such_interface) {
1239 // 'method_result' is only used as output register at the very end of this method.
1240 // Until then we can reuse it as 'holder_offset'.
1241 Register holder_offset = method_result;
1242 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset);
1243
1244 int vtable_start_offset = in_bytes(Klass::vtable_start_offset());
1245 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize;
1246 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
1247 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
1248
1249 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found;
1250
1251 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1252 add(recv_klass, recv_klass, vtable_start_offset + ioffset);
1253 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len;
1254 // temp_itbl_klass = itable[0]._interface;
1255 int vtblEntrySize = vtableEntry::size_in_bytes();
1256 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3");
1257 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1258 mov(holder_offset, zr);
1259 // scan_temp = &(itable[0]._interface)
1260 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1261
1262 // Initial checks:
1263 // - if (holder_klass != resolved_klass), go to "scan for resolved"
1264 // - if (itable[0] == holder_klass), shortcut to "holder found"
1265 // - if (itable[0] == 0), no such interface
1266 cmp(resolved_klass, holder_klass);
1267 br(Assembler::NE, L_loop_search_resolved_entry);
1268 cmp(holder_klass, temp_itbl_klass);
1269 br(Assembler::EQ, L_holder_found);
1270 cbz(temp_itbl_klass, L_no_such_interface);
1271
1272 // Loop: Look for holder_klass record in itable
1273 // do {
1274 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1275 // if (temp_itbl_klass == holder_klass) {
1276 // goto L_holder_found; // Found!
1277 // }
1278 // } while (temp_itbl_klass != 0);
1279 // goto L_no_such_interface // Not found.
1280 Label L_search_holder;
1281 bind(L_search_holder);
1282 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1283 cmp(holder_klass, temp_itbl_klass);
1284 br(Assembler::EQ, L_holder_found);
1285 cbnz(temp_itbl_klass, L_search_holder);
1286
1287 b(L_no_such_interface);
1288
1289 // Loop: Look for resolved_class record in itable
1290 // while (true) {
1291 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1292 // if (temp_itbl_klass == 0) {
1293 // goto L_no_such_interface;
1294 // }
1295 // if (temp_itbl_klass == resolved_klass) {
1296 // goto L_resolved_found; // Found!
1297 // }
1298 // if (temp_itbl_klass == holder_klass) {
1299 // holder_offset = scan_temp;
1300 // }
1301 // }
1302 //
1303 Label L_loop_search_resolved;
1304 bind(L_loop_search_resolved);
1305 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1306 bind(L_loop_search_resolved_entry);
1307 cbz(temp_itbl_klass, L_no_such_interface);
1308 cmp(resolved_klass, temp_itbl_klass);
1309 br(Assembler::EQ, L_resolved_found);
1310 cmp(holder_klass, temp_itbl_klass);
1311 br(Assembler::NE, L_loop_search_resolved);
1312 mov(holder_offset, scan_temp);
1313 b(L_loop_search_resolved);
1314
1315 // See if we already have a holder klass. If not, go and scan for it.
1316 bind(L_resolved_found);
1317 cbz(holder_offset, L_search_holder);
1318 mov(scan_temp, holder_offset);
1319
1320 // Finally, scan_temp contains holder_klass vtable offset
1321 bind(L_holder_found);
1322 ldrw(method_result, Address(scan_temp, ooffset - ioffset));
1323 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset())
1324 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass
1325 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0)));
1326 }
1327
1328 // virtual method calling
1329 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1330 RegisterOrConstant vtable_index,
1331 Register method_result) {
1332 assert(vtableEntry::size() * wordSize == 8,
1333 "adjust the scaling in the code below");
1334 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset());
1335
1336 if (vtable_index.is_register()) {
1337 lea(method_result, Address(recv_klass,
1338 vtable_index.as_register(),
1339 Address::lsl(LogBytesPerWord)));
1340 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1341 } else {
1342 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1343 ldr(method_result,
1344 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1345 }
1346 }
1347
1348 void MacroAssembler::check_klass_subtype(Register sub_klass,
1349 Register super_klass,
1350 Register temp_reg,
1351 Label& L_success) {
1352 Label L_failure;
1353 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
1354 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
1355 bind(L_failure);
1356 }
1357
1358
1359 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1360 Register super_klass,
1361 Register temp_reg,
1362 Label* L_success,
1363 Label* L_failure,
1364 Label* L_slow_path,
1365 Register super_check_offset) {
1366 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset);
1367 bool must_load_sco = ! super_check_offset->is_valid();
1368 if (must_load_sco) {
1369 assert(temp_reg != noreg, "supply either a temp or a register offset");
1370 }
1371
1372 Label L_fallthrough;
1373 int label_nulls = 0;
1374 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1375 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1376 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
1377 assert(label_nulls <= 1, "at most one null in the batch");
1378
1379 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1380 Address super_check_offset_addr(super_klass, sco_offset);
1381
1382 // Hacked jmp, which may only be used just before L_fallthrough.
1383 #define final_jmp(label) \
1384 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1385 else b(label) /*omit semi*/
1386
1387 // If the pointers are equal, we are done (e.g., String[] elements).
1388 // This self-check enables sharing of secondary supertype arrays among
1389 // non-primary types such as array-of-interface. Otherwise, each such
1390 // type would need its own customized SSA.
1391 // We move this check to the front of the fast path because many
1392 // type checks are in fact trivially successful in this manner,
1393 // so we get a nicely predicted branch right at the start of the check.
1394 cmp(sub_klass, super_klass);
1395 br(Assembler::EQ, *L_success);
1396
1397 // Check the supertype display:
1398 if (must_load_sco) {
1399 ldrw(temp_reg, super_check_offset_addr);
1400 super_check_offset = temp_reg;
1401 }
1402
1403 Address super_check_addr(sub_klass, super_check_offset);
1404 ldr(rscratch1, super_check_addr);
1405 cmp(super_klass, rscratch1); // load displayed supertype
1406 br(Assembler::EQ, *L_success);
1407
1408 // This check has worked decisively for primary supers.
1409 // Secondary supers are sought in the super_cache ('super_cache_addr').
1410 // (Secondary supers are interfaces and very deeply nested subtypes.)
1411 // This works in the same check above because of a tricky aliasing
1412 // between the super_cache and the primary super display elements.
1413 // (The 'super_check_addr' can address either, as the case requires.)
1414 // Note that the cache is updated below if it does not help us find
1415 // what we need immediately.
1416 // So if it was a primary super, we can just fail immediately.
1417 // Otherwise, it's the slow path for us (no success at this point).
1418
1419 sub(rscratch1, super_check_offset, in_bytes(Klass::secondary_super_cache_offset()));
1420 if (L_failure == &L_fallthrough) {
1421 cbz(rscratch1, *L_slow_path);
1422 } else {
1423 cbnz(rscratch1, *L_failure);
1424 final_jmp(*L_slow_path);
1425 }
1426
1427 bind(L_fallthrough);
1428
1429 #undef final_jmp
1430 }
1431
1432 // These two are taken from x86, but they look generally useful
1433
1434 // scans count pointer sized words at [addr] for occurrence of value,
1435 // generic
1436 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1437 Register scratch) {
1438 Label Lloop, Lexit;
1439 cbz(count, Lexit);
1440 bind(Lloop);
1441 ldr(scratch, post(addr, wordSize));
1442 cmp(value, scratch);
1443 br(EQ, Lexit);
1444 sub(count, count, 1);
1445 cbnz(count, Lloop);
1446 bind(Lexit);
1447 }
1448
1449 // scans count 4 byte words at [addr] for occurrence of value,
1450 // generic
1451 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1452 Register scratch) {
1453 Label Lloop, Lexit;
1454 cbz(count, Lexit);
1455 bind(Lloop);
1456 ldrw(scratch, post(addr, wordSize));
1457 cmpw(value, scratch);
1458 br(EQ, Lexit);
1459 sub(count, count, 1);
1460 cbnz(count, Lloop);
1461 bind(Lexit);
1462 }
1463
1464 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
1465 Register super_klass,
1466 Register temp_reg,
1467 Register temp2_reg,
1468 Label* L_success,
1469 Label* L_failure,
1470 bool set_cond_codes) {
1471 // NB! Callers may assume that, when temp2_reg is a valid register,
1472 // this code sets it to a nonzero value.
1473
1474 assert_different_registers(sub_klass, super_klass, temp_reg);
1475 if (temp2_reg != noreg)
1476 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1477 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1478
1479 Label L_fallthrough;
1480 int label_nulls = 0;
1481 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1482 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1483 assert(label_nulls <= 1, "at most one null in the batch");
1484
1485 // a couple of useful fields in sub_klass:
1486 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1487 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1488 Address secondary_supers_addr(sub_klass, ss_offset);
1489 Address super_cache_addr( sub_klass, sc_offset);
1490
1491 BLOCK_COMMENT("check_klass_subtype_slow_path");
1492
1493 // Do a linear scan of the secondary super-klass chain.
1494 // This code is rarely used, so simplicity is a virtue here.
1495 // The repne_scan instruction uses fixed registers, which we must spill.
1496 // Don't worry too much about pre-existing connections with the input regs.
1497
1498 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1499 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1500
1501 RegSet pushed_registers;
1502 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1503 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1504
1505 if (super_klass != r0) {
1506 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1507 }
1508
1509 push(pushed_registers, sp);
1510
1511 // Get super_klass value into r0 (even if it was in r5 or r2).
1512 if (super_klass != r0) {
1513 mov(r0, super_klass);
1514 }
1515
1516 #ifndef PRODUCT
1517 incrementw(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1518 #endif //PRODUCT
1519
1520 // We will consult the secondary-super array.
1521 ldr(r5, secondary_supers_addr);
1522 // Load the array length.
1523 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1524 // Skip to start of data.
1525 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1526
1527 cmp(sp, zr); // Clear Z flag; SP is never zero
1528 // Scan R2 words at [R5] for an occurrence of R0.
1529 // Set NZ/Z based on last compare.
1530 repne_scan(r5, r0, r2, rscratch1);
1531
1532 // Unspill the temp. registers:
1533 pop(pushed_registers, sp);
1534
1535 br(Assembler::NE, *L_failure);
1536
1537 // Success. Cache the super we found and proceed in triumph.
1538
1539 if (UseSecondarySupersCache) {
1540 str(super_klass, super_cache_addr);
1541 }
1542
1543 if (L_success != &L_fallthrough) {
1544 b(*L_success);
1545 }
1546
1547 #undef IS_A_TEMP
1548
1549 bind(L_fallthrough);
1550 }
1551
1552 // If Register r is invalid, remove a new register from
1553 // available_regs, and add new register to regs_to_push.
1554 Register MacroAssembler::allocate_if_noreg(Register r,
1555 RegSetIterator<Register> &available_regs,
1556 RegSet ®s_to_push) {
1557 if (!r->is_valid()) {
1558 r = *available_regs++;
1559 regs_to_push += r;
1560 }
1561 return r;
1562 }
1563
1564 // check_klass_subtype_slow_path_table() looks for super_klass in the
1565 // hash table belonging to super_klass, branching to L_success or
1566 // L_failure as appropriate. This is essentially a shim which
1567 // allocates registers as necessary then calls
1568 // lookup_secondary_supers_table() to do the work. Any of the temp
1569 // regs may be noreg, in which case this logic will chooses some
1570 // registers push and pop them from the stack.
1571 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
1572 Register super_klass,
1573 Register temp_reg,
1574 Register temp2_reg,
1575 Register temp3_reg,
1576 Register result_reg,
1577 FloatRegister vtemp,
1578 Label* L_success,
1579 Label* L_failure,
1580 bool set_cond_codes) {
1581 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
1582
1583 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1584
1585 Label L_fallthrough;
1586 int label_nulls = 0;
1587 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1588 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1589 assert(label_nulls <= 1, "at most one null in the batch");
1590
1591 BLOCK_COMMENT("check_klass_subtype_slow_path");
1592
1593 RegSetIterator<Register> available_regs
1594 = (RegSet::range(r0, r15) - temps - sub_klass - super_klass).begin();
1595
1596 RegSet pushed_regs;
1597
1598 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
1599 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
1600 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
1601 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
1602
1603 push(pushed_regs, sp);
1604
1605 lookup_secondary_supers_table_var(sub_klass,
1606 super_klass,
1607 temp_reg, temp2_reg, temp3_reg, vtemp, result_reg,
1608 nullptr);
1609 cmp(result_reg, zr);
1610
1611 // Unspill the temp. registers:
1612 pop(pushed_regs, sp);
1613
1614 // NB! Callers may assume that, when set_cond_codes is true, this
1615 // code sets temp2_reg to a nonzero value.
1616 if (set_cond_codes) {
1617 mov(temp2_reg, 1);
1618 }
1619
1620 br(Assembler::NE, *L_failure);
1621
1622 if (L_success != &L_fallthrough) {
1623 b(*L_success);
1624 }
1625
1626 bind(L_fallthrough);
1627 }
1628
1629 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1630 Register super_klass,
1631 Register temp_reg,
1632 Register temp2_reg,
1633 Label* L_success,
1634 Label* L_failure,
1635 bool set_cond_codes) {
1636 if (UseSecondarySupersTable) {
1637 check_klass_subtype_slow_path_table
1638 (sub_klass, super_klass, temp_reg, temp2_reg, /*temp3*/noreg, /*result*/noreg,
1639 /*vtemp*/fnoreg,
1640 L_success, L_failure, set_cond_codes);
1641 } else {
1642 check_klass_subtype_slow_path_linear
1643 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
1644 }
1645 }
1646
1647
1648 // Ensure that the inline code and the stub are using the same registers.
1649 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
1650 do { \
1651 assert(r_super_klass == r0 && \
1652 r_array_base == r1 && \
1653 r_array_length == r2 && \
1654 (r_array_index == r3 || r_array_index == noreg) && \
1655 (r_sub_klass == r4 || r_sub_klass == noreg) && \
1656 (r_bitmap == rscratch2 || r_bitmap == noreg) && \
1657 (result == r5 || result == noreg), "registers must match aarch64.ad"); \
1658 } while(0)
1659
1660 bool MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
1661 Register r_super_klass,
1662 Register temp1,
1663 Register temp2,
1664 Register temp3,
1665 FloatRegister vtemp,
1666 Register result,
1667 u1 super_klass_slot,
1668 bool stub_is_near) {
1669 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1670
1671 Label L_fallthrough;
1672
1673 BLOCK_COMMENT("lookup_secondary_supers_table {");
1674
1675 const Register
1676 r_array_base = temp1, // r1
1677 r_array_length = temp2, // r2
1678 r_array_index = temp3, // r3
1679 r_bitmap = rscratch2;
1680
1681 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1682
1683 u1 bit = super_klass_slot;
1684
1685 // Make sure that result is nonzero if the TBZ below misses.
1686 mov(result, 1);
1687
1688 // We're going to need the bitmap in a vector reg and in a core reg,
1689 // so load both now.
1690 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1691 if (bit != 0) {
1692 ldrd(vtemp, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1693 }
1694 // First check the bitmap to see if super_klass might be present. If
1695 // the bit is zero, we are certain that super_klass is not one of
1696 // the secondary supers.
1697 tbz(r_bitmap, bit, L_fallthrough);
1698
1699 // Get the first array index that can contain super_klass into r_array_index.
1700 if (bit != 0) {
1701 shld(vtemp, vtemp, Klass::SECONDARY_SUPERS_TABLE_MASK - bit);
1702 cnt(vtemp, T8B, vtemp);
1703 addv(vtemp, T8B, vtemp);
1704 fmovd(r_array_index, vtemp);
1705 } else {
1706 mov(r_array_index, (u1)1);
1707 }
1708 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1709
1710 // We will consult the secondary-super array.
1711 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1712
1713 // The value i in r_array_index is >= 1, so even though r_array_base
1714 // points to the length, we don't need to adjust it to point to the
1715 // data.
1716 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1717 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1718
1719 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1720 eor(result, result, r_super_klass);
1721 cbz(result, L_fallthrough); // Found a match
1722
1723 // Is there another entry to check? Consult the bitmap.
1724 tbz(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK, L_fallthrough);
1725
1726 // Linear probe.
1727 if (bit != 0) {
1728 ror(r_bitmap, r_bitmap, bit);
1729 }
1730
1731 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1732 // The next slot to be inspected, by the stub we're about to call,
1733 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1734 // have been checked.
1735 Address stub = RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub());
1736 if (stub_is_near) {
1737 bl(stub);
1738 } else {
1739 address call = trampoline_call(stub);
1740 if (call == nullptr) {
1741 return false; // trampoline allocation failed
1742 }
1743 }
1744
1745 BLOCK_COMMENT("} lookup_secondary_supers_table");
1746
1747 bind(L_fallthrough);
1748
1749 if (VerifySecondarySupers) {
1750 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1751 temp1, temp2, result); // r1, r2, r5
1752 }
1753 return true;
1754 }
1755
1756 // At runtime, return 0 in result if r_super_klass is a superclass of
1757 // r_sub_klass, otherwise return nonzero. Use this version of
1758 // lookup_secondary_supers_table() if you don't know ahead of time
1759 // which superclass will be searched for. Used by interpreter and
1760 // runtime stubs. It is larger and has somewhat greater latency than
1761 // the version above, which takes a constant super_klass_slot.
1762 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
1763 Register r_super_klass,
1764 Register temp1,
1765 Register temp2,
1766 Register temp3,
1767 FloatRegister vtemp,
1768 Register result,
1769 Label *L_success) {
1770 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1771
1772 Label L_fallthrough;
1773
1774 BLOCK_COMMENT("lookup_secondary_supers_table {");
1775
1776 const Register
1777 r_array_index = temp3,
1778 slot = rscratch1,
1779 r_bitmap = rscratch2;
1780
1781 ldrb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
1782
1783 // Make sure that result is nonzero if the test below misses.
1784 mov(result, 1);
1785
1786 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1787
1788 // First check the bitmap to see if super_klass might be present. If
1789 // the bit is zero, we are certain that super_klass is not one of
1790 // the secondary supers.
1791
1792 // This next instruction is equivalent to:
1793 // mov(tmp_reg, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1794 // sub(temp2, tmp_reg, slot);
1795 eor(temp2, slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1796 lslv(temp2, r_bitmap, temp2);
1797 tbz(temp2, Klass::SECONDARY_SUPERS_TABLE_SIZE - 1, L_fallthrough);
1798
1799 bool must_save_v0 = (vtemp == fnoreg);
1800 if (must_save_v0) {
1801 // temp1 and result are free, so use them to preserve vtemp
1802 vtemp = v0;
1803 mov(temp1, vtemp, D, 0);
1804 mov(result, vtemp, D, 1);
1805 }
1806
1807 // Get the first array index that can contain super_klass into r_array_index.
1808 mov(vtemp, D, 0, temp2);
1809 cnt(vtemp, T8B, vtemp);
1810 addv(vtemp, T8B, vtemp);
1811 mov(r_array_index, vtemp, D, 0);
1812
1813 if (must_save_v0) {
1814 mov(vtemp, D, 0, temp1 );
1815 mov(vtemp, D, 1, result);
1816 }
1817
1818 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1819
1820 const Register
1821 r_array_base = temp1,
1822 r_array_length = temp2;
1823
1824 // The value i in r_array_index is >= 1, so even though r_array_base
1825 // points to the length, we don't need to adjust it to point to the
1826 // data.
1827 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1828 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1829
1830 // We will consult the secondary-super array.
1831 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1832
1833 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1834 eor(result, result, r_super_klass);
1835 cbz(result, L_success ? *L_success : L_fallthrough); // Found a match
1836
1837 // Is there another entry to check? Consult the bitmap.
1838 rorv(r_bitmap, r_bitmap, slot);
1839 // rol(r_bitmap, r_bitmap, 1);
1840 tbz(r_bitmap, 1, L_fallthrough);
1841
1842 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1843 // The next slot to be inspected, by the logic we're about to call,
1844 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1845 // have been checked.
1846 lookup_secondary_supers_table_slow_path(r_super_klass, r_array_base, r_array_index,
1847 r_bitmap, r_array_length, result, /*is_stub*/false);
1848
1849 BLOCK_COMMENT("} lookup_secondary_supers_table");
1850
1851 bind(L_fallthrough);
1852
1853 if (VerifySecondarySupers) {
1854 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1855 temp1, temp2, result); // r1, r2, r5
1856 }
1857
1858 if (L_success) {
1859 cbz(result, *L_success);
1860 }
1861 }
1862
1863 // Called by code generated by check_klass_subtype_slow_path
1864 // above. This is called when there is a collision in the hashed
1865 // lookup in the secondary supers array.
1866 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
1867 Register r_array_base,
1868 Register r_array_index,
1869 Register r_bitmap,
1870 Register temp1,
1871 Register result,
1872 bool is_stub) {
1873 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, result, rscratch1);
1874
1875 const Register
1876 r_array_length = temp1,
1877 r_sub_klass = noreg; // unused
1878
1879 if (is_stub) {
1880 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1881 }
1882
1883 Label L_fallthrough, L_huge;
1884
1885 // Load the array length.
1886 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1887 // And adjust the array base to point to the data.
1888 // NB! Effectively increments current slot index by 1.
1889 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
1890 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1891
1892 // The bitmap is full to bursting.
1893 // Implicit invariant: BITMAP_FULL implies (length > 0)
1894 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
1895 cmpw(r_array_length, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 2));
1896 br(GT, L_huge);
1897
1898 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
1899 // current slot (at secondary_supers[r_array_index]) has not yet
1900 // been inspected, and r_array_index may be out of bounds if we
1901 // wrapped around the end of the array.
1902
1903 { // This is conventional linear probing, but instead of terminating
1904 // when a null entry is found in the table, we maintain a bitmap
1905 // in which a 0 indicates missing entries.
1906 // As long as the bitmap is not completely full,
1907 // array_length == popcount(bitmap). The array_length check above
1908 // guarantees there are 0s in the bitmap, so the loop eventually
1909 // terminates.
1910 Label L_loop;
1911 bind(L_loop);
1912
1913 // Check for wraparound.
1914 cmp(r_array_index, r_array_length);
1915 csel(r_array_index, zr, r_array_index, GE);
1916
1917 ldr(rscratch1, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1918 eor(result, rscratch1, r_super_klass);
1919 cbz(result, L_fallthrough);
1920
1921 tbz(r_bitmap, 2, L_fallthrough); // look-ahead check (Bit 2); result is non-zero
1922
1923 ror(r_bitmap, r_bitmap, 1);
1924 add(r_array_index, r_array_index, 1);
1925 b(L_loop);
1926 }
1927
1928 { // Degenerate case: more than 64 secondary supers.
1929 // FIXME: We could do something smarter here, maybe a vectorized
1930 // comparison or a binary search, but is that worth any added
1931 // complexity?
1932 bind(L_huge);
1933 cmp(sp, zr); // Clear Z flag; SP is never zero
1934 repne_scan(r_array_base, r_super_klass, r_array_length, rscratch1);
1935 cset(result, NE); // result == 0 iff we got a match.
1936 }
1937
1938 bind(L_fallthrough);
1939 }
1940
1941 // Make sure that the hashed lookup and a linear scan agree.
1942 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
1943 Register r_super_klass,
1944 Register temp1,
1945 Register temp2,
1946 Register result) {
1947 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, result, rscratch1);
1948
1949 const Register
1950 r_array_base = temp1,
1951 r_array_length = temp2;
1952
1953 BLOCK_COMMENT("verify_secondary_supers_table {");
1954
1955 // We will consult the secondary-super array.
1956 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1957
1958 // Load the array length.
1959 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1960 // And adjust the array base to point to the data.
1961 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1962
1963 cmp(sp, zr); // Clear Z flag; SP is never zero
1964 // Scan R2 words at [R5] for an occurrence of R0.
1965 // Set NZ/Z based on last compare.
1966 repne_scan(/*addr*/r_array_base, /*value*/r_super_klass, /*count*/r_array_length, rscratch2);
1967 // rscratch1 == 0 iff we got a match.
1968 cset(rscratch1, NE);
1969
1970 Label passed;
1971 cmp(result, zr);
1972 cset(result, NE); // normalize result to 0/1 for comparison
1973
1974 cmp(rscratch1, result);
1975 br(EQ, passed);
1976 {
1977 mov(r0, r_super_klass); // r0 <- r0
1978 mov(r1, r_sub_klass); // r1 <- r4
1979 mov(r2, /*expected*/rscratch1); // r2 <- r8
1980 mov(r3, result); // r3 <- r5
1981 mov(r4, (address)("mismatch")); // r4 <- const
1982 rt_call(CAST_FROM_FN_PTR(address, Klass::on_secondary_supers_verification_failure), rscratch2);
1983 should_not_reach_here();
1984 }
1985 bind(passed);
1986
1987 BLOCK_COMMENT("} verify_secondary_supers_table");
1988 }
1989
1990 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) {
1991 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
1992 assert_different_registers(klass, rthread, scratch);
1993
1994 Label L_fallthrough, L_tmp;
1995 if (L_fast_path == nullptr) {
1996 L_fast_path = &L_fallthrough;
1997 } else if (L_slow_path == nullptr) {
1998 L_slow_path = &L_fallthrough;
1999 }
2000 // Fast path check: class is fully initialized
2001 lea(scratch, Address(klass, InstanceKlass::init_state_offset()));
2002 ldarb(scratch, scratch);
2003 cmp(scratch, InstanceKlass::fully_initialized);
2004 br(Assembler::EQ, *L_fast_path);
2005
2006 // Fast path check: current thread is initializer thread
2007 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
2008 cmp(rthread, scratch);
2009
2010 if (L_slow_path == &L_fallthrough) {
2011 br(Assembler::EQ, *L_fast_path);
2012 bind(*L_slow_path);
2013 } else if (L_fast_path == &L_fallthrough) {
2014 br(Assembler::NE, *L_slow_path);
2015 bind(*L_fast_path);
2016 } else {
2017 Unimplemented();
2018 }
2019 }
2020
2021 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
2022 if (!VerifyOops) return;
2023
2024 // Pass register number to verify_oop_subroutine
2025 const char* b = nullptr;
2026 {
2027 ResourceMark rm;
2028 stringStream ss;
2029 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
2030 b = code_string(ss.as_string());
2031 }
2032 BLOCK_COMMENT("verify_oop {");
2033
2034 strip_return_address(); // This might happen within a stack frame.
2035 protect_return_address();
2036 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2037 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2038
2039 mov(r0, reg);
2040 movptr(rscratch1, (uintptr_t)(address)b);
2041
2042 // call indirectly to solve generation ordering problem
2043 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2044 ldr(rscratch2, Address(rscratch2));
2045 blr(rscratch2);
2046
2047 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2048 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2049 authenticate_return_address();
2050
2051 BLOCK_COMMENT("} verify_oop");
2052 }
2053
2054 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
2055 if (!VerifyOops) return;
2056
2057 const char* b = nullptr;
2058 {
2059 ResourceMark rm;
2060 stringStream ss;
2061 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
2062 b = code_string(ss.as_string());
2063 }
2064 BLOCK_COMMENT("verify_oop_addr {");
2065
2066 strip_return_address(); // This might happen within a stack frame.
2067 protect_return_address();
2068 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2069 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2070
2071 // addr may contain sp so we will have to adjust it based on the
2072 // pushes that we just did.
2073 if (addr.uses(sp)) {
2074 lea(r0, addr);
2075 ldr(r0, Address(r0, 4 * wordSize));
2076 } else {
2077 ldr(r0, addr);
2078 }
2079 movptr(rscratch1, (uintptr_t)(address)b);
2080
2081 // call indirectly to solve generation ordering problem
2082 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2083 ldr(rscratch2, Address(rscratch2));
2084 blr(rscratch2);
2085
2086 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2087 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2088 authenticate_return_address();
2089
2090 BLOCK_COMMENT("} verify_oop_addr");
2091 }
2092
2093 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
2094 int extra_slot_offset) {
2095 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2096 int stackElementSize = Interpreter::stackElementSize;
2097 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
2098 #ifdef ASSERT
2099 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
2100 assert(offset1 - offset == stackElementSize, "correct arithmetic");
2101 #endif
2102 if (arg_slot.is_constant()) {
2103 return Address(esp, arg_slot.as_constant() * stackElementSize
2104 + offset);
2105 } else {
2106 add(rscratch1, esp, arg_slot.as_register(),
2107 ext::uxtx, exact_log2(stackElementSize));
2108 return Address(rscratch1, offset);
2109 }
2110 }
2111
2112 // Handle the receiver type profile update given the "recv" klass.
2113 //
2114 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
2115 // If there are no matching or claimable receiver entries in RD, updates
2116 // the polymorphic counter.
2117 //
2118 // This code expected to run by either the interpreter or JIT-ed code, without
2119 // extra synchronization. For safety, receiver cells are claimed atomically, which
2120 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
2121 // counter updates are not atomic.
2122 //
2123 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
2124 assert_different_registers(recv, mdp, rscratch1, rscratch2);
2125
2126 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
2127 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
2128 int poly_count_offset = in_bytes(CounterData::count_offset());
2129 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
2130 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
2131
2132 // Adjust for MDP offsets.
2133 base_receiver_offset += mdp_offset;
2134 end_receiver_offset += mdp_offset;
2135 poly_count_offset += mdp_offset;
2136
2137 #ifdef ASSERT
2138 // We are about to walk the MDO slots without asking for offsets.
2139 // Check that our math hits all the right spots.
2140 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
2141 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
2142 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
2143 int offset = base_receiver_offset + receiver_step*c;
2144 int count_offset = offset + receiver_to_count_step;
2145 assert(offset == real_recv_offset, "receiver slot math");
2146 assert(count_offset == real_count_offset, "receiver count math");
2147 }
2148 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
2149 assert(poly_count_offset == real_poly_count_offset, "poly counter math");
2150 #endif
2151
2152 // Corner case: no profile table. Increment poly counter and exit.
2153 if (ReceiverTypeData::row_limit() == 0) {
2154 increment(Address(mdp, poly_count_offset), DataLayout::counter_increment);
2155 return;
2156 }
2157
2158 Register offset = rscratch2;
2159
2160 Label L_loop_search_receiver, L_loop_search_empty;
2161 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
2162
2163 // The code here recognizes three major cases:
2164 // A. Fastest: receiver found in the table
2165 // B. Fast: no receiver in the table, and the table is full
2166 // C. Slow: no receiver in the table, free slots in the table
2167 //
2168 // The case A performance is most important, as perfectly-behaved code would end up
2169 // there, especially with larger TypeProfileWidth. The case B performance is
2170 // important as well, this is where bulk of code would land for normally megamorphic
2171 // cases. The case C performance is not essential, its job is to deal with installation
2172 // races, we optimize for code density instead. Case C needs to make sure that receiver
2173 // rows are only claimed once. This makes sure we never overwrite a row for another
2174 // receiver and never duplicate the receivers in the list, making profile type-accurate.
2175 //
2176 // It is very tempting to handle these cases in a single loop, and claim the first slot
2177 // without checking the rest of the table. But, profiling code should tolerate free slots
2178 // in the table, as class unloading can clear them. After such cleanup, the receiver
2179 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
2180 // to complete, before trying to install new slots. Splitting the code in several tight
2181 // loops also helpfully optimizes for cases A and B.
2182 //
2183 // This code is effectively:
2184 //
2185 // restart:
2186 // // Fastest: receiver is already installed
2187 // for (i = 0; i < receiver_count(); i++) {
2188 // if (receiver(i) == recv) goto found_recv(i);
2189 // }
2190 //
2191 // // Fast: no receiver, but profile is full
2192 // for (i = 0; i < receiver_count(); i++) {
2193 // if (receiver(i) == null) goto found_null(i);
2194 // }
2195 // goto polymorphic
2196 //
2197 // // Slow: try to install receiver
2198 // found_null(i):
2199 // CAS(&receiver(i), null, recv);
2200 // goto restart
2201 //
2202 // polymorphic:
2203 // count++;
2204 // return
2205 //
2206 // found_recv(i):
2207 // *receiver_count(i)++
2208 //
2209
2210 bind(L_restart);
2211
2212 // Fastest: receiver is already installed
2213 mov(offset, base_receiver_offset);
2214 bind(L_loop_search_receiver);
2215 ldr(rscratch1, Address(mdp, offset));
2216 cmp(rscratch1, recv);
2217 br(Assembler::EQ, L_found_recv);
2218 add(offset, offset, receiver_step);
2219 sub(rscratch1, offset, end_receiver_offset);
2220 cbnz(rscratch1, L_loop_search_receiver);
2221
2222 // Fast: no receiver, but profile is full
2223 mov(offset, base_receiver_offset);
2224 bind(L_loop_search_empty);
2225 ldr(rscratch1, Address(mdp, offset));
2226 cbz(rscratch1, L_found_empty);
2227 add(offset, offset, receiver_step);
2228 sub(rscratch1, offset, end_receiver_offset);
2229 cbnz(rscratch1, L_loop_search_empty);
2230 b(L_polymorphic);
2231
2232 // Slow: try to install receiver
2233 bind(L_found_empty);
2234
2235 // Atomically swing receiver slot: null -> recv.
2236 //
2237 // The update uses CAS, which clobbers rscratch1. Therefore, rscratch2
2238 // is used to hold the destination address. This is safe because the
2239 // offset is no longer needed after the address is computed.
2240
2241 lea(rscratch2, Address(mdp, offset));
2242 cmpxchg(/*addr*/ rscratch2, /*expected*/ zr, /*new*/ recv, Assembler::xword,
2243 /*acquire*/ false, /*release*/ false, /*weak*/ true, noreg);
2244
2245 // CAS success means the slot now has the receiver we want. CAS failure means
2246 // something had claimed the slot concurrently: it can be the same receiver we want,
2247 // or something else. Since this is a slow path, we can optimize for code density,
2248 // and just restart the search from the beginning.
2249 b(L_restart);
2250
2251 // Counter updates:
2252
2253 // Increment polymorphic counter instead of receiver slot.
2254 bind(L_polymorphic);
2255 mov(offset, poly_count_offset);
2256 b(L_count_update);
2257
2258 // Found a receiver, convert its slot offset to corresponding count offset.
2259 bind(L_found_recv);
2260 add(offset, offset, receiver_to_count_step);
2261
2262 bind(L_count_update);
2263 increment(Address(mdp, offset), DataLayout::counter_increment);
2264 }
2265
2266
2267 void MacroAssembler::call_VM_leaf_base(address entry_point,
2268 int number_of_arguments,
2269 Label *retaddr) {
2270 Label E, L;
2271
2272 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
2273
2274 mov(rscratch1, RuntimeAddress(entry_point));
2275 blr(rscratch1);
2276 if (retaddr)
2277 bind(*retaddr);
2278
2279 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
2280 }
2281
2282 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2283 call_VM_leaf_base(entry_point, number_of_arguments);
2284 }
2285
2286 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2287 pass_arg0(this, arg_0);
2288 call_VM_leaf_base(entry_point, 1);
2289 }
2290
2291 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2292 assert_different_registers(arg_1, c_rarg0);
2293 pass_arg0(this, arg_0);
2294 pass_arg1(this, arg_1);
2295 call_VM_leaf_base(entry_point, 2);
2296 }
2297
2298 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2299 Register arg_1, Register arg_2) {
2300 assert_different_registers(arg_1, c_rarg0);
2301 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2302 pass_arg0(this, arg_0);
2303 pass_arg1(this, arg_1);
2304 pass_arg2(this, arg_2);
2305 call_VM_leaf_base(entry_point, 3);
2306 }
2307
2308 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2309 pass_arg0(this, arg_0);
2310 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2311 }
2312
2313 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2314
2315 assert_different_registers(arg_0, c_rarg1);
2316 pass_arg1(this, arg_1);
2317 pass_arg0(this, arg_0);
2318 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2319 }
2320
2321 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2322 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2323 assert_different_registers(arg_1, c_rarg2);
2324 pass_arg2(this, arg_2);
2325 pass_arg1(this, arg_1);
2326 pass_arg0(this, arg_0);
2327 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2328 }
2329
2330 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2331 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
2332 assert_different_registers(arg_1, c_rarg2, c_rarg3);
2333 assert_different_registers(arg_2, c_rarg3);
2334 pass_arg3(this, arg_3);
2335 pass_arg2(this, arg_2);
2336 pass_arg1(this, arg_1);
2337 pass_arg0(this, arg_0);
2338 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2339 }
2340
2341 void MacroAssembler::null_check(Register reg, int offset) {
2342 if (needs_explicit_null_check(offset)) {
2343 // provoke OS null exception if reg is null by
2344 // accessing M[reg] w/o changing any registers
2345 // NOTE: this is plenty to provoke a segv
2346 ldr(zr, Address(reg));
2347 } else {
2348 // nothing to do, (later) access of M[reg + offset]
2349 // will provoke OS null exception if reg is null
2350 }
2351 }
2352
2353 // MacroAssembler protected routines needed to implement
2354 // public methods
2355
2356 void MacroAssembler::mov(Register r, Address dest) {
2357 code_section()->relocate(pc(), dest.rspec());
2358 uint64_t imm64 = (uint64_t)dest.target();
2359 movptr(r, imm64);
2360 }
2361
2362 // Move a constant pointer into r. In AArch64 mode the virtual
2363 // address space is 48 bits in size, so we only need three
2364 // instructions to create a patchable instruction sequence that can
2365 // reach anywhere.
2366 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2367 #ifndef PRODUCT
2368 {
2369 char buffer[64];
2370 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2371 block_comment(buffer);
2372 }
2373 #endif
2374 assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
2375 movz(r, imm64 & 0xffff);
2376 imm64 >>= 16;
2377 movk(r, imm64 & 0xffff, 16);
2378 imm64 >>= 16;
2379 movk(r, imm64 & 0xffff, 32);
2380 }
2381
2382 // Macro to mov replicated immediate to vector register.
2383 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is,
2384 // the upper 56/48/32 bits must be zeros for B/H/S type.
2385 // Vd will get the following values for different arrangements in T
2386 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh
2387 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
2388 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh
2389 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
2390 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
2391 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
2392 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh
2393 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh
2394 // Clobbers rscratch1
2395 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) {
2396 assert(T != T1Q, "unsupported");
2397 if (T == T1D || T == T2D) {
2398 int imm = operand_valid_for_movi_immediate(imm64, T);
2399 if (-1 != imm) {
2400 movi(Vd, T, imm);
2401 } else {
2402 mov(rscratch1, imm64);
2403 dup(Vd, T, rscratch1);
2404 }
2405 return;
2406 }
2407
2408 #ifdef ASSERT
2409 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)");
2410 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)");
2411 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)");
2412 #endif
2413 int shift = operand_valid_for_movi_immediate(imm64, T);
2414 uint32_t imm32 = imm64 & 0xffffffffULL;
2415 if (shift >= 0) {
2416 movi(Vd, T, (imm32 >> shift) & 0xff, shift);
2417 } else {
2418 movw(rscratch1, imm32);
2419 dup(Vd, T, rscratch1);
2420 }
2421 }
2422
2423 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
2424 {
2425 #ifndef PRODUCT
2426 {
2427 char buffer[64];
2428 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, imm64);
2429 block_comment(buffer);
2430 }
2431 #endif
2432 if (operand_valid_for_logical_immediate(false, imm64)) {
2433 orr(dst, zr, imm64);
2434 } else {
2435 // we can use a combination of MOVZ or MOVN with
2436 // MOVK to build up the constant
2437 uint64_t imm_h[4];
2438 int zero_count = 0;
2439 int neg_count = 0;
2440 int i;
2441 for (i = 0; i < 4; i++) {
2442 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
2443 if (imm_h[i] == 0) {
2444 zero_count++;
2445 } else if (imm_h[i] == 0xffffL) {
2446 neg_count++;
2447 }
2448 }
2449 if (zero_count == 4) {
2450 // one MOVZ will do
2451 movz(dst, 0);
2452 } else if (neg_count == 4) {
2453 // one MOVN will do
2454 movn(dst, 0);
2455 } else if (zero_count == 3) {
2456 for (i = 0; i < 4; i++) {
2457 if (imm_h[i] != 0L) {
2458 movz(dst, (uint32_t)imm_h[i], (i << 4));
2459 break;
2460 }
2461 }
2462 } else if (neg_count == 3) {
2463 // one MOVN will do
2464 for (int i = 0; i < 4; i++) {
2465 if (imm_h[i] != 0xffffL) {
2466 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2467 break;
2468 }
2469 }
2470 } else if (zero_count == 2) {
2471 // one MOVZ and one MOVK will do
2472 for (i = 0; i < 3; i++) {
2473 if (imm_h[i] != 0L) {
2474 movz(dst, (uint32_t)imm_h[i], (i << 4));
2475 i++;
2476 break;
2477 }
2478 }
2479 for (;i < 4; i++) {
2480 if (imm_h[i] != 0L) {
2481 movk(dst, (uint32_t)imm_h[i], (i << 4));
2482 }
2483 }
2484 } else if (neg_count == 2) {
2485 // one MOVN and one MOVK will do
2486 for (i = 0; i < 4; i++) {
2487 if (imm_h[i] != 0xffffL) {
2488 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2489 i++;
2490 break;
2491 }
2492 }
2493 for (;i < 4; i++) {
2494 if (imm_h[i] != 0xffffL) {
2495 movk(dst, (uint32_t)imm_h[i], (i << 4));
2496 }
2497 }
2498 } else if (zero_count == 1) {
2499 // one MOVZ and two MOVKs will do
2500 for (i = 0; i < 4; i++) {
2501 if (imm_h[i] != 0L) {
2502 movz(dst, (uint32_t)imm_h[i], (i << 4));
2503 i++;
2504 break;
2505 }
2506 }
2507 for (;i < 4; i++) {
2508 if (imm_h[i] != 0x0L) {
2509 movk(dst, (uint32_t)imm_h[i], (i << 4));
2510 }
2511 }
2512 } else if (neg_count == 1) {
2513 // one MOVN and two MOVKs will do
2514 for (i = 0; i < 4; i++) {
2515 if (imm_h[i] != 0xffffL) {
2516 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2517 i++;
2518 break;
2519 }
2520 }
2521 for (;i < 4; i++) {
2522 if (imm_h[i] != 0xffffL) {
2523 movk(dst, (uint32_t)imm_h[i], (i << 4));
2524 }
2525 }
2526 } else {
2527 // use a MOVZ and 3 MOVKs (makes it easier to debug)
2528 movz(dst, (uint32_t)imm_h[0], 0);
2529 for (i = 1; i < 4; i++) {
2530 movk(dst, (uint32_t)imm_h[i], (i << 4));
2531 }
2532 }
2533 }
2534 }
2535
2536 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
2537 {
2538 #ifndef PRODUCT
2539 {
2540 char buffer[64];
2541 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX32, imm32);
2542 block_comment(buffer);
2543 }
2544 #endif
2545 if (operand_valid_for_logical_immediate(true, imm32)) {
2546 orrw(dst, zr, imm32);
2547 } else {
2548 // we can use MOVZ, MOVN or two calls to MOVK to build up the
2549 // constant
2550 uint32_t imm_h[2];
2551 imm_h[0] = imm32 & 0xffff;
2552 imm_h[1] = ((imm32 >> 16) & 0xffff);
2553 if (imm_h[0] == 0) {
2554 movzw(dst, imm_h[1], 16);
2555 } else if (imm_h[0] == 0xffff) {
2556 movnw(dst, imm_h[1] ^ 0xffff, 16);
2557 } else if (imm_h[1] == 0) {
2558 movzw(dst, imm_h[0], 0);
2559 } else if (imm_h[1] == 0xffff) {
2560 movnw(dst, imm_h[0] ^ 0xffff, 0);
2561 } else {
2562 // use a MOVZ and MOVK (makes it easier to debug)
2563 movzw(dst, imm_h[0], 0);
2564 movkw(dst, imm_h[1], 16);
2565 }
2566 }
2567 }
2568
2569 // Form an address from base + offset in Rd. Rd may or may
2570 // not actually be used: you must use the Address that is returned.
2571 // It is up to you to ensure that the shift provided matches the size
2572 // of your data.
2573 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
2574 if (Address::offset_ok_for_immed(byte_offset, shift))
2575 // It fits; no need for any heroics
2576 return Address(base, byte_offset);
2577
2578 // Don't do anything clever with negative or misaligned offsets
2579 unsigned mask = (1 << shift) - 1;
2580 if (byte_offset < 0 || byte_offset & mask) {
2581 mov(Rd, byte_offset);
2582 add(Rd, base, Rd);
2583 return Address(Rd);
2584 }
2585
2586 // See if we can do this with two 12-bit offsets
2587 {
2588 uint64_t word_offset = byte_offset >> shift;
2589 uint64_t masked_offset = word_offset & 0xfff000;
2590 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
2591 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
2592 add(Rd, base, masked_offset << shift);
2593 word_offset -= masked_offset;
2594 return Address(Rd, word_offset << shift);
2595 }
2596 }
2597
2598 // Do it the hard way
2599 mov(Rd, byte_offset);
2600 add(Rd, base, Rd);
2601 return Address(Rd);
2602 }
2603
2604 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
2605 bool want_remainder, Register scratch)
2606 {
2607 // Full implementation of Java idiv and irem. The function
2608 // returns the (pc) offset of the div instruction - may be needed
2609 // for implicit exceptions.
2610 //
2611 // constraint : ra/rb =/= scratch
2612 // normal case
2613 //
2614 // input : ra: dividend
2615 // rb: divisor
2616 //
2617 // result: either
2618 // quotient (= ra idiv rb)
2619 // remainder (= ra irem rb)
2620
2621 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2622
2623 int idivl_offset = offset();
2624 if (! want_remainder) {
2625 sdivw(result, ra, rb);
2626 } else {
2627 sdivw(scratch, ra, rb);
2628 Assembler::msubw(result, scratch, rb, ra);
2629 }
2630
2631 return idivl_offset;
2632 }
2633
2634 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
2635 bool want_remainder, Register scratch)
2636 {
2637 // Full implementation of Java ldiv and lrem. The function
2638 // returns the (pc) offset of the div instruction - may be needed
2639 // for implicit exceptions.
2640 //
2641 // constraint : ra/rb =/= scratch
2642 // normal case
2643 //
2644 // input : ra: dividend
2645 // rb: divisor
2646 //
2647 // result: either
2648 // quotient (= ra idiv rb)
2649 // remainder (= ra irem rb)
2650
2651 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2652
2653 int idivq_offset = offset();
2654 if (! want_remainder) {
2655 sdiv(result, ra, rb);
2656 } else {
2657 sdiv(scratch, ra, rb);
2658 Assembler::msub(result, scratch, rb, ra);
2659 }
2660
2661 return idivq_offset;
2662 }
2663
2664 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
2665 address prev = pc() - NativeMembar::instruction_size;
2666 address last = code()->last_insn();
2667 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) {
2668 NativeMembar *bar = NativeMembar_at(prev);
2669 if (AlwaysMergeDMB) {
2670 bar->set_kind(bar->get_kind() | order_constraint);
2671 BLOCK_COMMENT("merged membar(always)");
2672 return;
2673 }
2674 // Don't promote DMB ST|DMB LD to DMB (a full barrier) because
2675 // doing so would introduce a StoreLoad which the caller did not
2676 // intend
2677 if (bar->get_kind() == order_constraint
2678 || bar->get_kind() == AnyAny
2679 || order_constraint == AnyAny) {
2680 // We are merging two memory barrier instructions. On AArch64 we
2681 // can do this simply by ORing them together.
2682 bar->set_kind(bar->get_kind() | order_constraint);
2683 BLOCK_COMMENT("merged membar");
2684 return;
2685 } else {
2686 // A special case like "DMB ST;DMB LD;DMB ST", the last DMB can be skipped
2687 // We need check the last 2 instructions
2688 address prev2 = prev - NativeMembar::instruction_size;
2689 if (last != code()->last_label() && nativeInstruction_at(prev2)->is_Membar()) {
2690 NativeMembar *bar2 = NativeMembar_at(prev2);
2691 assert(bar2->get_kind() == order_constraint, "it should be merged before");
2692 BLOCK_COMMENT("merged membar(elided)");
2693 return;
2694 }
2695 }
2696 }
2697 code()->set_last_insn(pc());
2698 dmb(Assembler::barrier(order_constraint));
2699 }
2700
2701 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
2702 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
2703 merge_ldst(rt, adr, size_in_bytes, is_store);
2704 code()->clear_last_insn();
2705 return true;
2706 } else {
2707 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
2708 const uint64_t mask = size_in_bytes - 1;
2709 if (adr.getMode() == Address::base_plus_offset &&
2710 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
2711 code()->set_last_insn(pc());
2712 }
2713 return false;
2714 }
2715 }
2716
2717 void MacroAssembler::ldr(Register Rx, const Address &adr) {
2718 // We always try to merge two adjacent loads into one ldp.
2719 if (!try_merge_ldst(Rx, adr, 8, false)) {
2720 Assembler::ldr(Rx, adr);
2721 }
2722 }
2723
2724 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
2725 // We always try to merge two adjacent loads into one ldp.
2726 if (!try_merge_ldst(Rw, adr, 4, false)) {
2727 Assembler::ldrw(Rw, adr);
2728 }
2729 }
2730
2731 void MacroAssembler::str(Register Rx, const Address &adr) {
2732 // We always try to merge two adjacent stores into one stp.
2733 if (!try_merge_ldst(Rx, adr, 8, true)) {
2734 Assembler::str(Rx, adr);
2735 }
2736 }
2737
2738 void MacroAssembler::strw(Register Rw, const Address &adr) {
2739 // We always try to merge two adjacent stores into one stp.
2740 if (!try_merge_ldst(Rw, adr, 4, true)) {
2741 Assembler::strw(Rw, adr);
2742 }
2743 }
2744
2745 // MacroAssembler routines found actually to be needed
2746
2747 void MacroAssembler::push(Register src)
2748 {
2749 str(src, Address(pre(esp, -1 * wordSize)));
2750 }
2751
2752 void MacroAssembler::pop(Register dst)
2753 {
2754 ldr(dst, Address(post(esp, 1 * wordSize)));
2755 }
2756
2757 // Note: load_unsigned_short used to be called load_unsigned_word.
2758 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2759 int off = offset();
2760 ldrh(dst, src);
2761 return off;
2762 }
2763
2764 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2765 int off = offset();
2766 ldrb(dst, src);
2767 return off;
2768 }
2769
2770 int MacroAssembler::load_signed_short(Register dst, Address src) {
2771 int off = offset();
2772 ldrsh(dst, src);
2773 return off;
2774 }
2775
2776 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2777 int off = offset();
2778 ldrsb(dst, src);
2779 return off;
2780 }
2781
2782 int MacroAssembler::load_signed_short32(Register dst, Address src) {
2783 int off = offset();
2784 ldrshw(dst, src);
2785 return off;
2786 }
2787
2788 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
2789 int off = offset();
2790 ldrsbw(dst, src);
2791 return off;
2792 }
2793
2794 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2795 switch (size_in_bytes) {
2796 case 8: ldr(dst, src); break;
2797 case 4: ldrw(dst, src); break;
2798 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2799 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2800 default: ShouldNotReachHere();
2801 }
2802 }
2803
2804 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) {
2805 switch (size_in_bytes) {
2806 case 8: str(src, dst); break;
2807 case 4: strw(src, dst); break;
2808 case 2: strh(src, dst); break;
2809 case 1: strb(src, dst); break;
2810 default: ShouldNotReachHere();
2811 }
2812 }
2813
2814 void MacroAssembler::decrementw(Register reg, int value)
2815 {
2816 if (value < 0) { incrementw(reg, -value); return; }
2817 if (value == 0) { return; }
2818 if (value < (1 << 12)) { subw(reg, reg, value); return; }
2819 /* else */ {
2820 guarantee(reg != rscratch2, "invalid dst for register decrement");
2821 movw(rscratch2, (unsigned)value);
2822 subw(reg, reg, rscratch2);
2823 }
2824 }
2825
2826 void MacroAssembler::decrement(Register reg, int value)
2827 {
2828 if (value < 0) { increment(reg, -value); return; }
2829 if (value == 0) { return; }
2830 if (value < (1 << 12)) { sub(reg, reg, value); return; }
2831 /* else */ {
2832 assert(reg != rscratch2, "invalid dst for register decrement");
2833 mov(rscratch2, (uint64_t)value);
2834 sub(reg, reg, rscratch2);
2835 }
2836 }
2837
2838 void MacroAssembler::decrementw(Address dst, int value)
2839 {
2840 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
2841 if (dst.getMode() == Address::literal) {
2842 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2843 lea(rscratch2, dst);
2844 dst = Address(rscratch2);
2845 }
2846 ldrw(rscratch1, dst);
2847 decrementw(rscratch1, value);
2848 strw(rscratch1, dst);
2849 }
2850
2851 void MacroAssembler::decrement(Address dst, int value)
2852 {
2853 assert(!dst.uses(rscratch1), "invalid address for decrement");
2854 if (dst.getMode() == Address::literal) {
2855 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2856 lea(rscratch2, dst);
2857 dst = Address(rscratch2);
2858 }
2859 ldr(rscratch1, dst);
2860 decrement(rscratch1, value);
2861 str(rscratch1, dst);
2862 }
2863
2864 void MacroAssembler::incrementw(Register reg, int value)
2865 {
2866 if (value < 0) { decrementw(reg, -value); return; }
2867 if (value == 0) { return; }
2868 if (value < (1 << 12)) { addw(reg, reg, value); return; }
2869 /* else */ {
2870 assert(reg != rscratch2, "invalid dst for register increment");
2871 movw(rscratch2, (unsigned)value);
2872 addw(reg, reg, rscratch2);
2873 }
2874 }
2875
2876 void MacroAssembler::increment(Register reg, int value)
2877 {
2878 if (value < 0) { decrement(reg, -value); return; }
2879 if (value == 0) { return; }
2880 if (value < (1 << 12)) { add(reg, reg, value); return; }
2881 /* else */ {
2882 assert(reg != rscratch2, "invalid dst for register increment");
2883 movw(rscratch2, (unsigned)value);
2884 add(reg, reg, rscratch2);
2885 }
2886 }
2887
2888 void MacroAssembler::incrementw(Address dst, int value)
2889 {
2890 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2891 if (dst.getMode() == Address::literal) {
2892 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2893 lea(rscratch2, dst);
2894 dst = Address(rscratch2);
2895 }
2896 ldrw(rscratch1, dst);
2897 incrementw(rscratch1, value);
2898 strw(rscratch1, dst);
2899 }
2900
2901 void MacroAssembler::increment(Address dst, int value)
2902 {
2903 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2904 if (dst.getMode() == Address::literal) {
2905 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2906 lea(rscratch2, dst);
2907 dst = Address(rscratch2);
2908 }
2909 ldr(rscratch1, dst);
2910 increment(rscratch1, value);
2911 str(rscratch1, dst);
2912 }
2913
2914 // Push lots of registers in the bit set supplied. Don't push sp.
2915 // Return the number of words pushed
2916 int MacroAssembler::push(unsigned int bitset, Register stack) {
2917 int words_pushed = 0;
2918
2919 // Scan bitset to accumulate register pairs
2920 unsigned char regs[32];
2921 int count = 0;
2922 for (int reg = 0; reg <= 30; reg++) {
2923 if (1 & bitset)
2924 regs[count++] = reg;
2925 bitset >>= 1;
2926 }
2927 regs[count++] = zr->raw_encoding();
2928 count &= ~1; // Only push an even number of regs
2929
2930 if (count) {
2931 stp(as_Register(regs[0]), as_Register(regs[1]),
2932 Address(pre(stack, -count * wordSize)));
2933 words_pushed += 2;
2934 }
2935 for (int i = 2; i < count; i += 2) {
2936 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2937 Address(stack, i * wordSize));
2938 words_pushed += 2;
2939 }
2940
2941 assert(words_pushed == count, "oops, pushed != count");
2942
2943 return count;
2944 }
2945
2946 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2947 int words_pushed = 0;
2948
2949 // Scan bitset to accumulate register pairs
2950 unsigned char regs[32];
2951 int count = 0;
2952 for (int reg = 0; reg <= 30; reg++) {
2953 if (1 & bitset)
2954 regs[count++] = reg;
2955 bitset >>= 1;
2956 }
2957 regs[count++] = zr->raw_encoding();
2958 count &= ~1;
2959
2960 for (int i = 2; i < count; i += 2) {
2961 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2962 Address(stack, i * wordSize));
2963 words_pushed += 2;
2964 }
2965 if (count) {
2966 ldp(as_Register(regs[0]), as_Register(regs[1]),
2967 Address(post(stack, count * wordSize)));
2968 words_pushed += 2;
2969 }
2970
2971 assert(words_pushed == count, "oops, pushed != count");
2972
2973 return count;
2974 }
2975
2976 // Push lots of registers in the bit set supplied. Don't push sp.
2977 // Return the number of dwords pushed
2978 int MacroAssembler::push_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
2979 int words_pushed = 0;
2980 bool use_sve = false;
2981 int sve_vector_size_in_bytes = 0;
2982
2983 #ifdef COMPILER2
2984 use_sve = Matcher::supports_scalable_vector();
2985 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
2986 #endif
2987
2988 // Scan bitset to accumulate register pairs
2989 unsigned char regs[32];
2990 int count = 0;
2991 for (int reg = 0; reg <= 31; reg++) {
2992 if (1 & bitset)
2993 regs[count++] = reg;
2994 bitset >>= 1;
2995 }
2996
2997 if (count == 0) {
2998 return 0;
2999 }
3000
3001 if (mode == PushPopFull) {
3002 if (use_sve && sve_vector_size_in_bytes > 16) {
3003 mode = PushPopSVE;
3004 } else {
3005 mode = PushPopNeon;
3006 }
3007 }
3008
3009 #ifndef PRODUCT
3010 {
3011 char buffer[48];
3012 if (mode == PushPopSVE) {
3013 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d SVE registers", count);
3014 } else if (mode == PushPopNeon) {
3015 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d Neon registers", count);
3016 } else {
3017 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d fp registers", count);
3018 }
3019 block_comment(buffer);
3020 }
3021 #endif
3022
3023 if (mode == PushPopSVE) {
3024 sub(stack, stack, sve_vector_size_in_bytes * count);
3025 for (int i = 0; i < count; i++) {
3026 sve_str(as_FloatRegister(regs[i]), Address(stack, i));
3027 }
3028 return count * sve_vector_size_in_bytes / 8;
3029 }
3030
3031 if (mode == PushPopNeon) {
3032 if (count == 1) {
3033 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2)));
3034 return 2;
3035 }
3036
3037 bool odd = (count & 1) == 1;
3038 int push_slots = count + (odd ? 1 : 0);
3039
3040 // Always pushing full 128 bit registers.
3041 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2)));
3042 words_pushed += 2;
3043
3044 for (int i = 2; i + 1 < count; i += 2) {
3045 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3046 words_pushed += 2;
3047 }
3048
3049 if (odd) {
3050 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3051 words_pushed++;
3052 }
3053
3054 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3055 return count * 2;
3056 }
3057
3058 if (mode == PushPopFp) {
3059 bool odd = (count & 1) == 1;
3060 int push_slots = count + (odd ? 1 : 0);
3061
3062 if (count == 1) {
3063 // Stack pointer must be 16 bytes aligned
3064 strd(as_FloatRegister(regs[0]), Address(pre(stack, -push_slots * wordSize)));
3065 return 1;
3066 }
3067
3068 stpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize)));
3069 words_pushed += 2;
3070
3071 for (int i = 2; i + 1 < count; i += 2) {
3072 stpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3073 words_pushed += 2;
3074 }
3075
3076 if (odd) {
3077 // Stack pointer must be 16 bytes aligned
3078 strd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3079 words_pushed++;
3080 }
3081
3082 assert(words_pushed == count, "oops, pushed != count");
3083
3084 return count;
3085 }
3086
3087 return 0;
3088 }
3089
3090 // Return the number of dwords popped
3091 int MacroAssembler::pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
3092 int words_pushed = 0;
3093 bool use_sve = false;
3094 int sve_vector_size_in_bytes = 0;
3095
3096 #ifdef COMPILER2
3097 use_sve = Matcher::supports_scalable_vector();
3098 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
3099 #endif
3100 // Scan bitset to accumulate register pairs
3101 unsigned char regs[32];
3102 int count = 0;
3103 for (int reg = 0; reg <= 31; reg++) {
3104 if (1 & bitset)
3105 regs[count++] = reg;
3106 bitset >>= 1;
3107 }
3108
3109 if (count == 0) {
3110 return 0;
3111 }
3112
3113 if (mode == PushPopFull) {
3114 if (use_sve && sve_vector_size_in_bytes > 16) {
3115 mode = PushPopSVE;
3116 } else {
3117 mode = PushPopNeon;
3118 }
3119 }
3120
3121 #ifndef PRODUCT
3122 {
3123 char buffer[48];
3124 if (mode == PushPopSVE) {
3125 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d SVE registers", count);
3126 } else if (mode == PushPopNeon) {
3127 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d Neon registers", count);
3128 } else {
3129 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d fp registers", count);
3130 }
3131 block_comment(buffer);
3132 }
3133 #endif
3134
3135 if (mode == PushPopSVE) {
3136 for (int i = count - 1; i >= 0; i--) {
3137 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i));
3138 }
3139 add(stack, stack, sve_vector_size_in_bytes * count);
3140 return count * sve_vector_size_in_bytes / 8;
3141 }
3142
3143 if (mode == PushPopNeon) {
3144 if (count == 1) {
3145 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2)));
3146 return 2;
3147 }
3148
3149 bool odd = (count & 1) == 1;
3150 int push_slots = count + (odd ? 1 : 0);
3151
3152 if (odd) {
3153 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3154 words_pushed++;
3155 }
3156
3157 for (int i = 2; i + 1 < count; i += 2) {
3158 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3159 words_pushed += 2;
3160 }
3161
3162 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2)));
3163 words_pushed += 2;
3164
3165 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3166
3167 return count * 2;
3168 }
3169
3170 if (mode == PushPopFp) {
3171 bool odd = (count & 1) == 1;
3172 int push_slots = count + (odd ? 1 : 0);
3173
3174 if (count == 1) {
3175 ldrd(as_FloatRegister(regs[0]), Address(post(stack, push_slots * wordSize)));
3176 return 1;
3177 }
3178
3179 if (odd) {
3180 ldrd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3181 words_pushed++;
3182 }
3183
3184 for (int i = 2; i + 1 < count; i += 2) {
3185 ldpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3186 words_pushed += 2;
3187 }
3188
3189 ldpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize)));
3190 words_pushed += 2;
3191
3192 assert(words_pushed == count, "oops, pushed != count");
3193
3194 return count;
3195 }
3196
3197 return 0;
3198 }
3199
3200 // Return the number of dwords pushed
3201 int MacroAssembler::push_p(unsigned int bitset, Register stack) {
3202 bool use_sve = false;
3203 int sve_predicate_size_in_slots = 0;
3204
3205 #ifdef COMPILER2
3206 use_sve = Matcher::supports_scalable_vector();
3207 if (use_sve) {
3208 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3209 }
3210 #endif
3211
3212 if (!use_sve) {
3213 return 0;
3214 }
3215
3216 unsigned char regs[PRegister::number_of_registers];
3217 int count = 0;
3218 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3219 if (1 & bitset)
3220 regs[count++] = reg;
3221 bitset >>= 1;
3222 }
3223
3224 if (count == 0) {
3225 return 0;
3226 }
3227
3228 int total_push_bytes = align_up(sve_predicate_size_in_slots *
3229 VMRegImpl::stack_slot_size * count, 16);
3230 sub(stack, stack, total_push_bytes);
3231 for (int i = 0; i < count; i++) {
3232 sve_str(as_PRegister(regs[i]), Address(stack, i));
3233 }
3234 return total_push_bytes / 8;
3235 }
3236
3237 // Return the number of dwords popped
3238 int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
3239 bool use_sve = false;
3240 int sve_predicate_size_in_slots = 0;
3241
3242 #ifdef COMPILER2
3243 use_sve = Matcher::supports_scalable_vector();
3244 if (use_sve) {
3245 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3246 }
3247 #endif
3248
3249 if (!use_sve) {
3250 return 0;
3251 }
3252
3253 unsigned char regs[PRegister::number_of_registers];
3254 int count = 0;
3255 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3256 if (1 & bitset)
3257 regs[count++] = reg;
3258 bitset >>= 1;
3259 }
3260
3261 if (count == 0) {
3262 return 0;
3263 }
3264
3265 int total_pop_bytes = align_up(sve_predicate_size_in_slots *
3266 VMRegImpl::stack_slot_size * count, 16);
3267 for (int i = count - 1; i >= 0; i--) {
3268 sve_ldr(as_PRegister(regs[i]), Address(stack, i));
3269 }
3270 add(stack, stack, total_pop_bytes);
3271 return total_pop_bytes / 8;
3272 }
3273
3274 #ifdef ASSERT
3275 void MacroAssembler::verify_heapbase(const char* msg) {
3276 #if 0
3277 assert (Universe::heap() != nullptr, "java heap should be initialized");
3278 if (!UseCompressedOops || Universe::ptr_base() == nullptr) {
3279 // rheapbase is allocated as general register
3280 return;
3281 }
3282 if (CheckCompressedOops) {
3283 Label ok;
3284 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
3285 cmpptr(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3286 br(Assembler::EQ, ok);
3287 stop(msg);
3288 bind(ok);
3289 pop(1 << rscratch1->encoding(), sp);
3290 }
3291 #endif
3292 }
3293 #endif
3294
3295 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
3296 assert_different_registers(value, tmp1, tmp2);
3297 Label done, tagged, weak_tagged;
3298
3299 cbz(value, done); // Use null as-is.
3300 tst(value, JNIHandles::tag_mask); // Test for tag.
3301 br(Assembler::NE, tagged);
3302
3303 // Resolve local handle
3304 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2);
3305 verify_oop(value);
3306 b(done);
3307
3308 bind(tagged);
3309 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1);
3310 tbnz(value, 0, weak_tagged); // Test for weak tag.
3311
3312 // Resolve global handle
3313 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3314 verify_oop(value);
3315 b(done);
3316
3317 bind(weak_tagged);
3318 // Resolve jweak.
3319 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3320 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2);
3321 verify_oop(value);
3322
3323 bind(done);
3324 }
3325
3326 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) {
3327 assert_different_registers(value, tmp1, tmp2);
3328 Label done;
3329
3330 cbz(value, done); // Use null as-is.
3331
3332 #ifdef ASSERT
3333 {
3334 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10);
3335 Label valid_global_tag;
3336 tbnz(value, 1, valid_global_tag); // Test for global tag
3337 stop("non global jobject using resolve_global_jobject");
3338 bind(valid_global_tag);
3339 }
3340 #endif
3341
3342 // Resolve global handle
3343 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3344 verify_oop(value);
3345
3346 bind(done);
3347 }
3348
3349 void MacroAssembler::stop(const char* msg) {
3350 // Skip AOT caching C strings in scratch buffer.
3351 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
3352 BLOCK_COMMENT(str);
3353 // load msg into r0 so we can access it from the signal handler
3354 // ExternalAddress enables saving and restoring via the code cache
3355 lea(c_rarg0, ExternalAddress((address) str));
3356 dcps1(0xdeae);
3357 }
3358
3359 void MacroAssembler::unimplemented(const char* what) {
3360 const char* buf = nullptr;
3361 {
3362 ResourceMark rm;
3363 stringStream ss;
3364 ss.print("unimplemented: %s", what);
3365 buf = code_string(ss.as_string());
3366 }
3367 stop(buf);
3368 }
3369
3370 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
3371 #ifdef ASSERT
3372 Label OK;
3373 br(cc, OK);
3374 stop(msg);
3375 bind(OK);
3376 #endif
3377 }
3378
3379 // If a constant does not fit in an immediate field, generate some
3380 // number of MOV instructions and then perform the operation.
3381 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
3382 add_sub_imm_insn insn1,
3383 add_sub_reg_insn insn2,
3384 bool is32) {
3385 assert(Rd != zr, "Rd = zr and not setting flags?");
3386 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3387 if (fits) {
3388 (this->*insn1)(Rd, Rn, imm);
3389 } else {
3390 if (g_uabs(imm) < (1 << 24)) {
3391 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
3392 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
3393 } else {
3394 assert_different_registers(Rd, Rn);
3395 mov(Rd, imm);
3396 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3397 }
3398 }
3399 }
3400
3401 // Separate vsn which sets the flags. Optimisations are more restricted
3402 // because we must set the flags correctly.
3403 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
3404 add_sub_imm_insn insn1,
3405 add_sub_reg_insn insn2,
3406 bool is32) {
3407 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3408 if (fits) {
3409 (this->*insn1)(Rd, Rn, imm);
3410 } else {
3411 assert_different_registers(Rd, Rn);
3412 assert(Rd != zr, "overflow in immediate operand");
3413 mov(Rd, imm);
3414 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3415 }
3416 }
3417
3418
3419 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
3420 if (increment.is_register()) {
3421 add(Rd, Rn, increment.as_register());
3422 } else {
3423 add(Rd, Rn, increment.as_constant());
3424 }
3425 }
3426
3427 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
3428 if (increment.is_register()) {
3429 addw(Rd, Rn, increment.as_register());
3430 } else {
3431 addw(Rd, Rn, increment.as_constant());
3432 }
3433 }
3434
3435 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
3436 if (decrement.is_register()) {
3437 sub(Rd, Rn, decrement.as_register());
3438 } else {
3439 sub(Rd, Rn, decrement.as_constant());
3440 }
3441 }
3442
3443 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
3444 if (decrement.is_register()) {
3445 subw(Rd, Rn, decrement.as_register());
3446 } else {
3447 subw(Rd, Rn, decrement.as_constant());
3448 }
3449 }
3450
3451 void MacroAssembler::reinit_heapbase()
3452 {
3453 if (UseCompressedOops) {
3454 if (Universe::is_fully_initialized()) {
3455 mov(rheapbase, CompressedOops::base());
3456 } else {
3457 lea(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3458 ldr(rheapbase, Address(rheapbase));
3459 }
3460 }
3461 }
3462
3463 // A generic CAS; success or failure is in the EQ flag. A weak CAS
3464 // doesn't retry and may fail spuriously. If the oldval is wanted,
3465 // Pass a register for the result, otherwise pass noreg.
3466
3467 // Clobbers rscratch1
3468 void MacroAssembler::cmpxchg(Register addr, Register expected,
3469 Register new_val,
3470 enum operand_size size,
3471 bool acquire, bool release,
3472 bool weak,
3473 Register result) {
3474 if (result == noreg) result = rscratch1;
3475 BLOCK_COMMENT("cmpxchg {");
3476 if (UseLSE) {
3477 mov(result, expected);
3478 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
3479 compare_eq(result, expected, size);
3480 #ifdef ASSERT
3481 // Poison rscratch1 which is written on !UseLSE branch
3482 mov(rscratch1, 0x1f1f1f1f1f1f1f1f);
3483 #endif
3484 } else {
3485 Label retry_load, done;
3486 prfm(Address(addr), PSTL1STRM);
3487 bind(retry_load);
3488 load_exclusive(result, addr, size, acquire);
3489 compare_eq(result, expected, size);
3490 br(Assembler::NE, done);
3491 store_exclusive(rscratch1, new_val, addr, size, release);
3492 if (weak) {
3493 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
3494 } else {
3495 cbnzw(rscratch1, retry_load);
3496 }
3497 bind(done);
3498 }
3499 BLOCK_COMMENT("} cmpxchg");
3500 }
3501
3502 // A generic comparison. Only compares for equality, clobbers rscratch1.
3503 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
3504 if (size == xword) {
3505 cmp(rm, rn);
3506 } else if (size == word) {
3507 cmpw(rm, rn);
3508 } else if (size == halfword) {
3509 eorw(rscratch1, rm, rn);
3510 ands(zr, rscratch1, 0xffff);
3511 } else if (size == byte) {
3512 eorw(rscratch1, rm, rn);
3513 ands(zr, rscratch1, 0xff);
3514 } else {
3515 ShouldNotReachHere();
3516 }
3517 }
3518
3519
3520 static bool different(Register a, RegisterOrConstant b, Register c) {
3521 if (b.is_constant())
3522 return a != c;
3523 else
3524 return a != b.as_register() && a != c && b.as_register() != c;
3525 }
3526
3527 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
3528 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
3529 if (UseLSE) { \
3530 prev = prev->is_valid() ? prev : zr; \
3531 if (incr.is_register()) { \
3532 AOP(sz, incr.as_register(), prev, addr); \
3533 } else { \
3534 mov(rscratch2, incr.as_constant()); \
3535 AOP(sz, rscratch2, prev, addr); \
3536 } \
3537 return; \
3538 } \
3539 Register result = rscratch2; \
3540 if (prev->is_valid()) \
3541 result = different(prev, incr, addr) ? prev : rscratch2; \
3542 \
3543 Label retry_load; \
3544 prfm(Address(addr), PSTL1STRM); \
3545 bind(retry_load); \
3546 LDXR(result, addr); \
3547 OP(rscratch1, result, incr); \
3548 STXR(rscratch2, rscratch1, addr); \
3549 cbnzw(rscratch2, retry_load); \
3550 if (prev->is_valid() && prev != result) { \
3551 IOP(prev, rscratch1, incr); \
3552 } \
3553 }
3554
3555 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
3556 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
3557 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
3558 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
3559
3560 #undef ATOMIC_OP
3561
3562 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
3563 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
3564 if (UseLSE) { \
3565 prev = prev->is_valid() ? prev : zr; \
3566 AOP(sz, newv, prev, addr); \
3567 return; \
3568 } \
3569 Register result = rscratch2; \
3570 if (prev->is_valid()) \
3571 result = different(prev, newv, addr) ? prev : rscratch2; \
3572 \
3573 Label retry_load; \
3574 prfm(Address(addr), PSTL1STRM); \
3575 bind(retry_load); \
3576 LDXR(result, addr); \
3577 STXR(rscratch1, newv, addr); \
3578 cbnzw(rscratch1, retry_load); \
3579 if (prev->is_valid() && prev != result) \
3580 mov(prev, result); \
3581 }
3582
3583 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
3584 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
3585 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
3586 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
3587 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
3588 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
3589
3590 #undef ATOMIC_XCHG
3591
3592 #ifndef PRODUCT
3593 extern "C" void findpc(intptr_t x);
3594 #endif
3595
3596 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
3597 {
3598 // In order to get locks to work, we need to fake a in_VM state
3599 if (ShowMessageBoxOnError) {
3600 JavaThread* thread = JavaThread::current();
3601 thread->set_thread_state(_thread_in_vm);
3602 #ifndef PRODUCT
3603 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
3604 ttyLocker ttyl;
3605 BytecodeCounter::print();
3606 }
3607 #endif
3608 if (os::message_box(msg, "Execution stopped, print registers?")) {
3609 ttyLocker ttyl;
3610 tty->print_cr(" pc = 0x%016" PRIx64, pc);
3611 #ifndef PRODUCT
3612 tty->cr();
3613 findpc(pc);
3614 tty->cr();
3615 #endif
3616 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
3617 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
3618 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
3619 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
3620 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
3621 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
3622 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
3623 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
3624 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
3625 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
3626 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
3627 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
3628 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
3629 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
3630 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
3631 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
3632 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
3633 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
3634 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
3635 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
3636 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
3637 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
3638 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
3639 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
3640 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
3641 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
3642 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
3643 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
3644 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
3645 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
3646 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
3647 BREAKPOINT;
3648 }
3649 }
3650 fatal("DEBUG MESSAGE: %s", msg);
3651 }
3652
3653 RegSet MacroAssembler::call_clobbered_gp_registers() {
3654 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
3655 #ifndef R18_RESERVED
3656 regs += r18_tls;
3657 #endif
3658 return regs;
3659 }
3660
3661 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
3662 int step = 4 * wordSize;
3663 push(call_clobbered_gp_registers() - exclude, sp);
3664 sub(sp, sp, step);
3665 mov(rscratch1, -step);
3666 // Push v0-v7, v16-v31.
3667 for (int i = 31; i>= 4; i -= 4) {
3668 if (i <= v7->encoding() || i >= v16->encoding())
3669 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
3670 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
3671 }
3672 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
3673 as_FloatRegister(3), T1D, Address(sp));
3674 }
3675
3676 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
3677 for (int i = 0; i < 32; i += 4) {
3678 if (i <= v7->encoding() || i >= v16->encoding())
3679 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3680 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
3681 }
3682
3683 reinitialize_ptrue();
3684
3685 pop(call_clobbered_gp_registers() - exclude, sp);
3686 }
3687
3688 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
3689 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3690 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
3691 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3692 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3693 for (int i = 0; i < FloatRegister::number_of_registers; i++) {
3694 sve_str(as_FloatRegister(i), Address(sp, i));
3695 }
3696 } else {
3697 int step = (save_vectors ? 8 : 4) * wordSize;
3698 mov(rscratch1, -step);
3699 sub(sp, sp, step);
3700 for (int i = 28; i >= 4; i -= 4) {
3701 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3702 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
3703 }
3704 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
3705 }
3706 if (save_vectors && use_sve && total_predicate_in_bytes > 0) {
3707 sub(sp, sp, total_predicate_in_bytes);
3708 for (int i = 0; i < PRegister::number_of_registers; i++) {
3709 sve_str(as_PRegister(i), Address(sp, i));
3710 }
3711 }
3712 }
3713
3714 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
3715 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3716 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) {
3717 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) {
3718 sve_ldr(as_PRegister(i), Address(sp, i));
3719 }
3720 add(sp, sp, total_predicate_in_bytes);
3721 }
3722 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3723 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) {
3724 sve_ldr(as_FloatRegister(i), Address(sp, i));
3725 }
3726 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3727 } else {
3728 int step = (restore_vectors ? 8 : 4) * wordSize;
3729 for (int i = 0; i <= 28; i += 4)
3730 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3731 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
3732 }
3733
3734 // We may use predicate registers and rely on ptrue with SVE,
3735 // regardless of wide vector (> 8 bytes) used or not.
3736 if (use_sve) {
3737 reinitialize_ptrue();
3738 }
3739
3740 // integer registers except lr & sp
3741 pop(RegSet::range(r0, r17), sp);
3742 #ifdef R18_RESERVED
3743 ldp(zr, r19, Address(post(sp, 2 * wordSize)));
3744 pop(RegSet::range(r20, r29), sp);
3745 #else
3746 pop(RegSet::range(r18_tls, r29), sp);
3747 #endif
3748 }
3749
3750 /**
3751 * Helpers for multiply_to_len().
3752 */
3753 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
3754 Register src1, Register src2) {
3755 adds(dest_lo, dest_lo, src1);
3756 adc(dest_hi, dest_hi, zr);
3757 adds(dest_lo, dest_lo, src2);
3758 adc(final_dest_hi, dest_hi, zr);
3759 }
3760
3761 // Generate an address from (r + r1 extend offset). "size" is the
3762 // size of the operand. The result may be in rscratch2.
3763 Address MacroAssembler::offsetted_address(Register r, Register r1,
3764 Address::extend ext, int offset, int size) {
3765 if (offset || (ext.shift() % size != 0)) {
3766 lea(rscratch2, Address(r, r1, ext));
3767 return Address(rscratch2, offset);
3768 } else {
3769 return Address(r, r1, ext);
3770 }
3771 }
3772
3773 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
3774 {
3775 assert(offset >= 0, "spill to negative address?");
3776 // Offset reachable ?
3777 // Not aligned - 9 bits signed offset
3778 // Aligned - 12 bits unsigned offset shifted
3779 Register base = sp;
3780 if ((offset & (size-1)) && offset >= (1<<8)) {
3781 add(tmp, base, offset & ((1<<12)-1));
3782 base = tmp;
3783 offset &= -1u<<12;
3784 }
3785
3786 if (offset >= (1<<12) * size) {
3787 add(tmp, base, offset & (((1<<12)-1)<<12));
3788 base = tmp;
3789 offset &= ~(((1<<12)-1)<<12);
3790 }
3791
3792 return Address(base, offset);
3793 }
3794
3795 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) {
3796 assert(offset >= 0, "spill to negative address?");
3797
3798 Register base = sp;
3799
3800 // An immediate offset in the range 0 to 255 which is multiplied
3801 // by the current vector or predicate register size in bytes.
3802 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) {
3803 return Address(base, offset / sve_reg_size_in_bytes);
3804 }
3805
3806 add(tmp, base, offset);
3807 return Address(tmp);
3808 }
3809
3810 // Checks whether offset is aligned.
3811 // Returns true if it is, else false.
3812 bool MacroAssembler::merge_alignment_check(Register base,
3813 size_t size,
3814 int64_t cur_offset,
3815 int64_t prev_offset) const {
3816 if (AvoidUnalignedAccesses) {
3817 if (base == sp) {
3818 // Checks whether low offset if aligned to pair of registers.
3819 int64_t pair_mask = size * 2 - 1;
3820 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3821 return (offset & pair_mask) == 0;
3822 } else { // If base is not sp, we can't guarantee the access is aligned.
3823 return false;
3824 }
3825 } else {
3826 int64_t mask = size - 1;
3827 // Load/store pair instruction only supports element size aligned offset.
3828 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
3829 }
3830 }
3831
3832 // Checks whether current and previous loads/stores can be merged.
3833 // Returns true if it can be merged, else false.
3834 bool MacroAssembler::ldst_can_merge(Register rt,
3835 const Address &adr,
3836 size_t cur_size_in_bytes,
3837 bool is_store) const {
3838 address prev = pc() - NativeInstruction::instruction_size;
3839 address last = code()->last_insn();
3840
3841 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) {
3842 return false;
3843 }
3844
3845 if (adr.getMode() != Address::base_plus_offset || prev != last) {
3846 return false;
3847 }
3848
3849 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3850 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
3851
3852 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
3853 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
3854
3855 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
3856 return false;
3857 }
3858
3859 int64_t max_offset = 63 * prev_size_in_bytes;
3860 int64_t min_offset = -64 * prev_size_in_bytes;
3861
3862 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
3863
3864 // Only same base can be merged.
3865 if (adr.base() != prev_ldst->base()) {
3866 return false;
3867 }
3868
3869 int64_t cur_offset = adr.offset();
3870 int64_t prev_offset = prev_ldst->offset();
3871 size_t diff = abs(cur_offset - prev_offset);
3872 if (diff != prev_size_in_bytes) {
3873 return false;
3874 }
3875
3876 // Following cases can not be merged:
3877 // ldr x2, [x2, #8]
3878 // ldr x3, [x2, #16]
3879 // or:
3880 // ldr x2, [x3, #8]
3881 // ldr x2, [x3, #16]
3882 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
3883 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
3884 return false;
3885 }
3886
3887 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3888 // Offset range must be in ldp/stp instruction's range.
3889 if (low_offset > max_offset || low_offset < min_offset) {
3890 return false;
3891 }
3892
3893 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
3894 return true;
3895 }
3896
3897 return false;
3898 }
3899
3900 // Merge current load/store with previous load/store into ldp/stp.
3901 void MacroAssembler::merge_ldst(Register rt,
3902 const Address &adr,
3903 size_t cur_size_in_bytes,
3904 bool is_store) {
3905
3906 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
3907
3908 Register rt_low, rt_high;
3909 address prev = pc() - NativeInstruction::instruction_size;
3910 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3911
3912 int64_t offset;
3913
3914 if (adr.offset() < prev_ldst->offset()) {
3915 offset = adr.offset();
3916 rt_low = rt;
3917 rt_high = prev_ldst->target();
3918 } else {
3919 offset = prev_ldst->offset();
3920 rt_low = prev_ldst->target();
3921 rt_high = rt;
3922 }
3923
3924 Address adr_p = Address(prev_ldst->base(), offset);
3925 // Overwrite previous generated binary.
3926 code_section()->set_end(prev);
3927
3928 const size_t sz = prev_ldst->size_in_bytes();
3929 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
3930 if (!is_store) {
3931 BLOCK_COMMENT("merged ldr pair");
3932 if (sz == 8) {
3933 ldp(rt_low, rt_high, adr_p);
3934 } else {
3935 ldpw(rt_low, rt_high, adr_p);
3936 }
3937 } else {
3938 BLOCK_COMMENT("merged str pair");
3939 if (sz == 8) {
3940 stp(rt_low, rt_high, adr_p);
3941 } else {
3942 stpw(rt_low, rt_high, adr_p);
3943 }
3944 }
3945 }
3946
3947 /**
3948 * Multiply 64 bit by 64 bit first loop.
3949 */
3950 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
3951 Register y, Register y_idx, Register z,
3952 Register carry, Register product,
3953 Register idx, Register kdx) {
3954 //
3955 // jlong carry, x[], y[], z[];
3956 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3957 // huge_128 product = y[idx] * x[xstart] + carry;
3958 // z[kdx] = (jlong)product;
3959 // carry = (jlong)(product >>> 64);
3960 // }
3961 // z[xstart] = carry;
3962 //
3963
3964 Label L_first_loop, L_first_loop_exit;
3965 Label L_one_x, L_one_y, L_multiply;
3966
3967 subsw(xstart, xstart, 1);
3968 br(Assembler::MI, L_one_x);
3969
3970 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
3971 ldr(x_xstart, Address(rscratch1));
3972 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
3973
3974 bind(L_first_loop);
3975 subsw(idx, idx, 1);
3976 br(Assembler::MI, L_first_loop_exit);
3977 subsw(idx, idx, 1);
3978 br(Assembler::MI, L_one_y);
3979 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3980 ldr(y_idx, Address(rscratch1));
3981 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
3982 bind(L_multiply);
3983
3984 // AArch64 has a multiply-accumulate instruction that we can't use
3985 // here because it has no way to process carries, so we have to use
3986 // separate add and adc instructions. Bah.
3987 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
3988 mul(product, x_xstart, y_idx);
3989 adds(product, product, carry);
3990 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
3991
3992 subw(kdx, kdx, 2);
3993 ror(product, product, 32); // back to big-endian
3994 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
3995
3996 b(L_first_loop);
3997
3998 bind(L_one_y);
3999 ldrw(y_idx, Address(y, 0));
4000 b(L_multiply);
4001
4002 bind(L_one_x);
4003 ldrw(x_xstart, Address(x, 0));
4004 b(L_first_loop);
4005
4006 bind(L_first_loop_exit);
4007 }
4008
4009 /**
4010 * Multiply 128 bit by 128. Unrolled inner loop.
4011 *
4012 */
4013 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
4014 Register carry, Register carry2,
4015 Register idx, Register jdx,
4016 Register yz_idx1, Register yz_idx2,
4017 Register tmp, Register tmp3, Register tmp4,
4018 Register tmp6, Register product_hi) {
4019
4020 // jlong carry, x[], y[], z[];
4021 // int kdx = ystart+1;
4022 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
4023 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
4024 // jlong carry2 = (jlong)(tmp3 >>> 64);
4025 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
4026 // carry = (jlong)(tmp4 >>> 64);
4027 // z[kdx+idx+1] = (jlong)tmp3;
4028 // z[kdx+idx] = (jlong)tmp4;
4029 // }
4030 // idx += 2;
4031 // if (idx > 0) {
4032 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
4033 // z[kdx+idx] = (jlong)yz_idx1;
4034 // carry = (jlong)(yz_idx1 >>> 64);
4035 // }
4036 //
4037
4038 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
4039
4040 lsrw(jdx, idx, 2);
4041
4042 bind(L_third_loop);
4043
4044 subsw(jdx, jdx, 1);
4045 br(Assembler::MI, L_third_loop_exit);
4046 subw(idx, idx, 4);
4047
4048 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4049
4050 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
4051
4052 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4053
4054 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
4055 ror(yz_idx2, yz_idx2, 32);
4056
4057 ldp(rscratch2, rscratch1, Address(tmp6, 0));
4058
4059 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4060 umulh(tmp4, product_hi, yz_idx1);
4061
4062 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
4063 ror(rscratch2, rscratch2, 32);
4064
4065 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
4066 umulh(carry2, product_hi, yz_idx2);
4067
4068 // propagate sum of both multiplications into carry:tmp4:tmp3
4069 adds(tmp3, tmp3, carry);
4070 adc(tmp4, tmp4, zr);
4071 adds(tmp3, tmp3, rscratch1);
4072 adcs(tmp4, tmp4, tmp);
4073 adc(carry, carry2, zr);
4074 adds(tmp4, tmp4, rscratch2);
4075 adc(carry, carry, zr);
4076
4077 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
4078 ror(tmp4, tmp4, 32);
4079 stp(tmp4, tmp3, Address(tmp6, 0));
4080
4081 b(L_third_loop);
4082 bind (L_third_loop_exit);
4083
4084 andw (idx, idx, 0x3);
4085 cbz(idx, L_post_third_loop_done);
4086
4087 Label L_check_1;
4088 subsw(idx, idx, 2);
4089 br(Assembler::MI, L_check_1);
4090
4091 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4092 ldr(yz_idx1, Address(rscratch1, 0));
4093 ror(yz_idx1, yz_idx1, 32);
4094 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4095 umulh(tmp4, product_hi, yz_idx1);
4096 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4097 ldr(yz_idx2, Address(rscratch1, 0));
4098 ror(yz_idx2, yz_idx2, 32);
4099
4100 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
4101
4102 ror(tmp3, tmp3, 32);
4103 str(tmp3, Address(rscratch1, 0));
4104
4105 bind (L_check_1);
4106
4107 andw (idx, idx, 0x1);
4108 subsw(idx, idx, 1);
4109 br(Assembler::MI, L_post_third_loop_done);
4110 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4111 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
4112 umulh(carry2, tmp4, product_hi);
4113 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4114
4115 add2_with_carry(carry2, tmp3, tmp4, carry);
4116
4117 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4118 extr(carry, carry2, tmp3, 32);
4119
4120 bind(L_post_third_loop_done);
4121 }
4122
4123 /**
4124 * Code for BigInteger::multiplyToLen() intrinsic.
4125 *
4126 * r0: x
4127 * r1: xlen
4128 * r2: y
4129 * r3: ylen
4130 * r4: z
4131 * r5: tmp0
4132 * r10: tmp1
4133 * r11: tmp2
4134 * r12: tmp3
4135 * r13: tmp4
4136 * r14: tmp5
4137 * r15: tmp6
4138 * r16: tmp7
4139 *
4140 */
4141 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
4142 Register z, Register tmp0,
4143 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
4144 Register tmp5, Register tmp6, Register product_hi) {
4145
4146 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, product_hi);
4147
4148 const Register idx = tmp1;
4149 const Register kdx = tmp2;
4150 const Register xstart = tmp3;
4151
4152 const Register y_idx = tmp4;
4153 const Register carry = tmp5;
4154 const Register product = xlen;
4155 const Register x_xstart = tmp0;
4156
4157 // First Loop.
4158 //
4159 // final static long LONG_MASK = 0xffffffffL;
4160 // int xstart = xlen - 1;
4161 // int ystart = ylen - 1;
4162 // long carry = 0;
4163 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4164 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
4165 // z[kdx] = (int)product;
4166 // carry = product >>> 32;
4167 // }
4168 // z[xstart] = (int)carry;
4169 //
4170
4171 movw(idx, ylen); // idx = ylen;
4172 addw(kdx, xlen, ylen); // kdx = xlen+ylen;
4173 mov(carry, zr); // carry = 0;
4174
4175 Label L_done;
4176
4177 movw(xstart, xlen);
4178 subsw(xstart, xstart, 1);
4179 br(Assembler::MI, L_done);
4180
4181 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
4182
4183 Label L_second_loop;
4184 cbzw(kdx, L_second_loop);
4185
4186 Label L_carry;
4187 subw(kdx, kdx, 1);
4188 cbzw(kdx, L_carry);
4189
4190 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4191 lsr(carry, carry, 32);
4192 subw(kdx, kdx, 1);
4193
4194 bind(L_carry);
4195 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4196
4197 // Second and third (nested) loops.
4198 //
4199 // for (int i = xstart-1; i >= 0; i--) { // Second loop
4200 // carry = 0;
4201 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
4202 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
4203 // (z[k] & LONG_MASK) + carry;
4204 // z[k] = (int)product;
4205 // carry = product >>> 32;
4206 // }
4207 // z[i] = (int)carry;
4208 // }
4209 //
4210 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
4211
4212 const Register jdx = tmp1;
4213
4214 bind(L_second_loop);
4215 mov(carry, zr); // carry = 0;
4216 movw(jdx, ylen); // j = ystart+1
4217
4218 subsw(xstart, xstart, 1); // i = xstart-1;
4219 br(Assembler::MI, L_done);
4220
4221 str(z, Address(pre(sp, -4 * wordSize)));
4222
4223 Label L_last_x;
4224 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
4225 subsw(xstart, xstart, 1); // i = xstart-1;
4226 br(Assembler::MI, L_last_x);
4227
4228 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
4229 ldr(product_hi, Address(rscratch1));
4230 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
4231
4232 Label L_third_loop_prologue;
4233 bind(L_third_loop_prologue);
4234
4235 str(ylen, Address(sp, wordSize));
4236 stp(x, xstart, Address(sp, 2 * wordSize));
4237 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
4238 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
4239 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
4240 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
4241
4242 addw(tmp3, xlen, 1);
4243 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4244 subsw(tmp3, tmp3, 1);
4245 br(Assembler::MI, L_done);
4246
4247 lsr(carry, carry, 32);
4248 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4249 b(L_second_loop);
4250
4251 // Next infrequent code is moved outside loops.
4252 bind(L_last_x);
4253 ldrw(product_hi, Address(x, 0));
4254 b(L_third_loop_prologue);
4255
4256 bind(L_done);
4257 }
4258
4259 // Code for BigInteger::mulAdd intrinsic
4260 // out = r0
4261 // in = r1
4262 // offset = r2 (already out.length-offset)
4263 // len = r3
4264 // k = r4
4265 //
4266 // pseudo code from java implementation:
4267 // carry = 0;
4268 // offset = out.length-offset - 1;
4269 // for (int j=len-1; j >= 0; j--) {
4270 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
4271 // out[offset--] = (int)product;
4272 // carry = product >>> 32;
4273 // }
4274 // return (int)carry;
4275 void MacroAssembler::mul_add(Register out, Register in, Register offset,
4276 Register len, Register k) {
4277 Label LOOP, END;
4278 // pre-loop
4279 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
4280 csel(out, zr, out, Assembler::EQ);
4281 br(Assembler::EQ, END);
4282 add(in, in, len, LSL, 2); // in[j+1] address
4283 add(offset, out, offset, LSL, 2); // out[offset + 1] address
4284 mov(out, zr); // used to keep carry now
4285 BIND(LOOP);
4286 ldrw(rscratch1, Address(pre(in, -4)));
4287 madd(rscratch1, rscratch1, k, out);
4288 ldrw(rscratch2, Address(pre(offset, -4)));
4289 add(rscratch1, rscratch1, rscratch2);
4290 strw(rscratch1, Address(offset));
4291 lsr(out, rscratch1, 32);
4292 subs(len, len, 1);
4293 br(Assembler::NE, LOOP);
4294 BIND(END);
4295 }
4296
4297 /**
4298 * Emits code to update CRC-32 with a byte value according to constants in table
4299 *
4300 * @param [in,out]crc Register containing the crc.
4301 * @param [in]val Register containing the byte to fold into the CRC.
4302 * @param [in]table Register containing the table of crc constants.
4303 *
4304 * uint32_t crc;
4305 * val = crc_table[(val ^ crc) & 0xFF];
4306 * crc = val ^ (crc >> 8);
4307 *
4308 */
4309 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4310 eor(val, val, crc);
4311 andr(val, val, 0xff);
4312 ldrw(val, Address(table, val, Address::lsl(2)));
4313 eor(crc, val, crc, Assembler::LSR, 8);
4314 }
4315
4316 /**
4317 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
4318 *
4319 * @param [in,out]crc Register containing the crc.
4320 * @param [in]v Register containing the 32-bit to fold into the CRC.
4321 * @param [in]table0 Register containing table 0 of crc constants.
4322 * @param [in]table1 Register containing table 1 of crc constants.
4323 * @param [in]table2 Register containing table 2 of crc constants.
4324 * @param [in]table3 Register containing table 3 of crc constants.
4325 *
4326 * uint32_t crc;
4327 * v = crc ^ v
4328 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
4329 *
4330 */
4331 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
4332 Register table0, Register table1, Register table2, Register table3,
4333 bool upper) {
4334 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
4335 uxtb(tmp, v);
4336 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
4337 ubfx(tmp, v, 8, 8);
4338 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
4339 eor(crc, crc, tmp);
4340 ubfx(tmp, v, 16, 8);
4341 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
4342 eor(crc, crc, tmp);
4343 ubfx(tmp, v, 24, 8);
4344 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
4345 eor(crc, crc, tmp);
4346 }
4347
4348 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf,
4349 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4350 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4351 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4352
4353 subs(tmp0, len, 384);
4354 mvnw(crc, crc);
4355 br(Assembler::GE, CRC_by128_pre);
4356 BIND(CRC_less128);
4357 subs(len, len, 32);
4358 br(Assembler::GE, CRC_by32_loop);
4359 BIND(CRC_less32);
4360 adds(len, len, 32 - 4);
4361 br(Assembler::GE, CRC_by4_loop);
4362 adds(len, len, 4);
4363 br(Assembler::GT, CRC_by1_loop);
4364 b(L_exit);
4365
4366 BIND(CRC_by32_loop);
4367 ldp(tmp0, tmp1, Address(buf));
4368 crc32x(crc, crc, tmp0);
4369 ldp(tmp2, tmp3, Address(buf, 16));
4370 crc32x(crc, crc, tmp1);
4371 add(buf, buf, 32);
4372 crc32x(crc, crc, tmp2);
4373 subs(len, len, 32);
4374 crc32x(crc, crc, tmp3);
4375 br(Assembler::GE, CRC_by32_loop);
4376 cmn(len, (u1)32);
4377 br(Assembler::NE, CRC_less32);
4378 b(L_exit);
4379
4380 BIND(CRC_by4_loop);
4381 ldrw(tmp0, Address(post(buf, 4)));
4382 subs(len, len, 4);
4383 crc32w(crc, crc, tmp0);
4384 br(Assembler::GE, CRC_by4_loop);
4385 adds(len, len, 4);
4386 br(Assembler::LE, L_exit);
4387 BIND(CRC_by1_loop);
4388 ldrb(tmp0, Address(post(buf, 1)));
4389 subs(len, len, 1);
4390 crc32b(crc, crc, tmp0);
4391 br(Assembler::GT, CRC_by1_loop);
4392 b(L_exit);
4393
4394 BIND(CRC_by128_pre);
4395 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4396 4*256*sizeof(juint) + 8*sizeof(juint));
4397 mov(crc, 0);
4398 crc32x(crc, crc, tmp0);
4399 crc32x(crc, crc, tmp1);
4400
4401 cbnz(len, CRC_less128);
4402
4403 BIND(L_exit);
4404 mvnw(crc, crc);
4405 }
4406
4407 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
4408 Register len, Register tmp0, Register tmp1, Register tmp2,
4409 Register tmp3) {
4410 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4411 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4412
4413 mvnw(crc, crc);
4414
4415 subs(len, len, 128);
4416 br(Assembler::GE, CRC_by64_pre);
4417 BIND(CRC_less64);
4418 adds(len, len, 128-32);
4419 br(Assembler::GE, CRC_by32_loop);
4420 BIND(CRC_less32);
4421 adds(len, len, 32-4);
4422 br(Assembler::GE, CRC_by4_loop);
4423 adds(len, len, 4);
4424 br(Assembler::GT, CRC_by1_loop);
4425 b(L_exit);
4426
4427 BIND(CRC_by32_loop);
4428 ldp(tmp0, tmp1, Address(post(buf, 16)));
4429 subs(len, len, 32);
4430 crc32x(crc, crc, tmp0);
4431 ldr(tmp2, Address(post(buf, 8)));
4432 crc32x(crc, crc, tmp1);
4433 ldr(tmp3, Address(post(buf, 8)));
4434 crc32x(crc, crc, tmp2);
4435 crc32x(crc, crc, tmp3);
4436 br(Assembler::GE, CRC_by32_loop);
4437 cmn(len, (u1)32);
4438 br(Assembler::NE, CRC_less32);
4439 b(L_exit);
4440
4441 BIND(CRC_by4_loop);
4442 ldrw(tmp0, Address(post(buf, 4)));
4443 subs(len, len, 4);
4444 crc32w(crc, crc, tmp0);
4445 br(Assembler::GE, CRC_by4_loop);
4446 adds(len, len, 4);
4447 br(Assembler::LE, L_exit);
4448 BIND(CRC_by1_loop);
4449 ldrb(tmp0, Address(post(buf, 1)));
4450 subs(len, len, 1);
4451 crc32b(crc, crc, tmp0);
4452 br(Assembler::GT, CRC_by1_loop);
4453 b(L_exit);
4454
4455 BIND(CRC_by64_pre);
4456 sub(buf, buf, 8);
4457 ldp(tmp0, tmp1, Address(buf, 8));
4458 crc32x(crc, crc, tmp0);
4459 ldr(tmp2, Address(buf, 24));
4460 crc32x(crc, crc, tmp1);
4461 ldr(tmp3, Address(buf, 32));
4462 crc32x(crc, crc, tmp2);
4463 ldr(tmp0, Address(buf, 40));
4464 crc32x(crc, crc, tmp3);
4465 ldr(tmp1, Address(buf, 48));
4466 crc32x(crc, crc, tmp0);
4467 ldr(tmp2, Address(buf, 56));
4468 crc32x(crc, crc, tmp1);
4469 ldr(tmp3, Address(pre(buf, 64)));
4470
4471 b(CRC_by64_loop);
4472
4473 align(CodeEntryAlignment);
4474 BIND(CRC_by64_loop);
4475 subs(len, len, 64);
4476 crc32x(crc, crc, tmp2);
4477 ldr(tmp0, Address(buf, 8));
4478 crc32x(crc, crc, tmp3);
4479 ldr(tmp1, Address(buf, 16));
4480 crc32x(crc, crc, tmp0);
4481 ldr(tmp2, Address(buf, 24));
4482 crc32x(crc, crc, tmp1);
4483 ldr(tmp3, Address(buf, 32));
4484 crc32x(crc, crc, tmp2);
4485 ldr(tmp0, Address(buf, 40));
4486 crc32x(crc, crc, tmp3);
4487 ldr(tmp1, Address(buf, 48));
4488 crc32x(crc, crc, tmp0);
4489 ldr(tmp2, Address(buf, 56));
4490 crc32x(crc, crc, tmp1);
4491 ldr(tmp3, Address(pre(buf, 64)));
4492 br(Assembler::GE, CRC_by64_loop);
4493
4494 // post-loop
4495 crc32x(crc, crc, tmp2);
4496 crc32x(crc, crc, tmp3);
4497
4498 sub(len, len, 64);
4499 add(buf, buf, 8);
4500 cmn(len, (u1)128);
4501 br(Assembler::NE, CRC_less64);
4502 BIND(L_exit);
4503 mvnw(crc, crc);
4504 }
4505
4506 /**
4507 * @param crc register containing existing CRC (32-bit)
4508 * @param buf register pointing to input byte buffer (byte*)
4509 * @param len register containing number of bytes
4510 * @param table register that will contain address of CRC table
4511 * @param tmp scratch register
4512 */
4513 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
4514 Register table0, Register table1, Register table2, Register table3,
4515 Register tmp, Register tmp2, Register tmp3) {
4516 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
4517
4518 if (UseCryptoPmullForCRC32) {
4519 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4520 return;
4521 }
4522
4523 if (UseCRC32) {
4524 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
4525 return;
4526 }
4527
4528 mvnw(crc, crc);
4529
4530 {
4531 uint64_t offset;
4532 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4533 add(table0, table0, offset);
4534 }
4535 add(table1, table0, 1*256*sizeof(juint));
4536 add(table2, table0, 2*256*sizeof(juint));
4537 add(table3, table0, 3*256*sizeof(juint));
4538
4539 { // Neon code start
4540 cmp(len, (u1)64);
4541 br(Assembler::LT, L_by16);
4542 eor(v16, T16B, v16, v16);
4543
4544 Label L_fold;
4545
4546 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
4547
4548 ld1(v0, v1, T2D, post(buf, 32));
4549 ld1r(v4, T2D, post(tmp, 8));
4550 ld1r(v5, T2D, post(tmp, 8));
4551 ld1r(v6, T2D, post(tmp, 8));
4552 ld1r(v7, T2D, post(tmp, 8));
4553 mov(v16, S, 0, crc);
4554
4555 eor(v0, T16B, v0, v16);
4556 sub(len, len, 64);
4557
4558 BIND(L_fold);
4559 pmull(v22, T8H, v0, v5, T8B);
4560 pmull(v20, T8H, v0, v7, T8B);
4561 pmull(v23, T8H, v0, v4, T8B);
4562 pmull(v21, T8H, v0, v6, T8B);
4563
4564 pmull2(v18, T8H, v0, v5, T16B);
4565 pmull2(v16, T8H, v0, v7, T16B);
4566 pmull2(v19, T8H, v0, v4, T16B);
4567 pmull2(v17, T8H, v0, v6, T16B);
4568
4569 uzp1(v24, T8H, v20, v22);
4570 uzp2(v25, T8H, v20, v22);
4571 eor(v20, T16B, v24, v25);
4572
4573 uzp1(v26, T8H, v16, v18);
4574 uzp2(v27, T8H, v16, v18);
4575 eor(v16, T16B, v26, v27);
4576
4577 ushll2(v22, T4S, v20, T8H, 8);
4578 ushll(v20, T4S, v20, T4H, 8);
4579
4580 ushll2(v18, T4S, v16, T8H, 8);
4581 ushll(v16, T4S, v16, T4H, 8);
4582
4583 eor(v22, T16B, v23, v22);
4584 eor(v18, T16B, v19, v18);
4585 eor(v20, T16B, v21, v20);
4586 eor(v16, T16B, v17, v16);
4587
4588 uzp1(v17, T2D, v16, v20);
4589 uzp2(v21, T2D, v16, v20);
4590 eor(v17, T16B, v17, v21);
4591
4592 ushll2(v20, T2D, v17, T4S, 16);
4593 ushll(v16, T2D, v17, T2S, 16);
4594
4595 eor(v20, T16B, v20, v22);
4596 eor(v16, T16B, v16, v18);
4597
4598 uzp1(v17, T2D, v20, v16);
4599 uzp2(v21, T2D, v20, v16);
4600 eor(v28, T16B, v17, v21);
4601
4602 pmull(v22, T8H, v1, v5, T8B);
4603 pmull(v20, T8H, v1, v7, T8B);
4604 pmull(v23, T8H, v1, v4, T8B);
4605 pmull(v21, T8H, v1, v6, T8B);
4606
4607 pmull2(v18, T8H, v1, v5, T16B);
4608 pmull2(v16, T8H, v1, v7, T16B);
4609 pmull2(v19, T8H, v1, v4, T16B);
4610 pmull2(v17, T8H, v1, v6, T16B);
4611
4612 ld1(v0, v1, T2D, post(buf, 32));
4613
4614 uzp1(v24, T8H, v20, v22);
4615 uzp2(v25, T8H, v20, v22);
4616 eor(v20, T16B, v24, v25);
4617
4618 uzp1(v26, T8H, v16, v18);
4619 uzp2(v27, T8H, v16, v18);
4620 eor(v16, T16B, v26, v27);
4621
4622 ushll2(v22, T4S, v20, T8H, 8);
4623 ushll(v20, T4S, v20, T4H, 8);
4624
4625 ushll2(v18, T4S, v16, T8H, 8);
4626 ushll(v16, T4S, v16, T4H, 8);
4627
4628 eor(v22, T16B, v23, v22);
4629 eor(v18, T16B, v19, v18);
4630 eor(v20, T16B, v21, v20);
4631 eor(v16, T16B, v17, v16);
4632
4633 uzp1(v17, T2D, v16, v20);
4634 uzp2(v21, T2D, v16, v20);
4635 eor(v16, T16B, v17, v21);
4636
4637 ushll2(v20, T2D, v16, T4S, 16);
4638 ushll(v16, T2D, v16, T2S, 16);
4639
4640 eor(v20, T16B, v22, v20);
4641 eor(v16, T16B, v16, v18);
4642
4643 uzp1(v17, T2D, v20, v16);
4644 uzp2(v21, T2D, v20, v16);
4645 eor(v20, T16B, v17, v21);
4646
4647 shl(v16, T2D, v28, 1);
4648 shl(v17, T2D, v20, 1);
4649
4650 eor(v0, T16B, v0, v16);
4651 eor(v1, T16B, v1, v17);
4652
4653 subs(len, len, 32);
4654 br(Assembler::GE, L_fold);
4655
4656 mov(crc, 0);
4657 mov(tmp, v0, D, 0);
4658 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4659 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4660 mov(tmp, v0, D, 1);
4661 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4662 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4663 mov(tmp, v1, D, 0);
4664 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4665 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4666 mov(tmp, v1, D, 1);
4667 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4668 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4669
4670 add(len, len, 32);
4671 } // Neon code end
4672
4673 BIND(L_by16);
4674 subs(len, len, 16);
4675 br(Assembler::GE, L_by16_loop);
4676 adds(len, len, 16-4);
4677 br(Assembler::GE, L_by4_loop);
4678 adds(len, len, 4);
4679 br(Assembler::GT, L_by1_loop);
4680 b(L_exit);
4681
4682 BIND(L_by4_loop);
4683 ldrw(tmp, Address(post(buf, 4)));
4684 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
4685 subs(len, len, 4);
4686 br(Assembler::GE, L_by4_loop);
4687 adds(len, len, 4);
4688 br(Assembler::LE, L_exit);
4689 BIND(L_by1_loop);
4690 subs(len, len, 1);
4691 ldrb(tmp, Address(post(buf, 1)));
4692 update_byte_crc32(crc, tmp, table0);
4693 br(Assembler::GT, L_by1_loop);
4694 b(L_exit);
4695
4696 align(CodeEntryAlignment);
4697 BIND(L_by16_loop);
4698 subs(len, len, 16);
4699 ldp(tmp, tmp3, Address(post(buf, 16)));
4700 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4701 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4702 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
4703 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
4704 br(Assembler::GE, L_by16_loop);
4705 adds(len, len, 16-4);
4706 br(Assembler::GE, L_by4_loop);
4707 adds(len, len, 4);
4708 br(Assembler::GT, L_by1_loop);
4709 BIND(L_exit);
4710 mvnw(crc, crc);
4711 }
4712
4713 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
4714 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4715 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4716 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4717
4718 subs(tmp0, len, 384);
4719 br(Assembler::GE, CRC_by128_pre);
4720 BIND(CRC_less128);
4721 subs(len, len, 32);
4722 br(Assembler::GE, CRC_by32_loop);
4723 BIND(CRC_less32);
4724 adds(len, len, 32 - 4);
4725 br(Assembler::GE, CRC_by4_loop);
4726 adds(len, len, 4);
4727 br(Assembler::GT, CRC_by1_loop);
4728 b(L_exit);
4729
4730 BIND(CRC_by32_loop);
4731 ldp(tmp0, tmp1, Address(buf));
4732 crc32cx(crc, crc, tmp0);
4733 ldr(tmp2, Address(buf, 16));
4734 crc32cx(crc, crc, tmp1);
4735 ldr(tmp3, Address(buf, 24));
4736 crc32cx(crc, crc, tmp2);
4737 add(buf, buf, 32);
4738 subs(len, len, 32);
4739 crc32cx(crc, crc, tmp3);
4740 br(Assembler::GE, CRC_by32_loop);
4741 cmn(len, (u1)32);
4742 br(Assembler::NE, CRC_less32);
4743 b(L_exit);
4744
4745 BIND(CRC_by4_loop);
4746 ldrw(tmp0, Address(post(buf, 4)));
4747 subs(len, len, 4);
4748 crc32cw(crc, crc, tmp0);
4749 br(Assembler::GE, CRC_by4_loop);
4750 adds(len, len, 4);
4751 br(Assembler::LE, L_exit);
4752 BIND(CRC_by1_loop);
4753 ldrb(tmp0, Address(post(buf, 1)));
4754 subs(len, len, 1);
4755 crc32cb(crc, crc, tmp0);
4756 br(Assembler::GT, CRC_by1_loop);
4757 b(L_exit);
4758
4759 BIND(CRC_by128_pre);
4760 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4761 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50);
4762 mov(crc, 0);
4763 crc32cx(crc, crc, tmp0);
4764 crc32cx(crc, crc, tmp1);
4765
4766 cbnz(len, CRC_less128);
4767
4768 BIND(L_exit);
4769 }
4770
4771 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
4772 Register len, Register tmp0, Register tmp1, Register tmp2,
4773 Register tmp3) {
4774 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4775 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4776
4777 subs(len, len, 128);
4778 br(Assembler::GE, CRC_by64_pre);
4779 BIND(CRC_less64);
4780 adds(len, len, 128-32);
4781 br(Assembler::GE, CRC_by32_loop);
4782 BIND(CRC_less32);
4783 adds(len, len, 32-4);
4784 br(Assembler::GE, CRC_by4_loop);
4785 adds(len, len, 4);
4786 br(Assembler::GT, CRC_by1_loop);
4787 b(L_exit);
4788
4789 BIND(CRC_by32_loop);
4790 ldp(tmp0, tmp1, Address(post(buf, 16)));
4791 subs(len, len, 32);
4792 crc32cx(crc, crc, tmp0);
4793 ldr(tmp2, Address(post(buf, 8)));
4794 crc32cx(crc, crc, tmp1);
4795 ldr(tmp3, Address(post(buf, 8)));
4796 crc32cx(crc, crc, tmp2);
4797 crc32cx(crc, crc, tmp3);
4798 br(Assembler::GE, CRC_by32_loop);
4799 cmn(len, (u1)32);
4800 br(Assembler::NE, CRC_less32);
4801 b(L_exit);
4802
4803 BIND(CRC_by4_loop);
4804 ldrw(tmp0, Address(post(buf, 4)));
4805 subs(len, len, 4);
4806 crc32cw(crc, crc, tmp0);
4807 br(Assembler::GE, CRC_by4_loop);
4808 adds(len, len, 4);
4809 br(Assembler::LE, L_exit);
4810 BIND(CRC_by1_loop);
4811 ldrb(tmp0, Address(post(buf, 1)));
4812 subs(len, len, 1);
4813 crc32cb(crc, crc, tmp0);
4814 br(Assembler::GT, CRC_by1_loop);
4815 b(L_exit);
4816
4817 BIND(CRC_by64_pre);
4818 sub(buf, buf, 8);
4819 ldp(tmp0, tmp1, Address(buf, 8));
4820 crc32cx(crc, crc, tmp0);
4821 ldr(tmp2, Address(buf, 24));
4822 crc32cx(crc, crc, tmp1);
4823 ldr(tmp3, Address(buf, 32));
4824 crc32cx(crc, crc, tmp2);
4825 ldr(tmp0, Address(buf, 40));
4826 crc32cx(crc, crc, tmp3);
4827 ldr(tmp1, Address(buf, 48));
4828 crc32cx(crc, crc, tmp0);
4829 ldr(tmp2, Address(buf, 56));
4830 crc32cx(crc, crc, tmp1);
4831 ldr(tmp3, Address(pre(buf, 64)));
4832
4833 b(CRC_by64_loop);
4834
4835 align(CodeEntryAlignment);
4836 BIND(CRC_by64_loop);
4837 subs(len, len, 64);
4838 crc32cx(crc, crc, tmp2);
4839 ldr(tmp0, Address(buf, 8));
4840 crc32cx(crc, crc, tmp3);
4841 ldr(tmp1, Address(buf, 16));
4842 crc32cx(crc, crc, tmp0);
4843 ldr(tmp2, Address(buf, 24));
4844 crc32cx(crc, crc, tmp1);
4845 ldr(tmp3, Address(buf, 32));
4846 crc32cx(crc, crc, tmp2);
4847 ldr(tmp0, Address(buf, 40));
4848 crc32cx(crc, crc, tmp3);
4849 ldr(tmp1, Address(buf, 48));
4850 crc32cx(crc, crc, tmp0);
4851 ldr(tmp2, Address(buf, 56));
4852 crc32cx(crc, crc, tmp1);
4853 ldr(tmp3, Address(pre(buf, 64)));
4854 br(Assembler::GE, CRC_by64_loop);
4855
4856 // post-loop
4857 crc32cx(crc, crc, tmp2);
4858 crc32cx(crc, crc, tmp3);
4859
4860 sub(len, len, 64);
4861 add(buf, buf, 8);
4862 cmn(len, (u1)128);
4863 br(Assembler::NE, CRC_less64);
4864 BIND(L_exit);
4865 }
4866
4867 /**
4868 * @param crc register containing existing CRC (32-bit)
4869 * @param buf register pointing to input byte buffer (byte*)
4870 * @param len register containing number of bytes
4871 * @param table register that will contain address of CRC table
4872 * @param tmp scratch register
4873 */
4874 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
4875 Register table0, Register table1, Register table2, Register table3,
4876 Register tmp, Register tmp2, Register tmp3) {
4877 if (UseCryptoPmullForCRC32) {
4878 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4879 } else {
4880 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
4881 }
4882 }
4883
4884 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
4885 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) {
4886 Label CRC_by128_loop;
4887 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4888
4889 sub(len, len, 256);
4890 Register table = tmp0;
4891 {
4892 uint64_t offset;
4893 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4894 add(table, table, offset);
4895 }
4896 add(table, table, table_offset);
4897
4898 // Registers v0..v7 are used as data registers.
4899 // Registers v16..v31 are used as tmp registers.
4900 sub(buf, buf, 0x10);
4901 ldrq(v0, Address(buf, 0x10));
4902 ldrq(v1, Address(buf, 0x20));
4903 ldrq(v2, Address(buf, 0x30));
4904 ldrq(v3, Address(buf, 0x40));
4905 ldrq(v4, Address(buf, 0x50));
4906 ldrq(v5, Address(buf, 0x60));
4907 ldrq(v6, Address(buf, 0x70));
4908 ldrq(v7, Address(pre(buf, 0x80)));
4909
4910 movi(v31, T4S, 0);
4911 mov(v31, S, 0, crc);
4912 eor(v0, T16B, v0, v31);
4913
4914 // Register v16 contains constants from the crc table.
4915 ldrq(v16, Address(table));
4916 b(CRC_by128_loop);
4917
4918 align(OptoLoopAlignment);
4919 BIND(CRC_by128_loop);
4920 pmull (v17, T1Q, v0, v16, T1D);
4921 pmull2(v18, T1Q, v0, v16, T2D);
4922 ldrq(v0, Address(buf, 0x10));
4923 eor3(v0, T16B, v17, v18, v0);
4924
4925 pmull (v19, T1Q, v1, v16, T1D);
4926 pmull2(v20, T1Q, v1, v16, T2D);
4927 ldrq(v1, Address(buf, 0x20));
4928 eor3(v1, T16B, v19, v20, v1);
4929
4930 pmull (v21, T1Q, v2, v16, T1D);
4931 pmull2(v22, T1Q, v2, v16, T2D);
4932 ldrq(v2, Address(buf, 0x30));
4933 eor3(v2, T16B, v21, v22, v2);
4934
4935 pmull (v23, T1Q, v3, v16, T1D);
4936 pmull2(v24, T1Q, v3, v16, T2D);
4937 ldrq(v3, Address(buf, 0x40));
4938 eor3(v3, T16B, v23, v24, v3);
4939
4940 pmull (v25, T1Q, v4, v16, T1D);
4941 pmull2(v26, T1Q, v4, v16, T2D);
4942 ldrq(v4, Address(buf, 0x50));
4943 eor3(v4, T16B, v25, v26, v4);
4944
4945 pmull (v27, T1Q, v5, v16, T1D);
4946 pmull2(v28, T1Q, v5, v16, T2D);
4947 ldrq(v5, Address(buf, 0x60));
4948 eor3(v5, T16B, v27, v28, v5);
4949
4950 pmull (v29, T1Q, v6, v16, T1D);
4951 pmull2(v30, T1Q, v6, v16, T2D);
4952 ldrq(v6, Address(buf, 0x70));
4953 eor3(v6, T16B, v29, v30, v6);
4954
4955 // Reuse registers v23, v24.
4956 // Using them won't block the first instruction of the next iteration.
4957 pmull (v23, T1Q, v7, v16, T1D);
4958 pmull2(v24, T1Q, v7, v16, T2D);
4959 ldrq(v7, Address(pre(buf, 0x80)));
4960 eor3(v7, T16B, v23, v24, v7);
4961
4962 subs(len, len, 0x80);
4963 br(Assembler::GE, CRC_by128_loop);
4964
4965 // fold into 512 bits
4966 // Use v31 for constants because v16 can be still in use.
4967 ldrq(v31, Address(table, 0x10));
4968
4969 pmull (v17, T1Q, v0, v31, T1D);
4970 pmull2(v18, T1Q, v0, v31, T2D);
4971 eor3(v0, T16B, v17, v18, v4);
4972
4973 pmull (v19, T1Q, v1, v31, T1D);
4974 pmull2(v20, T1Q, v1, v31, T2D);
4975 eor3(v1, T16B, v19, v20, v5);
4976
4977 pmull (v21, T1Q, v2, v31, T1D);
4978 pmull2(v22, T1Q, v2, v31, T2D);
4979 eor3(v2, T16B, v21, v22, v6);
4980
4981 pmull (v23, T1Q, v3, v31, T1D);
4982 pmull2(v24, T1Q, v3, v31, T2D);
4983 eor3(v3, T16B, v23, v24, v7);
4984
4985 // fold into 128 bits
4986 // Use v17 for constants because v31 can be still in use.
4987 ldrq(v17, Address(table, 0x20));
4988 pmull (v25, T1Q, v0, v17, T1D);
4989 pmull2(v26, T1Q, v0, v17, T2D);
4990 eor3(v3, T16B, v3, v25, v26);
4991
4992 // Use v18 for constants because v17 can be still in use.
4993 ldrq(v18, Address(table, 0x30));
4994 pmull (v27, T1Q, v1, v18, T1D);
4995 pmull2(v28, T1Q, v1, v18, T2D);
4996 eor3(v3, T16B, v3, v27, v28);
4997
4998 // Use v19 for constants because v18 can be still in use.
4999 ldrq(v19, Address(table, 0x40));
5000 pmull (v29, T1Q, v2, v19, T1D);
5001 pmull2(v30, T1Q, v2, v19, T2D);
5002 eor3(v0, T16B, v3, v29, v30);
5003
5004 add(len, len, 0x80);
5005 add(buf, buf, 0x10);
5006
5007 mov(tmp0, v0, D, 0);
5008 mov(tmp1, v0, D, 1);
5009 }
5010
5011 void MacroAssembler::addptr(const Address &dst, int32_t src) {
5012 Address adr;
5013 switch(dst.getMode()) {
5014 case Address::base_plus_offset:
5015 // This is the expected mode, although we allow all the other
5016 // forms below.
5017 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
5018 break;
5019 default:
5020 lea(rscratch2, dst);
5021 adr = Address(rscratch2);
5022 break;
5023 }
5024 ldr(rscratch1, adr);
5025 add(rscratch1, rscratch1, src);
5026 str(rscratch1, adr);
5027 }
5028
5029 void MacroAssembler::cmpptr(Register src1, Address src2) {
5030 uint64_t offset;
5031 adrp(rscratch1, src2, offset);
5032 ldr(rscratch1, Address(rscratch1, offset));
5033 cmp(src1, rscratch1);
5034 }
5035
5036 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
5037 cmp(obj1, obj2);
5038 }
5039
5040 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5041 load_method_holder(rresult, rmethod);
5042 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5043 }
5044
5045 void MacroAssembler::load_method_holder(Register holder, Register method) {
5046 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
5047 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5048 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5049 }
5050
5051 // Loads the obj's Klass* into dst.
5052 // Preserves all registers (incl src, rscratch1 and rscratch2).
5053 // Input:
5054 // src - the oop we want to load the klass from.
5055 // dst - output narrow klass.
5056 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5057 assert(UseCompactObjectHeaders, "expects UseCompactObjectHeaders");
5058 ldr(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5059 lsr(dst, dst, markWord::klass_shift);
5060 }
5061
5062 void MacroAssembler::load_klass(Register dst, Register src) {
5063 if (UseCompactObjectHeaders) {
5064 load_narrow_klass_compact(dst, src);
5065 } else {
5066 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5067 }
5068 decode_klass_not_null(dst);
5069 }
5070
5071 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5072 if (RestoreMXCSROnJNICalls) {
5073 Label OK;
5074 get_fpcr(tmp1);
5075 mov(tmp2, tmp1);
5076 // Set FPCR to the state we need. We do want Round to Nearest. We
5077 // don't want non-IEEE rounding modes or floating-point traps.
5078 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5079 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5080 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5081 eor(tmp2, tmp1, tmp2);
5082 cbz(tmp2, OK); // Only reset FPCR if it's wrong
5083 set_fpcr(tmp1);
5084 bind(OK);
5085 }
5086 }
5087
5088 // ((OopHandle)result).resolve();
5089 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
5090 // OopHandle::resolve is an indirection.
5091 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
5092 }
5093
5094 // ((WeakHandle)result).resolve();
5095 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
5096 assert_different_registers(result, tmp1, tmp2);
5097 Label resolved;
5098
5099 // A null weak handle resolves to null.
5100 cbz(result, resolved);
5101
5102 // Only 64 bit platforms support GCs that require a tmp register
5103 // WeakHandle::resolve is an indirection like jweak.
5104 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5105 result, Address(result), tmp1, tmp2);
5106 bind(resolved);
5107 }
5108
5109 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) {
5110 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5111 ldr(dst, Address(rmethod, Method::const_offset()));
5112 ldr(dst, Address(dst, ConstMethod::constants_offset()));
5113 ldr(dst, Address(dst, ConstantPool::pool_holder_offset()));
5114 ldr(dst, Address(dst, mirror_offset));
5115 resolve_oop_handle(dst, tmp1, tmp2);
5116 }
5117
5118 void MacroAssembler::cmp_klass(Register obj, Register klass, Register tmp) {
5119 assert_different_registers(obj, klass, tmp);
5120 if (UseCompactObjectHeaders) {
5121 load_narrow_klass_compact(tmp, obj);
5122 } else {
5123 ldrw(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5124 }
5125 if (CompressedKlassPointers::base() == nullptr) {
5126 cmp(klass, tmp, LSL, CompressedKlassPointers::shift());
5127 return;
5128 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5129 && CompressedKlassPointers::shift() == 0) {
5130 // Only the bottom 32 bits matter
5131 cmpw(klass, tmp);
5132 return;
5133 }
5134 decode_klass_not_null(tmp);
5135 cmp(klass, tmp);
5136 }
5137
5138 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5139 if (UseCompactObjectHeaders) {
5140 load_narrow_klass_compact(tmp1, obj1);
5141 load_narrow_klass_compact(tmp2, obj2);
5142 } else {
5143 ldrw(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5144 ldrw(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5145 }
5146 cmpw(tmp1, tmp2);
5147 }
5148
5149 void MacroAssembler::store_klass(Register dst, Register src) {
5150 // FIXME: Should this be a store release? concurrent gcs assumes
5151 // klass length is valid if klass field is not null.
5152 assert(!UseCompactObjectHeaders, "not with compact headers");
5153 encode_klass_not_null(src);
5154 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5155 }
5156
5157 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5158 assert(!UseCompactObjectHeaders, "not with compact headers");
5159 // Store to klass gap in destination
5160 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5161 }
5162
5163 // Algorithm must match CompressedOops::encode.
5164 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5165 #ifdef ASSERT
5166 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5167 #endif
5168 verify_oop_msg(s, "broken oop in encode_heap_oop");
5169 if (CompressedOops::base() == nullptr) {
5170 if (CompressedOops::shift() != 0) {
5171 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5172 lsr(d, s, LogMinObjAlignmentInBytes);
5173 } else {
5174 mov(d, s);
5175 }
5176 } else {
5177 subs(d, s, rheapbase);
5178 csel(d, d, zr, Assembler::HS);
5179 lsr(d, d, LogMinObjAlignmentInBytes);
5180
5181 /* Old algorithm: is this any worse?
5182 Label nonnull;
5183 cbnz(r, nonnull);
5184 sub(r, r, rheapbase);
5185 bind(nonnull);
5186 lsr(r, r, LogMinObjAlignmentInBytes);
5187 */
5188 }
5189 }
5190
5191 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5192 #ifdef ASSERT
5193 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5194 if (CheckCompressedOops) {
5195 Label ok;
5196 cbnz(r, ok);
5197 stop("null oop passed to encode_heap_oop_not_null");
5198 bind(ok);
5199 }
5200 #endif
5201 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5202 if (CompressedOops::base() != nullptr) {
5203 sub(r, r, rheapbase);
5204 }
5205 if (CompressedOops::shift() != 0) {
5206 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5207 lsr(r, r, LogMinObjAlignmentInBytes);
5208 }
5209 }
5210
5211 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5212 #ifdef ASSERT
5213 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5214 if (CheckCompressedOops) {
5215 Label ok;
5216 cbnz(src, ok);
5217 stop("null oop passed to encode_heap_oop_not_null2");
5218 bind(ok);
5219 }
5220 #endif
5221 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5222
5223 Register data = src;
5224 if (CompressedOops::base() != nullptr) {
5225 sub(dst, src, rheapbase);
5226 data = dst;
5227 }
5228 if (CompressedOops::shift() != 0) {
5229 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5230 lsr(dst, data, LogMinObjAlignmentInBytes);
5231 data = dst;
5232 }
5233 if (data == src)
5234 mov(dst, src);
5235 }
5236
5237 void MacroAssembler::decode_heap_oop(Register d, Register s) {
5238 #ifdef ASSERT
5239 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5240 #endif
5241 if (CompressedOops::base() == nullptr) {
5242 if (CompressedOops::shift() != 0) {
5243 lsl(d, s, CompressedOops::shift());
5244 } else if (d != s) {
5245 mov(d, s);
5246 }
5247 } else {
5248 Label done;
5249 if (d != s)
5250 mov(d, s);
5251 cbz(s, done);
5252 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
5253 bind(done);
5254 }
5255 verify_oop_msg(d, "broken oop in decode_heap_oop");
5256 }
5257
5258 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5259 assert (UseCompressedOops, "should only be used for compressed headers");
5260 assert (Universe::heap() != nullptr, "java heap should be initialized");
5261 // Cannot assert, unverified entry point counts instructions (see .ad file)
5262 // vtableStubs also counts instructions in pd_code_size_limit.
5263 // Also do not verify_oop as this is called by verify_oop.
5264 if (CompressedOops::shift() != 0) {
5265 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5266 if (CompressedOops::base() != nullptr) {
5267 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5268 } else {
5269 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5270 }
5271 } else {
5272 assert (CompressedOops::base() == nullptr, "sanity");
5273 }
5274 }
5275
5276 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5277 assert (UseCompressedOops, "should only be used for compressed headers");
5278 assert (Universe::heap() != nullptr, "java heap should be initialized");
5279 // Cannot assert, unverified entry point counts instructions (see .ad file)
5280 // vtableStubs also counts instructions in pd_code_size_limit.
5281 // Also do not verify_oop as this is called by verify_oop.
5282 if (CompressedOops::shift() != 0) {
5283 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5284 if (CompressedOops::base() != nullptr) {
5285 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5286 } else {
5287 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5288 }
5289 } else {
5290 assert (CompressedOops::base() == nullptr, "sanity");
5291 if (dst != src) {
5292 mov(dst, src);
5293 }
5294 }
5295 }
5296
5297 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone);
5298
5299 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
5300 assert(Metaspace::initialized(), "metaspace not initialized yet");
5301 assert(_klass_decode_mode != KlassDecodeNone, "should be initialized");
5302 return _klass_decode_mode;
5303 }
5304
5305 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode(address base, int shift, const size_t range) {
5306 // KlassDecodeMode shouldn't be set already.
5307 assert(_klass_decode_mode == KlassDecodeNone, "set once");
5308
5309 if (base == nullptr) {
5310 return KlassDecodeZero;
5311 }
5312
5313 if (operand_valid_for_logical_immediate(
5314 /*is32*/false, (uint64_t)base)) {
5315 const uint64_t range_mask = right_n_bits(log2i_ceil(range));
5316 if (((uint64_t)base & range_mask) == 0) {
5317 return KlassDecodeXor;
5318 }
5319 }
5320
5321 const uint64_t shifted_base =
5322 (uint64_t)base >> shift;
5323 if ((shifted_base & 0xffff0000ffffffff) == 0) {
5324 return KlassDecodeMovk;
5325 }
5326
5327 // No valid encoding.
5328 return KlassDecodeNone;
5329 }
5330
5331 // Check if one of the above decoding modes will work for given base, shift and range.
5332 bool MacroAssembler::check_klass_decode_mode(address base, int shift, const size_t range) {
5333 return klass_decode_mode(base, shift, range) != KlassDecodeNone;
5334 }
5335
5336 bool MacroAssembler::set_klass_decode_mode(address base, int shift, const size_t range) {
5337 _klass_decode_mode = klass_decode_mode(base, shift, range);
5338 return _klass_decode_mode != KlassDecodeNone;
5339 }
5340
5341 static Register pick_different_tmp(Register dst, Register src) {
5342 auto tmps = RegSet::of(r0, r1, r2) - RegSet::of(src, dst);
5343 return *tmps.begin();
5344 }
5345
5346 void MacroAssembler::encode_klass_not_null_for_aot(Register dst, Register src) {
5347 // we have to load the klass base from the AOT constants area but
5348 // not the shift because it is not allowed to change
5349 int shift = CompressedKlassPointers::shift();
5350 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5351 if (dst != src) {
5352 // we can load the base into dst, subtract it formthe src and shift down
5353 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5354 ldr(dst, dst);
5355 sub(dst, src, dst);
5356 lsr(dst, dst, shift);
5357 } else {
5358 // we need an extra register in order to load the coop base
5359 Register tmp = pick_different_tmp(dst, src);
5360 RegSet regs = RegSet::of(tmp);
5361 push(regs, sp);
5362 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5363 ldr(tmp, tmp);
5364 sub(dst, src, tmp);
5365 lsr(dst, dst, shift);
5366 pop(regs, sp);
5367 }
5368 }
5369
5370 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5371 if (AOTCodeCache::is_on_for_dump()) {
5372 encode_klass_not_null_for_aot(dst, src);
5373 return;
5374 }
5375
5376 switch (klass_decode_mode()) {
5377 case KlassDecodeZero:
5378 if (CompressedKlassPointers::shift() != 0) {
5379 lsr(dst, src, CompressedKlassPointers::shift());
5380 } else {
5381 if (dst != src) mov(dst, src);
5382 }
5383 break;
5384
5385 case KlassDecodeXor:
5386 if (CompressedKlassPointers::shift() != 0) {
5387 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5388 lsr(dst, dst, CompressedKlassPointers::shift());
5389 } else {
5390 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5391 }
5392 break;
5393
5394 case KlassDecodeMovk:
5395 if (CompressedKlassPointers::shift() != 0) {
5396 ubfx(dst, src, CompressedKlassPointers::shift(), 32);
5397 } else {
5398 movw(dst, src);
5399 }
5400 break;
5401
5402 case KlassDecodeNone:
5403 ShouldNotReachHere();
5404 break;
5405 }
5406 }
5407
5408 void MacroAssembler::encode_klass_not_null(Register r) {
5409 encode_klass_not_null(r, r);
5410 }
5411
5412 void MacroAssembler::decode_klass_not_null_for_aot(Register dst, Register src) {
5413 // we have to load the klass base from the AOT constants area but
5414 // not the shift because it is not allowed to change
5415 int shift = CompressedKlassPointers::shift();
5416 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5417 if (dst != src) {
5418 // we can load the base into dst then add the offset with a suitable shift
5419 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5420 ldr(dst, dst);
5421 add(dst, dst, src, LSL, shift);
5422 } else {
5423 // we need an extra register in order to load the coop base
5424 Register tmp = pick_different_tmp(dst, src);
5425 RegSet regs = RegSet::of(tmp);
5426 push(regs, sp);
5427 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5428 ldr(tmp, tmp);
5429 add(dst, tmp, src, LSL, shift);
5430 pop(regs, sp);
5431 }
5432 }
5433
5434 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5435 if (AOTCodeCache::is_on_for_dump()) {
5436 decode_klass_not_null_for_aot(dst, src);
5437 return;
5438 }
5439
5440 switch (klass_decode_mode()) {
5441 case KlassDecodeZero:
5442 if (CompressedKlassPointers::shift() != 0) {
5443 lsl(dst, src, CompressedKlassPointers::shift());
5444 } else {
5445 if (dst != src) mov(dst, src);
5446 }
5447 break;
5448
5449 case KlassDecodeXor:
5450 if (CompressedKlassPointers::shift() != 0) {
5451 lsl(dst, src, CompressedKlassPointers::shift());
5452 eor(dst, dst, (uint64_t)CompressedKlassPointers::base());
5453 } else {
5454 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5455 }
5456 break;
5457
5458 case KlassDecodeMovk: {
5459 const uint64_t shifted_base =
5460 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5461
5462 if (dst != src) movw(dst, src);
5463 movk(dst, shifted_base >> 32, 32);
5464
5465 if (CompressedKlassPointers::shift() != 0) {
5466 lsl(dst, dst, CompressedKlassPointers::shift());
5467 }
5468
5469 break;
5470 }
5471
5472 case KlassDecodeNone:
5473 ShouldNotReachHere();
5474 break;
5475 }
5476 }
5477
5478 void MacroAssembler::decode_klass_not_null(Register r) {
5479 decode_klass_not_null(r, r);
5480 }
5481
5482 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5483 #ifdef ASSERT
5484 {
5485 ThreadInVMfromUnknown tiv;
5486 assert (UseCompressedOops, "should only be used for compressed oops");
5487 assert (Universe::heap() != nullptr, "java heap should be initialized");
5488 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5489 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5490 }
5491 #endif
5492 int oop_index = oop_recorder()->find_index(obj);
5493 InstructionMark im(this);
5494 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5495 code_section()->relocate(inst_mark(), rspec);
5496 movz(dst, 0xDEAD, 16);
5497 movk(dst, 0xBEEF);
5498 }
5499
5500 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5501 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5502 int index = oop_recorder()->find_index(k);
5503
5504 InstructionMark im(this);
5505 RelocationHolder rspec = metadata_Relocation::spec(index);
5506 code_section()->relocate(inst_mark(), rspec);
5507 narrowKlass nk = CompressedKlassPointers::encode(k);
5508 movz(dst, (nk >> 16), 16);
5509 movk(dst, nk & 0xffff);
5510 }
5511
5512 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
5513 Register dst, Address src,
5514 Register tmp1, Register tmp2) {
5515 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5516 decorators = AccessInternal::decorator_fixup(decorators, type);
5517 bool as_raw = (decorators & AS_RAW) != 0;
5518 if (as_raw) {
5519 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5520 } else {
5521 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5522 }
5523 }
5524
5525 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5526 Address dst, Register val,
5527 Register tmp1, Register tmp2, Register tmp3) {
5528 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5529 decorators = AccessInternal::decorator_fixup(decorators, type);
5530 bool as_raw = (decorators & AS_RAW) != 0;
5531 if (as_raw) {
5532 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5533 } else {
5534 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5535 }
5536 }
5537
5538 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5539 Register tmp2, DecoratorSet decorators) {
5540 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5541 }
5542
5543 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5544 Register tmp2, DecoratorSet decorators) {
5545 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5546 }
5547
5548 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5549 Register tmp2, Register tmp3, DecoratorSet decorators) {
5550 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5551 }
5552
5553 // Used for storing nulls.
5554 void MacroAssembler::store_heap_oop_null(Address dst) {
5555 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5556 }
5557
5558 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
5559 assert(oop_recorder() != nullptr, "this assembler needs a Recorder");
5560 int index = oop_recorder()->allocate_metadata_index(obj);
5561 RelocationHolder rspec = metadata_Relocation::spec(index);
5562 return Address((address)obj, rspec);
5563 }
5564
5565 // Move an oop into a register.
5566 void MacroAssembler::movoop(Register dst, jobject obj) {
5567 int oop_index;
5568 if (obj == nullptr) {
5569 oop_index = oop_recorder()->allocate_oop_index(obj);
5570 } else {
5571 #ifdef ASSERT
5572 {
5573 ThreadInVMfromUnknown tiv;
5574 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5575 }
5576 #endif
5577 oop_index = oop_recorder()->find_index(obj);
5578 }
5579 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5580
5581 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
5582 mov(dst, Address((address)obj, rspec));
5583 } else {
5584 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
5585 ldr(dst, Address(dummy, rspec));
5586 }
5587 }
5588
5589 // Move a metadata address into a register.
5590 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
5591 int oop_index;
5592 if (obj == nullptr) {
5593 oop_index = oop_recorder()->allocate_metadata_index(obj);
5594 } else {
5595 oop_index = oop_recorder()->find_index(obj);
5596 }
5597 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5598 mov(dst, Address((address)obj, rspec));
5599 }
5600
5601 Address MacroAssembler::constant_oop_address(jobject obj) {
5602 #ifdef ASSERT
5603 {
5604 ThreadInVMfromUnknown tiv;
5605 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5606 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5607 }
5608 #endif
5609 int oop_index = oop_recorder()->find_index(obj);
5610 return Address((address)obj, oop_Relocation::spec(oop_index));
5611 }
5612
5613 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5614 void MacroAssembler::tlab_allocate(Register obj,
5615 Register var_size_in_bytes,
5616 int con_size_in_bytes,
5617 Register t1,
5618 Register t2,
5619 Label& slow_case) {
5620 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5621 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5622 }
5623
5624 void MacroAssembler::verify_tlab() {
5625 #ifdef ASSERT
5626 if (UseTLAB && VerifyOops) {
5627 Label next, ok;
5628
5629 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5630
5631 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5632 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5633 cmp(rscratch2, rscratch1);
5634 br(Assembler::HS, next);
5635 STOP("assert(top >= start)");
5636 should_not_reach_here();
5637
5638 bind(next);
5639 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5640 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5641 cmp(rscratch2, rscratch1);
5642 br(Assembler::HS, ok);
5643 STOP("assert(top <= end)");
5644 should_not_reach_here();
5645
5646 bind(ok);
5647 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5648 }
5649 #endif
5650 }
5651
5652 // Writes to stack successive pages until offset reached to check for
5653 // stack overflow + shadow pages. This clobbers tmp.
5654 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5655 assert_different_registers(tmp, size, rscratch1);
5656 mov(tmp, sp);
5657 // Bang stack for total size given plus shadow page size.
5658 // Bang one page at a time because large size can bang beyond yellow and
5659 // red zones.
5660 Label loop;
5661 mov(rscratch1, (int)os::vm_page_size());
5662 bind(loop);
5663 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5664 subsw(size, size, rscratch1);
5665 str(size, Address(tmp));
5666 br(Assembler::GT, loop);
5667
5668 // Bang down shadow pages too.
5669 // At this point, (tmp-0) is the last address touched, so don't
5670 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5671 // was post-decremented.) Skip this address by starting at i=1, and
5672 // touch a few more pages below. N.B. It is important to touch all
5673 // the way down to and including i=StackShadowPages.
5674 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) {
5675 // this could be any sized move but this is can be a debugging crumb
5676 // so the bigger the better.
5677 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5678 str(size, Address(tmp));
5679 }
5680 }
5681
5682 // Move the address of the polling page into dest.
5683 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) {
5684 ldr(dest, Address(rthread, JavaThread::polling_page_offset()));
5685 }
5686
5687 // Read the polling page. The address of the polling page must
5688 // already be in r.
5689 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
5690 address mark;
5691 {
5692 InstructionMark im(this);
5693 code_section()->relocate(inst_mark(), rtype);
5694 ldrw(zr, Address(r, 0));
5695 mark = inst_mark();
5696 }
5697 verify_cross_modify_fence_not_required();
5698 return mark;
5699 }
5700
5701 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
5702 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
5703 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
5704 uint64_t dest_page = (uint64_t)dest.target() >> 12;
5705 int64_t offset_low = dest_page - low_page;
5706 int64_t offset_high = dest_page - high_page;
5707
5708 assert(is_valid_AArch64_address(dest.target()), "bad address");
5709 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
5710
5711 InstructionMark im(this);
5712 code_section()->relocate(inst_mark(), dest.rspec());
5713 // 8143067: Ensure that the adrp can reach the dest from anywhere within
5714 // the code cache so that if it is relocated we know it will still reach
5715 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
5716 _adrp(reg1, dest.target());
5717 } else {
5718 uint64_t target = (uint64_t)dest.target();
5719 uint64_t adrp_target
5720 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
5721
5722 _adrp(reg1, (address)adrp_target);
5723 movk(reg1, target >> 32, 32);
5724 }
5725 byte_offset = (uint64_t)dest.target() & 0xfff;
5726 }
5727
5728 void MacroAssembler::load_byte_map_base(Register reg) {
5729 #if INCLUDE_CDS
5730 if (AOTCodeCache::is_on_for_dump()) {
5731 address byte_map_base_adr = AOTRuntimeConstants::card_table_base_address();
5732 lea(reg, ExternalAddress(byte_map_base_adr));
5733 ldr(reg, Address(reg));
5734 return;
5735 }
5736 #endif
5737 CardTableBarrierSet* ctbs = CardTableBarrierSet::barrier_set();
5738
5739 // Strictly speaking the card table base isn't an address at all, and it might
5740 // even be negative. It is thus materialised as a constant.
5741 mov(reg, (uint64_t)ctbs->card_table_base_const());
5742 }
5743
5744 void MacroAssembler::load_aotrc_address(Register reg, address a) {
5745 #if INCLUDE_CDS
5746 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
5747 if (AOTCodeCache::is_on_for_dump()) {
5748 // all aotrc field addresses should be registered in the AOTCodeCache address table
5749 lea(reg, ExternalAddress(a));
5750 } else {
5751 mov(reg, (uint64_t)a);
5752 }
5753 #else
5754 ShouldNotReachHere();
5755 #endif
5756 }
5757
5758 void MacroAssembler::build_frame(int framesize) {
5759 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5760 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5761 protect_return_address();
5762 if (framesize < ((1 << 9) + 2 * wordSize)) {
5763 sub(sp, sp, framesize);
5764 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5765 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
5766 } else {
5767 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
5768 if (PreserveFramePointer) mov(rfp, sp);
5769 if (framesize < ((1 << 12) + 2 * wordSize))
5770 sub(sp, sp, framesize - 2 * wordSize);
5771 else {
5772 mov(rscratch1, framesize - 2 * wordSize);
5773 sub(sp, sp, rscratch1);
5774 }
5775 }
5776 verify_cross_modify_fence_not_required();
5777 }
5778
5779 void MacroAssembler::remove_frame(int framesize) {
5780 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5781 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5782 if (framesize < ((1 << 9) + 2 * wordSize)) {
5783 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5784 add(sp, sp, framesize);
5785 } else {
5786 if (framesize < ((1 << 12) + 2 * wordSize))
5787 add(sp, sp, framesize - 2 * wordSize);
5788 else {
5789 mov(rscratch1, framesize - 2 * wordSize);
5790 add(sp, sp, rscratch1);
5791 }
5792 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5793 }
5794 authenticate_return_address();
5795 }
5796
5797
5798 // This method counts leading positive bytes (highest bit not set) in provided byte array
5799 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5800 // Simple and most common case of aligned small array which is not at the
5801 // end of memory page is placed here. All other cases are in stub.
5802 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5803 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5804 assert_different_registers(ary1, len, result);
5805
5806 mov(result, len);
5807 cmpw(len, 0);
5808 br(LE, DONE);
5809 cmpw(len, 4 * wordSize);
5810 br(GE, STUB_LONG); // size > 32 then go to stub
5811
5812 int shift = 64 - exact_log2(os::vm_page_size());
5813 lsl(rscratch1, ary1, shift);
5814 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5815 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5816 br(CS, STUB); // at the end of page then go to stub
5817 subs(len, len, wordSize);
5818 br(LT, END);
5819
5820 BIND(LOOP);
5821 ldr(rscratch1, Address(post(ary1, wordSize)));
5822 tst(rscratch1, UPPER_BIT_MASK);
5823 br(NE, SET_RESULT);
5824 subs(len, len, wordSize);
5825 br(GE, LOOP);
5826 cmpw(len, -wordSize);
5827 br(EQ, DONE);
5828
5829 BIND(END);
5830 ldr(rscratch1, Address(ary1));
5831 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
5832 lslv(rscratch1, rscratch1, rscratch2);
5833 tst(rscratch1, UPPER_BIT_MASK);
5834 br(NE, SET_RESULT);
5835 b(DONE);
5836
5837 BIND(STUB);
5838 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives());
5839 assert(count_pos.target() != nullptr, "count_positives stub has not been generated");
5840 address tpc1 = trampoline_call(count_pos);
5841 if (tpc1 == nullptr) {
5842 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE));
5843 postcond(pc() == badAddress);
5844 return nullptr;
5845 }
5846 b(DONE);
5847
5848 BIND(STUB_LONG);
5849 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long());
5850 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated");
5851 address tpc2 = trampoline_call(count_pos_long);
5852 if (tpc2 == nullptr) {
5853 DEBUG_ONLY(reset_labels(SET_RESULT, DONE));
5854 postcond(pc() == badAddress);
5855 return nullptr;
5856 }
5857 b(DONE);
5858
5859 BIND(SET_RESULT);
5860
5861 add(len, len, wordSize);
5862 sub(result, result, len);
5863
5864 BIND(DONE);
5865 postcond(pc() != badAddress);
5866 return pc();
5867 }
5868
5869 // Clobbers: rscratch1, rscratch2, rflags
5870 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals)
5871 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
5872 Register tmp4, Register tmp5, Register result,
5873 Register cnt1, int elem_size) {
5874 Label DONE, SAME;
5875 Register tmp1 = rscratch1;
5876 Register tmp2 = rscratch2;
5877 int elem_per_word = wordSize/elem_size;
5878 int log_elem_size = exact_log2(elem_size);
5879 int klass_offset = arrayOopDesc::klass_offset_in_bytes();
5880 int length_offset = arrayOopDesc::length_offset_in_bytes();
5881 int base_offset
5882 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
5883 // When the length offset is not aligned to 8 bytes,
5884 // then we align it down. This is valid because the new
5885 // offset will always be the klass which is the same
5886 // for type arrays.
5887 int start_offset = align_down(length_offset, BytesPerWord);
5888 int extra_length = base_offset - start_offset;
5889 assert(start_offset == length_offset || start_offset == klass_offset,
5890 "start offset must be 8-byte-aligned or be the klass offset");
5891 assert(base_offset != start_offset, "must include the length field");
5892 extra_length = extra_length / elem_size; // We count in elements, not bytes.
5893 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
5894
5895 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
5896 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5897
5898 #ifndef PRODUCT
5899 {
5900 const char kind = (elem_size == 2) ? 'U' : 'L';
5901 char comment[64];
5902 os::snprintf_checked(comment, sizeof comment, "array_equals%c{", kind);
5903 BLOCK_COMMENT(comment);
5904 }
5905 #endif
5906
5907 // if (a1 == a2)
5908 // return true;
5909 cmpoop(a1, a2); // May have read barriers for a1 and a2.
5910 br(EQ, SAME);
5911
5912 if (UseSimpleArrayEquals) {
5913 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
5914 // if (a1 == nullptr || a2 == nullptr)
5915 // return false;
5916 // a1 & a2 == 0 means (some-pointer is null) or
5917 // (very-rare-or-even-probably-impossible-pointer-values)
5918 // so, we can save one branch in most cases
5919 tst(a1, a2);
5920 mov(result, false);
5921 br(EQ, A_MIGHT_BE_NULL);
5922 // if (a1.length != a2.length)
5923 // return false;
5924 bind(A_IS_NOT_NULL);
5925 ldrw(cnt1, Address(a1, length_offset));
5926 ldrw(tmp5, Address(a2, length_offset));
5927 cmp(cnt1, tmp5);
5928 br(NE, DONE); // If lengths differ, return false
5929 // Increase loop counter by diff between base- and actual start-offset.
5930 addw(cnt1, cnt1, extra_length);
5931 lea(a1, Address(a1, start_offset));
5932 lea(a2, Address(a2, start_offset));
5933 // Check for short strings, i.e. smaller than wordSize.
5934 subs(cnt1, cnt1, elem_per_word);
5935 br(Assembler::LT, SHORT);
5936 // Main 8 byte comparison loop.
5937 bind(NEXT_WORD); {
5938 ldr(tmp1, Address(post(a1, wordSize)));
5939 ldr(tmp2, Address(post(a2, wordSize)));
5940 subs(cnt1, cnt1, elem_per_word);
5941 eor(tmp5, tmp1, tmp2);
5942 cbnz(tmp5, DONE);
5943 } br(GT, NEXT_WORD);
5944 // Last longword. In the case where length == 4 we compare the
5945 // same longword twice, but that's still faster than another
5946 // conditional branch.
5947 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5948 // length == 4.
5949 if (log_elem_size > 0)
5950 lsl(cnt1, cnt1, log_elem_size);
5951 ldr(tmp3, Address(a1, cnt1));
5952 ldr(tmp4, Address(a2, cnt1));
5953 eor(tmp5, tmp3, tmp4);
5954 cbnz(tmp5, DONE);
5955 b(SAME);
5956 bind(A_MIGHT_BE_NULL);
5957 // in case both a1 and a2 are not-null, proceed with loads
5958 cbz(a1, DONE);
5959 cbz(a2, DONE);
5960 b(A_IS_NOT_NULL);
5961 bind(SHORT);
5962
5963 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
5964 {
5965 ldrw(tmp1, Address(post(a1, 4)));
5966 ldrw(tmp2, Address(post(a2, 4)));
5967 eorw(tmp5, tmp1, tmp2);
5968 cbnzw(tmp5, DONE);
5969 }
5970 bind(TAIL03);
5971 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
5972 {
5973 ldrh(tmp3, Address(post(a1, 2)));
5974 ldrh(tmp4, Address(post(a2, 2)));
5975 eorw(tmp5, tmp3, tmp4);
5976 cbnzw(tmp5, DONE);
5977 }
5978 bind(TAIL01);
5979 if (elem_size == 1) { // Only needed when comparing byte arrays.
5980 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5981 {
5982 ldrb(tmp1, a1);
5983 ldrb(tmp2, a2);
5984 eorw(tmp5, tmp1, tmp2);
5985 cbnzw(tmp5, DONE);
5986 }
5987 }
5988 } else {
5989 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
5990 CSET_EQ, LAST_CHECK;
5991 mov(result, false);
5992 cbz(a1, DONE);
5993 ldrw(cnt1, Address(a1, length_offset));
5994 cbz(a2, DONE);
5995 ldrw(tmp5, Address(a2, length_offset));
5996 cmp(cnt1, tmp5);
5997 br(NE, DONE); // If lengths differ, return false
5998 // Increase loop counter by diff between base- and actual start-offset.
5999 addw(cnt1, cnt1, extra_length);
6000
6001 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
6002 // faster to perform another branch before comparing a1 and a2
6003 cmp(cnt1, (u1)elem_per_word);
6004 br(LE, SHORT); // short or same
6005 ldr(tmp3, Address(pre(a1, start_offset)));
6006 subs(zr, cnt1, stubBytesThreshold);
6007 br(GE, STUB);
6008 ldr(tmp4, Address(pre(a2, start_offset)));
6009 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6010
6011 // Main 16 byte comparison loop with 2 exits
6012 bind(NEXT_DWORD); {
6013 ldr(tmp1, Address(pre(a1, wordSize)));
6014 ldr(tmp2, Address(pre(a2, wordSize)));
6015 subs(cnt1, cnt1, 2 * elem_per_word);
6016 br(LE, TAIL);
6017 eor(tmp4, tmp3, tmp4);
6018 cbnz(tmp4, DONE);
6019 ldr(tmp3, Address(pre(a1, wordSize)));
6020 ldr(tmp4, Address(pre(a2, wordSize)));
6021 cmp(cnt1, (u1)elem_per_word);
6022 br(LE, TAIL2);
6023 cmp(tmp1, tmp2);
6024 } br(EQ, NEXT_DWORD);
6025 b(DONE);
6026
6027 bind(TAIL);
6028 eor(tmp4, tmp3, tmp4);
6029 eor(tmp2, tmp1, tmp2);
6030 lslv(tmp2, tmp2, tmp5);
6031 orr(tmp5, tmp4, tmp2);
6032 cmp(tmp5, zr);
6033 b(CSET_EQ);
6034
6035 bind(TAIL2);
6036 eor(tmp2, tmp1, tmp2);
6037 cbnz(tmp2, DONE);
6038 b(LAST_CHECK);
6039
6040 bind(STUB);
6041 ldr(tmp4, Address(pre(a2, start_offset)));
6042 if (elem_size == 2) { // convert to byte counter
6043 lsl(cnt1, cnt1, 1);
6044 }
6045 eor(tmp5, tmp3, tmp4);
6046 cbnz(tmp5, DONE);
6047 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
6048 assert(stub.target() != nullptr, "array_equals_long stub has not been generated");
6049 address tpc = trampoline_call(stub);
6050 if (tpc == nullptr) {
6051 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
6052 postcond(pc() == badAddress);
6053 return nullptr;
6054 }
6055 b(DONE);
6056
6057 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
6058 // so, if a2 == null => return false(0), else return true, so we can return a2
6059 mov(result, a2);
6060 b(DONE);
6061 bind(SHORT);
6062 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6063 ldr(tmp3, Address(a1, start_offset));
6064 ldr(tmp4, Address(a2, start_offset));
6065 bind(LAST_CHECK);
6066 eor(tmp4, tmp3, tmp4);
6067 lslv(tmp5, tmp4, tmp5);
6068 cmp(tmp5, zr);
6069 bind(CSET_EQ);
6070 cset(result, EQ);
6071 b(DONE);
6072 }
6073
6074 bind(SAME);
6075 mov(result, true);
6076 // That's it.
6077 bind(DONE);
6078
6079 BLOCK_COMMENT("} array_equals");
6080 postcond(pc() != badAddress);
6081 return pc();
6082 }
6083
6084 // Compare Strings
6085
6086 // For Strings we're passed the address of the first characters in a1
6087 // and a2 and the length in cnt1.
6088 // There are two implementations. For arrays >= 8 bytes, all
6089 // comparisons (including the final one, which may overlap) are
6090 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
6091 // halfword, then a short, and then a byte.
6092
6093 void MacroAssembler::string_equals(Register a1, Register a2,
6094 Register result, Register cnt1)
6095 {
6096 Label SAME, DONE, SHORT, NEXT_WORD;
6097 Register tmp1 = rscratch1;
6098 Register tmp2 = rscratch2;
6099
6100 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
6101
6102 #ifndef PRODUCT
6103 {
6104 char comment[64];
6105 os::snprintf_checked(comment, sizeof comment, "{string_equalsL");
6106 BLOCK_COMMENT(comment);
6107 }
6108 #endif
6109
6110 mov(result, false);
6111
6112 // Check for short strings, i.e. smaller than wordSize.
6113 subs(cnt1, cnt1, wordSize);
6114 br(Assembler::LT, SHORT);
6115 // Main 8 byte comparison loop.
6116 bind(NEXT_WORD); {
6117 ldr(tmp1, Address(post(a1, wordSize)));
6118 ldr(tmp2, Address(post(a2, wordSize)));
6119 subs(cnt1, cnt1, wordSize);
6120 eor(tmp1, tmp1, tmp2);
6121 cbnz(tmp1, DONE);
6122 } br(GT, NEXT_WORD);
6123 // Last longword. In the case where length == 4 we compare the
6124 // same longword twice, but that's still faster than another
6125 // conditional branch.
6126 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6127 // length == 4.
6128 ldr(tmp1, Address(a1, cnt1));
6129 ldr(tmp2, Address(a2, cnt1));
6130 eor(tmp2, tmp1, tmp2);
6131 cbnz(tmp2, DONE);
6132 b(SAME);
6133
6134 bind(SHORT);
6135 Label TAIL03, TAIL01;
6136
6137 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
6138 {
6139 ldrw(tmp1, Address(post(a1, 4)));
6140 ldrw(tmp2, Address(post(a2, 4)));
6141 eorw(tmp1, tmp1, tmp2);
6142 cbnzw(tmp1, DONE);
6143 }
6144 bind(TAIL03);
6145 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
6146 {
6147 ldrh(tmp1, Address(post(a1, 2)));
6148 ldrh(tmp2, Address(post(a2, 2)));
6149 eorw(tmp1, tmp1, tmp2);
6150 cbnzw(tmp1, DONE);
6151 }
6152 bind(TAIL01);
6153 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6154 {
6155 ldrb(tmp1, a1);
6156 ldrb(tmp2, a2);
6157 eorw(tmp1, tmp1, tmp2);
6158 cbnzw(tmp1, DONE);
6159 }
6160 // Arrays are equal.
6161 bind(SAME);
6162 mov(result, true);
6163
6164 // That's it.
6165 bind(DONE);
6166 BLOCK_COMMENT("} string_equals");
6167 }
6168
6169
6170 // The size of the blocks erased by the zero_blocks stub. We must
6171 // handle anything smaller than this ourselves in zero_words().
6172 const int MacroAssembler::zero_words_block_size = 8;
6173
6174 // zero_words() is used by C2 ClearArray patterns and by
6175 // C1_MacroAssembler. It is as small as possible, handling small word
6176 // counts locally and delegating anything larger to the zero_blocks
6177 // stub. It is expanded many times in compiled code, so it is
6178 // important to keep it short.
6179
6180 // ptr: Address of a buffer to be zeroed.
6181 // cnt: Count in HeapWords.
6182 //
6183 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
6184 address MacroAssembler::zero_words(Register ptr, Register cnt)
6185 {
6186 assert(is_power_of_2(zero_words_block_size), "adjust this");
6187
6188 BLOCK_COMMENT("zero_words {");
6189 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
6190 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6191 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6192
6193 subs(rscratch1, cnt, zero_words_block_size);
6194 Label around;
6195 br(LO, around);
6196 {
6197 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6198 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6199 // Make sure this is a C2 compilation. C1 allocates space only for
6200 // trampoline stubs generated by Call LIR ops, and in any case it
6201 // makes sense for a C1 compilation task to proceed as quickly as
6202 // possible.
6203 CompileTask* task;
6204 if (StubRoutines::aarch64::complete()
6205 && Thread::current()->is_Compiler_thread()
6206 && (task = ciEnv::current()->task())
6207 && is_c2_compile(task->comp_level())) {
6208 address tpc = trampoline_call(zero_blocks);
6209 if (tpc == nullptr) {
6210 DEBUG_ONLY(reset_labels(around));
6211 return nullptr;
6212 }
6213 } else {
6214 far_call(zero_blocks);
6215 }
6216 }
6217 bind(around);
6218
6219 // We have a few words left to do. zero_blocks has adjusted r10 and r11
6220 // for us.
6221 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
6222 Label l;
6223 tbz(cnt, exact_log2(i), l);
6224 for (int j = 0; j < i; j += 2) {
6225 stp(zr, zr, post(ptr, 2 * BytesPerWord));
6226 }
6227 bind(l);
6228 }
6229 {
6230 Label l;
6231 tbz(cnt, 0, l);
6232 str(zr, Address(ptr));
6233 bind(l);
6234 }
6235
6236 BLOCK_COMMENT("} zero_words");
6237 return pc();
6238 }
6239
6240 // base: Address of a buffer to be zeroed, 8 bytes aligned.
6241 // cnt: Immediate count in HeapWords.
6242 //
6243 // r10, r11, rscratch1, and rscratch2 are clobbered.
6244 address MacroAssembler::zero_words(Register base, uint64_t cnt)
6245 {
6246 assert(wordSize <= BlockZeroingLowLimit,
6247 "increase BlockZeroingLowLimit");
6248 address result = nullptr;
6249 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) {
6250 #ifndef PRODUCT
6251 {
6252 char buf[64];
6253 os::snprintf_checked(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt);
6254 BLOCK_COMMENT(buf);
6255 }
6256 #endif
6257 if (cnt >= 16) {
6258 uint64_t loops = cnt/16;
6259 if (loops > 1) {
6260 mov(rscratch2, loops - 1);
6261 }
6262 {
6263 Label loop;
6264 bind(loop);
6265 for (int i = 0; i < 16; i += 2) {
6266 stp(zr, zr, Address(base, i * BytesPerWord));
6267 }
6268 add(base, base, 16 * BytesPerWord);
6269 if (loops > 1) {
6270 subs(rscratch2, rscratch2, 1);
6271 br(GE, loop);
6272 }
6273 }
6274 }
6275 cnt %= 16;
6276 int i = cnt & 1; // store any odd word to start
6277 if (i) str(zr, Address(base));
6278 for (; i < (int)cnt; i += 2) {
6279 stp(zr, zr, Address(base, i * wordSize));
6280 }
6281 BLOCK_COMMENT("} zero_words");
6282 result = pc();
6283 } else {
6284 mov(r10, base); mov(r11, cnt);
6285 result = zero_words(r10, r11);
6286 }
6287 return result;
6288 }
6289
6290 // Zero blocks of memory by using DC ZVA.
6291 //
6292 // Aligns the base address first sufficiently for DC ZVA, then uses
6293 // DC ZVA repeatedly for every full block. cnt is the size to be
6294 // zeroed in HeapWords. Returns the count of words left to be zeroed
6295 // in cnt.
6296 //
6297 // NOTE: This is intended to be used in the zero_blocks() stub. If
6298 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
6299 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
6300 Register tmp = rscratch1;
6301 Register tmp2 = rscratch2;
6302 int zva_length = VM_Version::zva_length();
6303 Label initial_table_end, loop_zva;
6304 Label fini;
6305
6306 // Base must be 16 byte aligned. If not just return and let caller handle it
6307 tst(base, 0x0f);
6308 br(Assembler::NE, fini);
6309 // Align base with ZVA length.
6310 neg(tmp, base);
6311 andr(tmp, tmp, zva_length - 1);
6312
6313 // tmp: the number of bytes to be filled to align the base with ZVA length.
6314 add(base, base, tmp);
6315 sub(cnt, cnt, tmp, Assembler::ASR, 3);
6316 adr(tmp2, initial_table_end);
6317 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
6318 br(tmp2);
6319
6320 for (int i = -zva_length + 16; i < 0; i += 16)
6321 stp(zr, zr, Address(base, i));
6322 bind(initial_table_end);
6323
6324 sub(cnt, cnt, zva_length >> 3);
6325 bind(loop_zva);
6326 dc(Assembler::ZVA, base);
6327 subs(cnt, cnt, zva_length >> 3);
6328 add(base, base, zva_length);
6329 br(Assembler::GE, loop_zva);
6330 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
6331 bind(fini);
6332 }
6333
6334 // base: Address of a buffer to be filled, 8 bytes aligned.
6335 // cnt: Count in 8-byte unit.
6336 // value: Value to be filled with.
6337 // base will point to the end of the buffer after filling.
6338 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
6339 {
6340 // Algorithm:
6341 //
6342 // if (cnt == 0) {
6343 // return;
6344 // }
6345 // if ((p & 8) != 0) {
6346 // *p++ = v;
6347 // }
6348 //
6349 // scratch1 = cnt & 14;
6350 // cnt -= scratch1;
6351 // p += scratch1;
6352 // switch (scratch1 / 2) {
6353 // do {
6354 // cnt -= 16;
6355 // p[-16] = v;
6356 // p[-15] = v;
6357 // case 7:
6358 // p[-14] = v;
6359 // p[-13] = v;
6360 // case 6:
6361 // p[-12] = v;
6362 // p[-11] = v;
6363 // // ...
6364 // case 1:
6365 // p[-2] = v;
6366 // p[-1] = v;
6367 // case 0:
6368 // p += 16;
6369 // } while (cnt);
6370 // }
6371 // if ((cnt & 1) == 1) {
6372 // *p++ = v;
6373 // }
6374
6375 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
6376
6377 Label fini, skip, entry, loop;
6378 const int unroll = 8; // Number of stp instructions we'll unroll
6379
6380 cbz(cnt, fini);
6381 tbz(base, 3, skip);
6382 str(value, Address(post(base, 8)));
6383 sub(cnt, cnt, 1);
6384 bind(skip);
6385
6386 andr(rscratch1, cnt, (unroll-1) * 2);
6387 sub(cnt, cnt, rscratch1);
6388 add(base, base, rscratch1, Assembler::LSL, 3);
6389 adr(rscratch2, entry);
6390 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
6391 br(rscratch2);
6392
6393 bind(loop);
6394 add(base, base, unroll * 16);
6395 for (int i = -unroll; i < 0; i++)
6396 stp(value, value, Address(base, i * 16));
6397 bind(entry);
6398 subs(cnt, cnt, unroll * 2);
6399 br(Assembler::GE, loop);
6400
6401 tbz(cnt, 0, fini);
6402 str(value, Address(post(base, 8)));
6403 bind(fini);
6404 }
6405
6406 // Intrinsic for
6407 //
6408 // - sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6409 // Encodes char[] to byte[] in ISO-8859-1
6410 //
6411 // - java.lang.StringCoding#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6412 // Encodes byte[] (containing UTF-16) to byte[] in ISO-8859-1
6413 //
6414 // - java.lang.StringCoding#encodeAsciiArray0(char[] sa, int sp, byte[] da, int dp, int len)
6415 // Encodes char[] to byte[] in ASCII
6416 //
6417 // This version always returns the number of characters copied, and does not
6418 // clobber the 'len' register. A successful copy will complete with the post-
6419 // condition: 'res' == 'len', while an unsuccessful copy will exit with the
6420 // post-condition: 0 <= 'res' < 'len'.
6421 //
6422 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
6423 // degrade performance (on Ampere Altra - Neoverse N1), to an extent
6424 // beyond the acceptable, even though the footprint would be smaller.
6425 // Using 'umaxv' in the ASCII-case comes with a small penalty but does
6426 // avoid additional bloat.
6427 //
6428 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags
6429 void MacroAssembler::encode_iso_array(Register src, Register dst,
6430 Register len, Register res, bool ascii,
6431 FloatRegister vtmp0, FloatRegister vtmp1,
6432 FloatRegister vtmp2, FloatRegister vtmp3,
6433 FloatRegister vtmp4, FloatRegister vtmp5)
6434 {
6435 Register cnt = res;
6436 Register max = rscratch1;
6437 Register chk = rscratch2;
6438
6439 prfm(Address(src), PLDL1STRM);
6440 movw(cnt, len);
6441
6442 #define ASCII(insn) do { if (ascii) { insn; } } while (0)
6443
6444 Label LOOP_32, DONE_32, FAIL_32;
6445
6446 BIND(LOOP_32);
6447 {
6448 cmpw(cnt, 32);
6449 br(LT, DONE_32);
6450 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
6451 // Extract lower bytes.
6452 FloatRegister vlo0 = vtmp4;
6453 FloatRegister vlo1 = vtmp5;
6454 uzp1(vlo0, T16B, vtmp0, vtmp1);
6455 uzp1(vlo1, T16B, vtmp2, vtmp3);
6456 // Merge bits...
6457 orr(vtmp0, T16B, vtmp0, vtmp1);
6458 orr(vtmp2, T16B, vtmp2, vtmp3);
6459 // Extract merged upper bytes.
6460 FloatRegister vhix = vtmp0;
6461 uzp2(vhix, T16B, vtmp0, vtmp2);
6462 // ISO-check on hi-parts (all zero).
6463 // ASCII-check on lo-parts (no sign).
6464 FloatRegister vlox = vtmp1; // Merge lower bytes.
6465 ASCII(orr(vlox, T16B, vlo0, vlo1));
6466 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox));
6467 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox));
6468 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0));
6469 ASCII(orr(chk, chk, max));
6470 cbnz(chk, FAIL_32);
6471 subw(cnt, cnt, 32);
6472 st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
6473 b(LOOP_32);
6474 }
6475 BIND(FAIL_32);
6476 sub(src, src, 64);
6477 BIND(DONE_32);
6478
6479 Label LOOP_8, SKIP_8;
6480
6481 BIND(LOOP_8);
6482 {
6483 cmpw(cnt, 8);
6484 br(LT, SKIP_8);
6485 FloatRegister vhi = vtmp0;
6486 FloatRegister vlo = vtmp1;
6487 ld1(vtmp3, T8H, src);
6488 uzp1(vlo, T16B, vtmp3, vtmp3);
6489 uzp2(vhi, T16B, vtmp3, vtmp3);
6490 // ISO-check on hi-parts (all zero).
6491 // ASCII-check on lo-parts (no sign).
6492 ASCII(cm(LT, vtmp2, T16B, vlo));
6493 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2));
6494 ASCII(umov(max, vtmp2, B, 0));
6495 ASCII(orr(chk, chk, max));
6496 cbnz(chk, SKIP_8);
6497
6498 strd(vlo, Address(post(dst, 8)));
6499 subw(cnt, cnt, 8);
6500 add(src, src, 16);
6501 b(LOOP_8);
6502 }
6503 BIND(SKIP_8);
6504
6505 #undef ASCII
6506
6507 Label LOOP, DONE;
6508
6509 cbz(cnt, DONE);
6510 BIND(LOOP);
6511 {
6512 Register chr = rscratch1;
6513 ldrh(chr, Address(post(src, 2)));
6514 tst(chr, ascii ? 0xff80 : 0xff00);
6515 br(NE, DONE);
6516 strb(chr, Address(post(dst, 1)));
6517 subs(cnt, cnt, 1);
6518 br(GT, LOOP);
6519 }
6520 BIND(DONE);
6521 // Return index where we stopped.
6522 subw(res, len, cnt);
6523 }
6524
6525 // Inflate byte[] array to char[].
6526 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6
6527 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
6528 FloatRegister vtmp1, FloatRegister vtmp2,
6529 FloatRegister vtmp3, Register tmp4) {
6530 Label big, done, after_init, to_stub;
6531
6532 assert_different_registers(src, dst, len, tmp4, rscratch1);
6533
6534 fmovd(vtmp1, 0.0);
6535 lsrw(tmp4, len, 3);
6536 bind(after_init);
6537 cbnzw(tmp4, big);
6538 // Short string: less than 8 bytes.
6539 {
6540 Label loop, tiny;
6541
6542 cmpw(len, 4);
6543 br(LT, tiny);
6544 // Use SIMD to do 4 bytes.
6545 ldrs(vtmp2, post(src, 4));
6546 zip1(vtmp3, T8B, vtmp2, vtmp1);
6547 subw(len, len, 4);
6548 strd(vtmp3, post(dst, 8));
6549
6550 cbzw(len, done);
6551
6552 // Do the remaining bytes by steam.
6553 bind(loop);
6554 ldrb(tmp4, post(src, 1));
6555 strh(tmp4, post(dst, 2));
6556 subw(len, len, 1);
6557
6558 bind(tiny);
6559 cbnz(len, loop);
6560
6561 b(done);
6562 }
6563
6564 if (SoftwarePrefetchHintDistance >= 0) {
6565 bind(to_stub);
6566 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
6567 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated");
6568 address tpc = trampoline_call(stub);
6569 if (tpc == nullptr) {
6570 DEBUG_ONLY(reset_labels(big, done));
6571 postcond(pc() == badAddress);
6572 return nullptr;
6573 }
6574 b(after_init);
6575 }
6576
6577 // Unpack the bytes 8 at a time.
6578 bind(big);
6579 {
6580 Label loop, around, loop_last, loop_start;
6581
6582 if (SoftwarePrefetchHintDistance >= 0) {
6583 const int large_loop_threshold = (64 + 16)/8;
6584 ldrd(vtmp2, post(src, 8));
6585 andw(len, len, 7);
6586 cmp(tmp4, (u1)large_loop_threshold);
6587 br(GE, to_stub);
6588 b(loop_start);
6589
6590 bind(loop);
6591 ldrd(vtmp2, post(src, 8));
6592 bind(loop_start);
6593 subs(tmp4, tmp4, 1);
6594 br(EQ, loop_last);
6595 zip1(vtmp2, T16B, vtmp2, vtmp1);
6596 ldrd(vtmp3, post(src, 8));
6597 st1(vtmp2, T8H, post(dst, 16));
6598 subs(tmp4, tmp4, 1);
6599 zip1(vtmp3, T16B, vtmp3, vtmp1);
6600 st1(vtmp3, T8H, post(dst, 16));
6601 br(NE, loop);
6602 b(around);
6603 bind(loop_last);
6604 zip1(vtmp2, T16B, vtmp2, vtmp1);
6605 st1(vtmp2, T8H, post(dst, 16));
6606 bind(around);
6607 cbz(len, done);
6608 } else {
6609 andw(len, len, 7);
6610 bind(loop);
6611 ldrd(vtmp2, post(src, 8));
6612 sub(tmp4, tmp4, 1);
6613 zip1(vtmp3, T16B, vtmp2, vtmp1);
6614 st1(vtmp3, T8H, post(dst, 16));
6615 cbnz(tmp4, loop);
6616 }
6617 }
6618
6619 // Do the tail of up to 8 bytes.
6620 add(src, src, len);
6621 ldrd(vtmp3, Address(src, -8));
6622 add(dst, dst, len, ext::uxtw, 1);
6623 zip1(vtmp3, T16B, vtmp3, vtmp1);
6624 strq(vtmp3, Address(dst, -16));
6625
6626 bind(done);
6627 postcond(pc() != badAddress);
6628 return pc();
6629 }
6630
6631 // Compress char[] array to byte[].
6632 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
6633 // Return the array length if every element in array can be encoded,
6634 // otherwise, the index of first non-latin1 (> 0xff) character.
6635 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
6636 Register res,
6637 FloatRegister tmp0, FloatRegister tmp1,
6638 FloatRegister tmp2, FloatRegister tmp3,
6639 FloatRegister tmp4, FloatRegister tmp5) {
6640 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
6641 }
6642
6643 // java.math.round(double a)
6644 // Returns the closest long to the argument, with ties rounding to
6645 // positive infinity. This requires some fiddling for corner
6646 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5).
6647 void MacroAssembler::java_round_double(Register dst, FloatRegister src,
6648 FloatRegister ftmp) {
6649 Label DONE;
6650 BLOCK_COMMENT("java_round_double: { ");
6651 fmovd(rscratch1, src);
6652 // Use RoundToNearestTiesAway unless src small and -ve.
6653 fcvtasd(dst, src);
6654 // Test if src >= 0 || abs(src) >= 0x1.0p52
6655 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit
6656 mov(rscratch2, julong_cast(0x1.0p52));
6657 cmp(rscratch1, rscratch2);
6658 br(HS, DONE); {
6659 // src < 0 && abs(src) < 0x1.0p52
6660 // src may have a fractional part, so add 0.5
6661 fmovd(ftmp, 0.5);
6662 faddd(ftmp, src, ftmp);
6663 // Convert double to jlong, use RoundTowardsNegative
6664 fcvtmsd(dst, ftmp);
6665 }
6666 bind(DONE);
6667 BLOCK_COMMENT("} java_round_double");
6668 }
6669
6670 void MacroAssembler::java_round_float(Register dst, FloatRegister src,
6671 FloatRegister ftmp) {
6672 Label DONE;
6673 BLOCK_COMMENT("java_round_float: { ");
6674 fmovs(rscratch1, src);
6675 // Use RoundToNearestTiesAway unless src small and -ve.
6676 fcvtassw(dst, src);
6677 // Test if src >= 0 || abs(src) >= 0x1.0p23
6678 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit
6679 mov(rscratch2, jint_cast(0x1.0p23f));
6680 cmp(rscratch1, rscratch2);
6681 br(HS, DONE); {
6682 // src < 0 && |src| < 0x1.0p23
6683 // src may have a fractional part, so add 0.5
6684 fmovs(ftmp, 0.5f);
6685 fadds(ftmp, src, ftmp);
6686 // Convert float to jint, use RoundTowardsNegative
6687 fcvtmssw(dst, ftmp);
6688 }
6689 bind(DONE);
6690 BLOCK_COMMENT("} java_round_float");
6691 }
6692
6693 // get_thread() can be called anywhere inside generated code so we
6694 // need to save whatever non-callee save context might get clobbered
6695 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
6696 // the call setup code.
6697 //
6698 // On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags.
6699 // On other systems, the helper is a usual C function.
6700 //
6701 void MacroAssembler::get_thread(Register dst) {
6702 RegSet saved_regs =
6703 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6704 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6705
6706 protect_return_address();
6707 push(saved_regs, sp);
6708
6709 mov(lr, ExternalAddress(CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)));
6710 blr(lr);
6711 if (dst != c_rarg0) {
6712 mov(dst, c_rarg0);
6713 }
6714
6715 pop(saved_regs, sp);
6716 authenticate_return_address();
6717 }
6718
6719 void MacroAssembler::cache_wb(Address line) {
6720 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6721 assert(line.index() == noreg, "index should be noreg");
6722 assert(line.offset() == 0, "offset should be 0");
6723 // would like to assert this
6724 // assert(line._ext.shift == 0, "shift should be zero");
6725 if (VM_Version::supports_dcpop()) {
6726 // writeback using clear virtual address to point of persistence
6727 dc(Assembler::CVAP, line.base());
6728 } else {
6729 // no need to generate anything as Unsafe.writebackMemory should
6730 // never invoke this stub
6731 }
6732 }
6733
6734 void MacroAssembler::cache_wbsync(bool is_pre) {
6735 // we only need a barrier post sync
6736 if (!is_pre) {
6737 membar(Assembler::AnyAny);
6738 }
6739 }
6740
6741 void MacroAssembler::verify_sve_vector_length(Register tmp) {
6742 if (!UseSVE || VM_Version::get_max_supported_sve_vector_length() == FloatRegister::sve_vl_min) {
6743 return;
6744 }
6745 // Make sure that native code does not change SVE vector length.
6746 Label verify_ok;
6747 movw(tmp, zr);
6748 sve_inc(tmp, B);
6749 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length());
6750 br(EQ, verify_ok);
6751 stop("Error: SVE vector length has changed since jvm startup");
6752 bind(verify_ok);
6753 }
6754
6755 void MacroAssembler::verify_ptrue() {
6756 Label verify_ok;
6757 if (!UseSVE) {
6758 return;
6759 }
6760 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
6761 sve_dec(rscratch1, B);
6762 cbz(rscratch1, verify_ok);
6763 stop("Error: the preserved predicate register (p7) elements are not all true");
6764 bind(verify_ok);
6765 }
6766
6767 void MacroAssembler::safepoint_isb() {
6768 isb();
6769 #ifndef PRODUCT
6770 if (VerifyCrossModifyFence) {
6771 // Clear the thread state.
6772 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6773 }
6774 #endif
6775 }
6776
6777 #ifndef PRODUCT
6778 void MacroAssembler::verify_cross_modify_fence_not_required() {
6779 if (VerifyCrossModifyFence) {
6780 // Check if thread needs a cross modify fence.
6781 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6782 Label fence_not_required;
6783 cbz(rscratch1, fence_not_required);
6784 // If it does then fail.
6785 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure)));
6786 mov(c_rarg0, rthread);
6787 blr(rscratch1);
6788 bind(fence_not_required);
6789 }
6790 }
6791 #endif
6792
6793 void MacroAssembler::spin_wait() {
6794 block_comment("spin_wait {");
6795 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
6796 switch (VM_Version::spin_wait_desc().inst()) {
6797 case SpinWait::NOP:
6798 nop();
6799 break;
6800 case SpinWait::ISB:
6801 isb();
6802 break;
6803 case SpinWait::YIELD:
6804 yield();
6805 break;
6806 case SpinWait::SB:
6807 assert(VM_Version::supports_sb(), "current CPU does not support SB instruction");
6808 sb();
6809 break;
6810 case SpinWait::WFET:
6811 spin_wait_wfet(VM_Version::spin_wait_desc().delay());
6812 break;
6813 default:
6814 ShouldNotReachHere();
6815 }
6816 }
6817 block_comment("}");
6818 }
6819
6820 void MacroAssembler::spin_wait_wfet(int delay_ns) {
6821 // The sequence assumes CNTFRQ_EL0 is fixed to 1GHz. The assumption is valid
6822 // starting from Armv8.6, according to the "D12.1.2 The system counter" of the
6823 // Arm Architecture Reference Manual for A-profile architecture version M.a.a.
6824 // This is sufficient because FEAT_WFXT is introduced from Armv8.6.
6825 Register target = rscratch1;
6826 Register current = rscratch2;
6827 get_cntvctss_el0(current);
6828 add(target, current, delay_ns);
6829
6830 Label L_wait_loop;
6831 bind(L_wait_loop);
6832
6833 wfet(target);
6834 get_cntvctss_el0(current);
6835
6836 cmp(current, target);
6837 br(LT, L_wait_loop);
6838
6839 sb();
6840 }
6841
6842 // Stack frame creation/removal
6843
6844 void MacroAssembler::enter(bool strip_ret_addr) {
6845 if (strip_ret_addr) {
6846 // Addresses can only be signed once. If there are multiple nested frames being created
6847 // in the same function, then the return address needs stripping first.
6848 strip_return_address();
6849 }
6850 protect_return_address();
6851 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6852 mov(rfp, sp);
6853 }
6854
6855 void MacroAssembler::leave() {
6856 mov(sp, rfp);
6857 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6858 authenticate_return_address();
6859 }
6860
6861 // ROP Protection
6862 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/
6863 // destroying stack frames or whenever directly loading/storing the LR to memory.
6864 // If ROP protection is not set then these functions are no-ops.
6865 // For more details on PAC see pauth_aarch64.hpp.
6866
6867 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory.
6868 // Uses value zero as the modifier.
6869 //
6870 void MacroAssembler::protect_return_address() {
6871 if (VM_Version::use_rop_protection()) {
6872 check_return_address();
6873 paciaz();
6874 }
6875 }
6876
6877 // Sign the return value in the given register. Use before updating the LR in the existing stack
6878 // frame for the current function.
6879 // Uses value zero as the modifier.
6880 //
6881 void MacroAssembler::protect_return_address(Register return_reg) {
6882 if (VM_Version::use_rop_protection()) {
6883 check_return_address(return_reg);
6884 paciza(return_reg);
6885 }
6886 }
6887
6888 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory.
6889 // Uses value zero as the modifier.
6890 //
6891 void MacroAssembler::authenticate_return_address() {
6892 if (VM_Version::use_rop_protection()) {
6893 autiaz();
6894 check_return_address();
6895 }
6896 }
6897
6898 // Authenticate the return value in the given register. Use before updating the LR in the existing
6899 // stack frame for the current function.
6900 // Uses value zero as the modifier.
6901 //
6902 void MacroAssembler::authenticate_return_address(Register return_reg) {
6903 if (VM_Version::use_rop_protection()) {
6904 autiza(return_reg);
6905 check_return_address(return_reg);
6906 }
6907 }
6908
6909 // Strip any PAC data from LR without performing any authentication. Use with caution - only if
6910 // there is no guaranteed way of authenticating the LR.
6911 //
6912 void MacroAssembler::strip_return_address() {
6913 if (VM_Version::use_rop_protection()) {
6914 xpaclri();
6915 }
6916 }
6917
6918 #ifndef PRODUCT
6919 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only
6920 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point
6921 // it is difficult to debug back to the callee function.
6922 // This function simply loads from the address in the given register.
6923 // Use directly after authentication to catch authentication failures.
6924 // Also use before signing to check that the pointer is valid and hasn't already been signed.
6925 //
6926 void MacroAssembler::check_return_address(Register return_reg) {
6927 if (VM_Version::use_rop_protection()) {
6928 ldr(zr, Address(return_reg));
6929 }
6930 }
6931 #endif
6932
6933 // The java_calling_convention describes stack locations as ideal slots on
6934 // a frame with no abi restrictions. Since we must observe abi restrictions
6935 // (like the placement of the register window) the slots must be biased by
6936 // the following value.
6937 static int reg2offset_in(VMReg r) {
6938 // Account for saved rfp and lr
6939 // This should really be in_preserve_stack_slots
6940 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
6941 }
6942
6943 static int reg2offset_out(VMReg r) {
6944 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
6945 }
6946
6947 // On 64bit we will store integer like items to the stack as
6948 // 64bits items (AArch64 ABI) even though java would only store
6949 // 32bits for a parameter. On 32bit it will simply be 32bits
6950 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
6951 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
6952 if (src.first()->is_stack()) {
6953 if (dst.first()->is_stack()) {
6954 // stack to stack
6955 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6956 str(tmp, Address(sp, reg2offset_out(dst.first())));
6957 } else {
6958 // stack to reg
6959 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
6960 }
6961 } else if (dst.first()->is_stack()) {
6962 // reg to stack
6963 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
6964 } else {
6965 if (dst.first() != src.first()) {
6966 sxtw(dst.first()->as_Register(), src.first()->as_Register());
6967 }
6968 }
6969 }
6970
6971 // An oop arg. Must pass a handle not the oop itself
6972 void MacroAssembler::object_move(
6973 OopMap* map,
6974 int oop_handle_offset,
6975 int framesize_in_slots,
6976 VMRegPair src,
6977 VMRegPair dst,
6978 bool is_receiver,
6979 int* receiver_offset) {
6980
6981 // must pass a handle. First figure out the location we use as a handle
6982
6983 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register();
6984
6985 // See if oop is null if it is we need no handle
6986
6987 if (src.first()->is_stack()) {
6988
6989 // Oop is already on the stack as an argument
6990 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
6991 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
6992 if (is_receiver) {
6993 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
6994 }
6995
6996 ldr(rscratch1, Address(rfp, reg2offset_in(src.first())));
6997 lea(rHandle, Address(rfp, reg2offset_in(src.first())));
6998 // conditionally move a null
6999 cmp(rscratch1, zr);
7000 csel(rHandle, zr, rHandle, Assembler::EQ);
7001 } else {
7002
7003 // Oop is in an a register we must store it to the space we reserve
7004 // on the stack for oop_handles and pass a handle if oop is non-null
7005
7006 const Register rOop = src.first()->as_Register();
7007 int oop_slot;
7008 if (rOop == j_rarg0)
7009 oop_slot = 0;
7010 else if (rOop == j_rarg1)
7011 oop_slot = 1;
7012 else if (rOop == j_rarg2)
7013 oop_slot = 2;
7014 else if (rOop == j_rarg3)
7015 oop_slot = 3;
7016 else if (rOop == j_rarg4)
7017 oop_slot = 4;
7018 else if (rOop == j_rarg5)
7019 oop_slot = 5;
7020 else if (rOop == j_rarg6)
7021 oop_slot = 6;
7022 else {
7023 assert(rOop == j_rarg7, "wrong register");
7024 oop_slot = 7;
7025 }
7026
7027 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
7028 int offset = oop_slot*VMRegImpl::stack_slot_size;
7029
7030 map->set_oop(VMRegImpl::stack2reg(oop_slot));
7031 // Store oop in handle area, may be null
7032 str(rOop, Address(sp, offset));
7033 if (is_receiver) {
7034 *receiver_offset = offset;
7035 }
7036
7037 cmp(rOop, zr);
7038 lea(rHandle, Address(sp, offset));
7039 // conditionally move a null
7040 csel(rHandle, zr, rHandle, Assembler::EQ);
7041 }
7042
7043 // If arg is on the stack then place it otherwise it is already in correct reg.
7044 if (dst.first()->is_stack()) {
7045 str(rHandle, Address(sp, reg2offset_out(dst.first())));
7046 }
7047 }
7048
7049 // A float arg may have to do float reg int reg conversion
7050 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
7051 if (src.first()->is_stack()) {
7052 if (dst.first()->is_stack()) {
7053 ldrw(tmp, Address(rfp, reg2offset_in(src.first())));
7054 strw(tmp, Address(sp, reg2offset_out(dst.first())));
7055 } else {
7056 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7057 }
7058 } else if (src.first() != dst.first()) {
7059 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7060 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7061 else
7062 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7063 }
7064 }
7065
7066 // A long move
7067 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
7068 if (src.first()->is_stack()) {
7069 if (dst.first()->is_stack()) {
7070 // stack to stack
7071 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7072 str(tmp, Address(sp, reg2offset_out(dst.first())));
7073 } else {
7074 // stack to reg
7075 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
7076 }
7077 } else if (dst.first()->is_stack()) {
7078 // reg to stack
7079 // Do we really have to sign extend???
7080 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
7081 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
7082 } else {
7083 if (dst.first() != src.first()) {
7084 mov(dst.first()->as_Register(), src.first()->as_Register());
7085 }
7086 }
7087 }
7088
7089
7090 // A double move
7091 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
7092 if (src.first()->is_stack()) {
7093 if (dst.first()->is_stack()) {
7094 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7095 str(tmp, Address(sp, reg2offset_out(dst.first())));
7096 } else {
7097 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7098 }
7099 } else if (src.first() != dst.first()) {
7100 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7101 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7102 else
7103 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7104 }
7105 }
7106
7107 // Implements fast-locking.
7108 //
7109 // - obj: the object to be locked
7110 // - t1, t2, t3: temporary registers, will be destroyed
7111 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding).
7112 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow) {
7113 assert_different_registers(basic_lock, obj, t1, t2, t3, rscratch1);
7114
7115 Label push;
7116 const Register top = t1;
7117 const Register mark = t2;
7118 const Register t = t3;
7119
7120 // Preload the markWord. It is important that this is the first
7121 // instruction emitted as it is part of C1's null check semantics.
7122 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7123
7124 if (UseObjectMonitorTable) {
7125 // Clear cache in case fast locking succeeds or we need to take the slow-path.
7126 str(zr, Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))));
7127 }
7128
7129 if (DiagnoseSyncOnValueBasedClasses != 0) {
7130 load_klass(t1, obj);
7131 ldrb(t1, Address(t1, Klass::misc_flags_offset()));
7132 tst(t1, KlassFlags::_misc_is_value_based_class);
7133 br(Assembler::NE, slow);
7134 }
7135
7136 // Check if the lock-stack is full.
7137 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7138 cmpw(top, (unsigned)LockStack::end_offset());
7139 br(Assembler::GE, slow);
7140
7141 // Check for recursion.
7142 subw(t, top, oopSize);
7143 ldr(t, Address(rthread, t));
7144 cmp(obj, t);
7145 br(Assembler::EQ, push);
7146
7147 // Check header for monitor (0b10).
7148 tst(mark, markWord::monitor_value);
7149 br(Assembler::NE, slow);
7150
7151 // Try to lock. Transition lock bits 0b01 => 0b00
7152 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7153 orr(mark, mark, markWord::unlocked_value);
7154 eor(t, mark, markWord::unlocked_value);
7155 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
7156 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
7157 br(Assembler::NE, slow);
7158
7159 bind(push);
7160 // After successful lock, push object on lock-stack.
7161 str(obj, Address(rthread, top));
7162 addw(top, top, oopSize);
7163 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7164 }
7165
7166 // Implements fast-unlocking.
7167 //
7168 // - obj: the object to be unlocked
7169 // - t1, t2, t3: temporary registers
7170 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
7171 void MacroAssembler::fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
7172 // cmpxchg clobbers rscratch1.
7173 assert_different_registers(obj, t1, t2, t3, rscratch1);
7174
7175 #ifdef ASSERT
7176 {
7177 // Check for lock-stack underflow.
7178 Label stack_ok;
7179 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
7180 cmpw(t1, (unsigned)LockStack::start_offset());
7181 br(Assembler::GE, stack_ok);
7182 STOP("Lock-stack underflow");
7183 bind(stack_ok);
7184 }
7185 #endif
7186
7187 Label unlocked, push_and_slow;
7188 const Register top = t1;
7189 const Register mark = t2;
7190 const Register t = t3;
7191
7192 // Check if obj is top of lock-stack.
7193 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7194 subw(top, top, oopSize);
7195 ldr(t, Address(rthread, top));
7196 cmp(obj, t);
7197 br(Assembler::NE, slow);
7198
7199 // Pop lock-stack.
7200 DEBUG_ONLY(str(zr, Address(rthread, top));)
7201 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7202
7203 // Check if recursive.
7204 subw(t, top, oopSize);
7205 ldr(t, Address(rthread, t));
7206 cmp(obj, t);
7207 br(Assembler::EQ, unlocked);
7208
7209 // Not recursive. Check header for monitor (0b10).
7210 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7211 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow);
7212
7213 #ifdef ASSERT
7214 // Check header not unlocked (0b01).
7215 Label not_unlocked;
7216 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked);
7217 stop("fast_unlock already unlocked");
7218 bind(not_unlocked);
7219 #endif
7220
7221 // Try to unlock. Transition lock bits 0b00 => 0b01
7222 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7223 orr(t, mark, markWord::unlocked_value);
7224 cmpxchg(obj, mark, t, Assembler::xword,
7225 /*acquire*/ false, /*release*/ true, /*weak*/ false, noreg);
7226 br(Assembler::EQ, unlocked);
7227
7228 bind(push_and_slow);
7229 // Restore lock-stack and handle the unlock in runtime.
7230 DEBUG_ONLY(str(obj, Address(rthread, top));)
7231 addw(top, top, oopSize);
7232 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7233 b(slow);
7234
7235 bind(unlocked);
7236 }