1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "ci/ciEnv.hpp"
29 #include "code/compiledIC.hpp"
30 #include "compiler/compileTask.hpp"
31 #include "compiler/disassembler.hpp"
32 #include "compiler/oopMap.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/cardTableBarrierSet.hpp"
36 #include "gc/shared/cardTable.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/tlab_globals.hpp"
39 #include "interpreter/bytecodeHistogram.hpp"
40 #include "interpreter/interpreter.hpp"
41 #include "interpreter/interpreterRuntime.hpp"
42 #include "jvm.h"
43 #include "memory/resourceArea.hpp"
44 #include "memory/universe.hpp"
45 #include "nativeInst_aarch64.hpp"
46 #include "oops/accessDecorators.hpp"
47 #include "oops/compressedKlass.inline.hpp"
48 #include "oops/compressedOops.inline.hpp"
49 #include "oops/klass.inline.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/icache.hpp"
52 #include "runtime/interfaceSupport.inline.hpp"
53 #include "runtime/javaThread.hpp"
54 #include "runtime/jniHandles.inline.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/globalDefinitions.hpp"
58 #include "utilities/powerOfTwo.hpp"
59 #ifdef COMPILER1
60 #include "c1/c1_LIRAssembler.hpp"
61 #endif
62 #ifdef COMPILER2
63 #include "oops/oop.hpp"
64 #include "opto/compile.hpp"
65 #include "opto/node.hpp"
66 #include "opto/output.hpp"
67 #endif
68
69 #include <sys/types.h>
70
71 #ifdef PRODUCT
72 #define BLOCK_COMMENT(str) /* nothing */
73 #else
74 #define BLOCK_COMMENT(str) block_comment(str)
75 #endif
76 #define STOP(str) stop(str);
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
79 #ifdef ASSERT
80 extern "C" void disnm(intptr_t p);
81 #endif
82 // Target-dependent relocation processing
83 //
84 // Instruction sequences whose target may need to be retrieved or
85 // patched are distinguished by their leading instruction, sorting
86 // them into three main instruction groups and related subgroups.
87 //
88 // 1) Branch, Exception and System (insn count = 1)
89 // 1a) Unconditional branch (immediate):
90 // b/bl imm19
91 // 1b) Compare & branch (immediate):
92 // cbz/cbnz Rt imm19
93 // 1c) Test & branch (immediate):
94 // tbz/tbnz Rt imm14
95 // 1d) Conditional branch (immediate):
96 // b.cond imm19
97 //
98 // 2) Loads and Stores (insn count = 1)
99 // 2a) Load register literal:
100 // ldr Rt imm19
101 //
102 // 3) Data Processing Immediate (insn count = 2 or 3)
103 // 3a) PC-rel. addressing
104 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12
105 // adr/adrp Rx imm21; add Ry Rx #imm12
106 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page]
107 // adr/adrp Rx imm21
108 // adr/adrp Rx imm21; movk Rx #imm16<<32
109 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page
110 // The latter form can only happen when the target is an
111 // ExternalAddress, and (by definition) ExternalAddresses don't
112 // move. Because of that property, there is never any need to
113 // patch the last of the three instructions. However,
114 // MacroAssembler::target_addr_for_insn takes all three
115 // instructions into account and returns the correct address.
116 // 3b) Move wide (immediate)
117 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32;
118 //
119 // A switch on a subset of the instruction's bits provides an
120 // efficient dispatch to these subcases.
121 //
122 // insn[28:26] -> main group ('x' == don't care)
123 // 00x -> UNALLOCATED
124 // 100 -> Data Processing Immediate
125 // 101 -> Branch, Exception and System
126 // x1x -> Loads and Stores
127 //
128 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care).
129 // n.b. in some cases extra bits need to be checked to verify the
130 // instruction is as expected
131 //
132 // 1) ... xx101x Branch, Exception and System
133 // 1a) 00___x Unconditional branch (immediate)
134 // 1b) 01___0 Compare & branch (immediate)
135 // 1c) 01___1 Test & branch (immediate)
136 // 1d) 10___0 Conditional branch (immediate)
137 // other Should not happen
138 //
139 // 2) ... xxx1x0 Loads and Stores
140 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0)
141 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0)
142 // strictly should be 64 bit non-FP/SIMD i.e.
143 // 0101_000 (i.e. requires insn[31:24] == 01011000)
144 //
145 // 3) ... xx100x Data Processing Immediate
146 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0)
147 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01)
148 // strictly should be 64 bit movz #imm16<<0
149 // 110___10100 (i.e. requires insn[31:21] == 11010010100)
150 //
151
152 static uint32_t insn_at(address insn_addr, int n) {
153 return ((uint32_t*)insn_addr)[n];
154 }
155
156 template<typename T>
157 class RelocActions : public AllStatic {
158
159 public:
160
161 static int ALWAYSINLINE run(address insn_addr, address &target) {
162 int instructions = 1;
163 uint32_t insn = insn_at(insn_addr, 0);
164
165 uint32_t dispatch = Instruction_aarch64::extract(insn, 30, 25);
166 switch(dispatch) {
167 case 0b001010:
168 case 0b001011: {
169 instructions = T::unconditionalBranch(insn_addr, target);
170 break;
171 }
172 case 0b101010: // Conditional branch (immediate)
173 case 0b011010: { // Compare & branch (immediate)
174 instructions = T::conditionalBranch(insn_addr, target);
175 break;
176 }
177 case 0b011011: {
178 instructions = T::testAndBranch(insn_addr, target);
179 break;
180 }
181 case 0b001100:
182 case 0b001110:
183 case 0b011100:
184 case 0b011110:
185 case 0b101100:
186 case 0b101110:
187 case 0b111100:
188 case 0b111110: {
189 // load/store
190 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
191 // Load register (literal)
192 instructions = T::loadStore(insn_addr, target);
193 break;
194 } else {
195 // nothing to do
196 assert(target == nullptr, "did not expect to relocate target for polling page load");
197 }
198 break;
199 }
200 case 0b001000:
201 case 0b011000:
202 case 0b101000:
203 case 0b111000: {
204 // adr/adrp
205 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
206 int shift = Instruction_aarch64::extract(insn, 31, 31);
207 if (shift) {
208 uint32_t insn2 = insn_at(insn_addr, 1);
209 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
210 Instruction_aarch64::extract(insn, 4, 0) ==
211 Instruction_aarch64::extract(insn2, 9, 5)) {
212 instructions = T::adrp(insn_addr, target, T::adrpMem);
213 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
214 Instruction_aarch64::extract(insn, 4, 0) ==
215 Instruction_aarch64::extract(insn2, 4, 0)) {
216 instructions = T::adrp(insn_addr, target, T::adrpAdd);
217 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
218 Instruction_aarch64::extract(insn, 4, 0) ==
219 Instruction_aarch64::extract(insn2, 4, 0)) {
220 instructions = T::adrp(insn_addr, target, T::adrpMovk);
221 } else {
222 ShouldNotReachHere();
223 }
224 } else {
225 instructions = T::adr(insn_addr, target);
226 }
227 break;
228 }
229 case 0b001001:
230 case 0b011001:
231 case 0b101001:
232 case 0b111001: {
233 instructions = T::immediate(insn_addr, target);
234 break;
235 }
236 default: {
237 ShouldNotReachHere();
238 }
239 }
240
241 T::verify(insn_addr, target);
242 return instructions * NativeInstruction::instruction_size;
243 }
244 };
245
246 class Patcher : public AllStatic {
247 public:
248 static int unconditionalBranch(address insn_addr, address &target) {
249 intptr_t offset = (target - insn_addr) >> 2;
250 Instruction_aarch64::spatch(insn_addr, 25, 0, offset);
251 return 1;
252 }
253 static int conditionalBranch(address insn_addr, address &target) {
254 intptr_t offset = (target - insn_addr) >> 2;
255 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
256 return 1;
257 }
258 static int testAndBranch(address insn_addr, address &target) {
259 intptr_t offset = (target - insn_addr) >> 2;
260 Instruction_aarch64::spatch(insn_addr, 18, 5, offset);
261 return 1;
262 }
263 static int loadStore(address insn_addr, address &target) {
264 intptr_t offset = (target - insn_addr) >> 2;
265 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
266 return 1;
267 }
268 static int adr(address insn_addr, address &target) {
269 #ifdef ASSERT
270 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
271 #endif
272 // PC-rel. addressing
273 ptrdiff_t offset = target - insn_addr;
274 int offset_lo = offset & 3;
275 offset >>= 2;
276 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
277 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
278 return 1;
279 }
280 template<typename U>
281 static int adrp(address insn_addr, address &target, U inner) {
282 int instructions = 1;
283 #ifdef ASSERT
284 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
285 #endif
286 ptrdiff_t offset = target - insn_addr;
287 instructions = 2;
288 precond(inner != nullptr);
289 // Give the inner reloc a chance to modify the target.
290 address adjusted_target = target;
291 instructions = inner(insn_addr, adjusted_target);
292 uintptr_t pc_page = (uintptr_t)insn_addr >> 12;
293 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12;
294 offset = adr_page - pc_page;
295 int offset_lo = offset & 3;
296 offset >>= 2;
297 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
298 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
299 return instructions;
300 }
301 static int adrpMem(address insn_addr, address &target) {
302 uintptr_t dest = (uintptr_t)target;
303 int offset_lo = dest & 0xfff;
304 uint32_t insn2 = insn_at(insn_addr, 1);
305 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
306 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size);
307 guarantee(((dest >> size) << size) == dest, "misaligned target");
308 return 2;
309 }
310 static int adrpAdd(address insn_addr, address &target) {
311 uintptr_t dest = (uintptr_t)target;
312 int offset_lo = dest & 0xfff;
313 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo);
314 return 2;
315 }
316 static int adrpMovk(address insn_addr, address &target) {
317 uintptr_t dest = uintptr_t(target);
318 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32);
319 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL);
320 target = address(dest);
321 return 2;
322 }
323 static int immediate(address insn_addr, address &target) {
324 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010100, "must be");
325 uint64_t dest = (uint64_t)target;
326 // Move wide constant
327 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
328 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
329 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
330 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
331 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
332 return 3;
333 }
334 static void verify(address insn_addr, address &target) {
335 #ifdef ASSERT
336 address address_is = MacroAssembler::target_addr_for_insn(insn_addr);
337 if (!(address_is == target)) {
338 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target);
339 disnm((intptr_t)insn_addr);
340 assert(address_is == target, "should be");
341 }
342 #endif
343 }
344 };
345
346 // If insn1 and insn2 use the same register to form an address, either
347 // by an offsetted LDR or a simple ADD, return the offset. If the
348 // second instruction is an LDR, the offset may be scaled.
349 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) {
350 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
351 Instruction_aarch64::extract(insn1, 4, 0) ==
352 Instruction_aarch64::extract(insn2, 9, 5)) {
353 // Load/store register (unsigned immediate)
354 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
355 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
356 byte_offset <<= size;
357 return true;
358 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
359 Instruction_aarch64::extract(insn1, 4, 0) ==
360 Instruction_aarch64::extract(insn2, 4, 0)) {
361 // add (immediate)
362 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
363 return true;
364 }
365 return false;
366 }
367
368 class AArch64Decoder : public AllStatic {
369 public:
370
371 static int loadStore(address insn_addr, address &target) {
372 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
373 target = insn_addr + (offset << 2);
374 return 1;
375 }
376 static int unconditionalBranch(address insn_addr, address &target) {
377 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 25, 0);
378 target = insn_addr + (offset << 2);
379 return 1;
380 }
381 static int conditionalBranch(address insn_addr, address &target) {
382 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
383 target = address(((uint64_t)insn_addr + (offset << 2)));
384 return 1;
385 }
386 static int testAndBranch(address insn_addr, address &target) {
387 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 18, 5);
388 target = address(((uint64_t)insn_addr + (offset << 2)));
389 return 1;
390 }
391 static int adr(address insn_addr, address &target) {
392 // PC-rel. addressing
393 uint32_t insn = insn_at(insn_addr, 0);
394 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
395 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
396 target = address((uint64_t)insn_addr + offset);
397 return 1;
398 }
399 template<typename U>
400 static int adrp(address insn_addr, address &target, U inner) {
401 uint32_t insn = insn_at(insn_addr, 0);
402 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
403 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
404 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
405 int shift = 12;
406 offset <<= shift;
407 uint64_t target_page = ((uint64_t)insn_addr) + offset;
408 target_page &= ((uint64_t)-1) << shift;
409 uint32_t insn2 = insn_at(insn_addr, 1);
410 target = address(target_page);
411 precond(inner != nullptr);
412 inner(insn_addr, target);
413 return 2;
414 }
415 static int adrpMem(address insn_addr, address &target) {
416 uint32_t insn2 = insn_at(insn_addr, 1);
417 // Load/store register (unsigned immediate)
418 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
419 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
420 byte_offset <<= size;
421 target += byte_offset;
422 return 2;
423 }
424 static int adrpAdd(address insn_addr, address &target) {
425 uint32_t insn2 = insn_at(insn_addr, 1);
426 // add (immediate)
427 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
428 target += byte_offset;
429 return 2;
430 }
431 static int adrpMovk(address insn_addr, address &target) {
432 uint32_t insn2 = insn_at(insn_addr, 1);
433 uint64_t dest = uint64_t(target);
434 dest = (dest & 0xffff0000ffffffff) |
435 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
436 target = address(dest);
437
438 // We know the destination 4k page. Maybe we have a third
439 // instruction.
440 uint32_t insn = insn_at(insn_addr, 0);
441 uint32_t insn3 = insn_at(insn_addr, 2);
442 ptrdiff_t byte_offset;
443 if (offset_for(insn, insn3, byte_offset)) {
444 target += byte_offset;
445 return 3;
446 } else {
447 return 2;
448 }
449 }
450 static int immediate(address insn_addr, address &target) {
451 uint32_t *insns = (uint32_t *)insn_addr;
452 assert(Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010100, "must be");
453 // Move wide constant: movz, movk, movk. See movptr().
454 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
455 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
456 target = address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5))
457 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
458 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
459 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
460 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
461 return 3;
462 }
463 static void verify(address insn_addr, address &target) {
464 }
465 };
466
467 address MacroAssembler::target_addr_for_insn(address insn_addr) {
468 address target;
469 RelocActions<AArch64Decoder>::run(insn_addr, target);
470 return target;
471 }
472
473 // Patch any kind of instruction; there may be several instructions.
474 // Return the total length (in bytes) of the instructions.
475 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) {
476 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
477 return RelocActions<Patcher>::run(insn_addr, target);
478 }
479
480 int MacroAssembler::patch_oop(address insn_addr, address o) {
481 int instructions;
482 unsigned insn = *(unsigned*)insn_addr;
483 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
484
485 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
486
487 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
488 // narrow OOPs by setting the upper 16 bits in the first
489 // instruction.
490 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
491 // Move narrow OOP
492 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
493 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
494 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
495 instructions = 2;
496 } else {
497 // Move wide OOP
498 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
499 uintptr_t dest = (uintptr_t)o;
500 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
501 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
502 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
503 instructions = 3;
504 }
505 return instructions * NativeInstruction::instruction_size;
506 }
507
508 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
509 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
510 // We encode narrow ones by setting the upper 16 bits in the first
511 // instruction.
512 NativeInstruction *insn = nativeInstruction_at(insn_addr);
513 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
514 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
515
516 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
517
518 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
519 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
520 return 2 * NativeInstruction::instruction_size;
521 }
522
523 address MacroAssembler::target_addr_for_insn_or_null(address insn_addr) {
524 if (NativeInstruction::is_ldrw_to_zr(insn_addr)) {
525 return nullptr;
526 }
527 return MacroAssembler::target_addr_for_insn(insn_addr);
528 }
529
530 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp) {
531 ldr(tmp, Address(rthread, JavaThread::polling_word_offset()));
532 if (at_return) {
533 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
534 // we may safely use the sp instead to perform the stack watermark check.
535 cmp(in_nmethod ? sp : rfp, tmp);
536 br(Assembler::HI, slow_path);
537 } else {
538 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path);
539 }
540 }
541
542 void MacroAssembler::rt_call(address dest, Register tmp) {
543 CodeBlob *cb = CodeCache::find_blob(dest);
544 if (cb) {
545 far_call(RuntimeAddress(dest));
546 } else {
547 lea(tmp, RuntimeAddress(dest));
548 blr(tmp);
549 }
550 }
551
552 void MacroAssembler::push_cont_fastpath(Register java_thread) {
553 if (!Continuations::enabled()) return;
554 Label done;
555 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
556 cmp(sp, rscratch1);
557 br(Assembler::LS, done);
558 mov(rscratch1, sp); // we can't use sp as the source in str
559 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
560 bind(done);
561 }
562
563 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
564 if (!Continuations::enabled()) return;
565 Label done;
566 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
567 cmp(sp, rscratch1);
568 br(Assembler::LO, done);
569 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset()));
570 bind(done);
571 }
572
573 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
574 // we must set sp to zero to clear frame
575 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
576
577 // must clear fp, so that compiled frames are not confused; it is
578 // possible that we need it only for debugging
579 if (clear_fp) {
580 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
581 }
582
583 // Always clear the pc because it could have been set by make_walkable()
584 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
585 }
586
587 // Calls to C land
588 //
589 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
590 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
591 // has to be reset to 0. This is required to allow proper stack traversal.
592 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
593 Register last_java_fp,
594 Register last_java_pc,
595 Register scratch) {
596
597 if (last_java_pc->is_valid()) {
598 str(last_java_pc, Address(rthread,
599 JavaThread::frame_anchor_offset()
600 + JavaFrameAnchor::last_Java_pc_offset()));
601 }
602
603 // determine last_java_sp register
604 if (last_java_sp == sp) {
605 mov(scratch, sp);
606 last_java_sp = scratch;
607 } else if (!last_java_sp->is_valid()) {
608 last_java_sp = esp;
609 }
610
611 // last_java_fp is optional
612 if (last_java_fp->is_valid()) {
613 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
614 }
615
616 // We must set sp last.
617 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
618 }
619
620 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
621 Register last_java_fp,
622 address last_java_pc,
623 Register scratch) {
624 assert(last_java_pc != nullptr, "must provide a valid PC");
625
626 adr(scratch, last_java_pc);
627 str(scratch, Address(rthread,
628 JavaThread::frame_anchor_offset()
629 + JavaFrameAnchor::last_Java_pc_offset()));
630
631 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
632 }
633
634 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
635 Register last_java_fp,
636 Label &L,
637 Register scratch) {
638 if (L.is_bound()) {
639 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
640 } else {
641 InstructionMark im(this);
642 L.add_patch_at(code(), locator());
643 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch);
644 }
645 }
646
647 static inline bool target_needs_far_branch(address addr) {
648 if (AOTCodeCache::is_on_for_dump()) {
649 return true;
650 }
651 // codecache size <= 128M
652 if (!MacroAssembler::far_branches()) {
653 return false;
654 }
655 // codecache size > 240M
656 if (MacroAssembler::codestub_branch_needs_far_jump()) {
657 return true;
658 }
659 // codecache size: 128M..240M
660 return !CodeCache::is_non_nmethod(addr);
661 }
662
663 void MacroAssembler::far_call(Address entry, Register tmp) {
664 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
665 assert(CodeCache::find_blob(entry.target()) != nullptr,
666 "destination of far call not found in code cache");
667 assert(entry.rspec().type() == relocInfo::external_word_type
668 || entry.rspec().type() == relocInfo::runtime_call_type
669 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
670 if (target_needs_far_branch(entry.target())) {
671 uint64_t offset;
672 // We can use ADRP here because we know that the total size of
673 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
674 adrp(tmp, entry, offset);
675 add(tmp, tmp, offset);
676 blr(tmp);
677 } else {
678 bl(entry);
679 }
680 }
681
682 int MacroAssembler::far_jump(Address entry, Register tmp) {
683 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
684 assert(CodeCache::find_blob(entry.target()) != nullptr,
685 "destination of far call not found in code cache");
686 assert(entry.rspec().type() == relocInfo::external_word_type
687 || entry.rspec().type() == relocInfo::runtime_call_type
688 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
689 address start = pc();
690 if (target_needs_far_branch(entry.target())) {
691 uint64_t offset;
692 // We can use ADRP here because we know that the total size of
693 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
694 adrp(tmp, entry, offset);
695 add(tmp, tmp, offset);
696 br(tmp);
697 } else {
698 b(entry);
699 }
700 return pc() - start;
701 }
702
703 void MacroAssembler::reserved_stack_check() {
704 // testing if reserved zone needs to be enabled
705 Label no_reserved_zone_enabling;
706
707 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
708 cmp(sp, rscratch1);
709 br(Assembler::LO, no_reserved_zone_enabling);
710
711 enter(); // LR and FP are live.
712 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)));
713 mov(c_rarg0, rthread);
714 blr(rscratch1);
715 leave();
716
717 // We have already removed our own frame.
718 // throw_delayed_StackOverflowError will think that it's been
719 // called by our caller.
720 lea(rscratch1, RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
721 br(rscratch1);
722 should_not_reach_here();
723
724 bind(no_reserved_zone_enabling);
725 }
726
727 static void pass_arg0(MacroAssembler* masm, Register arg) {
728 if (c_rarg0 != arg ) {
729 masm->mov(c_rarg0, arg);
730 }
731 }
732
733 static void pass_arg1(MacroAssembler* masm, Register arg) {
734 if (c_rarg1 != arg ) {
735 masm->mov(c_rarg1, arg);
736 }
737 }
738
739 static void pass_arg2(MacroAssembler* masm, Register arg) {
740 if (c_rarg2 != arg ) {
741 masm->mov(c_rarg2, arg);
742 }
743 }
744
745 static void pass_arg3(MacroAssembler* masm, Register arg) {
746 if (c_rarg3 != arg ) {
747 masm->mov(c_rarg3, arg);
748 }
749 }
750
751 void MacroAssembler::call_VM_base(Register oop_result,
752 Register java_thread,
753 Register last_java_sp,
754 Label* return_pc,
755 address entry_point,
756 int number_of_arguments,
757 bool check_exceptions) {
758 // determine java_thread register
759 if (!java_thread->is_valid()) {
760 java_thread = rthread;
761 }
762
763 // determine last_java_sp register
764 if (!last_java_sp->is_valid()) {
765 last_java_sp = esp;
766 }
767
768 // debugging support
769 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
770 assert(java_thread == rthread, "unexpected register");
771 #ifdef ASSERT
772 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
773 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
774 #endif // ASSERT
775
776 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
777 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
778
779 // push java thread (becomes first argument of C function)
780
781 mov(c_rarg0, java_thread);
782
783 // set last Java frame before call
784 assert(last_java_sp != rfp, "can't use rfp");
785
786 Label l;
787 set_last_Java_frame(last_java_sp, rfp, return_pc != nullptr ? *return_pc : l, rscratch1);
788
789 // do the call, remove parameters
790 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
791
792 // lr could be poisoned with PAC signature during throw_pending_exception
793 // if it was tail-call optimized by compiler, since lr is not callee-saved
794 // reload it with proper value
795 adr(lr, l);
796
797 // reset last Java frame
798 // Only interpreter should have to clear fp
799 reset_last_Java_frame(true);
800
801 // C++ interp handles this in the interpreter
802 check_and_handle_popframe(java_thread);
803 check_and_handle_earlyret(java_thread);
804
805 if (check_exceptions) {
806 // check for pending exceptions (java_thread is set upon return)
807 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
808 Label ok;
809 cbz(rscratch1, ok);
810 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
811 br(rscratch1);
812 bind(ok);
813 }
814
815 // get oop result if there is one and reset the value in the thread
816 if (oop_result->is_valid()) {
817 get_vm_result_oop(oop_result, java_thread);
818 }
819 }
820
821 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
822 call_VM_base(oop_result, noreg, noreg, nullptr, entry_point, number_of_arguments, check_exceptions);
823 }
824
825 // Check the entry target is always reachable from any branch.
826 static bool is_always_within_branch_range(Address entry) {
827 if (AOTCodeCache::is_on_for_dump()) {
828 return false;
829 }
830 const address target = entry.target();
831
832 if (!CodeCache::contains(target)) {
833 // We always use trampolines for callees outside CodeCache.
834 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target");
835 return false;
836 }
837
838 if (!MacroAssembler::far_branches()) {
839 return true;
840 }
841
842 if (entry.rspec().type() == relocInfo::runtime_call_type) {
843 // Runtime calls are calls of a non-compiled method (stubs, adapters).
844 // Non-compiled methods stay forever in CodeCache.
845 // We check whether the longest possible branch is within the branch range.
846 assert(CodeCache::find_blob(target) != nullptr &&
847 !CodeCache::find_blob(target)->is_nmethod(),
848 "runtime call of compiled method");
849 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size;
850 const address left_longest_branch_start = CodeCache::low_bound();
851 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) &&
852 Assembler::reachable_from_branch_at(right_longest_branch_start, target);
853 return is_reachable;
854 }
855
856 return false;
857 }
858
859 // Maybe emit a call via a trampoline. If the code cache is small
860 // trampolines won't be emitted.
861 address MacroAssembler::trampoline_call(Address entry) {
862 assert(entry.rspec().type() == relocInfo::runtime_call_type
863 || entry.rspec().type() == relocInfo::opt_virtual_call_type
864 || entry.rspec().type() == relocInfo::static_call_type
865 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
866
867 address target = entry.target();
868
869 if (!is_always_within_branch_range(entry)) {
870 if (!in_scratch_emit_size()) {
871 // We don't want to emit a trampoline if C2 is generating dummy
872 // code during its branch shortening phase.
873 if (entry.rspec().type() == relocInfo::runtime_call_type) {
874 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs");
875 code()->share_trampoline_for(entry.target(), offset());
876 } else {
877 address stub = emit_trampoline_stub(offset(), target);
878 if (stub == nullptr) {
879 postcond(pc() == badAddress);
880 return nullptr; // CodeCache is full
881 }
882 }
883 }
884 target = pc();
885 }
886
887 address call_pc = pc();
888 relocate(entry.rspec());
889 bl(target);
890
891 postcond(pc() != badAddress);
892 return call_pc;
893 }
894
895 // Emit a trampoline stub for a call to a target which is too far away.
896 //
897 // code sequences:
898 //
899 // call-site:
900 // branch-and-link to <destination> or <trampoline stub>
901 //
902 // Related trampoline stub for this call site in the stub section:
903 // load the call target from the constant pool
904 // branch (LR still points to the call site above)
905
906 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
907 address dest) {
908 // Max stub size: alignment nop, TrampolineStub.
909 address stub = start_a_stub(max_trampoline_stub_size());
910 if (stub == nullptr) {
911 return nullptr; // CodeBuffer::expand failed
912 }
913
914 // Create a trampoline stub relocation which relates this trampoline stub
915 // with the call instruction at insts_call_instruction_offset in the
916 // instructions code-section.
917 align(wordSize);
918 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
919 + insts_call_instruction_offset));
920 const int stub_start_offset = offset();
921
922 // Now, create the trampoline stub's code:
923 // - load the call
924 // - call
925 Label target;
926 ldr(rscratch1, target);
927 br(rscratch1);
928 bind(target);
929 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
930 "should be");
931 emit_int64((int64_t)dest);
932
933 const address stub_start_addr = addr_at(stub_start_offset);
934
935 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
936
937 end_a_stub();
938 return stub_start_addr;
939 }
940
941 int MacroAssembler::max_trampoline_stub_size() {
942 // Max stub size: alignment nop, TrampolineStub.
943 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size;
944 }
945
946 void MacroAssembler::emit_static_call_stub() {
947 // CompiledDirectCall::set_to_interpreted knows the
948 // exact layout of this stub.
949
950 isb();
951 mov_metadata(rmethod, nullptr);
952
953 // Jump to the entry point of the c2i stub.
954 if (codestub_branch_needs_far_jump()) {
955 movptr(rscratch1, 0);
956 br(rscratch1);
957 } else {
958 b(pc());
959 }
960 }
961
962 int MacroAssembler::static_call_stub_size() {
963 if (!codestub_branch_needs_far_jump()) {
964 // isb; movk; movz; movz; b
965 return 5 * NativeInstruction::instruction_size;
966 }
967 // isb; movk; movz; movz; movk; movz; movz; br
968 return 8 * NativeInstruction::instruction_size;
969 }
970
971 void MacroAssembler::c2bool(Register x) {
972 // implements x == 0 ? 0 : 1
973 // note: must only look at least-significant byte of x
974 // since C-style booleans are stored in one byte
975 // only! (was bug)
976 tst(x, 0xff);
977 cset(x, Assembler::NE);
978 }
979
980 address MacroAssembler::ic_call(address entry, jint method_index) {
981 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
982 movptr(rscratch2, (intptr_t)Universe::non_oop_word());
983 return trampoline_call(Address(entry, rh));
984 }
985
986 int MacroAssembler::ic_check_size() {
987 int extra_instructions = UseCompactObjectHeaders ? 1 : 0;
988 if (target_needs_far_branch(CAST_FROM_FN_PTR(address, SharedRuntime::get_ic_miss_stub()))) {
989 return NativeInstruction::instruction_size * (7 + extra_instructions);
990 } else {
991 return NativeInstruction::instruction_size * (5 + extra_instructions);
992 }
993 }
994
995 int MacroAssembler::ic_check(int end_alignment) {
996 Register receiver = j_rarg0;
997 Register data = rscratch2;
998 Register tmp1 = rscratch1;
999 Register tmp2 = r10;
1000
1001 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1002 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1003 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1004 // before the inline cache check here, and not after
1005 align(end_alignment, offset() + ic_check_size());
1006
1007 int uep_offset = offset();
1008
1009 if (UseCompactObjectHeaders) {
1010 load_narrow_klass_compact(tmp1, receiver);
1011 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1012 cmpw(tmp1, tmp2);
1013 } else if (UseCompressedClassPointers) {
1014 ldrw(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1015 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1016 cmpw(tmp1, tmp2);
1017 } else {
1018 ldr(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1019 ldr(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1020 cmp(tmp1, tmp2);
1021 }
1022
1023 Label dont;
1024 br(Assembler::EQ, dont);
1025 far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1026 bind(dont);
1027 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1028
1029 return uep_offset;
1030 }
1031
1032 // Implementation of call_VM versions
1033
1034 void MacroAssembler::call_VM(Register oop_result,
1035 address entry_point,
1036 bool check_exceptions) {
1037 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1038 }
1039
1040 void MacroAssembler::call_VM(Register oop_result,
1041 address entry_point,
1042 Register arg_1,
1043 bool check_exceptions) {
1044 pass_arg1(this, arg_1);
1045 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1046 }
1047
1048 void MacroAssembler::call_VM(Register oop_result,
1049 address entry_point,
1050 Register arg_1,
1051 Register arg_2,
1052 bool check_exceptions) {
1053 assert_different_registers(arg_1, c_rarg2);
1054 pass_arg2(this, arg_2);
1055 pass_arg1(this, arg_1);
1056 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1057 }
1058
1059 void MacroAssembler::call_VM(Register oop_result,
1060 address entry_point,
1061 Register arg_1,
1062 Register arg_2,
1063 Register arg_3,
1064 bool check_exceptions) {
1065 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1066 assert_different_registers(arg_2, c_rarg3);
1067 pass_arg3(this, arg_3);
1068
1069 pass_arg2(this, arg_2);
1070
1071 pass_arg1(this, arg_1);
1072 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1073 }
1074
1075 void MacroAssembler::call_VM(Register oop_result,
1076 Register last_java_sp,
1077 address entry_point,
1078 int number_of_arguments,
1079 bool check_exceptions) {
1080 call_VM_base(oop_result, rthread, last_java_sp, nullptr, entry_point, number_of_arguments, check_exceptions);
1081 }
1082
1083 void MacroAssembler::call_VM(Register oop_result,
1084 Register last_java_sp,
1085 address entry_point,
1086 Register arg_1,
1087 bool check_exceptions) {
1088 pass_arg1(this, arg_1);
1089 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1090 }
1091
1092 void MacroAssembler::call_VM(Register oop_result,
1093 Register last_java_sp,
1094 address entry_point,
1095 Register arg_1,
1096 Register arg_2,
1097 bool check_exceptions) {
1098
1099 assert_different_registers(arg_1, c_rarg2);
1100 pass_arg2(this, arg_2);
1101 pass_arg1(this, arg_1);
1102 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1103 }
1104
1105 void MacroAssembler::call_VM(Register oop_result,
1106 Register last_java_sp,
1107 address entry_point,
1108 Register arg_1,
1109 Register arg_2,
1110 Register arg_3,
1111 bool check_exceptions) {
1112 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1113 assert_different_registers(arg_2, c_rarg3);
1114 pass_arg3(this, arg_3);
1115 pass_arg2(this, arg_2);
1116 pass_arg1(this, arg_1);
1117 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1118 }
1119
1120
1121 void MacroAssembler::get_vm_result_oop(Register oop_result, Register java_thread) {
1122 ldr(oop_result, Address(java_thread, JavaThread::vm_result_oop_offset()));
1123 str(zr, Address(java_thread, JavaThread::vm_result_oop_offset()));
1124 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1125 }
1126
1127 void MacroAssembler::get_vm_result_metadata(Register metadata_result, Register java_thread) {
1128 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1129 str(zr, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1130 }
1131
1132 void MacroAssembler::align(int modulus) {
1133 align(modulus, offset());
1134 }
1135
1136 // Ensure that the code at target bytes offset from the current offset() is aligned
1137 // according to modulus.
1138 void MacroAssembler::align(int modulus, int target) {
1139 int delta = target - offset();
1140 while ((offset() + delta) % modulus != 0) nop();
1141 }
1142
1143 void MacroAssembler::post_call_nop() {
1144 if (!Continuations::enabled()) {
1145 return;
1146 }
1147 InstructionMark im(this);
1148 relocate(post_call_nop_Relocation::spec());
1149 InlineSkippedInstructionsCounter skipCounter(this);
1150 nop();
1151 movk(zr, 0);
1152 movk(zr, 0);
1153 }
1154
1155 // these are no-ops overridden by InterpreterMacroAssembler
1156
1157 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1158
1159 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1160
1161 // Look up the method for a megamorphic invokeinterface call.
1162 // The target method is determined by <intf_klass, itable_index>.
1163 // The receiver klass is in recv_klass.
1164 // On success, the result will be in method_result, and execution falls through.
1165 // On failure, execution transfers to the given label.
1166 void MacroAssembler::lookup_interface_method(Register recv_klass,
1167 Register intf_klass,
1168 RegisterOrConstant itable_index,
1169 Register method_result,
1170 Register scan_temp,
1171 Label& L_no_such_interface,
1172 bool return_method) {
1173 assert_different_registers(recv_klass, intf_klass, scan_temp);
1174 assert_different_registers(method_result, intf_klass, scan_temp);
1175 assert(recv_klass != method_result || !return_method,
1176 "recv_klass can be destroyed when method isn't needed");
1177 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1178 "caller must use same register for non-constant itable index as for method");
1179
1180 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1181 int vtable_base = in_bytes(Klass::vtable_start_offset());
1182 int itentry_off = in_bytes(itableMethodEntry::method_offset());
1183 int scan_step = itableOffsetEntry::size() * wordSize;
1184 int vte_size = vtableEntry::size_in_bytes();
1185 assert(vte_size == wordSize, "else adjust times_vte_scale");
1186
1187 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1188
1189 // Could store the aligned, prescaled offset in the klass.
1190 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
1191 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
1192 add(scan_temp, scan_temp, vtable_base);
1193
1194 if (return_method) {
1195 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1196 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1197 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1198 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
1199 if (itentry_off)
1200 add(recv_klass, recv_klass, itentry_off);
1201 }
1202
1203 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
1204 // if (scan->interface() == intf) {
1205 // result = (klass + scan->offset() + itable_index);
1206 // }
1207 // }
1208 Label search, found_method;
1209
1210 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1211 cmp(intf_klass, method_result);
1212 br(Assembler::EQ, found_method);
1213 bind(search);
1214 // Check that the previous entry is non-null. A null entry means that
1215 // the receiver class doesn't implement the interface, and wasn't the
1216 // same as when the caller was compiled.
1217 cbz(method_result, L_no_such_interface);
1218 if (itableOffsetEntry::interface_offset() != 0) {
1219 add(scan_temp, scan_temp, scan_step);
1220 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1221 } else {
1222 ldr(method_result, Address(pre(scan_temp, scan_step)));
1223 }
1224 cmp(intf_klass, method_result);
1225 br(Assembler::NE, search);
1226
1227 bind(found_method);
1228
1229 // Got a hit.
1230 if (return_method) {
1231 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
1232 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1233 }
1234 }
1235
1236 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
1237 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
1238 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
1239 // The target method is determined by <holder_klass, itable_index>.
1240 // The receiver klass is in recv_klass.
1241 // On success, the result will be in method_result, and execution falls through.
1242 // On failure, execution transfers to the given label.
1243 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
1244 Register holder_klass,
1245 Register resolved_klass,
1246 Register method_result,
1247 Register temp_itbl_klass,
1248 Register scan_temp,
1249 int itable_index,
1250 Label& L_no_such_interface) {
1251 // 'method_result' is only used as output register at the very end of this method.
1252 // Until then we can reuse it as 'holder_offset'.
1253 Register holder_offset = method_result;
1254 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset);
1255
1256 int vtable_start_offset = in_bytes(Klass::vtable_start_offset());
1257 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize;
1258 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
1259 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
1260
1261 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found;
1262
1263 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1264 add(recv_klass, recv_klass, vtable_start_offset + ioffset);
1265 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len;
1266 // temp_itbl_klass = itable[0]._interface;
1267 int vtblEntrySize = vtableEntry::size_in_bytes();
1268 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3");
1269 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1270 mov(holder_offset, zr);
1271 // scan_temp = &(itable[0]._interface)
1272 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1273
1274 // Initial checks:
1275 // - if (holder_klass != resolved_klass), go to "scan for resolved"
1276 // - if (itable[0] == holder_klass), shortcut to "holder found"
1277 // - if (itable[0] == 0), no such interface
1278 cmp(resolved_klass, holder_klass);
1279 br(Assembler::NE, L_loop_search_resolved_entry);
1280 cmp(holder_klass, temp_itbl_klass);
1281 br(Assembler::EQ, L_holder_found);
1282 cbz(temp_itbl_klass, L_no_such_interface);
1283
1284 // Loop: Look for holder_klass record in itable
1285 // do {
1286 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1287 // if (temp_itbl_klass == holder_klass) {
1288 // goto L_holder_found; // Found!
1289 // }
1290 // } while (temp_itbl_klass != 0);
1291 // goto L_no_such_interface // Not found.
1292 Label L_search_holder;
1293 bind(L_search_holder);
1294 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1295 cmp(holder_klass, temp_itbl_klass);
1296 br(Assembler::EQ, L_holder_found);
1297 cbnz(temp_itbl_klass, L_search_holder);
1298
1299 b(L_no_such_interface);
1300
1301 // Loop: Look for resolved_class record in itable
1302 // while (true) {
1303 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1304 // if (temp_itbl_klass == 0) {
1305 // goto L_no_such_interface;
1306 // }
1307 // if (temp_itbl_klass == resolved_klass) {
1308 // goto L_resolved_found; // Found!
1309 // }
1310 // if (temp_itbl_klass == holder_klass) {
1311 // holder_offset = scan_temp;
1312 // }
1313 // }
1314 //
1315 Label L_loop_search_resolved;
1316 bind(L_loop_search_resolved);
1317 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1318 bind(L_loop_search_resolved_entry);
1319 cbz(temp_itbl_klass, L_no_such_interface);
1320 cmp(resolved_klass, temp_itbl_klass);
1321 br(Assembler::EQ, L_resolved_found);
1322 cmp(holder_klass, temp_itbl_klass);
1323 br(Assembler::NE, L_loop_search_resolved);
1324 mov(holder_offset, scan_temp);
1325 b(L_loop_search_resolved);
1326
1327 // See if we already have a holder klass. If not, go and scan for it.
1328 bind(L_resolved_found);
1329 cbz(holder_offset, L_search_holder);
1330 mov(scan_temp, holder_offset);
1331
1332 // Finally, scan_temp contains holder_klass vtable offset
1333 bind(L_holder_found);
1334 ldrw(method_result, Address(scan_temp, ooffset - ioffset));
1335 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset())
1336 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass
1337 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0)));
1338 }
1339
1340 // virtual method calling
1341 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1342 RegisterOrConstant vtable_index,
1343 Register method_result) {
1344 assert(vtableEntry::size() * wordSize == 8,
1345 "adjust the scaling in the code below");
1346 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset());
1347
1348 if (vtable_index.is_register()) {
1349 lea(method_result, Address(recv_klass,
1350 vtable_index.as_register(),
1351 Address::lsl(LogBytesPerWord)));
1352 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1353 } else {
1354 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1355 ldr(method_result,
1356 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1357 }
1358 }
1359
1360 void MacroAssembler::check_klass_subtype(Register sub_klass,
1361 Register super_klass,
1362 Register temp_reg,
1363 Label& L_success) {
1364 Label L_failure;
1365 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
1366 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
1367 bind(L_failure);
1368 }
1369
1370
1371 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1372 Register super_klass,
1373 Register temp_reg,
1374 Label* L_success,
1375 Label* L_failure,
1376 Label* L_slow_path,
1377 Register super_check_offset) {
1378 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset);
1379 bool must_load_sco = ! super_check_offset->is_valid();
1380 if (must_load_sco) {
1381 assert(temp_reg != noreg, "supply either a temp or a register offset");
1382 }
1383
1384 Label L_fallthrough;
1385 int label_nulls = 0;
1386 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1387 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1388 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
1389 assert(label_nulls <= 1, "at most one null in the batch");
1390
1391 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1392 Address super_check_offset_addr(super_klass, sco_offset);
1393
1394 // Hacked jmp, which may only be used just before L_fallthrough.
1395 #define final_jmp(label) \
1396 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1397 else b(label) /*omit semi*/
1398
1399 // If the pointers are equal, we are done (e.g., String[] elements).
1400 // This self-check enables sharing of secondary supertype arrays among
1401 // non-primary types such as array-of-interface. Otherwise, each such
1402 // type would need its own customized SSA.
1403 // We move this check to the front of the fast path because many
1404 // type checks are in fact trivially successful in this manner,
1405 // so we get a nicely predicted branch right at the start of the check.
1406 cmp(sub_klass, super_klass);
1407 br(Assembler::EQ, *L_success);
1408
1409 // Check the supertype display:
1410 if (must_load_sco) {
1411 ldrw(temp_reg, super_check_offset_addr);
1412 super_check_offset = temp_reg;
1413 }
1414
1415 Address super_check_addr(sub_klass, super_check_offset);
1416 ldr(rscratch1, super_check_addr);
1417 cmp(super_klass, rscratch1); // load displayed supertype
1418 br(Assembler::EQ, *L_success);
1419
1420 // This check has worked decisively for primary supers.
1421 // Secondary supers are sought in the super_cache ('super_cache_addr').
1422 // (Secondary supers are interfaces and very deeply nested subtypes.)
1423 // This works in the same check above because of a tricky aliasing
1424 // between the super_cache and the primary super display elements.
1425 // (The 'super_check_addr' can address either, as the case requires.)
1426 // Note that the cache is updated below if it does not help us find
1427 // what we need immediately.
1428 // So if it was a primary super, we can just fail immediately.
1429 // Otherwise, it's the slow path for us (no success at this point).
1430
1431 sub(rscratch1, super_check_offset, in_bytes(Klass::secondary_super_cache_offset()));
1432 if (L_failure == &L_fallthrough) {
1433 cbz(rscratch1, *L_slow_path);
1434 } else {
1435 cbnz(rscratch1, *L_failure);
1436 final_jmp(*L_slow_path);
1437 }
1438
1439 bind(L_fallthrough);
1440
1441 #undef final_jmp
1442 }
1443
1444 // These two are taken from x86, but they look generally useful
1445
1446 // scans count pointer sized words at [addr] for occurrence of value,
1447 // generic
1448 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1449 Register scratch) {
1450 Label Lloop, Lexit;
1451 cbz(count, Lexit);
1452 bind(Lloop);
1453 ldr(scratch, post(addr, wordSize));
1454 cmp(value, scratch);
1455 br(EQ, Lexit);
1456 sub(count, count, 1);
1457 cbnz(count, Lloop);
1458 bind(Lexit);
1459 }
1460
1461 // scans count 4 byte words at [addr] for occurrence of value,
1462 // generic
1463 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1464 Register scratch) {
1465 Label Lloop, Lexit;
1466 cbz(count, Lexit);
1467 bind(Lloop);
1468 ldrw(scratch, post(addr, wordSize));
1469 cmpw(value, scratch);
1470 br(EQ, Lexit);
1471 sub(count, count, 1);
1472 cbnz(count, Lloop);
1473 bind(Lexit);
1474 }
1475
1476 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
1477 Register super_klass,
1478 Register temp_reg,
1479 Register temp2_reg,
1480 Label* L_success,
1481 Label* L_failure,
1482 bool set_cond_codes) {
1483 // NB! Callers may assume that, when temp2_reg is a valid register,
1484 // this code sets it to a nonzero value.
1485
1486 assert_different_registers(sub_klass, super_klass, temp_reg);
1487 if (temp2_reg != noreg)
1488 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1489 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1490
1491 Label L_fallthrough;
1492 int label_nulls = 0;
1493 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1494 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1495 assert(label_nulls <= 1, "at most one null in the batch");
1496
1497 // a couple of useful fields in sub_klass:
1498 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1499 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1500 Address secondary_supers_addr(sub_klass, ss_offset);
1501 Address super_cache_addr( sub_klass, sc_offset);
1502
1503 BLOCK_COMMENT("check_klass_subtype_slow_path");
1504
1505 // Do a linear scan of the secondary super-klass chain.
1506 // This code is rarely used, so simplicity is a virtue here.
1507 // The repne_scan instruction uses fixed registers, which we must spill.
1508 // Don't worry too much about pre-existing connections with the input regs.
1509
1510 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1511 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1512
1513 RegSet pushed_registers;
1514 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1515 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1516
1517 if (super_klass != r0) {
1518 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1519 }
1520
1521 push(pushed_registers, sp);
1522
1523 // Get super_klass value into r0 (even if it was in r5 or r2).
1524 if (super_klass != r0) {
1525 mov(r0, super_klass);
1526 }
1527
1528 #ifndef PRODUCT
1529 incrementw(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1530 #endif //PRODUCT
1531
1532 // We will consult the secondary-super array.
1533 ldr(r5, secondary_supers_addr);
1534 // Load the array length.
1535 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1536 // Skip to start of data.
1537 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1538
1539 cmp(sp, zr); // Clear Z flag; SP is never zero
1540 // Scan R2 words at [R5] for an occurrence of R0.
1541 // Set NZ/Z based on last compare.
1542 repne_scan(r5, r0, r2, rscratch1);
1543
1544 // Unspill the temp. registers:
1545 pop(pushed_registers, sp);
1546
1547 br(Assembler::NE, *L_failure);
1548
1549 // Success. Cache the super we found and proceed in triumph.
1550
1551 if (UseSecondarySupersCache) {
1552 str(super_klass, super_cache_addr);
1553 }
1554
1555 if (L_success != &L_fallthrough) {
1556 b(*L_success);
1557 }
1558
1559 #undef IS_A_TEMP
1560
1561 bind(L_fallthrough);
1562 }
1563
1564 // If Register r is invalid, remove a new register from
1565 // available_regs, and add new register to regs_to_push.
1566 Register MacroAssembler::allocate_if_noreg(Register r,
1567 RegSetIterator<Register> &available_regs,
1568 RegSet ®s_to_push) {
1569 if (!r->is_valid()) {
1570 r = *available_regs++;
1571 regs_to_push += r;
1572 }
1573 return r;
1574 }
1575
1576 // check_klass_subtype_slow_path_table() looks for super_klass in the
1577 // hash table belonging to super_klass, branching to L_success or
1578 // L_failure as appropriate. This is essentially a shim which
1579 // allocates registers as necessary then calls
1580 // lookup_secondary_supers_table() to do the work. Any of the temp
1581 // regs may be noreg, in which case this logic will chooses some
1582 // registers push and pop them from the stack.
1583 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
1584 Register super_klass,
1585 Register temp_reg,
1586 Register temp2_reg,
1587 Register temp3_reg,
1588 Register result_reg,
1589 FloatRegister vtemp,
1590 Label* L_success,
1591 Label* L_failure,
1592 bool set_cond_codes) {
1593 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
1594
1595 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1596
1597 Label L_fallthrough;
1598 int label_nulls = 0;
1599 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1600 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1601 assert(label_nulls <= 1, "at most one null in the batch");
1602
1603 BLOCK_COMMENT("check_klass_subtype_slow_path");
1604
1605 RegSetIterator<Register> available_regs
1606 = (RegSet::range(r0, r15) - temps - sub_klass - super_klass).begin();
1607
1608 RegSet pushed_regs;
1609
1610 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
1611 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
1612 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
1613 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
1614
1615 push(pushed_regs, sp);
1616
1617 lookup_secondary_supers_table_var(sub_klass,
1618 super_klass,
1619 temp_reg, temp2_reg, temp3_reg, vtemp, result_reg,
1620 nullptr);
1621 cmp(result_reg, zr);
1622
1623 // Unspill the temp. registers:
1624 pop(pushed_regs, sp);
1625
1626 // NB! Callers may assume that, when set_cond_codes is true, this
1627 // code sets temp2_reg to a nonzero value.
1628 if (set_cond_codes) {
1629 mov(temp2_reg, 1);
1630 }
1631
1632 br(Assembler::NE, *L_failure);
1633
1634 if (L_success != &L_fallthrough) {
1635 b(*L_success);
1636 }
1637
1638 bind(L_fallthrough);
1639 }
1640
1641 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1642 Register super_klass,
1643 Register temp_reg,
1644 Register temp2_reg,
1645 Label* L_success,
1646 Label* L_failure,
1647 bool set_cond_codes) {
1648 if (UseSecondarySupersTable) {
1649 check_klass_subtype_slow_path_table
1650 (sub_klass, super_klass, temp_reg, temp2_reg, /*temp3*/noreg, /*result*/noreg,
1651 /*vtemp*/fnoreg,
1652 L_success, L_failure, set_cond_codes);
1653 } else {
1654 check_klass_subtype_slow_path_linear
1655 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
1656 }
1657 }
1658
1659
1660 // Ensure that the inline code and the stub are using the same registers.
1661 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
1662 do { \
1663 assert(r_super_klass == r0 && \
1664 r_array_base == r1 && \
1665 r_array_length == r2 && \
1666 (r_array_index == r3 || r_array_index == noreg) && \
1667 (r_sub_klass == r4 || r_sub_klass == noreg) && \
1668 (r_bitmap == rscratch2 || r_bitmap == noreg) && \
1669 (result == r5 || result == noreg), "registers must match aarch64.ad"); \
1670 } while(0)
1671
1672 bool MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
1673 Register r_super_klass,
1674 Register temp1,
1675 Register temp2,
1676 Register temp3,
1677 FloatRegister vtemp,
1678 Register result,
1679 u1 super_klass_slot,
1680 bool stub_is_near) {
1681 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1682
1683 Label L_fallthrough;
1684
1685 BLOCK_COMMENT("lookup_secondary_supers_table {");
1686
1687 const Register
1688 r_array_base = temp1, // r1
1689 r_array_length = temp2, // r2
1690 r_array_index = temp3, // r3
1691 r_bitmap = rscratch2;
1692
1693 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1694
1695 u1 bit = super_klass_slot;
1696
1697 // Make sure that result is nonzero if the TBZ below misses.
1698 mov(result, 1);
1699
1700 // We're going to need the bitmap in a vector reg and in a core reg,
1701 // so load both now.
1702 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1703 if (bit != 0) {
1704 ldrd(vtemp, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1705 }
1706 // First check the bitmap to see if super_klass might be present. If
1707 // the bit is zero, we are certain that super_klass is not one of
1708 // the secondary supers.
1709 tbz(r_bitmap, bit, L_fallthrough);
1710
1711 // Get the first array index that can contain super_klass into r_array_index.
1712 if (bit != 0) {
1713 shld(vtemp, vtemp, Klass::SECONDARY_SUPERS_TABLE_MASK - bit);
1714 cnt(vtemp, T8B, vtemp);
1715 addv(vtemp, T8B, vtemp);
1716 fmovd(r_array_index, vtemp);
1717 } else {
1718 mov(r_array_index, (u1)1);
1719 }
1720 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1721
1722 // We will consult the secondary-super array.
1723 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1724
1725 // The value i in r_array_index is >= 1, so even though r_array_base
1726 // points to the length, we don't need to adjust it to point to the
1727 // data.
1728 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1729 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1730
1731 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1732 eor(result, result, r_super_klass);
1733 cbz(result, L_fallthrough); // Found a match
1734
1735 // Is there another entry to check? Consult the bitmap.
1736 tbz(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK, L_fallthrough);
1737
1738 // Linear probe.
1739 if (bit != 0) {
1740 ror(r_bitmap, r_bitmap, bit);
1741 }
1742
1743 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1744 // The next slot to be inspected, by the stub we're about to call,
1745 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1746 // have been checked.
1747 Address stub = RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub());
1748 if (stub_is_near) {
1749 bl(stub);
1750 } else {
1751 address call = trampoline_call(stub);
1752 if (call == nullptr) {
1753 return false; // trampoline allocation failed
1754 }
1755 }
1756
1757 BLOCK_COMMENT("} lookup_secondary_supers_table");
1758
1759 bind(L_fallthrough);
1760
1761 if (VerifySecondarySupers) {
1762 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1763 temp1, temp2, result); // r1, r2, r5
1764 }
1765 return true;
1766 }
1767
1768 // At runtime, return 0 in result if r_super_klass is a superclass of
1769 // r_sub_klass, otherwise return nonzero. Use this version of
1770 // lookup_secondary_supers_table() if you don't know ahead of time
1771 // which superclass will be searched for. Used by interpreter and
1772 // runtime stubs. It is larger and has somewhat greater latency than
1773 // the version above, which takes a constant super_klass_slot.
1774 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
1775 Register r_super_klass,
1776 Register temp1,
1777 Register temp2,
1778 Register temp3,
1779 FloatRegister vtemp,
1780 Register result,
1781 Label *L_success) {
1782 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1783
1784 Label L_fallthrough;
1785
1786 BLOCK_COMMENT("lookup_secondary_supers_table {");
1787
1788 const Register
1789 r_array_index = temp3,
1790 slot = rscratch1,
1791 r_bitmap = rscratch2;
1792
1793 ldrb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
1794
1795 // Make sure that result is nonzero if the test below misses.
1796 mov(result, 1);
1797
1798 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1799
1800 // First check the bitmap to see if super_klass might be present. If
1801 // the bit is zero, we are certain that super_klass is not one of
1802 // the secondary supers.
1803
1804 // This next instruction is equivalent to:
1805 // mov(tmp_reg, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1806 // sub(temp2, tmp_reg, slot);
1807 eor(temp2, slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1808 lslv(temp2, r_bitmap, temp2);
1809 tbz(temp2, Klass::SECONDARY_SUPERS_TABLE_SIZE - 1, L_fallthrough);
1810
1811 bool must_save_v0 = (vtemp == fnoreg);
1812 if (must_save_v0) {
1813 // temp1 and result are free, so use them to preserve vtemp
1814 vtemp = v0;
1815 mov(temp1, vtemp, D, 0);
1816 mov(result, vtemp, D, 1);
1817 }
1818
1819 // Get the first array index that can contain super_klass into r_array_index.
1820 mov(vtemp, D, 0, temp2);
1821 cnt(vtemp, T8B, vtemp);
1822 addv(vtemp, T8B, vtemp);
1823 mov(r_array_index, vtemp, D, 0);
1824
1825 if (must_save_v0) {
1826 mov(vtemp, D, 0, temp1 );
1827 mov(vtemp, D, 1, result);
1828 }
1829
1830 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1831
1832 const Register
1833 r_array_base = temp1,
1834 r_array_length = temp2;
1835
1836 // The value i in r_array_index is >= 1, so even though r_array_base
1837 // points to the length, we don't need to adjust it to point to the
1838 // data.
1839 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1840 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1841
1842 // We will consult the secondary-super array.
1843 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1844
1845 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1846 eor(result, result, r_super_klass);
1847 cbz(result, L_success ? *L_success : L_fallthrough); // Found a match
1848
1849 // Is there another entry to check? Consult the bitmap.
1850 rorv(r_bitmap, r_bitmap, slot);
1851 // rol(r_bitmap, r_bitmap, 1);
1852 tbz(r_bitmap, 1, L_fallthrough);
1853
1854 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1855 // The next slot to be inspected, by the logic we're about to call,
1856 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1857 // have been checked.
1858 lookup_secondary_supers_table_slow_path(r_super_klass, r_array_base, r_array_index,
1859 r_bitmap, r_array_length, result, /*is_stub*/false);
1860
1861 BLOCK_COMMENT("} lookup_secondary_supers_table");
1862
1863 bind(L_fallthrough);
1864
1865 if (VerifySecondarySupers) {
1866 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1867 temp1, temp2, result); // r1, r2, r5
1868 }
1869
1870 if (L_success) {
1871 cbz(result, *L_success);
1872 }
1873 }
1874
1875 // Called by code generated by check_klass_subtype_slow_path
1876 // above. This is called when there is a collision in the hashed
1877 // lookup in the secondary supers array.
1878 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
1879 Register r_array_base,
1880 Register r_array_index,
1881 Register r_bitmap,
1882 Register temp1,
1883 Register result,
1884 bool is_stub) {
1885 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, result, rscratch1);
1886
1887 const Register
1888 r_array_length = temp1,
1889 r_sub_klass = noreg; // unused
1890
1891 if (is_stub) {
1892 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1893 }
1894
1895 Label L_fallthrough, L_huge;
1896
1897 // Load the array length.
1898 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1899 // And adjust the array base to point to the data.
1900 // NB! Effectively increments current slot index by 1.
1901 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
1902 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1903
1904 // The bitmap is full to bursting.
1905 // Implicit invariant: BITMAP_FULL implies (length > 0)
1906 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
1907 cmpw(r_array_length, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 2));
1908 br(GT, L_huge);
1909
1910 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
1911 // current slot (at secondary_supers[r_array_index]) has not yet
1912 // been inspected, and r_array_index may be out of bounds if we
1913 // wrapped around the end of the array.
1914
1915 { // This is conventional linear probing, but instead of terminating
1916 // when a null entry is found in the table, we maintain a bitmap
1917 // in which a 0 indicates missing entries.
1918 // As long as the bitmap is not completely full,
1919 // array_length == popcount(bitmap). The array_length check above
1920 // guarantees there are 0s in the bitmap, so the loop eventually
1921 // terminates.
1922 Label L_loop;
1923 bind(L_loop);
1924
1925 // Check for wraparound.
1926 cmp(r_array_index, r_array_length);
1927 csel(r_array_index, zr, r_array_index, GE);
1928
1929 ldr(rscratch1, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1930 eor(result, rscratch1, r_super_klass);
1931 cbz(result, L_fallthrough);
1932
1933 tbz(r_bitmap, 2, L_fallthrough); // look-ahead check (Bit 2); result is non-zero
1934
1935 ror(r_bitmap, r_bitmap, 1);
1936 add(r_array_index, r_array_index, 1);
1937 b(L_loop);
1938 }
1939
1940 { // Degenerate case: more than 64 secondary supers.
1941 // FIXME: We could do something smarter here, maybe a vectorized
1942 // comparison or a binary search, but is that worth any added
1943 // complexity?
1944 bind(L_huge);
1945 cmp(sp, zr); // Clear Z flag; SP is never zero
1946 repne_scan(r_array_base, r_super_klass, r_array_length, rscratch1);
1947 cset(result, NE); // result == 0 iff we got a match.
1948 }
1949
1950 bind(L_fallthrough);
1951 }
1952
1953 // Make sure that the hashed lookup and a linear scan agree.
1954 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
1955 Register r_super_klass,
1956 Register temp1,
1957 Register temp2,
1958 Register result) {
1959 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, result, rscratch1);
1960
1961 const Register
1962 r_array_base = temp1,
1963 r_array_length = temp2,
1964 r_array_index = noreg, // unused
1965 r_bitmap = noreg; // unused
1966
1967 BLOCK_COMMENT("verify_secondary_supers_table {");
1968
1969 // We will consult the secondary-super array.
1970 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1971
1972 // Load the array length.
1973 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1974 // And adjust the array base to point to the data.
1975 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1976
1977 cmp(sp, zr); // Clear Z flag; SP is never zero
1978 // Scan R2 words at [R5] for an occurrence of R0.
1979 // Set NZ/Z based on last compare.
1980 repne_scan(/*addr*/r_array_base, /*value*/r_super_klass, /*count*/r_array_length, rscratch2);
1981 // rscratch1 == 0 iff we got a match.
1982 cset(rscratch1, NE);
1983
1984 Label passed;
1985 cmp(result, zr);
1986 cset(result, NE); // normalize result to 0/1 for comparison
1987
1988 cmp(rscratch1, result);
1989 br(EQ, passed);
1990 {
1991 mov(r0, r_super_klass); // r0 <- r0
1992 mov(r1, r_sub_klass); // r1 <- r4
1993 mov(r2, /*expected*/rscratch1); // r2 <- r8
1994 mov(r3, result); // r3 <- r5
1995 mov(r4, (address)("mismatch")); // r4 <- const
1996 rt_call(CAST_FROM_FN_PTR(address, Klass::on_secondary_supers_verification_failure), rscratch2);
1997 should_not_reach_here();
1998 }
1999 bind(passed);
2000
2001 BLOCK_COMMENT("} verify_secondary_supers_table");
2002 }
2003
2004 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) {
2005 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
2006 assert_different_registers(klass, rthread, scratch);
2007
2008 Label L_fallthrough, L_tmp;
2009 if (L_fast_path == nullptr) {
2010 L_fast_path = &L_fallthrough;
2011 } else if (L_slow_path == nullptr) {
2012 L_slow_path = &L_fallthrough;
2013 }
2014 // Fast path check: class is fully initialized
2015 lea(scratch, Address(klass, InstanceKlass::init_state_offset()));
2016 ldarb(scratch, scratch);
2017 cmp(scratch, InstanceKlass::fully_initialized);
2018 br(Assembler::EQ, *L_fast_path);
2019
2020 // Fast path check: current thread is initializer thread
2021 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
2022 cmp(rthread, scratch);
2023
2024 if (L_slow_path == &L_fallthrough) {
2025 br(Assembler::EQ, *L_fast_path);
2026 bind(*L_slow_path);
2027 } else if (L_fast_path == &L_fallthrough) {
2028 br(Assembler::NE, *L_slow_path);
2029 bind(*L_fast_path);
2030 } else {
2031 Unimplemented();
2032 }
2033 }
2034
2035 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
2036 if (!VerifyOops) return;
2037
2038 // Pass register number to verify_oop_subroutine
2039 const char* b = nullptr;
2040 {
2041 ResourceMark rm;
2042 stringStream ss;
2043 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
2044 b = code_string(ss.as_string());
2045 }
2046 BLOCK_COMMENT("verify_oop {");
2047
2048 strip_return_address(); // This might happen within a stack frame.
2049 protect_return_address();
2050 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2051 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2052
2053 mov(r0, reg);
2054 movptr(rscratch1, (uintptr_t)(address)b);
2055
2056 // call indirectly to solve generation ordering problem
2057 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2058 ldr(rscratch2, Address(rscratch2));
2059 blr(rscratch2);
2060
2061 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2062 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2063 authenticate_return_address();
2064
2065 BLOCK_COMMENT("} verify_oop");
2066 }
2067
2068 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
2069 if (!VerifyOops) return;
2070
2071 const char* b = nullptr;
2072 {
2073 ResourceMark rm;
2074 stringStream ss;
2075 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
2076 b = code_string(ss.as_string());
2077 }
2078 BLOCK_COMMENT("verify_oop_addr {");
2079
2080 strip_return_address(); // This might happen within a stack frame.
2081 protect_return_address();
2082 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2083 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2084
2085 // addr may contain sp so we will have to adjust it based on the
2086 // pushes that we just did.
2087 if (addr.uses(sp)) {
2088 lea(r0, addr);
2089 ldr(r0, Address(r0, 4 * wordSize));
2090 } else {
2091 ldr(r0, addr);
2092 }
2093 movptr(rscratch1, (uintptr_t)(address)b);
2094
2095 // call indirectly to solve generation ordering problem
2096 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2097 ldr(rscratch2, Address(rscratch2));
2098 blr(rscratch2);
2099
2100 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2101 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2102 authenticate_return_address();
2103
2104 BLOCK_COMMENT("} verify_oop_addr");
2105 }
2106
2107 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
2108 int extra_slot_offset) {
2109 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2110 int stackElementSize = Interpreter::stackElementSize;
2111 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
2112 #ifdef ASSERT
2113 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
2114 assert(offset1 - offset == stackElementSize, "correct arithmetic");
2115 #endif
2116 if (arg_slot.is_constant()) {
2117 return Address(esp, arg_slot.as_constant() * stackElementSize
2118 + offset);
2119 } else {
2120 add(rscratch1, esp, arg_slot.as_register(),
2121 ext::uxtx, exact_log2(stackElementSize));
2122 return Address(rscratch1, offset);
2123 }
2124 }
2125
2126 // Handle the receiver type profile update given the "recv" klass.
2127 //
2128 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
2129 // If there are no matching or claimable receiver entries in RD, updates
2130 // the polymorphic counter.
2131 //
2132 // This code expected to run by either the interpreter or JIT-ed code, without
2133 // extra synchronization. For safety, receiver cells are claimed atomically, which
2134 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
2135 // counter updates are not atomic.
2136 //
2137 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
2138 assert_different_registers(recv, mdp, rscratch1, rscratch2);
2139
2140 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
2141 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
2142 int poly_count_offset = in_bytes(CounterData::count_offset());
2143 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
2144 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
2145
2146 // Adjust for MDP offsets.
2147 base_receiver_offset += mdp_offset;
2148 end_receiver_offset += mdp_offset;
2149 poly_count_offset += mdp_offset;
2150
2151 #ifdef ASSERT
2152 // We are about to walk the MDO slots without asking for offsets.
2153 // Check that our math hits all the right spots.
2154 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
2155 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
2156 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
2157 int offset = base_receiver_offset + receiver_step*c;
2158 int count_offset = offset + receiver_to_count_step;
2159 assert(offset == real_recv_offset, "receiver slot math");
2160 assert(count_offset == real_count_offset, "receiver count math");
2161 }
2162 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
2163 assert(poly_count_offset == real_poly_count_offset, "poly counter math");
2164 #endif
2165
2166 // Corner case: no profile table. Increment poly counter and exit.
2167 if (ReceiverTypeData::row_limit() == 0) {
2168 increment(Address(mdp, poly_count_offset), DataLayout::counter_increment);
2169 return;
2170 }
2171
2172 Register offset = rscratch2;
2173
2174 Label L_loop_search_receiver, L_loop_search_empty;
2175 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
2176
2177 // The code here recognizes three major cases:
2178 // A. Fastest: receiver found in the table
2179 // B. Fast: no receiver in the table, and the table is full
2180 // C. Slow: no receiver in the table, free slots in the table
2181 //
2182 // The case A performance is most important, as perfectly-behaved code would end up
2183 // there, especially with larger TypeProfileWidth. The case B performance is
2184 // important as well, this is where bulk of code would land for normally megamorphic
2185 // cases. The case C performance is not essential, its job is to deal with installation
2186 // races, we optimize for code density instead. Case C needs to make sure that receiver
2187 // rows are only claimed once. This makes sure we never overwrite a row for another
2188 // receiver and never duplicate the receivers in the list, making profile type-accurate.
2189 //
2190 // It is very tempting to handle these cases in a single loop, and claim the first slot
2191 // without checking the rest of the table. But, profiling code should tolerate free slots
2192 // in the table, as class unloading can clear them. After such cleanup, the receiver
2193 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
2194 // to complete, before trying to install new slots. Splitting the code in several tight
2195 // loops also helpfully optimizes for cases A and B.
2196 //
2197 // This code is effectively:
2198 //
2199 // restart:
2200 // // Fastest: receiver is already installed
2201 // for (i = 0; i < receiver_count(); i++) {
2202 // if (receiver(i) == recv) goto found_recv(i);
2203 // }
2204 //
2205 // // Fast: no receiver, but profile is full
2206 // for (i = 0; i < receiver_count(); i++) {
2207 // if (receiver(i) == null) goto found_null(i);
2208 // }
2209 // goto polymorphic
2210 //
2211 // // Slow: try to install receiver
2212 // found_null(i):
2213 // CAS(&receiver(i), null, recv);
2214 // goto restart
2215 //
2216 // polymorphic:
2217 // count++;
2218 // return
2219 //
2220 // found_recv(i):
2221 // *receiver_count(i)++
2222 //
2223
2224 bind(L_restart);
2225
2226 // Fastest: receiver is already installed
2227 mov(offset, base_receiver_offset);
2228 bind(L_loop_search_receiver);
2229 ldr(rscratch1, Address(mdp, offset));
2230 cmp(rscratch1, recv);
2231 br(Assembler::EQ, L_found_recv);
2232 add(offset, offset, receiver_step);
2233 sub(rscratch1, offset, end_receiver_offset);
2234 cbnz(rscratch1, L_loop_search_receiver);
2235
2236 // Fast: no receiver, but profile is full
2237 mov(offset, base_receiver_offset);
2238 bind(L_loop_search_empty);
2239 ldr(rscratch1, Address(mdp, offset));
2240 cbz(rscratch1, L_found_empty);
2241 add(offset, offset, receiver_step);
2242 sub(rscratch1, offset, end_receiver_offset);
2243 cbnz(rscratch1, L_loop_search_empty);
2244 b(L_polymorphic);
2245
2246 // Slow: try to install receiver
2247 bind(L_found_empty);
2248
2249 // Atomically swing receiver slot: null -> recv.
2250 //
2251 // The update uses CAS, which clobbers rscratch1. Therefore, rscratch2
2252 // is used to hold the destination address. This is safe because the
2253 // offset is no longer needed after the address is computed.
2254
2255 lea(rscratch2, Address(mdp, offset));
2256 cmpxchg(/*addr*/ rscratch2, /*expected*/ zr, /*new*/ recv, Assembler::xword,
2257 /*acquire*/ false, /*release*/ false, /*weak*/ true, noreg);
2258
2259 // CAS success means the slot now has the receiver we want. CAS failure means
2260 // something had claimed the slot concurrently: it can be the same receiver we want,
2261 // or something else. Since this is a slow path, we can optimize for code density,
2262 // and just restart the search from the beginning.
2263 b(L_restart);
2264
2265 // Counter updates:
2266
2267 // Increment polymorphic counter instead of receiver slot.
2268 bind(L_polymorphic);
2269 mov(offset, poly_count_offset);
2270 b(L_count_update);
2271
2272 // Found a receiver, convert its slot offset to corresponding count offset.
2273 bind(L_found_recv);
2274 add(offset, offset, receiver_to_count_step);
2275
2276 bind(L_count_update);
2277 increment(Address(mdp, offset), DataLayout::counter_increment);
2278 }
2279
2280
2281 void MacroAssembler::call_VM_leaf_base(address entry_point,
2282 int number_of_arguments,
2283 Label *retaddr) {
2284 Label E, L;
2285
2286 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
2287
2288 mov(rscratch1, RuntimeAddress(entry_point));
2289 blr(rscratch1);
2290 if (retaddr)
2291 bind(*retaddr);
2292
2293 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
2294 }
2295
2296 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2297 call_VM_leaf_base(entry_point, number_of_arguments);
2298 }
2299
2300 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2301 pass_arg0(this, arg_0);
2302 call_VM_leaf_base(entry_point, 1);
2303 }
2304
2305 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2306 assert_different_registers(arg_1, c_rarg0);
2307 pass_arg0(this, arg_0);
2308 pass_arg1(this, arg_1);
2309 call_VM_leaf_base(entry_point, 2);
2310 }
2311
2312 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2313 Register arg_1, Register arg_2) {
2314 assert_different_registers(arg_1, c_rarg0);
2315 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2316 pass_arg0(this, arg_0);
2317 pass_arg1(this, arg_1);
2318 pass_arg2(this, arg_2);
2319 call_VM_leaf_base(entry_point, 3);
2320 }
2321
2322 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2323 pass_arg0(this, arg_0);
2324 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2325 }
2326
2327 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2328
2329 assert_different_registers(arg_0, c_rarg1);
2330 pass_arg1(this, arg_1);
2331 pass_arg0(this, arg_0);
2332 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2333 }
2334
2335 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2336 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2337 assert_different_registers(arg_1, c_rarg2);
2338 pass_arg2(this, arg_2);
2339 pass_arg1(this, arg_1);
2340 pass_arg0(this, arg_0);
2341 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2342 }
2343
2344 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2345 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
2346 assert_different_registers(arg_1, c_rarg2, c_rarg3);
2347 assert_different_registers(arg_2, c_rarg3);
2348 pass_arg3(this, arg_3);
2349 pass_arg2(this, arg_2);
2350 pass_arg1(this, arg_1);
2351 pass_arg0(this, arg_0);
2352 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2353 }
2354
2355 void MacroAssembler::null_check(Register reg, int offset) {
2356 if (needs_explicit_null_check(offset)) {
2357 // provoke OS null exception if reg is null by
2358 // accessing M[reg] w/o changing any registers
2359 // NOTE: this is plenty to provoke a segv
2360 ldr(zr, Address(reg));
2361 } else {
2362 // nothing to do, (later) access of M[reg + offset]
2363 // will provoke OS null exception if reg is null
2364 }
2365 }
2366
2367 // MacroAssembler protected routines needed to implement
2368 // public methods
2369
2370 void MacroAssembler::mov(Register r, Address dest) {
2371 code_section()->relocate(pc(), dest.rspec());
2372 uint64_t imm64 = (uint64_t)dest.target();
2373 movptr(r, imm64);
2374 }
2375
2376 // Move a constant pointer into r. In AArch64 mode the virtual
2377 // address space is 48 bits in size, so we only need three
2378 // instructions to create a patchable instruction sequence that can
2379 // reach anywhere.
2380 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2381 #ifndef PRODUCT
2382 {
2383 char buffer[64];
2384 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2385 block_comment(buffer);
2386 }
2387 #endif
2388 assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
2389 movz(r, imm64 & 0xffff);
2390 imm64 >>= 16;
2391 movk(r, imm64 & 0xffff, 16);
2392 imm64 >>= 16;
2393 movk(r, imm64 & 0xffff, 32);
2394 }
2395
2396 // Macro to mov replicated immediate to vector register.
2397 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is,
2398 // the upper 56/48/32 bits must be zeros for B/H/S type.
2399 // Vd will get the following values for different arrangements in T
2400 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh
2401 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
2402 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh
2403 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
2404 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
2405 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
2406 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh
2407 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh
2408 // Clobbers rscratch1
2409 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) {
2410 assert(T != T1Q, "unsupported");
2411 if (T == T1D || T == T2D) {
2412 int imm = operand_valid_for_movi_immediate(imm64, T);
2413 if (-1 != imm) {
2414 movi(Vd, T, imm);
2415 } else {
2416 mov(rscratch1, imm64);
2417 dup(Vd, T, rscratch1);
2418 }
2419 return;
2420 }
2421
2422 #ifdef ASSERT
2423 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)");
2424 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)");
2425 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)");
2426 #endif
2427 int shift = operand_valid_for_movi_immediate(imm64, T);
2428 uint32_t imm32 = imm64 & 0xffffffffULL;
2429 if (shift >= 0) {
2430 movi(Vd, T, (imm32 >> shift) & 0xff, shift);
2431 } else {
2432 movw(rscratch1, imm32);
2433 dup(Vd, T, rscratch1);
2434 }
2435 }
2436
2437 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
2438 {
2439 #ifndef PRODUCT
2440 {
2441 char buffer[64];
2442 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, imm64);
2443 block_comment(buffer);
2444 }
2445 #endif
2446 if (operand_valid_for_logical_immediate(false, imm64)) {
2447 orr(dst, zr, imm64);
2448 } else {
2449 // we can use a combination of MOVZ or MOVN with
2450 // MOVK to build up the constant
2451 uint64_t imm_h[4];
2452 int zero_count = 0;
2453 int neg_count = 0;
2454 int i;
2455 for (i = 0; i < 4; i++) {
2456 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
2457 if (imm_h[i] == 0) {
2458 zero_count++;
2459 } else if (imm_h[i] == 0xffffL) {
2460 neg_count++;
2461 }
2462 }
2463 if (zero_count == 4) {
2464 // one MOVZ will do
2465 movz(dst, 0);
2466 } else if (neg_count == 4) {
2467 // one MOVN will do
2468 movn(dst, 0);
2469 } else if (zero_count == 3) {
2470 for (i = 0; i < 4; i++) {
2471 if (imm_h[i] != 0L) {
2472 movz(dst, (uint32_t)imm_h[i], (i << 4));
2473 break;
2474 }
2475 }
2476 } else if (neg_count == 3) {
2477 // one MOVN will do
2478 for (int i = 0; i < 4; i++) {
2479 if (imm_h[i] != 0xffffL) {
2480 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2481 break;
2482 }
2483 }
2484 } else if (zero_count == 2) {
2485 // one MOVZ and one MOVK will do
2486 for (i = 0; i < 3; i++) {
2487 if (imm_h[i] != 0L) {
2488 movz(dst, (uint32_t)imm_h[i], (i << 4));
2489 i++;
2490 break;
2491 }
2492 }
2493 for (;i < 4; i++) {
2494 if (imm_h[i] != 0L) {
2495 movk(dst, (uint32_t)imm_h[i], (i << 4));
2496 }
2497 }
2498 } else if (neg_count == 2) {
2499 // one MOVN and one MOVK will do
2500 for (i = 0; i < 4; i++) {
2501 if (imm_h[i] != 0xffffL) {
2502 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2503 i++;
2504 break;
2505 }
2506 }
2507 for (;i < 4; i++) {
2508 if (imm_h[i] != 0xffffL) {
2509 movk(dst, (uint32_t)imm_h[i], (i << 4));
2510 }
2511 }
2512 } else if (zero_count == 1) {
2513 // one MOVZ and two MOVKs will do
2514 for (i = 0; i < 4; i++) {
2515 if (imm_h[i] != 0L) {
2516 movz(dst, (uint32_t)imm_h[i], (i << 4));
2517 i++;
2518 break;
2519 }
2520 }
2521 for (;i < 4; i++) {
2522 if (imm_h[i] != 0x0L) {
2523 movk(dst, (uint32_t)imm_h[i], (i << 4));
2524 }
2525 }
2526 } else if (neg_count == 1) {
2527 // one MOVN and two MOVKs will do
2528 for (i = 0; i < 4; i++) {
2529 if (imm_h[i] != 0xffffL) {
2530 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2531 i++;
2532 break;
2533 }
2534 }
2535 for (;i < 4; i++) {
2536 if (imm_h[i] != 0xffffL) {
2537 movk(dst, (uint32_t)imm_h[i], (i << 4));
2538 }
2539 }
2540 } else {
2541 // use a MOVZ and 3 MOVKs (makes it easier to debug)
2542 movz(dst, (uint32_t)imm_h[0], 0);
2543 for (i = 1; i < 4; i++) {
2544 movk(dst, (uint32_t)imm_h[i], (i << 4));
2545 }
2546 }
2547 }
2548 }
2549
2550 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
2551 {
2552 #ifndef PRODUCT
2553 {
2554 char buffer[64];
2555 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX32, imm32);
2556 block_comment(buffer);
2557 }
2558 #endif
2559 if (operand_valid_for_logical_immediate(true, imm32)) {
2560 orrw(dst, zr, imm32);
2561 } else {
2562 // we can use MOVZ, MOVN or two calls to MOVK to build up the
2563 // constant
2564 uint32_t imm_h[2];
2565 imm_h[0] = imm32 & 0xffff;
2566 imm_h[1] = ((imm32 >> 16) & 0xffff);
2567 if (imm_h[0] == 0) {
2568 movzw(dst, imm_h[1], 16);
2569 } else if (imm_h[0] == 0xffff) {
2570 movnw(dst, imm_h[1] ^ 0xffff, 16);
2571 } else if (imm_h[1] == 0) {
2572 movzw(dst, imm_h[0], 0);
2573 } else if (imm_h[1] == 0xffff) {
2574 movnw(dst, imm_h[0] ^ 0xffff, 0);
2575 } else {
2576 // use a MOVZ and MOVK (makes it easier to debug)
2577 movzw(dst, imm_h[0], 0);
2578 movkw(dst, imm_h[1], 16);
2579 }
2580 }
2581 }
2582
2583 // Form an address from base + offset in Rd. Rd may or may
2584 // not actually be used: you must use the Address that is returned.
2585 // It is up to you to ensure that the shift provided matches the size
2586 // of your data.
2587 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
2588 if (Address::offset_ok_for_immed(byte_offset, shift))
2589 // It fits; no need for any heroics
2590 return Address(base, byte_offset);
2591
2592 // Don't do anything clever with negative or misaligned offsets
2593 unsigned mask = (1 << shift) - 1;
2594 if (byte_offset < 0 || byte_offset & mask) {
2595 mov(Rd, byte_offset);
2596 add(Rd, base, Rd);
2597 return Address(Rd);
2598 }
2599
2600 // See if we can do this with two 12-bit offsets
2601 {
2602 uint64_t word_offset = byte_offset >> shift;
2603 uint64_t masked_offset = word_offset & 0xfff000;
2604 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
2605 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
2606 add(Rd, base, masked_offset << shift);
2607 word_offset -= masked_offset;
2608 return Address(Rd, word_offset << shift);
2609 }
2610 }
2611
2612 // Do it the hard way
2613 mov(Rd, byte_offset);
2614 add(Rd, base, Rd);
2615 return Address(Rd);
2616 }
2617
2618 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
2619 bool want_remainder, Register scratch)
2620 {
2621 // Full implementation of Java idiv and irem. The function
2622 // returns the (pc) offset of the div instruction - may be needed
2623 // for implicit exceptions.
2624 //
2625 // constraint : ra/rb =/= scratch
2626 // normal case
2627 //
2628 // input : ra: dividend
2629 // rb: divisor
2630 //
2631 // result: either
2632 // quotient (= ra idiv rb)
2633 // remainder (= ra irem rb)
2634
2635 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2636
2637 int idivl_offset = offset();
2638 if (! want_remainder) {
2639 sdivw(result, ra, rb);
2640 } else {
2641 sdivw(scratch, ra, rb);
2642 Assembler::msubw(result, scratch, rb, ra);
2643 }
2644
2645 return idivl_offset;
2646 }
2647
2648 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
2649 bool want_remainder, Register scratch)
2650 {
2651 // Full implementation of Java ldiv and lrem. The function
2652 // returns the (pc) offset of the div instruction - may be needed
2653 // for implicit exceptions.
2654 //
2655 // constraint : ra/rb =/= scratch
2656 // normal case
2657 //
2658 // input : ra: dividend
2659 // rb: divisor
2660 //
2661 // result: either
2662 // quotient (= ra idiv rb)
2663 // remainder (= ra irem rb)
2664
2665 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2666
2667 int idivq_offset = offset();
2668 if (! want_remainder) {
2669 sdiv(result, ra, rb);
2670 } else {
2671 sdiv(scratch, ra, rb);
2672 Assembler::msub(result, scratch, rb, ra);
2673 }
2674
2675 return idivq_offset;
2676 }
2677
2678 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
2679 address prev = pc() - NativeMembar::instruction_size;
2680 address last = code()->last_insn();
2681 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) {
2682 NativeMembar *bar = NativeMembar_at(prev);
2683 if (AlwaysMergeDMB) {
2684 bar->set_kind(bar->get_kind() | order_constraint);
2685 BLOCK_COMMENT("merged membar(always)");
2686 return;
2687 }
2688 // Don't promote DMB ST|DMB LD to DMB (a full barrier) because
2689 // doing so would introduce a StoreLoad which the caller did not
2690 // intend
2691 if (bar->get_kind() == order_constraint
2692 || bar->get_kind() == AnyAny
2693 || order_constraint == AnyAny) {
2694 // We are merging two memory barrier instructions. On AArch64 we
2695 // can do this simply by ORing them together.
2696 bar->set_kind(bar->get_kind() | order_constraint);
2697 BLOCK_COMMENT("merged membar");
2698 return;
2699 } else {
2700 // A special case like "DMB ST;DMB LD;DMB ST", the last DMB can be skipped
2701 // We need check the last 2 instructions
2702 address prev2 = prev - NativeMembar::instruction_size;
2703 if (last != code()->last_label() && nativeInstruction_at(prev2)->is_Membar()) {
2704 NativeMembar *bar2 = NativeMembar_at(prev2);
2705 assert(bar2->get_kind() == order_constraint, "it should be merged before");
2706 BLOCK_COMMENT("merged membar(elided)");
2707 return;
2708 }
2709 }
2710 }
2711 code()->set_last_insn(pc());
2712 dmb(Assembler::barrier(order_constraint));
2713 }
2714
2715 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
2716 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
2717 merge_ldst(rt, adr, size_in_bytes, is_store);
2718 code()->clear_last_insn();
2719 return true;
2720 } else {
2721 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
2722 const uint64_t mask = size_in_bytes - 1;
2723 if (adr.getMode() == Address::base_plus_offset &&
2724 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
2725 code()->set_last_insn(pc());
2726 }
2727 return false;
2728 }
2729 }
2730
2731 void MacroAssembler::ldr(Register Rx, const Address &adr) {
2732 // We always try to merge two adjacent loads into one ldp.
2733 if (!try_merge_ldst(Rx, adr, 8, false)) {
2734 Assembler::ldr(Rx, adr);
2735 }
2736 }
2737
2738 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
2739 // We always try to merge two adjacent loads into one ldp.
2740 if (!try_merge_ldst(Rw, adr, 4, false)) {
2741 Assembler::ldrw(Rw, adr);
2742 }
2743 }
2744
2745 void MacroAssembler::str(Register Rx, const Address &adr) {
2746 // We always try to merge two adjacent stores into one stp.
2747 if (!try_merge_ldst(Rx, adr, 8, true)) {
2748 Assembler::str(Rx, adr);
2749 }
2750 }
2751
2752 void MacroAssembler::strw(Register Rw, const Address &adr) {
2753 // We always try to merge two adjacent stores into one stp.
2754 if (!try_merge_ldst(Rw, adr, 4, true)) {
2755 Assembler::strw(Rw, adr);
2756 }
2757 }
2758
2759 // MacroAssembler routines found actually to be needed
2760
2761 void MacroAssembler::push(Register src)
2762 {
2763 str(src, Address(pre(esp, -1 * wordSize)));
2764 }
2765
2766 void MacroAssembler::pop(Register dst)
2767 {
2768 ldr(dst, Address(post(esp, 1 * wordSize)));
2769 }
2770
2771 // Note: load_unsigned_short used to be called load_unsigned_word.
2772 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2773 int off = offset();
2774 ldrh(dst, src);
2775 return off;
2776 }
2777
2778 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2779 int off = offset();
2780 ldrb(dst, src);
2781 return off;
2782 }
2783
2784 int MacroAssembler::load_signed_short(Register dst, Address src) {
2785 int off = offset();
2786 ldrsh(dst, src);
2787 return off;
2788 }
2789
2790 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2791 int off = offset();
2792 ldrsb(dst, src);
2793 return off;
2794 }
2795
2796 int MacroAssembler::load_signed_short32(Register dst, Address src) {
2797 int off = offset();
2798 ldrshw(dst, src);
2799 return off;
2800 }
2801
2802 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
2803 int off = offset();
2804 ldrsbw(dst, src);
2805 return off;
2806 }
2807
2808 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2809 switch (size_in_bytes) {
2810 case 8: ldr(dst, src); break;
2811 case 4: ldrw(dst, src); break;
2812 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2813 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2814 default: ShouldNotReachHere();
2815 }
2816 }
2817
2818 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) {
2819 switch (size_in_bytes) {
2820 case 8: str(src, dst); break;
2821 case 4: strw(src, dst); break;
2822 case 2: strh(src, dst); break;
2823 case 1: strb(src, dst); break;
2824 default: ShouldNotReachHere();
2825 }
2826 }
2827
2828 void MacroAssembler::decrementw(Register reg, int value)
2829 {
2830 if (value < 0) { incrementw(reg, -value); return; }
2831 if (value == 0) { return; }
2832 if (value < (1 << 12)) { subw(reg, reg, value); return; }
2833 /* else */ {
2834 guarantee(reg != rscratch2, "invalid dst for register decrement");
2835 movw(rscratch2, (unsigned)value);
2836 subw(reg, reg, rscratch2);
2837 }
2838 }
2839
2840 void MacroAssembler::decrement(Register reg, int value)
2841 {
2842 if (value < 0) { increment(reg, -value); return; }
2843 if (value == 0) { return; }
2844 if (value < (1 << 12)) { sub(reg, reg, value); return; }
2845 /* else */ {
2846 assert(reg != rscratch2, "invalid dst for register decrement");
2847 mov(rscratch2, (uint64_t)value);
2848 sub(reg, reg, rscratch2);
2849 }
2850 }
2851
2852 void MacroAssembler::decrementw(Address dst, int value)
2853 {
2854 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
2855 if (dst.getMode() == Address::literal) {
2856 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2857 lea(rscratch2, dst);
2858 dst = Address(rscratch2);
2859 }
2860 ldrw(rscratch1, dst);
2861 decrementw(rscratch1, value);
2862 strw(rscratch1, dst);
2863 }
2864
2865 void MacroAssembler::decrement(Address dst, int value)
2866 {
2867 assert(!dst.uses(rscratch1), "invalid address for decrement");
2868 if (dst.getMode() == Address::literal) {
2869 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2870 lea(rscratch2, dst);
2871 dst = Address(rscratch2);
2872 }
2873 ldr(rscratch1, dst);
2874 decrement(rscratch1, value);
2875 str(rscratch1, dst);
2876 }
2877
2878 void MacroAssembler::incrementw(Register reg, int value)
2879 {
2880 if (value < 0) { decrementw(reg, -value); return; }
2881 if (value == 0) { return; }
2882 if (value < (1 << 12)) { addw(reg, reg, value); return; }
2883 /* else */ {
2884 assert(reg != rscratch2, "invalid dst for register increment");
2885 movw(rscratch2, (unsigned)value);
2886 addw(reg, reg, rscratch2);
2887 }
2888 }
2889
2890 void MacroAssembler::increment(Register reg, int value)
2891 {
2892 if (value < 0) { decrement(reg, -value); return; }
2893 if (value == 0) { return; }
2894 if (value < (1 << 12)) { add(reg, reg, value); return; }
2895 /* else */ {
2896 assert(reg != rscratch2, "invalid dst for register increment");
2897 movw(rscratch2, (unsigned)value);
2898 add(reg, reg, rscratch2);
2899 }
2900 }
2901
2902 void MacroAssembler::incrementw(Address dst, int value)
2903 {
2904 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2905 if (dst.getMode() == Address::literal) {
2906 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2907 lea(rscratch2, dst);
2908 dst = Address(rscratch2);
2909 }
2910 ldrw(rscratch1, dst);
2911 incrementw(rscratch1, value);
2912 strw(rscratch1, dst);
2913 }
2914
2915 void MacroAssembler::increment(Address dst, int value)
2916 {
2917 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2918 if (dst.getMode() == Address::literal) {
2919 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2920 lea(rscratch2, dst);
2921 dst = Address(rscratch2);
2922 }
2923 ldr(rscratch1, dst);
2924 increment(rscratch1, value);
2925 str(rscratch1, dst);
2926 }
2927
2928 // Push lots of registers in the bit set supplied. Don't push sp.
2929 // Return the number of words pushed
2930 int MacroAssembler::push(unsigned int bitset, Register stack) {
2931 int words_pushed = 0;
2932
2933 // Scan bitset to accumulate register pairs
2934 unsigned char regs[32];
2935 int count = 0;
2936 for (int reg = 0; reg <= 30; reg++) {
2937 if (1 & bitset)
2938 regs[count++] = reg;
2939 bitset >>= 1;
2940 }
2941 regs[count++] = zr->raw_encoding();
2942 count &= ~1; // Only push an even number of regs
2943
2944 if (count) {
2945 stp(as_Register(regs[0]), as_Register(regs[1]),
2946 Address(pre(stack, -count * wordSize)));
2947 words_pushed += 2;
2948 }
2949 for (int i = 2; i < count; i += 2) {
2950 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2951 Address(stack, i * wordSize));
2952 words_pushed += 2;
2953 }
2954
2955 assert(words_pushed == count, "oops, pushed != count");
2956
2957 return count;
2958 }
2959
2960 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2961 int words_pushed = 0;
2962
2963 // Scan bitset to accumulate register pairs
2964 unsigned char regs[32];
2965 int count = 0;
2966 for (int reg = 0; reg <= 30; reg++) {
2967 if (1 & bitset)
2968 regs[count++] = reg;
2969 bitset >>= 1;
2970 }
2971 regs[count++] = zr->raw_encoding();
2972 count &= ~1;
2973
2974 for (int i = 2; i < count; i += 2) {
2975 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2976 Address(stack, i * wordSize));
2977 words_pushed += 2;
2978 }
2979 if (count) {
2980 ldp(as_Register(regs[0]), as_Register(regs[1]),
2981 Address(post(stack, count * wordSize)));
2982 words_pushed += 2;
2983 }
2984
2985 assert(words_pushed == count, "oops, pushed != count");
2986
2987 return count;
2988 }
2989
2990 // Push lots of registers in the bit set supplied. Don't push sp.
2991 // Return the number of dwords pushed
2992 int MacroAssembler::push_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
2993 int words_pushed = 0;
2994 bool use_sve = false;
2995 int sve_vector_size_in_bytes = 0;
2996
2997 #ifdef COMPILER2
2998 use_sve = Matcher::supports_scalable_vector();
2999 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
3000 #endif
3001
3002 // Scan bitset to accumulate register pairs
3003 unsigned char regs[32];
3004 int count = 0;
3005 for (int reg = 0; reg <= 31; reg++) {
3006 if (1 & bitset)
3007 regs[count++] = reg;
3008 bitset >>= 1;
3009 }
3010
3011 if (count == 0) {
3012 return 0;
3013 }
3014
3015 if (mode == PushPopFull) {
3016 if (use_sve && sve_vector_size_in_bytes > 16) {
3017 mode = PushPopSVE;
3018 } else {
3019 mode = PushPopNeon;
3020 }
3021 }
3022
3023 #ifndef PRODUCT
3024 {
3025 char buffer[48];
3026 if (mode == PushPopSVE) {
3027 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d SVE registers", count);
3028 } else if (mode == PushPopNeon) {
3029 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d Neon registers", count);
3030 } else {
3031 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d fp registers", count);
3032 }
3033 block_comment(buffer);
3034 }
3035 #endif
3036
3037 if (mode == PushPopSVE) {
3038 sub(stack, stack, sve_vector_size_in_bytes * count);
3039 for (int i = 0; i < count; i++) {
3040 sve_str(as_FloatRegister(regs[i]), Address(stack, i));
3041 }
3042 return count * sve_vector_size_in_bytes / 8;
3043 }
3044
3045 if (mode == PushPopNeon) {
3046 if (count == 1) {
3047 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2)));
3048 return 2;
3049 }
3050
3051 bool odd = (count & 1) == 1;
3052 int push_slots = count + (odd ? 1 : 0);
3053
3054 // Always pushing full 128 bit registers.
3055 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2)));
3056 words_pushed += 2;
3057
3058 for (int i = 2; i + 1 < count; i += 2) {
3059 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3060 words_pushed += 2;
3061 }
3062
3063 if (odd) {
3064 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3065 words_pushed++;
3066 }
3067
3068 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3069 return count * 2;
3070 }
3071
3072 if (mode == PushPopFp) {
3073 bool odd = (count & 1) == 1;
3074 int push_slots = count + (odd ? 1 : 0);
3075
3076 if (count == 1) {
3077 // Stack pointer must be 16 bytes aligned
3078 strd(as_FloatRegister(regs[0]), Address(pre(stack, -push_slots * wordSize)));
3079 return 1;
3080 }
3081
3082 stpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize)));
3083 words_pushed += 2;
3084
3085 for (int i = 2; i + 1 < count; i += 2) {
3086 stpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3087 words_pushed += 2;
3088 }
3089
3090 if (odd) {
3091 // Stack pointer must be 16 bytes aligned
3092 strd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3093 words_pushed++;
3094 }
3095
3096 assert(words_pushed == count, "oops, pushed != count");
3097
3098 return count;
3099 }
3100
3101 return 0;
3102 }
3103
3104 // Return the number of dwords popped
3105 int MacroAssembler::pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
3106 int words_pushed = 0;
3107 bool use_sve = false;
3108 int sve_vector_size_in_bytes = 0;
3109
3110 #ifdef COMPILER2
3111 use_sve = Matcher::supports_scalable_vector();
3112 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
3113 #endif
3114 // Scan bitset to accumulate register pairs
3115 unsigned char regs[32];
3116 int count = 0;
3117 for (int reg = 0; reg <= 31; reg++) {
3118 if (1 & bitset)
3119 regs[count++] = reg;
3120 bitset >>= 1;
3121 }
3122
3123 if (count == 0) {
3124 return 0;
3125 }
3126
3127 if (mode == PushPopFull) {
3128 if (use_sve && sve_vector_size_in_bytes > 16) {
3129 mode = PushPopSVE;
3130 } else {
3131 mode = PushPopNeon;
3132 }
3133 }
3134
3135 #ifndef PRODUCT
3136 {
3137 char buffer[48];
3138 if (mode == PushPopSVE) {
3139 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d SVE registers", count);
3140 } else if (mode == PushPopNeon) {
3141 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d Neon registers", count);
3142 } else {
3143 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d fp registers", count);
3144 }
3145 block_comment(buffer);
3146 }
3147 #endif
3148
3149 if (mode == PushPopSVE) {
3150 for (int i = count - 1; i >= 0; i--) {
3151 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i));
3152 }
3153 add(stack, stack, sve_vector_size_in_bytes * count);
3154 return count * sve_vector_size_in_bytes / 8;
3155 }
3156
3157 if (mode == PushPopNeon) {
3158 if (count == 1) {
3159 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2)));
3160 return 2;
3161 }
3162
3163 bool odd = (count & 1) == 1;
3164 int push_slots = count + (odd ? 1 : 0);
3165
3166 if (odd) {
3167 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3168 words_pushed++;
3169 }
3170
3171 for (int i = 2; i + 1 < count; i += 2) {
3172 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3173 words_pushed += 2;
3174 }
3175
3176 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2)));
3177 words_pushed += 2;
3178
3179 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3180
3181 return count * 2;
3182 }
3183
3184 if (mode == PushPopFp) {
3185 bool odd = (count & 1) == 1;
3186 int push_slots = count + (odd ? 1 : 0);
3187
3188 if (count == 1) {
3189 ldrd(as_FloatRegister(regs[0]), Address(post(stack, push_slots * wordSize)));
3190 return 1;
3191 }
3192
3193 if (odd) {
3194 ldrd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3195 words_pushed++;
3196 }
3197
3198 for (int i = 2; i + 1 < count; i += 2) {
3199 ldpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3200 words_pushed += 2;
3201 }
3202
3203 ldpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize)));
3204 words_pushed += 2;
3205
3206 assert(words_pushed == count, "oops, pushed != count");
3207
3208 return count;
3209 }
3210
3211 return 0;
3212 }
3213
3214 // Return the number of dwords pushed
3215 int MacroAssembler::push_p(unsigned int bitset, Register stack) {
3216 bool use_sve = false;
3217 int sve_predicate_size_in_slots = 0;
3218
3219 #ifdef COMPILER2
3220 use_sve = Matcher::supports_scalable_vector();
3221 if (use_sve) {
3222 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3223 }
3224 #endif
3225
3226 if (!use_sve) {
3227 return 0;
3228 }
3229
3230 unsigned char regs[PRegister::number_of_registers];
3231 int count = 0;
3232 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3233 if (1 & bitset)
3234 regs[count++] = reg;
3235 bitset >>= 1;
3236 }
3237
3238 if (count == 0) {
3239 return 0;
3240 }
3241
3242 int total_push_bytes = align_up(sve_predicate_size_in_slots *
3243 VMRegImpl::stack_slot_size * count, 16);
3244 sub(stack, stack, total_push_bytes);
3245 for (int i = 0; i < count; i++) {
3246 sve_str(as_PRegister(regs[i]), Address(stack, i));
3247 }
3248 return total_push_bytes / 8;
3249 }
3250
3251 // Return the number of dwords popped
3252 int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
3253 bool use_sve = false;
3254 int sve_predicate_size_in_slots = 0;
3255
3256 #ifdef COMPILER2
3257 use_sve = Matcher::supports_scalable_vector();
3258 if (use_sve) {
3259 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3260 }
3261 #endif
3262
3263 if (!use_sve) {
3264 return 0;
3265 }
3266
3267 unsigned char regs[PRegister::number_of_registers];
3268 int count = 0;
3269 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3270 if (1 & bitset)
3271 regs[count++] = reg;
3272 bitset >>= 1;
3273 }
3274
3275 if (count == 0) {
3276 return 0;
3277 }
3278
3279 int total_pop_bytes = align_up(sve_predicate_size_in_slots *
3280 VMRegImpl::stack_slot_size * count, 16);
3281 for (int i = count - 1; i >= 0; i--) {
3282 sve_ldr(as_PRegister(regs[i]), Address(stack, i));
3283 }
3284 add(stack, stack, total_pop_bytes);
3285 return total_pop_bytes / 8;
3286 }
3287
3288 #ifdef ASSERT
3289 void MacroAssembler::verify_heapbase(const char* msg) {
3290 #if 0
3291 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
3292 assert (Universe::heap() != nullptr, "java heap should be initialized");
3293 if (!UseCompressedOops || Universe::ptr_base() == nullptr) {
3294 // rheapbase is allocated as general register
3295 return;
3296 }
3297 if (CheckCompressedOops) {
3298 Label ok;
3299 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
3300 cmpptr(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3301 br(Assembler::EQ, ok);
3302 stop(msg);
3303 bind(ok);
3304 pop(1 << rscratch1->encoding(), sp);
3305 }
3306 #endif
3307 }
3308 #endif
3309
3310 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
3311 assert_different_registers(value, tmp1, tmp2);
3312 Label done, tagged, weak_tagged;
3313
3314 cbz(value, done); // Use null as-is.
3315 tst(value, JNIHandles::tag_mask); // Test for tag.
3316 br(Assembler::NE, tagged);
3317
3318 // Resolve local handle
3319 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2);
3320 verify_oop(value);
3321 b(done);
3322
3323 bind(tagged);
3324 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1);
3325 tbnz(value, 0, weak_tagged); // Test for weak tag.
3326
3327 // Resolve global handle
3328 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3329 verify_oop(value);
3330 b(done);
3331
3332 bind(weak_tagged);
3333 // Resolve jweak.
3334 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3335 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2);
3336 verify_oop(value);
3337
3338 bind(done);
3339 }
3340
3341 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) {
3342 assert_different_registers(value, tmp1, tmp2);
3343 Label done;
3344
3345 cbz(value, done); // Use null as-is.
3346
3347 #ifdef ASSERT
3348 {
3349 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10);
3350 Label valid_global_tag;
3351 tbnz(value, 1, valid_global_tag); // Test for global tag
3352 stop("non global jobject using resolve_global_jobject");
3353 bind(valid_global_tag);
3354 }
3355 #endif
3356
3357 // Resolve global handle
3358 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3359 verify_oop(value);
3360
3361 bind(done);
3362 }
3363
3364 void MacroAssembler::stop(const char* msg) {
3365 // Skip AOT caching C strings in scratch buffer.
3366 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
3367 BLOCK_COMMENT(str);
3368 // load msg into r0 so we can access it from the signal handler
3369 // ExternalAddress enables saving and restoring via the code cache
3370 lea(c_rarg0, ExternalAddress((address) str));
3371 dcps1(0xdeae);
3372 }
3373
3374 void MacroAssembler::unimplemented(const char* what) {
3375 const char* buf = nullptr;
3376 {
3377 ResourceMark rm;
3378 stringStream ss;
3379 ss.print("unimplemented: %s", what);
3380 buf = code_string(ss.as_string());
3381 }
3382 stop(buf);
3383 }
3384
3385 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
3386 #ifdef ASSERT
3387 Label OK;
3388 br(cc, OK);
3389 stop(msg);
3390 bind(OK);
3391 #endif
3392 }
3393
3394 // If a constant does not fit in an immediate field, generate some
3395 // number of MOV instructions and then perform the operation.
3396 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
3397 add_sub_imm_insn insn1,
3398 add_sub_reg_insn insn2,
3399 bool is32) {
3400 assert(Rd != zr, "Rd = zr and not setting flags?");
3401 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3402 if (fits) {
3403 (this->*insn1)(Rd, Rn, imm);
3404 } else {
3405 if (g_uabs(imm) < (1 << 24)) {
3406 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
3407 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
3408 } else {
3409 assert_different_registers(Rd, Rn);
3410 mov(Rd, imm);
3411 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3412 }
3413 }
3414 }
3415
3416 // Separate vsn which sets the flags. Optimisations are more restricted
3417 // because we must set the flags correctly.
3418 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
3419 add_sub_imm_insn insn1,
3420 add_sub_reg_insn insn2,
3421 bool is32) {
3422 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3423 if (fits) {
3424 (this->*insn1)(Rd, Rn, imm);
3425 } else {
3426 assert_different_registers(Rd, Rn);
3427 assert(Rd != zr, "overflow in immediate operand");
3428 mov(Rd, imm);
3429 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3430 }
3431 }
3432
3433
3434 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
3435 if (increment.is_register()) {
3436 add(Rd, Rn, increment.as_register());
3437 } else {
3438 add(Rd, Rn, increment.as_constant());
3439 }
3440 }
3441
3442 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
3443 if (increment.is_register()) {
3444 addw(Rd, Rn, increment.as_register());
3445 } else {
3446 addw(Rd, Rn, increment.as_constant());
3447 }
3448 }
3449
3450 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
3451 if (decrement.is_register()) {
3452 sub(Rd, Rn, decrement.as_register());
3453 } else {
3454 sub(Rd, Rn, decrement.as_constant());
3455 }
3456 }
3457
3458 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
3459 if (decrement.is_register()) {
3460 subw(Rd, Rn, decrement.as_register());
3461 } else {
3462 subw(Rd, Rn, decrement.as_constant());
3463 }
3464 }
3465
3466 void MacroAssembler::reinit_heapbase()
3467 {
3468 if (UseCompressedOops) {
3469 if (Universe::is_fully_initialized()) {
3470 mov(rheapbase, CompressedOops::base());
3471 } else {
3472 lea(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3473 ldr(rheapbase, Address(rheapbase));
3474 }
3475 }
3476 }
3477
3478 // A generic CAS; success or failure is in the EQ flag. A weak CAS
3479 // doesn't retry and may fail spuriously. If the oldval is wanted,
3480 // Pass a register for the result, otherwise pass noreg.
3481
3482 // Clobbers rscratch1
3483 void MacroAssembler::cmpxchg(Register addr, Register expected,
3484 Register new_val,
3485 enum operand_size size,
3486 bool acquire, bool release,
3487 bool weak,
3488 Register result) {
3489 if (result == noreg) result = rscratch1;
3490 BLOCK_COMMENT("cmpxchg {");
3491 if (UseLSE) {
3492 mov(result, expected);
3493 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
3494 compare_eq(result, expected, size);
3495 #ifdef ASSERT
3496 // Poison rscratch1 which is written on !UseLSE branch
3497 mov(rscratch1, 0x1f1f1f1f1f1f1f1f);
3498 #endif
3499 } else {
3500 Label retry_load, done;
3501 prfm(Address(addr), PSTL1STRM);
3502 bind(retry_load);
3503 load_exclusive(result, addr, size, acquire);
3504 compare_eq(result, expected, size);
3505 br(Assembler::NE, done);
3506 store_exclusive(rscratch1, new_val, addr, size, release);
3507 if (weak) {
3508 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
3509 } else {
3510 cbnzw(rscratch1, retry_load);
3511 }
3512 bind(done);
3513 }
3514 BLOCK_COMMENT("} cmpxchg");
3515 }
3516
3517 // A generic comparison. Only compares for equality, clobbers rscratch1.
3518 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
3519 if (size == xword) {
3520 cmp(rm, rn);
3521 } else if (size == word) {
3522 cmpw(rm, rn);
3523 } else if (size == halfword) {
3524 eorw(rscratch1, rm, rn);
3525 ands(zr, rscratch1, 0xffff);
3526 } else if (size == byte) {
3527 eorw(rscratch1, rm, rn);
3528 ands(zr, rscratch1, 0xff);
3529 } else {
3530 ShouldNotReachHere();
3531 }
3532 }
3533
3534
3535 static bool different(Register a, RegisterOrConstant b, Register c) {
3536 if (b.is_constant())
3537 return a != c;
3538 else
3539 return a != b.as_register() && a != c && b.as_register() != c;
3540 }
3541
3542 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
3543 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
3544 if (UseLSE) { \
3545 prev = prev->is_valid() ? prev : zr; \
3546 if (incr.is_register()) { \
3547 AOP(sz, incr.as_register(), prev, addr); \
3548 } else { \
3549 mov(rscratch2, incr.as_constant()); \
3550 AOP(sz, rscratch2, prev, addr); \
3551 } \
3552 return; \
3553 } \
3554 Register result = rscratch2; \
3555 if (prev->is_valid()) \
3556 result = different(prev, incr, addr) ? prev : rscratch2; \
3557 \
3558 Label retry_load; \
3559 prfm(Address(addr), PSTL1STRM); \
3560 bind(retry_load); \
3561 LDXR(result, addr); \
3562 OP(rscratch1, result, incr); \
3563 STXR(rscratch2, rscratch1, addr); \
3564 cbnzw(rscratch2, retry_load); \
3565 if (prev->is_valid() && prev != result) { \
3566 IOP(prev, rscratch1, incr); \
3567 } \
3568 }
3569
3570 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
3571 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
3572 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
3573 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
3574
3575 #undef ATOMIC_OP
3576
3577 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
3578 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
3579 if (UseLSE) { \
3580 prev = prev->is_valid() ? prev : zr; \
3581 AOP(sz, newv, prev, addr); \
3582 return; \
3583 } \
3584 Register result = rscratch2; \
3585 if (prev->is_valid()) \
3586 result = different(prev, newv, addr) ? prev : rscratch2; \
3587 \
3588 Label retry_load; \
3589 prfm(Address(addr), PSTL1STRM); \
3590 bind(retry_load); \
3591 LDXR(result, addr); \
3592 STXR(rscratch1, newv, addr); \
3593 cbnzw(rscratch1, retry_load); \
3594 if (prev->is_valid() && prev != result) \
3595 mov(prev, result); \
3596 }
3597
3598 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
3599 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
3600 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
3601 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
3602 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
3603 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
3604
3605 #undef ATOMIC_XCHG
3606
3607 #ifndef PRODUCT
3608 extern "C" void findpc(intptr_t x);
3609 #endif
3610
3611 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
3612 {
3613 // In order to get locks to work, we need to fake a in_VM state
3614 if (ShowMessageBoxOnError ) {
3615 JavaThread* thread = JavaThread::current();
3616 JavaThreadState saved_state = thread->thread_state();
3617 thread->set_thread_state(_thread_in_vm);
3618 #ifndef PRODUCT
3619 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
3620 ttyLocker ttyl;
3621 BytecodeCounter::print();
3622 }
3623 #endif
3624 if (os::message_box(msg, "Execution stopped, print registers?")) {
3625 ttyLocker ttyl;
3626 tty->print_cr(" pc = 0x%016" PRIx64, pc);
3627 #ifndef PRODUCT
3628 tty->cr();
3629 findpc(pc);
3630 tty->cr();
3631 #endif
3632 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
3633 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
3634 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
3635 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
3636 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
3637 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
3638 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
3639 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
3640 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
3641 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
3642 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
3643 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
3644 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
3645 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
3646 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
3647 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
3648 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
3649 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
3650 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
3651 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
3652 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
3653 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
3654 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
3655 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
3656 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
3657 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
3658 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
3659 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
3660 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
3661 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
3662 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
3663 BREAKPOINT;
3664 }
3665 }
3666 fatal("DEBUG MESSAGE: %s", msg);
3667 }
3668
3669 RegSet MacroAssembler::call_clobbered_gp_registers() {
3670 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
3671 #ifndef R18_RESERVED
3672 regs += r18_tls;
3673 #endif
3674 return regs;
3675 }
3676
3677 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
3678 int step = 4 * wordSize;
3679 push(call_clobbered_gp_registers() - exclude, sp);
3680 sub(sp, sp, step);
3681 mov(rscratch1, -step);
3682 // Push v0-v7, v16-v31.
3683 for (int i = 31; i>= 4; i -= 4) {
3684 if (i <= v7->encoding() || i >= v16->encoding())
3685 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
3686 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
3687 }
3688 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
3689 as_FloatRegister(3), T1D, Address(sp));
3690 }
3691
3692 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
3693 for (int i = 0; i < 32; i += 4) {
3694 if (i <= v7->encoding() || i >= v16->encoding())
3695 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3696 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
3697 }
3698
3699 reinitialize_ptrue();
3700
3701 pop(call_clobbered_gp_registers() - exclude, sp);
3702 }
3703
3704 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
3705 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3706 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
3707 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3708 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3709 for (int i = 0; i < FloatRegister::number_of_registers; i++) {
3710 sve_str(as_FloatRegister(i), Address(sp, i));
3711 }
3712 } else {
3713 int step = (save_vectors ? 8 : 4) * wordSize;
3714 mov(rscratch1, -step);
3715 sub(sp, sp, step);
3716 for (int i = 28; i >= 4; i -= 4) {
3717 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3718 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
3719 }
3720 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
3721 }
3722 if (save_vectors && use_sve && total_predicate_in_bytes > 0) {
3723 sub(sp, sp, total_predicate_in_bytes);
3724 for (int i = 0; i < PRegister::number_of_registers; i++) {
3725 sve_str(as_PRegister(i), Address(sp, i));
3726 }
3727 }
3728 }
3729
3730 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
3731 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3732 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) {
3733 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) {
3734 sve_ldr(as_PRegister(i), Address(sp, i));
3735 }
3736 add(sp, sp, total_predicate_in_bytes);
3737 }
3738 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3739 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) {
3740 sve_ldr(as_FloatRegister(i), Address(sp, i));
3741 }
3742 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3743 } else {
3744 int step = (restore_vectors ? 8 : 4) * wordSize;
3745 for (int i = 0; i <= 28; i += 4)
3746 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3747 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
3748 }
3749
3750 // We may use predicate registers and rely on ptrue with SVE,
3751 // regardless of wide vector (> 8 bytes) used or not.
3752 if (use_sve) {
3753 reinitialize_ptrue();
3754 }
3755
3756 // integer registers except lr & sp
3757 pop(RegSet::range(r0, r17), sp);
3758 #ifdef R18_RESERVED
3759 ldp(zr, r19, Address(post(sp, 2 * wordSize)));
3760 pop(RegSet::range(r20, r29), sp);
3761 #else
3762 pop(RegSet::range(r18_tls, r29), sp);
3763 #endif
3764 }
3765
3766 /**
3767 * Helpers for multiply_to_len().
3768 */
3769 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
3770 Register src1, Register src2) {
3771 adds(dest_lo, dest_lo, src1);
3772 adc(dest_hi, dest_hi, zr);
3773 adds(dest_lo, dest_lo, src2);
3774 adc(final_dest_hi, dest_hi, zr);
3775 }
3776
3777 // Generate an address from (r + r1 extend offset). "size" is the
3778 // size of the operand. The result may be in rscratch2.
3779 Address MacroAssembler::offsetted_address(Register r, Register r1,
3780 Address::extend ext, int offset, int size) {
3781 if (offset || (ext.shift() % size != 0)) {
3782 lea(rscratch2, Address(r, r1, ext));
3783 return Address(rscratch2, offset);
3784 } else {
3785 return Address(r, r1, ext);
3786 }
3787 }
3788
3789 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
3790 {
3791 assert(offset >= 0, "spill to negative address?");
3792 // Offset reachable ?
3793 // Not aligned - 9 bits signed offset
3794 // Aligned - 12 bits unsigned offset shifted
3795 Register base = sp;
3796 if ((offset & (size-1)) && offset >= (1<<8)) {
3797 add(tmp, base, offset & ((1<<12)-1));
3798 base = tmp;
3799 offset &= -1u<<12;
3800 }
3801
3802 if (offset >= (1<<12) * size) {
3803 add(tmp, base, offset & (((1<<12)-1)<<12));
3804 base = tmp;
3805 offset &= ~(((1<<12)-1)<<12);
3806 }
3807
3808 return Address(base, offset);
3809 }
3810
3811 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) {
3812 assert(offset >= 0, "spill to negative address?");
3813
3814 Register base = sp;
3815
3816 // An immediate offset in the range 0 to 255 which is multiplied
3817 // by the current vector or predicate register size in bytes.
3818 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) {
3819 return Address(base, offset / sve_reg_size_in_bytes);
3820 }
3821
3822 add(tmp, base, offset);
3823 return Address(tmp);
3824 }
3825
3826 // Checks whether offset is aligned.
3827 // Returns true if it is, else false.
3828 bool MacroAssembler::merge_alignment_check(Register base,
3829 size_t size,
3830 int64_t cur_offset,
3831 int64_t prev_offset) const {
3832 if (AvoidUnalignedAccesses) {
3833 if (base == sp) {
3834 // Checks whether low offset if aligned to pair of registers.
3835 int64_t pair_mask = size * 2 - 1;
3836 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3837 return (offset & pair_mask) == 0;
3838 } else { // If base is not sp, we can't guarantee the access is aligned.
3839 return false;
3840 }
3841 } else {
3842 int64_t mask = size - 1;
3843 // Load/store pair instruction only supports element size aligned offset.
3844 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
3845 }
3846 }
3847
3848 // Checks whether current and previous loads/stores can be merged.
3849 // Returns true if it can be merged, else false.
3850 bool MacroAssembler::ldst_can_merge(Register rt,
3851 const Address &adr,
3852 size_t cur_size_in_bytes,
3853 bool is_store) const {
3854 address prev = pc() - NativeInstruction::instruction_size;
3855 address last = code()->last_insn();
3856
3857 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) {
3858 return false;
3859 }
3860
3861 if (adr.getMode() != Address::base_plus_offset || prev != last) {
3862 return false;
3863 }
3864
3865 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3866 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
3867
3868 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
3869 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
3870
3871 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
3872 return false;
3873 }
3874
3875 int64_t max_offset = 63 * prev_size_in_bytes;
3876 int64_t min_offset = -64 * prev_size_in_bytes;
3877
3878 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
3879
3880 // Only same base can be merged.
3881 if (adr.base() != prev_ldst->base()) {
3882 return false;
3883 }
3884
3885 int64_t cur_offset = adr.offset();
3886 int64_t prev_offset = prev_ldst->offset();
3887 size_t diff = abs(cur_offset - prev_offset);
3888 if (diff != prev_size_in_bytes) {
3889 return false;
3890 }
3891
3892 // Following cases can not be merged:
3893 // ldr x2, [x2, #8]
3894 // ldr x3, [x2, #16]
3895 // or:
3896 // ldr x2, [x3, #8]
3897 // ldr x2, [x3, #16]
3898 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
3899 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
3900 return false;
3901 }
3902
3903 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3904 // Offset range must be in ldp/stp instruction's range.
3905 if (low_offset > max_offset || low_offset < min_offset) {
3906 return false;
3907 }
3908
3909 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
3910 return true;
3911 }
3912
3913 return false;
3914 }
3915
3916 // Merge current load/store with previous load/store into ldp/stp.
3917 void MacroAssembler::merge_ldst(Register rt,
3918 const Address &adr,
3919 size_t cur_size_in_bytes,
3920 bool is_store) {
3921
3922 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
3923
3924 Register rt_low, rt_high;
3925 address prev = pc() - NativeInstruction::instruction_size;
3926 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3927
3928 int64_t offset;
3929
3930 if (adr.offset() < prev_ldst->offset()) {
3931 offset = adr.offset();
3932 rt_low = rt;
3933 rt_high = prev_ldst->target();
3934 } else {
3935 offset = prev_ldst->offset();
3936 rt_low = prev_ldst->target();
3937 rt_high = rt;
3938 }
3939
3940 Address adr_p = Address(prev_ldst->base(), offset);
3941 // Overwrite previous generated binary.
3942 code_section()->set_end(prev);
3943
3944 const size_t sz = prev_ldst->size_in_bytes();
3945 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
3946 if (!is_store) {
3947 BLOCK_COMMENT("merged ldr pair");
3948 if (sz == 8) {
3949 ldp(rt_low, rt_high, adr_p);
3950 } else {
3951 ldpw(rt_low, rt_high, adr_p);
3952 }
3953 } else {
3954 BLOCK_COMMENT("merged str pair");
3955 if (sz == 8) {
3956 stp(rt_low, rt_high, adr_p);
3957 } else {
3958 stpw(rt_low, rt_high, adr_p);
3959 }
3960 }
3961 }
3962
3963 /**
3964 * Multiply 64 bit by 64 bit first loop.
3965 */
3966 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
3967 Register y, Register y_idx, Register z,
3968 Register carry, Register product,
3969 Register idx, Register kdx) {
3970 //
3971 // jlong carry, x[], y[], z[];
3972 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3973 // huge_128 product = y[idx] * x[xstart] + carry;
3974 // z[kdx] = (jlong)product;
3975 // carry = (jlong)(product >>> 64);
3976 // }
3977 // z[xstart] = carry;
3978 //
3979
3980 Label L_first_loop, L_first_loop_exit;
3981 Label L_one_x, L_one_y, L_multiply;
3982
3983 subsw(xstart, xstart, 1);
3984 br(Assembler::MI, L_one_x);
3985
3986 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
3987 ldr(x_xstart, Address(rscratch1));
3988 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
3989
3990 bind(L_first_loop);
3991 subsw(idx, idx, 1);
3992 br(Assembler::MI, L_first_loop_exit);
3993 subsw(idx, idx, 1);
3994 br(Assembler::MI, L_one_y);
3995 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3996 ldr(y_idx, Address(rscratch1));
3997 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
3998 bind(L_multiply);
3999
4000 // AArch64 has a multiply-accumulate instruction that we can't use
4001 // here because it has no way to process carries, so we have to use
4002 // separate add and adc instructions. Bah.
4003 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
4004 mul(product, x_xstart, y_idx);
4005 adds(product, product, carry);
4006 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
4007
4008 subw(kdx, kdx, 2);
4009 ror(product, product, 32); // back to big-endian
4010 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
4011
4012 b(L_first_loop);
4013
4014 bind(L_one_y);
4015 ldrw(y_idx, Address(y, 0));
4016 b(L_multiply);
4017
4018 bind(L_one_x);
4019 ldrw(x_xstart, Address(x, 0));
4020 b(L_first_loop);
4021
4022 bind(L_first_loop_exit);
4023 }
4024
4025 /**
4026 * Multiply 128 bit by 128. Unrolled inner loop.
4027 *
4028 */
4029 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
4030 Register carry, Register carry2,
4031 Register idx, Register jdx,
4032 Register yz_idx1, Register yz_idx2,
4033 Register tmp, Register tmp3, Register tmp4,
4034 Register tmp6, Register product_hi) {
4035
4036 // jlong carry, x[], y[], z[];
4037 // int kdx = ystart+1;
4038 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
4039 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
4040 // jlong carry2 = (jlong)(tmp3 >>> 64);
4041 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
4042 // carry = (jlong)(tmp4 >>> 64);
4043 // z[kdx+idx+1] = (jlong)tmp3;
4044 // z[kdx+idx] = (jlong)tmp4;
4045 // }
4046 // idx += 2;
4047 // if (idx > 0) {
4048 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
4049 // z[kdx+idx] = (jlong)yz_idx1;
4050 // carry = (jlong)(yz_idx1 >>> 64);
4051 // }
4052 //
4053
4054 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
4055
4056 lsrw(jdx, idx, 2);
4057
4058 bind(L_third_loop);
4059
4060 subsw(jdx, jdx, 1);
4061 br(Assembler::MI, L_third_loop_exit);
4062 subw(idx, idx, 4);
4063
4064 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4065
4066 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
4067
4068 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4069
4070 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
4071 ror(yz_idx2, yz_idx2, 32);
4072
4073 ldp(rscratch2, rscratch1, Address(tmp6, 0));
4074
4075 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4076 umulh(tmp4, product_hi, yz_idx1);
4077
4078 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
4079 ror(rscratch2, rscratch2, 32);
4080
4081 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
4082 umulh(carry2, product_hi, yz_idx2);
4083
4084 // propagate sum of both multiplications into carry:tmp4:tmp3
4085 adds(tmp3, tmp3, carry);
4086 adc(tmp4, tmp4, zr);
4087 adds(tmp3, tmp3, rscratch1);
4088 adcs(tmp4, tmp4, tmp);
4089 adc(carry, carry2, zr);
4090 adds(tmp4, tmp4, rscratch2);
4091 adc(carry, carry, zr);
4092
4093 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
4094 ror(tmp4, tmp4, 32);
4095 stp(tmp4, tmp3, Address(tmp6, 0));
4096
4097 b(L_third_loop);
4098 bind (L_third_loop_exit);
4099
4100 andw (idx, idx, 0x3);
4101 cbz(idx, L_post_third_loop_done);
4102
4103 Label L_check_1;
4104 subsw(idx, idx, 2);
4105 br(Assembler::MI, L_check_1);
4106
4107 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4108 ldr(yz_idx1, Address(rscratch1, 0));
4109 ror(yz_idx1, yz_idx1, 32);
4110 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4111 umulh(tmp4, product_hi, yz_idx1);
4112 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4113 ldr(yz_idx2, Address(rscratch1, 0));
4114 ror(yz_idx2, yz_idx2, 32);
4115
4116 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
4117
4118 ror(tmp3, tmp3, 32);
4119 str(tmp3, Address(rscratch1, 0));
4120
4121 bind (L_check_1);
4122
4123 andw (idx, idx, 0x1);
4124 subsw(idx, idx, 1);
4125 br(Assembler::MI, L_post_third_loop_done);
4126 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4127 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
4128 umulh(carry2, tmp4, product_hi);
4129 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4130
4131 add2_with_carry(carry2, tmp3, tmp4, carry);
4132
4133 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4134 extr(carry, carry2, tmp3, 32);
4135
4136 bind(L_post_third_loop_done);
4137 }
4138
4139 /**
4140 * Code for BigInteger::multiplyToLen() intrinsic.
4141 *
4142 * r0: x
4143 * r1: xlen
4144 * r2: y
4145 * r3: ylen
4146 * r4: z
4147 * r5: tmp0
4148 * r10: tmp1
4149 * r11: tmp2
4150 * r12: tmp3
4151 * r13: tmp4
4152 * r14: tmp5
4153 * r15: tmp6
4154 * r16: tmp7
4155 *
4156 */
4157 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
4158 Register z, Register tmp0,
4159 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
4160 Register tmp5, Register tmp6, Register product_hi) {
4161
4162 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, product_hi);
4163
4164 const Register idx = tmp1;
4165 const Register kdx = tmp2;
4166 const Register xstart = tmp3;
4167
4168 const Register y_idx = tmp4;
4169 const Register carry = tmp5;
4170 const Register product = xlen;
4171 const Register x_xstart = tmp0;
4172
4173 // First Loop.
4174 //
4175 // final static long LONG_MASK = 0xffffffffL;
4176 // int xstart = xlen - 1;
4177 // int ystart = ylen - 1;
4178 // long carry = 0;
4179 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4180 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
4181 // z[kdx] = (int)product;
4182 // carry = product >>> 32;
4183 // }
4184 // z[xstart] = (int)carry;
4185 //
4186
4187 movw(idx, ylen); // idx = ylen;
4188 addw(kdx, xlen, ylen); // kdx = xlen+ylen;
4189 mov(carry, zr); // carry = 0;
4190
4191 Label L_done;
4192
4193 movw(xstart, xlen);
4194 subsw(xstart, xstart, 1);
4195 br(Assembler::MI, L_done);
4196
4197 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
4198
4199 Label L_second_loop;
4200 cbzw(kdx, L_second_loop);
4201
4202 Label L_carry;
4203 subw(kdx, kdx, 1);
4204 cbzw(kdx, L_carry);
4205
4206 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4207 lsr(carry, carry, 32);
4208 subw(kdx, kdx, 1);
4209
4210 bind(L_carry);
4211 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4212
4213 // Second and third (nested) loops.
4214 //
4215 // for (int i = xstart-1; i >= 0; i--) { // Second loop
4216 // carry = 0;
4217 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
4218 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
4219 // (z[k] & LONG_MASK) + carry;
4220 // z[k] = (int)product;
4221 // carry = product >>> 32;
4222 // }
4223 // z[i] = (int)carry;
4224 // }
4225 //
4226 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
4227
4228 const Register jdx = tmp1;
4229
4230 bind(L_second_loop);
4231 mov(carry, zr); // carry = 0;
4232 movw(jdx, ylen); // j = ystart+1
4233
4234 subsw(xstart, xstart, 1); // i = xstart-1;
4235 br(Assembler::MI, L_done);
4236
4237 str(z, Address(pre(sp, -4 * wordSize)));
4238
4239 Label L_last_x;
4240 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
4241 subsw(xstart, xstart, 1); // i = xstart-1;
4242 br(Assembler::MI, L_last_x);
4243
4244 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
4245 ldr(product_hi, Address(rscratch1));
4246 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
4247
4248 Label L_third_loop_prologue;
4249 bind(L_third_loop_prologue);
4250
4251 str(ylen, Address(sp, wordSize));
4252 stp(x, xstart, Address(sp, 2 * wordSize));
4253 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
4254 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
4255 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
4256 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
4257
4258 addw(tmp3, xlen, 1);
4259 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4260 subsw(tmp3, tmp3, 1);
4261 br(Assembler::MI, L_done);
4262
4263 lsr(carry, carry, 32);
4264 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4265 b(L_second_loop);
4266
4267 // Next infrequent code is moved outside loops.
4268 bind(L_last_x);
4269 ldrw(product_hi, Address(x, 0));
4270 b(L_third_loop_prologue);
4271
4272 bind(L_done);
4273 }
4274
4275 // Code for BigInteger::mulAdd intrinsic
4276 // out = r0
4277 // in = r1
4278 // offset = r2 (already out.length-offset)
4279 // len = r3
4280 // k = r4
4281 //
4282 // pseudo code from java implementation:
4283 // carry = 0;
4284 // offset = out.length-offset - 1;
4285 // for (int j=len-1; j >= 0; j--) {
4286 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
4287 // out[offset--] = (int)product;
4288 // carry = product >>> 32;
4289 // }
4290 // return (int)carry;
4291 void MacroAssembler::mul_add(Register out, Register in, Register offset,
4292 Register len, Register k) {
4293 Label LOOP, END;
4294 // pre-loop
4295 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
4296 csel(out, zr, out, Assembler::EQ);
4297 br(Assembler::EQ, END);
4298 add(in, in, len, LSL, 2); // in[j+1] address
4299 add(offset, out, offset, LSL, 2); // out[offset + 1] address
4300 mov(out, zr); // used to keep carry now
4301 BIND(LOOP);
4302 ldrw(rscratch1, Address(pre(in, -4)));
4303 madd(rscratch1, rscratch1, k, out);
4304 ldrw(rscratch2, Address(pre(offset, -4)));
4305 add(rscratch1, rscratch1, rscratch2);
4306 strw(rscratch1, Address(offset));
4307 lsr(out, rscratch1, 32);
4308 subs(len, len, 1);
4309 br(Assembler::NE, LOOP);
4310 BIND(END);
4311 }
4312
4313 /**
4314 * Emits code to update CRC-32 with a byte value according to constants in table
4315 *
4316 * @param [in,out]crc Register containing the crc.
4317 * @param [in]val Register containing the byte to fold into the CRC.
4318 * @param [in]table Register containing the table of crc constants.
4319 *
4320 * uint32_t crc;
4321 * val = crc_table[(val ^ crc) & 0xFF];
4322 * crc = val ^ (crc >> 8);
4323 *
4324 */
4325 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4326 eor(val, val, crc);
4327 andr(val, val, 0xff);
4328 ldrw(val, Address(table, val, Address::lsl(2)));
4329 eor(crc, val, crc, Assembler::LSR, 8);
4330 }
4331
4332 /**
4333 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
4334 *
4335 * @param [in,out]crc Register containing the crc.
4336 * @param [in]v Register containing the 32-bit to fold into the CRC.
4337 * @param [in]table0 Register containing table 0 of crc constants.
4338 * @param [in]table1 Register containing table 1 of crc constants.
4339 * @param [in]table2 Register containing table 2 of crc constants.
4340 * @param [in]table3 Register containing table 3 of crc constants.
4341 *
4342 * uint32_t crc;
4343 * v = crc ^ v
4344 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
4345 *
4346 */
4347 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
4348 Register table0, Register table1, Register table2, Register table3,
4349 bool upper) {
4350 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
4351 uxtb(tmp, v);
4352 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
4353 ubfx(tmp, v, 8, 8);
4354 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
4355 eor(crc, crc, tmp);
4356 ubfx(tmp, v, 16, 8);
4357 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
4358 eor(crc, crc, tmp);
4359 ubfx(tmp, v, 24, 8);
4360 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
4361 eor(crc, crc, tmp);
4362 }
4363
4364 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf,
4365 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4366 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4367 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4368
4369 subs(tmp0, len, 384);
4370 mvnw(crc, crc);
4371 br(Assembler::GE, CRC_by128_pre);
4372 BIND(CRC_less128);
4373 subs(len, len, 32);
4374 br(Assembler::GE, CRC_by32_loop);
4375 BIND(CRC_less32);
4376 adds(len, len, 32 - 4);
4377 br(Assembler::GE, CRC_by4_loop);
4378 adds(len, len, 4);
4379 br(Assembler::GT, CRC_by1_loop);
4380 b(L_exit);
4381
4382 BIND(CRC_by32_loop);
4383 ldp(tmp0, tmp1, Address(buf));
4384 crc32x(crc, crc, tmp0);
4385 ldp(tmp2, tmp3, Address(buf, 16));
4386 crc32x(crc, crc, tmp1);
4387 add(buf, buf, 32);
4388 crc32x(crc, crc, tmp2);
4389 subs(len, len, 32);
4390 crc32x(crc, crc, tmp3);
4391 br(Assembler::GE, CRC_by32_loop);
4392 cmn(len, (u1)32);
4393 br(Assembler::NE, CRC_less32);
4394 b(L_exit);
4395
4396 BIND(CRC_by4_loop);
4397 ldrw(tmp0, Address(post(buf, 4)));
4398 subs(len, len, 4);
4399 crc32w(crc, crc, tmp0);
4400 br(Assembler::GE, CRC_by4_loop);
4401 adds(len, len, 4);
4402 br(Assembler::LE, L_exit);
4403 BIND(CRC_by1_loop);
4404 ldrb(tmp0, Address(post(buf, 1)));
4405 subs(len, len, 1);
4406 crc32b(crc, crc, tmp0);
4407 br(Assembler::GT, CRC_by1_loop);
4408 b(L_exit);
4409
4410 BIND(CRC_by128_pre);
4411 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4412 4*256*sizeof(juint) + 8*sizeof(juint));
4413 mov(crc, 0);
4414 crc32x(crc, crc, tmp0);
4415 crc32x(crc, crc, tmp1);
4416
4417 cbnz(len, CRC_less128);
4418
4419 BIND(L_exit);
4420 mvnw(crc, crc);
4421 }
4422
4423 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
4424 Register len, Register tmp0, Register tmp1, Register tmp2,
4425 Register tmp3) {
4426 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4427 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4428
4429 mvnw(crc, crc);
4430
4431 subs(len, len, 128);
4432 br(Assembler::GE, CRC_by64_pre);
4433 BIND(CRC_less64);
4434 adds(len, len, 128-32);
4435 br(Assembler::GE, CRC_by32_loop);
4436 BIND(CRC_less32);
4437 adds(len, len, 32-4);
4438 br(Assembler::GE, CRC_by4_loop);
4439 adds(len, len, 4);
4440 br(Assembler::GT, CRC_by1_loop);
4441 b(L_exit);
4442
4443 BIND(CRC_by32_loop);
4444 ldp(tmp0, tmp1, Address(post(buf, 16)));
4445 subs(len, len, 32);
4446 crc32x(crc, crc, tmp0);
4447 ldr(tmp2, Address(post(buf, 8)));
4448 crc32x(crc, crc, tmp1);
4449 ldr(tmp3, Address(post(buf, 8)));
4450 crc32x(crc, crc, tmp2);
4451 crc32x(crc, crc, tmp3);
4452 br(Assembler::GE, CRC_by32_loop);
4453 cmn(len, (u1)32);
4454 br(Assembler::NE, CRC_less32);
4455 b(L_exit);
4456
4457 BIND(CRC_by4_loop);
4458 ldrw(tmp0, Address(post(buf, 4)));
4459 subs(len, len, 4);
4460 crc32w(crc, crc, tmp0);
4461 br(Assembler::GE, CRC_by4_loop);
4462 adds(len, len, 4);
4463 br(Assembler::LE, L_exit);
4464 BIND(CRC_by1_loop);
4465 ldrb(tmp0, Address(post(buf, 1)));
4466 subs(len, len, 1);
4467 crc32b(crc, crc, tmp0);
4468 br(Assembler::GT, CRC_by1_loop);
4469 b(L_exit);
4470
4471 BIND(CRC_by64_pre);
4472 sub(buf, buf, 8);
4473 ldp(tmp0, tmp1, Address(buf, 8));
4474 crc32x(crc, crc, tmp0);
4475 ldr(tmp2, Address(buf, 24));
4476 crc32x(crc, crc, tmp1);
4477 ldr(tmp3, Address(buf, 32));
4478 crc32x(crc, crc, tmp2);
4479 ldr(tmp0, Address(buf, 40));
4480 crc32x(crc, crc, tmp3);
4481 ldr(tmp1, Address(buf, 48));
4482 crc32x(crc, crc, tmp0);
4483 ldr(tmp2, Address(buf, 56));
4484 crc32x(crc, crc, tmp1);
4485 ldr(tmp3, Address(pre(buf, 64)));
4486
4487 b(CRC_by64_loop);
4488
4489 align(CodeEntryAlignment);
4490 BIND(CRC_by64_loop);
4491 subs(len, len, 64);
4492 crc32x(crc, crc, tmp2);
4493 ldr(tmp0, Address(buf, 8));
4494 crc32x(crc, crc, tmp3);
4495 ldr(tmp1, Address(buf, 16));
4496 crc32x(crc, crc, tmp0);
4497 ldr(tmp2, Address(buf, 24));
4498 crc32x(crc, crc, tmp1);
4499 ldr(tmp3, Address(buf, 32));
4500 crc32x(crc, crc, tmp2);
4501 ldr(tmp0, Address(buf, 40));
4502 crc32x(crc, crc, tmp3);
4503 ldr(tmp1, Address(buf, 48));
4504 crc32x(crc, crc, tmp0);
4505 ldr(tmp2, Address(buf, 56));
4506 crc32x(crc, crc, tmp1);
4507 ldr(tmp3, Address(pre(buf, 64)));
4508 br(Assembler::GE, CRC_by64_loop);
4509
4510 // post-loop
4511 crc32x(crc, crc, tmp2);
4512 crc32x(crc, crc, tmp3);
4513
4514 sub(len, len, 64);
4515 add(buf, buf, 8);
4516 cmn(len, (u1)128);
4517 br(Assembler::NE, CRC_less64);
4518 BIND(L_exit);
4519 mvnw(crc, crc);
4520 }
4521
4522 /**
4523 * @param crc register containing existing CRC (32-bit)
4524 * @param buf register pointing to input byte buffer (byte*)
4525 * @param len register containing number of bytes
4526 * @param table register that will contain address of CRC table
4527 * @param tmp scratch register
4528 */
4529 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
4530 Register table0, Register table1, Register table2, Register table3,
4531 Register tmp, Register tmp2, Register tmp3) {
4532 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
4533
4534 if (UseCryptoPmullForCRC32) {
4535 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4536 return;
4537 }
4538
4539 if (UseCRC32) {
4540 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
4541 return;
4542 }
4543
4544 mvnw(crc, crc);
4545
4546 {
4547 uint64_t offset;
4548 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4549 add(table0, table0, offset);
4550 }
4551 add(table1, table0, 1*256*sizeof(juint));
4552 add(table2, table0, 2*256*sizeof(juint));
4553 add(table3, table0, 3*256*sizeof(juint));
4554
4555 { // Neon code start
4556 cmp(len, (u1)64);
4557 br(Assembler::LT, L_by16);
4558 eor(v16, T16B, v16, v16);
4559
4560 Label L_fold;
4561
4562 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
4563
4564 ld1(v0, v1, T2D, post(buf, 32));
4565 ld1r(v4, T2D, post(tmp, 8));
4566 ld1r(v5, T2D, post(tmp, 8));
4567 ld1r(v6, T2D, post(tmp, 8));
4568 ld1r(v7, T2D, post(tmp, 8));
4569 mov(v16, S, 0, crc);
4570
4571 eor(v0, T16B, v0, v16);
4572 sub(len, len, 64);
4573
4574 BIND(L_fold);
4575 pmull(v22, T8H, v0, v5, T8B);
4576 pmull(v20, T8H, v0, v7, T8B);
4577 pmull(v23, T8H, v0, v4, T8B);
4578 pmull(v21, T8H, v0, v6, T8B);
4579
4580 pmull2(v18, T8H, v0, v5, T16B);
4581 pmull2(v16, T8H, v0, v7, T16B);
4582 pmull2(v19, T8H, v0, v4, T16B);
4583 pmull2(v17, T8H, v0, v6, T16B);
4584
4585 uzp1(v24, T8H, v20, v22);
4586 uzp2(v25, T8H, v20, v22);
4587 eor(v20, T16B, v24, v25);
4588
4589 uzp1(v26, T8H, v16, v18);
4590 uzp2(v27, T8H, v16, v18);
4591 eor(v16, T16B, v26, v27);
4592
4593 ushll2(v22, T4S, v20, T8H, 8);
4594 ushll(v20, T4S, v20, T4H, 8);
4595
4596 ushll2(v18, T4S, v16, T8H, 8);
4597 ushll(v16, T4S, v16, T4H, 8);
4598
4599 eor(v22, T16B, v23, v22);
4600 eor(v18, T16B, v19, v18);
4601 eor(v20, T16B, v21, v20);
4602 eor(v16, T16B, v17, v16);
4603
4604 uzp1(v17, T2D, v16, v20);
4605 uzp2(v21, T2D, v16, v20);
4606 eor(v17, T16B, v17, v21);
4607
4608 ushll2(v20, T2D, v17, T4S, 16);
4609 ushll(v16, T2D, v17, T2S, 16);
4610
4611 eor(v20, T16B, v20, v22);
4612 eor(v16, T16B, v16, v18);
4613
4614 uzp1(v17, T2D, v20, v16);
4615 uzp2(v21, T2D, v20, v16);
4616 eor(v28, T16B, v17, v21);
4617
4618 pmull(v22, T8H, v1, v5, T8B);
4619 pmull(v20, T8H, v1, v7, T8B);
4620 pmull(v23, T8H, v1, v4, T8B);
4621 pmull(v21, T8H, v1, v6, T8B);
4622
4623 pmull2(v18, T8H, v1, v5, T16B);
4624 pmull2(v16, T8H, v1, v7, T16B);
4625 pmull2(v19, T8H, v1, v4, T16B);
4626 pmull2(v17, T8H, v1, v6, T16B);
4627
4628 ld1(v0, v1, T2D, post(buf, 32));
4629
4630 uzp1(v24, T8H, v20, v22);
4631 uzp2(v25, T8H, v20, v22);
4632 eor(v20, T16B, v24, v25);
4633
4634 uzp1(v26, T8H, v16, v18);
4635 uzp2(v27, T8H, v16, v18);
4636 eor(v16, T16B, v26, v27);
4637
4638 ushll2(v22, T4S, v20, T8H, 8);
4639 ushll(v20, T4S, v20, T4H, 8);
4640
4641 ushll2(v18, T4S, v16, T8H, 8);
4642 ushll(v16, T4S, v16, T4H, 8);
4643
4644 eor(v22, T16B, v23, v22);
4645 eor(v18, T16B, v19, v18);
4646 eor(v20, T16B, v21, v20);
4647 eor(v16, T16B, v17, v16);
4648
4649 uzp1(v17, T2D, v16, v20);
4650 uzp2(v21, T2D, v16, v20);
4651 eor(v16, T16B, v17, v21);
4652
4653 ushll2(v20, T2D, v16, T4S, 16);
4654 ushll(v16, T2D, v16, T2S, 16);
4655
4656 eor(v20, T16B, v22, v20);
4657 eor(v16, T16B, v16, v18);
4658
4659 uzp1(v17, T2D, v20, v16);
4660 uzp2(v21, T2D, v20, v16);
4661 eor(v20, T16B, v17, v21);
4662
4663 shl(v16, T2D, v28, 1);
4664 shl(v17, T2D, v20, 1);
4665
4666 eor(v0, T16B, v0, v16);
4667 eor(v1, T16B, v1, v17);
4668
4669 subs(len, len, 32);
4670 br(Assembler::GE, L_fold);
4671
4672 mov(crc, 0);
4673 mov(tmp, v0, D, 0);
4674 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4675 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4676 mov(tmp, v0, D, 1);
4677 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4678 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4679 mov(tmp, v1, D, 0);
4680 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4681 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4682 mov(tmp, v1, D, 1);
4683 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4684 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4685
4686 add(len, len, 32);
4687 } // Neon code end
4688
4689 BIND(L_by16);
4690 subs(len, len, 16);
4691 br(Assembler::GE, L_by16_loop);
4692 adds(len, len, 16-4);
4693 br(Assembler::GE, L_by4_loop);
4694 adds(len, len, 4);
4695 br(Assembler::GT, L_by1_loop);
4696 b(L_exit);
4697
4698 BIND(L_by4_loop);
4699 ldrw(tmp, Address(post(buf, 4)));
4700 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
4701 subs(len, len, 4);
4702 br(Assembler::GE, L_by4_loop);
4703 adds(len, len, 4);
4704 br(Assembler::LE, L_exit);
4705 BIND(L_by1_loop);
4706 subs(len, len, 1);
4707 ldrb(tmp, Address(post(buf, 1)));
4708 update_byte_crc32(crc, tmp, table0);
4709 br(Assembler::GT, L_by1_loop);
4710 b(L_exit);
4711
4712 align(CodeEntryAlignment);
4713 BIND(L_by16_loop);
4714 subs(len, len, 16);
4715 ldp(tmp, tmp3, Address(post(buf, 16)));
4716 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4717 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4718 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
4719 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
4720 br(Assembler::GE, L_by16_loop);
4721 adds(len, len, 16-4);
4722 br(Assembler::GE, L_by4_loop);
4723 adds(len, len, 4);
4724 br(Assembler::GT, L_by1_loop);
4725 BIND(L_exit);
4726 mvnw(crc, crc);
4727 }
4728
4729 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
4730 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4731 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4732 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4733
4734 subs(tmp0, len, 384);
4735 br(Assembler::GE, CRC_by128_pre);
4736 BIND(CRC_less128);
4737 subs(len, len, 32);
4738 br(Assembler::GE, CRC_by32_loop);
4739 BIND(CRC_less32);
4740 adds(len, len, 32 - 4);
4741 br(Assembler::GE, CRC_by4_loop);
4742 adds(len, len, 4);
4743 br(Assembler::GT, CRC_by1_loop);
4744 b(L_exit);
4745
4746 BIND(CRC_by32_loop);
4747 ldp(tmp0, tmp1, Address(buf));
4748 crc32cx(crc, crc, tmp0);
4749 ldr(tmp2, Address(buf, 16));
4750 crc32cx(crc, crc, tmp1);
4751 ldr(tmp3, Address(buf, 24));
4752 crc32cx(crc, crc, tmp2);
4753 add(buf, buf, 32);
4754 subs(len, len, 32);
4755 crc32cx(crc, crc, tmp3);
4756 br(Assembler::GE, CRC_by32_loop);
4757 cmn(len, (u1)32);
4758 br(Assembler::NE, CRC_less32);
4759 b(L_exit);
4760
4761 BIND(CRC_by4_loop);
4762 ldrw(tmp0, Address(post(buf, 4)));
4763 subs(len, len, 4);
4764 crc32cw(crc, crc, tmp0);
4765 br(Assembler::GE, CRC_by4_loop);
4766 adds(len, len, 4);
4767 br(Assembler::LE, L_exit);
4768 BIND(CRC_by1_loop);
4769 ldrb(tmp0, Address(post(buf, 1)));
4770 subs(len, len, 1);
4771 crc32cb(crc, crc, tmp0);
4772 br(Assembler::GT, CRC_by1_loop);
4773 b(L_exit);
4774
4775 BIND(CRC_by128_pre);
4776 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4777 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50);
4778 mov(crc, 0);
4779 crc32cx(crc, crc, tmp0);
4780 crc32cx(crc, crc, tmp1);
4781
4782 cbnz(len, CRC_less128);
4783
4784 BIND(L_exit);
4785 }
4786
4787 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
4788 Register len, Register tmp0, Register tmp1, Register tmp2,
4789 Register tmp3) {
4790 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4791 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4792
4793 subs(len, len, 128);
4794 br(Assembler::GE, CRC_by64_pre);
4795 BIND(CRC_less64);
4796 adds(len, len, 128-32);
4797 br(Assembler::GE, CRC_by32_loop);
4798 BIND(CRC_less32);
4799 adds(len, len, 32-4);
4800 br(Assembler::GE, CRC_by4_loop);
4801 adds(len, len, 4);
4802 br(Assembler::GT, CRC_by1_loop);
4803 b(L_exit);
4804
4805 BIND(CRC_by32_loop);
4806 ldp(tmp0, tmp1, Address(post(buf, 16)));
4807 subs(len, len, 32);
4808 crc32cx(crc, crc, tmp0);
4809 ldr(tmp2, Address(post(buf, 8)));
4810 crc32cx(crc, crc, tmp1);
4811 ldr(tmp3, Address(post(buf, 8)));
4812 crc32cx(crc, crc, tmp2);
4813 crc32cx(crc, crc, tmp3);
4814 br(Assembler::GE, CRC_by32_loop);
4815 cmn(len, (u1)32);
4816 br(Assembler::NE, CRC_less32);
4817 b(L_exit);
4818
4819 BIND(CRC_by4_loop);
4820 ldrw(tmp0, Address(post(buf, 4)));
4821 subs(len, len, 4);
4822 crc32cw(crc, crc, tmp0);
4823 br(Assembler::GE, CRC_by4_loop);
4824 adds(len, len, 4);
4825 br(Assembler::LE, L_exit);
4826 BIND(CRC_by1_loop);
4827 ldrb(tmp0, Address(post(buf, 1)));
4828 subs(len, len, 1);
4829 crc32cb(crc, crc, tmp0);
4830 br(Assembler::GT, CRC_by1_loop);
4831 b(L_exit);
4832
4833 BIND(CRC_by64_pre);
4834 sub(buf, buf, 8);
4835 ldp(tmp0, tmp1, Address(buf, 8));
4836 crc32cx(crc, crc, tmp0);
4837 ldr(tmp2, Address(buf, 24));
4838 crc32cx(crc, crc, tmp1);
4839 ldr(tmp3, Address(buf, 32));
4840 crc32cx(crc, crc, tmp2);
4841 ldr(tmp0, Address(buf, 40));
4842 crc32cx(crc, crc, tmp3);
4843 ldr(tmp1, Address(buf, 48));
4844 crc32cx(crc, crc, tmp0);
4845 ldr(tmp2, Address(buf, 56));
4846 crc32cx(crc, crc, tmp1);
4847 ldr(tmp3, Address(pre(buf, 64)));
4848
4849 b(CRC_by64_loop);
4850
4851 align(CodeEntryAlignment);
4852 BIND(CRC_by64_loop);
4853 subs(len, len, 64);
4854 crc32cx(crc, crc, tmp2);
4855 ldr(tmp0, Address(buf, 8));
4856 crc32cx(crc, crc, tmp3);
4857 ldr(tmp1, Address(buf, 16));
4858 crc32cx(crc, crc, tmp0);
4859 ldr(tmp2, Address(buf, 24));
4860 crc32cx(crc, crc, tmp1);
4861 ldr(tmp3, Address(buf, 32));
4862 crc32cx(crc, crc, tmp2);
4863 ldr(tmp0, Address(buf, 40));
4864 crc32cx(crc, crc, tmp3);
4865 ldr(tmp1, Address(buf, 48));
4866 crc32cx(crc, crc, tmp0);
4867 ldr(tmp2, Address(buf, 56));
4868 crc32cx(crc, crc, tmp1);
4869 ldr(tmp3, Address(pre(buf, 64)));
4870 br(Assembler::GE, CRC_by64_loop);
4871
4872 // post-loop
4873 crc32cx(crc, crc, tmp2);
4874 crc32cx(crc, crc, tmp3);
4875
4876 sub(len, len, 64);
4877 add(buf, buf, 8);
4878 cmn(len, (u1)128);
4879 br(Assembler::NE, CRC_less64);
4880 BIND(L_exit);
4881 }
4882
4883 /**
4884 * @param crc register containing existing CRC (32-bit)
4885 * @param buf register pointing to input byte buffer (byte*)
4886 * @param len register containing number of bytes
4887 * @param table register that will contain address of CRC table
4888 * @param tmp scratch register
4889 */
4890 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
4891 Register table0, Register table1, Register table2, Register table3,
4892 Register tmp, Register tmp2, Register tmp3) {
4893 if (UseCryptoPmullForCRC32) {
4894 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4895 } else {
4896 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
4897 }
4898 }
4899
4900 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
4901 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) {
4902 Label CRC_by128_loop;
4903 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4904
4905 sub(len, len, 256);
4906 Register table = tmp0;
4907 {
4908 uint64_t offset;
4909 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4910 add(table, table, offset);
4911 }
4912 add(table, table, table_offset);
4913
4914 // Registers v0..v7 are used as data registers.
4915 // Registers v16..v31 are used as tmp registers.
4916 sub(buf, buf, 0x10);
4917 ldrq(v0, Address(buf, 0x10));
4918 ldrq(v1, Address(buf, 0x20));
4919 ldrq(v2, Address(buf, 0x30));
4920 ldrq(v3, Address(buf, 0x40));
4921 ldrq(v4, Address(buf, 0x50));
4922 ldrq(v5, Address(buf, 0x60));
4923 ldrq(v6, Address(buf, 0x70));
4924 ldrq(v7, Address(pre(buf, 0x80)));
4925
4926 movi(v31, T4S, 0);
4927 mov(v31, S, 0, crc);
4928 eor(v0, T16B, v0, v31);
4929
4930 // Register v16 contains constants from the crc table.
4931 ldrq(v16, Address(table));
4932 b(CRC_by128_loop);
4933
4934 align(OptoLoopAlignment);
4935 BIND(CRC_by128_loop);
4936 pmull (v17, T1Q, v0, v16, T1D);
4937 pmull2(v18, T1Q, v0, v16, T2D);
4938 ldrq(v0, Address(buf, 0x10));
4939 eor3(v0, T16B, v17, v18, v0);
4940
4941 pmull (v19, T1Q, v1, v16, T1D);
4942 pmull2(v20, T1Q, v1, v16, T2D);
4943 ldrq(v1, Address(buf, 0x20));
4944 eor3(v1, T16B, v19, v20, v1);
4945
4946 pmull (v21, T1Q, v2, v16, T1D);
4947 pmull2(v22, T1Q, v2, v16, T2D);
4948 ldrq(v2, Address(buf, 0x30));
4949 eor3(v2, T16B, v21, v22, v2);
4950
4951 pmull (v23, T1Q, v3, v16, T1D);
4952 pmull2(v24, T1Q, v3, v16, T2D);
4953 ldrq(v3, Address(buf, 0x40));
4954 eor3(v3, T16B, v23, v24, v3);
4955
4956 pmull (v25, T1Q, v4, v16, T1D);
4957 pmull2(v26, T1Q, v4, v16, T2D);
4958 ldrq(v4, Address(buf, 0x50));
4959 eor3(v4, T16B, v25, v26, v4);
4960
4961 pmull (v27, T1Q, v5, v16, T1D);
4962 pmull2(v28, T1Q, v5, v16, T2D);
4963 ldrq(v5, Address(buf, 0x60));
4964 eor3(v5, T16B, v27, v28, v5);
4965
4966 pmull (v29, T1Q, v6, v16, T1D);
4967 pmull2(v30, T1Q, v6, v16, T2D);
4968 ldrq(v6, Address(buf, 0x70));
4969 eor3(v6, T16B, v29, v30, v6);
4970
4971 // Reuse registers v23, v24.
4972 // Using them won't block the first instruction of the next iteration.
4973 pmull (v23, T1Q, v7, v16, T1D);
4974 pmull2(v24, T1Q, v7, v16, T2D);
4975 ldrq(v7, Address(pre(buf, 0x80)));
4976 eor3(v7, T16B, v23, v24, v7);
4977
4978 subs(len, len, 0x80);
4979 br(Assembler::GE, CRC_by128_loop);
4980
4981 // fold into 512 bits
4982 // Use v31 for constants because v16 can be still in use.
4983 ldrq(v31, Address(table, 0x10));
4984
4985 pmull (v17, T1Q, v0, v31, T1D);
4986 pmull2(v18, T1Q, v0, v31, T2D);
4987 eor3(v0, T16B, v17, v18, v4);
4988
4989 pmull (v19, T1Q, v1, v31, T1D);
4990 pmull2(v20, T1Q, v1, v31, T2D);
4991 eor3(v1, T16B, v19, v20, v5);
4992
4993 pmull (v21, T1Q, v2, v31, T1D);
4994 pmull2(v22, T1Q, v2, v31, T2D);
4995 eor3(v2, T16B, v21, v22, v6);
4996
4997 pmull (v23, T1Q, v3, v31, T1D);
4998 pmull2(v24, T1Q, v3, v31, T2D);
4999 eor3(v3, T16B, v23, v24, v7);
5000
5001 // fold into 128 bits
5002 // Use v17 for constants because v31 can be still in use.
5003 ldrq(v17, Address(table, 0x20));
5004 pmull (v25, T1Q, v0, v17, T1D);
5005 pmull2(v26, T1Q, v0, v17, T2D);
5006 eor3(v3, T16B, v3, v25, v26);
5007
5008 // Use v18 for constants because v17 can be still in use.
5009 ldrq(v18, Address(table, 0x30));
5010 pmull (v27, T1Q, v1, v18, T1D);
5011 pmull2(v28, T1Q, v1, v18, T2D);
5012 eor3(v3, T16B, v3, v27, v28);
5013
5014 // Use v19 for constants because v18 can be still in use.
5015 ldrq(v19, Address(table, 0x40));
5016 pmull (v29, T1Q, v2, v19, T1D);
5017 pmull2(v30, T1Q, v2, v19, T2D);
5018 eor3(v0, T16B, v3, v29, v30);
5019
5020 add(len, len, 0x80);
5021 add(buf, buf, 0x10);
5022
5023 mov(tmp0, v0, D, 0);
5024 mov(tmp1, v0, D, 1);
5025 }
5026
5027 void MacroAssembler::addptr(const Address &dst, int32_t src) {
5028 Address adr;
5029 switch(dst.getMode()) {
5030 case Address::base_plus_offset:
5031 // This is the expected mode, although we allow all the other
5032 // forms below.
5033 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
5034 break;
5035 default:
5036 lea(rscratch2, dst);
5037 adr = Address(rscratch2);
5038 break;
5039 }
5040 ldr(rscratch1, adr);
5041 add(rscratch1, rscratch1, src);
5042 str(rscratch1, adr);
5043 }
5044
5045 void MacroAssembler::cmpptr(Register src1, Address src2) {
5046 uint64_t offset;
5047 adrp(rscratch1, src2, offset);
5048 ldr(rscratch1, Address(rscratch1, offset));
5049 cmp(src1, rscratch1);
5050 }
5051
5052 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
5053 cmp(obj1, obj2);
5054 }
5055
5056 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5057 load_method_holder(rresult, rmethod);
5058 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5059 }
5060
5061 void MacroAssembler::load_method_holder(Register holder, Register method) {
5062 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
5063 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5064 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5065 }
5066
5067 // Loads the obj's Klass* into dst.
5068 // Preserves all registers (incl src, rscratch1 and rscratch2).
5069 // Input:
5070 // src - the oop we want to load the klass from.
5071 // dst - output narrow klass.
5072 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5073 assert(UseCompactObjectHeaders, "expects UseCompactObjectHeaders");
5074 ldr(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5075 lsr(dst, dst, markWord::klass_shift);
5076 }
5077
5078 void MacroAssembler::load_klass(Register dst, Register src) {
5079 if (UseCompactObjectHeaders) {
5080 load_narrow_klass_compact(dst, src);
5081 decode_klass_not_null(dst);
5082 } else if (UseCompressedClassPointers) {
5083 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5084 decode_klass_not_null(dst);
5085 } else {
5086 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5087 }
5088 }
5089
5090 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5091 if (RestoreMXCSROnJNICalls) {
5092 Label OK;
5093 get_fpcr(tmp1);
5094 mov(tmp2, tmp1);
5095 // Set FPCR to the state we need. We do want Round to Nearest. We
5096 // don't want non-IEEE rounding modes or floating-point traps.
5097 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5098 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5099 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5100 eor(tmp2, tmp1, tmp2);
5101 cbz(tmp2, OK); // Only reset FPCR if it's wrong
5102 set_fpcr(tmp1);
5103 bind(OK);
5104 }
5105 }
5106
5107 // ((OopHandle)result).resolve();
5108 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
5109 // OopHandle::resolve is an indirection.
5110 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
5111 }
5112
5113 // ((WeakHandle)result).resolve();
5114 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
5115 assert_different_registers(result, tmp1, tmp2);
5116 Label resolved;
5117
5118 // A null weak handle resolves to null.
5119 cbz(result, resolved);
5120
5121 // Only 64 bit platforms support GCs that require a tmp register
5122 // WeakHandle::resolve is an indirection like jweak.
5123 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5124 result, Address(result), tmp1, tmp2);
5125 bind(resolved);
5126 }
5127
5128 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) {
5129 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5130 ldr(dst, Address(rmethod, Method::const_offset()));
5131 ldr(dst, Address(dst, ConstMethod::constants_offset()));
5132 ldr(dst, Address(dst, ConstantPool::pool_holder_offset()));
5133 ldr(dst, Address(dst, mirror_offset));
5134 resolve_oop_handle(dst, tmp1, tmp2);
5135 }
5136
5137 void MacroAssembler::cmp_klass(Register obj, Register klass, Register tmp) {
5138 assert_different_registers(obj, klass, tmp);
5139 if (UseCompressedClassPointers) {
5140 if (UseCompactObjectHeaders) {
5141 load_narrow_klass_compact(tmp, obj);
5142 } else {
5143 ldrw(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5144 }
5145 if (CompressedKlassPointers::base() == nullptr) {
5146 cmp(klass, tmp, LSL, CompressedKlassPointers::shift());
5147 return;
5148 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5149 && CompressedKlassPointers::shift() == 0) {
5150 // Only the bottom 32 bits matter
5151 cmpw(klass, tmp);
5152 return;
5153 }
5154 decode_klass_not_null(tmp);
5155 } else {
5156 ldr(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5157 }
5158 cmp(klass, tmp);
5159 }
5160
5161 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5162 if (UseCompactObjectHeaders) {
5163 load_narrow_klass_compact(tmp1, obj1);
5164 load_narrow_klass_compact(tmp2, obj2);
5165 cmpw(tmp1, tmp2);
5166 } else if (UseCompressedClassPointers) {
5167 ldrw(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5168 ldrw(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5169 cmpw(tmp1, tmp2);
5170 } else {
5171 ldr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5172 ldr(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5173 cmp(tmp1, tmp2);
5174 }
5175 }
5176
5177 void MacroAssembler::store_klass(Register dst, Register src) {
5178 // FIXME: Should this be a store release? concurrent gcs assumes
5179 // klass length is valid if klass field is not null.
5180 assert(!UseCompactObjectHeaders, "not with compact headers");
5181 if (UseCompressedClassPointers) {
5182 encode_klass_not_null(src);
5183 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5184 } else {
5185 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5186 }
5187 }
5188
5189 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5190 assert(!UseCompactObjectHeaders, "not with compact headers");
5191 if (UseCompressedClassPointers) {
5192 // Store to klass gap in destination
5193 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5194 }
5195 }
5196
5197 // Algorithm must match CompressedOops::encode.
5198 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5199 #ifdef ASSERT
5200 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5201 #endif
5202 verify_oop_msg(s, "broken oop in encode_heap_oop");
5203 if (CompressedOops::base() == nullptr) {
5204 if (CompressedOops::shift() != 0) {
5205 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5206 lsr(d, s, LogMinObjAlignmentInBytes);
5207 } else {
5208 mov(d, s);
5209 }
5210 } else {
5211 subs(d, s, rheapbase);
5212 csel(d, d, zr, Assembler::HS);
5213 lsr(d, d, LogMinObjAlignmentInBytes);
5214
5215 /* Old algorithm: is this any worse?
5216 Label nonnull;
5217 cbnz(r, nonnull);
5218 sub(r, r, rheapbase);
5219 bind(nonnull);
5220 lsr(r, r, LogMinObjAlignmentInBytes);
5221 */
5222 }
5223 }
5224
5225 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5226 #ifdef ASSERT
5227 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5228 if (CheckCompressedOops) {
5229 Label ok;
5230 cbnz(r, ok);
5231 stop("null oop passed to encode_heap_oop_not_null");
5232 bind(ok);
5233 }
5234 #endif
5235 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5236 if (CompressedOops::base() != nullptr) {
5237 sub(r, r, rheapbase);
5238 }
5239 if (CompressedOops::shift() != 0) {
5240 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5241 lsr(r, r, LogMinObjAlignmentInBytes);
5242 }
5243 }
5244
5245 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5246 #ifdef ASSERT
5247 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5248 if (CheckCompressedOops) {
5249 Label ok;
5250 cbnz(src, ok);
5251 stop("null oop passed to encode_heap_oop_not_null2");
5252 bind(ok);
5253 }
5254 #endif
5255 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5256
5257 Register data = src;
5258 if (CompressedOops::base() != nullptr) {
5259 sub(dst, src, rheapbase);
5260 data = dst;
5261 }
5262 if (CompressedOops::shift() != 0) {
5263 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5264 lsr(dst, data, LogMinObjAlignmentInBytes);
5265 data = dst;
5266 }
5267 if (data == src)
5268 mov(dst, src);
5269 }
5270
5271 void MacroAssembler::decode_heap_oop(Register d, Register s) {
5272 #ifdef ASSERT
5273 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5274 #endif
5275 if (CompressedOops::base() == nullptr) {
5276 if (CompressedOops::shift() != 0) {
5277 lsl(d, s, CompressedOops::shift());
5278 } else if (d != s) {
5279 mov(d, s);
5280 }
5281 } else {
5282 Label done;
5283 if (d != s)
5284 mov(d, s);
5285 cbz(s, done);
5286 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
5287 bind(done);
5288 }
5289 verify_oop_msg(d, "broken oop in decode_heap_oop");
5290 }
5291
5292 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5293 assert (UseCompressedOops, "should only be used for compressed headers");
5294 assert (Universe::heap() != nullptr, "java heap should be initialized");
5295 // Cannot assert, unverified entry point counts instructions (see .ad file)
5296 // vtableStubs also counts instructions in pd_code_size_limit.
5297 // Also do not verify_oop as this is called by verify_oop.
5298 if (CompressedOops::shift() != 0) {
5299 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5300 if (CompressedOops::base() != nullptr) {
5301 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5302 } else {
5303 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5304 }
5305 } else {
5306 assert (CompressedOops::base() == nullptr, "sanity");
5307 }
5308 }
5309
5310 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5311 assert (UseCompressedOops, "should only be used for compressed headers");
5312 assert (Universe::heap() != nullptr, "java heap should be initialized");
5313 // Cannot assert, unverified entry point counts instructions (see .ad file)
5314 // vtableStubs also counts instructions in pd_code_size_limit.
5315 // Also do not verify_oop as this is called by verify_oop.
5316 if (CompressedOops::shift() != 0) {
5317 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5318 if (CompressedOops::base() != nullptr) {
5319 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5320 } else {
5321 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5322 }
5323 } else {
5324 assert (CompressedOops::base() == nullptr, "sanity");
5325 if (dst != src) {
5326 mov(dst, src);
5327 }
5328 }
5329 }
5330
5331 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone);
5332
5333 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
5334 assert(Metaspace::initialized(), "metaspace not initialized yet");
5335 assert(_klass_decode_mode != KlassDecodeNone, "should be initialized");
5336 return _klass_decode_mode;
5337 }
5338
5339 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode(address base, int shift, const size_t range) {
5340 assert(UseCompressedClassPointers, "not using compressed class pointers");
5341
5342 // KlassDecodeMode shouldn't be set already.
5343 assert(_klass_decode_mode == KlassDecodeNone, "set once");
5344
5345 if (base == nullptr) {
5346 return KlassDecodeZero;
5347 }
5348
5349 if (operand_valid_for_logical_immediate(
5350 /*is32*/false, (uint64_t)base)) {
5351 const uint64_t range_mask = right_n_bits(log2i_ceil(range));
5352 if (((uint64_t)base & range_mask) == 0) {
5353 return KlassDecodeXor;
5354 }
5355 }
5356
5357 const uint64_t shifted_base =
5358 (uint64_t)base >> shift;
5359 if ((shifted_base & 0xffff0000ffffffff) == 0) {
5360 return KlassDecodeMovk;
5361 }
5362
5363 // No valid encoding.
5364 return KlassDecodeNone;
5365 }
5366
5367 // Check if one of the above decoding modes will work for given base, shift and range.
5368 bool MacroAssembler::check_klass_decode_mode(address base, int shift, const size_t range) {
5369 return klass_decode_mode(base, shift, range) != KlassDecodeNone;
5370 }
5371
5372 bool MacroAssembler::set_klass_decode_mode(address base, int shift, const size_t range) {
5373 _klass_decode_mode = klass_decode_mode(base, shift, range);
5374 return _klass_decode_mode != KlassDecodeNone;
5375 }
5376
5377 static Register pick_different_tmp(Register dst, Register src) {
5378 auto tmps = RegSet::of(r0, r1, r2) - RegSet::of(src, dst);
5379 return *tmps.begin();
5380 }
5381
5382 void MacroAssembler::encode_klass_not_null_for_aot(Register dst, Register src) {
5383 // we have to load the klass base from the AOT constants area but
5384 // not the shift because it is not allowed to change
5385 int shift = CompressedKlassPointers::shift();
5386 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5387 if (dst != src) {
5388 // we can load the base into dst, subtract it formthe src and shift down
5389 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5390 ldr(dst, dst);
5391 sub(dst, src, dst);
5392 lsr(dst, dst, shift);
5393 } else {
5394 // we need an extra register in order to load the coop base
5395 Register tmp = pick_different_tmp(dst, src);
5396 RegSet regs = RegSet::of(tmp);
5397 push(regs, sp);
5398 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5399 ldr(tmp, tmp);
5400 sub(dst, src, tmp);
5401 lsr(dst, dst, shift);
5402 pop(regs, sp);
5403 }
5404 }
5405
5406 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5407 if (AOTCodeCache::is_on_for_dump()) {
5408 encode_klass_not_null_for_aot(dst, src);
5409 return;
5410 }
5411
5412 switch (klass_decode_mode()) {
5413 case KlassDecodeZero:
5414 if (CompressedKlassPointers::shift() != 0) {
5415 lsr(dst, src, CompressedKlassPointers::shift());
5416 } else {
5417 if (dst != src) mov(dst, src);
5418 }
5419 break;
5420
5421 case KlassDecodeXor:
5422 if (CompressedKlassPointers::shift() != 0) {
5423 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5424 lsr(dst, dst, CompressedKlassPointers::shift());
5425 } else {
5426 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5427 }
5428 break;
5429
5430 case KlassDecodeMovk:
5431 if (CompressedKlassPointers::shift() != 0) {
5432 ubfx(dst, src, CompressedKlassPointers::shift(), 32);
5433 } else {
5434 movw(dst, src);
5435 }
5436 break;
5437
5438 case KlassDecodeNone:
5439 ShouldNotReachHere();
5440 break;
5441 }
5442 }
5443
5444 void MacroAssembler::encode_klass_not_null(Register r) {
5445 encode_klass_not_null(r, r);
5446 }
5447
5448 void MacroAssembler::decode_klass_not_null_for_aot(Register dst, Register src) {
5449 // we have to load the klass base from the AOT constants area but
5450 // not the shift because it is not allowed to change
5451 int shift = CompressedKlassPointers::shift();
5452 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5453 if (dst != src) {
5454 // we can load the base into dst then add the offset with a suitable shift
5455 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5456 ldr(dst, dst);
5457 add(dst, dst, src, LSL, shift);
5458 } else {
5459 // we need an extra register in order to load the coop base
5460 Register tmp = pick_different_tmp(dst, src);
5461 RegSet regs = RegSet::of(tmp);
5462 push(regs, sp);
5463 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5464 ldr(tmp, tmp);
5465 add(dst, tmp, src, LSL, shift);
5466 pop(regs, sp);
5467 }
5468 }
5469
5470 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5471 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5472
5473 if (AOTCodeCache::is_on_for_dump()) {
5474 decode_klass_not_null_for_aot(dst, src);
5475 return;
5476 }
5477
5478 switch (klass_decode_mode()) {
5479 case KlassDecodeZero:
5480 if (CompressedKlassPointers::shift() != 0) {
5481 lsl(dst, src, CompressedKlassPointers::shift());
5482 } else {
5483 if (dst != src) mov(dst, src);
5484 }
5485 break;
5486
5487 case KlassDecodeXor:
5488 if (CompressedKlassPointers::shift() != 0) {
5489 lsl(dst, src, CompressedKlassPointers::shift());
5490 eor(dst, dst, (uint64_t)CompressedKlassPointers::base());
5491 } else {
5492 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5493 }
5494 break;
5495
5496 case KlassDecodeMovk: {
5497 const uint64_t shifted_base =
5498 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5499
5500 if (dst != src) movw(dst, src);
5501 movk(dst, shifted_base >> 32, 32);
5502
5503 if (CompressedKlassPointers::shift() != 0) {
5504 lsl(dst, dst, CompressedKlassPointers::shift());
5505 }
5506
5507 break;
5508 }
5509
5510 case KlassDecodeNone:
5511 ShouldNotReachHere();
5512 break;
5513 }
5514 }
5515
5516 void MacroAssembler::decode_klass_not_null(Register r) {
5517 decode_klass_not_null(r, r);
5518 }
5519
5520 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5521 #ifdef ASSERT
5522 {
5523 ThreadInVMfromUnknown tiv;
5524 assert (UseCompressedOops, "should only be used for compressed oops");
5525 assert (Universe::heap() != nullptr, "java heap should be initialized");
5526 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5527 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5528 }
5529 #endif
5530 int oop_index = oop_recorder()->find_index(obj);
5531 InstructionMark im(this);
5532 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5533 code_section()->relocate(inst_mark(), rspec);
5534 movz(dst, 0xDEAD, 16);
5535 movk(dst, 0xBEEF);
5536 }
5537
5538 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5539 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5540 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5541 int index = oop_recorder()->find_index(k);
5542
5543 InstructionMark im(this);
5544 RelocationHolder rspec = metadata_Relocation::spec(index);
5545 code_section()->relocate(inst_mark(), rspec);
5546 narrowKlass nk = CompressedKlassPointers::encode(k);
5547 movz(dst, (nk >> 16), 16);
5548 movk(dst, nk & 0xffff);
5549 }
5550
5551 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
5552 Register dst, Address src,
5553 Register tmp1, Register tmp2) {
5554 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5555 decorators = AccessInternal::decorator_fixup(decorators, type);
5556 bool as_raw = (decorators & AS_RAW) != 0;
5557 if (as_raw) {
5558 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5559 } else {
5560 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5561 }
5562 }
5563
5564 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5565 Address dst, Register val,
5566 Register tmp1, Register tmp2, Register tmp3) {
5567 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5568 decorators = AccessInternal::decorator_fixup(decorators, type);
5569 bool as_raw = (decorators & AS_RAW) != 0;
5570 if (as_raw) {
5571 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5572 } else {
5573 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5574 }
5575 }
5576
5577 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5578 Register tmp2, DecoratorSet decorators) {
5579 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5580 }
5581
5582 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5583 Register tmp2, DecoratorSet decorators) {
5584 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5585 }
5586
5587 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5588 Register tmp2, Register tmp3, DecoratorSet decorators) {
5589 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5590 }
5591
5592 // Used for storing nulls.
5593 void MacroAssembler::store_heap_oop_null(Address dst) {
5594 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5595 }
5596
5597 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
5598 assert(oop_recorder() != nullptr, "this assembler needs a Recorder");
5599 int index = oop_recorder()->allocate_metadata_index(obj);
5600 RelocationHolder rspec = metadata_Relocation::spec(index);
5601 return Address((address)obj, rspec);
5602 }
5603
5604 // Move an oop into a register.
5605 void MacroAssembler::movoop(Register dst, jobject obj) {
5606 int oop_index;
5607 if (obj == nullptr) {
5608 oop_index = oop_recorder()->allocate_oop_index(obj);
5609 } else {
5610 #ifdef ASSERT
5611 {
5612 ThreadInVMfromUnknown tiv;
5613 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5614 }
5615 #endif
5616 oop_index = oop_recorder()->find_index(obj);
5617 }
5618 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5619
5620 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
5621 mov(dst, Address((address)obj, rspec));
5622 } else {
5623 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
5624 ldr(dst, Address(dummy, rspec));
5625 }
5626 }
5627
5628 // Move a metadata address into a register.
5629 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
5630 int oop_index;
5631 if (obj == nullptr) {
5632 oop_index = oop_recorder()->allocate_metadata_index(obj);
5633 } else {
5634 oop_index = oop_recorder()->find_index(obj);
5635 }
5636 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5637 mov(dst, Address((address)obj, rspec));
5638 }
5639
5640 Address MacroAssembler::constant_oop_address(jobject obj) {
5641 #ifdef ASSERT
5642 {
5643 ThreadInVMfromUnknown tiv;
5644 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5645 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5646 }
5647 #endif
5648 int oop_index = oop_recorder()->find_index(obj);
5649 return Address((address)obj, oop_Relocation::spec(oop_index));
5650 }
5651
5652 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5653 void MacroAssembler::tlab_allocate(Register obj,
5654 Register var_size_in_bytes,
5655 int con_size_in_bytes,
5656 Register t1,
5657 Register t2,
5658 Label& slow_case) {
5659 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5660 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5661 }
5662
5663 void MacroAssembler::verify_tlab() {
5664 #ifdef ASSERT
5665 if (UseTLAB && VerifyOops) {
5666 Label next, ok;
5667
5668 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5669
5670 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5671 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5672 cmp(rscratch2, rscratch1);
5673 br(Assembler::HS, next);
5674 STOP("assert(top >= start)");
5675 should_not_reach_here();
5676
5677 bind(next);
5678 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5679 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5680 cmp(rscratch2, rscratch1);
5681 br(Assembler::HS, ok);
5682 STOP("assert(top <= end)");
5683 should_not_reach_here();
5684
5685 bind(ok);
5686 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5687 }
5688 #endif
5689 }
5690
5691 // Writes to stack successive pages until offset reached to check for
5692 // stack overflow + shadow pages. This clobbers tmp.
5693 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5694 assert_different_registers(tmp, size, rscratch1);
5695 mov(tmp, sp);
5696 // Bang stack for total size given plus shadow page size.
5697 // Bang one page at a time because large size can bang beyond yellow and
5698 // red zones.
5699 Label loop;
5700 mov(rscratch1, (int)os::vm_page_size());
5701 bind(loop);
5702 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5703 subsw(size, size, rscratch1);
5704 str(size, Address(tmp));
5705 br(Assembler::GT, loop);
5706
5707 // Bang down shadow pages too.
5708 // At this point, (tmp-0) is the last address touched, so don't
5709 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5710 // was post-decremented.) Skip this address by starting at i=1, and
5711 // touch a few more pages below. N.B. It is important to touch all
5712 // the way down to and including i=StackShadowPages.
5713 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) {
5714 // this could be any sized move but this is can be a debugging crumb
5715 // so the bigger the better.
5716 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5717 str(size, Address(tmp));
5718 }
5719 }
5720
5721 // Move the address of the polling page into dest.
5722 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) {
5723 ldr(dest, Address(rthread, JavaThread::polling_page_offset()));
5724 }
5725
5726 // Read the polling page. The address of the polling page must
5727 // already be in r.
5728 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
5729 address mark;
5730 {
5731 InstructionMark im(this);
5732 code_section()->relocate(inst_mark(), rtype);
5733 ldrw(zr, Address(r, 0));
5734 mark = inst_mark();
5735 }
5736 verify_cross_modify_fence_not_required();
5737 return mark;
5738 }
5739
5740 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
5741 relocInfo::relocType rtype = dest.rspec().reloc()->type();
5742 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
5743 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
5744 uint64_t dest_page = (uint64_t)dest.target() >> 12;
5745 int64_t offset_low = dest_page - low_page;
5746 int64_t offset_high = dest_page - high_page;
5747
5748 assert(is_valid_AArch64_address(dest.target()), "bad address");
5749 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
5750
5751 InstructionMark im(this);
5752 code_section()->relocate(inst_mark(), dest.rspec());
5753 // 8143067: Ensure that the adrp can reach the dest from anywhere within
5754 // the code cache so that if it is relocated we know it will still reach
5755 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
5756 _adrp(reg1, dest.target());
5757 } else {
5758 uint64_t target = (uint64_t)dest.target();
5759 uint64_t adrp_target
5760 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
5761
5762 _adrp(reg1, (address)adrp_target);
5763 movk(reg1, target >> 32, 32);
5764 }
5765 byte_offset = (uint64_t)dest.target() & 0xfff;
5766 }
5767
5768 void MacroAssembler::load_byte_map_base(Register reg) {
5769 CardTableBarrierSet* ctbs = CardTableBarrierSet::barrier_set();
5770
5771 // Strictly speaking the card table base isn't an address at all, and it might
5772 // even be negative. It is thus materialised as a constant.
5773 mov(reg, (uint64_t)ctbs->card_table_base_const());
5774 }
5775
5776 void MacroAssembler::build_frame(int framesize) {
5777 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5778 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5779 protect_return_address();
5780 if (framesize < ((1 << 9) + 2 * wordSize)) {
5781 sub(sp, sp, framesize);
5782 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5783 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
5784 } else {
5785 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
5786 if (PreserveFramePointer) mov(rfp, sp);
5787 if (framesize < ((1 << 12) + 2 * wordSize))
5788 sub(sp, sp, framesize - 2 * wordSize);
5789 else {
5790 mov(rscratch1, framesize - 2 * wordSize);
5791 sub(sp, sp, rscratch1);
5792 }
5793 }
5794 verify_cross_modify_fence_not_required();
5795 }
5796
5797 void MacroAssembler::remove_frame(int framesize) {
5798 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5799 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5800 if (framesize < ((1 << 9) + 2 * wordSize)) {
5801 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5802 add(sp, sp, framesize);
5803 } else {
5804 if (framesize < ((1 << 12) + 2 * wordSize))
5805 add(sp, sp, framesize - 2 * wordSize);
5806 else {
5807 mov(rscratch1, framesize - 2 * wordSize);
5808 add(sp, sp, rscratch1);
5809 }
5810 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5811 }
5812 authenticate_return_address();
5813 }
5814
5815
5816 // This method counts leading positive bytes (highest bit not set) in provided byte array
5817 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5818 // Simple and most common case of aligned small array which is not at the
5819 // end of memory page is placed here. All other cases are in stub.
5820 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5821 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5822 assert_different_registers(ary1, len, result);
5823
5824 mov(result, len);
5825 cmpw(len, 0);
5826 br(LE, DONE);
5827 cmpw(len, 4 * wordSize);
5828 br(GE, STUB_LONG); // size > 32 then go to stub
5829
5830 int shift = 64 - exact_log2(os::vm_page_size());
5831 lsl(rscratch1, ary1, shift);
5832 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5833 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5834 br(CS, STUB); // at the end of page then go to stub
5835 subs(len, len, wordSize);
5836 br(LT, END);
5837
5838 BIND(LOOP);
5839 ldr(rscratch1, Address(post(ary1, wordSize)));
5840 tst(rscratch1, UPPER_BIT_MASK);
5841 br(NE, SET_RESULT);
5842 subs(len, len, wordSize);
5843 br(GE, LOOP);
5844 cmpw(len, -wordSize);
5845 br(EQ, DONE);
5846
5847 BIND(END);
5848 ldr(rscratch1, Address(ary1));
5849 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
5850 lslv(rscratch1, rscratch1, rscratch2);
5851 tst(rscratch1, UPPER_BIT_MASK);
5852 br(NE, SET_RESULT);
5853 b(DONE);
5854
5855 BIND(STUB);
5856 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives());
5857 assert(count_pos.target() != nullptr, "count_positives stub has not been generated");
5858 address tpc1 = trampoline_call(count_pos);
5859 if (tpc1 == nullptr) {
5860 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE));
5861 postcond(pc() == badAddress);
5862 return nullptr;
5863 }
5864 b(DONE);
5865
5866 BIND(STUB_LONG);
5867 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long());
5868 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated");
5869 address tpc2 = trampoline_call(count_pos_long);
5870 if (tpc2 == nullptr) {
5871 DEBUG_ONLY(reset_labels(SET_RESULT, DONE));
5872 postcond(pc() == badAddress);
5873 return nullptr;
5874 }
5875 b(DONE);
5876
5877 BIND(SET_RESULT);
5878
5879 add(len, len, wordSize);
5880 sub(result, result, len);
5881
5882 BIND(DONE);
5883 postcond(pc() != badAddress);
5884 return pc();
5885 }
5886
5887 // Clobbers: rscratch1, rscratch2, rflags
5888 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals)
5889 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
5890 Register tmp4, Register tmp5, Register result,
5891 Register cnt1, int elem_size) {
5892 Label DONE, SAME;
5893 Register tmp1 = rscratch1;
5894 Register tmp2 = rscratch2;
5895 int elem_per_word = wordSize/elem_size;
5896 int log_elem_size = exact_log2(elem_size);
5897 int klass_offset = arrayOopDesc::klass_offset_in_bytes();
5898 int length_offset = arrayOopDesc::length_offset_in_bytes();
5899 int base_offset
5900 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
5901 // When the length offset is not aligned to 8 bytes,
5902 // then we align it down. This is valid because the new
5903 // offset will always be the klass which is the same
5904 // for type arrays.
5905 int start_offset = align_down(length_offset, BytesPerWord);
5906 int extra_length = base_offset - start_offset;
5907 assert(start_offset == length_offset || start_offset == klass_offset,
5908 "start offset must be 8-byte-aligned or be the klass offset");
5909 assert(base_offset != start_offset, "must include the length field");
5910 extra_length = extra_length / elem_size; // We count in elements, not bytes.
5911 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
5912
5913 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
5914 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5915
5916 #ifndef PRODUCT
5917 {
5918 const char kind = (elem_size == 2) ? 'U' : 'L';
5919 char comment[64];
5920 os::snprintf_checked(comment, sizeof comment, "array_equals%c{", kind);
5921 BLOCK_COMMENT(comment);
5922 }
5923 #endif
5924
5925 // if (a1 == a2)
5926 // return true;
5927 cmpoop(a1, a2); // May have read barriers for a1 and a2.
5928 br(EQ, SAME);
5929
5930 if (UseSimpleArrayEquals) {
5931 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
5932 // if (a1 == nullptr || a2 == nullptr)
5933 // return false;
5934 // a1 & a2 == 0 means (some-pointer is null) or
5935 // (very-rare-or-even-probably-impossible-pointer-values)
5936 // so, we can save one branch in most cases
5937 tst(a1, a2);
5938 mov(result, false);
5939 br(EQ, A_MIGHT_BE_NULL);
5940 // if (a1.length != a2.length)
5941 // return false;
5942 bind(A_IS_NOT_NULL);
5943 ldrw(cnt1, Address(a1, length_offset));
5944 ldrw(tmp5, Address(a2, length_offset));
5945 cmp(cnt1, tmp5);
5946 br(NE, DONE); // If lengths differ, return false
5947 // Increase loop counter by diff between base- and actual start-offset.
5948 addw(cnt1, cnt1, extra_length);
5949 lea(a1, Address(a1, start_offset));
5950 lea(a2, Address(a2, start_offset));
5951 // Check for short strings, i.e. smaller than wordSize.
5952 subs(cnt1, cnt1, elem_per_word);
5953 br(Assembler::LT, SHORT);
5954 // Main 8 byte comparison loop.
5955 bind(NEXT_WORD); {
5956 ldr(tmp1, Address(post(a1, wordSize)));
5957 ldr(tmp2, Address(post(a2, wordSize)));
5958 subs(cnt1, cnt1, elem_per_word);
5959 eor(tmp5, tmp1, tmp2);
5960 cbnz(tmp5, DONE);
5961 } br(GT, NEXT_WORD);
5962 // Last longword. In the case where length == 4 we compare the
5963 // same longword twice, but that's still faster than another
5964 // conditional branch.
5965 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5966 // length == 4.
5967 if (log_elem_size > 0)
5968 lsl(cnt1, cnt1, log_elem_size);
5969 ldr(tmp3, Address(a1, cnt1));
5970 ldr(tmp4, Address(a2, cnt1));
5971 eor(tmp5, tmp3, tmp4);
5972 cbnz(tmp5, DONE);
5973 b(SAME);
5974 bind(A_MIGHT_BE_NULL);
5975 // in case both a1 and a2 are not-null, proceed with loads
5976 cbz(a1, DONE);
5977 cbz(a2, DONE);
5978 b(A_IS_NOT_NULL);
5979 bind(SHORT);
5980
5981 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
5982 {
5983 ldrw(tmp1, Address(post(a1, 4)));
5984 ldrw(tmp2, Address(post(a2, 4)));
5985 eorw(tmp5, tmp1, tmp2);
5986 cbnzw(tmp5, DONE);
5987 }
5988 bind(TAIL03);
5989 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
5990 {
5991 ldrh(tmp3, Address(post(a1, 2)));
5992 ldrh(tmp4, Address(post(a2, 2)));
5993 eorw(tmp5, tmp3, tmp4);
5994 cbnzw(tmp5, DONE);
5995 }
5996 bind(TAIL01);
5997 if (elem_size == 1) { // Only needed when comparing byte arrays.
5998 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5999 {
6000 ldrb(tmp1, a1);
6001 ldrb(tmp2, a2);
6002 eorw(tmp5, tmp1, tmp2);
6003 cbnzw(tmp5, DONE);
6004 }
6005 }
6006 } else {
6007 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
6008 CSET_EQ, LAST_CHECK;
6009 mov(result, false);
6010 cbz(a1, DONE);
6011 ldrw(cnt1, Address(a1, length_offset));
6012 cbz(a2, DONE);
6013 ldrw(tmp5, Address(a2, length_offset));
6014 cmp(cnt1, tmp5);
6015 br(NE, DONE); // If lengths differ, return false
6016 // Increase loop counter by diff between base- and actual start-offset.
6017 addw(cnt1, cnt1, extra_length);
6018
6019 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
6020 // faster to perform another branch before comparing a1 and a2
6021 cmp(cnt1, (u1)elem_per_word);
6022 br(LE, SHORT); // short or same
6023 ldr(tmp3, Address(pre(a1, start_offset)));
6024 subs(zr, cnt1, stubBytesThreshold);
6025 br(GE, STUB);
6026 ldr(tmp4, Address(pre(a2, start_offset)));
6027 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6028
6029 // Main 16 byte comparison loop with 2 exits
6030 bind(NEXT_DWORD); {
6031 ldr(tmp1, Address(pre(a1, wordSize)));
6032 ldr(tmp2, Address(pre(a2, wordSize)));
6033 subs(cnt1, cnt1, 2 * elem_per_word);
6034 br(LE, TAIL);
6035 eor(tmp4, tmp3, tmp4);
6036 cbnz(tmp4, DONE);
6037 ldr(tmp3, Address(pre(a1, wordSize)));
6038 ldr(tmp4, Address(pre(a2, wordSize)));
6039 cmp(cnt1, (u1)elem_per_word);
6040 br(LE, TAIL2);
6041 cmp(tmp1, tmp2);
6042 } br(EQ, NEXT_DWORD);
6043 b(DONE);
6044
6045 bind(TAIL);
6046 eor(tmp4, tmp3, tmp4);
6047 eor(tmp2, tmp1, tmp2);
6048 lslv(tmp2, tmp2, tmp5);
6049 orr(tmp5, tmp4, tmp2);
6050 cmp(tmp5, zr);
6051 b(CSET_EQ);
6052
6053 bind(TAIL2);
6054 eor(tmp2, tmp1, tmp2);
6055 cbnz(tmp2, DONE);
6056 b(LAST_CHECK);
6057
6058 bind(STUB);
6059 ldr(tmp4, Address(pre(a2, start_offset)));
6060 if (elem_size == 2) { // convert to byte counter
6061 lsl(cnt1, cnt1, 1);
6062 }
6063 eor(tmp5, tmp3, tmp4);
6064 cbnz(tmp5, DONE);
6065 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
6066 assert(stub.target() != nullptr, "array_equals_long stub has not been generated");
6067 address tpc = trampoline_call(stub);
6068 if (tpc == nullptr) {
6069 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
6070 postcond(pc() == badAddress);
6071 return nullptr;
6072 }
6073 b(DONE);
6074
6075 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
6076 // so, if a2 == null => return false(0), else return true, so we can return a2
6077 mov(result, a2);
6078 b(DONE);
6079 bind(SHORT);
6080 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6081 ldr(tmp3, Address(a1, start_offset));
6082 ldr(tmp4, Address(a2, start_offset));
6083 bind(LAST_CHECK);
6084 eor(tmp4, tmp3, tmp4);
6085 lslv(tmp5, tmp4, tmp5);
6086 cmp(tmp5, zr);
6087 bind(CSET_EQ);
6088 cset(result, EQ);
6089 b(DONE);
6090 }
6091
6092 bind(SAME);
6093 mov(result, true);
6094 // That's it.
6095 bind(DONE);
6096
6097 BLOCK_COMMENT("} array_equals");
6098 postcond(pc() != badAddress);
6099 return pc();
6100 }
6101
6102 // Compare Strings
6103
6104 // For Strings we're passed the address of the first characters in a1
6105 // and a2 and the length in cnt1.
6106 // There are two implementations. For arrays >= 8 bytes, all
6107 // comparisons (including the final one, which may overlap) are
6108 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
6109 // halfword, then a short, and then a byte.
6110
6111 void MacroAssembler::string_equals(Register a1, Register a2,
6112 Register result, Register cnt1)
6113 {
6114 Label SAME, DONE, SHORT, NEXT_WORD;
6115 Register tmp1 = rscratch1;
6116 Register tmp2 = rscratch2;
6117 Register cnt2 = tmp2; // cnt2 only used in array length compare
6118
6119 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
6120
6121 #ifndef PRODUCT
6122 {
6123 char comment[64];
6124 os::snprintf_checked(comment, sizeof comment, "{string_equalsL");
6125 BLOCK_COMMENT(comment);
6126 }
6127 #endif
6128
6129 mov(result, false);
6130
6131 // Check for short strings, i.e. smaller than wordSize.
6132 subs(cnt1, cnt1, wordSize);
6133 br(Assembler::LT, SHORT);
6134 // Main 8 byte comparison loop.
6135 bind(NEXT_WORD); {
6136 ldr(tmp1, Address(post(a1, wordSize)));
6137 ldr(tmp2, Address(post(a2, wordSize)));
6138 subs(cnt1, cnt1, wordSize);
6139 eor(tmp1, tmp1, tmp2);
6140 cbnz(tmp1, DONE);
6141 } br(GT, NEXT_WORD);
6142 // Last longword. In the case where length == 4 we compare the
6143 // same longword twice, but that's still faster than another
6144 // conditional branch.
6145 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6146 // length == 4.
6147 ldr(tmp1, Address(a1, cnt1));
6148 ldr(tmp2, Address(a2, cnt1));
6149 eor(tmp2, tmp1, tmp2);
6150 cbnz(tmp2, DONE);
6151 b(SAME);
6152
6153 bind(SHORT);
6154 Label TAIL03, TAIL01;
6155
6156 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
6157 {
6158 ldrw(tmp1, Address(post(a1, 4)));
6159 ldrw(tmp2, Address(post(a2, 4)));
6160 eorw(tmp1, tmp1, tmp2);
6161 cbnzw(tmp1, DONE);
6162 }
6163 bind(TAIL03);
6164 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
6165 {
6166 ldrh(tmp1, Address(post(a1, 2)));
6167 ldrh(tmp2, Address(post(a2, 2)));
6168 eorw(tmp1, tmp1, tmp2);
6169 cbnzw(tmp1, DONE);
6170 }
6171 bind(TAIL01);
6172 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6173 {
6174 ldrb(tmp1, a1);
6175 ldrb(tmp2, a2);
6176 eorw(tmp1, tmp1, tmp2);
6177 cbnzw(tmp1, DONE);
6178 }
6179 // Arrays are equal.
6180 bind(SAME);
6181 mov(result, true);
6182
6183 // That's it.
6184 bind(DONE);
6185 BLOCK_COMMENT("} string_equals");
6186 }
6187
6188
6189 // The size of the blocks erased by the zero_blocks stub. We must
6190 // handle anything smaller than this ourselves in zero_words().
6191 const int MacroAssembler::zero_words_block_size = 8;
6192
6193 // zero_words() is used by C2 ClearArray patterns and by
6194 // C1_MacroAssembler. It is as small as possible, handling small word
6195 // counts locally and delegating anything larger to the zero_blocks
6196 // stub. It is expanded many times in compiled code, so it is
6197 // important to keep it short.
6198
6199 // ptr: Address of a buffer to be zeroed.
6200 // cnt: Count in HeapWords.
6201 //
6202 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
6203 address MacroAssembler::zero_words(Register ptr, Register cnt)
6204 {
6205 assert(is_power_of_2(zero_words_block_size), "adjust this");
6206
6207 BLOCK_COMMENT("zero_words {");
6208 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
6209 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6210 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6211
6212 subs(rscratch1, cnt, zero_words_block_size);
6213 Label around;
6214 br(LO, around);
6215 {
6216 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6217 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6218 // Make sure this is a C2 compilation. C1 allocates space only for
6219 // trampoline stubs generated by Call LIR ops, and in any case it
6220 // makes sense for a C1 compilation task to proceed as quickly as
6221 // possible.
6222 CompileTask* task;
6223 if (StubRoutines::aarch64::complete()
6224 && Thread::current()->is_Compiler_thread()
6225 && (task = ciEnv::current()->task())
6226 && is_c2_compile(task->comp_level())) {
6227 address tpc = trampoline_call(zero_blocks);
6228 if (tpc == nullptr) {
6229 DEBUG_ONLY(reset_labels(around));
6230 return nullptr;
6231 }
6232 } else {
6233 far_call(zero_blocks);
6234 }
6235 }
6236 bind(around);
6237
6238 // We have a few words left to do. zero_blocks has adjusted r10 and r11
6239 // for us.
6240 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
6241 Label l;
6242 tbz(cnt, exact_log2(i), l);
6243 for (int j = 0; j < i; j += 2) {
6244 stp(zr, zr, post(ptr, 2 * BytesPerWord));
6245 }
6246 bind(l);
6247 }
6248 {
6249 Label l;
6250 tbz(cnt, 0, l);
6251 str(zr, Address(ptr));
6252 bind(l);
6253 }
6254
6255 BLOCK_COMMENT("} zero_words");
6256 return pc();
6257 }
6258
6259 // base: Address of a buffer to be zeroed, 8 bytes aligned.
6260 // cnt: Immediate count in HeapWords.
6261 //
6262 // r10, r11, rscratch1, and rscratch2 are clobbered.
6263 address MacroAssembler::zero_words(Register base, uint64_t cnt)
6264 {
6265 assert(wordSize <= BlockZeroingLowLimit,
6266 "increase BlockZeroingLowLimit");
6267 address result = nullptr;
6268 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) {
6269 #ifndef PRODUCT
6270 {
6271 char buf[64];
6272 os::snprintf_checked(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt);
6273 BLOCK_COMMENT(buf);
6274 }
6275 #endif
6276 if (cnt >= 16) {
6277 uint64_t loops = cnt/16;
6278 if (loops > 1) {
6279 mov(rscratch2, loops - 1);
6280 }
6281 {
6282 Label loop;
6283 bind(loop);
6284 for (int i = 0; i < 16; i += 2) {
6285 stp(zr, zr, Address(base, i * BytesPerWord));
6286 }
6287 add(base, base, 16 * BytesPerWord);
6288 if (loops > 1) {
6289 subs(rscratch2, rscratch2, 1);
6290 br(GE, loop);
6291 }
6292 }
6293 }
6294 cnt %= 16;
6295 int i = cnt & 1; // store any odd word to start
6296 if (i) str(zr, Address(base));
6297 for (; i < (int)cnt; i += 2) {
6298 stp(zr, zr, Address(base, i * wordSize));
6299 }
6300 BLOCK_COMMENT("} zero_words");
6301 result = pc();
6302 } else {
6303 mov(r10, base); mov(r11, cnt);
6304 result = zero_words(r10, r11);
6305 }
6306 return result;
6307 }
6308
6309 // Zero blocks of memory by using DC ZVA.
6310 //
6311 // Aligns the base address first sufficiently for DC ZVA, then uses
6312 // DC ZVA repeatedly for every full block. cnt is the size to be
6313 // zeroed in HeapWords. Returns the count of words left to be zeroed
6314 // in cnt.
6315 //
6316 // NOTE: This is intended to be used in the zero_blocks() stub. If
6317 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
6318 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
6319 Register tmp = rscratch1;
6320 Register tmp2 = rscratch2;
6321 int zva_length = VM_Version::zva_length();
6322 Label initial_table_end, loop_zva;
6323 Label fini;
6324
6325 // Base must be 16 byte aligned. If not just return and let caller handle it
6326 tst(base, 0x0f);
6327 br(Assembler::NE, fini);
6328 // Align base with ZVA length.
6329 neg(tmp, base);
6330 andr(tmp, tmp, zva_length - 1);
6331
6332 // tmp: the number of bytes to be filled to align the base with ZVA length.
6333 add(base, base, tmp);
6334 sub(cnt, cnt, tmp, Assembler::ASR, 3);
6335 adr(tmp2, initial_table_end);
6336 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
6337 br(tmp2);
6338
6339 for (int i = -zva_length + 16; i < 0; i += 16)
6340 stp(zr, zr, Address(base, i));
6341 bind(initial_table_end);
6342
6343 sub(cnt, cnt, zva_length >> 3);
6344 bind(loop_zva);
6345 dc(Assembler::ZVA, base);
6346 subs(cnt, cnt, zva_length >> 3);
6347 add(base, base, zva_length);
6348 br(Assembler::GE, loop_zva);
6349 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
6350 bind(fini);
6351 }
6352
6353 // base: Address of a buffer to be filled, 8 bytes aligned.
6354 // cnt: Count in 8-byte unit.
6355 // value: Value to be filled with.
6356 // base will point to the end of the buffer after filling.
6357 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
6358 {
6359 // Algorithm:
6360 //
6361 // if (cnt == 0) {
6362 // return;
6363 // }
6364 // if ((p & 8) != 0) {
6365 // *p++ = v;
6366 // }
6367 //
6368 // scratch1 = cnt & 14;
6369 // cnt -= scratch1;
6370 // p += scratch1;
6371 // switch (scratch1 / 2) {
6372 // do {
6373 // cnt -= 16;
6374 // p[-16] = v;
6375 // p[-15] = v;
6376 // case 7:
6377 // p[-14] = v;
6378 // p[-13] = v;
6379 // case 6:
6380 // p[-12] = v;
6381 // p[-11] = v;
6382 // // ...
6383 // case 1:
6384 // p[-2] = v;
6385 // p[-1] = v;
6386 // case 0:
6387 // p += 16;
6388 // } while (cnt);
6389 // }
6390 // if ((cnt & 1) == 1) {
6391 // *p++ = v;
6392 // }
6393
6394 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
6395
6396 Label fini, skip, entry, loop;
6397 const int unroll = 8; // Number of stp instructions we'll unroll
6398
6399 cbz(cnt, fini);
6400 tbz(base, 3, skip);
6401 str(value, Address(post(base, 8)));
6402 sub(cnt, cnt, 1);
6403 bind(skip);
6404
6405 andr(rscratch1, cnt, (unroll-1) * 2);
6406 sub(cnt, cnt, rscratch1);
6407 add(base, base, rscratch1, Assembler::LSL, 3);
6408 adr(rscratch2, entry);
6409 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
6410 br(rscratch2);
6411
6412 bind(loop);
6413 add(base, base, unroll * 16);
6414 for (int i = -unroll; i < 0; i++)
6415 stp(value, value, Address(base, i * 16));
6416 bind(entry);
6417 subs(cnt, cnt, unroll * 2);
6418 br(Assembler::GE, loop);
6419
6420 tbz(cnt, 0, fini);
6421 str(value, Address(post(base, 8)));
6422 bind(fini);
6423 }
6424
6425 // Intrinsic for
6426 //
6427 // - sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6428 // Encodes char[] to byte[] in ISO-8859-1
6429 //
6430 // - java.lang.StringCoding#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6431 // Encodes byte[] (containing UTF-16) to byte[] in ISO-8859-1
6432 //
6433 // - java.lang.StringCoding#encodeAsciiArray0(char[] sa, int sp, byte[] da, int dp, int len)
6434 // Encodes char[] to byte[] in ASCII
6435 //
6436 // This version always returns the number of characters copied, and does not
6437 // clobber the 'len' register. A successful copy will complete with the post-
6438 // condition: 'res' == 'len', while an unsuccessful copy will exit with the
6439 // post-condition: 0 <= 'res' < 'len'.
6440 //
6441 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
6442 // degrade performance (on Ampere Altra - Neoverse N1), to an extent
6443 // beyond the acceptable, even though the footprint would be smaller.
6444 // Using 'umaxv' in the ASCII-case comes with a small penalty but does
6445 // avoid additional bloat.
6446 //
6447 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags
6448 void MacroAssembler::encode_iso_array(Register src, Register dst,
6449 Register len, Register res, bool ascii,
6450 FloatRegister vtmp0, FloatRegister vtmp1,
6451 FloatRegister vtmp2, FloatRegister vtmp3,
6452 FloatRegister vtmp4, FloatRegister vtmp5)
6453 {
6454 Register cnt = res;
6455 Register max = rscratch1;
6456 Register chk = rscratch2;
6457
6458 prfm(Address(src), PLDL1STRM);
6459 movw(cnt, len);
6460
6461 #define ASCII(insn) do { if (ascii) { insn; } } while (0)
6462
6463 Label LOOP_32, DONE_32, FAIL_32;
6464
6465 BIND(LOOP_32);
6466 {
6467 cmpw(cnt, 32);
6468 br(LT, DONE_32);
6469 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
6470 // Extract lower bytes.
6471 FloatRegister vlo0 = vtmp4;
6472 FloatRegister vlo1 = vtmp5;
6473 uzp1(vlo0, T16B, vtmp0, vtmp1);
6474 uzp1(vlo1, T16B, vtmp2, vtmp3);
6475 // Merge bits...
6476 orr(vtmp0, T16B, vtmp0, vtmp1);
6477 orr(vtmp2, T16B, vtmp2, vtmp3);
6478 // Extract merged upper bytes.
6479 FloatRegister vhix = vtmp0;
6480 uzp2(vhix, T16B, vtmp0, vtmp2);
6481 // ISO-check on hi-parts (all zero).
6482 // ASCII-check on lo-parts (no sign).
6483 FloatRegister vlox = vtmp1; // Merge lower bytes.
6484 ASCII(orr(vlox, T16B, vlo0, vlo1));
6485 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox));
6486 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox));
6487 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0));
6488 ASCII(orr(chk, chk, max));
6489 cbnz(chk, FAIL_32);
6490 subw(cnt, cnt, 32);
6491 st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
6492 b(LOOP_32);
6493 }
6494 BIND(FAIL_32);
6495 sub(src, src, 64);
6496 BIND(DONE_32);
6497
6498 Label LOOP_8, SKIP_8;
6499
6500 BIND(LOOP_8);
6501 {
6502 cmpw(cnt, 8);
6503 br(LT, SKIP_8);
6504 FloatRegister vhi = vtmp0;
6505 FloatRegister vlo = vtmp1;
6506 ld1(vtmp3, T8H, src);
6507 uzp1(vlo, T16B, vtmp3, vtmp3);
6508 uzp2(vhi, T16B, vtmp3, vtmp3);
6509 // ISO-check on hi-parts (all zero).
6510 // ASCII-check on lo-parts (no sign).
6511 ASCII(cm(LT, vtmp2, T16B, vlo));
6512 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2));
6513 ASCII(umov(max, vtmp2, B, 0));
6514 ASCII(orr(chk, chk, max));
6515 cbnz(chk, SKIP_8);
6516
6517 strd(vlo, Address(post(dst, 8)));
6518 subw(cnt, cnt, 8);
6519 add(src, src, 16);
6520 b(LOOP_8);
6521 }
6522 BIND(SKIP_8);
6523
6524 #undef ASCII
6525
6526 Label LOOP, DONE;
6527
6528 cbz(cnt, DONE);
6529 BIND(LOOP);
6530 {
6531 Register chr = rscratch1;
6532 ldrh(chr, Address(post(src, 2)));
6533 tst(chr, ascii ? 0xff80 : 0xff00);
6534 br(NE, DONE);
6535 strb(chr, Address(post(dst, 1)));
6536 subs(cnt, cnt, 1);
6537 br(GT, LOOP);
6538 }
6539 BIND(DONE);
6540 // Return index where we stopped.
6541 subw(res, len, cnt);
6542 }
6543
6544 // Inflate byte[] array to char[].
6545 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6
6546 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
6547 FloatRegister vtmp1, FloatRegister vtmp2,
6548 FloatRegister vtmp3, Register tmp4) {
6549 Label big, done, after_init, to_stub;
6550
6551 assert_different_registers(src, dst, len, tmp4, rscratch1);
6552
6553 fmovd(vtmp1, 0.0);
6554 lsrw(tmp4, len, 3);
6555 bind(after_init);
6556 cbnzw(tmp4, big);
6557 // Short string: less than 8 bytes.
6558 {
6559 Label loop, tiny;
6560
6561 cmpw(len, 4);
6562 br(LT, tiny);
6563 // Use SIMD to do 4 bytes.
6564 ldrs(vtmp2, post(src, 4));
6565 zip1(vtmp3, T8B, vtmp2, vtmp1);
6566 subw(len, len, 4);
6567 strd(vtmp3, post(dst, 8));
6568
6569 cbzw(len, done);
6570
6571 // Do the remaining bytes by steam.
6572 bind(loop);
6573 ldrb(tmp4, post(src, 1));
6574 strh(tmp4, post(dst, 2));
6575 subw(len, len, 1);
6576
6577 bind(tiny);
6578 cbnz(len, loop);
6579
6580 b(done);
6581 }
6582
6583 if (SoftwarePrefetchHintDistance >= 0) {
6584 bind(to_stub);
6585 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
6586 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated");
6587 address tpc = trampoline_call(stub);
6588 if (tpc == nullptr) {
6589 DEBUG_ONLY(reset_labels(big, done));
6590 postcond(pc() == badAddress);
6591 return nullptr;
6592 }
6593 b(after_init);
6594 }
6595
6596 // Unpack the bytes 8 at a time.
6597 bind(big);
6598 {
6599 Label loop, around, loop_last, loop_start;
6600
6601 if (SoftwarePrefetchHintDistance >= 0) {
6602 const int large_loop_threshold = (64 + 16)/8;
6603 ldrd(vtmp2, post(src, 8));
6604 andw(len, len, 7);
6605 cmp(tmp4, (u1)large_loop_threshold);
6606 br(GE, to_stub);
6607 b(loop_start);
6608
6609 bind(loop);
6610 ldrd(vtmp2, post(src, 8));
6611 bind(loop_start);
6612 subs(tmp4, tmp4, 1);
6613 br(EQ, loop_last);
6614 zip1(vtmp2, T16B, vtmp2, vtmp1);
6615 ldrd(vtmp3, post(src, 8));
6616 st1(vtmp2, T8H, post(dst, 16));
6617 subs(tmp4, tmp4, 1);
6618 zip1(vtmp3, T16B, vtmp3, vtmp1);
6619 st1(vtmp3, T8H, post(dst, 16));
6620 br(NE, loop);
6621 b(around);
6622 bind(loop_last);
6623 zip1(vtmp2, T16B, vtmp2, vtmp1);
6624 st1(vtmp2, T8H, post(dst, 16));
6625 bind(around);
6626 cbz(len, done);
6627 } else {
6628 andw(len, len, 7);
6629 bind(loop);
6630 ldrd(vtmp2, post(src, 8));
6631 sub(tmp4, tmp4, 1);
6632 zip1(vtmp3, T16B, vtmp2, vtmp1);
6633 st1(vtmp3, T8H, post(dst, 16));
6634 cbnz(tmp4, loop);
6635 }
6636 }
6637
6638 // Do the tail of up to 8 bytes.
6639 add(src, src, len);
6640 ldrd(vtmp3, Address(src, -8));
6641 add(dst, dst, len, ext::uxtw, 1);
6642 zip1(vtmp3, T16B, vtmp3, vtmp1);
6643 strq(vtmp3, Address(dst, -16));
6644
6645 bind(done);
6646 postcond(pc() != badAddress);
6647 return pc();
6648 }
6649
6650 // Compress char[] array to byte[].
6651 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
6652 // Return the array length if every element in array can be encoded,
6653 // otherwise, the index of first non-latin1 (> 0xff) character.
6654 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
6655 Register res,
6656 FloatRegister tmp0, FloatRegister tmp1,
6657 FloatRegister tmp2, FloatRegister tmp3,
6658 FloatRegister tmp4, FloatRegister tmp5) {
6659 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
6660 }
6661
6662 // java.math.round(double a)
6663 // Returns the closest long to the argument, with ties rounding to
6664 // positive infinity. This requires some fiddling for corner
6665 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5).
6666 void MacroAssembler::java_round_double(Register dst, FloatRegister src,
6667 FloatRegister ftmp) {
6668 Label DONE;
6669 BLOCK_COMMENT("java_round_double: { ");
6670 fmovd(rscratch1, src);
6671 // Use RoundToNearestTiesAway unless src small and -ve.
6672 fcvtasd(dst, src);
6673 // Test if src >= 0 || abs(src) >= 0x1.0p52
6674 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit
6675 mov(rscratch2, julong_cast(0x1.0p52));
6676 cmp(rscratch1, rscratch2);
6677 br(HS, DONE); {
6678 // src < 0 && abs(src) < 0x1.0p52
6679 // src may have a fractional part, so add 0.5
6680 fmovd(ftmp, 0.5);
6681 faddd(ftmp, src, ftmp);
6682 // Convert double to jlong, use RoundTowardsNegative
6683 fcvtmsd(dst, ftmp);
6684 }
6685 bind(DONE);
6686 BLOCK_COMMENT("} java_round_double");
6687 }
6688
6689 void MacroAssembler::java_round_float(Register dst, FloatRegister src,
6690 FloatRegister ftmp) {
6691 Label DONE;
6692 BLOCK_COMMENT("java_round_float: { ");
6693 fmovs(rscratch1, src);
6694 // Use RoundToNearestTiesAway unless src small and -ve.
6695 fcvtassw(dst, src);
6696 // Test if src >= 0 || abs(src) >= 0x1.0p23
6697 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit
6698 mov(rscratch2, jint_cast(0x1.0p23f));
6699 cmp(rscratch1, rscratch2);
6700 br(HS, DONE); {
6701 // src < 0 && |src| < 0x1.0p23
6702 // src may have a fractional part, so add 0.5
6703 fmovs(ftmp, 0.5f);
6704 fadds(ftmp, src, ftmp);
6705 // Convert float to jint, use RoundTowardsNegative
6706 fcvtmssw(dst, ftmp);
6707 }
6708 bind(DONE);
6709 BLOCK_COMMENT("} java_round_float");
6710 }
6711
6712 // get_thread() can be called anywhere inside generated code so we
6713 // need to save whatever non-callee save context might get clobbered
6714 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
6715 // the call setup code.
6716 //
6717 // On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags.
6718 // On other systems, the helper is a usual C function.
6719 //
6720 void MacroAssembler::get_thread(Register dst) {
6721 RegSet saved_regs =
6722 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6723 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6724
6725 protect_return_address();
6726 push(saved_regs, sp);
6727
6728 mov(lr, ExternalAddress(CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)));
6729 blr(lr);
6730 if (dst != c_rarg0) {
6731 mov(dst, c_rarg0);
6732 }
6733
6734 pop(saved_regs, sp);
6735 authenticate_return_address();
6736 }
6737
6738 void MacroAssembler::cache_wb(Address line) {
6739 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6740 assert(line.index() == noreg, "index should be noreg");
6741 assert(line.offset() == 0, "offset should be 0");
6742 // would like to assert this
6743 // assert(line._ext.shift == 0, "shift should be zero");
6744 if (VM_Version::supports_dcpop()) {
6745 // writeback using clear virtual address to point of persistence
6746 dc(Assembler::CVAP, line.base());
6747 } else {
6748 // no need to generate anything as Unsafe.writebackMemory should
6749 // never invoke this stub
6750 }
6751 }
6752
6753 void MacroAssembler::cache_wbsync(bool is_pre) {
6754 // we only need a barrier post sync
6755 if (!is_pre) {
6756 membar(Assembler::AnyAny);
6757 }
6758 }
6759
6760 void MacroAssembler::verify_sve_vector_length(Register tmp) {
6761 if (!UseSVE || VM_Version::get_max_supported_sve_vector_length() == FloatRegister::sve_vl_min) {
6762 return;
6763 }
6764 // Make sure that native code does not change SVE vector length.
6765 Label verify_ok;
6766 movw(tmp, zr);
6767 sve_inc(tmp, B);
6768 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length());
6769 br(EQ, verify_ok);
6770 stop("Error: SVE vector length has changed since jvm startup");
6771 bind(verify_ok);
6772 }
6773
6774 void MacroAssembler::verify_ptrue() {
6775 Label verify_ok;
6776 if (!UseSVE) {
6777 return;
6778 }
6779 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
6780 sve_dec(rscratch1, B);
6781 cbz(rscratch1, verify_ok);
6782 stop("Error: the preserved predicate register (p7) elements are not all true");
6783 bind(verify_ok);
6784 }
6785
6786 void MacroAssembler::safepoint_isb() {
6787 isb();
6788 #ifndef PRODUCT
6789 if (VerifyCrossModifyFence) {
6790 // Clear the thread state.
6791 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6792 }
6793 #endif
6794 }
6795
6796 #ifndef PRODUCT
6797 void MacroAssembler::verify_cross_modify_fence_not_required() {
6798 if (VerifyCrossModifyFence) {
6799 // Check if thread needs a cross modify fence.
6800 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6801 Label fence_not_required;
6802 cbz(rscratch1, fence_not_required);
6803 // If it does then fail.
6804 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure)));
6805 mov(c_rarg0, rthread);
6806 blr(rscratch1);
6807 bind(fence_not_required);
6808 }
6809 }
6810 #endif
6811
6812 void MacroAssembler::spin_wait() {
6813 block_comment("spin_wait {");
6814 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
6815 switch (VM_Version::spin_wait_desc().inst()) {
6816 case SpinWait::NOP:
6817 nop();
6818 break;
6819 case SpinWait::ISB:
6820 isb();
6821 break;
6822 case SpinWait::YIELD:
6823 yield();
6824 break;
6825 case SpinWait::SB:
6826 assert(VM_Version::supports_sb(), "current CPU does not support SB instruction");
6827 sb();
6828 break;
6829 default:
6830 ShouldNotReachHere();
6831 }
6832 }
6833 block_comment("}");
6834 }
6835
6836 // Stack frame creation/removal
6837
6838 void MacroAssembler::enter(bool strip_ret_addr) {
6839 if (strip_ret_addr) {
6840 // Addresses can only be signed once. If there are multiple nested frames being created
6841 // in the same function, then the return address needs stripping first.
6842 strip_return_address();
6843 }
6844 protect_return_address();
6845 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6846 mov(rfp, sp);
6847 }
6848
6849 void MacroAssembler::leave() {
6850 mov(sp, rfp);
6851 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6852 authenticate_return_address();
6853 }
6854
6855 // ROP Protection
6856 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/
6857 // destroying stack frames or whenever directly loading/storing the LR to memory.
6858 // If ROP protection is not set then these functions are no-ops.
6859 // For more details on PAC see pauth_aarch64.hpp.
6860
6861 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory.
6862 // Uses value zero as the modifier.
6863 //
6864 void MacroAssembler::protect_return_address() {
6865 if (VM_Version::use_rop_protection()) {
6866 check_return_address();
6867 paciaz();
6868 }
6869 }
6870
6871 // Sign the return value in the given register. Use before updating the LR in the existing stack
6872 // frame for the current function.
6873 // Uses value zero as the modifier.
6874 //
6875 void MacroAssembler::protect_return_address(Register return_reg) {
6876 if (VM_Version::use_rop_protection()) {
6877 check_return_address(return_reg);
6878 paciza(return_reg);
6879 }
6880 }
6881
6882 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory.
6883 // Uses value zero as the modifier.
6884 //
6885 void MacroAssembler::authenticate_return_address() {
6886 if (VM_Version::use_rop_protection()) {
6887 autiaz();
6888 check_return_address();
6889 }
6890 }
6891
6892 // Authenticate the return value in the given register. Use before updating the LR in the existing
6893 // stack frame for the current function.
6894 // Uses value zero as the modifier.
6895 //
6896 void MacroAssembler::authenticate_return_address(Register return_reg) {
6897 if (VM_Version::use_rop_protection()) {
6898 autiza(return_reg);
6899 check_return_address(return_reg);
6900 }
6901 }
6902
6903 // Strip any PAC data from LR without performing any authentication. Use with caution - only if
6904 // there is no guaranteed way of authenticating the LR.
6905 //
6906 void MacroAssembler::strip_return_address() {
6907 if (VM_Version::use_rop_protection()) {
6908 xpaclri();
6909 }
6910 }
6911
6912 #ifndef PRODUCT
6913 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only
6914 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point
6915 // it is difficult to debug back to the callee function.
6916 // This function simply loads from the address in the given register.
6917 // Use directly after authentication to catch authentication failures.
6918 // Also use before signing to check that the pointer is valid and hasn't already been signed.
6919 //
6920 void MacroAssembler::check_return_address(Register return_reg) {
6921 if (VM_Version::use_rop_protection()) {
6922 ldr(zr, Address(return_reg));
6923 }
6924 }
6925 #endif
6926
6927 // The java_calling_convention describes stack locations as ideal slots on
6928 // a frame with no abi restrictions. Since we must observe abi restrictions
6929 // (like the placement of the register window) the slots must be biased by
6930 // the following value.
6931 static int reg2offset_in(VMReg r) {
6932 // Account for saved rfp and lr
6933 // This should really be in_preserve_stack_slots
6934 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
6935 }
6936
6937 static int reg2offset_out(VMReg r) {
6938 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
6939 }
6940
6941 // On 64bit we will store integer like items to the stack as
6942 // 64bits items (AArch64 ABI) even though java would only store
6943 // 32bits for a parameter. On 32bit it will simply be 32bits
6944 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
6945 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
6946 if (src.first()->is_stack()) {
6947 if (dst.first()->is_stack()) {
6948 // stack to stack
6949 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6950 str(tmp, Address(sp, reg2offset_out(dst.first())));
6951 } else {
6952 // stack to reg
6953 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
6954 }
6955 } else if (dst.first()->is_stack()) {
6956 // reg to stack
6957 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
6958 } else {
6959 if (dst.first() != src.first()) {
6960 sxtw(dst.first()->as_Register(), src.first()->as_Register());
6961 }
6962 }
6963 }
6964
6965 // An oop arg. Must pass a handle not the oop itself
6966 void MacroAssembler::object_move(
6967 OopMap* map,
6968 int oop_handle_offset,
6969 int framesize_in_slots,
6970 VMRegPair src,
6971 VMRegPair dst,
6972 bool is_receiver,
6973 int* receiver_offset) {
6974
6975 // must pass a handle. First figure out the location we use as a handle
6976
6977 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register();
6978
6979 // See if oop is null if it is we need no handle
6980
6981 if (src.first()->is_stack()) {
6982
6983 // Oop is already on the stack as an argument
6984 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
6985 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
6986 if (is_receiver) {
6987 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
6988 }
6989
6990 ldr(rscratch1, Address(rfp, reg2offset_in(src.first())));
6991 lea(rHandle, Address(rfp, reg2offset_in(src.first())));
6992 // conditionally move a null
6993 cmp(rscratch1, zr);
6994 csel(rHandle, zr, rHandle, Assembler::EQ);
6995 } else {
6996
6997 // Oop is in an a register we must store it to the space we reserve
6998 // on the stack for oop_handles and pass a handle if oop is non-null
6999
7000 const Register rOop = src.first()->as_Register();
7001 int oop_slot;
7002 if (rOop == j_rarg0)
7003 oop_slot = 0;
7004 else if (rOop == j_rarg1)
7005 oop_slot = 1;
7006 else if (rOop == j_rarg2)
7007 oop_slot = 2;
7008 else if (rOop == j_rarg3)
7009 oop_slot = 3;
7010 else if (rOop == j_rarg4)
7011 oop_slot = 4;
7012 else if (rOop == j_rarg5)
7013 oop_slot = 5;
7014 else if (rOop == j_rarg6)
7015 oop_slot = 6;
7016 else {
7017 assert(rOop == j_rarg7, "wrong register");
7018 oop_slot = 7;
7019 }
7020
7021 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
7022 int offset = oop_slot*VMRegImpl::stack_slot_size;
7023
7024 map->set_oop(VMRegImpl::stack2reg(oop_slot));
7025 // Store oop in handle area, may be null
7026 str(rOop, Address(sp, offset));
7027 if (is_receiver) {
7028 *receiver_offset = offset;
7029 }
7030
7031 cmp(rOop, zr);
7032 lea(rHandle, Address(sp, offset));
7033 // conditionally move a null
7034 csel(rHandle, zr, rHandle, Assembler::EQ);
7035 }
7036
7037 // If arg is on the stack then place it otherwise it is already in correct reg.
7038 if (dst.first()->is_stack()) {
7039 str(rHandle, Address(sp, reg2offset_out(dst.first())));
7040 }
7041 }
7042
7043 // A float arg may have to do float reg int reg conversion
7044 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
7045 if (src.first()->is_stack()) {
7046 if (dst.first()->is_stack()) {
7047 ldrw(tmp, Address(rfp, reg2offset_in(src.first())));
7048 strw(tmp, Address(sp, reg2offset_out(dst.first())));
7049 } else {
7050 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7051 }
7052 } else if (src.first() != dst.first()) {
7053 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7054 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7055 else
7056 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7057 }
7058 }
7059
7060 // A long move
7061 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
7062 if (src.first()->is_stack()) {
7063 if (dst.first()->is_stack()) {
7064 // stack to stack
7065 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7066 str(tmp, Address(sp, reg2offset_out(dst.first())));
7067 } else {
7068 // stack to reg
7069 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
7070 }
7071 } else if (dst.first()->is_stack()) {
7072 // reg to stack
7073 // Do we really have to sign extend???
7074 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
7075 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
7076 } else {
7077 if (dst.first() != src.first()) {
7078 mov(dst.first()->as_Register(), src.first()->as_Register());
7079 }
7080 }
7081 }
7082
7083
7084 // A double move
7085 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
7086 if (src.first()->is_stack()) {
7087 if (dst.first()->is_stack()) {
7088 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7089 str(tmp, Address(sp, reg2offset_out(dst.first())));
7090 } else {
7091 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7092 }
7093 } else if (src.first() != dst.first()) {
7094 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7095 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7096 else
7097 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7098 }
7099 }
7100
7101 // Implements fast-locking.
7102 //
7103 // - obj: the object to be locked
7104 // - t1, t2, t3: temporary registers, will be destroyed
7105 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding).
7106 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow) {
7107 assert_different_registers(basic_lock, obj, t1, t2, t3, rscratch1);
7108
7109 Label push;
7110 const Register top = t1;
7111 const Register mark = t2;
7112 const Register t = t3;
7113
7114 // Preload the markWord. It is important that this is the first
7115 // instruction emitted as it is part of C1's null check semantics.
7116 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7117
7118 if (UseObjectMonitorTable) {
7119 // Clear cache in case fast locking succeeds or we need to take the slow-path.
7120 str(zr, Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))));
7121 }
7122
7123 if (DiagnoseSyncOnValueBasedClasses != 0) {
7124 load_klass(t1, obj);
7125 ldrb(t1, Address(t1, Klass::misc_flags_offset()));
7126 tst(t1, KlassFlags::_misc_is_value_based_class);
7127 br(Assembler::NE, slow);
7128 }
7129
7130 // Check if the lock-stack is full.
7131 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7132 cmpw(top, (unsigned)LockStack::end_offset());
7133 br(Assembler::GE, slow);
7134
7135 // Check for recursion.
7136 subw(t, top, oopSize);
7137 ldr(t, Address(rthread, t));
7138 cmp(obj, t);
7139 br(Assembler::EQ, push);
7140
7141 // Check header for monitor (0b10).
7142 tst(mark, markWord::monitor_value);
7143 br(Assembler::NE, slow);
7144
7145 // Try to lock. Transition lock bits 0b01 => 0b00
7146 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7147 orr(mark, mark, markWord::unlocked_value);
7148 eor(t, mark, markWord::unlocked_value);
7149 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
7150 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
7151 br(Assembler::NE, slow);
7152
7153 bind(push);
7154 // After successful lock, push object on lock-stack.
7155 str(obj, Address(rthread, top));
7156 addw(top, top, oopSize);
7157 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7158 }
7159
7160 // Implements fast-unlocking.
7161 //
7162 // - obj: the object to be unlocked
7163 // - t1, t2, t3: temporary registers
7164 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
7165 void MacroAssembler::fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
7166 // cmpxchg clobbers rscratch1.
7167 assert_different_registers(obj, t1, t2, t3, rscratch1);
7168
7169 #ifdef ASSERT
7170 {
7171 // Check for lock-stack underflow.
7172 Label stack_ok;
7173 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
7174 cmpw(t1, (unsigned)LockStack::start_offset());
7175 br(Assembler::GE, stack_ok);
7176 STOP("Lock-stack underflow");
7177 bind(stack_ok);
7178 }
7179 #endif
7180
7181 Label unlocked, push_and_slow;
7182 const Register top = t1;
7183 const Register mark = t2;
7184 const Register t = t3;
7185
7186 // Check if obj is top of lock-stack.
7187 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7188 subw(top, top, oopSize);
7189 ldr(t, Address(rthread, top));
7190 cmp(obj, t);
7191 br(Assembler::NE, slow);
7192
7193 // Pop lock-stack.
7194 DEBUG_ONLY(str(zr, Address(rthread, top));)
7195 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7196
7197 // Check if recursive.
7198 subw(t, top, oopSize);
7199 ldr(t, Address(rthread, t));
7200 cmp(obj, t);
7201 br(Assembler::EQ, unlocked);
7202
7203 // Not recursive. Check header for monitor (0b10).
7204 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7205 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow);
7206
7207 #ifdef ASSERT
7208 // Check header not unlocked (0b01).
7209 Label not_unlocked;
7210 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked);
7211 stop("fast_unlock already unlocked");
7212 bind(not_unlocked);
7213 #endif
7214
7215 // Try to unlock. Transition lock bits 0b00 => 0b01
7216 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7217 orr(t, mark, markWord::unlocked_value);
7218 cmpxchg(obj, mark, t, Assembler::xword,
7219 /*acquire*/ false, /*release*/ true, /*weak*/ false, noreg);
7220 br(Assembler::EQ, unlocked);
7221
7222 bind(push_and_slow);
7223 // Restore lock-stack and handle the unlock in runtime.
7224 DEBUG_ONLY(str(obj, Address(rthread, top));)
7225 addw(top, top, oopSize);
7226 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7227 b(slow);
7228
7229 bind(unlocked);
7230 }