1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "ci/ciEnv.hpp"
29 #include "ci/ciInlineKlass.hpp"
30 #include "code/compiledIC.hpp"
31 #include "compiler/compileTask.hpp"
32 #include "compiler/disassembler.hpp"
33 #include "compiler/oopMap.hpp"
34 #include "gc/shared/barrierSet.hpp"
35 #include "gc/shared/barrierSetAssembler.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/cardTable.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/tlab_globals.hpp"
40 #include "interpreter/bytecodeHistogram.hpp"
41 #include "interpreter/interpreter.hpp"
42 #include "interpreter/interpreterRuntime.hpp"
43 #include "jvm.h"
44 #include "memory/resourceArea.hpp"
45 #include "memory/universe.hpp"
46 #include "nativeInst_aarch64.hpp"
47 #include "oops/accessDecorators.hpp"
48 #include "oops/compressedKlass.inline.hpp"
49 #include "oops/compressedOops.inline.hpp"
50 #include "oops/klass.inline.hpp"
51 #include "oops/resolvedFieldEntry.hpp"
52 #include "runtime/arguments.hpp"
53 #include "runtime/continuation.hpp"
54 #include "runtime/globals.hpp"
55 #include "runtime/icache.hpp"
56 #include "runtime/interfaceSupport.inline.hpp"
57 #include "runtime/javaThread.hpp"
58 #include "runtime/jniHandles.inline.hpp"
59 #include "runtime/sharedRuntime.hpp"
60 #include "runtime/signature_cc.hpp"
61 #include "runtime/stubRoutines.hpp"
62 #include "utilities/globalDefinitions.hpp"
63 #include "utilities/powerOfTwo.hpp"
64 #include "vmreg_aarch64.inline.hpp"
65 #ifdef COMPILER1
66 #include "c1/c1_LIRAssembler.hpp"
67 #endif
68 #ifdef COMPILER2
69 #include "oops/oop.hpp"
70 #include "opto/compile.hpp"
71 #include "opto/node.hpp"
72 #include "opto/output.hpp"
73 #endif
74
75 #include <sys/types.h>
76
77 #ifdef PRODUCT
78 #define BLOCK_COMMENT(str) /* nothing */
79 #else
80 #define BLOCK_COMMENT(str) block_comment(str)
81 #endif
82 #define STOP(str) stop(str);
83 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
84
85 #ifdef ASSERT
86 extern "C" void disnm(intptr_t p);
87 #endif
88 // Target-dependent relocation processing
89 //
90 // Instruction sequences whose target may need to be retrieved or
91 // patched are distinguished by their leading instruction, sorting
92 // them into three main instruction groups and related subgroups.
93 //
94 // 1) Branch, Exception and System (insn count = 1)
95 // 1a) Unconditional branch (immediate):
96 // b/bl imm19
97 // 1b) Compare & branch (immediate):
98 // cbz/cbnz Rt imm19
99 // 1c) Test & branch (immediate):
100 // tbz/tbnz Rt imm14
101 // 1d) Conditional branch (immediate):
102 // b.cond imm19
103 //
104 // 2) Loads and Stores (insn count = 1)
105 // 2a) Load register literal:
106 // ldr Rt imm19
107 //
108 // 3) Data Processing Immediate (insn count = 2 or 3)
109 // 3a) PC-rel. addressing
110 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12
111 // adr/adrp Rx imm21; add Ry Rx #imm12
112 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page]
113 // adr/adrp Rx imm21
114 // adr/adrp Rx imm21; movk Rx #imm16<<32
115 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page
116 // The latter form can only happen when the target is an
117 // ExternalAddress, and (by definition) ExternalAddresses don't
118 // move. Because of that property, there is never any need to
119 // patch the last of the three instructions. However,
120 // MacroAssembler::target_addr_for_insn takes all three
121 // instructions into account and returns the correct address.
122 // 3b) Move wide (immediate)
123 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32;
124 //
125 // A switch on a subset of the instruction's bits provides an
126 // efficient dispatch to these subcases.
127 //
128 // insn[28:26] -> main group ('x' == don't care)
129 // 00x -> UNALLOCATED
130 // 100 -> Data Processing Immediate
131 // 101 -> Branch, Exception and System
132 // x1x -> Loads and Stores
133 //
134 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care).
135 // n.b. in some cases extra bits need to be checked to verify the
136 // instruction is as expected
137 //
138 // 1) ... xx101x Branch, Exception and System
139 // 1a) 00___x Unconditional branch (immediate)
140 // 1b) 01___0 Compare & branch (immediate)
141 // 1c) 01___1 Test & branch (immediate)
142 // 1d) 10___0 Conditional branch (immediate)
143 // other Should not happen
144 //
145 // 2) ... xxx1x0 Loads and Stores
146 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0)
147 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0)
148 // strictly should be 64 bit non-FP/SIMD i.e.
149 // 0101_000 (i.e. requires insn[31:24] == 01011000)
150 //
151 // 3) ... xx100x Data Processing Immediate
152 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0)
153 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01)
154 // strictly should be 64 bit movz #imm16<<0
155 // 110___10100 (i.e. requires insn[31:21] == 11010010100)
156 //
157
158 static uint32_t insn_at(address insn_addr, int n) {
159 return ((uint32_t*)insn_addr)[n];
160 }
161
162 template<typename T>
163 class RelocActions : public AllStatic {
164
165 public:
166
167 static int ALWAYSINLINE run(address insn_addr, address &target) {
168 int instructions = 1;
169 uint32_t insn = insn_at(insn_addr, 0);
170
171 uint32_t dispatch = Instruction_aarch64::extract(insn, 30, 25);
172 switch(dispatch) {
173 case 0b001010:
174 case 0b001011: {
175 instructions = T::unconditionalBranch(insn_addr, target);
176 break;
177 }
178 case 0b101010: // Conditional branch (immediate)
179 case 0b011010: { // Compare & branch (immediate)
180 instructions = T::conditionalBranch(insn_addr, target);
181 break;
182 }
183 case 0b011011: {
184 instructions = T::testAndBranch(insn_addr, target);
185 break;
186 }
187 case 0b001100:
188 case 0b001110:
189 case 0b011100:
190 case 0b011110:
191 case 0b101100:
192 case 0b101110:
193 case 0b111100:
194 case 0b111110: {
195 // load/store
196 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
197 // Load register (literal)
198 instructions = T::loadStore(insn_addr, target);
199 break;
200 } else {
201 // nothing to do
202 assert(target == nullptr, "did not expect to relocate target for polling page load");
203 }
204 break;
205 }
206 case 0b001000:
207 case 0b011000:
208 case 0b101000:
209 case 0b111000: {
210 // adr/adrp
211 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
212 int shift = Instruction_aarch64::extract(insn, 31, 31);
213 if (shift) {
214 uint32_t insn2 = insn_at(insn_addr, 1);
215 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
216 Instruction_aarch64::extract(insn, 4, 0) ==
217 Instruction_aarch64::extract(insn2, 9, 5)) {
218 instructions = T::adrp(insn_addr, target, T::adrpMem);
219 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
220 Instruction_aarch64::extract(insn, 4, 0) ==
221 Instruction_aarch64::extract(insn2, 4, 0)) {
222 instructions = T::adrp(insn_addr, target, T::adrpAdd);
223 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
224 Instruction_aarch64::extract(insn, 4, 0) ==
225 Instruction_aarch64::extract(insn2, 4, 0)) {
226 instructions = T::adrp(insn_addr, target, T::adrpMovk);
227 } else {
228 ShouldNotReachHere();
229 }
230 } else {
231 instructions = T::adr(insn_addr, target);
232 }
233 break;
234 }
235 case 0b001001:
236 case 0b011001:
237 case 0b101001:
238 case 0b111001: {
239 instructions = T::immediate(insn_addr, target);
240 break;
241 }
242 default: {
243 ShouldNotReachHere();
244 }
245 }
246
247 T::verify(insn_addr, target);
248 return instructions * NativeInstruction::instruction_size;
249 }
250 };
251
252 class Patcher : public AllStatic {
253 public:
254 static int unconditionalBranch(address insn_addr, address &target) {
255 intptr_t offset = (target - insn_addr) >> 2;
256 Instruction_aarch64::spatch(insn_addr, 25, 0, offset);
257 return 1;
258 }
259 static int conditionalBranch(address insn_addr, address &target) {
260 intptr_t offset = (target - insn_addr) >> 2;
261 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
262 return 1;
263 }
264 static int testAndBranch(address insn_addr, address &target) {
265 intptr_t offset = (target - insn_addr) >> 2;
266 Instruction_aarch64::spatch(insn_addr, 18, 5, offset);
267 return 1;
268 }
269 static int loadStore(address insn_addr, address &target) {
270 intptr_t offset = (target - insn_addr) >> 2;
271 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
272 return 1;
273 }
274 static int adr(address insn_addr, address &target) {
275 #ifdef ASSERT
276 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
277 #endif
278 // PC-rel. addressing
279 ptrdiff_t offset = target - insn_addr;
280 int offset_lo = offset & 3;
281 offset >>= 2;
282 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
283 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
284 return 1;
285 }
286 template<typename U>
287 static int adrp(address insn_addr, address &target, U inner) {
288 int instructions = 1;
289 #ifdef ASSERT
290 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
291 #endif
292 ptrdiff_t offset = target - insn_addr;
293 instructions = 2;
294 precond(inner != nullptr);
295 // Give the inner reloc a chance to modify the target.
296 address adjusted_target = target;
297 instructions = inner(insn_addr, adjusted_target);
298 uintptr_t pc_page = (uintptr_t)insn_addr >> 12;
299 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12;
300 offset = adr_page - pc_page;
301 int offset_lo = offset & 3;
302 offset >>= 2;
303 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
304 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
305 return instructions;
306 }
307 static int adrpMem(address insn_addr, address &target) {
308 uintptr_t dest = (uintptr_t)target;
309 int offset_lo = dest & 0xfff;
310 uint32_t insn2 = insn_at(insn_addr, 1);
311 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
312 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size);
313 guarantee(((dest >> size) << size) == dest, "misaligned target");
314 return 2;
315 }
316 static int adrpAdd(address insn_addr, address &target) {
317 uintptr_t dest = (uintptr_t)target;
318 int offset_lo = dest & 0xfff;
319 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo);
320 return 2;
321 }
322 static int adrpMovk(address insn_addr, address &target) {
323 uintptr_t dest = uintptr_t(target);
324 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32);
325 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL);
326 target = address(dest);
327 return 2;
328 }
329 static int immediate(address insn_addr, address &target) {
330 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010100, "must be");
331 uint64_t dest = (uint64_t)target;
332 // Move wide constant
333 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
334 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
335 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
336 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
337 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
338 return 3;
339 }
340 static void verify(address insn_addr, address &target) {
341 #ifdef ASSERT
342 address address_is = MacroAssembler::target_addr_for_insn(insn_addr);
343 if (!(address_is == target)) {
344 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target);
345 disnm((intptr_t)insn_addr);
346 assert(address_is == target, "should be");
347 }
348 #endif
349 }
350 };
351
352 // If insn1 and insn2 use the same register to form an address, either
353 // by an offsetted LDR or a simple ADD, return the offset. If the
354 // second instruction is an LDR, the offset may be scaled.
355 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) {
356 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
357 Instruction_aarch64::extract(insn1, 4, 0) ==
358 Instruction_aarch64::extract(insn2, 9, 5)) {
359 // Load/store register (unsigned immediate)
360 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
361 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
362 byte_offset <<= size;
363 return true;
364 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
365 Instruction_aarch64::extract(insn1, 4, 0) ==
366 Instruction_aarch64::extract(insn2, 4, 0)) {
367 // add (immediate)
368 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
369 return true;
370 }
371 return false;
372 }
373
374 class AArch64Decoder : public AllStatic {
375 public:
376
377 static int loadStore(address insn_addr, address &target) {
378 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
379 target = insn_addr + (offset << 2);
380 return 1;
381 }
382 static int unconditionalBranch(address insn_addr, address &target) {
383 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 25, 0);
384 target = insn_addr + (offset << 2);
385 return 1;
386 }
387 static int conditionalBranch(address insn_addr, address &target) {
388 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
389 target = address(((uint64_t)insn_addr + (offset << 2)));
390 return 1;
391 }
392 static int testAndBranch(address insn_addr, address &target) {
393 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 18, 5);
394 target = address(((uint64_t)insn_addr + (offset << 2)));
395 return 1;
396 }
397 static int adr(address insn_addr, address &target) {
398 // PC-rel. addressing
399 uint32_t insn = insn_at(insn_addr, 0);
400 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
401 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
402 target = address((uint64_t)insn_addr + offset);
403 return 1;
404 }
405 template<typename U>
406 static int adrp(address insn_addr, address &target, U inner) {
407 uint32_t insn = insn_at(insn_addr, 0);
408 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
409 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
410 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
411 int shift = 12;
412 offset <<= shift;
413 uint64_t target_page = ((uint64_t)insn_addr) + offset;
414 target_page &= ((uint64_t)-1) << shift;
415 target = address(target_page);
416 precond(inner != nullptr);
417 inner(insn_addr, target);
418 return 2;
419 }
420 static int adrpMem(address insn_addr, address &target) {
421 uint32_t insn2 = insn_at(insn_addr, 1);
422 // Load/store register (unsigned immediate)
423 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
424 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
425 byte_offset <<= size;
426 target += byte_offset;
427 return 2;
428 }
429 static int adrpAdd(address insn_addr, address &target) {
430 uint32_t insn2 = insn_at(insn_addr, 1);
431 // add (immediate)
432 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
433 target += byte_offset;
434 return 2;
435 }
436 static int adrpMovk(address insn_addr, address &target) {
437 uint32_t insn2 = insn_at(insn_addr, 1);
438 uint64_t dest = uint64_t(target);
439 dest = (dest & 0xffff0000ffffffff) |
440 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
441 target = address(dest);
442
443 // We know the destination 4k page. Maybe we have a third
444 // instruction.
445 uint32_t insn = insn_at(insn_addr, 0);
446 uint32_t insn3 = insn_at(insn_addr, 2);
447 ptrdiff_t byte_offset;
448 if (offset_for(insn, insn3, byte_offset)) {
449 target += byte_offset;
450 return 3;
451 } else {
452 return 2;
453 }
454 }
455 static int immediate(address insn_addr, address &target) {
456 uint32_t *insns = (uint32_t *)insn_addr;
457 assert(Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010100, "must be");
458 // Move wide constant: movz, movk, movk. See movptr().
459 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
460 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
461 target = address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5))
462 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
463 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
464 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
465 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
466 return 3;
467 }
468 static void verify(address insn_addr, address &target) {
469 }
470 };
471
472 address MacroAssembler::target_addr_for_insn(address insn_addr) {
473 address target;
474 RelocActions<AArch64Decoder>::run(insn_addr, target);
475 return target;
476 }
477
478 // Patch any kind of instruction; there may be several instructions.
479 // Return the total length (in bytes) of the instructions.
480 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) {
481 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
482 return RelocActions<Patcher>::run(insn_addr, target);
483 }
484
485 int MacroAssembler::patch_oop(address insn_addr, address o) {
486 int instructions;
487 unsigned insn = *(unsigned*)insn_addr;
488 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
489
490 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
491
492 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
493 // narrow OOPs by setting the upper 16 bits in the first
494 // instruction.
495 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
496 // Move narrow OOP
497 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
498 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
499 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
500 instructions = 2;
501 } else {
502 // Move wide OOP
503 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
504 uintptr_t dest = (uintptr_t)o;
505 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
506 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
507 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
508 instructions = 3;
509 }
510 return instructions * NativeInstruction::instruction_size;
511 }
512
513 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
514 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
515 // We encode narrow ones by setting the upper 16 bits in the first
516 // instruction.
517 NativeInstruction *insn = nativeInstruction_at(insn_addr);
518 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
519 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
520
521 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
522
523 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
524 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
525 return 2 * NativeInstruction::instruction_size;
526 }
527
528 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp) {
529 ldr(tmp, Address(rthread, JavaThread::polling_word_offset()));
530 if (at_return) {
531 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
532 // we may safely use the sp instead to perform the stack watermark check.
533 cmp(in_nmethod ? sp : rfp, tmp);
534 br(Assembler::HI, slow_path);
535 } else {
536 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path);
537 }
538 }
539
540 void MacroAssembler::rt_call(address dest, Register tmp) {
541 CodeBlob *cb = CodeCache::find_blob(dest);
542 if (cb) {
543 far_call(RuntimeAddress(dest));
544 } else {
545 lea(tmp, RuntimeAddress(dest));
546 blr(tmp);
547 }
548 }
549
550 void MacroAssembler::push_cont_fastpath(Register java_thread) {
551 if (!Continuations::enabled()) return;
552 Label done;
553 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
554 cmp(sp, rscratch1);
555 br(Assembler::LS, done);
556 mov(rscratch1, sp); // we can't use sp as the source in str
557 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
558 bind(done);
559 }
560
561 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
562 if (!Continuations::enabled()) return;
563 Label done;
564 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
565 cmp(sp, rscratch1);
566 br(Assembler::LO, done);
567 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset()));
568 bind(done);
569 }
570
571 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
572 // we must set sp to zero to clear frame
573 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
574
575 // must clear fp, so that compiled frames are not confused; it is
576 // possible that we need it only for debugging
577 if (clear_fp) {
578 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
579 }
580
581 // Always clear the pc because it could have been set by make_walkable()
582 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
583 }
584
585 // Calls to C land
586 //
587 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
588 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
589 // has to be reset to 0. This is required to allow proper stack traversal.
590 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
591 Register last_java_fp,
592 Register last_java_pc,
593 Register scratch) {
594
595 if (last_java_pc->is_valid()) {
596 str(last_java_pc, Address(rthread,
597 JavaThread::frame_anchor_offset()
598 + JavaFrameAnchor::last_Java_pc_offset()));
599 }
600
601 // determine last_java_sp register
602 if (last_java_sp == sp) {
603 mov(scratch, sp);
604 last_java_sp = scratch;
605 } else if (!last_java_sp->is_valid()) {
606 last_java_sp = esp;
607 }
608
609 // last_java_fp is optional
610 if (last_java_fp->is_valid()) {
611 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
612 }
613
614 // We must set sp last.
615 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
616 }
617
618 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
619 Register last_java_fp,
620 address last_java_pc,
621 Register scratch) {
622 assert(last_java_pc != nullptr, "must provide a valid PC");
623
624 adr(scratch, last_java_pc);
625 str(scratch, Address(rthread,
626 JavaThread::frame_anchor_offset()
627 + JavaFrameAnchor::last_Java_pc_offset()));
628
629 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
630 }
631
632 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
633 Register last_java_fp,
634 Label &L,
635 Register scratch) {
636 if (L.is_bound()) {
637 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
638 } else {
639 InstructionMark im(this);
640 L.add_patch_at(code(), locator());
641 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch);
642 }
643 }
644
645 static inline bool target_needs_far_branch(address addr) {
646 if (AOTCodeCache::is_on_for_dump()) {
647 return true;
648 }
649 // codecache size <= 128M
650 if (!MacroAssembler::far_branches()) {
651 return false;
652 }
653 // codecache size > 240M
654 if (MacroAssembler::codestub_branch_needs_far_jump()) {
655 return true;
656 }
657 // codecache size: 128M..240M
658 return !CodeCache::is_non_nmethod(addr);
659 }
660
661 void MacroAssembler::far_call(Address entry, Register tmp) {
662 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
663 assert(CodeCache::find_blob(entry.target()) != nullptr,
664 "destination of far call not found in code cache");
665 assert(entry.rspec().type() == relocInfo::external_word_type
666 || entry.rspec().type() == relocInfo::runtime_call_type
667 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
668 if (target_needs_far_branch(entry.target())) {
669 uint64_t offset;
670 // We can use ADRP here because we know that the total size of
671 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
672 adrp(tmp, entry, offset);
673 add(tmp, tmp, offset);
674 blr(tmp);
675 } else {
676 bl(entry);
677 }
678 }
679
680 int MacroAssembler::far_jump(Address entry, Register tmp) {
681 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
682 assert(CodeCache::find_blob(entry.target()) != nullptr,
683 "destination of far call not found in code cache");
684 assert(entry.rspec().type() == relocInfo::external_word_type
685 || entry.rspec().type() == relocInfo::runtime_call_type
686 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
687 address start = pc();
688 if (target_needs_far_branch(entry.target())) {
689 uint64_t offset;
690 // We can use ADRP here because we know that the total size of
691 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
692 adrp(tmp, entry, offset);
693 add(tmp, tmp, offset);
694 br(tmp);
695 } else {
696 b(entry);
697 }
698 return pc() - start;
699 }
700
701 void MacroAssembler::reserved_stack_check() {
702 // testing if reserved zone needs to be enabled
703 Label no_reserved_zone_enabling;
704
705 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
706 cmp(sp, rscratch1);
707 br(Assembler::LO, no_reserved_zone_enabling);
708
709 enter(); // LR and FP are live.
710 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)));
711 mov(c_rarg0, rthread);
712 blr(rscratch1);
713 leave();
714
715 // We have already removed our own frame.
716 // throw_delayed_StackOverflowError will think that it's been
717 // called by our caller.
718 lea(rscratch1, RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
719 br(rscratch1);
720 should_not_reach_here();
721
722 bind(no_reserved_zone_enabling);
723 }
724
725 static void pass_arg0(MacroAssembler* masm, Register arg) {
726 if (c_rarg0 != arg ) {
727 masm->mov(c_rarg0, arg);
728 }
729 }
730
731 static void pass_arg1(MacroAssembler* masm, Register arg) {
732 if (c_rarg1 != arg ) {
733 masm->mov(c_rarg1, arg);
734 }
735 }
736
737 static void pass_arg2(MacroAssembler* masm, Register arg) {
738 if (c_rarg2 != arg ) {
739 masm->mov(c_rarg2, arg);
740 }
741 }
742
743 static void pass_arg3(MacroAssembler* masm, Register arg) {
744 if (c_rarg3 != arg ) {
745 masm->mov(c_rarg3, arg);
746 }
747 }
748
749 void MacroAssembler::call_VM_base(Register oop_result,
750 Register java_thread,
751 Register last_java_sp,
752 Label* return_pc,
753 address entry_point,
754 int number_of_arguments,
755 bool check_exceptions) {
756 // determine java_thread register
757 if (!java_thread->is_valid()) {
758 java_thread = rthread;
759 }
760
761 // determine last_java_sp register
762 if (!last_java_sp->is_valid()) {
763 last_java_sp = esp;
764 }
765
766 // debugging support
767 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
768 assert(java_thread == rthread, "unexpected register");
769 #ifdef ASSERT
770 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
771 // if (!TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
772 #endif // ASSERT
773
774 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
775 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
776
777 // push java thread (becomes first argument of C function)
778
779 mov(c_rarg0, java_thread);
780
781 // set last Java frame before call
782 assert(last_java_sp != rfp, "can't use rfp");
783
784 Label l;
785 set_last_Java_frame(last_java_sp, rfp, return_pc != nullptr ? *return_pc : l, rscratch1);
786
787 // do the call, remove parameters
788 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
789
790 // lr could be poisoned with PAC signature during throw_pending_exception
791 // if it was tail-call optimized by compiler, since lr is not callee-saved
792 // reload it with proper value
793 adr(lr, l);
794
795 // reset last Java frame
796 // Only interpreter should have to clear fp
797 reset_last_Java_frame(true);
798
799 // C++ interp handles this in the interpreter
800 check_and_handle_popframe(java_thread);
801 check_and_handle_earlyret(java_thread);
802
803 if (check_exceptions) {
804 // check for pending exceptions (java_thread is set upon return)
805 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
806 Label ok;
807 cbz(rscratch1, ok);
808 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
809 br(rscratch1);
810 bind(ok);
811 }
812
813 // get oop result if there is one and reset the value in the thread
814 if (oop_result->is_valid()) {
815 get_vm_result_oop(oop_result, java_thread);
816 }
817 }
818
819 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
820 call_VM_base(oop_result, noreg, noreg, nullptr, entry_point, number_of_arguments, check_exceptions);
821 }
822
823 // Check the entry target is always reachable from any branch.
824 static bool is_always_within_branch_range(Address entry) {
825 if (AOTCodeCache::is_on_for_dump()) {
826 return false;
827 }
828 const address target = entry.target();
829
830 if (!CodeCache::contains(target)) {
831 // We always use trampolines for callees outside CodeCache.
832 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target");
833 return false;
834 }
835
836 if (!MacroAssembler::far_branches()) {
837 return true;
838 }
839
840 if (entry.rspec().type() == relocInfo::runtime_call_type) {
841 // Runtime calls are calls of a non-compiled method (stubs, adapters).
842 // Non-compiled methods stay forever in CodeCache.
843 // We check whether the longest possible branch is within the branch range.
844 assert(CodeCache::find_blob(target) != nullptr &&
845 !CodeCache::find_blob(target)->is_nmethod(),
846 "runtime call of compiled method");
847 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size;
848 const address left_longest_branch_start = CodeCache::low_bound();
849 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) &&
850 Assembler::reachable_from_branch_at(right_longest_branch_start, target);
851 return is_reachable;
852 }
853
854 return false;
855 }
856
857 // Maybe emit a call via a trampoline. If the code cache is small
858 // trampolines won't be emitted.
859 address MacroAssembler::trampoline_call(Address entry) {
860 assert(entry.rspec().type() == relocInfo::runtime_call_type
861 || entry.rspec().type() == relocInfo::opt_virtual_call_type
862 || entry.rspec().type() == relocInfo::static_call_type
863 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
864
865 address target = entry.target();
866
867 if (!is_always_within_branch_range(entry)) {
868 if (!in_scratch_emit_size()) {
869 // We don't want to emit a trampoline if C2 is generating dummy
870 // code during its branch shortening phase.
871 if (entry.rspec().type() == relocInfo::runtime_call_type) {
872 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs");
873 code()->share_trampoline_for(entry.target(), offset());
874 } else {
875 address stub = emit_trampoline_stub(offset(), target);
876 if (stub == nullptr) {
877 postcond(pc() == badAddress);
878 return nullptr; // CodeCache is full
879 }
880 }
881 }
882 target = pc();
883 }
884
885 address call_pc = pc();
886 relocate(entry.rspec());
887 bl(target);
888
889 postcond(pc() != badAddress);
890 return call_pc;
891 }
892
893 // Emit a trampoline stub for a call to a target which is too far away.
894 //
895 // code sequences:
896 //
897 // call-site:
898 // branch-and-link to <destination> or <trampoline stub>
899 //
900 // Related trampoline stub for this call site in the stub section:
901 // load the call target from the constant pool
902 // branch (LR still points to the call site above)
903
904 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
905 address dest) {
906 // Max stub size: alignment nop, TrampolineStub.
907 address stub = start_a_stub(max_trampoline_stub_size());
908 if (stub == nullptr) {
909 return nullptr; // CodeBuffer::expand failed
910 }
911
912 // Create a trampoline stub relocation which relates this trampoline stub
913 // with the call instruction at insts_call_instruction_offset in the
914 // instructions code-section.
915 align(wordSize);
916 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
917 + insts_call_instruction_offset));
918 const int stub_start_offset = offset();
919
920 // Now, create the trampoline stub's code:
921 // - load the call
922 // - call
923 Label target;
924 ldr(rscratch1, target);
925 br(rscratch1);
926 bind(target);
927 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
928 "should be");
929 emit_int64((int64_t)dest);
930
931 const address stub_start_addr = addr_at(stub_start_offset);
932
933 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
934
935 end_a_stub();
936 return stub_start_addr;
937 }
938
939 int MacroAssembler::max_trampoline_stub_size() {
940 // Max stub size: alignment nop, TrampolineStub.
941 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size;
942 }
943
944 void MacroAssembler::emit_static_call_stub() {
945 // CompiledDirectCall::set_to_interpreted knows the
946 // exact layout of this stub.
947
948 isb();
949 mov_metadata(rmethod, nullptr);
950
951 // Jump to the entry point of the c2i stub.
952 if (codestub_branch_needs_far_jump()) {
953 movptr(rscratch1, 0);
954 br(rscratch1);
955 } else {
956 b(pc());
957 }
958 }
959
960 int MacroAssembler::static_call_stub_size() {
961 if (!codestub_branch_needs_far_jump()) {
962 // isb; movk; movz; movz; b
963 return 5 * NativeInstruction::instruction_size;
964 }
965 // isb; movk; movz; movz; movk; movz; movz; br
966 return 8 * NativeInstruction::instruction_size;
967 }
968
969 void MacroAssembler::c2bool(Register x) {
970 // implements x == 0 ? 0 : 1
971 // note: must only look at least-significant byte of x
972 // since C-style booleans are stored in one byte
973 // only! (was bug)
974 tst(x, 0xff);
975 cset(x, Assembler::NE);
976 }
977
978 address MacroAssembler::ic_call(address entry, jint method_index) {
979 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
980 movptr(rscratch2, (intptr_t)Universe::non_oop_word());
981 return trampoline_call(Address(entry, rh));
982 }
983
984 int MacroAssembler::ic_check_size() {
985 int extra_instructions = UseCompactObjectHeaders ? 1 : 0;
986 if (target_needs_far_branch(CAST_FROM_FN_PTR(address, SharedRuntime::get_ic_miss_stub()))) {
987 return NativeInstruction::instruction_size * (7 + extra_instructions);
988 } else {
989 return NativeInstruction::instruction_size * (5 + extra_instructions);
990 }
991 }
992
993 int MacroAssembler::ic_check(int end_alignment) {
994 Register receiver = j_rarg0;
995 Register data = rscratch2;
996 Register tmp1 = rscratch1;
997 Register tmp2 = r10;
998
999 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1000 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1001 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1002 // before the inline cache check here, and not after
1003 align(end_alignment, offset() + ic_check_size());
1004
1005 int uep_offset = offset();
1006
1007 if (UseCompactObjectHeaders) {
1008 load_narrow_klass_compact(tmp1, receiver);
1009 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1010 cmpw(tmp1, tmp2);
1011 } else {
1012 ldrw(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1013 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1014 cmpw(tmp1, tmp2);
1015 }
1016
1017 Label dont;
1018 br(Assembler::EQ, dont);
1019 far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1020 bind(dont);
1021 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1022
1023 return uep_offset;
1024 }
1025
1026 // Implementation of call_VM versions
1027
1028 void MacroAssembler::call_VM(Register oop_result,
1029 address entry_point,
1030 bool check_exceptions) {
1031 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1032 }
1033
1034 void MacroAssembler::call_VM(Register oop_result,
1035 address entry_point,
1036 Register arg_1,
1037 bool check_exceptions) {
1038 pass_arg1(this, arg_1);
1039 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1040 }
1041
1042 void MacroAssembler::call_VM(Register oop_result,
1043 address entry_point,
1044 Register arg_1,
1045 Register arg_2,
1046 bool check_exceptions) {
1047 assert_different_registers(arg_1, c_rarg2);
1048 pass_arg2(this, arg_2);
1049 pass_arg1(this, arg_1);
1050 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1051 }
1052
1053 void MacroAssembler::call_VM(Register oop_result,
1054 address entry_point,
1055 Register arg_1,
1056 Register arg_2,
1057 Register arg_3,
1058 bool check_exceptions) {
1059 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1060 assert_different_registers(arg_2, c_rarg3);
1061 pass_arg3(this, arg_3);
1062
1063 pass_arg2(this, arg_2);
1064
1065 pass_arg1(this, arg_1);
1066 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1067 }
1068
1069 void MacroAssembler::call_VM(Register oop_result,
1070 Register last_java_sp,
1071 address entry_point,
1072 int number_of_arguments,
1073 bool check_exceptions) {
1074 call_VM_base(oop_result, rthread, last_java_sp, nullptr, entry_point, number_of_arguments, check_exceptions);
1075 }
1076
1077 void MacroAssembler::call_VM(Register oop_result,
1078 Register last_java_sp,
1079 address entry_point,
1080 Register arg_1,
1081 bool check_exceptions) {
1082 pass_arg1(this, arg_1);
1083 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1084 }
1085
1086 void MacroAssembler::call_VM(Register oop_result,
1087 Register last_java_sp,
1088 address entry_point,
1089 Register arg_1,
1090 Register arg_2,
1091 bool check_exceptions) {
1092
1093 assert_different_registers(arg_1, c_rarg2);
1094 pass_arg2(this, arg_2);
1095 pass_arg1(this, arg_1);
1096 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1097 }
1098
1099 void MacroAssembler::call_VM(Register oop_result,
1100 Register last_java_sp,
1101 address entry_point,
1102 Register arg_1,
1103 Register arg_2,
1104 Register arg_3,
1105 bool check_exceptions) {
1106 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1107 assert_different_registers(arg_2, c_rarg3);
1108 pass_arg3(this, arg_3);
1109 pass_arg2(this, arg_2);
1110 pass_arg1(this, arg_1);
1111 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1112 }
1113
1114
1115 void MacroAssembler::get_vm_result_oop(Register oop_result, Register java_thread) {
1116 ldr(oop_result, Address(java_thread, JavaThread::vm_result_oop_offset()));
1117 str(zr, Address(java_thread, JavaThread::vm_result_oop_offset()));
1118 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1119 }
1120
1121 void MacroAssembler::get_vm_result_metadata(Register metadata_result, Register java_thread) {
1122 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1123 str(zr, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1124 }
1125
1126 void MacroAssembler::align(int modulus) {
1127 align(modulus, offset());
1128 }
1129
1130 // Ensure that the code at target bytes offset from the current offset() is aligned
1131 // according to modulus.
1132 void MacroAssembler::align(int modulus, int target) {
1133 int delta = target - offset();
1134 while ((offset() + delta) % modulus != 0) nop();
1135 }
1136
1137 void MacroAssembler::post_call_nop() {
1138 if (!Continuations::enabled()) {
1139 return;
1140 }
1141 InstructionMark im(this);
1142 relocate(post_call_nop_Relocation::spec());
1143 InlineSkippedInstructionsCounter skipCounter(this);
1144 nop();
1145 movk(zr, 0);
1146 movk(zr, 0);
1147 }
1148
1149 // these are no-ops overridden by InterpreterMacroAssembler
1150
1151 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1152
1153 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1154
1155 // Look up the method for a megamorphic invokeinterface call.
1156 // The target method is determined by <intf_klass, itable_index>.
1157 // The receiver klass is in recv_klass.
1158 // On success, the result will be in method_result, and execution falls through.
1159 // On failure, execution transfers to the given label.
1160 void MacroAssembler::lookup_interface_method(Register recv_klass,
1161 Register intf_klass,
1162 RegisterOrConstant itable_index,
1163 Register method_result,
1164 Register scan_temp,
1165 Label& L_no_such_interface,
1166 bool return_method) {
1167 assert_different_registers(recv_klass, intf_klass, scan_temp);
1168 assert_different_registers(method_result, intf_klass, scan_temp);
1169 assert(recv_klass != method_result || !return_method,
1170 "recv_klass can be destroyed when method isn't needed");
1171 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1172 "caller must use same register for non-constant itable index as for method");
1173
1174 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1175 int vtable_base = in_bytes(Klass::vtable_start_offset());
1176 int itentry_off = in_bytes(itableMethodEntry::method_offset());
1177 int scan_step = itableOffsetEntry::size() * wordSize;
1178 int vte_size = vtableEntry::size_in_bytes();
1179 assert(vte_size == wordSize, "else adjust times_vte_scale");
1180
1181 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1182
1183 // Could store the aligned, prescaled offset in the klass.
1184 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
1185 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
1186 add(scan_temp, scan_temp, vtable_base);
1187
1188 if (return_method) {
1189 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1190 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1191 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1192 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
1193 if (itentry_off)
1194 add(recv_klass, recv_klass, itentry_off);
1195 }
1196
1197 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
1198 // if (scan->interface() == intf) {
1199 // result = (klass + scan->offset() + itable_index);
1200 // }
1201 // }
1202 Label search, found_method;
1203
1204 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1205 cmp(intf_klass, method_result);
1206 br(Assembler::EQ, found_method);
1207 bind(search);
1208 // Check that the previous entry is non-null. A null entry means that
1209 // the receiver class doesn't implement the interface, and wasn't the
1210 // same as when the caller was compiled.
1211 cbz(method_result, L_no_such_interface);
1212 if (itableOffsetEntry::interface_offset() != 0) {
1213 add(scan_temp, scan_temp, scan_step);
1214 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1215 } else {
1216 ldr(method_result, Address(pre(scan_temp, scan_step)));
1217 }
1218 cmp(intf_klass, method_result);
1219 br(Assembler::NE, search);
1220
1221 bind(found_method);
1222
1223 // Got a hit.
1224 if (return_method) {
1225 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
1226 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1227 }
1228 }
1229
1230 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
1231 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
1232 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
1233 // The target method is determined by <holder_klass, itable_index>.
1234 // The receiver klass is in recv_klass.
1235 // On success, the result will be in method_result, and execution falls through.
1236 // On failure, execution transfers to the given label.
1237 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
1238 Register holder_klass,
1239 Register resolved_klass,
1240 Register method_result,
1241 Register temp_itbl_klass,
1242 Register scan_temp,
1243 int itable_index,
1244 Label& L_no_such_interface) {
1245 // 'method_result' is only used as output register at the very end of this method.
1246 // Until then we can reuse it as 'holder_offset'.
1247 Register holder_offset = method_result;
1248 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset);
1249
1250 int vtable_start_offset = in_bytes(Klass::vtable_start_offset());
1251 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize;
1252 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
1253 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
1254
1255 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found;
1256
1257 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1258 add(recv_klass, recv_klass, vtable_start_offset + ioffset);
1259 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len;
1260 // temp_itbl_klass = itable[0]._interface;
1261 int vtblEntrySize = vtableEntry::size_in_bytes();
1262 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3");
1263 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1264 mov(holder_offset, zr);
1265 // scan_temp = &(itable[0]._interface)
1266 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1267
1268 // Initial checks:
1269 // - if (holder_klass != resolved_klass), go to "scan for resolved"
1270 // - if (itable[0] == holder_klass), shortcut to "holder found"
1271 // - if (itable[0] == 0), no such interface
1272 cmp(resolved_klass, holder_klass);
1273 br(Assembler::NE, L_loop_search_resolved_entry);
1274 cmp(holder_klass, temp_itbl_klass);
1275 br(Assembler::EQ, L_holder_found);
1276 cbz(temp_itbl_klass, L_no_such_interface);
1277
1278 // Loop: Look for holder_klass record in itable
1279 // do {
1280 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1281 // if (temp_itbl_klass == holder_klass) {
1282 // goto L_holder_found; // Found!
1283 // }
1284 // } while (temp_itbl_klass != 0);
1285 // goto L_no_such_interface // Not found.
1286 Label L_search_holder;
1287 bind(L_search_holder);
1288 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1289 cmp(holder_klass, temp_itbl_klass);
1290 br(Assembler::EQ, L_holder_found);
1291 cbnz(temp_itbl_klass, L_search_holder);
1292
1293 b(L_no_such_interface);
1294
1295 // Loop: Look for resolved_class record in itable
1296 // while (true) {
1297 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1298 // if (temp_itbl_klass == 0) {
1299 // goto L_no_such_interface;
1300 // }
1301 // if (temp_itbl_klass == resolved_klass) {
1302 // goto L_resolved_found; // Found!
1303 // }
1304 // if (temp_itbl_klass == holder_klass) {
1305 // holder_offset = scan_temp;
1306 // }
1307 // }
1308 //
1309 Label L_loop_search_resolved;
1310 bind(L_loop_search_resolved);
1311 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1312 bind(L_loop_search_resolved_entry);
1313 cbz(temp_itbl_klass, L_no_such_interface);
1314 cmp(resolved_klass, temp_itbl_klass);
1315 br(Assembler::EQ, L_resolved_found);
1316 cmp(holder_klass, temp_itbl_klass);
1317 br(Assembler::NE, L_loop_search_resolved);
1318 mov(holder_offset, scan_temp);
1319 b(L_loop_search_resolved);
1320
1321 // See if we already have a holder klass. If not, go and scan for it.
1322 bind(L_resolved_found);
1323 cbz(holder_offset, L_search_holder);
1324 mov(scan_temp, holder_offset);
1325
1326 // Finally, scan_temp contains holder_klass vtable offset
1327 bind(L_holder_found);
1328 ldrw(method_result, Address(scan_temp, ooffset - ioffset));
1329 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset())
1330 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass
1331 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0)));
1332 }
1333
1334 // virtual method calling
1335 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1336 RegisterOrConstant vtable_index,
1337 Register method_result) {
1338 assert(vtableEntry::size() * wordSize == 8,
1339 "adjust the scaling in the code below");
1340 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset());
1341
1342 if (vtable_index.is_register()) {
1343 lea(method_result, Address(recv_klass,
1344 vtable_index.as_register(),
1345 Address::lsl(LogBytesPerWord)));
1346 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1347 } else {
1348 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1349 ldr(method_result,
1350 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1351 }
1352 }
1353
1354 void MacroAssembler::check_klass_subtype(Register sub_klass,
1355 Register super_klass,
1356 Register temp_reg,
1357 Label& L_success) {
1358 Label L_failure;
1359 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
1360 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
1361 bind(L_failure);
1362 }
1363
1364
1365 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1366 Register super_klass,
1367 Register temp_reg,
1368 Label* L_success,
1369 Label* L_failure,
1370 Label* L_slow_path,
1371 Register super_check_offset) {
1372 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset);
1373 bool must_load_sco = ! super_check_offset->is_valid();
1374 if (must_load_sco) {
1375 assert(temp_reg != noreg, "supply either a temp or a register offset");
1376 }
1377
1378 Label L_fallthrough;
1379 int label_nulls = 0;
1380 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1381 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1382 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
1383 assert(label_nulls <= 1, "at most one null in the batch");
1384
1385 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1386 Address super_check_offset_addr(super_klass, sco_offset);
1387
1388 // Hacked jmp, which may only be used just before L_fallthrough.
1389 #define final_jmp(label) \
1390 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1391 else b(label) /*omit semi*/
1392
1393 // If the pointers are equal, we are done (e.g., String[] elements).
1394 // This self-check enables sharing of secondary supertype arrays among
1395 // non-primary types such as array-of-interface. Otherwise, each such
1396 // type would need its own customized SSA.
1397 // We move this check to the front of the fast path because many
1398 // type checks are in fact trivially successful in this manner,
1399 // so we get a nicely predicted branch right at the start of the check.
1400 cmp(sub_klass, super_klass);
1401 br(Assembler::EQ, *L_success);
1402
1403 // Check the supertype display:
1404 if (must_load_sco) {
1405 ldrw(temp_reg, super_check_offset_addr);
1406 super_check_offset = temp_reg;
1407 }
1408
1409 Address super_check_addr(sub_klass, super_check_offset);
1410 ldr(rscratch1, super_check_addr);
1411 cmp(super_klass, rscratch1); // load displayed supertype
1412 br(Assembler::EQ, *L_success);
1413
1414 // This check has worked decisively for primary supers.
1415 // Secondary supers are sought in the super_cache ('super_cache_addr').
1416 // (Secondary supers are interfaces and very deeply nested subtypes.)
1417 // This works in the same check above because of a tricky aliasing
1418 // between the super_cache and the primary super display elements.
1419 // (The 'super_check_addr' can address either, as the case requires.)
1420 // Note that the cache is updated below if it does not help us find
1421 // what we need immediately.
1422 // So if it was a primary super, we can just fail immediately.
1423 // Otherwise, it's the slow path for us (no success at this point).
1424
1425 sub(rscratch1, super_check_offset, in_bytes(Klass::secondary_super_cache_offset()));
1426 if (L_failure == &L_fallthrough) {
1427 cbz(rscratch1, *L_slow_path);
1428 } else {
1429 cbnz(rscratch1, *L_failure);
1430 final_jmp(*L_slow_path);
1431 }
1432
1433 bind(L_fallthrough);
1434
1435 #undef final_jmp
1436 }
1437
1438 // These two are taken from x86, but they look generally useful
1439
1440 // scans count pointer sized words at [addr] for occurrence of value,
1441 // generic
1442 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1443 Register scratch) {
1444 Label Lloop, Lexit;
1445 cbz(count, Lexit);
1446 bind(Lloop);
1447 ldr(scratch, post(addr, wordSize));
1448 cmp(value, scratch);
1449 br(EQ, Lexit);
1450 sub(count, count, 1);
1451 cbnz(count, Lloop);
1452 bind(Lexit);
1453 }
1454
1455 // scans count 4 byte words at [addr] for occurrence of value,
1456 // generic
1457 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1458 Register scratch) {
1459 Label Lloop, Lexit;
1460 cbz(count, Lexit);
1461 bind(Lloop);
1462 ldrw(scratch, post(addr, wordSize));
1463 cmpw(value, scratch);
1464 br(EQ, Lexit);
1465 sub(count, count, 1);
1466 cbnz(count, Lloop);
1467 bind(Lexit);
1468 }
1469
1470 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
1471 Register super_klass,
1472 Register temp_reg,
1473 Register temp2_reg,
1474 Label* L_success,
1475 Label* L_failure,
1476 bool set_cond_codes) {
1477 // NB! Callers may assume that, when temp2_reg is a valid register,
1478 // this code sets it to a nonzero value.
1479
1480 assert_different_registers(sub_klass, super_klass, temp_reg);
1481 if (temp2_reg != noreg)
1482 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1483 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1484
1485 Label L_fallthrough;
1486 int label_nulls = 0;
1487 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1488 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1489 assert(label_nulls <= 1, "at most one null in the batch");
1490
1491 // a couple of useful fields in sub_klass:
1492 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1493 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1494 Address secondary_supers_addr(sub_klass, ss_offset);
1495 Address super_cache_addr( sub_klass, sc_offset);
1496
1497 BLOCK_COMMENT("check_klass_subtype_slow_path");
1498
1499 // Do a linear scan of the secondary super-klass chain.
1500 // This code is rarely used, so simplicity is a virtue here.
1501 // The repne_scan instruction uses fixed registers, which we must spill.
1502 // Don't worry too much about pre-existing connections with the input regs.
1503
1504 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1505 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1506
1507 RegSet pushed_registers;
1508 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1509 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1510
1511 if (super_klass != r0) {
1512 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1513 }
1514
1515 push(pushed_registers, sp);
1516
1517 // Get super_klass value into r0 (even if it was in r5 or r2).
1518 if (super_klass != r0) {
1519 mov(r0, super_klass);
1520 }
1521
1522 #ifndef PRODUCT
1523 incrementw(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1524 #endif //PRODUCT
1525
1526 // We will consult the secondary-super array.
1527 ldr(r5, secondary_supers_addr);
1528 // Load the array length.
1529 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1530 // Skip to start of data.
1531 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1532
1533 cmp(sp, zr); // Clear Z flag; SP is never zero
1534 // Scan R2 words at [R5] for an occurrence of R0.
1535 // Set NZ/Z based on last compare.
1536 repne_scan(r5, r0, r2, rscratch1);
1537
1538 // Unspill the temp. registers:
1539 pop(pushed_registers, sp);
1540
1541 br(Assembler::NE, *L_failure);
1542
1543 // Success. Cache the super we found and proceed in triumph.
1544
1545 if (UseSecondarySupersCache) {
1546 str(super_klass, super_cache_addr);
1547 }
1548
1549 if (L_success != &L_fallthrough) {
1550 b(*L_success);
1551 }
1552
1553 #undef IS_A_TEMP
1554
1555 bind(L_fallthrough);
1556 }
1557
1558 // If Register r is invalid, remove a new register from
1559 // available_regs, and add new register to regs_to_push.
1560 Register MacroAssembler::allocate_if_noreg(Register r,
1561 RegSetIterator<Register> &available_regs,
1562 RegSet ®s_to_push) {
1563 if (!r->is_valid()) {
1564 r = *available_regs++;
1565 regs_to_push += r;
1566 }
1567 return r;
1568 }
1569
1570 // check_klass_subtype_slow_path_table() looks for super_klass in the
1571 // hash table belonging to super_klass, branching to L_success or
1572 // L_failure as appropriate. This is essentially a shim which
1573 // allocates registers as necessary then calls
1574 // lookup_secondary_supers_table() to do the work. Any of the temp
1575 // regs may be noreg, in which case this logic will chooses some
1576 // registers push and pop them from the stack.
1577 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
1578 Register super_klass,
1579 Register temp_reg,
1580 Register temp2_reg,
1581 Register temp3_reg,
1582 Register result_reg,
1583 FloatRegister vtemp,
1584 Label* L_success,
1585 Label* L_failure,
1586 bool set_cond_codes) {
1587 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
1588
1589 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1590
1591 Label L_fallthrough;
1592 int label_nulls = 0;
1593 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1594 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1595 assert(label_nulls <= 1, "at most one null in the batch");
1596
1597 BLOCK_COMMENT("check_klass_subtype_slow_path");
1598
1599 RegSetIterator<Register> available_regs
1600 = (RegSet::range(r0, r15) - temps - sub_klass - super_klass).begin();
1601
1602 RegSet pushed_regs;
1603
1604 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
1605 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
1606 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
1607 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
1608
1609 push(pushed_regs, sp);
1610
1611 lookup_secondary_supers_table_var(sub_klass,
1612 super_klass,
1613 temp_reg, temp2_reg, temp3_reg, vtemp, result_reg,
1614 nullptr);
1615 cmp(result_reg, zr);
1616
1617 // Unspill the temp. registers:
1618 pop(pushed_regs, sp);
1619
1620 // NB! Callers may assume that, when set_cond_codes is true, this
1621 // code sets temp2_reg to a nonzero value.
1622 if (set_cond_codes) {
1623 mov(temp2_reg, 1);
1624 }
1625
1626 br(Assembler::NE, *L_failure);
1627
1628 if (L_success != &L_fallthrough) {
1629 b(*L_success);
1630 }
1631
1632 bind(L_fallthrough);
1633 }
1634
1635 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1636 Register super_klass,
1637 Register temp_reg,
1638 Register temp2_reg,
1639 Label* L_success,
1640 Label* L_failure,
1641 bool set_cond_codes) {
1642 if (UseSecondarySupersTable) {
1643 check_klass_subtype_slow_path_table
1644 (sub_klass, super_klass, temp_reg, temp2_reg, /*temp3*/noreg, /*result*/noreg,
1645 /*vtemp*/fnoreg,
1646 L_success, L_failure, set_cond_codes);
1647 } else {
1648 check_klass_subtype_slow_path_linear
1649 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
1650 }
1651 }
1652
1653
1654 // Ensure that the inline code and the stub are using the same registers.
1655 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
1656 do { \
1657 assert(r_super_klass == r0 && \
1658 r_array_base == r1 && \
1659 r_array_length == r2 && \
1660 (r_array_index == r3 || r_array_index == noreg) && \
1661 (r_sub_klass == r4 || r_sub_klass == noreg) && \
1662 (r_bitmap == rscratch2 || r_bitmap == noreg) && \
1663 (result == r5 || result == noreg), "registers must match aarch64.ad"); \
1664 } while(0)
1665
1666 bool MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
1667 Register r_super_klass,
1668 Register temp1,
1669 Register temp2,
1670 Register temp3,
1671 FloatRegister vtemp,
1672 Register result,
1673 u1 super_klass_slot,
1674 bool stub_is_near) {
1675 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1676
1677 Label L_fallthrough;
1678
1679 BLOCK_COMMENT("lookup_secondary_supers_table {");
1680
1681 const Register
1682 r_array_base = temp1, // r1
1683 r_array_length = temp2, // r2
1684 r_array_index = temp3, // r3
1685 r_bitmap = rscratch2;
1686
1687 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1688
1689 u1 bit = super_klass_slot;
1690
1691 // Make sure that result is nonzero if the TBZ below misses.
1692 mov(result, 1);
1693
1694 // We're going to need the bitmap in a vector reg and in a core reg,
1695 // so load both now.
1696 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1697 if (bit != 0) {
1698 ldrd(vtemp, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1699 }
1700 // First check the bitmap to see if super_klass might be present. If
1701 // the bit is zero, we are certain that super_klass is not one of
1702 // the secondary supers.
1703 tbz(r_bitmap, bit, L_fallthrough);
1704
1705 // Get the first array index that can contain super_klass into r_array_index.
1706 if (bit != 0) {
1707 shld(vtemp, vtemp, Klass::SECONDARY_SUPERS_TABLE_MASK - bit);
1708 cnt(vtemp, T8B, vtemp);
1709 addv(vtemp, T8B, vtemp);
1710 fmovd(r_array_index, vtemp);
1711 } else {
1712 mov(r_array_index, (u1)1);
1713 }
1714 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1715
1716 // We will consult the secondary-super array.
1717 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1718
1719 // The value i in r_array_index is >= 1, so even though r_array_base
1720 // points to the length, we don't need to adjust it to point to the
1721 // data.
1722 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1723 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1724
1725 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1726 eor(result, result, r_super_klass);
1727 cbz(result, L_fallthrough); // Found a match
1728
1729 // Is there another entry to check? Consult the bitmap.
1730 tbz(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK, L_fallthrough);
1731
1732 // Linear probe.
1733 if (bit != 0) {
1734 ror(r_bitmap, r_bitmap, bit);
1735 }
1736
1737 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1738 // The next slot to be inspected, by the stub we're about to call,
1739 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1740 // have been checked.
1741 Address stub = RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub());
1742 if (stub_is_near) {
1743 bl(stub);
1744 } else {
1745 address call = trampoline_call(stub);
1746 if (call == nullptr) {
1747 return false; // trampoline allocation failed
1748 }
1749 }
1750
1751 BLOCK_COMMENT("} lookup_secondary_supers_table");
1752
1753 bind(L_fallthrough);
1754
1755 if (VerifySecondarySupers) {
1756 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1757 temp1, temp2, result); // r1, r2, r5
1758 }
1759 return true;
1760 }
1761
1762 // At runtime, return 0 in result if r_super_klass is a superclass of
1763 // r_sub_klass, otherwise return nonzero. Use this version of
1764 // lookup_secondary_supers_table() if you don't know ahead of time
1765 // which superclass will be searched for. Used by interpreter and
1766 // runtime stubs. It is larger and has somewhat greater latency than
1767 // the version above, which takes a constant super_klass_slot.
1768 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
1769 Register r_super_klass,
1770 Register temp1,
1771 Register temp2,
1772 Register temp3,
1773 FloatRegister vtemp,
1774 Register result,
1775 Label *L_success) {
1776 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1777
1778 Label L_fallthrough;
1779
1780 BLOCK_COMMENT("lookup_secondary_supers_table {");
1781
1782 const Register
1783 r_array_index = temp3,
1784 slot = rscratch1,
1785 r_bitmap = rscratch2;
1786
1787 ldrb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
1788
1789 // Make sure that result is nonzero if the test below misses.
1790 mov(result, 1);
1791
1792 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1793
1794 // First check the bitmap to see if super_klass might be present. If
1795 // the bit is zero, we are certain that super_klass is not one of
1796 // the secondary supers.
1797
1798 // This next instruction is equivalent to:
1799 // mov(tmp_reg, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1800 // sub(temp2, tmp_reg, slot);
1801 eor(temp2, slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1802 lslv(temp2, r_bitmap, temp2);
1803 tbz(temp2, Klass::SECONDARY_SUPERS_TABLE_SIZE - 1, L_fallthrough);
1804
1805 bool must_save_v0 = (vtemp == fnoreg);
1806 if (must_save_v0) {
1807 // temp1 and result are free, so use them to preserve vtemp
1808 vtemp = v0;
1809 mov(temp1, vtemp, D, 0);
1810 mov(result, vtemp, D, 1);
1811 }
1812
1813 // Get the first array index that can contain super_klass into r_array_index.
1814 mov(vtemp, D, 0, temp2);
1815 cnt(vtemp, T8B, vtemp);
1816 addv(vtemp, T8B, vtemp);
1817 mov(r_array_index, vtemp, D, 0);
1818
1819 if (must_save_v0) {
1820 mov(vtemp, D, 0, temp1 );
1821 mov(vtemp, D, 1, result);
1822 }
1823
1824 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1825
1826 const Register
1827 r_array_base = temp1,
1828 r_array_length = temp2;
1829
1830 // The value i in r_array_index is >= 1, so even though r_array_base
1831 // points to the length, we don't need to adjust it to point to the
1832 // data.
1833 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1834 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1835
1836 // We will consult the secondary-super array.
1837 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1838
1839 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1840 eor(result, result, r_super_klass);
1841 cbz(result, L_success ? *L_success : L_fallthrough); // Found a match
1842
1843 // Is there another entry to check? Consult the bitmap.
1844 rorv(r_bitmap, r_bitmap, slot);
1845 // rol(r_bitmap, r_bitmap, 1);
1846 tbz(r_bitmap, 1, L_fallthrough);
1847
1848 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1849 // The next slot to be inspected, by the logic we're about to call,
1850 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1851 // have been checked.
1852 lookup_secondary_supers_table_slow_path(r_super_klass, r_array_base, r_array_index,
1853 r_bitmap, r_array_length, result, /*is_stub*/false);
1854
1855 BLOCK_COMMENT("} lookup_secondary_supers_table");
1856
1857 bind(L_fallthrough);
1858
1859 if (VerifySecondarySupers) {
1860 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1861 temp1, temp2, result); // r1, r2, r5
1862 }
1863
1864 if (L_success) {
1865 cbz(result, *L_success);
1866 }
1867 }
1868
1869 // Called by code generated by check_klass_subtype_slow_path
1870 // above. This is called when there is a collision in the hashed
1871 // lookup in the secondary supers array.
1872 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
1873 Register r_array_base,
1874 Register r_array_index,
1875 Register r_bitmap,
1876 Register temp1,
1877 Register result,
1878 bool is_stub) {
1879 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, result, rscratch1);
1880
1881 const Register
1882 r_array_length = temp1,
1883 r_sub_klass = noreg; // unused
1884
1885 if (is_stub) {
1886 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1887 }
1888
1889 Label L_fallthrough, L_huge;
1890
1891 // Load the array length.
1892 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1893 // And adjust the array base to point to the data.
1894 // NB! Effectively increments current slot index by 1.
1895 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
1896 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1897
1898 // The bitmap is full to bursting.
1899 // Implicit invariant: BITMAP_FULL implies (length > 0)
1900 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
1901 cmpw(r_array_length, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 2));
1902 br(GT, L_huge);
1903
1904 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
1905 // current slot (at secondary_supers[r_array_index]) has not yet
1906 // been inspected, and r_array_index may be out of bounds if we
1907 // wrapped around the end of the array.
1908
1909 { // This is conventional linear probing, but instead of terminating
1910 // when a null entry is found in the table, we maintain a bitmap
1911 // in which a 0 indicates missing entries.
1912 // As long as the bitmap is not completely full,
1913 // array_length == popcount(bitmap). The array_length check above
1914 // guarantees there are 0s in the bitmap, so the loop eventually
1915 // terminates.
1916 Label L_loop;
1917 bind(L_loop);
1918
1919 // Check for wraparound.
1920 cmp(r_array_index, r_array_length);
1921 csel(r_array_index, zr, r_array_index, GE);
1922
1923 ldr(rscratch1, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1924 eor(result, rscratch1, r_super_klass);
1925 cbz(result, L_fallthrough);
1926
1927 tbz(r_bitmap, 2, L_fallthrough); // look-ahead check (Bit 2); result is non-zero
1928
1929 ror(r_bitmap, r_bitmap, 1);
1930 add(r_array_index, r_array_index, 1);
1931 b(L_loop);
1932 }
1933
1934 { // Degenerate case: more than 64 secondary supers.
1935 // FIXME: We could do something smarter here, maybe a vectorized
1936 // comparison or a binary search, but is that worth any added
1937 // complexity?
1938 bind(L_huge);
1939 cmp(sp, zr); // Clear Z flag; SP is never zero
1940 repne_scan(r_array_base, r_super_klass, r_array_length, rscratch1);
1941 cset(result, NE); // result == 0 iff we got a match.
1942 }
1943
1944 bind(L_fallthrough);
1945 }
1946
1947 // Make sure that the hashed lookup and a linear scan agree.
1948 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
1949 Register r_super_klass,
1950 Register temp1,
1951 Register temp2,
1952 Register result) {
1953 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, result, rscratch1);
1954
1955 const Register
1956 r_array_base = temp1,
1957 r_array_length = temp2;
1958
1959 BLOCK_COMMENT("verify_secondary_supers_table {");
1960
1961 // We will consult the secondary-super array.
1962 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1963
1964 // Load the array length.
1965 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1966 // And adjust the array base to point to the data.
1967 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1968
1969 cmp(sp, zr); // Clear Z flag; SP is never zero
1970 // Scan R2 words at [R5] for an occurrence of R0.
1971 // Set NZ/Z based on last compare.
1972 repne_scan(/*addr*/r_array_base, /*value*/r_super_klass, /*count*/r_array_length, rscratch2);
1973 // rscratch1 == 0 iff we got a match.
1974 cset(rscratch1, NE);
1975
1976 Label passed;
1977 cmp(result, zr);
1978 cset(result, NE); // normalize result to 0/1 for comparison
1979
1980 cmp(rscratch1, result);
1981 br(EQ, passed);
1982 {
1983 mov(r0, r_super_klass); // r0 <- r0
1984 mov(r1, r_sub_klass); // r1 <- r4
1985 mov(r2, /*expected*/rscratch1); // r2 <- r8
1986 mov(r3, result); // r3 <- r5
1987 mov(r4, (address)("mismatch")); // r4 <- const
1988 rt_call(CAST_FROM_FN_PTR(address, Klass::on_secondary_supers_verification_failure), rscratch2);
1989 should_not_reach_here();
1990 }
1991 bind(passed);
1992
1993 BLOCK_COMMENT("} verify_secondary_supers_table");
1994 }
1995
1996 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) {
1997 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
1998 assert_different_registers(klass, rthread, scratch);
1999
2000 Label L_fallthrough, L_tmp;
2001 if (L_fast_path == nullptr) {
2002 L_fast_path = &L_fallthrough;
2003 } else if (L_slow_path == nullptr) {
2004 L_slow_path = &L_fallthrough;
2005 }
2006 // Fast path check: class is fully initialized
2007 lea(scratch, Address(klass, InstanceKlass::init_state_offset()));
2008 ldarb(scratch, scratch);
2009 cmp(scratch, InstanceKlass::fully_initialized);
2010 br(Assembler::EQ, *L_fast_path);
2011
2012 // Fast path check: current thread is initializer thread
2013 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
2014 cmp(rthread, scratch);
2015
2016 if (L_slow_path == &L_fallthrough) {
2017 br(Assembler::EQ, *L_fast_path);
2018 bind(*L_slow_path);
2019 } else if (L_fast_path == &L_fallthrough) {
2020 br(Assembler::NE, *L_slow_path);
2021 bind(*L_fast_path);
2022 } else {
2023 Unimplemented();
2024 }
2025 }
2026
2027 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
2028 if (!VerifyOops || VerifyAdapterSharing) {
2029 // Below address of the code string confuses VerifyAdapterSharing
2030 // because it may differ between otherwise equivalent adapters.
2031 return;
2032 }
2033
2034 // Pass register number to verify_oop_subroutine
2035 const char* b = nullptr;
2036 {
2037 ResourceMark rm;
2038 stringStream ss;
2039 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
2040 b = code_string(ss.as_string());
2041 }
2042 BLOCK_COMMENT("verify_oop {");
2043
2044 strip_return_address(); // This might happen within a stack frame.
2045 protect_return_address();
2046 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2047 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2048
2049 mov(r0, reg);
2050 movptr(rscratch1, (uintptr_t)(address)b);
2051
2052 // call indirectly to solve generation ordering problem
2053 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2054 ldr(rscratch2, Address(rscratch2));
2055 blr(rscratch2);
2056
2057 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2058 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2059 authenticate_return_address();
2060
2061 BLOCK_COMMENT("} verify_oop");
2062 }
2063
2064 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
2065 if (!VerifyOops || VerifyAdapterSharing) {
2066 // Below address of the code string confuses VerifyAdapterSharing
2067 // because it may differ between otherwise equivalent adapters.
2068 return;
2069 }
2070
2071 const char* b = nullptr;
2072 {
2073 ResourceMark rm;
2074 stringStream ss;
2075 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
2076 b = code_string(ss.as_string());
2077 }
2078 BLOCK_COMMENT("verify_oop_addr {");
2079
2080 strip_return_address(); // This might happen within a stack frame.
2081 protect_return_address();
2082 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2083 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2084
2085 // addr may contain sp so we will have to adjust it based on the
2086 // pushes that we just did.
2087 if (addr.uses(sp)) {
2088 lea(r0, addr);
2089 ldr(r0, Address(r0, 4 * wordSize));
2090 } else {
2091 ldr(r0, addr);
2092 }
2093 movptr(rscratch1, (uintptr_t)(address)b);
2094
2095 // call indirectly to solve generation ordering problem
2096 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2097 ldr(rscratch2, Address(rscratch2));
2098 blr(rscratch2);
2099
2100 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2101 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2102 authenticate_return_address();
2103
2104 BLOCK_COMMENT("} verify_oop_addr");
2105 }
2106
2107 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
2108 int extra_slot_offset) {
2109 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2110 int stackElementSize = Interpreter::stackElementSize;
2111 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
2112 #ifdef ASSERT
2113 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
2114 assert(offset1 - offset == stackElementSize, "correct arithmetic");
2115 #endif
2116 if (arg_slot.is_constant()) {
2117 return Address(esp, arg_slot.as_constant() * stackElementSize
2118 + offset);
2119 } else {
2120 add(rscratch1, esp, arg_slot.as_register(),
2121 ext::uxtx, exact_log2(stackElementSize));
2122 return Address(rscratch1, offset);
2123 }
2124 }
2125
2126 // Handle the receiver type profile update given the "recv" klass.
2127 //
2128 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
2129 // If there are no matching or claimable receiver entries in RD, updates
2130 // the polymorphic counter.
2131 //
2132 // This code expected to run by either the interpreter or JIT-ed code, without
2133 // extra synchronization. For safety, receiver cells are claimed atomically, which
2134 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
2135 // counter updates are not atomic.
2136 //
2137 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
2138 assert_different_registers(recv, mdp, rscratch1, rscratch2);
2139
2140 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
2141 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
2142 int poly_count_offset = in_bytes(CounterData::count_offset());
2143 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
2144 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
2145
2146 // Adjust for MDP offsets.
2147 base_receiver_offset += mdp_offset;
2148 end_receiver_offset += mdp_offset;
2149 poly_count_offset += mdp_offset;
2150
2151 #ifdef ASSERT
2152 // We are about to walk the MDO slots without asking for offsets.
2153 // Check that our math hits all the right spots.
2154 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
2155 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
2156 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
2157 int offset = base_receiver_offset + receiver_step*c;
2158 int count_offset = offset + receiver_to_count_step;
2159 assert(offset == real_recv_offset, "receiver slot math");
2160 assert(count_offset == real_count_offset, "receiver count math");
2161 }
2162 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
2163 assert(poly_count_offset == real_poly_count_offset, "poly counter math");
2164 #endif
2165
2166 // Corner case: no profile table. Increment poly counter and exit.
2167 if (ReceiverTypeData::row_limit() == 0) {
2168 increment(Address(mdp, poly_count_offset), DataLayout::counter_increment);
2169 return;
2170 }
2171
2172 Register offset = rscratch2;
2173
2174 Label L_loop_search_receiver, L_loop_search_empty;
2175 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
2176
2177 // The code here recognizes three major cases:
2178 // A. Fastest: receiver found in the table
2179 // B. Fast: no receiver in the table, and the table is full
2180 // C. Slow: no receiver in the table, free slots in the table
2181 //
2182 // The case A performance is most important, as perfectly-behaved code would end up
2183 // there, especially with larger TypeProfileWidth. The case B performance is
2184 // important as well, this is where bulk of code would land for normally megamorphic
2185 // cases. The case C performance is not essential, its job is to deal with installation
2186 // races, we optimize for code density instead. Case C needs to make sure that receiver
2187 // rows are only claimed once. This makes sure we never overwrite a row for another
2188 // receiver and never duplicate the receivers in the list, making profile type-accurate.
2189 //
2190 // It is very tempting to handle these cases in a single loop, and claim the first slot
2191 // without checking the rest of the table. But, profiling code should tolerate free slots
2192 // in the table, as class unloading can clear them. After such cleanup, the receiver
2193 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
2194 // to complete, before trying to install new slots. Splitting the code in several tight
2195 // loops also helpfully optimizes for cases A and B.
2196 //
2197 // This code is effectively:
2198 //
2199 // restart:
2200 // // Fastest: receiver is already installed
2201 // for (i = 0; i < receiver_count(); i++) {
2202 // if (receiver(i) == recv) goto found_recv(i);
2203 // }
2204 //
2205 // // Fast: no receiver, but profile is full
2206 // for (i = 0; i < receiver_count(); i++) {
2207 // if (receiver(i) == null) goto found_null(i);
2208 // }
2209 // goto polymorphic
2210 //
2211 // // Slow: try to install receiver
2212 // found_null(i):
2213 // CAS(&receiver(i), null, recv);
2214 // goto restart
2215 //
2216 // polymorphic:
2217 // count++;
2218 // return
2219 //
2220 // found_recv(i):
2221 // *receiver_count(i)++
2222 //
2223
2224 bind(L_restart);
2225
2226 // Fastest: receiver is already installed
2227 mov(offset, base_receiver_offset);
2228 bind(L_loop_search_receiver);
2229 ldr(rscratch1, Address(mdp, offset));
2230 cmp(rscratch1, recv);
2231 br(Assembler::EQ, L_found_recv);
2232 add(offset, offset, receiver_step);
2233 sub(rscratch1, offset, end_receiver_offset);
2234 cbnz(rscratch1, L_loop_search_receiver);
2235
2236 // Fast: no receiver, but profile is full
2237 mov(offset, base_receiver_offset);
2238 bind(L_loop_search_empty);
2239 ldr(rscratch1, Address(mdp, offset));
2240 cbz(rscratch1, L_found_empty);
2241 add(offset, offset, receiver_step);
2242 sub(rscratch1, offset, end_receiver_offset);
2243 cbnz(rscratch1, L_loop_search_empty);
2244 b(L_polymorphic);
2245
2246 // Slow: try to install receiver
2247 bind(L_found_empty);
2248
2249 // Atomically swing receiver slot: null -> recv.
2250 //
2251 // The update uses CAS, which clobbers rscratch1. Therefore, rscratch2
2252 // is used to hold the destination address. This is safe because the
2253 // offset is no longer needed after the address is computed.
2254
2255 lea(rscratch2, Address(mdp, offset));
2256 cmpxchg(/*addr*/ rscratch2, /*expected*/ zr, /*new*/ recv, Assembler::xword,
2257 /*acquire*/ false, /*release*/ false, /*weak*/ true, noreg);
2258
2259 // CAS success means the slot now has the receiver we want. CAS failure means
2260 // something had claimed the slot concurrently: it can be the same receiver we want,
2261 // or something else. Since this is a slow path, we can optimize for code density,
2262 // and just restart the search from the beginning.
2263 b(L_restart);
2264
2265 // Counter updates:
2266
2267 // Increment polymorphic counter instead of receiver slot.
2268 bind(L_polymorphic);
2269 mov(offset, poly_count_offset);
2270 b(L_count_update);
2271
2272 // Found a receiver, convert its slot offset to corresponding count offset.
2273 bind(L_found_recv);
2274 add(offset, offset, receiver_to_count_step);
2275
2276 bind(L_count_update);
2277 increment(Address(mdp, offset), DataLayout::counter_increment);
2278 }
2279
2280
2281 void MacroAssembler::call_VM_leaf_base(address entry_point,
2282 int number_of_arguments,
2283 Label *retaddr) {
2284 Label E, L;
2285
2286 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
2287
2288 mov(rscratch1, RuntimeAddress(entry_point));
2289 blr(rscratch1);
2290 if (retaddr)
2291 bind(*retaddr);
2292
2293 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
2294 }
2295
2296 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2297 call_VM_leaf_base(entry_point, number_of_arguments);
2298 }
2299
2300 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2301 pass_arg0(this, arg_0);
2302 call_VM_leaf_base(entry_point, 1);
2303 }
2304
2305 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2306 assert_different_registers(arg_1, c_rarg0);
2307 pass_arg0(this, arg_0);
2308 pass_arg1(this, arg_1);
2309 call_VM_leaf_base(entry_point, 2);
2310 }
2311
2312 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2313 Register arg_1, Register arg_2) {
2314 assert_different_registers(arg_1, c_rarg0);
2315 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2316 pass_arg0(this, arg_0);
2317 pass_arg1(this, arg_1);
2318 pass_arg2(this, arg_2);
2319 call_VM_leaf_base(entry_point, 3);
2320 }
2321
2322 void MacroAssembler::super_call_VM_leaf(address entry_point) {
2323 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2324 }
2325
2326 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2327 pass_arg0(this, arg_0);
2328 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2329 }
2330
2331 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2332
2333 assert_different_registers(arg_0, c_rarg1);
2334 pass_arg1(this, arg_1);
2335 pass_arg0(this, arg_0);
2336 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2337 }
2338
2339 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2340 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2341 assert_different_registers(arg_1, c_rarg2);
2342 pass_arg2(this, arg_2);
2343 pass_arg1(this, arg_1);
2344 pass_arg0(this, arg_0);
2345 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2346 }
2347
2348 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2349 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
2350 assert_different_registers(arg_1, c_rarg2, c_rarg3);
2351 assert_different_registers(arg_2, c_rarg3);
2352 pass_arg3(this, arg_3);
2353 pass_arg2(this, arg_2);
2354 pass_arg1(this, arg_1);
2355 pass_arg0(this, arg_0);
2356 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2357 }
2358
2359 void MacroAssembler::null_check(Register reg, int offset) {
2360 if (needs_explicit_null_check(offset)) {
2361 // provoke OS null exception if reg is null by
2362 // accessing M[reg] w/o changing any registers
2363 // NOTE: this is plenty to provoke a segv
2364 ldr(zr, Address(reg));
2365 } else {
2366 // nothing to do, (later) access of M[reg + offset]
2367 // will provoke OS null exception if reg is null
2368 }
2369 }
2370
2371 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2372 assert_different_registers(markword, rscratch2);
2373 mov(rscratch2, markWord::inline_type_pattern_mask);
2374 andr(markword, markword, rscratch2);
2375 mov(rscratch2, markWord::inline_type_pattern);
2376 cmp(markword, rscratch2);
2377 br(Assembler::EQ, is_inline_type);
2378 }
2379
2380 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null) {
2381 assert_different_registers(tmp, rscratch1);
2382 if (can_be_null) {
2383 cbz(object, not_inline_type);
2384 }
2385 const int is_inline_type_mask = markWord::inline_type_pattern;
2386 ldr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2387 mov(rscratch1, is_inline_type_mask);
2388 andr(tmp, tmp, rscratch1);
2389 cmp(tmp, rscratch1);
2390 br(Assembler::NE, not_inline_type);
2391 }
2392
2393 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2394 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2395 tbnz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, is_null_free_inline_type);
2396 }
2397
2398 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2399 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2400 tbz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, not_null_free_inline_type);
2401 }
2402
2403 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2404 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2405 tbnz(flags, ResolvedFieldEntry::is_flat_shift, is_flat);
2406 }
2407
2408 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) {
2409 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2410 tbnz(flags, ResolvedFieldEntry::has_null_marker_shift, has_null_marker);
2411 }
2412
2413 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2414 Label test_mark_word;
2415 // load mark word
2416 ldr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2417 // check displaced
2418 tst(temp_reg, markWord::unlocked_value);
2419 br(Assembler::NE, test_mark_word);
2420 // slow path use klass prototype
2421 load_prototype_header(temp_reg, oop);
2422
2423 bind(test_mark_word);
2424 andr(temp_reg, temp_reg, test_bit);
2425 if (jmp_set) {
2426 cbnz(temp_reg, jmp_label);
2427 } else {
2428 cbz(temp_reg, jmp_label);
2429 }
2430 }
2431
2432 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array) {
2433 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2434 }
2435
2436 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2437 Label&is_non_flat_array) {
2438 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2439 }
2440
2441 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array) {
2442 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2443 }
2444
2445 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2446 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2447 }
2448
2449 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2450 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2451 br(Assembler::NE, is_flat_array);
2452 }
2453
2454 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
2455 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2456 br(Assembler::EQ, is_non_flat_array);
2457 }
2458
2459 // MacroAssembler protected routines needed to implement
2460 // public methods
2461
2462 void MacroAssembler::mov(Register r, Address dest) {
2463 code_section()->relocate(pc(), dest.rspec());
2464 uint64_t imm64 = (uint64_t)dest.target();
2465 movptr(r, imm64);
2466 }
2467
2468 // Move a constant pointer into r. In AArch64 mode the virtual
2469 // address space is 48 bits in size, so we only need three
2470 // instructions to create a patchable instruction sequence that can
2471 // reach anywhere.
2472 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2473 #ifndef PRODUCT
2474 {
2475 char buffer[64];
2476 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2477 block_comment(buffer);
2478 }
2479 #endif
2480 assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
2481 movz(r, imm64 & 0xffff);
2482 imm64 >>= 16;
2483 movk(r, imm64 & 0xffff, 16);
2484 imm64 >>= 16;
2485 movk(r, imm64 & 0xffff, 32);
2486 }
2487
2488 // Macro to mov replicated immediate to vector register.
2489 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is,
2490 // the upper 56/48/32 bits must be zeros for B/H/S type.
2491 // Vd will get the following values for different arrangements in T
2492 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh
2493 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
2494 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh
2495 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
2496 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
2497 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
2498 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh
2499 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh
2500 // Clobbers rscratch1
2501 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) {
2502 assert(T != T1Q, "unsupported");
2503 if (T == T1D || T == T2D) {
2504 int imm = operand_valid_for_movi_immediate(imm64, T);
2505 if (-1 != imm) {
2506 movi(Vd, T, imm);
2507 } else {
2508 mov(rscratch1, imm64);
2509 dup(Vd, T, rscratch1);
2510 }
2511 return;
2512 }
2513
2514 #ifdef ASSERT
2515 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)");
2516 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)");
2517 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)");
2518 #endif
2519 int shift = operand_valid_for_movi_immediate(imm64, T);
2520 uint32_t imm32 = imm64 & 0xffffffffULL;
2521 if (shift >= 0) {
2522 movi(Vd, T, (imm32 >> shift) & 0xff, shift);
2523 } else {
2524 movw(rscratch1, imm32);
2525 dup(Vd, T, rscratch1);
2526 }
2527 }
2528
2529 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
2530 {
2531 #ifndef PRODUCT
2532 {
2533 char buffer[64];
2534 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, imm64);
2535 block_comment(buffer);
2536 }
2537 #endif
2538 if (operand_valid_for_logical_immediate(false, imm64)) {
2539 orr(dst, zr, imm64);
2540 } else {
2541 // we can use a combination of MOVZ or MOVN with
2542 // MOVK to build up the constant
2543 uint64_t imm_h[4];
2544 int zero_count = 0;
2545 int neg_count = 0;
2546 int i;
2547 for (i = 0; i < 4; i++) {
2548 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
2549 if (imm_h[i] == 0) {
2550 zero_count++;
2551 } else if (imm_h[i] == 0xffffL) {
2552 neg_count++;
2553 }
2554 }
2555 if (zero_count == 4) {
2556 // one MOVZ will do
2557 movz(dst, 0);
2558 } else if (neg_count == 4) {
2559 // one MOVN will do
2560 movn(dst, 0);
2561 } else if (zero_count == 3) {
2562 for (i = 0; i < 4; i++) {
2563 if (imm_h[i] != 0L) {
2564 movz(dst, (uint32_t)imm_h[i], (i << 4));
2565 break;
2566 }
2567 }
2568 } else if (neg_count == 3) {
2569 // one MOVN will do
2570 for (int i = 0; i < 4; i++) {
2571 if (imm_h[i] != 0xffffL) {
2572 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2573 break;
2574 }
2575 }
2576 } else if (zero_count == 2) {
2577 // one MOVZ and one MOVK will do
2578 for (i = 0; i < 3; i++) {
2579 if (imm_h[i] != 0L) {
2580 movz(dst, (uint32_t)imm_h[i], (i << 4));
2581 i++;
2582 break;
2583 }
2584 }
2585 for (;i < 4; i++) {
2586 if (imm_h[i] != 0L) {
2587 movk(dst, (uint32_t)imm_h[i], (i << 4));
2588 }
2589 }
2590 } else if (neg_count == 2) {
2591 // one MOVN and one MOVK will do
2592 for (i = 0; i < 4; i++) {
2593 if (imm_h[i] != 0xffffL) {
2594 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2595 i++;
2596 break;
2597 }
2598 }
2599 for (;i < 4; i++) {
2600 if (imm_h[i] != 0xffffL) {
2601 movk(dst, (uint32_t)imm_h[i], (i << 4));
2602 }
2603 }
2604 } else if (zero_count == 1) {
2605 // one MOVZ and two MOVKs will do
2606 for (i = 0; i < 4; i++) {
2607 if (imm_h[i] != 0L) {
2608 movz(dst, (uint32_t)imm_h[i], (i << 4));
2609 i++;
2610 break;
2611 }
2612 }
2613 for (;i < 4; i++) {
2614 if (imm_h[i] != 0x0L) {
2615 movk(dst, (uint32_t)imm_h[i], (i << 4));
2616 }
2617 }
2618 } else if (neg_count == 1) {
2619 // one MOVN and two MOVKs will do
2620 for (i = 0; i < 4; i++) {
2621 if (imm_h[i] != 0xffffL) {
2622 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2623 i++;
2624 break;
2625 }
2626 }
2627 for (;i < 4; i++) {
2628 if (imm_h[i] != 0xffffL) {
2629 movk(dst, (uint32_t)imm_h[i], (i << 4));
2630 }
2631 }
2632 } else {
2633 // use a MOVZ and 3 MOVKs (makes it easier to debug)
2634 movz(dst, (uint32_t)imm_h[0], 0);
2635 for (i = 1; i < 4; i++) {
2636 movk(dst, (uint32_t)imm_h[i], (i << 4));
2637 }
2638 }
2639 }
2640 }
2641
2642 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
2643 {
2644 #ifndef PRODUCT
2645 {
2646 char buffer[64];
2647 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX32, imm32);
2648 block_comment(buffer);
2649 }
2650 #endif
2651 if (operand_valid_for_logical_immediate(true, imm32)) {
2652 orrw(dst, zr, imm32);
2653 } else {
2654 // we can use MOVZ, MOVN or two calls to MOVK to build up the
2655 // constant
2656 uint32_t imm_h[2];
2657 imm_h[0] = imm32 & 0xffff;
2658 imm_h[1] = ((imm32 >> 16) & 0xffff);
2659 if (imm_h[0] == 0) {
2660 movzw(dst, imm_h[1], 16);
2661 } else if (imm_h[0] == 0xffff) {
2662 movnw(dst, imm_h[1] ^ 0xffff, 16);
2663 } else if (imm_h[1] == 0) {
2664 movzw(dst, imm_h[0], 0);
2665 } else if (imm_h[1] == 0xffff) {
2666 movnw(dst, imm_h[0] ^ 0xffff, 0);
2667 } else {
2668 // use a MOVZ and MOVK (makes it easier to debug)
2669 movzw(dst, imm_h[0], 0);
2670 movkw(dst, imm_h[1], 16);
2671 }
2672 }
2673 }
2674
2675 // Form an address from base + offset in Rd. Rd may or may
2676 // not actually be used: you must use the Address that is returned.
2677 // It is up to you to ensure that the shift provided matches the size
2678 // of your data.
2679 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
2680 if (Address::offset_ok_for_immed(byte_offset, shift))
2681 // It fits; no need for any heroics
2682 return Address(base, byte_offset);
2683
2684 // Don't do anything clever with negative or misaligned offsets
2685 unsigned mask = (1 << shift) - 1;
2686 if (byte_offset < 0 || byte_offset & mask) {
2687 mov(Rd, byte_offset);
2688 add(Rd, base, Rd);
2689 return Address(Rd);
2690 }
2691
2692 // See if we can do this with two 12-bit offsets
2693 {
2694 uint64_t word_offset = byte_offset >> shift;
2695 uint64_t masked_offset = word_offset & 0xfff000;
2696 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
2697 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
2698 add(Rd, base, masked_offset << shift);
2699 word_offset -= masked_offset;
2700 return Address(Rd, word_offset << shift);
2701 }
2702 }
2703
2704 // Do it the hard way
2705 mov(Rd, byte_offset);
2706 add(Rd, base, Rd);
2707 return Address(Rd);
2708 }
2709
2710 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
2711 bool want_remainder, Register scratch)
2712 {
2713 // Full implementation of Java idiv and irem. The function
2714 // returns the (pc) offset of the div instruction - may be needed
2715 // for implicit exceptions.
2716 //
2717 // constraint : ra/rb =/= scratch
2718 // normal case
2719 //
2720 // input : ra: dividend
2721 // rb: divisor
2722 //
2723 // result: either
2724 // quotient (= ra idiv rb)
2725 // remainder (= ra irem rb)
2726
2727 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2728
2729 int idivl_offset = offset();
2730 if (! want_remainder) {
2731 sdivw(result, ra, rb);
2732 } else {
2733 sdivw(scratch, ra, rb);
2734 Assembler::msubw(result, scratch, rb, ra);
2735 }
2736
2737 return idivl_offset;
2738 }
2739
2740 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
2741 bool want_remainder, Register scratch)
2742 {
2743 // Full implementation of Java ldiv and lrem. The function
2744 // returns the (pc) offset of the div instruction - may be needed
2745 // for implicit exceptions.
2746 //
2747 // constraint : ra/rb =/= scratch
2748 // normal case
2749 //
2750 // input : ra: dividend
2751 // rb: divisor
2752 //
2753 // result: either
2754 // quotient (= ra idiv rb)
2755 // remainder (= ra irem rb)
2756
2757 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2758
2759 int idivq_offset = offset();
2760 if (! want_remainder) {
2761 sdiv(result, ra, rb);
2762 } else {
2763 sdiv(scratch, ra, rb);
2764 Assembler::msub(result, scratch, rb, ra);
2765 }
2766
2767 return idivq_offset;
2768 }
2769
2770 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
2771 address prev = pc() - NativeMembar::instruction_size;
2772 address last = code()->last_insn();
2773 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) {
2774 NativeMembar *bar = NativeMembar_at(prev);
2775 if (AlwaysMergeDMB) {
2776 bar->set_kind(bar->get_kind() | order_constraint);
2777 BLOCK_COMMENT("merged membar(always)");
2778 return;
2779 }
2780 // Don't promote DMB ST|DMB LD to DMB (a full barrier) because
2781 // doing so would introduce a StoreLoad which the caller did not
2782 // intend
2783 if (bar->get_kind() == order_constraint
2784 || bar->get_kind() == AnyAny
2785 || order_constraint == AnyAny) {
2786 // We are merging two memory barrier instructions. On AArch64 we
2787 // can do this simply by ORing them together.
2788 bar->set_kind(bar->get_kind() | order_constraint);
2789 BLOCK_COMMENT("merged membar");
2790 return;
2791 } else {
2792 // A special case like "DMB ST;DMB LD;DMB ST", the last DMB can be skipped
2793 // We need check the last 2 instructions
2794 address prev2 = prev - NativeMembar::instruction_size;
2795 if (last != code()->last_label() && nativeInstruction_at(prev2)->is_Membar()) {
2796 NativeMembar *bar2 = NativeMembar_at(prev2);
2797 assert(bar2->get_kind() == order_constraint, "it should be merged before");
2798 BLOCK_COMMENT("merged membar(elided)");
2799 return;
2800 }
2801 }
2802 }
2803 code()->set_last_insn(pc());
2804 dmb(Assembler::barrier(order_constraint));
2805 }
2806
2807 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
2808 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
2809 merge_ldst(rt, adr, size_in_bytes, is_store);
2810 code()->clear_last_insn();
2811 return true;
2812 } else {
2813 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
2814 const uint64_t mask = size_in_bytes - 1;
2815 if (adr.getMode() == Address::base_plus_offset &&
2816 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
2817 code()->set_last_insn(pc());
2818 }
2819 return false;
2820 }
2821 }
2822
2823 void MacroAssembler::ldr(Register Rx, const Address &adr) {
2824 // We always try to merge two adjacent loads into one ldp.
2825 if (!try_merge_ldst(Rx, adr, 8, false)) {
2826 Assembler::ldr(Rx, adr);
2827 }
2828 }
2829
2830 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
2831 // We always try to merge two adjacent loads into one ldp.
2832 if (!try_merge_ldst(Rw, adr, 4, false)) {
2833 Assembler::ldrw(Rw, adr);
2834 }
2835 }
2836
2837 void MacroAssembler::str(Register Rx, const Address &adr) {
2838 // We always try to merge two adjacent stores into one stp.
2839 if (!try_merge_ldst(Rx, adr, 8, true)) {
2840 Assembler::str(Rx, adr);
2841 }
2842 }
2843
2844 void MacroAssembler::strw(Register Rw, const Address &adr) {
2845 // We always try to merge two adjacent stores into one stp.
2846 if (!try_merge_ldst(Rw, adr, 4, true)) {
2847 Assembler::strw(Rw, adr);
2848 }
2849 }
2850
2851 // MacroAssembler routines found actually to be needed
2852
2853 void MacroAssembler::push(Register src)
2854 {
2855 str(src, Address(pre(esp, -1 * wordSize)));
2856 }
2857
2858 void MacroAssembler::pop(Register dst)
2859 {
2860 ldr(dst, Address(post(esp, 1 * wordSize)));
2861 }
2862
2863 // Note: load_unsigned_short used to be called load_unsigned_word.
2864 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2865 int off = offset();
2866 ldrh(dst, src);
2867 return off;
2868 }
2869
2870 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2871 int off = offset();
2872 ldrb(dst, src);
2873 return off;
2874 }
2875
2876 int MacroAssembler::load_signed_short(Register dst, Address src) {
2877 int off = offset();
2878 ldrsh(dst, src);
2879 return off;
2880 }
2881
2882 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2883 int off = offset();
2884 ldrsb(dst, src);
2885 return off;
2886 }
2887
2888 int MacroAssembler::load_signed_short32(Register dst, Address src) {
2889 int off = offset();
2890 ldrshw(dst, src);
2891 return off;
2892 }
2893
2894 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
2895 int off = offset();
2896 ldrsbw(dst, src);
2897 return off;
2898 }
2899
2900 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2901 switch (size_in_bytes) {
2902 case 8: ldr(dst, src); break;
2903 case 4: ldrw(dst, src); break;
2904 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2905 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2906 default: ShouldNotReachHere();
2907 }
2908 }
2909
2910 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) {
2911 switch (size_in_bytes) {
2912 case 8: str(src, dst); break;
2913 case 4: strw(src, dst); break;
2914 case 2: strh(src, dst); break;
2915 case 1: strb(src, dst); break;
2916 default: ShouldNotReachHere();
2917 }
2918 }
2919
2920 void MacroAssembler::decrementw(Register reg, int value)
2921 {
2922 if (value < 0) { incrementw(reg, -value); return; }
2923 if (value == 0) { return; }
2924 if (value < (1 << 12)) { subw(reg, reg, value); return; }
2925 /* else */ {
2926 guarantee(reg != rscratch2, "invalid dst for register decrement");
2927 movw(rscratch2, (unsigned)value);
2928 subw(reg, reg, rscratch2);
2929 }
2930 }
2931
2932 void MacroAssembler::decrement(Register reg, int value)
2933 {
2934 if (value < 0) { increment(reg, -value); return; }
2935 if (value == 0) { return; }
2936 if (value < (1 << 12)) { sub(reg, reg, value); return; }
2937 /* else */ {
2938 assert(reg != rscratch2, "invalid dst for register decrement");
2939 mov(rscratch2, (uint64_t)value);
2940 sub(reg, reg, rscratch2);
2941 }
2942 }
2943
2944 void MacroAssembler::decrementw(Address dst, int value)
2945 {
2946 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
2947 if (dst.getMode() == Address::literal) {
2948 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2949 lea(rscratch2, dst);
2950 dst = Address(rscratch2);
2951 }
2952 ldrw(rscratch1, dst);
2953 decrementw(rscratch1, value);
2954 strw(rscratch1, dst);
2955 }
2956
2957 void MacroAssembler::decrement(Address dst, int value)
2958 {
2959 assert(!dst.uses(rscratch1), "invalid address for decrement");
2960 if (dst.getMode() == Address::literal) {
2961 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2962 lea(rscratch2, dst);
2963 dst = Address(rscratch2);
2964 }
2965 ldr(rscratch1, dst);
2966 decrement(rscratch1, value);
2967 str(rscratch1, dst);
2968 }
2969
2970 void MacroAssembler::incrementw(Register reg, int value)
2971 {
2972 if (value < 0) { decrementw(reg, -value); return; }
2973 if (value == 0) { return; }
2974 if (value < (1 << 12)) { addw(reg, reg, value); return; }
2975 /* else */ {
2976 assert(reg != rscratch2, "invalid dst for register increment");
2977 movw(rscratch2, (unsigned)value);
2978 addw(reg, reg, rscratch2);
2979 }
2980 }
2981
2982 void MacroAssembler::increment(Register reg, int value)
2983 {
2984 if (value < 0) { decrement(reg, -value); return; }
2985 if (value == 0) { return; }
2986 if (value < (1 << 12)) { add(reg, reg, value); return; }
2987 /* else */ {
2988 assert(reg != rscratch2, "invalid dst for register increment");
2989 movw(rscratch2, (unsigned)value);
2990 add(reg, reg, rscratch2);
2991 }
2992 }
2993
2994 void MacroAssembler::incrementw(Address dst, int value)
2995 {
2996 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2997 if (dst.getMode() == Address::literal) {
2998 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2999 lea(rscratch2, dst);
3000 dst = Address(rscratch2);
3001 }
3002 ldrw(rscratch1, dst);
3003 incrementw(rscratch1, value);
3004 strw(rscratch1, dst);
3005 }
3006
3007 void MacroAssembler::increment(Address dst, int value)
3008 {
3009 assert(!dst.uses(rscratch1), "invalid dst for address increment");
3010 if (dst.getMode() == Address::literal) {
3011 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
3012 lea(rscratch2, dst);
3013 dst = Address(rscratch2);
3014 }
3015 ldr(rscratch1, dst);
3016 increment(rscratch1, value);
3017 str(rscratch1, dst);
3018 }
3019
3020 // Push lots of registers in the bit set supplied. Don't push sp.
3021 // Return the number of words pushed
3022 int MacroAssembler::push(unsigned int bitset, Register stack) {
3023 int words_pushed = 0;
3024
3025 // Scan bitset to accumulate register pairs
3026 unsigned char regs[32];
3027 int count = 0;
3028 for (int reg = 0; reg <= 30; reg++) {
3029 if (1 & bitset)
3030 regs[count++] = reg;
3031 bitset >>= 1;
3032 }
3033 regs[count++] = zr->raw_encoding();
3034 count &= ~1; // Only push an even number of regs
3035
3036 if (count) {
3037 stp(as_Register(regs[0]), as_Register(regs[1]),
3038 Address(pre(stack, -count * wordSize)));
3039 words_pushed += 2;
3040 }
3041 for (int i = 2; i < count; i += 2) {
3042 stp(as_Register(regs[i]), as_Register(regs[i+1]),
3043 Address(stack, i * wordSize));
3044 words_pushed += 2;
3045 }
3046
3047 assert(words_pushed == count, "oops, pushed != count");
3048
3049 return count;
3050 }
3051
3052 int MacroAssembler::pop(unsigned int bitset, Register stack) {
3053 int words_pushed = 0;
3054
3055 // Scan bitset to accumulate register pairs
3056 unsigned char regs[32];
3057 int count = 0;
3058 for (int reg = 0; reg <= 30; reg++) {
3059 if (1 & bitset)
3060 regs[count++] = reg;
3061 bitset >>= 1;
3062 }
3063 regs[count++] = zr->raw_encoding();
3064 count &= ~1;
3065
3066 for (int i = 2; i < count; i += 2) {
3067 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
3068 Address(stack, i * wordSize));
3069 words_pushed += 2;
3070 }
3071 if (count) {
3072 ldp(as_Register(regs[0]), as_Register(regs[1]),
3073 Address(post(stack, count * wordSize)));
3074 words_pushed += 2;
3075 }
3076
3077 assert(words_pushed == count, "oops, pushed != count");
3078
3079 return count;
3080 }
3081
3082 // Push lots of registers in the bit set supplied. Don't push sp.
3083 // Return the number of dwords pushed
3084 int MacroAssembler::push_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
3085 int words_pushed = 0;
3086 bool use_sve = false;
3087 int sve_vector_size_in_bytes = 0;
3088
3089 #ifdef COMPILER2
3090 use_sve = Matcher::supports_scalable_vector();
3091 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
3092 #endif
3093
3094 // Scan bitset to accumulate register pairs
3095 unsigned char regs[32];
3096 int count = 0;
3097 for (int reg = 0; reg <= 31; reg++) {
3098 if (1 & bitset)
3099 regs[count++] = reg;
3100 bitset >>= 1;
3101 }
3102
3103 if (count == 0) {
3104 return 0;
3105 }
3106
3107 if (mode == PushPopFull) {
3108 if (use_sve && sve_vector_size_in_bytes > 16) {
3109 mode = PushPopSVE;
3110 } else {
3111 mode = PushPopNeon;
3112 }
3113 }
3114
3115 #ifndef PRODUCT
3116 {
3117 char buffer[48];
3118 if (mode == PushPopSVE) {
3119 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d SVE registers", count);
3120 } else if (mode == PushPopNeon) {
3121 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d Neon registers", count);
3122 } else {
3123 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d fp registers", count);
3124 }
3125 block_comment(buffer);
3126 }
3127 #endif
3128
3129 if (mode == PushPopSVE) {
3130 sub(stack, stack, sve_vector_size_in_bytes * count);
3131 for (int i = 0; i < count; i++) {
3132 sve_str(as_FloatRegister(regs[i]), Address(stack, i));
3133 }
3134 return count * sve_vector_size_in_bytes / 8;
3135 }
3136
3137 if (mode == PushPopNeon) {
3138 if (count == 1) {
3139 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2)));
3140 return 2;
3141 }
3142
3143 bool odd = (count & 1) == 1;
3144 int push_slots = count + (odd ? 1 : 0);
3145
3146 // Always pushing full 128 bit registers.
3147 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2)));
3148 words_pushed += 2;
3149
3150 for (int i = 2; i + 1 < count; i += 2) {
3151 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3152 words_pushed += 2;
3153 }
3154
3155 if (odd) {
3156 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3157 words_pushed++;
3158 }
3159
3160 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3161 return count * 2;
3162 }
3163
3164 if (mode == PushPopFp) {
3165 bool odd = (count & 1) == 1;
3166 int push_slots = count + (odd ? 1 : 0);
3167
3168 if (count == 1) {
3169 // Stack pointer must be 16 bytes aligned
3170 strd(as_FloatRegister(regs[0]), Address(pre(stack, -push_slots * wordSize)));
3171 return 1;
3172 }
3173
3174 stpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize)));
3175 words_pushed += 2;
3176
3177 for (int i = 2; i + 1 < count; i += 2) {
3178 stpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3179 words_pushed += 2;
3180 }
3181
3182 if (odd) {
3183 // Stack pointer must be 16 bytes aligned
3184 strd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3185 words_pushed++;
3186 }
3187
3188 assert(words_pushed == count, "oops, pushed != count");
3189
3190 return count;
3191 }
3192
3193 return 0;
3194 }
3195
3196 // Return the number of dwords popped
3197 int MacroAssembler::pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
3198 int words_pushed = 0;
3199 bool use_sve = false;
3200 int sve_vector_size_in_bytes = 0;
3201
3202 #ifdef COMPILER2
3203 use_sve = Matcher::supports_scalable_vector();
3204 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
3205 #endif
3206 // Scan bitset to accumulate register pairs
3207 unsigned char regs[32];
3208 int count = 0;
3209 for (int reg = 0; reg <= 31; reg++) {
3210 if (1 & bitset)
3211 regs[count++] = reg;
3212 bitset >>= 1;
3213 }
3214
3215 if (count == 0) {
3216 return 0;
3217 }
3218
3219 if (mode == PushPopFull) {
3220 if (use_sve && sve_vector_size_in_bytes > 16) {
3221 mode = PushPopSVE;
3222 } else {
3223 mode = PushPopNeon;
3224 }
3225 }
3226
3227 #ifndef PRODUCT
3228 {
3229 char buffer[48];
3230 if (mode == PushPopSVE) {
3231 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d SVE registers", count);
3232 } else if (mode == PushPopNeon) {
3233 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d Neon registers", count);
3234 } else {
3235 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d fp registers", count);
3236 }
3237 block_comment(buffer);
3238 }
3239 #endif
3240
3241 if (mode == PushPopSVE) {
3242 for (int i = count - 1; i >= 0; i--) {
3243 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i));
3244 }
3245 add(stack, stack, sve_vector_size_in_bytes * count);
3246 return count * sve_vector_size_in_bytes / 8;
3247 }
3248
3249 if (mode == PushPopNeon) {
3250 if (count == 1) {
3251 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2)));
3252 return 2;
3253 }
3254
3255 bool odd = (count & 1) == 1;
3256 int push_slots = count + (odd ? 1 : 0);
3257
3258 if (odd) {
3259 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3260 words_pushed++;
3261 }
3262
3263 for (int i = 2; i + 1 < count; i += 2) {
3264 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3265 words_pushed += 2;
3266 }
3267
3268 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2)));
3269 words_pushed += 2;
3270
3271 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3272
3273 return count * 2;
3274 }
3275
3276 if (mode == PushPopFp) {
3277 bool odd = (count & 1) == 1;
3278 int push_slots = count + (odd ? 1 : 0);
3279
3280 if (count == 1) {
3281 ldrd(as_FloatRegister(regs[0]), Address(post(stack, push_slots * wordSize)));
3282 return 1;
3283 }
3284
3285 if (odd) {
3286 ldrd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3287 words_pushed++;
3288 }
3289
3290 for (int i = 2; i + 1 < count; i += 2) {
3291 ldpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3292 words_pushed += 2;
3293 }
3294
3295 ldpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize)));
3296 words_pushed += 2;
3297
3298 assert(words_pushed == count, "oops, pushed != count");
3299
3300 return count;
3301 }
3302
3303 return 0;
3304 }
3305
3306 // Return the number of dwords pushed
3307 int MacroAssembler::push_p(unsigned int bitset, Register stack) {
3308 bool use_sve = false;
3309 int sve_predicate_size_in_slots = 0;
3310
3311 #ifdef COMPILER2
3312 use_sve = Matcher::supports_scalable_vector();
3313 if (use_sve) {
3314 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3315 }
3316 #endif
3317
3318 if (!use_sve) {
3319 return 0;
3320 }
3321
3322 unsigned char regs[PRegister::number_of_registers];
3323 int count = 0;
3324 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3325 if (1 & bitset)
3326 regs[count++] = reg;
3327 bitset >>= 1;
3328 }
3329
3330 if (count == 0) {
3331 return 0;
3332 }
3333
3334 int total_push_bytes = align_up(sve_predicate_size_in_slots *
3335 VMRegImpl::stack_slot_size * count, 16);
3336 sub(stack, stack, total_push_bytes);
3337 for (int i = 0; i < count; i++) {
3338 sve_str(as_PRegister(regs[i]), Address(stack, i));
3339 }
3340 return total_push_bytes / 8;
3341 }
3342
3343 // Return the number of dwords popped
3344 int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
3345 bool use_sve = false;
3346 int sve_predicate_size_in_slots = 0;
3347
3348 #ifdef COMPILER2
3349 use_sve = Matcher::supports_scalable_vector();
3350 if (use_sve) {
3351 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3352 }
3353 #endif
3354
3355 if (!use_sve) {
3356 return 0;
3357 }
3358
3359 unsigned char regs[PRegister::number_of_registers];
3360 int count = 0;
3361 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3362 if (1 & bitset)
3363 regs[count++] = reg;
3364 bitset >>= 1;
3365 }
3366
3367 if (count == 0) {
3368 return 0;
3369 }
3370
3371 int total_pop_bytes = align_up(sve_predicate_size_in_slots *
3372 VMRegImpl::stack_slot_size * count, 16);
3373 for (int i = count - 1; i >= 0; i--) {
3374 sve_ldr(as_PRegister(regs[i]), Address(stack, i));
3375 }
3376 add(stack, stack, total_pop_bytes);
3377 return total_pop_bytes / 8;
3378 }
3379
3380 #ifdef ASSERT
3381 void MacroAssembler::verify_heapbase(const char* msg) {
3382 #if 0
3383 assert (Universe::heap() != nullptr, "java heap should be initialized");
3384 if (!UseCompressedOops || Universe::ptr_base() == nullptr) {
3385 // rheapbase is allocated as general register
3386 return;
3387 }
3388 if (CheckCompressedOops) {
3389 Label ok;
3390 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
3391 cmpptr(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3392 br(Assembler::EQ, ok);
3393 stop(msg);
3394 bind(ok);
3395 pop(1 << rscratch1->encoding(), sp);
3396 }
3397 #endif
3398 }
3399 #endif
3400
3401 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
3402 assert_different_registers(value, tmp1, tmp2);
3403 Label done, tagged, weak_tagged;
3404
3405 cbz(value, done); // Use null as-is.
3406 tst(value, JNIHandles::tag_mask); // Test for tag.
3407 br(Assembler::NE, tagged);
3408
3409 // Resolve local handle
3410 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2);
3411 verify_oop(value);
3412 b(done);
3413
3414 bind(tagged);
3415 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1);
3416 tbnz(value, 0, weak_tagged); // Test for weak tag.
3417
3418 // Resolve global handle
3419 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3420 verify_oop(value);
3421 b(done);
3422
3423 bind(weak_tagged);
3424 // Resolve jweak.
3425 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3426 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2);
3427 verify_oop(value);
3428
3429 bind(done);
3430 }
3431
3432 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) {
3433 assert_different_registers(value, tmp1, tmp2);
3434 Label done;
3435
3436 cbz(value, done); // Use null as-is.
3437
3438 #ifdef ASSERT
3439 {
3440 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10);
3441 Label valid_global_tag;
3442 tbnz(value, 1, valid_global_tag); // Test for global tag
3443 stop("non global jobject using resolve_global_jobject");
3444 bind(valid_global_tag);
3445 }
3446 #endif
3447
3448 // Resolve global handle
3449 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3450 verify_oop(value);
3451
3452 bind(done);
3453 }
3454
3455 void MacroAssembler::stop(const char* msg) {
3456 // Skip AOT caching C strings in scratch buffer.
3457 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
3458 BLOCK_COMMENT(str);
3459 // load msg into r0 so we can access it from the signal handler
3460 // ExternalAddress enables saving and restoring via the code cache
3461 lea(c_rarg0, ExternalAddress((address) str));
3462 dcps1(0xdeae);
3463 }
3464
3465 void MacroAssembler::unimplemented(const char* what) {
3466 const char* buf = nullptr;
3467 {
3468 ResourceMark rm;
3469 stringStream ss;
3470 ss.print("unimplemented: %s", what);
3471 buf = code_string(ss.as_string());
3472 }
3473 stop(buf);
3474 }
3475
3476 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
3477 #ifdef ASSERT
3478 Label OK;
3479 br(cc, OK);
3480 stop(msg);
3481 bind(OK);
3482 #endif
3483 }
3484
3485 // If a constant does not fit in an immediate field, generate some
3486 // number of MOV instructions and then perform the operation.
3487 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
3488 add_sub_imm_insn insn1,
3489 add_sub_reg_insn insn2,
3490 bool is32) {
3491 assert(Rd != zr, "Rd = zr and not setting flags?");
3492 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3493 if (fits) {
3494 (this->*insn1)(Rd, Rn, imm);
3495 } else {
3496 if (g_uabs(imm) < (1 << 24)) {
3497 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
3498 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
3499 } else {
3500 assert_different_registers(Rd, Rn);
3501 mov(Rd, imm);
3502 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3503 }
3504 }
3505 }
3506
3507 // Separate vsn which sets the flags. Optimisations are more restricted
3508 // because we must set the flags correctly.
3509 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
3510 add_sub_imm_insn insn1,
3511 add_sub_reg_insn insn2,
3512 bool is32) {
3513 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3514 if (fits) {
3515 (this->*insn1)(Rd, Rn, imm);
3516 } else {
3517 assert_different_registers(Rd, Rn);
3518 assert(Rd != zr, "overflow in immediate operand");
3519 mov(Rd, imm);
3520 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3521 }
3522 }
3523
3524
3525 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
3526 if (increment.is_register()) {
3527 add(Rd, Rn, increment.as_register());
3528 } else {
3529 add(Rd, Rn, increment.as_constant());
3530 }
3531 }
3532
3533 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
3534 if (increment.is_register()) {
3535 addw(Rd, Rn, increment.as_register());
3536 } else {
3537 addw(Rd, Rn, increment.as_constant());
3538 }
3539 }
3540
3541 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
3542 if (decrement.is_register()) {
3543 sub(Rd, Rn, decrement.as_register());
3544 } else {
3545 sub(Rd, Rn, decrement.as_constant());
3546 }
3547 }
3548
3549 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
3550 if (decrement.is_register()) {
3551 subw(Rd, Rn, decrement.as_register());
3552 } else {
3553 subw(Rd, Rn, decrement.as_constant());
3554 }
3555 }
3556
3557 void MacroAssembler::reinit_heapbase()
3558 {
3559 if (UseCompressedOops) {
3560 if (Universe::is_fully_initialized()) {
3561 mov(rheapbase, CompressedOops::base());
3562 } else {
3563 lea(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3564 ldr(rheapbase, Address(rheapbase));
3565 }
3566 }
3567 }
3568
3569 // A generic CAS; success or failure is in the EQ flag. A weak CAS
3570 // doesn't retry and may fail spuriously. If the oldval is wanted,
3571 // Pass a register for the result, otherwise pass noreg.
3572
3573 // Clobbers rscratch1
3574 void MacroAssembler::cmpxchg(Register addr, Register expected,
3575 Register new_val,
3576 enum operand_size size,
3577 bool acquire, bool release,
3578 bool weak,
3579 Register result) {
3580 if (result == noreg) result = rscratch1;
3581 BLOCK_COMMENT("cmpxchg {");
3582 if (UseLSE) {
3583 mov(result, expected);
3584 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
3585 compare_eq(result, expected, size);
3586 #ifdef ASSERT
3587 // Poison rscratch1 which is written on !UseLSE branch
3588 mov(rscratch1, 0x1f1f1f1f1f1f1f1f);
3589 #endif
3590 } else {
3591 Label retry_load, done;
3592 prfm(Address(addr), PSTL1STRM);
3593 bind(retry_load);
3594 load_exclusive(result, addr, size, acquire);
3595 compare_eq(result, expected, size);
3596 br(Assembler::NE, done);
3597 store_exclusive(rscratch1, new_val, addr, size, release);
3598 if (weak) {
3599 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
3600 } else {
3601 cbnzw(rscratch1, retry_load);
3602 }
3603 bind(done);
3604 }
3605 BLOCK_COMMENT("} cmpxchg");
3606 }
3607
3608 // A generic comparison. Only compares for equality, clobbers rscratch1.
3609 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
3610 if (size == xword) {
3611 cmp(rm, rn);
3612 } else if (size == word) {
3613 cmpw(rm, rn);
3614 } else if (size == halfword) {
3615 eorw(rscratch1, rm, rn);
3616 ands(zr, rscratch1, 0xffff);
3617 } else if (size == byte) {
3618 eorw(rscratch1, rm, rn);
3619 ands(zr, rscratch1, 0xff);
3620 } else {
3621 ShouldNotReachHere();
3622 }
3623 }
3624
3625
3626 static bool different(Register a, RegisterOrConstant b, Register c) {
3627 if (b.is_constant())
3628 return a != c;
3629 else
3630 return a != b.as_register() && a != c && b.as_register() != c;
3631 }
3632
3633 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
3634 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
3635 if (UseLSE) { \
3636 prev = prev->is_valid() ? prev : zr; \
3637 if (incr.is_register()) { \
3638 AOP(sz, incr.as_register(), prev, addr); \
3639 } else { \
3640 mov(rscratch2, incr.as_constant()); \
3641 AOP(sz, rscratch2, prev, addr); \
3642 } \
3643 return; \
3644 } \
3645 Register result = rscratch2; \
3646 if (prev->is_valid()) \
3647 result = different(prev, incr, addr) ? prev : rscratch2; \
3648 \
3649 Label retry_load; \
3650 prfm(Address(addr), PSTL1STRM); \
3651 bind(retry_load); \
3652 LDXR(result, addr); \
3653 OP(rscratch1, result, incr); \
3654 STXR(rscratch2, rscratch1, addr); \
3655 cbnzw(rscratch2, retry_load); \
3656 if (prev->is_valid() && prev != result) { \
3657 IOP(prev, rscratch1, incr); \
3658 } \
3659 }
3660
3661 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
3662 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
3663 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
3664 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
3665
3666 #undef ATOMIC_OP
3667
3668 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
3669 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
3670 if (UseLSE) { \
3671 prev = prev->is_valid() ? prev : zr; \
3672 AOP(sz, newv, prev, addr); \
3673 return; \
3674 } \
3675 Register result = rscratch2; \
3676 if (prev->is_valid()) \
3677 result = different(prev, newv, addr) ? prev : rscratch2; \
3678 \
3679 Label retry_load; \
3680 prfm(Address(addr), PSTL1STRM); \
3681 bind(retry_load); \
3682 LDXR(result, addr); \
3683 STXR(rscratch1, newv, addr); \
3684 cbnzw(rscratch1, retry_load); \
3685 if (prev->is_valid() && prev != result) \
3686 mov(prev, result); \
3687 }
3688
3689 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
3690 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
3691 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
3692 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
3693 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
3694 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
3695
3696 #undef ATOMIC_XCHG
3697
3698 #ifndef PRODUCT
3699 extern "C" void findpc(intptr_t x);
3700 #endif
3701
3702 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
3703 {
3704 // In order to get locks to work, we need to fake a in_VM state
3705 if (ShowMessageBoxOnError) {
3706 JavaThread* thread = JavaThread::current();
3707 thread->set_thread_state(_thread_in_vm);
3708 #ifndef PRODUCT
3709 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
3710 ttyLocker ttyl;
3711 BytecodeCounter::print();
3712 }
3713 #endif
3714 if (os::message_box(msg, "Execution stopped, print registers?")) {
3715 ttyLocker ttyl;
3716 tty->print_cr(" pc = 0x%016" PRIx64, pc);
3717 #ifndef PRODUCT
3718 tty->cr();
3719 findpc(pc);
3720 tty->cr();
3721 #endif
3722 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
3723 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
3724 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
3725 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
3726 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
3727 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
3728 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
3729 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
3730 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
3731 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
3732 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
3733 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
3734 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
3735 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
3736 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
3737 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
3738 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
3739 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
3740 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
3741 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
3742 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
3743 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
3744 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
3745 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
3746 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
3747 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
3748 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
3749 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
3750 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
3751 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
3752 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
3753 BREAKPOINT;
3754 }
3755 }
3756 fatal("DEBUG MESSAGE: %s", msg);
3757 }
3758
3759 RegSet MacroAssembler::call_clobbered_gp_registers() {
3760 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
3761 #ifndef R18_RESERVED
3762 regs += r18_tls;
3763 #endif
3764 return regs;
3765 }
3766
3767 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
3768 int step = 4 * wordSize;
3769 push(call_clobbered_gp_registers() - exclude, sp);
3770 sub(sp, sp, step);
3771 mov(rscratch1, -step);
3772 // Push v0-v7, v16-v31.
3773 for (int i = 31; i>= 4; i -= 4) {
3774 if (i <= v7->encoding() || i >= v16->encoding())
3775 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
3776 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
3777 }
3778 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
3779 as_FloatRegister(3), T1D, Address(sp));
3780 }
3781
3782 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
3783 for (int i = 0; i < 32; i += 4) {
3784 if (i <= v7->encoding() || i >= v16->encoding())
3785 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3786 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
3787 }
3788
3789 reinitialize_ptrue();
3790
3791 pop(call_clobbered_gp_registers() - exclude, sp);
3792 }
3793
3794 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
3795 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3796 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
3797 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3798 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3799 for (int i = 0; i < FloatRegister::number_of_registers; i++) {
3800 sve_str(as_FloatRegister(i), Address(sp, i));
3801 }
3802 } else {
3803 int step = (save_vectors ? 8 : 4) * wordSize;
3804 mov(rscratch1, -step);
3805 sub(sp, sp, step);
3806 for (int i = 28; i >= 4; i -= 4) {
3807 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3808 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
3809 }
3810 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
3811 }
3812 if (save_vectors && use_sve && total_predicate_in_bytes > 0) {
3813 sub(sp, sp, total_predicate_in_bytes);
3814 for (int i = 0; i < PRegister::number_of_registers; i++) {
3815 sve_str(as_PRegister(i), Address(sp, i));
3816 }
3817 }
3818 }
3819
3820 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
3821 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3822 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) {
3823 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) {
3824 sve_ldr(as_PRegister(i), Address(sp, i));
3825 }
3826 add(sp, sp, total_predicate_in_bytes);
3827 }
3828 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3829 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) {
3830 sve_ldr(as_FloatRegister(i), Address(sp, i));
3831 }
3832 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3833 } else {
3834 int step = (restore_vectors ? 8 : 4) * wordSize;
3835 for (int i = 0; i <= 28; i += 4)
3836 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3837 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
3838 }
3839
3840 // We may use predicate registers and rely on ptrue with SVE,
3841 // regardless of wide vector (> 8 bytes) used or not.
3842 if (use_sve) {
3843 reinitialize_ptrue();
3844 }
3845
3846 // integer registers except lr & sp
3847 pop(RegSet::range(r0, r17), sp);
3848 #ifdef R18_RESERVED
3849 ldp(zr, r19, Address(post(sp, 2 * wordSize)));
3850 pop(RegSet::range(r20, r29), sp);
3851 #else
3852 pop(RegSet::range(r18_tls, r29), sp);
3853 #endif
3854 }
3855
3856 /**
3857 * Helpers for multiply_to_len().
3858 */
3859 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
3860 Register src1, Register src2) {
3861 adds(dest_lo, dest_lo, src1);
3862 adc(dest_hi, dest_hi, zr);
3863 adds(dest_lo, dest_lo, src2);
3864 adc(final_dest_hi, dest_hi, zr);
3865 }
3866
3867 // Generate an address from (r + r1 extend offset). "size" is the
3868 // size of the operand. The result may be in rscratch2.
3869 Address MacroAssembler::offsetted_address(Register r, Register r1,
3870 Address::extend ext, int offset, int size) {
3871 if (offset || (ext.shift() % size != 0)) {
3872 lea(rscratch2, Address(r, r1, ext));
3873 return Address(rscratch2, offset);
3874 } else {
3875 return Address(r, r1, ext);
3876 }
3877 }
3878
3879 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
3880 {
3881 assert(offset >= 0, "spill to negative address?");
3882 // Offset reachable ?
3883 // Not aligned - 9 bits signed offset
3884 // Aligned - 12 bits unsigned offset shifted
3885 Register base = sp;
3886 if ((offset & (size-1)) && offset >= (1<<8)) {
3887 add(tmp, base, offset & ((1<<12)-1));
3888 base = tmp;
3889 offset &= -1u<<12;
3890 }
3891
3892 if (offset >= (1<<12) * size) {
3893 add(tmp, base, offset & (((1<<12)-1)<<12));
3894 base = tmp;
3895 offset &= ~(((1<<12)-1)<<12);
3896 }
3897
3898 return Address(base, offset);
3899 }
3900
3901 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) {
3902 assert(offset >= 0, "spill to negative address?");
3903
3904 Register base = sp;
3905
3906 // An immediate offset in the range 0 to 255 which is multiplied
3907 // by the current vector or predicate register size in bytes.
3908 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) {
3909 return Address(base, offset / sve_reg_size_in_bytes);
3910 }
3911
3912 add(tmp, base, offset);
3913 return Address(tmp);
3914 }
3915
3916 // Checks whether offset is aligned.
3917 // Returns true if it is, else false.
3918 bool MacroAssembler::merge_alignment_check(Register base,
3919 size_t size,
3920 int64_t cur_offset,
3921 int64_t prev_offset) const {
3922 if (AvoidUnalignedAccesses) {
3923 if (base == sp) {
3924 // Checks whether low offset if aligned to pair of registers.
3925 int64_t pair_mask = size * 2 - 1;
3926 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3927 return (offset & pair_mask) == 0;
3928 } else { // If base is not sp, we can't guarantee the access is aligned.
3929 return false;
3930 }
3931 } else {
3932 int64_t mask = size - 1;
3933 // Load/store pair instruction only supports element size aligned offset.
3934 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
3935 }
3936 }
3937
3938 // Checks whether current and previous loads/stores can be merged.
3939 // Returns true if it can be merged, else false.
3940 bool MacroAssembler::ldst_can_merge(Register rt,
3941 const Address &adr,
3942 size_t cur_size_in_bytes,
3943 bool is_store) const {
3944 address prev = pc() - NativeInstruction::instruction_size;
3945 address last = code()->last_insn();
3946
3947 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) {
3948 return false;
3949 }
3950
3951 if (adr.getMode() != Address::base_plus_offset || prev != last) {
3952 return false;
3953 }
3954
3955 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3956 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
3957
3958 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
3959 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
3960
3961 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
3962 return false;
3963 }
3964
3965 int64_t max_offset = 63 * prev_size_in_bytes;
3966 int64_t min_offset = -64 * prev_size_in_bytes;
3967
3968 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
3969
3970 // Only same base can be merged.
3971 if (adr.base() != prev_ldst->base()) {
3972 return false;
3973 }
3974
3975 int64_t cur_offset = adr.offset();
3976 int64_t prev_offset = prev_ldst->offset();
3977 size_t diff = abs(cur_offset - prev_offset);
3978 if (diff != prev_size_in_bytes) {
3979 return false;
3980 }
3981
3982 // Following cases can not be merged:
3983 // ldr x2, [x2, #8]
3984 // ldr x3, [x2, #16]
3985 // or:
3986 // ldr x2, [x3, #8]
3987 // ldr x2, [x3, #16]
3988 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
3989 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
3990 return false;
3991 }
3992
3993 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3994 // Offset range must be in ldp/stp instruction's range.
3995 if (low_offset > max_offset || low_offset < min_offset) {
3996 return false;
3997 }
3998
3999 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
4000 return true;
4001 }
4002
4003 return false;
4004 }
4005
4006 // Merge current load/store with previous load/store into ldp/stp.
4007 void MacroAssembler::merge_ldst(Register rt,
4008 const Address &adr,
4009 size_t cur_size_in_bytes,
4010 bool is_store) {
4011
4012 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
4013
4014 Register rt_low, rt_high;
4015 address prev = pc() - NativeInstruction::instruction_size;
4016 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
4017
4018 int64_t offset;
4019
4020 if (adr.offset() < prev_ldst->offset()) {
4021 offset = adr.offset();
4022 rt_low = rt;
4023 rt_high = prev_ldst->target();
4024 } else {
4025 offset = prev_ldst->offset();
4026 rt_low = prev_ldst->target();
4027 rt_high = rt;
4028 }
4029
4030 Address adr_p = Address(prev_ldst->base(), offset);
4031 // Overwrite previous generated binary.
4032 code_section()->set_end(prev);
4033
4034 const size_t sz = prev_ldst->size_in_bytes();
4035 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
4036 if (!is_store) {
4037 BLOCK_COMMENT("merged ldr pair");
4038 if (sz == 8) {
4039 ldp(rt_low, rt_high, adr_p);
4040 } else {
4041 ldpw(rt_low, rt_high, adr_p);
4042 }
4043 } else {
4044 BLOCK_COMMENT("merged str pair");
4045 if (sz == 8) {
4046 stp(rt_low, rt_high, adr_p);
4047 } else {
4048 stpw(rt_low, rt_high, adr_p);
4049 }
4050 }
4051 }
4052
4053 /**
4054 * Multiply 64 bit by 64 bit first loop.
4055 */
4056 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
4057 Register y, Register y_idx, Register z,
4058 Register carry, Register product,
4059 Register idx, Register kdx) {
4060 //
4061 // jlong carry, x[], y[], z[];
4062 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4063 // huge_128 product = y[idx] * x[xstart] + carry;
4064 // z[kdx] = (jlong)product;
4065 // carry = (jlong)(product >>> 64);
4066 // }
4067 // z[xstart] = carry;
4068 //
4069
4070 Label L_first_loop, L_first_loop_exit;
4071 Label L_one_x, L_one_y, L_multiply;
4072
4073 subsw(xstart, xstart, 1);
4074 br(Assembler::MI, L_one_x);
4075
4076 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
4077 ldr(x_xstart, Address(rscratch1));
4078 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
4079
4080 bind(L_first_loop);
4081 subsw(idx, idx, 1);
4082 br(Assembler::MI, L_first_loop_exit);
4083 subsw(idx, idx, 1);
4084 br(Assembler::MI, L_one_y);
4085 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4086 ldr(y_idx, Address(rscratch1));
4087 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
4088 bind(L_multiply);
4089
4090 // AArch64 has a multiply-accumulate instruction that we can't use
4091 // here because it has no way to process carries, so we have to use
4092 // separate add and adc instructions. Bah.
4093 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
4094 mul(product, x_xstart, y_idx);
4095 adds(product, product, carry);
4096 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
4097
4098 subw(kdx, kdx, 2);
4099 ror(product, product, 32); // back to big-endian
4100 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
4101
4102 b(L_first_loop);
4103
4104 bind(L_one_y);
4105 ldrw(y_idx, Address(y, 0));
4106 b(L_multiply);
4107
4108 bind(L_one_x);
4109 ldrw(x_xstart, Address(x, 0));
4110 b(L_first_loop);
4111
4112 bind(L_first_loop_exit);
4113 }
4114
4115 /**
4116 * Multiply 128 bit by 128. Unrolled inner loop.
4117 *
4118 */
4119 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
4120 Register carry, Register carry2,
4121 Register idx, Register jdx,
4122 Register yz_idx1, Register yz_idx2,
4123 Register tmp, Register tmp3, Register tmp4,
4124 Register tmp6, Register product_hi) {
4125
4126 // jlong carry, x[], y[], z[];
4127 // int kdx = ystart+1;
4128 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
4129 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
4130 // jlong carry2 = (jlong)(tmp3 >>> 64);
4131 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
4132 // carry = (jlong)(tmp4 >>> 64);
4133 // z[kdx+idx+1] = (jlong)tmp3;
4134 // z[kdx+idx] = (jlong)tmp4;
4135 // }
4136 // idx += 2;
4137 // if (idx > 0) {
4138 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
4139 // z[kdx+idx] = (jlong)yz_idx1;
4140 // carry = (jlong)(yz_idx1 >>> 64);
4141 // }
4142 //
4143
4144 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
4145
4146 lsrw(jdx, idx, 2);
4147
4148 bind(L_third_loop);
4149
4150 subsw(jdx, jdx, 1);
4151 br(Assembler::MI, L_third_loop_exit);
4152 subw(idx, idx, 4);
4153
4154 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4155
4156 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
4157
4158 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4159
4160 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
4161 ror(yz_idx2, yz_idx2, 32);
4162
4163 ldp(rscratch2, rscratch1, Address(tmp6, 0));
4164
4165 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4166 umulh(tmp4, product_hi, yz_idx1);
4167
4168 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
4169 ror(rscratch2, rscratch2, 32);
4170
4171 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
4172 umulh(carry2, product_hi, yz_idx2);
4173
4174 // propagate sum of both multiplications into carry:tmp4:tmp3
4175 adds(tmp3, tmp3, carry);
4176 adc(tmp4, tmp4, zr);
4177 adds(tmp3, tmp3, rscratch1);
4178 adcs(tmp4, tmp4, tmp);
4179 adc(carry, carry2, zr);
4180 adds(tmp4, tmp4, rscratch2);
4181 adc(carry, carry, zr);
4182
4183 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
4184 ror(tmp4, tmp4, 32);
4185 stp(tmp4, tmp3, Address(tmp6, 0));
4186
4187 b(L_third_loop);
4188 bind (L_third_loop_exit);
4189
4190 andw (idx, idx, 0x3);
4191 cbz(idx, L_post_third_loop_done);
4192
4193 Label L_check_1;
4194 subsw(idx, idx, 2);
4195 br(Assembler::MI, L_check_1);
4196
4197 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4198 ldr(yz_idx1, Address(rscratch1, 0));
4199 ror(yz_idx1, yz_idx1, 32);
4200 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4201 umulh(tmp4, product_hi, yz_idx1);
4202 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4203 ldr(yz_idx2, Address(rscratch1, 0));
4204 ror(yz_idx2, yz_idx2, 32);
4205
4206 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
4207
4208 ror(tmp3, tmp3, 32);
4209 str(tmp3, Address(rscratch1, 0));
4210
4211 bind (L_check_1);
4212
4213 andw (idx, idx, 0x1);
4214 subsw(idx, idx, 1);
4215 br(Assembler::MI, L_post_third_loop_done);
4216 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4217 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
4218 umulh(carry2, tmp4, product_hi);
4219 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4220
4221 add2_with_carry(carry2, tmp3, tmp4, carry);
4222
4223 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4224 extr(carry, carry2, tmp3, 32);
4225
4226 bind(L_post_third_loop_done);
4227 }
4228
4229 /**
4230 * Code for BigInteger::multiplyToLen() intrinsic.
4231 *
4232 * r0: x
4233 * r1: xlen
4234 * r2: y
4235 * r3: ylen
4236 * r4: z
4237 * r5: tmp0
4238 * r10: tmp1
4239 * r11: tmp2
4240 * r12: tmp3
4241 * r13: tmp4
4242 * r14: tmp5
4243 * r15: tmp6
4244 * r16: tmp7
4245 *
4246 */
4247 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
4248 Register z, Register tmp0,
4249 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
4250 Register tmp5, Register tmp6, Register product_hi) {
4251
4252 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, product_hi);
4253
4254 const Register idx = tmp1;
4255 const Register kdx = tmp2;
4256 const Register xstart = tmp3;
4257
4258 const Register y_idx = tmp4;
4259 const Register carry = tmp5;
4260 const Register product = xlen;
4261 const Register x_xstart = tmp0;
4262
4263 // First Loop.
4264 //
4265 // final static long LONG_MASK = 0xffffffffL;
4266 // int xstart = xlen - 1;
4267 // int ystart = ylen - 1;
4268 // long carry = 0;
4269 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4270 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
4271 // z[kdx] = (int)product;
4272 // carry = product >>> 32;
4273 // }
4274 // z[xstart] = (int)carry;
4275 //
4276
4277 movw(idx, ylen); // idx = ylen;
4278 addw(kdx, xlen, ylen); // kdx = xlen+ylen;
4279 mov(carry, zr); // carry = 0;
4280
4281 Label L_done;
4282
4283 movw(xstart, xlen);
4284 subsw(xstart, xstart, 1);
4285 br(Assembler::MI, L_done);
4286
4287 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
4288
4289 Label L_second_loop;
4290 cbzw(kdx, L_second_loop);
4291
4292 Label L_carry;
4293 subw(kdx, kdx, 1);
4294 cbzw(kdx, L_carry);
4295
4296 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4297 lsr(carry, carry, 32);
4298 subw(kdx, kdx, 1);
4299
4300 bind(L_carry);
4301 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4302
4303 // Second and third (nested) loops.
4304 //
4305 // for (int i = xstart-1; i >= 0; i--) { // Second loop
4306 // carry = 0;
4307 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
4308 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
4309 // (z[k] & LONG_MASK) + carry;
4310 // z[k] = (int)product;
4311 // carry = product >>> 32;
4312 // }
4313 // z[i] = (int)carry;
4314 // }
4315 //
4316 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
4317
4318 const Register jdx = tmp1;
4319
4320 bind(L_second_loop);
4321 mov(carry, zr); // carry = 0;
4322 movw(jdx, ylen); // j = ystart+1
4323
4324 subsw(xstart, xstart, 1); // i = xstart-1;
4325 br(Assembler::MI, L_done);
4326
4327 str(z, Address(pre(sp, -4 * wordSize)));
4328
4329 Label L_last_x;
4330 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
4331 subsw(xstart, xstart, 1); // i = xstart-1;
4332 br(Assembler::MI, L_last_x);
4333
4334 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
4335 ldr(product_hi, Address(rscratch1));
4336 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
4337
4338 Label L_third_loop_prologue;
4339 bind(L_third_loop_prologue);
4340
4341 str(ylen, Address(sp, wordSize));
4342 stp(x, xstart, Address(sp, 2 * wordSize));
4343 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
4344 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
4345 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
4346 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
4347
4348 addw(tmp3, xlen, 1);
4349 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4350 subsw(tmp3, tmp3, 1);
4351 br(Assembler::MI, L_done);
4352
4353 lsr(carry, carry, 32);
4354 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4355 b(L_second_loop);
4356
4357 // Next infrequent code is moved outside loops.
4358 bind(L_last_x);
4359 ldrw(product_hi, Address(x, 0));
4360 b(L_third_loop_prologue);
4361
4362 bind(L_done);
4363 }
4364
4365 // Code for BigInteger::mulAdd intrinsic
4366 // out = r0
4367 // in = r1
4368 // offset = r2 (already out.length-offset)
4369 // len = r3
4370 // k = r4
4371 //
4372 // pseudo code from java implementation:
4373 // carry = 0;
4374 // offset = out.length-offset - 1;
4375 // for (int j=len-1; j >= 0; j--) {
4376 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
4377 // out[offset--] = (int)product;
4378 // carry = product >>> 32;
4379 // }
4380 // return (int)carry;
4381 void MacroAssembler::mul_add(Register out, Register in, Register offset,
4382 Register len, Register k) {
4383 Label LOOP, END;
4384 // pre-loop
4385 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
4386 csel(out, zr, out, Assembler::EQ);
4387 br(Assembler::EQ, END);
4388 add(in, in, len, LSL, 2); // in[j+1] address
4389 add(offset, out, offset, LSL, 2); // out[offset + 1] address
4390 mov(out, zr); // used to keep carry now
4391 BIND(LOOP);
4392 ldrw(rscratch1, Address(pre(in, -4)));
4393 madd(rscratch1, rscratch1, k, out);
4394 ldrw(rscratch2, Address(pre(offset, -4)));
4395 add(rscratch1, rscratch1, rscratch2);
4396 strw(rscratch1, Address(offset));
4397 lsr(out, rscratch1, 32);
4398 subs(len, len, 1);
4399 br(Assembler::NE, LOOP);
4400 BIND(END);
4401 }
4402
4403 /**
4404 * Emits code to update CRC-32 with a byte value according to constants in table
4405 *
4406 * @param [in,out]crc Register containing the crc.
4407 * @param [in]val Register containing the byte to fold into the CRC.
4408 * @param [in]table Register containing the table of crc constants.
4409 *
4410 * uint32_t crc;
4411 * val = crc_table[(val ^ crc) & 0xFF];
4412 * crc = val ^ (crc >> 8);
4413 *
4414 */
4415 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4416 eor(val, val, crc);
4417 andr(val, val, 0xff);
4418 ldrw(val, Address(table, val, Address::lsl(2)));
4419 eor(crc, val, crc, Assembler::LSR, 8);
4420 }
4421
4422 /**
4423 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
4424 *
4425 * @param [in,out]crc Register containing the crc.
4426 * @param [in]v Register containing the 32-bit to fold into the CRC.
4427 * @param [in]table0 Register containing table 0 of crc constants.
4428 * @param [in]table1 Register containing table 1 of crc constants.
4429 * @param [in]table2 Register containing table 2 of crc constants.
4430 * @param [in]table3 Register containing table 3 of crc constants.
4431 *
4432 * uint32_t crc;
4433 * v = crc ^ v
4434 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
4435 *
4436 */
4437 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
4438 Register table0, Register table1, Register table2, Register table3,
4439 bool upper) {
4440 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
4441 uxtb(tmp, v);
4442 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
4443 ubfx(tmp, v, 8, 8);
4444 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
4445 eor(crc, crc, tmp);
4446 ubfx(tmp, v, 16, 8);
4447 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
4448 eor(crc, crc, tmp);
4449 ubfx(tmp, v, 24, 8);
4450 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
4451 eor(crc, crc, tmp);
4452 }
4453
4454 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf,
4455 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4456 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4457 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4458
4459 subs(tmp0, len, 384);
4460 mvnw(crc, crc);
4461 br(Assembler::GE, CRC_by128_pre);
4462 BIND(CRC_less128);
4463 subs(len, len, 32);
4464 br(Assembler::GE, CRC_by32_loop);
4465 BIND(CRC_less32);
4466 adds(len, len, 32 - 4);
4467 br(Assembler::GE, CRC_by4_loop);
4468 adds(len, len, 4);
4469 br(Assembler::GT, CRC_by1_loop);
4470 b(L_exit);
4471
4472 BIND(CRC_by32_loop);
4473 ldp(tmp0, tmp1, Address(buf));
4474 crc32x(crc, crc, tmp0);
4475 ldp(tmp2, tmp3, Address(buf, 16));
4476 crc32x(crc, crc, tmp1);
4477 add(buf, buf, 32);
4478 crc32x(crc, crc, tmp2);
4479 subs(len, len, 32);
4480 crc32x(crc, crc, tmp3);
4481 br(Assembler::GE, CRC_by32_loop);
4482 cmn(len, (u1)32);
4483 br(Assembler::NE, CRC_less32);
4484 b(L_exit);
4485
4486 BIND(CRC_by4_loop);
4487 ldrw(tmp0, Address(post(buf, 4)));
4488 subs(len, len, 4);
4489 crc32w(crc, crc, tmp0);
4490 br(Assembler::GE, CRC_by4_loop);
4491 adds(len, len, 4);
4492 br(Assembler::LE, L_exit);
4493 BIND(CRC_by1_loop);
4494 ldrb(tmp0, Address(post(buf, 1)));
4495 subs(len, len, 1);
4496 crc32b(crc, crc, tmp0);
4497 br(Assembler::GT, CRC_by1_loop);
4498 b(L_exit);
4499
4500 BIND(CRC_by128_pre);
4501 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4502 4*256*sizeof(juint) + 8*sizeof(juint));
4503 mov(crc, 0);
4504 crc32x(crc, crc, tmp0);
4505 crc32x(crc, crc, tmp1);
4506
4507 cbnz(len, CRC_less128);
4508
4509 BIND(L_exit);
4510 mvnw(crc, crc);
4511 }
4512
4513 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
4514 Register len, Register tmp0, Register tmp1, Register tmp2,
4515 Register tmp3) {
4516 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4517 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4518
4519 mvnw(crc, crc);
4520
4521 subs(len, len, 128);
4522 br(Assembler::GE, CRC_by64_pre);
4523 BIND(CRC_less64);
4524 adds(len, len, 128-32);
4525 br(Assembler::GE, CRC_by32_loop);
4526 BIND(CRC_less32);
4527 adds(len, len, 32-4);
4528 br(Assembler::GE, CRC_by4_loop);
4529 adds(len, len, 4);
4530 br(Assembler::GT, CRC_by1_loop);
4531 b(L_exit);
4532
4533 BIND(CRC_by32_loop);
4534 ldp(tmp0, tmp1, Address(post(buf, 16)));
4535 subs(len, len, 32);
4536 crc32x(crc, crc, tmp0);
4537 ldr(tmp2, Address(post(buf, 8)));
4538 crc32x(crc, crc, tmp1);
4539 ldr(tmp3, Address(post(buf, 8)));
4540 crc32x(crc, crc, tmp2);
4541 crc32x(crc, crc, tmp3);
4542 br(Assembler::GE, CRC_by32_loop);
4543 cmn(len, (u1)32);
4544 br(Assembler::NE, CRC_less32);
4545 b(L_exit);
4546
4547 BIND(CRC_by4_loop);
4548 ldrw(tmp0, Address(post(buf, 4)));
4549 subs(len, len, 4);
4550 crc32w(crc, crc, tmp0);
4551 br(Assembler::GE, CRC_by4_loop);
4552 adds(len, len, 4);
4553 br(Assembler::LE, L_exit);
4554 BIND(CRC_by1_loop);
4555 ldrb(tmp0, Address(post(buf, 1)));
4556 subs(len, len, 1);
4557 crc32b(crc, crc, tmp0);
4558 br(Assembler::GT, CRC_by1_loop);
4559 b(L_exit);
4560
4561 BIND(CRC_by64_pre);
4562 sub(buf, buf, 8);
4563 ldp(tmp0, tmp1, Address(buf, 8));
4564 crc32x(crc, crc, tmp0);
4565 ldr(tmp2, Address(buf, 24));
4566 crc32x(crc, crc, tmp1);
4567 ldr(tmp3, Address(buf, 32));
4568 crc32x(crc, crc, tmp2);
4569 ldr(tmp0, Address(buf, 40));
4570 crc32x(crc, crc, tmp3);
4571 ldr(tmp1, Address(buf, 48));
4572 crc32x(crc, crc, tmp0);
4573 ldr(tmp2, Address(buf, 56));
4574 crc32x(crc, crc, tmp1);
4575 ldr(tmp3, Address(pre(buf, 64)));
4576
4577 b(CRC_by64_loop);
4578
4579 align(CodeEntryAlignment);
4580 BIND(CRC_by64_loop);
4581 subs(len, len, 64);
4582 crc32x(crc, crc, tmp2);
4583 ldr(tmp0, Address(buf, 8));
4584 crc32x(crc, crc, tmp3);
4585 ldr(tmp1, Address(buf, 16));
4586 crc32x(crc, crc, tmp0);
4587 ldr(tmp2, Address(buf, 24));
4588 crc32x(crc, crc, tmp1);
4589 ldr(tmp3, Address(buf, 32));
4590 crc32x(crc, crc, tmp2);
4591 ldr(tmp0, Address(buf, 40));
4592 crc32x(crc, crc, tmp3);
4593 ldr(tmp1, Address(buf, 48));
4594 crc32x(crc, crc, tmp0);
4595 ldr(tmp2, Address(buf, 56));
4596 crc32x(crc, crc, tmp1);
4597 ldr(tmp3, Address(pre(buf, 64)));
4598 br(Assembler::GE, CRC_by64_loop);
4599
4600 // post-loop
4601 crc32x(crc, crc, tmp2);
4602 crc32x(crc, crc, tmp3);
4603
4604 sub(len, len, 64);
4605 add(buf, buf, 8);
4606 cmn(len, (u1)128);
4607 br(Assembler::NE, CRC_less64);
4608 BIND(L_exit);
4609 mvnw(crc, crc);
4610 }
4611
4612 /**
4613 * @param crc register containing existing CRC (32-bit)
4614 * @param buf register pointing to input byte buffer (byte*)
4615 * @param len register containing number of bytes
4616 * @param table register that will contain address of CRC table
4617 * @param tmp scratch register
4618 */
4619 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
4620 Register table0, Register table1, Register table2, Register table3,
4621 Register tmp, Register tmp2, Register tmp3) {
4622 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
4623
4624 if (UseCryptoPmullForCRC32) {
4625 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4626 return;
4627 }
4628
4629 if (UseCRC32) {
4630 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
4631 return;
4632 }
4633
4634 mvnw(crc, crc);
4635
4636 {
4637 uint64_t offset;
4638 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4639 add(table0, table0, offset);
4640 }
4641 add(table1, table0, 1*256*sizeof(juint));
4642 add(table2, table0, 2*256*sizeof(juint));
4643 add(table3, table0, 3*256*sizeof(juint));
4644
4645 { // Neon code start
4646 cmp(len, (u1)64);
4647 br(Assembler::LT, L_by16);
4648 eor(v16, T16B, v16, v16);
4649
4650 Label L_fold;
4651
4652 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
4653
4654 ld1(v0, v1, T2D, post(buf, 32));
4655 ld1r(v4, T2D, post(tmp, 8));
4656 ld1r(v5, T2D, post(tmp, 8));
4657 ld1r(v6, T2D, post(tmp, 8));
4658 ld1r(v7, T2D, post(tmp, 8));
4659 mov(v16, S, 0, crc);
4660
4661 eor(v0, T16B, v0, v16);
4662 sub(len, len, 64);
4663
4664 BIND(L_fold);
4665 pmull(v22, T8H, v0, v5, T8B);
4666 pmull(v20, T8H, v0, v7, T8B);
4667 pmull(v23, T8H, v0, v4, T8B);
4668 pmull(v21, T8H, v0, v6, T8B);
4669
4670 pmull2(v18, T8H, v0, v5, T16B);
4671 pmull2(v16, T8H, v0, v7, T16B);
4672 pmull2(v19, T8H, v0, v4, T16B);
4673 pmull2(v17, T8H, v0, v6, T16B);
4674
4675 uzp1(v24, T8H, v20, v22);
4676 uzp2(v25, T8H, v20, v22);
4677 eor(v20, T16B, v24, v25);
4678
4679 uzp1(v26, T8H, v16, v18);
4680 uzp2(v27, T8H, v16, v18);
4681 eor(v16, T16B, v26, v27);
4682
4683 ushll2(v22, T4S, v20, T8H, 8);
4684 ushll(v20, T4S, v20, T4H, 8);
4685
4686 ushll2(v18, T4S, v16, T8H, 8);
4687 ushll(v16, T4S, v16, T4H, 8);
4688
4689 eor(v22, T16B, v23, v22);
4690 eor(v18, T16B, v19, v18);
4691 eor(v20, T16B, v21, v20);
4692 eor(v16, T16B, v17, v16);
4693
4694 uzp1(v17, T2D, v16, v20);
4695 uzp2(v21, T2D, v16, v20);
4696 eor(v17, T16B, v17, v21);
4697
4698 ushll2(v20, T2D, v17, T4S, 16);
4699 ushll(v16, T2D, v17, T2S, 16);
4700
4701 eor(v20, T16B, v20, v22);
4702 eor(v16, T16B, v16, v18);
4703
4704 uzp1(v17, T2D, v20, v16);
4705 uzp2(v21, T2D, v20, v16);
4706 eor(v28, T16B, v17, v21);
4707
4708 pmull(v22, T8H, v1, v5, T8B);
4709 pmull(v20, T8H, v1, v7, T8B);
4710 pmull(v23, T8H, v1, v4, T8B);
4711 pmull(v21, T8H, v1, v6, T8B);
4712
4713 pmull2(v18, T8H, v1, v5, T16B);
4714 pmull2(v16, T8H, v1, v7, T16B);
4715 pmull2(v19, T8H, v1, v4, T16B);
4716 pmull2(v17, T8H, v1, v6, T16B);
4717
4718 ld1(v0, v1, T2D, post(buf, 32));
4719
4720 uzp1(v24, T8H, v20, v22);
4721 uzp2(v25, T8H, v20, v22);
4722 eor(v20, T16B, v24, v25);
4723
4724 uzp1(v26, T8H, v16, v18);
4725 uzp2(v27, T8H, v16, v18);
4726 eor(v16, T16B, v26, v27);
4727
4728 ushll2(v22, T4S, v20, T8H, 8);
4729 ushll(v20, T4S, v20, T4H, 8);
4730
4731 ushll2(v18, T4S, v16, T8H, 8);
4732 ushll(v16, T4S, v16, T4H, 8);
4733
4734 eor(v22, T16B, v23, v22);
4735 eor(v18, T16B, v19, v18);
4736 eor(v20, T16B, v21, v20);
4737 eor(v16, T16B, v17, v16);
4738
4739 uzp1(v17, T2D, v16, v20);
4740 uzp2(v21, T2D, v16, v20);
4741 eor(v16, T16B, v17, v21);
4742
4743 ushll2(v20, T2D, v16, T4S, 16);
4744 ushll(v16, T2D, v16, T2S, 16);
4745
4746 eor(v20, T16B, v22, v20);
4747 eor(v16, T16B, v16, v18);
4748
4749 uzp1(v17, T2D, v20, v16);
4750 uzp2(v21, T2D, v20, v16);
4751 eor(v20, T16B, v17, v21);
4752
4753 shl(v16, T2D, v28, 1);
4754 shl(v17, T2D, v20, 1);
4755
4756 eor(v0, T16B, v0, v16);
4757 eor(v1, T16B, v1, v17);
4758
4759 subs(len, len, 32);
4760 br(Assembler::GE, L_fold);
4761
4762 mov(crc, 0);
4763 mov(tmp, v0, D, 0);
4764 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4765 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4766 mov(tmp, v0, D, 1);
4767 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4768 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4769 mov(tmp, v1, D, 0);
4770 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4771 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4772 mov(tmp, v1, D, 1);
4773 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4774 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4775
4776 add(len, len, 32);
4777 } // Neon code end
4778
4779 BIND(L_by16);
4780 subs(len, len, 16);
4781 br(Assembler::GE, L_by16_loop);
4782 adds(len, len, 16-4);
4783 br(Assembler::GE, L_by4_loop);
4784 adds(len, len, 4);
4785 br(Assembler::GT, L_by1_loop);
4786 b(L_exit);
4787
4788 BIND(L_by4_loop);
4789 ldrw(tmp, Address(post(buf, 4)));
4790 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
4791 subs(len, len, 4);
4792 br(Assembler::GE, L_by4_loop);
4793 adds(len, len, 4);
4794 br(Assembler::LE, L_exit);
4795 BIND(L_by1_loop);
4796 subs(len, len, 1);
4797 ldrb(tmp, Address(post(buf, 1)));
4798 update_byte_crc32(crc, tmp, table0);
4799 br(Assembler::GT, L_by1_loop);
4800 b(L_exit);
4801
4802 align(CodeEntryAlignment);
4803 BIND(L_by16_loop);
4804 subs(len, len, 16);
4805 ldp(tmp, tmp3, Address(post(buf, 16)));
4806 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4807 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4808 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
4809 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
4810 br(Assembler::GE, L_by16_loop);
4811 adds(len, len, 16-4);
4812 br(Assembler::GE, L_by4_loop);
4813 adds(len, len, 4);
4814 br(Assembler::GT, L_by1_loop);
4815 BIND(L_exit);
4816 mvnw(crc, crc);
4817 }
4818
4819 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
4820 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4821 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4822 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4823
4824 subs(tmp0, len, 384);
4825 br(Assembler::GE, CRC_by128_pre);
4826 BIND(CRC_less128);
4827 subs(len, len, 32);
4828 br(Assembler::GE, CRC_by32_loop);
4829 BIND(CRC_less32);
4830 adds(len, len, 32 - 4);
4831 br(Assembler::GE, CRC_by4_loop);
4832 adds(len, len, 4);
4833 br(Assembler::GT, CRC_by1_loop);
4834 b(L_exit);
4835
4836 BIND(CRC_by32_loop);
4837 ldp(tmp0, tmp1, Address(buf));
4838 crc32cx(crc, crc, tmp0);
4839 ldr(tmp2, Address(buf, 16));
4840 crc32cx(crc, crc, tmp1);
4841 ldr(tmp3, Address(buf, 24));
4842 crc32cx(crc, crc, tmp2);
4843 add(buf, buf, 32);
4844 subs(len, len, 32);
4845 crc32cx(crc, crc, tmp3);
4846 br(Assembler::GE, CRC_by32_loop);
4847 cmn(len, (u1)32);
4848 br(Assembler::NE, CRC_less32);
4849 b(L_exit);
4850
4851 BIND(CRC_by4_loop);
4852 ldrw(tmp0, Address(post(buf, 4)));
4853 subs(len, len, 4);
4854 crc32cw(crc, crc, tmp0);
4855 br(Assembler::GE, CRC_by4_loop);
4856 adds(len, len, 4);
4857 br(Assembler::LE, L_exit);
4858 BIND(CRC_by1_loop);
4859 ldrb(tmp0, Address(post(buf, 1)));
4860 subs(len, len, 1);
4861 crc32cb(crc, crc, tmp0);
4862 br(Assembler::GT, CRC_by1_loop);
4863 b(L_exit);
4864
4865 BIND(CRC_by128_pre);
4866 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4867 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50);
4868 mov(crc, 0);
4869 crc32cx(crc, crc, tmp0);
4870 crc32cx(crc, crc, tmp1);
4871
4872 cbnz(len, CRC_less128);
4873
4874 BIND(L_exit);
4875 }
4876
4877 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
4878 Register len, Register tmp0, Register tmp1, Register tmp2,
4879 Register tmp3) {
4880 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4881 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4882
4883 subs(len, len, 128);
4884 br(Assembler::GE, CRC_by64_pre);
4885 BIND(CRC_less64);
4886 adds(len, len, 128-32);
4887 br(Assembler::GE, CRC_by32_loop);
4888 BIND(CRC_less32);
4889 adds(len, len, 32-4);
4890 br(Assembler::GE, CRC_by4_loop);
4891 adds(len, len, 4);
4892 br(Assembler::GT, CRC_by1_loop);
4893 b(L_exit);
4894
4895 BIND(CRC_by32_loop);
4896 ldp(tmp0, tmp1, Address(post(buf, 16)));
4897 subs(len, len, 32);
4898 crc32cx(crc, crc, tmp0);
4899 ldr(tmp2, Address(post(buf, 8)));
4900 crc32cx(crc, crc, tmp1);
4901 ldr(tmp3, Address(post(buf, 8)));
4902 crc32cx(crc, crc, tmp2);
4903 crc32cx(crc, crc, tmp3);
4904 br(Assembler::GE, CRC_by32_loop);
4905 cmn(len, (u1)32);
4906 br(Assembler::NE, CRC_less32);
4907 b(L_exit);
4908
4909 BIND(CRC_by4_loop);
4910 ldrw(tmp0, Address(post(buf, 4)));
4911 subs(len, len, 4);
4912 crc32cw(crc, crc, tmp0);
4913 br(Assembler::GE, CRC_by4_loop);
4914 adds(len, len, 4);
4915 br(Assembler::LE, L_exit);
4916 BIND(CRC_by1_loop);
4917 ldrb(tmp0, Address(post(buf, 1)));
4918 subs(len, len, 1);
4919 crc32cb(crc, crc, tmp0);
4920 br(Assembler::GT, CRC_by1_loop);
4921 b(L_exit);
4922
4923 BIND(CRC_by64_pre);
4924 sub(buf, buf, 8);
4925 ldp(tmp0, tmp1, Address(buf, 8));
4926 crc32cx(crc, crc, tmp0);
4927 ldr(tmp2, Address(buf, 24));
4928 crc32cx(crc, crc, tmp1);
4929 ldr(tmp3, Address(buf, 32));
4930 crc32cx(crc, crc, tmp2);
4931 ldr(tmp0, Address(buf, 40));
4932 crc32cx(crc, crc, tmp3);
4933 ldr(tmp1, Address(buf, 48));
4934 crc32cx(crc, crc, tmp0);
4935 ldr(tmp2, Address(buf, 56));
4936 crc32cx(crc, crc, tmp1);
4937 ldr(tmp3, Address(pre(buf, 64)));
4938
4939 b(CRC_by64_loop);
4940
4941 align(CodeEntryAlignment);
4942 BIND(CRC_by64_loop);
4943 subs(len, len, 64);
4944 crc32cx(crc, crc, tmp2);
4945 ldr(tmp0, Address(buf, 8));
4946 crc32cx(crc, crc, tmp3);
4947 ldr(tmp1, Address(buf, 16));
4948 crc32cx(crc, crc, tmp0);
4949 ldr(tmp2, Address(buf, 24));
4950 crc32cx(crc, crc, tmp1);
4951 ldr(tmp3, Address(buf, 32));
4952 crc32cx(crc, crc, tmp2);
4953 ldr(tmp0, Address(buf, 40));
4954 crc32cx(crc, crc, tmp3);
4955 ldr(tmp1, Address(buf, 48));
4956 crc32cx(crc, crc, tmp0);
4957 ldr(tmp2, Address(buf, 56));
4958 crc32cx(crc, crc, tmp1);
4959 ldr(tmp3, Address(pre(buf, 64)));
4960 br(Assembler::GE, CRC_by64_loop);
4961
4962 // post-loop
4963 crc32cx(crc, crc, tmp2);
4964 crc32cx(crc, crc, tmp3);
4965
4966 sub(len, len, 64);
4967 add(buf, buf, 8);
4968 cmn(len, (u1)128);
4969 br(Assembler::NE, CRC_less64);
4970 BIND(L_exit);
4971 }
4972
4973 /**
4974 * @param crc register containing existing CRC (32-bit)
4975 * @param buf register pointing to input byte buffer (byte*)
4976 * @param len register containing number of bytes
4977 * @param table register that will contain address of CRC table
4978 * @param tmp scratch register
4979 */
4980 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
4981 Register table0, Register table1, Register table2, Register table3,
4982 Register tmp, Register tmp2, Register tmp3) {
4983 if (UseCryptoPmullForCRC32) {
4984 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4985 } else {
4986 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
4987 }
4988 }
4989
4990 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
4991 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) {
4992 Label CRC_by128_loop;
4993 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4994
4995 sub(len, len, 256);
4996 Register table = tmp0;
4997 {
4998 uint64_t offset;
4999 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset);
5000 add(table, table, offset);
5001 }
5002 add(table, table, table_offset);
5003
5004 // Registers v0..v7 are used as data registers.
5005 // Registers v16..v31 are used as tmp registers.
5006 sub(buf, buf, 0x10);
5007 ldrq(v0, Address(buf, 0x10));
5008 ldrq(v1, Address(buf, 0x20));
5009 ldrq(v2, Address(buf, 0x30));
5010 ldrq(v3, Address(buf, 0x40));
5011 ldrq(v4, Address(buf, 0x50));
5012 ldrq(v5, Address(buf, 0x60));
5013 ldrq(v6, Address(buf, 0x70));
5014 ldrq(v7, Address(pre(buf, 0x80)));
5015
5016 movi(v31, T4S, 0);
5017 mov(v31, S, 0, crc);
5018 eor(v0, T16B, v0, v31);
5019
5020 // Register v16 contains constants from the crc table.
5021 ldrq(v16, Address(table));
5022 b(CRC_by128_loop);
5023
5024 align(OptoLoopAlignment);
5025 BIND(CRC_by128_loop);
5026 pmull (v17, T1Q, v0, v16, T1D);
5027 pmull2(v18, T1Q, v0, v16, T2D);
5028 ldrq(v0, Address(buf, 0x10));
5029 eor3(v0, T16B, v17, v18, v0);
5030
5031 pmull (v19, T1Q, v1, v16, T1D);
5032 pmull2(v20, T1Q, v1, v16, T2D);
5033 ldrq(v1, Address(buf, 0x20));
5034 eor3(v1, T16B, v19, v20, v1);
5035
5036 pmull (v21, T1Q, v2, v16, T1D);
5037 pmull2(v22, T1Q, v2, v16, T2D);
5038 ldrq(v2, Address(buf, 0x30));
5039 eor3(v2, T16B, v21, v22, v2);
5040
5041 pmull (v23, T1Q, v3, v16, T1D);
5042 pmull2(v24, T1Q, v3, v16, T2D);
5043 ldrq(v3, Address(buf, 0x40));
5044 eor3(v3, T16B, v23, v24, v3);
5045
5046 pmull (v25, T1Q, v4, v16, T1D);
5047 pmull2(v26, T1Q, v4, v16, T2D);
5048 ldrq(v4, Address(buf, 0x50));
5049 eor3(v4, T16B, v25, v26, v4);
5050
5051 pmull (v27, T1Q, v5, v16, T1D);
5052 pmull2(v28, T1Q, v5, v16, T2D);
5053 ldrq(v5, Address(buf, 0x60));
5054 eor3(v5, T16B, v27, v28, v5);
5055
5056 pmull (v29, T1Q, v6, v16, T1D);
5057 pmull2(v30, T1Q, v6, v16, T2D);
5058 ldrq(v6, Address(buf, 0x70));
5059 eor3(v6, T16B, v29, v30, v6);
5060
5061 // Reuse registers v23, v24.
5062 // Using them won't block the first instruction of the next iteration.
5063 pmull (v23, T1Q, v7, v16, T1D);
5064 pmull2(v24, T1Q, v7, v16, T2D);
5065 ldrq(v7, Address(pre(buf, 0x80)));
5066 eor3(v7, T16B, v23, v24, v7);
5067
5068 subs(len, len, 0x80);
5069 br(Assembler::GE, CRC_by128_loop);
5070
5071 // fold into 512 bits
5072 // Use v31 for constants because v16 can be still in use.
5073 ldrq(v31, Address(table, 0x10));
5074
5075 pmull (v17, T1Q, v0, v31, T1D);
5076 pmull2(v18, T1Q, v0, v31, T2D);
5077 eor3(v0, T16B, v17, v18, v4);
5078
5079 pmull (v19, T1Q, v1, v31, T1D);
5080 pmull2(v20, T1Q, v1, v31, T2D);
5081 eor3(v1, T16B, v19, v20, v5);
5082
5083 pmull (v21, T1Q, v2, v31, T1D);
5084 pmull2(v22, T1Q, v2, v31, T2D);
5085 eor3(v2, T16B, v21, v22, v6);
5086
5087 pmull (v23, T1Q, v3, v31, T1D);
5088 pmull2(v24, T1Q, v3, v31, T2D);
5089 eor3(v3, T16B, v23, v24, v7);
5090
5091 // fold into 128 bits
5092 // Use v17 for constants because v31 can be still in use.
5093 ldrq(v17, Address(table, 0x20));
5094 pmull (v25, T1Q, v0, v17, T1D);
5095 pmull2(v26, T1Q, v0, v17, T2D);
5096 eor3(v3, T16B, v3, v25, v26);
5097
5098 // Use v18 for constants because v17 can be still in use.
5099 ldrq(v18, Address(table, 0x30));
5100 pmull (v27, T1Q, v1, v18, T1D);
5101 pmull2(v28, T1Q, v1, v18, T2D);
5102 eor3(v3, T16B, v3, v27, v28);
5103
5104 // Use v19 for constants because v18 can be still in use.
5105 ldrq(v19, Address(table, 0x40));
5106 pmull (v29, T1Q, v2, v19, T1D);
5107 pmull2(v30, T1Q, v2, v19, T2D);
5108 eor3(v0, T16B, v3, v29, v30);
5109
5110 add(len, len, 0x80);
5111 add(buf, buf, 0x10);
5112
5113 mov(tmp0, v0, D, 0);
5114 mov(tmp1, v0, D, 1);
5115 }
5116
5117 void MacroAssembler::addptr(const Address &dst, int32_t src) {
5118 Address adr;
5119 switch(dst.getMode()) {
5120 case Address::base_plus_offset:
5121 // This is the expected mode, although we allow all the other
5122 // forms below.
5123 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
5124 break;
5125 default:
5126 lea(rscratch2, dst);
5127 adr = Address(rscratch2);
5128 break;
5129 }
5130 ldr(rscratch1, adr);
5131 add(rscratch1, rscratch1, src);
5132 str(rscratch1, adr);
5133 }
5134
5135 void MacroAssembler::cmpptr(Register src1, Address src2) {
5136 uint64_t offset;
5137 adrp(rscratch1, src2, offset);
5138 ldr(rscratch1, Address(rscratch1, offset));
5139 cmp(src1, rscratch1);
5140 }
5141
5142 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
5143 cmp(obj1, obj2);
5144 }
5145
5146 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5147 load_method_holder(rresult, rmethod);
5148 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5149 }
5150
5151 void MacroAssembler::load_method_holder(Register holder, Register method) {
5152 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
5153 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5154 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5155 }
5156
5157 void MacroAssembler::load_metadata(Register dst, Register src) {
5158 if (UseCompactObjectHeaders) {
5159 load_narrow_klass_compact(dst, src);
5160 } else {
5161 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5162 }
5163 }
5164
5165 // Loads the obj's Klass* into dst.
5166 // Preserves all registers (incl src, rscratch1 and rscratch2).
5167 // Input:
5168 // src - the oop we want to load the klass from.
5169 // dst - output narrow klass.
5170 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5171 assert(UseCompactObjectHeaders, "expects UseCompactObjectHeaders");
5172 ldr(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5173 lsr(dst, dst, markWord::klass_shift);
5174 }
5175
5176 void MacroAssembler::load_klass(Register dst, Register src) {
5177 if (UseCompactObjectHeaders) {
5178 load_narrow_klass_compact(dst, src);
5179 } else {
5180 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5181 }
5182 decode_klass_not_null(dst);
5183 }
5184
5185 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5186 if (RestoreMXCSROnJNICalls) {
5187 Label OK;
5188 get_fpcr(tmp1);
5189 mov(tmp2, tmp1);
5190 // Set FPCR to the state we need. We do want Round to Nearest. We
5191 // don't want non-IEEE rounding modes or floating-point traps.
5192 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5193 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5194 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5195 eor(tmp2, tmp1, tmp2);
5196 cbz(tmp2, OK); // Only reset FPCR if it's wrong
5197 set_fpcr(tmp1);
5198 bind(OK);
5199 }
5200 }
5201
5202 // ((OopHandle)result).resolve();
5203 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
5204 // OopHandle::resolve is an indirection.
5205 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
5206 }
5207
5208 // ((WeakHandle)result).resolve();
5209 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
5210 assert_different_registers(result, tmp1, tmp2);
5211 Label resolved;
5212
5213 // A null weak handle resolves to null.
5214 cbz(result, resolved);
5215
5216 // Only 64 bit platforms support GCs that require a tmp register
5217 // WeakHandle::resolve is an indirection like jweak.
5218 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5219 result, Address(result), tmp1, tmp2);
5220 bind(resolved);
5221 }
5222
5223 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) {
5224 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5225 ldr(dst, Address(rmethod, Method::const_offset()));
5226 ldr(dst, Address(dst, ConstMethod::constants_offset()));
5227 ldr(dst, Address(dst, ConstantPool::pool_holder_offset()));
5228 ldr(dst, Address(dst, mirror_offset));
5229 resolve_oop_handle(dst, tmp1, tmp2);
5230 }
5231
5232 void MacroAssembler::cmp_klass(Register obj, Register klass, Register tmp) {
5233 assert_different_registers(obj, klass, tmp);
5234 if (UseCompactObjectHeaders) {
5235 load_narrow_klass_compact(tmp, obj);
5236 } else {
5237 ldrw(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5238 }
5239 if (CompressedKlassPointers::base() == nullptr) {
5240 cmp(klass, tmp, LSL, CompressedKlassPointers::shift());
5241 return;
5242 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5243 && CompressedKlassPointers::shift() == 0) {
5244 // Only the bottom 32 bits matter
5245 cmpw(klass, tmp);
5246 return;
5247 }
5248 decode_klass_not_null(tmp);
5249 cmp(klass, tmp);
5250 }
5251
5252 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5253 if (UseCompactObjectHeaders) {
5254 load_narrow_klass_compact(tmp1, obj1);
5255 load_narrow_klass_compact(tmp2, obj2);
5256 } else {
5257 ldrw(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5258 ldrw(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5259 }
5260 cmpw(tmp1, tmp2);
5261 }
5262
5263 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5264 load_klass(dst, src);
5265 ldr(dst, Address(dst, Klass::prototype_header_offset()));
5266 }
5267
5268 void MacroAssembler::store_klass(Register dst, Register src) {
5269 // FIXME: Should this be a store release? concurrent gcs assumes
5270 // klass length is valid if klass field is not null.
5271 assert(!UseCompactObjectHeaders, "not with compact headers");
5272 encode_klass_not_null(src);
5273 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5274 }
5275
5276 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5277 assert(!UseCompactObjectHeaders, "not with compact headers");
5278 // Store to klass gap in destination
5279 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5280 }
5281
5282 // Algorithm must match CompressedOops::encode.
5283 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5284 #ifdef ASSERT
5285 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5286 #endif
5287 verify_oop_msg(s, "broken oop in encode_heap_oop");
5288 if (CompressedOops::base() == nullptr) {
5289 if (CompressedOops::shift() != 0) {
5290 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5291 lsr(d, s, LogMinObjAlignmentInBytes);
5292 } else {
5293 mov(d, s);
5294 }
5295 } else {
5296 subs(d, s, rheapbase);
5297 csel(d, d, zr, Assembler::HS);
5298 lsr(d, d, LogMinObjAlignmentInBytes);
5299
5300 /* Old algorithm: is this any worse?
5301 Label nonnull;
5302 cbnz(r, nonnull);
5303 sub(r, r, rheapbase);
5304 bind(nonnull);
5305 lsr(r, r, LogMinObjAlignmentInBytes);
5306 */
5307 }
5308 }
5309
5310 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5311 #ifdef ASSERT
5312 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5313 if (CheckCompressedOops) {
5314 Label ok;
5315 cbnz(r, ok);
5316 stop("null oop passed to encode_heap_oop_not_null");
5317 bind(ok);
5318 }
5319 #endif
5320 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5321 if (CompressedOops::base() != nullptr) {
5322 sub(r, r, rheapbase);
5323 }
5324 if (CompressedOops::shift() != 0) {
5325 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5326 lsr(r, r, LogMinObjAlignmentInBytes);
5327 }
5328 }
5329
5330 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5331 #ifdef ASSERT
5332 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5333 if (CheckCompressedOops) {
5334 Label ok;
5335 cbnz(src, ok);
5336 stop("null oop passed to encode_heap_oop_not_null2");
5337 bind(ok);
5338 }
5339 #endif
5340 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5341
5342 Register data = src;
5343 if (CompressedOops::base() != nullptr) {
5344 sub(dst, src, rheapbase);
5345 data = dst;
5346 }
5347 if (CompressedOops::shift() != 0) {
5348 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5349 lsr(dst, data, LogMinObjAlignmentInBytes);
5350 data = dst;
5351 }
5352 if (data == src)
5353 mov(dst, src);
5354 }
5355
5356 void MacroAssembler::decode_heap_oop(Register d, Register s) {
5357 #ifdef ASSERT
5358 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5359 #endif
5360 if (CompressedOops::base() == nullptr) {
5361 if (CompressedOops::shift() != 0) {
5362 lsl(d, s, CompressedOops::shift());
5363 } else if (d != s) {
5364 mov(d, s);
5365 }
5366 } else {
5367 Label done;
5368 if (d != s)
5369 mov(d, s);
5370 cbz(s, done);
5371 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
5372 bind(done);
5373 }
5374 verify_oop_msg(d, "broken oop in decode_heap_oop");
5375 }
5376
5377 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5378 assert (UseCompressedOops, "should only be used for compressed headers");
5379 assert (Universe::heap() != nullptr, "java heap should be initialized");
5380 // Cannot assert, unverified entry point counts instructions (see .ad file)
5381 // vtableStubs also counts instructions in pd_code_size_limit.
5382 // Also do not verify_oop as this is called by verify_oop.
5383 if (CompressedOops::shift() != 0) {
5384 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5385 if (CompressedOops::base() != nullptr) {
5386 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5387 } else {
5388 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5389 }
5390 } else {
5391 assert (CompressedOops::base() == nullptr, "sanity");
5392 }
5393 }
5394
5395 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5396 assert (UseCompressedOops, "should only be used for compressed headers");
5397 assert (Universe::heap() != nullptr, "java heap should be initialized");
5398 // Cannot assert, unverified entry point counts instructions (see .ad file)
5399 // vtableStubs also counts instructions in pd_code_size_limit.
5400 // Also do not verify_oop as this is called by verify_oop.
5401 if (CompressedOops::shift() != 0) {
5402 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5403 if (CompressedOops::base() != nullptr) {
5404 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5405 } else {
5406 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5407 }
5408 } else {
5409 assert (CompressedOops::base() == nullptr, "sanity");
5410 if (dst != src) {
5411 mov(dst, src);
5412 }
5413 }
5414 }
5415
5416 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone);
5417
5418 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
5419 assert(Metaspace::initialized(), "metaspace not initialized yet");
5420 assert(_klass_decode_mode != KlassDecodeNone, "should be initialized");
5421 return _klass_decode_mode;
5422 }
5423
5424 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode(address base, int shift, const size_t range) {
5425 // KlassDecodeMode shouldn't be set already.
5426 assert(_klass_decode_mode == KlassDecodeNone, "set once");
5427
5428 if (base == nullptr) {
5429 return KlassDecodeZero;
5430 }
5431
5432 if (operand_valid_for_logical_immediate(
5433 /*is32*/false, (uint64_t)base)) {
5434 const uint64_t range_mask = right_n_bits(log2i_ceil(range));
5435 if (((uint64_t)base & range_mask) == 0) {
5436 return KlassDecodeXor;
5437 }
5438 }
5439
5440 const uint64_t shifted_base =
5441 (uint64_t)base >> shift;
5442 if ((shifted_base & 0xffff0000ffffffff) == 0) {
5443 return KlassDecodeMovk;
5444 }
5445
5446 // No valid encoding.
5447 return KlassDecodeNone;
5448 }
5449
5450 // Check if one of the above decoding modes will work for given base, shift and range.
5451 bool MacroAssembler::check_klass_decode_mode(address base, int shift, const size_t range) {
5452 return klass_decode_mode(base, shift, range) != KlassDecodeNone;
5453 }
5454
5455 bool MacroAssembler::set_klass_decode_mode(address base, int shift, const size_t range) {
5456 _klass_decode_mode = klass_decode_mode(base, shift, range);
5457 return _klass_decode_mode != KlassDecodeNone;
5458 }
5459
5460 static Register pick_different_tmp(Register dst, Register src) {
5461 auto tmps = RegSet::of(r0, r1, r2) - RegSet::of(src, dst);
5462 return *tmps.begin();
5463 }
5464
5465 void MacroAssembler::encode_klass_not_null_for_aot(Register dst, Register src) {
5466 // we have to load the klass base from the AOT constants area but
5467 // not the shift because it is not allowed to change
5468 int shift = CompressedKlassPointers::shift();
5469 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5470 if (dst != src) {
5471 // we can load the base into dst, subtract it formthe src and shift down
5472 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5473 ldr(dst, dst);
5474 sub(dst, src, dst);
5475 lsr(dst, dst, shift);
5476 } else {
5477 // we need an extra register in order to load the coop base
5478 Register tmp = pick_different_tmp(dst, src);
5479 RegSet regs = RegSet::of(tmp);
5480 push(regs, sp);
5481 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5482 ldr(tmp, tmp);
5483 sub(dst, src, tmp);
5484 lsr(dst, dst, shift);
5485 pop(regs, sp);
5486 }
5487 }
5488
5489 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5490 if (AOTCodeCache::is_on_for_dump()) {
5491 encode_klass_not_null_for_aot(dst, src);
5492 return;
5493 }
5494
5495 switch (klass_decode_mode()) {
5496 case KlassDecodeZero:
5497 if (CompressedKlassPointers::shift() != 0) {
5498 lsr(dst, src, CompressedKlassPointers::shift());
5499 } else {
5500 if (dst != src) mov(dst, src);
5501 }
5502 break;
5503
5504 case KlassDecodeXor:
5505 if (CompressedKlassPointers::shift() != 0) {
5506 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5507 lsr(dst, dst, CompressedKlassPointers::shift());
5508 } else {
5509 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5510 }
5511 break;
5512
5513 case KlassDecodeMovk:
5514 if (CompressedKlassPointers::shift() != 0) {
5515 ubfx(dst, src, CompressedKlassPointers::shift(), 32);
5516 } else {
5517 movw(dst, src);
5518 }
5519 break;
5520
5521 case KlassDecodeNone:
5522 ShouldNotReachHere();
5523 break;
5524 }
5525 }
5526
5527 void MacroAssembler::encode_klass_not_null(Register r) {
5528 encode_klass_not_null(r, r);
5529 }
5530
5531 void MacroAssembler::decode_klass_not_null_for_aot(Register dst, Register src) {
5532 // we have to load the klass base from the AOT constants area but
5533 // not the shift because it is not allowed to change
5534 int shift = CompressedKlassPointers::shift();
5535 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5536 if (dst != src) {
5537 // we can load the base into dst then add the offset with a suitable shift
5538 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5539 ldr(dst, dst);
5540 add(dst, dst, src, LSL, shift);
5541 } else {
5542 // we need an extra register in order to load the coop base
5543 Register tmp = pick_different_tmp(dst, src);
5544 RegSet regs = RegSet::of(tmp);
5545 push(regs, sp);
5546 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5547 ldr(tmp, tmp);
5548 add(dst, tmp, src, LSL, shift);
5549 pop(regs, sp);
5550 }
5551 }
5552
5553 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5554 if (AOTCodeCache::is_on_for_dump()) {
5555 decode_klass_not_null_for_aot(dst, src);
5556 return;
5557 }
5558
5559 switch (klass_decode_mode()) {
5560 case KlassDecodeZero:
5561 if (CompressedKlassPointers::shift() != 0) {
5562 lsl(dst, src, CompressedKlassPointers::shift());
5563 } else {
5564 if (dst != src) mov(dst, src);
5565 }
5566 break;
5567
5568 case KlassDecodeXor:
5569 if (CompressedKlassPointers::shift() != 0) {
5570 lsl(dst, src, CompressedKlassPointers::shift());
5571 eor(dst, dst, (uint64_t)CompressedKlassPointers::base());
5572 } else {
5573 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5574 }
5575 break;
5576
5577 case KlassDecodeMovk: {
5578 const uint64_t shifted_base =
5579 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5580
5581 if (dst != src) movw(dst, src);
5582 movk(dst, shifted_base >> 32, 32);
5583
5584 if (CompressedKlassPointers::shift() != 0) {
5585 lsl(dst, dst, CompressedKlassPointers::shift());
5586 }
5587
5588 break;
5589 }
5590
5591 case KlassDecodeNone:
5592 ShouldNotReachHere();
5593 break;
5594 }
5595 }
5596
5597 void MacroAssembler::decode_klass_not_null(Register r) {
5598 decode_klass_not_null(r, r);
5599 }
5600
5601 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5602 #ifdef ASSERT
5603 {
5604 ThreadInVMfromUnknown tiv;
5605 assert (UseCompressedOops, "should only be used for compressed oops");
5606 assert (Universe::heap() != nullptr, "java heap should be initialized");
5607 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5608 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5609 }
5610 #endif
5611 int oop_index = oop_recorder()->find_index(obj);
5612 InstructionMark im(this);
5613 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5614 code_section()->relocate(inst_mark(), rspec);
5615 movz(dst, 0xDEAD, 16);
5616 movk(dst, 0xBEEF);
5617 }
5618
5619 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5620 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5621 int index = oop_recorder()->find_index(k);
5622
5623 InstructionMark im(this);
5624 RelocationHolder rspec = metadata_Relocation::spec(index);
5625 code_section()->relocate(inst_mark(), rspec);
5626 narrowKlass nk = CompressedKlassPointers::encode(k);
5627 movz(dst, (nk >> 16), 16);
5628 movk(dst, nk & 0xffff);
5629 }
5630
5631 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
5632 Register dst, Address src,
5633 Register tmp1, Register tmp2) {
5634 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5635 decorators = AccessInternal::decorator_fixup(decorators, type);
5636 bool as_raw = (decorators & AS_RAW) != 0;
5637 if (as_raw) {
5638 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5639 } else {
5640 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5641 }
5642 }
5643
5644 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5645 Address dst, Register val,
5646 Register tmp1, Register tmp2, Register tmp3) {
5647 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5648 decorators = AccessInternal::decorator_fixup(decorators, type);
5649 bool as_raw = (decorators & AS_RAW) != 0;
5650 if (as_raw) {
5651 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5652 } else {
5653 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5654 }
5655 }
5656
5657 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
5658 Register inline_layout_info) {
5659 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5660 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
5661 }
5662
5663 void MacroAssembler::payload_offset(Register inline_klass, Register offset) {
5664 ldr(offset, Address(inline_klass, InlineKlass::adr_members_offset()));
5665 ldrw(offset, Address(offset, InlineKlass::payload_offset_offset()));
5666 }
5667
5668 void MacroAssembler::payload_address(Register oop, Register data, Register inline_klass) {
5669 // ((address) (void*) o) + vk->payload_offset();
5670 Register offset = (data == oop) ? rscratch1 : data;
5671 payload_offset(inline_klass, offset);
5672 if (data == oop) {
5673 add(data, data, offset);
5674 } else {
5675 lea(data, Address(oop, offset));
5676 }
5677 }
5678
5679 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
5680 Register index, Register data) {
5681 assert_different_registers(array, array_klass, index);
5682 assert_different_registers(rscratch1, array, index);
5683
5684 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
5685 ldrw(rscratch1, Address(array_klass, Klass::layout_helper_offset()));
5686
5687 // Klass::layout_helper_log2_element_size(lh)
5688 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
5689 lsr(rscratch1, rscratch1, Klass::_lh_log2_element_size_shift);
5690 andr(rscratch1, rscratch1, Klass::_lh_log2_element_size_mask);
5691 lslv(index, index, rscratch1);
5692
5693 add(data, array, index);
5694 add(data, data, arrayOopDesc::base_offset_in_bytes(T_FLAT_ELEMENT));
5695 }
5696
5697 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5698 Register tmp2, DecoratorSet decorators) {
5699 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5700 }
5701
5702 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5703 Register tmp2, DecoratorSet decorators) {
5704 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5705 }
5706
5707 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5708 Register tmp2, Register tmp3, DecoratorSet decorators) {
5709 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5710 }
5711
5712 // Used for storing nulls.
5713 void MacroAssembler::store_heap_oop_null(Address dst) {
5714 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5715 }
5716
5717 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
5718 assert(oop_recorder() != nullptr, "this assembler needs a Recorder");
5719 int index = oop_recorder()->allocate_metadata_index(obj);
5720 RelocationHolder rspec = metadata_Relocation::spec(index);
5721 return Address((address)obj, rspec);
5722 }
5723
5724 // Move an oop into a register.
5725 void MacroAssembler::movoop(Register dst, jobject obj) {
5726 int oop_index;
5727 if (obj == nullptr) {
5728 oop_index = oop_recorder()->allocate_oop_index(obj);
5729 } else {
5730 #ifdef ASSERT
5731 {
5732 ThreadInVMfromUnknown tiv;
5733 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5734 }
5735 #endif
5736 oop_index = oop_recorder()->find_index(obj);
5737 }
5738 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5739
5740 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
5741 mov(dst, Address((address)obj, rspec));
5742 } else {
5743 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
5744 ldr(dst, Address(dummy, rspec));
5745 }
5746 }
5747
5748 // Move a metadata address into a register.
5749 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
5750 int oop_index;
5751 if (obj == nullptr) {
5752 oop_index = oop_recorder()->allocate_metadata_index(obj);
5753 } else {
5754 oop_index = oop_recorder()->find_index(obj);
5755 }
5756 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5757 mov(dst, Address((address)obj, rspec));
5758 }
5759
5760 Address MacroAssembler::constant_oop_address(jobject obj) {
5761 #ifdef ASSERT
5762 {
5763 ThreadInVMfromUnknown tiv;
5764 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5765 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5766 }
5767 #endif
5768 int oop_index = oop_recorder()->find_index(obj);
5769 return Address((address)obj, oop_Relocation::spec(oop_index));
5770 }
5771
5772 // Object / value buffer allocation...
5773 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
5774 Register t1, Register t2,
5775 bool clear_fields, Label& alloc_failed)
5776 {
5777 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
5778 Register layout_size = t1;
5779 assert(new_obj == r0, "needs to be r0");
5780 assert_different_registers(klass, new_obj, t1, t2);
5781
5782 // get instance_size in InstanceKlass (scaled to a count of bytes)
5783 ldrw(layout_size, Address(klass, Klass::layout_helper_offset()));
5784 // test to see if it is malformed in some way
5785 tst(layout_size, Klass::_lh_instance_slow_path_bit);
5786 br(Assembler::NE, slow_case_no_pop);
5787
5788 // Allocate the instance:
5789 // If TLAB is enabled:
5790 // Try to allocate in the TLAB.
5791 // If fails, go to the slow path.
5792 // Initialize the allocation.
5793 // Exit.
5794 //
5795 // Go to slow path.
5796
5797 if (UseTLAB) {
5798 push(klass);
5799 tlab_allocate(new_obj, layout_size, 0, klass, t2, slow_case);
5800 if (ZeroTLAB || (!clear_fields)) {
5801 // the fields have been already cleared
5802 b(initialize_header);
5803 } else {
5804 // initialize both the header and fields
5805 b(initialize_object);
5806 }
5807
5808 if (clear_fields) {
5809 // The object is initialized before the header. If the object size is
5810 // zero, go directly to the header initialization.
5811 bind(initialize_object);
5812 int header_size = oopDesc::header_size() * HeapWordSize;
5813 assert(is_aligned(header_size, BytesPerLong), "oop header size must be 8-byte-aligned");
5814 subs(layout_size, layout_size, header_size);
5815 br(Assembler::EQ, initialize_header);
5816
5817 // Initialize topmost object field, divide size by 8, check if odd and
5818 // test if zero.
5819
5820 #ifdef ASSERT
5821 // make sure instance_size was multiple of 8
5822 Label L;
5823 tst(layout_size, 7);
5824 br(Assembler::EQ, L);
5825 stop("object size is not multiple of 8 - adjust this code");
5826 bind(L);
5827 // must be > 0, no extra check needed here
5828 #endif
5829
5830 lsr(layout_size, layout_size, LogBytesPerLong);
5831
5832 // initialize remaining object fields: instance_size was a multiple of 8
5833 {
5834 Label loop;
5835 Register base = t2;
5836
5837 bind(loop);
5838 add(rscratch1, new_obj, layout_size, Assembler::LSL, LogBytesPerLong);
5839 str(zr, Address(rscratch1, header_size - 1*oopSize));
5840 subs(layout_size, layout_size, 1);
5841 br(Assembler::NE, loop);
5842 }
5843 } // clear_fields
5844
5845 // initialize object header only.
5846 bind(initialize_header);
5847 pop(klass);
5848 Register mark_word = t2;
5849 if (UseCompactObjectHeaders || Arguments::is_valhalla_enabled()) {
5850 ldr(mark_word, Address(klass, Klass::prototype_header_offset()));
5851 str(mark_word, Address(new_obj, oopDesc::mark_offset_in_bytes()));
5852 } else {
5853 mov(mark_word, (intptr_t)markWord::prototype().value());
5854 str(mark_word, Address(new_obj, oopDesc::mark_offset_in_bytes()));
5855 }
5856 if (!UseCompactObjectHeaders) {
5857 store_klass_gap(new_obj, zr); // zero klass gap for compressed oops
5858 mov(t2, klass); // preserve klass
5859 store_klass(new_obj, t2); // src klass reg is potentially compressed
5860 }
5861 b(done);
5862 }
5863
5864 if (UseTLAB) {
5865 bind(slow_case);
5866 pop(klass);
5867 }
5868 bind(slow_case_no_pop);
5869 b(alloc_failed);
5870
5871 bind(done);
5872 }
5873
5874 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5875 void MacroAssembler::tlab_allocate(Register obj,
5876 Register var_size_in_bytes,
5877 int con_size_in_bytes,
5878 Register t1,
5879 Register t2,
5880 Label& slow_case) {
5881 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5882 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5883 }
5884
5885 void MacroAssembler::verify_tlab() {
5886 #ifdef ASSERT
5887 if (UseTLAB && VerifyOops) {
5888 Label next, ok;
5889
5890 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5891
5892 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5893 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5894 cmp(rscratch2, rscratch1);
5895 br(Assembler::HS, next);
5896 STOP("assert(top >= start)");
5897 should_not_reach_here();
5898
5899 bind(next);
5900 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5901 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5902 cmp(rscratch2, rscratch1);
5903 br(Assembler::HS, ok);
5904 STOP("assert(top <= end)");
5905 should_not_reach_here();
5906
5907 bind(ok);
5908 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5909 }
5910 #endif
5911 }
5912
5913 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
5914 assert_different_registers(holder_klass, index, layout_info);
5915 InlineLayoutInfo array[2];
5916 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
5917 if (is_power_of_2(size)) {
5918 lsl(index, index, log2i_exact(size)); // Scale index by power of 2
5919 } else {
5920 mov(layout_info, size);
5921 mul(index, index, layout_info); // Scale the index to be the entry index * array_element_size
5922 }
5923 ldr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
5924 add(layout_info, layout_info, Array<InlineLayoutInfo>::base_offset_in_bytes());
5925 lea(layout_info, Address(layout_info, index));
5926 }
5927
5928 // Writes to stack successive pages until offset reached to check for
5929 // stack overflow + shadow pages. This clobbers tmp.
5930 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5931 assert_different_registers(tmp, size, rscratch1);
5932 mov(tmp, sp);
5933 // Bang stack for total size given plus shadow page size.
5934 // Bang one page at a time because large size can bang beyond yellow and
5935 // red zones.
5936 Label loop;
5937 mov(rscratch1, (int)os::vm_page_size());
5938 bind(loop);
5939 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5940 subsw(size, size, rscratch1);
5941 str(size, Address(tmp));
5942 br(Assembler::GT, loop);
5943
5944 // Bang down shadow pages too.
5945 // At this point, (tmp-0) is the last address touched, so don't
5946 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5947 // was post-decremented.) Skip this address by starting at i=1, and
5948 // touch a few more pages below. N.B. It is important to touch all
5949 // the way down to and including i=StackShadowPages.
5950 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) {
5951 // this could be any sized move but this is can be a debugging crumb
5952 // so the bigger the better.
5953 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5954 str(size, Address(tmp));
5955 }
5956 }
5957
5958 // Move the address of the polling page into dest.
5959 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) {
5960 ldr(dest, Address(rthread, JavaThread::polling_page_offset()));
5961 }
5962
5963 // Read the polling page. The address of the polling page must
5964 // already be in r.
5965 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
5966 address mark;
5967 {
5968 InstructionMark im(this);
5969 code_section()->relocate(inst_mark(), rtype);
5970 ldrw(zr, Address(r, 0));
5971 mark = inst_mark();
5972 }
5973 verify_cross_modify_fence_not_required();
5974 return mark;
5975 }
5976
5977 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
5978 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
5979 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
5980 uint64_t dest_page = (uint64_t)dest.target() >> 12;
5981 int64_t offset_low = dest_page - low_page;
5982 int64_t offset_high = dest_page - high_page;
5983
5984 assert(is_valid_AArch64_address(dest.target()), "bad address");
5985 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
5986
5987 InstructionMark im(this);
5988 code_section()->relocate(inst_mark(), dest.rspec());
5989 // 8143067: Ensure that the adrp can reach the dest from anywhere within
5990 // the code cache so that if it is relocated we know it will still reach
5991 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
5992 _adrp(reg1, dest.target());
5993 } else {
5994 uint64_t target = (uint64_t)dest.target();
5995 uint64_t adrp_target
5996 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
5997
5998 _adrp(reg1, (address)adrp_target);
5999 movk(reg1, target >> 32, 32);
6000 }
6001 byte_offset = (uint64_t)dest.target() & 0xfff;
6002 }
6003
6004 void MacroAssembler::load_byte_map_base(Register reg) {
6005 #if INCLUDE_CDS
6006 if (AOTCodeCache::is_on_for_dump()) {
6007 address byte_map_base_adr = AOTRuntimeConstants::card_table_base_address();
6008 lea(reg, ExternalAddress(byte_map_base_adr));
6009 ldr(reg, Address(reg));
6010 return;
6011 }
6012 #endif
6013 CardTableBarrierSet* ctbs = CardTableBarrierSet::barrier_set();
6014
6015 // Strictly speaking the card table base isn't an address at all, and it might
6016 // even be negative. It is thus materialised as a constant.
6017 mov(reg, (uint64_t)ctbs->card_table_base_const());
6018 }
6019
6020 void MacroAssembler::load_aotrc_address(Register reg, address a) {
6021 #if INCLUDE_CDS
6022 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
6023 if (AOTCodeCache::is_on_for_dump()) {
6024 // all aotrc field addresses should be registered in the AOTCodeCache address table
6025 lea(reg, ExternalAddress(a));
6026 } else {
6027 mov(reg, (uint64_t)a);
6028 }
6029 #else
6030 ShouldNotReachHere();
6031 #endif
6032 }
6033
6034 #ifdef ASSERT
6035 void MacroAssembler::build_frame(int framesize) {
6036 build_frame(framesize, false);
6037 }
6038 #endif
6039
6040 void MacroAssembler::build_frame(int framesize DEBUG_ONLY(COMMA bool zap_rfp_lr_spills)) {
6041 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
6042 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
6043 protect_return_address();
6044 if (framesize < ((1 << 9) + 2 * wordSize)) {
6045 sub(sp, sp, framesize);
6046 if (DEBUG_ONLY(zap_rfp_lr_spills ||) false) {
6047 mov_immediate64(rscratch1, ((uint64_t)badRegWordVal) << 32 | (uint64_t)badRegWordVal);
6048 stp(rscratch1, rscratch1, Address(sp, framesize - 2 * wordSize));
6049 } else {
6050 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
6051 }
6052 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
6053 } else {
6054 if (DEBUG_ONLY(zap_rfp_lr_spills ||) false) {
6055 mov_immediate64(rscratch1, ((uint64_t)badRegWordVal) << 32 | (uint64_t)badRegWordVal);
6056 stp(rscratch1, rscratch1, Address(pre(sp, -2 * wordSize)));
6057 } else {
6058 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6059 }
6060 if (PreserveFramePointer) mov(rfp, sp);
6061 if (framesize < ((1 << 12) + 2 * wordSize))
6062 sub(sp, sp, framesize - 2 * wordSize);
6063 else {
6064 mov(rscratch1, framesize - 2 * wordSize);
6065 sub(sp, sp, rscratch1);
6066 }
6067 }
6068 verify_cross_modify_fence_not_required();
6069 }
6070
6071 void MacroAssembler::remove_frame(int framesize) {
6072 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
6073 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
6074 if (framesize < ((1 << 9) + 2 * wordSize)) {
6075 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
6076 add(sp, sp, framesize);
6077 } else {
6078 if (framesize < ((1 << 12) + 2 * wordSize))
6079 add(sp, sp, framesize - 2 * wordSize);
6080 else {
6081 mov(rscratch1, framesize - 2 * wordSize);
6082 add(sp, sp, rscratch1);
6083 }
6084 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6085 }
6086 authenticate_return_address();
6087 }
6088
6089 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
6090 if (needs_stack_repair) {
6091 // The method has a scalarized entry point (where fields of value object arguments
6092 // are passed through registers and stack), and a non-scalarized entry point (where
6093 // value object arguments are given as oops). The non-scalarized entry point will
6094 // first load each field of value object arguments and store them in registers and on
6095 // the stack in a way compatible with the scalarized entry point. To do so, some extra
6096 // stack space might be reserved (if argument registers are not enough). On leaving the
6097 // method, this space must be freed.
6098 //
6099 // In case we used the non-scalarized entry point the stack looks like this:
6100 //
6101 // | Arguments from caller |
6102 // |---------------------------| <-- caller's SP
6103 // | Saved LR #1 |
6104 // | Saved FP #1 |
6105 // |---------------------------|
6106 // | Extension space for |
6107 // | inline arg (un)packing |
6108 // |---------------------------| <-- start of this method's frame
6109 // | Saved LR #2 |
6110 // | Saved FP #2 |
6111 // |---------------------------| <-- FP (with -XX:+PreserveFramePointer)
6112 // | sp_inc |
6113 // | method locals |
6114 // |---------------------------| <-- SP
6115 //
6116 // There are two copies of FP and LR on the stack. They will be identical at
6117 // first, but that can change.
6118 // If the caller has been deoptimized, LR #1 will be patched to point at the
6119 // deopt blob, and LR #2 will still point into the old method.
6120 // If the saved FP (x29) was not used as the frame pointer, but to store an
6121 // oop, the GC will be aware only of FP #1 as the spilled location of x29 and
6122 // will fix only this one. Overall, FP/LR #2 are not reliable and are simply
6123 // needed to add space between the extension space and the locals, as there
6124 // would be between the real arguments and the locals if we don't need to
6125 // do unpacking (from the scalarized entry point).
6126 //
6127 // When restoring, one must then load FP #1 into x29, and LR #1 into x30,
6128 // while keeping in mind that from the scalarized entry point, there will be
6129 // only one copy of each. Indeed, in the case we used the scalarized calling
6130 // convention, the stack looks like this:
6131 //
6132 // | Arguments from caller |
6133 // |---------------------------| <-- caller's SP / start of this method's frame
6134 // | Saved LR |
6135 // | Saved FP |
6136 // |---------------------------| <-- FP (with -XX:+PreserveFramePointer)
6137 // | sp_inc |
6138 // | method locals |
6139 // |---------------------------| <-- SP
6140 //
6141 // The sp_inc stack slot holds the total size of the frame including the
6142 // extension space minus two words for the saved FP and LR. That is how to
6143 // find FP/LR #1. This size is expressed in bytes. Be careful when using it
6144 // from C++ in pointer arithmetic; you might need to divide it by wordSize.
6145 //
6146 // One can find sp_inc since the start the method's frame is SP + initial_framesize.
6147
6148 int sp_inc_offset = initial_framesize - 3 * wordSize; // Immediately below saved LR and FP
6149
6150 ldr(rscratch1, Address(sp, sp_inc_offset));
6151 add(sp, sp, rscratch1);
6152 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6153 } else {
6154 remove_frame(initial_framesize);
6155 }
6156 }
6157
6158 void MacroAssembler::save_stack_increment(int sp_inc, int frame_size) {
6159 int real_frame_size = frame_size + sp_inc;
6160 assert(sp_inc == 0 || sp_inc > 2*wordSize, "invalid sp_inc value");
6161 assert(real_frame_size >= 2*wordSize, "frame size must include FP/LR space");
6162 assert((real_frame_size & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6163
6164 int sp_inc_offset = frame_size - 3 * wordSize; // Immediately below saved LR and FP
6165
6166 // Subtract two words for the saved FP and LR as these will be popped
6167 // separately. See remove_frame above.
6168 mov(rscratch1, real_frame_size - 2*wordSize);
6169 str(rscratch1, Address(sp, sp_inc_offset));
6170 }
6171
6172 // This method counts leading positive bytes (highest bit not set) in provided byte array
6173 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
6174 // Simple and most common case of aligned small array which is not at the
6175 // end of memory page is placed here. All other cases are in stub.
6176 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
6177 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
6178 assert_different_registers(ary1, len, result);
6179
6180 mov(result, len);
6181 cmpw(len, 0);
6182 br(LE, DONE);
6183 cmpw(len, 4 * wordSize);
6184 br(GE, STUB_LONG); // size > 32 then go to stub
6185
6186 int shift = 64 - exact_log2(os::vm_page_size());
6187 lsl(rscratch1, ary1, shift);
6188 mov(rscratch2, (size_t)(4 * wordSize) << shift);
6189 adds(rscratch2, rscratch1, rscratch2); // At end of page?
6190 br(CS, STUB); // at the end of page then go to stub
6191 subs(len, len, wordSize);
6192 br(LT, END);
6193
6194 BIND(LOOP);
6195 ldr(rscratch1, Address(post(ary1, wordSize)));
6196 tst(rscratch1, UPPER_BIT_MASK);
6197 br(NE, SET_RESULT);
6198 subs(len, len, wordSize);
6199 br(GE, LOOP);
6200 cmpw(len, -wordSize);
6201 br(EQ, DONE);
6202
6203 BIND(END);
6204 ldr(rscratch1, Address(ary1));
6205 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
6206 lslv(rscratch1, rscratch1, rscratch2);
6207 tst(rscratch1, UPPER_BIT_MASK);
6208 br(NE, SET_RESULT);
6209 b(DONE);
6210
6211 BIND(STUB);
6212 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives());
6213 assert(count_pos.target() != nullptr, "count_positives stub has not been generated");
6214 address tpc1 = trampoline_call(count_pos);
6215 if (tpc1 == nullptr) {
6216 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE));
6217 postcond(pc() == badAddress);
6218 return nullptr;
6219 }
6220 b(DONE);
6221
6222 BIND(STUB_LONG);
6223 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long());
6224 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated");
6225 address tpc2 = trampoline_call(count_pos_long);
6226 if (tpc2 == nullptr) {
6227 DEBUG_ONLY(reset_labels(SET_RESULT, DONE));
6228 postcond(pc() == badAddress);
6229 return nullptr;
6230 }
6231 b(DONE);
6232
6233 BIND(SET_RESULT);
6234
6235 add(len, len, wordSize);
6236 sub(result, result, len);
6237
6238 BIND(DONE);
6239 postcond(pc() != badAddress);
6240 return pc();
6241 }
6242
6243 // Clobbers: rscratch1, rscratch2, rflags
6244 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals)
6245 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
6246 Register tmp4, Register tmp5, Register result,
6247 Register cnt1, int elem_size) {
6248 Label DONE, SAME;
6249 Register tmp1 = rscratch1;
6250 Register tmp2 = rscratch2;
6251 int elem_per_word = wordSize/elem_size;
6252 int log_elem_size = exact_log2(elem_size);
6253 int klass_offset = arrayOopDesc::klass_offset_in_bytes();
6254 int length_offset = arrayOopDesc::length_offset_in_bytes();
6255 int base_offset
6256 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
6257 // When the length offset is not aligned to 8 bytes,
6258 // then we align it down. This is valid because the new
6259 // offset will always be the klass which is the same
6260 // for type arrays.
6261 int start_offset = align_down(length_offset, BytesPerWord);
6262 int extra_length = base_offset - start_offset;
6263 assert(start_offset == length_offset || start_offset == klass_offset,
6264 "start offset must be 8-byte-aligned or be the klass offset");
6265 assert(base_offset != start_offset, "must include the length field");
6266 extra_length = extra_length / elem_size; // We count in elements, not bytes.
6267 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
6268
6269 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
6270 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
6271
6272 #ifndef PRODUCT
6273 {
6274 const char kind = (elem_size == 2) ? 'U' : 'L';
6275 char comment[64];
6276 os::snprintf_checked(comment, sizeof comment, "array_equals%c{", kind);
6277 BLOCK_COMMENT(comment);
6278 }
6279 #endif
6280
6281 // if (a1 == a2)
6282 // return true;
6283 cmpoop(a1, a2); // May have read barriers for a1 and a2.
6284 br(EQ, SAME);
6285
6286 if (UseSimpleArrayEquals) {
6287 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
6288 // if (a1 == nullptr || a2 == nullptr)
6289 // return false;
6290 // a1 & a2 == 0 means (some-pointer is null) or
6291 // (very-rare-or-even-probably-impossible-pointer-values)
6292 // so, we can save one branch in most cases
6293 tst(a1, a2);
6294 mov(result, false);
6295 br(EQ, A_MIGHT_BE_NULL);
6296 // if (a1.length != a2.length)
6297 // return false;
6298 bind(A_IS_NOT_NULL);
6299 ldrw(cnt1, Address(a1, length_offset));
6300 ldrw(tmp5, Address(a2, length_offset));
6301 cmp(cnt1, tmp5);
6302 br(NE, DONE); // If lengths differ, return false
6303 // Increase loop counter by diff between base- and actual start-offset.
6304 addw(cnt1, cnt1, extra_length);
6305 lea(a1, Address(a1, start_offset));
6306 lea(a2, Address(a2, start_offset));
6307 // Check for short strings, i.e. smaller than wordSize.
6308 subs(cnt1, cnt1, elem_per_word);
6309 br(Assembler::LT, SHORT);
6310 // Main 8 byte comparison loop.
6311 bind(NEXT_WORD); {
6312 ldr(tmp1, Address(post(a1, wordSize)));
6313 ldr(tmp2, Address(post(a2, wordSize)));
6314 subs(cnt1, cnt1, elem_per_word);
6315 eor(tmp5, tmp1, tmp2);
6316 cbnz(tmp5, DONE);
6317 } br(GT, NEXT_WORD);
6318 // Last longword. In the case where length == 4 we compare the
6319 // same longword twice, but that's still faster than another
6320 // conditional branch.
6321 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6322 // length == 4.
6323 if (log_elem_size > 0)
6324 lsl(cnt1, cnt1, log_elem_size);
6325 ldr(tmp3, Address(a1, cnt1));
6326 ldr(tmp4, Address(a2, cnt1));
6327 eor(tmp5, tmp3, tmp4);
6328 cbnz(tmp5, DONE);
6329 b(SAME);
6330 bind(A_MIGHT_BE_NULL);
6331 // in case both a1 and a2 are not-null, proceed with loads
6332 cbz(a1, DONE);
6333 cbz(a2, DONE);
6334 b(A_IS_NOT_NULL);
6335 bind(SHORT);
6336
6337 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
6338 {
6339 ldrw(tmp1, Address(post(a1, 4)));
6340 ldrw(tmp2, Address(post(a2, 4)));
6341 eorw(tmp5, tmp1, tmp2);
6342 cbnzw(tmp5, DONE);
6343 }
6344 bind(TAIL03);
6345 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
6346 {
6347 ldrh(tmp3, Address(post(a1, 2)));
6348 ldrh(tmp4, Address(post(a2, 2)));
6349 eorw(tmp5, tmp3, tmp4);
6350 cbnzw(tmp5, DONE);
6351 }
6352 bind(TAIL01);
6353 if (elem_size == 1) { // Only needed when comparing byte arrays.
6354 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6355 {
6356 ldrb(tmp1, a1);
6357 ldrb(tmp2, a2);
6358 eorw(tmp5, tmp1, tmp2);
6359 cbnzw(tmp5, DONE);
6360 }
6361 }
6362 } else {
6363 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
6364 CSET_EQ, LAST_CHECK;
6365 mov(result, false);
6366 cbz(a1, DONE);
6367 ldrw(cnt1, Address(a1, length_offset));
6368 cbz(a2, DONE);
6369 ldrw(tmp5, Address(a2, length_offset));
6370 cmp(cnt1, tmp5);
6371 br(NE, DONE); // If lengths differ, return false
6372 // Increase loop counter by diff between base- and actual start-offset.
6373 addw(cnt1, cnt1, extra_length);
6374
6375 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
6376 // faster to perform another branch before comparing a1 and a2
6377 cmp(cnt1, (u1)elem_per_word);
6378 br(LE, SHORT); // short or same
6379 ldr(tmp3, Address(pre(a1, start_offset)));
6380 subs(zr, cnt1, stubBytesThreshold);
6381 br(GE, STUB);
6382 ldr(tmp4, Address(pre(a2, start_offset)));
6383 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6384
6385 // Main 16 byte comparison loop with 2 exits
6386 bind(NEXT_DWORD); {
6387 ldr(tmp1, Address(pre(a1, wordSize)));
6388 ldr(tmp2, Address(pre(a2, wordSize)));
6389 subs(cnt1, cnt1, 2 * elem_per_word);
6390 br(LE, TAIL);
6391 eor(tmp4, tmp3, tmp4);
6392 cbnz(tmp4, DONE);
6393 ldr(tmp3, Address(pre(a1, wordSize)));
6394 ldr(tmp4, Address(pre(a2, wordSize)));
6395 cmp(cnt1, (u1)elem_per_word);
6396 br(LE, TAIL2);
6397 cmp(tmp1, tmp2);
6398 } br(EQ, NEXT_DWORD);
6399 b(DONE);
6400
6401 bind(TAIL);
6402 eor(tmp4, tmp3, tmp4);
6403 eor(tmp2, tmp1, tmp2);
6404 lslv(tmp2, tmp2, tmp5);
6405 orr(tmp5, tmp4, tmp2);
6406 cmp(tmp5, zr);
6407 b(CSET_EQ);
6408
6409 bind(TAIL2);
6410 eor(tmp2, tmp1, tmp2);
6411 cbnz(tmp2, DONE);
6412 b(LAST_CHECK);
6413
6414 bind(STUB);
6415 ldr(tmp4, Address(pre(a2, start_offset)));
6416 if (elem_size == 2) { // convert to byte counter
6417 lsl(cnt1, cnt1, 1);
6418 }
6419 eor(tmp5, tmp3, tmp4);
6420 cbnz(tmp5, DONE);
6421 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
6422 assert(stub.target() != nullptr, "array_equals_long stub has not been generated");
6423 address tpc = trampoline_call(stub);
6424 if (tpc == nullptr) {
6425 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
6426 postcond(pc() == badAddress);
6427 return nullptr;
6428 }
6429 b(DONE);
6430
6431 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
6432 // so, if a2 == null => return false(0), else return true, so we can return a2
6433 mov(result, a2);
6434 b(DONE);
6435 bind(SHORT);
6436 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6437 ldr(tmp3, Address(a1, start_offset));
6438 ldr(tmp4, Address(a2, start_offset));
6439 bind(LAST_CHECK);
6440 eor(tmp4, tmp3, tmp4);
6441 lslv(tmp5, tmp4, tmp5);
6442 cmp(tmp5, zr);
6443 bind(CSET_EQ);
6444 cset(result, EQ);
6445 b(DONE);
6446 }
6447
6448 bind(SAME);
6449 mov(result, true);
6450 // That's it.
6451 bind(DONE);
6452
6453 BLOCK_COMMENT("} array_equals");
6454 postcond(pc() != badAddress);
6455 return pc();
6456 }
6457
6458 // Compare Strings
6459
6460 // For Strings we're passed the address of the first characters in a1
6461 // and a2 and the length in cnt1.
6462 // There are two implementations. For arrays >= 8 bytes, all
6463 // comparisons (including the final one, which may overlap) are
6464 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
6465 // halfword, then a short, and then a byte.
6466
6467 void MacroAssembler::string_equals(Register a1, Register a2,
6468 Register result, Register cnt1)
6469 {
6470 Label SAME, DONE, SHORT, NEXT_WORD;
6471 Register tmp1 = rscratch1;
6472 Register tmp2 = rscratch2;
6473
6474 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
6475
6476 #ifndef PRODUCT
6477 {
6478 char comment[64];
6479 os::snprintf_checked(comment, sizeof comment, "{string_equalsL");
6480 BLOCK_COMMENT(comment);
6481 }
6482 #endif
6483
6484 mov(result, false);
6485
6486 // Check for short strings, i.e. smaller than wordSize.
6487 subs(cnt1, cnt1, wordSize);
6488 br(Assembler::LT, SHORT);
6489 // Main 8 byte comparison loop.
6490 bind(NEXT_WORD); {
6491 ldr(tmp1, Address(post(a1, wordSize)));
6492 ldr(tmp2, Address(post(a2, wordSize)));
6493 subs(cnt1, cnt1, wordSize);
6494 eor(tmp1, tmp1, tmp2);
6495 cbnz(tmp1, DONE);
6496 } br(GT, NEXT_WORD);
6497 // Last longword. In the case where length == 4 we compare the
6498 // same longword twice, but that's still faster than another
6499 // conditional branch.
6500 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6501 // length == 4.
6502 ldr(tmp1, Address(a1, cnt1));
6503 ldr(tmp2, Address(a2, cnt1));
6504 eor(tmp2, tmp1, tmp2);
6505 cbnz(tmp2, DONE);
6506 b(SAME);
6507
6508 bind(SHORT);
6509 Label TAIL03, TAIL01;
6510
6511 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
6512 {
6513 ldrw(tmp1, Address(post(a1, 4)));
6514 ldrw(tmp2, Address(post(a2, 4)));
6515 eorw(tmp1, tmp1, tmp2);
6516 cbnzw(tmp1, DONE);
6517 }
6518 bind(TAIL03);
6519 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
6520 {
6521 ldrh(tmp1, Address(post(a1, 2)));
6522 ldrh(tmp2, Address(post(a2, 2)));
6523 eorw(tmp1, tmp1, tmp2);
6524 cbnzw(tmp1, DONE);
6525 }
6526 bind(TAIL01);
6527 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6528 {
6529 ldrb(tmp1, a1);
6530 ldrb(tmp2, a2);
6531 eorw(tmp1, tmp1, tmp2);
6532 cbnzw(tmp1, DONE);
6533 }
6534 // Arrays are equal.
6535 bind(SAME);
6536 mov(result, true);
6537
6538 // That's it.
6539 bind(DONE);
6540 BLOCK_COMMENT("} string_equals");
6541 }
6542
6543
6544 // The size of the blocks erased by the zero_blocks stub. We must
6545 // handle anything smaller than this ourselves in zero_words().
6546 const int MacroAssembler::zero_words_block_size = 8;
6547
6548 // zero_words() is used by C2 ClearArray patterns and by
6549 // C1_MacroAssembler. It is as small as possible, handling small word
6550 // counts locally and delegating anything larger to the zero_blocks
6551 // stub. It is expanded many times in compiled code, so it is
6552 // important to keep it short.
6553
6554 // ptr: Address of a buffer to be zeroed.
6555 // cnt: Count in HeapWords.
6556 //
6557 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
6558 address MacroAssembler::zero_words(Register ptr, Register cnt)
6559 {
6560 assert(is_power_of_2(zero_words_block_size), "adjust this");
6561
6562 BLOCK_COMMENT("zero_words {");
6563 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
6564 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6565 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6566
6567 subs(rscratch1, cnt, zero_words_block_size);
6568 Label around;
6569 br(LO, around);
6570 {
6571 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6572 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6573 // Make sure this is a C2 compilation. C1 allocates space only for
6574 // trampoline stubs generated by Call LIR ops, and in any case it
6575 // makes sense for a C1 compilation task to proceed as quickly as
6576 // possible.
6577 CompileTask* task;
6578 if (StubRoutines::aarch64::complete()
6579 && Thread::current()->is_Compiler_thread()
6580 && (task = ciEnv::current()->task())
6581 && is_c2_compile(task->comp_level())) {
6582 address tpc = trampoline_call(zero_blocks);
6583 if (tpc == nullptr) {
6584 DEBUG_ONLY(reset_labels(around));
6585 return nullptr;
6586 }
6587 } else {
6588 far_call(zero_blocks);
6589 }
6590 }
6591 bind(around);
6592
6593 // We have a few words left to do. zero_blocks has adjusted r10 and r11
6594 // for us.
6595 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
6596 Label l;
6597 tbz(cnt, exact_log2(i), l);
6598 for (int j = 0; j < i; j += 2) {
6599 stp(zr, zr, post(ptr, 2 * BytesPerWord));
6600 }
6601 bind(l);
6602 }
6603 {
6604 Label l;
6605 tbz(cnt, 0, l);
6606 str(zr, Address(ptr));
6607 bind(l);
6608 }
6609
6610 BLOCK_COMMENT("} zero_words");
6611 return pc();
6612 }
6613
6614 // base: Address of a buffer to be zeroed, 8 bytes aligned.
6615 // cnt: Immediate count in HeapWords.
6616 //
6617 // r10, r11, rscratch1, and rscratch2 are clobbered.
6618 address MacroAssembler::zero_words(Register base, uint64_t cnt)
6619 {
6620 assert(wordSize <= BlockZeroingLowLimit,
6621 "increase BlockZeroingLowLimit");
6622 address result = nullptr;
6623 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) {
6624 #ifndef PRODUCT
6625 {
6626 char buf[64];
6627 os::snprintf_checked(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt);
6628 BLOCK_COMMENT(buf);
6629 }
6630 #endif
6631 if (cnt >= 16) {
6632 uint64_t loops = cnt/16;
6633 if (loops > 1) {
6634 mov(rscratch2, loops - 1);
6635 }
6636 {
6637 Label loop;
6638 bind(loop);
6639 for (int i = 0; i < 16; i += 2) {
6640 stp(zr, zr, Address(base, i * BytesPerWord));
6641 }
6642 add(base, base, 16 * BytesPerWord);
6643 if (loops > 1) {
6644 subs(rscratch2, rscratch2, 1);
6645 br(GE, loop);
6646 }
6647 }
6648 }
6649 cnt %= 16;
6650 int i = cnt & 1; // store any odd word to start
6651 if (i) str(zr, Address(base));
6652 for (; i < (int)cnt; i += 2) {
6653 stp(zr, zr, Address(base, i * wordSize));
6654 }
6655 BLOCK_COMMENT("} zero_words");
6656 result = pc();
6657 } else {
6658 mov(r10, base); mov(r11, cnt);
6659 result = zero_words(r10, r11);
6660 }
6661 return result;
6662 }
6663
6664 // Zero blocks of memory by using DC ZVA.
6665 //
6666 // Aligns the base address first sufficiently for DC ZVA, then uses
6667 // DC ZVA repeatedly for every full block. cnt is the size to be
6668 // zeroed in HeapWords. Returns the count of words left to be zeroed
6669 // in cnt.
6670 //
6671 // NOTE: This is intended to be used in the zero_blocks() stub. If
6672 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
6673 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
6674 Register tmp = rscratch1;
6675 Register tmp2 = rscratch2;
6676 int zva_length = VM_Version::zva_length();
6677 Label initial_table_end, loop_zva;
6678 Label fini;
6679
6680 // Base must be 16 byte aligned. If not just return and let caller handle it
6681 tst(base, 0x0f);
6682 br(Assembler::NE, fini);
6683 // Align base with ZVA length.
6684 neg(tmp, base);
6685 andr(tmp, tmp, zva_length - 1);
6686
6687 // tmp: the number of bytes to be filled to align the base with ZVA length.
6688 add(base, base, tmp);
6689 sub(cnt, cnt, tmp, Assembler::ASR, 3);
6690 adr(tmp2, initial_table_end);
6691 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
6692 br(tmp2);
6693
6694 for (int i = -zva_length + 16; i < 0; i += 16)
6695 stp(zr, zr, Address(base, i));
6696 bind(initial_table_end);
6697
6698 sub(cnt, cnt, zva_length >> 3);
6699 bind(loop_zva);
6700 dc(Assembler::ZVA, base);
6701 subs(cnt, cnt, zva_length >> 3);
6702 add(base, base, zva_length);
6703 br(Assembler::GE, loop_zva);
6704 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
6705 bind(fini);
6706 }
6707
6708 // base: Address of a buffer to be filled, 8 bytes aligned.
6709 // cnt: Count in 8-byte unit.
6710 // value: Value to be filled with.
6711 // base will point to the end of the buffer after filling.
6712 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
6713 {
6714 // Algorithm:
6715 //
6716 // if (cnt == 0) {
6717 // return;
6718 // }
6719 // if ((p & 8) != 0) {
6720 // *p++ = v;
6721 // }
6722 //
6723 // scratch1 = cnt & 14;
6724 // cnt -= scratch1;
6725 // p += scratch1;
6726 // switch (scratch1 / 2) {
6727 // do {
6728 // cnt -= 16;
6729 // p[-16] = v;
6730 // p[-15] = v;
6731 // case 7:
6732 // p[-14] = v;
6733 // p[-13] = v;
6734 // case 6:
6735 // p[-12] = v;
6736 // p[-11] = v;
6737 // // ...
6738 // case 1:
6739 // p[-2] = v;
6740 // p[-1] = v;
6741 // case 0:
6742 // p += 16;
6743 // } while (cnt);
6744 // }
6745 // if ((cnt & 1) == 1) {
6746 // *p++ = v;
6747 // }
6748
6749 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
6750
6751 Label fini, skip, entry, loop;
6752 const int unroll = 8; // Number of stp instructions we'll unroll
6753
6754 cbz(cnt, fini);
6755 tbz(base, 3, skip);
6756 str(value, Address(post(base, 8)));
6757 sub(cnt, cnt, 1);
6758 bind(skip);
6759
6760 andr(rscratch1, cnt, (unroll-1) * 2);
6761 sub(cnt, cnt, rscratch1);
6762 add(base, base, rscratch1, Assembler::LSL, 3);
6763 adr(rscratch2, entry);
6764 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
6765 br(rscratch2);
6766
6767 bind(loop);
6768 add(base, base, unroll * 16);
6769 for (int i = -unroll; i < 0; i++)
6770 stp(value, value, Address(base, i * 16));
6771 bind(entry);
6772 subs(cnt, cnt, unroll * 2);
6773 br(Assembler::GE, loop);
6774
6775 tbz(cnt, 0, fini);
6776 str(value, Address(post(base, 8)));
6777 bind(fini);
6778 }
6779
6780 // Intrinsic for
6781 //
6782 // - sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6783 // Encodes char[] to byte[] in ISO-8859-1
6784 //
6785 // - java.lang.StringCoding#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6786 // Encodes byte[] (containing UTF-16) to byte[] in ISO-8859-1
6787 //
6788 // - java.lang.StringCoding#encodeAsciiArray0(char[] sa, int sp, byte[] da, int dp, int len)
6789 // Encodes char[] to byte[] in ASCII
6790 //
6791 // This version always returns the number of characters copied, and does not
6792 // clobber the 'len' register. A successful copy will complete with the post-
6793 // condition: 'res' == 'len', while an unsuccessful copy will exit with the
6794 // post-condition: 0 <= 'res' < 'len'.
6795 //
6796 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
6797 // degrade performance (on Ampere Altra - Neoverse N1), to an extent
6798 // beyond the acceptable, even though the footprint would be smaller.
6799 // Using 'umaxv' in the ASCII-case comes with a small penalty but does
6800 // avoid additional bloat.
6801 //
6802 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags
6803 void MacroAssembler::encode_iso_array(Register src, Register dst,
6804 Register len, Register res, bool ascii,
6805 FloatRegister vtmp0, FloatRegister vtmp1,
6806 FloatRegister vtmp2, FloatRegister vtmp3,
6807 FloatRegister vtmp4, FloatRegister vtmp5)
6808 {
6809 Register cnt = res;
6810 Register max = rscratch1;
6811 Register chk = rscratch2;
6812
6813 prfm(Address(src), PLDL1STRM);
6814 movw(cnt, len);
6815
6816 #define ASCII(insn) do { if (ascii) { insn; } } while (0)
6817
6818 Label LOOP_32, DONE_32, FAIL_32;
6819
6820 BIND(LOOP_32);
6821 {
6822 cmpw(cnt, 32);
6823 br(LT, DONE_32);
6824 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
6825 // Extract lower bytes.
6826 FloatRegister vlo0 = vtmp4;
6827 FloatRegister vlo1 = vtmp5;
6828 uzp1(vlo0, T16B, vtmp0, vtmp1);
6829 uzp1(vlo1, T16B, vtmp2, vtmp3);
6830 // Merge bits...
6831 orr(vtmp0, T16B, vtmp0, vtmp1);
6832 orr(vtmp2, T16B, vtmp2, vtmp3);
6833 // Extract merged upper bytes.
6834 FloatRegister vhix = vtmp0;
6835 uzp2(vhix, T16B, vtmp0, vtmp2);
6836 // ISO-check on hi-parts (all zero).
6837 // ASCII-check on lo-parts (no sign).
6838 FloatRegister vlox = vtmp1; // Merge lower bytes.
6839 ASCII(orr(vlox, T16B, vlo0, vlo1));
6840 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox));
6841 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox));
6842 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0));
6843 ASCII(orr(chk, chk, max));
6844 cbnz(chk, FAIL_32);
6845 subw(cnt, cnt, 32);
6846 st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
6847 b(LOOP_32);
6848 }
6849 BIND(FAIL_32);
6850 sub(src, src, 64);
6851 BIND(DONE_32);
6852
6853 Label LOOP_8, SKIP_8;
6854
6855 BIND(LOOP_8);
6856 {
6857 cmpw(cnt, 8);
6858 br(LT, SKIP_8);
6859 FloatRegister vhi = vtmp0;
6860 FloatRegister vlo = vtmp1;
6861 ld1(vtmp3, T8H, src);
6862 uzp1(vlo, T16B, vtmp3, vtmp3);
6863 uzp2(vhi, T16B, vtmp3, vtmp3);
6864 // ISO-check on hi-parts (all zero).
6865 // ASCII-check on lo-parts (no sign).
6866 ASCII(cm(LT, vtmp2, T16B, vlo));
6867 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2));
6868 ASCII(umov(max, vtmp2, B, 0));
6869 ASCII(orr(chk, chk, max));
6870 cbnz(chk, SKIP_8);
6871
6872 strd(vlo, Address(post(dst, 8)));
6873 subw(cnt, cnt, 8);
6874 add(src, src, 16);
6875 b(LOOP_8);
6876 }
6877 BIND(SKIP_8);
6878
6879 #undef ASCII
6880
6881 Label LOOP, DONE;
6882
6883 cbz(cnt, DONE);
6884 BIND(LOOP);
6885 {
6886 Register chr = rscratch1;
6887 ldrh(chr, Address(post(src, 2)));
6888 tst(chr, ascii ? 0xff80 : 0xff00);
6889 br(NE, DONE);
6890 strb(chr, Address(post(dst, 1)));
6891 subs(cnt, cnt, 1);
6892 br(GT, LOOP);
6893 }
6894 BIND(DONE);
6895 // Return index where we stopped.
6896 subw(res, len, cnt);
6897 }
6898
6899 // Inflate byte[] array to char[].
6900 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6
6901 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
6902 FloatRegister vtmp1, FloatRegister vtmp2,
6903 FloatRegister vtmp3, Register tmp4) {
6904 Label big, done, after_init, to_stub;
6905
6906 assert_different_registers(src, dst, len, tmp4, rscratch1);
6907
6908 fmovd(vtmp1, 0.0);
6909 lsrw(tmp4, len, 3);
6910 bind(after_init);
6911 cbnzw(tmp4, big);
6912 // Short string: less than 8 bytes.
6913 {
6914 Label loop, tiny;
6915
6916 cmpw(len, 4);
6917 br(LT, tiny);
6918 // Use SIMD to do 4 bytes.
6919 ldrs(vtmp2, post(src, 4));
6920 zip1(vtmp3, T8B, vtmp2, vtmp1);
6921 subw(len, len, 4);
6922 strd(vtmp3, post(dst, 8));
6923
6924 cbzw(len, done);
6925
6926 // Do the remaining bytes by steam.
6927 bind(loop);
6928 ldrb(tmp4, post(src, 1));
6929 strh(tmp4, post(dst, 2));
6930 subw(len, len, 1);
6931
6932 bind(tiny);
6933 cbnz(len, loop);
6934
6935 b(done);
6936 }
6937
6938 if (SoftwarePrefetchHintDistance >= 0) {
6939 bind(to_stub);
6940 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
6941 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated");
6942 address tpc = trampoline_call(stub);
6943 if (tpc == nullptr) {
6944 DEBUG_ONLY(reset_labels(big, done));
6945 postcond(pc() == badAddress);
6946 return nullptr;
6947 }
6948 b(after_init);
6949 }
6950
6951 // Unpack the bytes 8 at a time.
6952 bind(big);
6953 {
6954 Label loop, around, loop_last, loop_start;
6955
6956 if (SoftwarePrefetchHintDistance >= 0) {
6957 const int large_loop_threshold = (64 + 16)/8;
6958 ldrd(vtmp2, post(src, 8));
6959 andw(len, len, 7);
6960 cmp(tmp4, (u1)large_loop_threshold);
6961 br(GE, to_stub);
6962 b(loop_start);
6963
6964 bind(loop);
6965 ldrd(vtmp2, post(src, 8));
6966 bind(loop_start);
6967 subs(tmp4, tmp4, 1);
6968 br(EQ, loop_last);
6969 zip1(vtmp2, T16B, vtmp2, vtmp1);
6970 ldrd(vtmp3, post(src, 8));
6971 st1(vtmp2, T8H, post(dst, 16));
6972 subs(tmp4, tmp4, 1);
6973 zip1(vtmp3, T16B, vtmp3, vtmp1);
6974 st1(vtmp3, T8H, post(dst, 16));
6975 br(NE, loop);
6976 b(around);
6977 bind(loop_last);
6978 zip1(vtmp2, T16B, vtmp2, vtmp1);
6979 st1(vtmp2, T8H, post(dst, 16));
6980 bind(around);
6981 cbz(len, done);
6982 } else {
6983 andw(len, len, 7);
6984 bind(loop);
6985 ldrd(vtmp2, post(src, 8));
6986 sub(tmp4, tmp4, 1);
6987 zip1(vtmp3, T16B, vtmp2, vtmp1);
6988 st1(vtmp3, T8H, post(dst, 16));
6989 cbnz(tmp4, loop);
6990 }
6991 }
6992
6993 // Do the tail of up to 8 bytes.
6994 add(src, src, len);
6995 ldrd(vtmp3, Address(src, -8));
6996 add(dst, dst, len, ext::uxtw, 1);
6997 zip1(vtmp3, T16B, vtmp3, vtmp1);
6998 strq(vtmp3, Address(dst, -16));
6999
7000 bind(done);
7001 postcond(pc() != badAddress);
7002 return pc();
7003 }
7004
7005 // Compress char[] array to byte[].
7006 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
7007 // Return the array length if every element in array can be encoded,
7008 // otherwise, the index of first non-latin1 (> 0xff) character.
7009 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
7010 Register res,
7011 FloatRegister tmp0, FloatRegister tmp1,
7012 FloatRegister tmp2, FloatRegister tmp3,
7013 FloatRegister tmp4, FloatRegister tmp5) {
7014 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
7015 }
7016
7017 // java.math.round(double a)
7018 // Returns the closest long to the argument, with ties rounding to
7019 // positive infinity. This requires some fiddling for corner
7020 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5).
7021 void MacroAssembler::java_round_double(Register dst, FloatRegister src,
7022 FloatRegister ftmp) {
7023 Label DONE;
7024 BLOCK_COMMENT("java_round_double: { ");
7025 fmovd(rscratch1, src);
7026 // Use RoundToNearestTiesAway unless src small and -ve.
7027 fcvtasd(dst, src);
7028 // Test if src >= 0 || abs(src) >= 0x1.0p52
7029 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit
7030 mov(rscratch2, julong_cast(0x1.0p52));
7031 cmp(rscratch1, rscratch2);
7032 br(HS, DONE); {
7033 // src < 0 && abs(src) < 0x1.0p52
7034 // src may have a fractional part, so add 0.5
7035 fmovd(ftmp, 0.5);
7036 faddd(ftmp, src, ftmp);
7037 // Convert double to jlong, use RoundTowardsNegative
7038 fcvtmsd(dst, ftmp);
7039 }
7040 bind(DONE);
7041 BLOCK_COMMENT("} java_round_double");
7042 }
7043
7044 void MacroAssembler::java_round_float(Register dst, FloatRegister src,
7045 FloatRegister ftmp) {
7046 Label DONE;
7047 BLOCK_COMMENT("java_round_float: { ");
7048 fmovs(rscratch1, src);
7049 // Use RoundToNearestTiesAway unless src small and -ve.
7050 fcvtassw(dst, src);
7051 // Test if src >= 0 || abs(src) >= 0x1.0p23
7052 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit
7053 mov(rscratch2, jint_cast(0x1.0p23f));
7054 cmp(rscratch1, rscratch2);
7055 br(HS, DONE); {
7056 // src < 0 && |src| < 0x1.0p23
7057 // src may have a fractional part, so add 0.5
7058 fmovs(ftmp, 0.5f);
7059 fadds(ftmp, src, ftmp);
7060 // Convert float to jint, use RoundTowardsNegative
7061 fcvtmssw(dst, ftmp);
7062 }
7063 bind(DONE);
7064 BLOCK_COMMENT("} java_round_float");
7065 }
7066
7067 // get_thread() can be called anywhere inside generated code so we
7068 // need to save whatever non-callee save context might get clobbered
7069 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
7070 // the call setup code.
7071 //
7072 // On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags.
7073 // On other systems, the helper is a usual C function.
7074 //
7075 void MacroAssembler::get_thread(Register dst) {
7076 RegSet saved_regs =
7077 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
7078 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
7079
7080 protect_return_address();
7081 push(saved_regs, sp);
7082
7083 mov(lr, ExternalAddress(CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)));
7084 blr(lr);
7085 if (dst != c_rarg0) {
7086 mov(dst, c_rarg0);
7087 }
7088
7089 pop(saved_regs, sp);
7090 authenticate_return_address();
7091 }
7092
7093 #ifdef COMPILER2
7094 // C2 compiled method's prolog code
7095 // Moved here from aarch64.ad to support Valhalla code below
7096 void MacroAssembler::verified_entry(Compile* C, int sp_inc) {
7097 if (C->clinit_barrier_on_entry()) {
7098 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
7099
7100 Label L_skip_barrier;
7101
7102 mov_metadata(rscratch2, C->method()->holder()->constant_encoding());
7103 clinit_barrier(rscratch2, rscratch1, &L_skip_barrier);
7104 far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
7105 bind(L_skip_barrier);
7106 }
7107
7108 if (C->max_vector_size() > 0) {
7109 reinitialize_ptrue();
7110 }
7111
7112 int bangsize = C->output()->bang_size_in_bytes();
7113 if (C->output()->need_stack_bang(bangsize))
7114 generate_stack_overflow_check(bangsize);
7115
7116 // n.b. frame size includes space for return pc and rfp
7117 const long framesize = C->output()->frame_size_in_bytes();
7118 build_frame(framesize DEBUG_ONLY(COMMA sp_inc != 0));
7119
7120 if (C->needs_stack_repair()) {
7121 save_stack_increment(sp_inc, framesize);
7122 }
7123
7124 if (VerifyStackAtCalls) {
7125 Unimplemented();
7126 }
7127 }
7128 #endif // COMPILER2
7129
7130 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
7131 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
7132 // An inline type might be returned. If fields are in registers we
7133 // need to allocate an inline type instance and initialize it with
7134 // the value of the fields.
7135 Label skip;
7136 // We only need a new buffered inline type if a new one is not returned
7137 tbz(r0, 0, skip);
7138 int call_offset = -1;
7139
7140 // Be careful not to clobber r1-7 which hold returned fields
7141 // Also do not use callee-saved registers as these may be live in the interpreter
7142 Register tmp1 = r13, tmp2 = r14, klass = r15, r0_preserved = r12;
7143
7144 // The following code is similar to allocate_instance but has some slight differences,
7145 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
7146 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these.
7147 Label slow_case;
7148 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
7149 mov(r0_preserved, r0); // save r0 for slow_case since *_allocate may corrupt it when allocation failed
7150
7151 if (vk != nullptr) {
7152 // Called from C1, where the return type is statically known.
7153 movptr(klass, (intptr_t)vk->get_InlineKlass());
7154 jint lh = vk->layout_helper();
7155 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
7156 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
7157 tlab_allocate(r0, noreg, lh, tmp1, tmp2, slow_case);
7158 } else {
7159 b(slow_case);
7160 }
7161 } else {
7162 // Call from interpreter. R0 contains ((the InlineKlass* of the return type) | 0x01)
7163 andr(klass, r0, -2);
7164 if (UseTLAB) {
7165 ldrw(tmp2, Address(klass, Klass::layout_helper_offset()));
7166 tst(tmp2, Klass::_lh_instance_slow_path_bit);
7167 br(Assembler::NE, slow_case);
7168 tlab_allocate(r0, tmp2, 0, tmp1, tmp2, slow_case);
7169 } else {
7170 b(slow_case);
7171 }
7172 }
7173 if (UseTLAB) {
7174 // 2. Initialize buffered inline instance header
7175 Register buffer_obj = r0;
7176 if (UseCompactObjectHeaders) {
7177 ldr(rscratch1, Address(klass, Klass::prototype_header_offset()));
7178 str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes()));
7179 } else {
7180 mov(rscratch1, (intptr_t)markWord::inline_type_prototype().value());
7181 str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes()));
7182 store_klass_gap(buffer_obj, zr);
7183 if (vk == nullptr) {
7184 // store_klass corrupts klass, so save it for later use (interpreter case only).
7185 mov(tmp1, klass);
7186 }
7187 store_klass(buffer_obj, klass);
7188 klass = tmp1;
7189 }
7190 // 3. Initialize its fields with an inline class specific handler
7191 if (vk != nullptr) {
7192 far_call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
7193 } else {
7194 ldr(tmp1, Address(klass, InlineKlass::adr_members_offset()));
7195 ldr(tmp1, Address(tmp1, InlineKlass::pack_handler_offset()));
7196 blr(tmp1);
7197 }
7198
7199 membar(Assembler::StoreStore);
7200 b(skip);
7201 } else {
7202 // Must have already branched to slow_case above.
7203 DEBUG_ONLY(should_not_reach_here());
7204 }
7205 bind(slow_case);
7206 // We failed to allocate a new inline type, fall back to a runtime
7207 // call. Some oop field may be live in some registers but we can't
7208 // tell. That runtime call will take care of preserving them
7209 // across a GC if there's one.
7210 mov(r0, r0_preserved);
7211
7212 if (from_interpreter) {
7213 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
7214 } else {
7215 far_call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
7216 call_offset = offset();
7217 }
7218 membar(Assembler::StoreStore);
7219
7220 bind(skip);
7221 return call_offset;
7222 }
7223
7224 // Move a value between registers/stack slots and update the reg_state
7225 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
7226 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
7227 if (reg_state[to->value()] == reg_written) {
7228 return true; // Already written
7229 }
7230
7231 if (from != to && bt != T_VOID) {
7232 if (reg_state[to->value()] == reg_readonly) {
7233 return false; // Not yet writable
7234 }
7235 if (from->is_reg()) {
7236 if (to->is_reg()) {
7237 if (from->is_Register() && to->is_Register()) {
7238 mov(to->as_Register(), from->as_Register());
7239 } else if (from->is_FloatRegister() && to->is_FloatRegister()) {
7240 fmovd(to->as_FloatRegister(), from->as_FloatRegister());
7241 } else {
7242 ShouldNotReachHere();
7243 }
7244 } else {
7245 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
7246 Address to_addr = Address(sp, st_off);
7247 if (from->is_FloatRegister()) {
7248 if (bt == T_DOUBLE) {
7249 strd(from->as_FloatRegister(), to_addr);
7250 } else {
7251 assert(bt == T_FLOAT, "must be float");
7252 strs(from->as_FloatRegister(), to_addr);
7253 }
7254 } else {
7255 str(from->as_Register(), to_addr);
7256 }
7257 }
7258 } else {
7259 Address from_addr = Address(sp, from->reg2stack() * VMRegImpl::stack_slot_size);
7260 if (to->is_reg()) {
7261 if (to->is_FloatRegister()) {
7262 if (bt == T_DOUBLE) {
7263 ldrd(to->as_FloatRegister(), from_addr);
7264 } else {
7265 assert(bt == T_FLOAT, "must be float");
7266 ldrs(to->as_FloatRegister(), from_addr);
7267 }
7268 } else {
7269 ldr(to->as_Register(), from_addr);
7270 }
7271 } else {
7272 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
7273 ldr(rscratch1, from_addr);
7274 str(rscratch1, Address(sp, st_off));
7275 }
7276 }
7277 }
7278
7279 // Update register states
7280 reg_state[from->value()] = reg_writable;
7281 reg_state[to->value()] = reg_written;
7282 return true;
7283 }
7284
7285 // Calculate the extra stack space required for packing or unpacking inline
7286 // args and adjust the stack pointer
7287 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
7288 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
7289 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
7290 assert(sp_inc > 0, "sanity");
7291
7292 // Save a copy of the FP and LR here for deoptimization patching and frame walking
7293 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
7294
7295 // Adjust the stack pointer. This will be repaired on return by MacroAssembler::remove_frame
7296 if (sp_inc < (1 << 9)) {
7297 sub(sp, sp, sp_inc); // Fits in an immediate
7298 } else {
7299 mov(rscratch1, sp_inc);
7300 sub(sp, sp, rscratch1);
7301 }
7302
7303 return sp_inc + 2 * wordSize; // Account for the FP/LR space
7304 }
7305
7306 // Read all fields from an inline type oop and store the values in registers/stack slots
7307 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
7308 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
7309 RegState reg_state[]) {
7310 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
7311 assert(from->is_valid(), "source must be valid");
7312 bool progress = false;
7313 #ifdef ASSERT
7314 const int start_offset = offset();
7315 #endif
7316
7317 Label L_null, L_notNull;
7318 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
7319 Register tmp1 = r10;
7320 Register tmp2 = r11;
7321
7322 #ifndef ASSERT
7323 RegSet clobbered_gp_regs = MacroAssembler::call_clobbered_gp_registers();
7324 assert(clobbered_gp_regs.contains(tmp1), "tmp1 must be saved explicitly if it's not a clobber");
7325 assert(clobbered_gp_regs.contains(tmp2), "tmp2 must be saved explicitly if it's not a clobber");
7326 assert(clobbered_gp_regs.contains(r14), "r14 must be saved explicitly if it's not a clobber");
7327 #endif
7328
7329 Register fromReg = noreg;
7330 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, true);
7331 bool done = true;
7332 bool mark_done = true;
7333 VMReg toReg;
7334 BasicType bt;
7335 // Check if argument requires a null check
7336 bool null_check = false;
7337 VMReg nullCheckReg;
7338 while (stream.next(nullCheckReg, bt)) {
7339 if (sig->at(stream.sig_index())._offset == -1) {
7340 null_check = true;
7341 break;
7342 }
7343 }
7344 stream.reset(sig_index, to_index);
7345 while (stream.next(toReg, bt)) {
7346 assert(toReg->is_valid(), "destination must be valid");
7347 int idx = (int)toReg->value();
7348 if (reg_state[idx] == reg_readonly) {
7349 if (idx != from->value()) {
7350 mark_done = false;
7351 }
7352 done = false;
7353 continue;
7354 } else if (reg_state[idx] == reg_written) {
7355 continue;
7356 }
7357 assert(reg_state[idx] == reg_writable, "must be writable");
7358 reg_state[idx] = reg_written;
7359 progress = true;
7360
7361 if (fromReg == noreg) {
7362 if (from->is_reg()) {
7363 fromReg = from->as_Register();
7364 } else {
7365 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size;
7366 ldr(tmp1, Address(sp, st_off));
7367 fromReg = tmp1;
7368 }
7369 if (null_check) {
7370 // Nullable inline type argument, emit null check
7371 cbz(fromReg, L_null);
7372 }
7373 }
7374 int off = sig->at(stream.sig_index())._offset;
7375 if (off == -1) {
7376 assert(null_check, "Missing null check at");
7377 if (toReg->is_stack()) {
7378 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7379 mov(tmp2, 1);
7380 str(tmp2, Address(sp, st_off));
7381 } else {
7382 mov(toReg->as_Register(), 1);
7383 }
7384 continue;
7385 }
7386 if (sig->at(stream.sig_index())._vt_oop) {
7387 if (toReg->is_stack()) {
7388 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7389 str(fromReg, Address(sp, st_off));
7390 } else {
7391 mov(toReg->as_Register(), fromReg);
7392 }
7393 continue;
7394 }
7395 assert(off > 0, "offset in object should be positive");
7396 Address fromAddr = Address(fromReg, off);
7397 if (!toReg->is_FloatRegister()) {
7398 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
7399 if (is_reference_type(bt)) {
7400 load_heap_oop(dst, fromAddr, rscratch1, rscratch2);
7401 } else {
7402 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
7403 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
7404 }
7405 if (toReg->is_stack()) {
7406 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7407 str(dst, Address(sp, st_off));
7408 }
7409 } else if (bt == T_DOUBLE) {
7410 ldrd(toReg->as_FloatRegister(), fromAddr);
7411 } else {
7412 assert(bt == T_FLOAT, "must be float");
7413 ldrs(toReg->as_FloatRegister(), fromAddr);
7414 }
7415 }
7416 if (progress && null_check) {
7417 if (done) {
7418 b(L_notNull);
7419 bind(L_null);
7420 // Set null marker to zero to signal that the argument is null.
7421 // Also set all fields to zero since the runtime requires a canonical
7422 // representation of a flat null.
7423 stream.reset(sig_index, to_index);
7424 while (stream.next(toReg, bt)) {
7425 if (toReg->is_stack()) {
7426 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7427 str(zr, Address(sp, st_off));
7428 } else if (toReg->is_FloatRegister()) {
7429 mov(toReg->as_FloatRegister(), T2S, 0);
7430 } else {
7431 mov(toReg->as_Register(), zr);
7432 }
7433 }
7434 bind(L_notNull);
7435 } else {
7436 bind(L_null);
7437 }
7438 }
7439
7440 sig_index = stream.sig_index();
7441 to_index = stream.regs_index();
7442
7443 if (mark_done && reg_state[from->value()] != reg_written) {
7444 // This is okay because no one else will write to that slot
7445 reg_state[from->value()] = reg_writable;
7446 }
7447 from_index--;
7448 assert(progress || (start_offset == offset()), "should not emit code");
7449 return done;
7450 }
7451
7452 // Pack fields back into an inline type oop
7453 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
7454 VMRegPair* from, int from_count, int& from_index, VMReg to,
7455 RegState reg_state[], Register val_array) {
7456 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
7457 assert(to->is_valid(), "destination must be valid");
7458
7459 if (reg_state[to->value()] == reg_written) {
7460 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7461 return true; // Already written
7462 }
7463
7464 // The GC barrier expanded by store_heap_oop below may call into the
7465 // runtime so use callee-saved registers for any values that need to be
7466 // preserved. The GC barrier assembler should take care of saving the
7467 // Java argument registers.
7468 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
7469 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
7470 Register val_obj_tmp = r21;
7471 Register from_reg_tmp = r22;
7472 Register tmp1 = r14;
7473 Register tmp2 = r13;
7474 Register tmp3 = r12;
7475 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
7476
7477 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
7478
7479 if (reg_state[to->value()] == reg_readonly) {
7480 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
7481 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7482 return false; // Not yet writable
7483 }
7484 val_obj = val_obj_tmp;
7485 }
7486
7487 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
7488 VMReg fromReg;
7489 BasicType bt;
7490 Label L_null;
7491 while (stream.next(fromReg, bt)) {
7492 assert(fromReg->is_valid(), "source must be valid");
7493 reg_state[fromReg->value()] = reg_writable;
7494
7495 int off = sig->at(stream.sig_index())._offset;
7496 if (off == -1) {
7497 // Nullable inline type argument, emit null check
7498 Label L_notNull;
7499 if (fromReg->is_stack()) {
7500 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7501 ldrb(tmp2, Address(sp, ld_off));
7502 cbnz(tmp2, L_notNull);
7503 } else {
7504 cbnz(fromReg->as_Register(), L_notNull);
7505 }
7506 mov(val_obj, 0);
7507 b(L_null);
7508 bind(L_notNull);
7509 continue;
7510 }
7511 if (sig->at(stream.sig_index())._vt_oop) {
7512 if (fromReg->is_stack()) {
7513 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7514 ldr(val_obj, Address(sp, ld_off));
7515 } else {
7516 mov(val_obj, fromReg->as_Register());
7517 }
7518 cbnz(val_obj, L_null);
7519 // get the buffer from the just allocated pool of buffers
7520 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
7521 load_heap_oop(val_obj, Address(val_array, index), rscratch1, rscratch2);
7522 continue;
7523 }
7524
7525 assert(off > 0, "offset in object should be positive");
7526 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
7527
7528 // Pack the scalarized field into the value object.
7529 Address dst(val_obj, off);
7530 if (!fromReg->is_FloatRegister()) {
7531 Register src;
7532 if (fromReg->is_stack()) {
7533 src = from_reg_tmp;
7534 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7535 load_sized_value(src, Address(sp, ld_off), size_in_bytes, /* is_signed */ false);
7536 } else {
7537 src = fromReg->as_Register();
7538 }
7539 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
7540 if (is_reference_type(bt)) {
7541 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep val_obj valid.
7542 mov(tmp3, val_obj);
7543 Address dst_with_tmp3(tmp3, off);
7544 store_heap_oop(dst_with_tmp3, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
7545 } else {
7546 store_sized_value(dst, src, size_in_bytes);
7547 }
7548 } else if (bt == T_DOUBLE) {
7549 strd(fromReg->as_FloatRegister(), dst);
7550 } else {
7551 assert(bt == T_FLOAT, "must be float");
7552 strs(fromReg->as_FloatRegister(), dst);
7553 }
7554 }
7555 bind(L_null);
7556 sig_index = stream.sig_index();
7557 from_index = stream.regs_index();
7558
7559 assert(reg_state[to->value()] == reg_writable, "must have already been read");
7560 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
7561 assert(success, "to register must be writeable");
7562 return true;
7563 }
7564
7565 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
7566 return (reg->is_FloatRegister()) ? v8->as_VMReg() : r14->as_VMReg();
7567 }
7568
7569 void MacroAssembler::cache_wb(Address line) {
7570 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
7571 assert(line.index() == noreg, "index should be noreg");
7572 assert(line.offset() == 0, "offset should be 0");
7573 // would like to assert this
7574 // assert(line._ext.shift == 0, "shift should be zero");
7575 if (VM_Version::supports_dcpop()) {
7576 // writeback using clear virtual address to point of persistence
7577 dc(Assembler::CVAP, line.base());
7578 } else {
7579 // no need to generate anything as Unsafe.writebackMemory should
7580 // never invoke this stub
7581 }
7582 }
7583
7584 void MacroAssembler::cache_wbsync(bool is_pre) {
7585 // we only need a barrier post sync
7586 if (!is_pre) {
7587 membar(Assembler::AnyAny);
7588 }
7589 }
7590
7591 void MacroAssembler::verify_sve_vector_length(Register tmp) {
7592 if (!UseSVE || VM_Version::get_max_supported_sve_vector_length() == FloatRegister::sve_vl_min) {
7593 return;
7594 }
7595 // Make sure that native code does not change SVE vector length.
7596 Label verify_ok;
7597 movw(tmp, zr);
7598 sve_inc(tmp, B);
7599 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length());
7600 br(EQ, verify_ok);
7601 stop("Error: SVE vector length has changed since jvm startup");
7602 bind(verify_ok);
7603 }
7604
7605 void MacroAssembler::verify_ptrue() {
7606 Label verify_ok;
7607 if (!UseSVE) {
7608 return;
7609 }
7610 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
7611 sve_dec(rscratch1, B);
7612 cbz(rscratch1, verify_ok);
7613 stop("Error: the preserved predicate register (p7) elements are not all true");
7614 bind(verify_ok);
7615 }
7616
7617 void MacroAssembler::safepoint_isb() {
7618 isb();
7619 #ifndef PRODUCT
7620 if (VerifyCrossModifyFence) {
7621 // Clear the thread state.
7622 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
7623 }
7624 #endif
7625 }
7626
7627 #ifndef PRODUCT
7628 void MacroAssembler::verify_cross_modify_fence_not_required() {
7629 if (VerifyCrossModifyFence) {
7630 // Check if thread needs a cross modify fence.
7631 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
7632 Label fence_not_required;
7633 cbz(rscratch1, fence_not_required);
7634 // If it does then fail.
7635 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure)));
7636 mov(c_rarg0, rthread);
7637 blr(rscratch1);
7638 bind(fence_not_required);
7639 }
7640 }
7641 #endif
7642
7643 void MacroAssembler::spin_wait() {
7644 block_comment("spin_wait {");
7645 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
7646 switch (VM_Version::spin_wait_desc().inst()) {
7647 case SpinWait::NOP:
7648 nop();
7649 break;
7650 case SpinWait::ISB:
7651 isb();
7652 break;
7653 case SpinWait::YIELD:
7654 yield();
7655 break;
7656 case SpinWait::SB:
7657 assert(VM_Version::supports_sb(), "current CPU does not support SB instruction");
7658 sb();
7659 break;
7660 case SpinWait::WFET:
7661 spin_wait_wfet(VM_Version::spin_wait_desc().delay());
7662 break;
7663 default:
7664 ShouldNotReachHere();
7665 }
7666 }
7667 block_comment("}");
7668 }
7669
7670 void MacroAssembler::spin_wait_wfet(int delay_ns) {
7671 // The sequence assumes CNTFRQ_EL0 is fixed to 1GHz. The assumption is valid
7672 // starting from Armv8.6, according to the "D12.1.2 The system counter" of the
7673 // Arm Architecture Reference Manual for A-profile architecture version M.a.a.
7674 // This is sufficient because FEAT_WFXT is introduced from Armv8.6.
7675 Register target = rscratch1;
7676 Register current = rscratch2;
7677 get_cntvctss_el0(current);
7678 add(target, current, delay_ns);
7679
7680 Label L_wait_loop;
7681 bind(L_wait_loop);
7682
7683 wfet(target);
7684 get_cntvctss_el0(current);
7685
7686 cmp(current, target);
7687 br(LT, L_wait_loop);
7688
7689 sb();
7690 }
7691
7692 // Stack frame creation/removal
7693
7694 void MacroAssembler::enter(bool strip_ret_addr) {
7695 if (strip_ret_addr) {
7696 // Addresses can only be signed once. If there are multiple nested frames being created
7697 // in the same function, then the return address needs stripping first.
7698 strip_return_address();
7699 }
7700 protect_return_address();
7701 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
7702 mov(rfp, sp);
7703 }
7704
7705 void MacroAssembler::leave() {
7706 mov(sp, rfp);
7707 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
7708 authenticate_return_address();
7709 }
7710
7711 // ROP Protection
7712 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/
7713 // destroying stack frames or whenever directly loading/storing the LR to memory.
7714 // If ROP protection is not set then these functions are no-ops.
7715 // For more details on PAC see pauth_aarch64.hpp.
7716
7717 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory.
7718 // Uses value zero as the modifier.
7719 //
7720 void MacroAssembler::protect_return_address() {
7721 if (VM_Version::use_rop_protection()) {
7722 check_return_address();
7723 paciaz();
7724 }
7725 }
7726
7727 // Sign the return value in the given register. Use before updating the LR in the existing stack
7728 // frame for the current function.
7729 // Uses value zero as the modifier.
7730 //
7731 void MacroAssembler::protect_return_address(Register return_reg) {
7732 if (VM_Version::use_rop_protection()) {
7733 check_return_address(return_reg);
7734 paciza(return_reg);
7735 }
7736 }
7737
7738 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory.
7739 // Uses value zero as the modifier.
7740 //
7741 void MacroAssembler::authenticate_return_address() {
7742 if (VM_Version::use_rop_protection()) {
7743 autiaz();
7744 check_return_address();
7745 }
7746 }
7747
7748 // Authenticate the return value in the given register. Use before updating the LR in the existing
7749 // stack frame for the current function.
7750 // Uses value zero as the modifier.
7751 //
7752 void MacroAssembler::authenticate_return_address(Register return_reg) {
7753 if (VM_Version::use_rop_protection()) {
7754 autiza(return_reg);
7755 check_return_address(return_reg);
7756 }
7757 }
7758
7759 // Strip any PAC data from LR without performing any authentication. Use with caution - only if
7760 // there is no guaranteed way of authenticating the LR.
7761 //
7762 void MacroAssembler::strip_return_address() {
7763 if (VM_Version::use_rop_protection()) {
7764 xpaclri();
7765 }
7766 }
7767
7768 #ifndef PRODUCT
7769 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only
7770 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point
7771 // it is difficult to debug back to the callee function.
7772 // This function simply loads from the address in the given register.
7773 // Use directly after authentication to catch authentication failures.
7774 // Also use before signing to check that the pointer is valid and hasn't already been signed.
7775 //
7776 void MacroAssembler::check_return_address(Register return_reg) {
7777 if (VM_Version::use_rop_protection()) {
7778 ldr(zr, Address(return_reg));
7779 }
7780 }
7781 #endif
7782
7783 // The java_calling_convention describes stack locations as ideal slots on
7784 // a frame with no abi restrictions. Since we must observe abi restrictions
7785 // (like the placement of the register window) the slots must be biased by
7786 // the following value.
7787 static int reg2offset_in(VMReg r) {
7788 // Account for saved rfp and lr
7789 // This should really be in_preserve_stack_slots
7790 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
7791 }
7792
7793 static int reg2offset_out(VMReg r) {
7794 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
7795 }
7796
7797 // On 64bit we will store integer like items to the stack as
7798 // 64bits items (AArch64 ABI) even though java would only store
7799 // 32bits for a parameter. On 32bit it will simply be 32bits
7800 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
7801 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
7802 if (src.first()->is_stack()) {
7803 if (dst.first()->is_stack()) {
7804 // stack to stack
7805 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7806 str(tmp, Address(sp, reg2offset_out(dst.first())));
7807 } else {
7808 // stack to reg
7809 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
7810 }
7811 } else if (dst.first()->is_stack()) {
7812 // reg to stack
7813 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
7814 } else {
7815 if (dst.first() != src.first()) {
7816 sxtw(dst.first()->as_Register(), src.first()->as_Register());
7817 }
7818 }
7819 }
7820
7821 // An oop arg. Must pass a handle not the oop itself
7822 void MacroAssembler::object_move(
7823 OopMap* map,
7824 int oop_handle_offset,
7825 int framesize_in_slots,
7826 VMRegPair src,
7827 VMRegPair dst,
7828 bool is_receiver,
7829 int* receiver_offset) {
7830
7831 // must pass a handle. First figure out the location we use as a handle
7832
7833 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register();
7834
7835 // See if oop is null if it is we need no handle
7836
7837 if (src.first()->is_stack()) {
7838
7839 // Oop is already on the stack as an argument
7840 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
7841 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
7842 if (is_receiver) {
7843 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
7844 }
7845
7846 ldr(rscratch1, Address(rfp, reg2offset_in(src.first())));
7847 lea(rHandle, Address(rfp, reg2offset_in(src.first())));
7848 // conditionally move a null
7849 cmp(rscratch1, zr);
7850 csel(rHandle, zr, rHandle, Assembler::EQ);
7851 } else {
7852
7853 // Oop is in an a register we must store it to the space we reserve
7854 // on the stack for oop_handles and pass a handle if oop is non-null
7855
7856 const Register rOop = src.first()->as_Register();
7857 int oop_slot;
7858 if (rOop == j_rarg0)
7859 oop_slot = 0;
7860 else if (rOop == j_rarg1)
7861 oop_slot = 1;
7862 else if (rOop == j_rarg2)
7863 oop_slot = 2;
7864 else if (rOop == j_rarg3)
7865 oop_slot = 3;
7866 else if (rOop == j_rarg4)
7867 oop_slot = 4;
7868 else if (rOop == j_rarg5)
7869 oop_slot = 5;
7870 else if (rOop == j_rarg6)
7871 oop_slot = 6;
7872 else {
7873 assert(rOop == j_rarg7, "wrong register");
7874 oop_slot = 7;
7875 }
7876
7877 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
7878 int offset = oop_slot*VMRegImpl::stack_slot_size;
7879
7880 map->set_oop(VMRegImpl::stack2reg(oop_slot));
7881 // Store oop in handle area, may be null
7882 str(rOop, Address(sp, offset));
7883 if (is_receiver) {
7884 *receiver_offset = offset;
7885 }
7886
7887 cmp(rOop, zr);
7888 lea(rHandle, Address(sp, offset));
7889 // conditionally move a null
7890 csel(rHandle, zr, rHandle, Assembler::EQ);
7891 }
7892
7893 // If arg is on the stack then place it otherwise it is already in correct reg.
7894 if (dst.first()->is_stack()) {
7895 str(rHandle, Address(sp, reg2offset_out(dst.first())));
7896 }
7897 }
7898
7899 // A float arg may have to do float reg int reg conversion
7900 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
7901 if (src.first()->is_stack()) {
7902 if (dst.first()->is_stack()) {
7903 ldrw(tmp, Address(rfp, reg2offset_in(src.first())));
7904 strw(tmp, Address(sp, reg2offset_out(dst.first())));
7905 } else {
7906 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7907 }
7908 } else if (src.first() != dst.first()) {
7909 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7910 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7911 else
7912 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7913 }
7914 }
7915
7916 // A long move
7917 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
7918 if (src.first()->is_stack()) {
7919 if (dst.first()->is_stack()) {
7920 // stack to stack
7921 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7922 str(tmp, Address(sp, reg2offset_out(dst.first())));
7923 } else {
7924 // stack to reg
7925 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
7926 }
7927 } else if (dst.first()->is_stack()) {
7928 // reg to stack
7929 // Do we really have to sign extend???
7930 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
7931 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
7932 } else {
7933 if (dst.first() != src.first()) {
7934 mov(dst.first()->as_Register(), src.first()->as_Register());
7935 }
7936 }
7937 }
7938
7939
7940 // A double move
7941 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
7942 if (src.first()->is_stack()) {
7943 if (dst.first()->is_stack()) {
7944 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7945 str(tmp, Address(sp, reg2offset_out(dst.first())));
7946 } else {
7947 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7948 }
7949 } else if (src.first() != dst.first()) {
7950 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7951 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7952 else
7953 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7954 }
7955 }
7956
7957 // Implements fast-locking.
7958 //
7959 // - obj: the object to be locked
7960 // - t1, t2, t3: temporary registers, will be destroyed
7961 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding).
7962 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow) {
7963 assert_different_registers(basic_lock, obj, t1, t2, t3, rscratch1);
7964
7965 Label push;
7966 const Register top = t1;
7967 const Register mark = t2;
7968 const Register t = t3;
7969
7970 // Preload the markWord. It is important that this is the first
7971 // instruction emitted as it is part of C1's null check semantics.
7972 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7973
7974 if (UseObjectMonitorTable) {
7975 // Clear cache in case fast locking succeeds or we need to take the slow-path.
7976 str(zr, Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))));
7977 }
7978
7979 if (DiagnoseSyncOnValueBasedClasses != 0) {
7980 load_klass(t1, obj);
7981 ldrb(t1, Address(t1, Klass::misc_flags_offset()));
7982 tst(t1, KlassFlags::_misc_is_value_based_class);
7983 br(Assembler::NE, slow);
7984 }
7985
7986 // Check if the lock-stack is full.
7987 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7988 cmpw(top, (unsigned)LockStack::end_offset());
7989 br(Assembler::GE, slow);
7990
7991 // Check for recursion.
7992 subw(t, top, oopSize);
7993 ldr(t, Address(rthread, t));
7994 cmp(obj, t);
7995 br(Assembler::EQ, push);
7996
7997 // Check header for monitor (0b10).
7998 tst(mark, markWord::monitor_value);
7999 br(Assembler::NE, slow);
8000
8001 // Try to lock. Transition lock bits 0b01 => 0b00
8002 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
8003 orr(mark, mark, markWord::unlocked_value);
8004 // Mask inline_type bit such that we go to the slow path if object is an inline type
8005 andr(mark, mark, ~((int) markWord::inline_type_bit_in_place));
8006
8007 eor(t, mark, markWord::unlocked_value);
8008 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
8009 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
8010 br(Assembler::NE, slow);
8011
8012 bind(push);
8013 // After successful lock, push object on lock-stack.
8014 str(obj, Address(rthread, top));
8015 addw(top, top, oopSize);
8016 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
8017 }
8018
8019 // Implements fast-unlocking.
8020 //
8021 // - obj: the object to be unlocked
8022 // - t1, t2, t3: temporary registers
8023 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
8024 void MacroAssembler::fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
8025 // cmpxchg clobbers rscratch1.
8026 assert_different_registers(obj, t1, t2, t3, rscratch1);
8027
8028 #ifdef ASSERT
8029 {
8030 // Check for lock-stack underflow.
8031 Label stack_ok;
8032 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
8033 cmpw(t1, (unsigned)LockStack::start_offset());
8034 br(Assembler::GE, stack_ok);
8035 STOP("Lock-stack underflow");
8036 bind(stack_ok);
8037 }
8038 #endif
8039
8040 Label unlocked, push_and_slow;
8041 const Register top = t1;
8042 const Register mark = t2;
8043 const Register t = t3;
8044
8045 // Check if obj is top of lock-stack.
8046 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
8047 subw(top, top, oopSize);
8048 ldr(t, Address(rthread, top));
8049 cmp(obj, t);
8050 br(Assembler::NE, slow);
8051
8052 // Pop lock-stack.
8053 DEBUG_ONLY(str(zr, Address(rthread, top));)
8054 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
8055
8056 // Check if recursive.
8057 subw(t, top, oopSize);
8058 ldr(t, Address(rthread, t));
8059 cmp(obj, t);
8060 br(Assembler::EQ, unlocked);
8061
8062 // Not recursive. Check header for monitor (0b10).
8063 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
8064 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow);
8065
8066 #ifdef ASSERT
8067 // Check header not unlocked (0b01).
8068 Label not_unlocked;
8069 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked);
8070 stop("fast_unlock already unlocked");
8071 bind(not_unlocked);
8072 #endif
8073
8074 // Try to unlock. Transition lock bits 0b00 => 0b01
8075 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
8076 orr(t, mark, markWord::unlocked_value);
8077 cmpxchg(obj, mark, t, Assembler::xword,
8078 /*acquire*/ false, /*release*/ true, /*weak*/ false, noreg);
8079 br(Assembler::EQ, unlocked);
8080
8081 bind(push_and_slow);
8082 // Restore lock-stack and handle the unlock in runtime.
8083 DEBUG_ONLY(str(obj, Address(rthread, top));)
8084 addw(top, top, oopSize);
8085 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
8086 b(slow);
8087
8088 bind(unlocked);
8089 }