1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "ci/ciEnv.hpp"
29 #include "ci/ciInlineKlass.hpp"
30 #include "code/compiledIC.hpp"
31 #include "compiler/compileTask.hpp"
32 #include "compiler/disassembler.hpp"
33 #include "compiler/oopMap.hpp"
34 #include "gc/shared/barrierSet.hpp"
35 #include "gc/shared/barrierSetAssembler.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/cardTable.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/tlab_globals.hpp"
40 #include "interpreter/bytecodeHistogram.hpp"
41 #include "interpreter/interpreter.hpp"
42 #include "interpreter/interpreterRuntime.hpp"
43 #include "jvm.h"
44 #include "memory/resourceArea.hpp"
45 #include "memory/universe.hpp"
46 #include "nativeInst_aarch64.hpp"
47 #include "oops/accessDecorators.hpp"
48 #include "oops/compressedKlass.inline.hpp"
49 #include "oops/compressedOops.inline.hpp"
50 #include "oops/klass.inline.hpp"
51 #include "oops/resolvedFieldEntry.hpp"
52 #include "runtime/arguments.hpp"
53 #include "runtime/continuation.hpp"
54 #include "runtime/globals.hpp"
55 #include "runtime/icache.hpp"
56 #include "runtime/interfaceSupport.inline.hpp"
57 #include "runtime/javaThread.hpp"
58 #include "runtime/jniHandles.inline.hpp"
59 #include "runtime/sharedRuntime.hpp"
60 #include "runtime/signature_cc.hpp"
61 #include "runtime/stubRoutines.hpp"
62 #include "utilities/globalDefinitions.hpp"
63 #include "utilities/powerOfTwo.hpp"
64 #include "vmreg_aarch64.inline.hpp"
65 #ifdef COMPILER1
66 #include "c1/c1_LIRAssembler.hpp"
67 #endif
68 #ifdef COMPILER2
69 #include "oops/oop.hpp"
70 #include "opto/compile.hpp"
71 #include "opto/node.hpp"
72 #include "opto/output.hpp"
73 #endif
74
75 #include <sys/types.h>
76
77 #ifdef PRODUCT
78 #define BLOCK_COMMENT(str) /* nothing */
79 #else
80 #define BLOCK_COMMENT(str) block_comment(str)
81 #endif
82 #define STOP(str) stop(str);
83 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
84
85 #ifdef ASSERT
86 extern "C" void disnm(intptr_t p);
87 #endif
88 // Target-dependent relocation processing
89 //
90 // Instruction sequences whose target may need to be retrieved or
91 // patched are distinguished by their leading instruction, sorting
92 // them into three main instruction groups and related subgroups.
93 //
94 // 1) Branch, Exception and System (insn count = 1)
95 // 1a) Unconditional branch (immediate):
96 // b/bl imm19
97 // 1b) Compare & branch (immediate):
98 // cbz/cbnz Rt imm19
99 // 1c) Test & branch (immediate):
100 // tbz/tbnz Rt imm14
101 // 1d) Conditional branch (immediate):
102 // b.cond imm19
103 //
104 // 2) Loads and Stores (insn count = 1)
105 // 2a) Load register literal:
106 // ldr Rt imm19
107 //
108 // 3) Data Processing Immediate (insn count = 2 or 3)
109 // 3a) PC-rel. addressing
110 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12
111 // adr/adrp Rx imm21; add Ry Rx #imm12
112 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page]
113 // adr/adrp Rx imm21
114 // adr/adrp Rx imm21; movk Rx #imm16<<32
115 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page
116 // The latter form can only happen when the target is an
117 // ExternalAddress, and (by definition) ExternalAddresses don't
118 // move. Because of that property, there is never any need to
119 // patch the last of the three instructions. However,
120 // MacroAssembler::target_addr_for_insn takes all three
121 // instructions into account and returns the correct address.
122 // 3b) Move wide (immediate)
123 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32;
124 //
125 // A switch on a subset of the instruction's bits provides an
126 // efficient dispatch to these subcases.
127 //
128 // insn[28:26] -> main group ('x' == don't care)
129 // 00x -> UNALLOCATED
130 // 100 -> Data Processing Immediate
131 // 101 -> Branch, Exception and System
132 // x1x -> Loads and Stores
133 //
134 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care).
135 // n.b. in some cases extra bits need to be checked to verify the
136 // instruction is as expected
137 //
138 // 1) ... xx101x Branch, Exception and System
139 // 1a) 00___x Unconditional branch (immediate)
140 // 1b) 01___0 Compare & branch (immediate)
141 // 1c) 01___1 Test & branch (immediate)
142 // 1d) 10___0 Conditional branch (immediate)
143 // other Should not happen
144 //
145 // 2) ... xxx1x0 Loads and Stores
146 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0)
147 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0)
148 // strictly should be 64 bit non-FP/SIMD i.e.
149 // 0101_000 (i.e. requires insn[31:24] == 01011000)
150 //
151 // 3) ... xx100x Data Processing Immediate
152 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0)
153 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01)
154 // strictly should be 64 bit movz #imm16<<0
155 // 110___10100 (i.e. requires insn[31:21] == 11010010100)
156 //
157
158 static uint32_t insn_at(address insn_addr, int n) {
159 return ((uint32_t*)insn_addr)[n];
160 }
161
162 template<typename T>
163 class RelocActions : public AllStatic {
164
165 public:
166
167 static int ALWAYSINLINE run(address insn_addr, address &target) {
168 int instructions = 1;
169 uint32_t insn = insn_at(insn_addr, 0);
170
171 uint32_t dispatch = Instruction_aarch64::extract(insn, 30, 25);
172 switch(dispatch) {
173 case 0b001010:
174 case 0b001011: {
175 instructions = T::unconditionalBranch(insn_addr, target);
176 break;
177 }
178 case 0b101010: // Conditional branch (immediate)
179 case 0b011010: { // Compare & branch (immediate)
180 instructions = T::conditionalBranch(insn_addr, target);
181 break;
182 }
183 case 0b011011: {
184 instructions = T::testAndBranch(insn_addr, target);
185 break;
186 }
187 case 0b001100:
188 case 0b001110:
189 case 0b011100:
190 case 0b011110:
191 case 0b101100:
192 case 0b101110:
193 case 0b111100:
194 case 0b111110: {
195 // load/store
196 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
197 // Load register (literal)
198 instructions = T::loadStore(insn_addr, target);
199 break;
200 } else {
201 // nothing to do
202 assert(target == nullptr, "did not expect to relocate target for polling page load");
203 }
204 break;
205 }
206 case 0b001000:
207 case 0b011000:
208 case 0b101000:
209 case 0b111000: {
210 // adr/adrp
211 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
212 int shift = Instruction_aarch64::extract(insn, 31, 31);
213 if (shift) {
214 uint32_t insn2 = insn_at(insn_addr, 1);
215 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
216 Instruction_aarch64::extract(insn, 4, 0) ==
217 Instruction_aarch64::extract(insn2, 9, 5)) {
218 instructions = T::adrp(insn_addr, target, T::adrpMem);
219 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
220 Instruction_aarch64::extract(insn, 4, 0) ==
221 Instruction_aarch64::extract(insn2, 4, 0)) {
222 instructions = T::adrp(insn_addr, target, T::adrpAdd);
223 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
224 Instruction_aarch64::extract(insn, 4, 0) ==
225 Instruction_aarch64::extract(insn2, 4, 0)) {
226 instructions = T::adrp(insn_addr, target, T::adrpMovk);
227 } else {
228 ShouldNotReachHere();
229 }
230 } else {
231 instructions = T::adr(insn_addr, target);
232 }
233 break;
234 }
235 case 0b001001:
236 case 0b011001:
237 case 0b101001:
238 case 0b111001: {
239 instructions = T::immediate(insn_addr, target);
240 break;
241 }
242 default: {
243 ShouldNotReachHere();
244 }
245 }
246
247 T::verify(insn_addr, target);
248 return instructions * NativeInstruction::instruction_size;
249 }
250 };
251
252 class Patcher : public AllStatic {
253 public:
254 static int unconditionalBranch(address insn_addr, address &target) {
255 intptr_t offset = (target - insn_addr) >> 2;
256 Instruction_aarch64::spatch(insn_addr, 25, 0, offset);
257 return 1;
258 }
259 static int conditionalBranch(address insn_addr, address &target) {
260 intptr_t offset = (target - insn_addr) >> 2;
261 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
262 return 1;
263 }
264 static int testAndBranch(address insn_addr, address &target) {
265 intptr_t offset = (target - insn_addr) >> 2;
266 Instruction_aarch64::spatch(insn_addr, 18, 5, offset);
267 return 1;
268 }
269 static int loadStore(address insn_addr, address &target) {
270 intptr_t offset = (target - insn_addr) >> 2;
271 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
272 return 1;
273 }
274 static int adr(address insn_addr, address &target) {
275 #ifdef ASSERT
276 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
277 #endif
278 // PC-rel. addressing
279 ptrdiff_t offset = target - insn_addr;
280 int offset_lo = offset & 3;
281 offset >>= 2;
282 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
283 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
284 return 1;
285 }
286 template<typename U>
287 static int adrp(address insn_addr, address &target, U inner) {
288 int instructions = 1;
289 #ifdef ASSERT
290 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
291 #endif
292 ptrdiff_t offset = target - insn_addr;
293 instructions = 2;
294 precond(inner != nullptr);
295 // Give the inner reloc a chance to modify the target.
296 address adjusted_target = target;
297 instructions = inner(insn_addr, adjusted_target);
298 uintptr_t pc_page = (uintptr_t)insn_addr >> 12;
299 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12;
300 offset = adr_page - pc_page;
301 int offset_lo = offset & 3;
302 offset >>= 2;
303 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
304 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
305 return instructions;
306 }
307 static int adrpMem(address insn_addr, address &target) {
308 uintptr_t dest = (uintptr_t)target;
309 int offset_lo = dest & 0xfff;
310 uint32_t insn2 = insn_at(insn_addr, 1);
311 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
312 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size);
313 guarantee(((dest >> size) << size) == dest, "misaligned target");
314 return 2;
315 }
316 static int adrpAdd(address insn_addr, address &target) {
317 uintptr_t dest = (uintptr_t)target;
318 int offset_lo = dest & 0xfff;
319 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo);
320 return 2;
321 }
322 static int adrpMovk(address insn_addr, address &target) {
323 uintptr_t dest = uintptr_t(target);
324 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32);
325 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL);
326 target = address(dest);
327 return 2;
328 }
329 static int immediate(address insn_addr, address &target) {
330 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010100, "must be");
331 uint64_t dest = (uint64_t)target;
332 // Move wide constant
333 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
334 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
335 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
336 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
337 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
338 return 3;
339 }
340 static void verify(address insn_addr, address &target) {
341 #ifdef ASSERT
342 address address_is = MacroAssembler::target_addr_for_insn(insn_addr);
343 if (!(address_is == target)) {
344 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target);
345 disnm((intptr_t)insn_addr);
346 assert(address_is == target, "should be");
347 }
348 #endif
349 }
350 };
351
352 // If insn1 and insn2 use the same register to form an address, either
353 // by an offsetted LDR or a simple ADD, return the offset. If the
354 // second instruction is an LDR, the offset may be scaled.
355 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) {
356 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
357 Instruction_aarch64::extract(insn1, 4, 0) ==
358 Instruction_aarch64::extract(insn2, 9, 5)) {
359 // Load/store register (unsigned immediate)
360 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
361 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
362 byte_offset <<= size;
363 return true;
364 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
365 Instruction_aarch64::extract(insn1, 4, 0) ==
366 Instruction_aarch64::extract(insn2, 4, 0)) {
367 // add (immediate)
368 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
369 return true;
370 }
371 return false;
372 }
373
374 class AArch64Decoder : public AllStatic {
375 public:
376
377 static int loadStore(address insn_addr, address &target) {
378 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
379 target = insn_addr + (offset << 2);
380 return 1;
381 }
382 static int unconditionalBranch(address insn_addr, address &target) {
383 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 25, 0);
384 target = insn_addr + (offset << 2);
385 return 1;
386 }
387 static int conditionalBranch(address insn_addr, address &target) {
388 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
389 target = address(((uint64_t)insn_addr + (offset << 2)));
390 return 1;
391 }
392 static int testAndBranch(address insn_addr, address &target) {
393 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 18, 5);
394 target = address(((uint64_t)insn_addr + (offset << 2)));
395 return 1;
396 }
397 static int adr(address insn_addr, address &target) {
398 // PC-rel. addressing
399 uint32_t insn = insn_at(insn_addr, 0);
400 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
401 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
402 target = address((uint64_t)insn_addr + offset);
403 return 1;
404 }
405 template<typename U>
406 static int adrp(address insn_addr, address &target, U inner) {
407 uint32_t insn = insn_at(insn_addr, 0);
408 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
409 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
410 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
411 int shift = 12;
412 offset <<= shift;
413 uint64_t target_page = ((uint64_t)insn_addr) + offset;
414 target_page &= ((uint64_t)-1) << shift;
415 uint32_t insn2 = insn_at(insn_addr, 1);
416 target = address(target_page);
417 precond(inner != nullptr);
418 inner(insn_addr, target);
419 return 2;
420 }
421 static int adrpMem(address insn_addr, address &target) {
422 uint32_t insn2 = insn_at(insn_addr, 1);
423 // Load/store register (unsigned immediate)
424 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
425 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
426 byte_offset <<= size;
427 target += byte_offset;
428 return 2;
429 }
430 static int adrpAdd(address insn_addr, address &target) {
431 uint32_t insn2 = insn_at(insn_addr, 1);
432 // add (immediate)
433 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
434 target += byte_offset;
435 return 2;
436 }
437 static int adrpMovk(address insn_addr, address &target) {
438 uint32_t insn2 = insn_at(insn_addr, 1);
439 uint64_t dest = uint64_t(target);
440 dest = (dest & 0xffff0000ffffffff) |
441 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
442 target = address(dest);
443
444 // We know the destination 4k page. Maybe we have a third
445 // instruction.
446 uint32_t insn = insn_at(insn_addr, 0);
447 uint32_t insn3 = insn_at(insn_addr, 2);
448 ptrdiff_t byte_offset;
449 if (offset_for(insn, insn3, byte_offset)) {
450 target += byte_offset;
451 return 3;
452 } else {
453 return 2;
454 }
455 }
456 static int immediate(address insn_addr, address &target) {
457 uint32_t *insns = (uint32_t *)insn_addr;
458 assert(Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010100, "must be");
459 // Move wide constant: movz, movk, movk. See movptr().
460 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
461 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
462 target = address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5))
463 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
464 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
465 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
466 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
467 return 3;
468 }
469 static void verify(address insn_addr, address &target) {
470 }
471 };
472
473 address MacroAssembler::target_addr_for_insn(address insn_addr) {
474 address target;
475 RelocActions<AArch64Decoder>::run(insn_addr, target);
476 return target;
477 }
478
479 // Patch any kind of instruction; there may be several instructions.
480 // Return the total length (in bytes) of the instructions.
481 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) {
482 return RelocActions<Patcher>::run(insn_addr, target);
483 }
484
485 int MacroAssembler::patch_oop(address insn_addr, address o) {
486 int instructions;
487 unsigned insn = *(unsigned*)insn_addr;
488 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
489
490 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
491 // narrow OOPs by setting the upper 16 bits in the first
492 // instruction.
493 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
494 // Move narrow OOP
495 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
496 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
497 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
498 instructions = 2;
499 } else {
500 // Move wide OOP
501 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
502 uintptr_t dest = (uintptr_t)o;
503 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
504 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
505 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
506 instructions = 3;
507 }
508 return instructions * NativeInstruction::instruction_size;
509 }
510
511 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
512 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
513 // We encode narrow ones by setting the upper 16 bits in the first
514 // instruction.
515 NativeInstruction *insn = nativeInstruction_at(insn_addr);
516 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
517 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
518
519 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
520 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
521 return 2 * NativeInstruction::instruction_size;
522 }
523
524 address MacroAssembler::target_addr_for_insn_or_null(address insn_addr) {
525 if (NativeInstruction::is_ldrw_to_zr(insn_addr)) {
526 return nullptr;
527 }
528 return MacroAssembler::target_addr_for_insn(insn_addr);
529 }
530
531 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp) {
532 ldr(tmp, Address(rthread, JavaThread::polling_word_offset()));
533 if (at_return) {
534 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
535 // we may safely use the sp instead to perform the stack watermark check.
536 cmp(in_nmethod ? sp : rfp, tmp);
537 br(Assembler::HI, slow_path);
538 } else {
539 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path);
540 }
541 }
542
543 void MacroAssembler::rt_call(address dest, Register tmp) {
544 CodeBlob *cb = CodeCache::find_blob(dest);
545 if (cb) {
546 far_call(RuntimeAddress(dest));
547 } else {
548 lea(tmp, RuntimeAddress(dest));
549 blr(tmp);
550 }
551 }
552
553 void MacroAssembler::push_cont_fastpath(Register java_thread) {
554 if (!Continuations::enabled()) return;
555 Label done;
556 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
557 cmp(sp, rscratch1);
558 br(Assembler::LS, done);
559 mov(rscratch1, sp); // we can't use sp as the source in str
560 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
561 bind(done);
562 }
563
564 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
565 if (!Continuations::enabled()) return;
566 Label done;
567 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
568 cmp(sp, rscratch1);
569 br(Assembler::LO, done);
570 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset()));
571 bind(done);
572 }
573
574 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
575 // we must set sp to zero to clear frame
576 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
577
578 // must clear fp, so that compiled frames are not confused; it is
579 // possible that we need it only for debugging
580 if (clear_fp) {
581 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
582 }
583
584 // Always clear the pc because it could have been set by make_walkable()
585 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
586 }
587
588 // Calls to C land
589 //
590 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
591 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
592 // has to be reset to 0. This is required to allow proper stack traversal.
593 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
594 Register last_java_fp,
595 Register last_java_pc,
596 Register scratch) {
597
598 if (last_java_pc->is_valid()) {
599 str(last_java_pc, Address(rthread,
600 JavaThread::frame_anchor_offset()
601 + JavaFrameAnchor::last_Java_pc_offset()));
602 }
603
604 // determine last_java_sp register
605 if (last_java_sp == sp) {
606 mov(scratch, sp);
607 last_java_sp = scratch;
608 } else if (!last_java_sp->is_valid()) {
609 last_java_sp = esp;
610 }
611
612 // last_java_fp is optional
613 if (last_java_fp->is_valid()) {
614 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
615 }
616
617 // We must set sp last.
618 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
619 }
620
621 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
622 Register last_java_fp,
623 address last_java_pc,
624 Register scratch) {
625 assert(last_java_pc != nullptr, "must provide a valid PC");
626
627 adr(scratch, last_java_pc);
628 str(scratch, Address(rthread,
629 JavaThread::frame_anchor_offset()
630 + JavaFrameAnchor::last_Java_pc_offset()));
631
632 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
633 }
634
635 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
636 Register last_java_fp,
637 Label &L,
638 Register scratch) {
639 if (L.is_bound()) {
640 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
641 } else {
642 InstructionMark im(this);
643 L.add_patch_at(code(), locator());
644 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch);
645 }
646 }
647
648 static inline bool target_needs_far_branch(address addr) {
649 if (AOTCodeCache::is_on_for_dump()) {
650 return true;
651 }
652 // codecache size <= 128M
653 if (!MacroAssembler::far_branches()) {
654 return false;
655 }
656 // codecache size > 240M
657 if (MacroAssembler::codestub_branch_needs_far_jump()) {
658 return true;
659 }
660 // codecache size: 128M..240M
661 return !CodeCache::is_non_nmethod(addr);
662 }
663
664 void MacroAssembler::far_call(Address entry, Register tmp) {
665 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
666 assert(CodeCache::find_blob(entry.target()) != nullptr,
667 "destination of far call not found in code cache");
668 assert(entry.rspec().type() == relocInfo::external_word_type
669 || entry.rspec().type() == relocInfo::runtime_call_type
670 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
671 if (target_needs_far_branch(entry.target())) {
672 uint64_t offset;
673 // We can use ADRP here because we know that the total size of
674 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
675 adrp(tmp, entry, offset);
676 add(tmp, tmp, offset);
677 blr(tmp);
678 } else {
679 bl(entry);
680 }
681 }
682
683 int MacroAssembler::far_jump(Address entry, Register tmp) {
684 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
685 assert(CodeCache::find_blob(entry.target()) != nullptr,
686 "destination of far call not found in code cache");
687 assert(entry.rspec().type() == relocInfo::external_word_type
688 || entry.rspec().type() == relocInfo::runtime_call_type
689 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
690 address start = pc();
691 if (target_needs_far_branch(entry.target())) {
692 uint64_t offset;
693 // We can use ADRP here because we know that the total size of
694 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
695 adrp(tmp, entry, offset);
696 add(tmp, tmp, offset);
697 br(tmp);
698 } else {
699 b(entry);
700 }
701 return pc() - start;
702 }
703
704 void MacroAssembler::reserved_stack_check() {
705 // testing if reserved zone needs to be enabled
706 Label no_reserved_zone_enabling;
707
708 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
709 cmp(sp, rscratch1);
710 br(Assembler::LO, no_reserved_zone_enabling);
711
712 enter(); // LR and FP are live.
713 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)));
714 mov(c_rarg0, rthread);
715 blr(rscratch1);
716 leave();
717
718 // We have already removed our own frame.
719 // throw_delayed_StackOverflowError will think that it's been
720 // called by our caller.
721 lea(rscratch1, RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
722 br(rscratch1);
723 should_not_reach_here();
724
725 bind(no_reserved_zone_enabling);
726 }
727
728 static void pass_arg0(MacroAssembler* masm, Register arg) {
729 if (c_rarg0 != arg ) {
730 masm->mov(c_rarg0, arg);
731 }
732 }
733
734 static void pass_arg1(MacroAssembler* masm, Register arg) {
735 if (c_rarg1 != arg ) {
736 masm->mov(c_rarg1, arg);
737 }
738 }
739
740 static void pass_arg2(MacroAssembler* masm, Register arg) {
741 if (c_rarg2 != arg ) {
742 masm->mov(c_rarg2, arg);
743 }
744 }
745
746 static void pass_arg3(MacroAssembler* masm, Register arg) {
747 if (c_rarg3 != arg ) {
748 masm->mov(c_rarg3, arg);
749 }
750 }
751
752 void MacroAssembler::call_VM_base(Register oop_result,
753 Register java_thread,
754 Register last_java_sp,
755 Label* return_pc,
756 address entry_point,
757 int number_of_arguments,
758 bool check_exceptions) {
759 // determine java_thread register
760 if (!java_thread->is_valid()) {
761 java_thread = rthread;
762 }
763
764 // determine last_java_sp register
765 if (!last_java_sp->is_valid()) {
766 last_java_sp = esp;
767 }
768
769 // debugging support
770 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
771 assert(java_thread == rthread, "unexpected register");
772 #ifdef ASSERT
773 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
774 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
775 #endif // ASSERT
776
777 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
778 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
779
780 // push java thread (becomes first argument of C function)
781
782 mov(c_rarg0, java_thread);
783
784 // set last Java frame before call
785 assert(last_java_sp != rfp, "can't use rfp");
786
787 Label l;
788 set_last_Java_frame(last_java_sp, rfp, return_pc != nullptr ? *return_pc : l, rscratch1);
789
790 // do the call, remove parameters
791 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
792
793 // lr could be poisoned with PAC signature during throw_pending_exception
794 // if it was tail-call optimized by compiler, since lr is not callee-saved
795 // reload it with proper value
796 adr(lr, l);
797
798 // reset last Java frame
799 // Only interpreter should have to clear fp
800 reset_last_Java_frame(true);
801
802 // C++ interp handles this in the interpreter
803 check_and_handle_popframe(java_thread);
804 check_and_handle_earlyret(java_thread);
805
806 if (check_exceptions) {
807 // check for pending exceptions (java_thread is set upon return)
808 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
809 Label ok;
810 cbz(rscratch1, ok);
811 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
812 br(rscratch1);
813 bind(ok);
814 }
815
816 // get oop result if there is one and reset the value in the thread
817 if (oop_result->is_valid()) {
818 get_vm_result_oop(oop_result, java_thread);
819 }
820 }
821
822 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
823 call_VM_base(oop_result, noreg, noreg, nullptr, entry_point, number_of_arguments, check_exceptions);
824 }
825
826 // Check the entry target is always reachable from any branch.
827 static bool is_always_within_branch_range(Address entry) {
828 if (AOTCodeCache::is_on_for_dump()) {
829 return false;
830 }
831 const address target = entry.target();
832
833 if (!CodeCache::contains(target)) {
834 // We always use trampolines for callees outside CodeCache.
835 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target");
836 return false;
837 }
838
839 if (!MacroAssembler::far_branches()) {
840 return true;
841 }
842
843 if (entry.rspec().type() == relocInfo::runtime_call_type) {
844 // Runtime calls are calls of a non-compiled method (stubs, adapters).
845 // Non-compiled methods stay forever in CodeCache.
846 // We check whether the longest possible branch is within the branch range.
847 assert(CodeCache::find_blob(target) != nullptr &&
848 !CodeCache::find_blob(target)->is_nmethod(),
849 "runtime call of compiled method");
850 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size;
851 const address left_longest_branch_start = CodeCache::low_bound();
852 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) &&
853 Assembler::reachable_from_branch_at(right_longest_branch_start, target);
854 return is_reachable;
855 }
856
857 return false;
858 }
859
860 // Maybe emit a call via a trampoline. If the code cache is small
861 // trampolines won't be emitted.
862 address MacroAssembler::trampoline_call(Address entry) {
863 assert(entry.rspec().type() == relocInfo::runtime_call_type
864 || entry.rspec().type() == relocInfo::opt_virtual_call_type
865 || entry.rspec().type() == relocInfo::static_call_type
866 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
867
868 address target = entry.target();
869
870 if (!is_always_within_branch_range(entry)) {
871 if (!in_scratch_emit_size()) {
872 // We don't want to emit a trampoline if C2 is generating dummy
873 // code during its branch shortening phase.
874 if (entry.rspec().type() == relocInfo::runtime_call_type) {
875 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs");
876 code()->share_trampoline_for(entry.target(), offset());
877 } else {
878 address stub = emit_trampoline_stub(offset(), target);
879 if (stub == nullptr) {
880 postcond(pc() == badAddress);
881 return nullptr; // CodeCache is full
882 }
883 }
884 }
885 target = pc();
886 }
887
888 address call_pc = pc();
889 relocate(entry.rspec());
890 bl(target);
891
892 postcond(pc() != badAddress);
893 return call_pc;
894 }
895
896 // Emit a trampoline stub for a call to a target which is too far away.
897 //
898 // code sequences:
899 //
900 // call-site:
901 // branch-and-link to <destination> or <trampoline stub>
902 //
903 // Related trampoline stub for this call site in the stub section:
904 // load the call target from the constant pool
905 // branch (LR still points to the call site above)
906
907 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
908 address dest) {
909 // Max stub size: alignment nop, TrampolineStub.
910 address stub = start_a_stub(max_trampoline_stub_size());
911 if (stub == nullptr) {
912 return nullptr; // CodeBuffer::expand failed
913 }
914
915 // Create a trampoline stub relocation which relates this trampoline stub
916 // with the call instruction at insts_call_instruction_offset in the
917 // instructions code-section.
918 align(wordSize);
919 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
920 + insts_call_instruction_offset));
921 const int stub_start_offset = offset();
922
923 // Now, create the trampoline stub's code:
924 // - load the call
925 // - call
926 Label target;
927 ldr(rscratch1, target);
928 br(rscratch1);
929 bind(target);
930 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
931 "should be");
932 emit_int64((int64_t)dest);
933
934 const address stub_start_addr = addr_at(stub_start_offset);
935
936 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
937
938 end_a_stub();
939 return stub_start_addr;
940 }
941
942 int MacroAssembler::max_trampoline_stub_size() {
943 // Max stub size: alignment nop, TrampolineStub.
944 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size;
945 }
946
947 void MacroAssembler::emit_static_call_stub() {
948 // CompiledDirectCall::set_to_interpreted knows the
949 // exact layout of this stub.
950
951 isb();
952 mov_metadata(rmethod, nullptr);
953
954 // Jump to the entry point of the c2i stub.
955 if (codestub_branch_needs_far_jump()) {
956 movptr(rscratch1, 0);
957 br(rscratch1);
958 } else {
959 b(pc());
960 }
961 }
962
963 int MacroAssembler::static_call_stub_size() {
964 if (!codestub_branch_needs_far_jump()) {
965 // isb; movk; movz; movz; b
966 return 5 * NativeInstruction::instruction_size;
967 }
968 // isb; movk; movz; movz; movk; movz; movz; br
969 return 8 * NativeInstruction::instruction_size;
970 }
971
972 void MacroAssembler::c2bool(Register x) {
973 // implements x == 0 ? 0 : 1
974 // note: must only look at least-significant byte of x
975 // since C-style booleans are stored in one byte
976 // only! (was bug)
977 tst(x, 0xff);
978 cset(x, Assembler::NE);
979 }
980
981 address MacroAssembler::ic_call(address entry, jint method_index) {
982 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
983 movptr(rscratch2, (intptr_t)Universe::non_oop_word());
984 return trampoline_call(Address(entry, rh));
985 }
986
987 int MacroAssembler::ic_check_size() {
988 int extra_instructions = UseCompactObjectHeaders ? 1 : 0;
989 if (target_needs_far_branch(CAST_FROM_FN_PTR(address, SharedRuntime::get_ic_miss_stub()))) {
990 return NativeInstruction::instruction_size * (7 + extra_instructions);
991 } else {
992 return NativeInstruction::instruction_size * (5 + extra_instructions);
993 }
994 }
995
996 int MacroAssembler::ic_check(int end_alignment) {
997 Register receiver = j_rarg0;
998 Register data = rscratch2;
999 Register tmp1 = rscratch1;
1000 Register tmp2 = r10;
1001
1002 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1003 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1004 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1005 // before the inline cache check here, and not after
1006 align(end_alignment, offset() + ic_check_size());
1007
1008 int uep_offset = offset();
1009
1010 if (UseCompactObjectHeaders) {
1011 load_narrow_klass_compact(tmp1, receiver);
1012 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1013 cmpw(tmp1, tmp2);
1014 } else if (UseCompressedClassPointers) {
1015 ldrw(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1016 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1017 cmpw(tmp1, tmp2);
1018 } else {
1019 ldr(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1020 ldr(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1021 cmp(tmp1, tmp2);
1022 }
1023
1024 Label dont;
1025 br(Assembler::EQ, dont);
1026 far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1027 bind(dont);
1028 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1029
1030 return uep_offset;
1031 }
1032
1033 // Implementation of call_VM versions
1034
1035 void MacroAssembler::call_VM(Register oop_result,
1036 address entry_point,
1037 bool check_exceptions) {
1038 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1039 }
1040
1041 void MacroAssembler::call_VM(Register oop_result,
1042 address entry_point,
1043 Register arg_1,
1044 bool check_exceptions) {
1045 pass_arg1(this, arg_1);
1046 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1047 }
1048
1049 void MacroAssembler::call_VM(Register oop_result,
1050 address entry_point,
1051 Register arg_1,
1052 Register arg_2,
1053 bool check_exceptions) {
1054 assert_different_registers(arg_1, c_rarg2);
1055 pass_arg2(this, arg_2);
1056 pass_arg1(this, arg_1);
1057 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1058 }
1059
1060 void MacroAssembler::call_VM(Register oop_result,
1061 address entry_point,
1062 Register arg_1,
1063 Register arg_2,
1064 Register arg_3,
1065 bool check_exceptions) {
1066 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1067 assert_different_registers(arg_2, c_rarg3);
1068 pass_arg3(this, arg_3);
1069
1070 pass_arg2(this, arg_2);
1071
1072 pass_arg1(this, arg_1);
1073 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1074 }
1075
1076 void MacroAssembler::call_VM(Register oop_result,
1077 Register last_java_sp,
1078 address entry_point,
1079 int number_of_arguments,
1080 bool check_exceptions) {
1081 call_VM_base(oop_result, rthread, last_java_sp, nullptr, entry_point, number_of_arguments, check_exceptions);
1082 }
1083
1084 void MacroAssembler::call_VM(Register oop_result,
1085 Register last_java_sp,
1086 address entry_point,
1087 Register arg_1,
1088 bool check_exceptions) {
1089 pass_arg1(this, arg_1);
1090 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1091 }
1092
1093 void MacroAssembler::call_VM(Register oop_result,
1094 Register last_java_sp,
1095 address entry_point,
1096 Register arg_1,
1097 Register arg_2,
1098 bool check_exceptions) {
1099
1100 assert_different_registers(arg_1, c_rarg2);
1101 pass_arg2(this, arg_2);
1102 pass_arg1(this, arg_1);
1103 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1104 }
1105
1106 void MacroAssembler::call_VM(Register oop_result,
1107 Register last_java_sp,
1108 address entry_point,
1109 Register arg_1,
1110 Register arg_2,
1111 Register arg_3,
1112 bool check_exceptions) {
1113 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1114 assert_different_registers(arg_2, c_rarg3);
1115 pass_arg3(this, arg_3);
1116 pass_arg2(this, arg_2);
1117 pass_arg1(this, arg_1);
1118 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1119 }
1120
1121
1122 void MacroAssembler::get_vm_result_oop(Register oop_result, Register java_thread) {
1123 ldr(oop_result, Address(java_thread, JavaThread::vm_result_oop_offset()));
1124 str(zr, Address(java_thread, JavaThread::vm_result_oop_offset()));
1125 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1126 }
1127
1128 void MacroAssembler::get_vm_result_metadata(Register metadata_result, Register java_thread) {
1129 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1130 str(zr, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1131 }
1132
1133 void MacroAssembler::align(int modulus) {
1134 align(modulus, offset());
1135 }
1136
1137 // Ensure that the code at target bytes offset from the current offset() is aligned
1138 // according to modulus.
1139 void MacroAssembler::align(int modulus, int target) {
1140 int delta = target - offset();
1141 while ((offset() + delta) % modulus != 0) nop();
1142 }
1143
1144 void MacroAssembler::post_call_nop() {
1145 if (!Continuations::enabled()) {
1146 return;
1147 }
1148 InstructionMark im(this);
1149 relocate(post_call_nop_Relocation::spec());
1150 InlineSkippedInstructionsCounter skipCounter(this);
1151 nop();
1152 movk(zr, 0);
1153 movk(zr, 0);
1154 }
1155
1156 // these are no-ops overridden by InterpreterMacroAssembler
1157
1158 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1159
1160 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1161
1162 // Look up the method for a megamorphic invokeinterface call.
1163 // The target method is determined by <intf_klass, itable_index>.
1164 // The receiver klass is in recv_klass.
1165 // On success, the result will be in method_result, and execution falls through.
1166 // On failure, execution transfers to the given label.
1167 void MacroAssembler::lookup_interface_method(Register recv_klass,
1168 Register intf_klass,
1169 RegisterOrConstant itable_index,
1170 Register method_result,
1171 Register scan_temp,
1172 Label& L_no_such_interface,
1173 bool return_method) {
1174 assert_different_registers(recv_klass, intf_klass, scan_temp);
1175 assert_different_registers(method_result, intf_klass, scan_temp);
1176 assert(recv_klass != method_result || !return_method,
1177 "recv_klass can be destroyed when method isn't needed");
1178 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1179 "caller must use same register for non-constant itable index as for method");
1180
1181 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1182 int vtable_base = in_bytes(Klass::vtable_start_offset());
1183 int itentry_off = in_bytes(itableMethodEntry::method_offset());
1184 int scan_step = itableOffsetEntry::size() * wordSize;
1185 int vte_size = vtableEntry::size_in_bytes();
1186 assert(vte_size == wordSize, "else adjust times_vte_scale");
1187
1188 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1189
1190 // Could store the aligned, prescaled offset in the klass.
1191 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
1192 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
1193 add(scan_temp, scan_temp, vtable_base);
1194
1195 if (return_method) {
1196 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1197 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1198 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1199 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
1200 if (itentry_off)
1201 add(recv_klass, recv_klass, itentry_off);
1202 }
1203
1204 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
1205 // if (scan->interface() == intf) {
1206 // result = (klass + scan->offset() + itable_index);
1207 // }
1208 // }
1209 Label search, found_method;
1210
1211 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1212 cmp(intf_klass, method_result);
1213 br(Assembler::EQ, found_method);
1214 bind(search);
1215 // Check that the previous entry is non-null. A null entry means that
1216 // the receiver class doesn't implement the interface, and wasn't the
1217 // same as when the caller was compiled.
1218 cbz(method_result, L_no_such_interface);
1219 if (itableOffsetEntry::interface_offset() != 0) {
1220 add(scan_temp, scan_temp, scan_step);
1221 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1222 } else {
1223 ldr(method_result, Address(pre(scan_temp, scan_step)));
1224 }
1225 cmp(intf_klass, method_result);
1226 br(Assembler::NE, search);
1227
1228 bind(found_method);
1229
1230 // Got a hit.
1231 if (return_method) {
1232 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
1233 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1234 }
1235 }
1236
1237 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
1238 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
1239 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
1240 // The target method is determined by <holder_klass, itable_index>.
1241 // The receiver klass is in recv_klass.
1242 // On success, the result will be in method_result, and execution falls through.
1243 // On failure, execution transfers to the given label.
1244 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
1245 Register holder_klass,
1246 Register resolved_klass,
1247 Register method_result,
1248 Register temp_itbl_klass,
1249 Register scan_temp,
1250 int itable_index,
1251 Label& L_no_such_interface) {
1252 // 'method_result' is only used as output register at the very end of this method.
1253 // Until then we can reuse it as 'holder_offset'.
1254 Register holder_offset = method_result;
1255 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset);
1256
1257 int vtable_start_offset = in_bytes(Klass::vtable_start_offset());
1258 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize;
1259 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
1260 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
1261
1262 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found;
1263
1264 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1265 add(recv_klass, recv_klass, vtable_start_offset + ioffset);
1266 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len;
1267 // temp_itbl_klass = itable[0]._interface;
1268 int vtblEntrySize = vtableEntry::size_in_bytes();
1269 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3");
1270 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1271 mov(holder_offset, zr);
1272 // scan_temp = &(itable[0]._interface)
1273 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1274
1275 // Initial checks:
1276 // - if (holder_klass != resolved_klass), go to "scan for resolved"
1277 // - if (itable[0] == holder_klass), shortcut to "holder found"
1278 // - if (itable[0] == 0), no such interface
1279 cmp(resolved_klass, holder_klass);
1280 br(Assembler::NE, L_loop_search_resolved_entry);
1281 cmp(holder_klass, temp_itbl_klass);
1282 br(Assembler::EQ, L_holder_found);
1283 cbz(temp_itbl_klass, L_no_such_interface);
1284
1285 // Loop: Look for holder_klass record in itable
1286 // do {
1287 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1288 // if (temp_itbl_klass == holder_klass) {
1289 // goto L_holder_found; // Found!
1290 // }
1291 // } while (temp_itbl_klass != 0);
1292 // goto L_no_such_interface // Not found.
1293 Label L_search_holder;
1294 bind(L_search_holder);
1295 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1296 cmp(holder_klass, temp_itbl_klass);
1297 br(Assembler::EQ, L_holder_found);
1298 cbnz(temp_itbl_klass, L_search_holder);
1299
1300 b(L_no_such_interface);
1301
1302 // Loop: Look for resolved_class record in itable
1303 // while (true) {
1304 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1305 // if (temp_itbl_klass == 0) {
1306 // goto L_no_such_interface;
1307 // }
1308 // if (temp_itbl_klass == resolved_klass) {
1309 // goto L_resolved_found; // Found!
1310 // }
1311 // if (temp_itbl_klass == holder_klass) {
1312 // holder_offset = scan_temp;
1313 // }
1314 // }
1315 //
1316 Label L_loop_search_resolved;
1317 bind(L_loop_search_resolved);
1318 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1319 bind(L_loop_search_resolved_entry);
1320 cbz(temp_itbl_klass, L_no_such_interface);
1321 cmp(resolved_klass, temp_itbl_klass);
1322 br(Assembler::EQ, L_resolved_found);
1323 cmp(holder_klass, temp_itbl_klass);
1324 br(Assembler::NE, L_loop_search_resolved);
1325 mov(holder_offset, scan_temp);
1326 b(L_loop_search_resolved);
1327
1328 // See if we already have a holder klass. If not, go and scan for it.
1329 bind(L_resolved_found);
1330 cbz(holder_offset, L_search_holder);
1331 mov(scan_temp, holder_offset);
1332
1333 // Finally, scan_temp contains holder_klass vtable offset
1334 bind(L_holder_found);
1335 ldrw(method_result, Address(scan_temp, ooffset - ioffset));
1336 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset())
1337 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass
1338 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0)));
1339 }
1340
1341 // virtual method calling
1342 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1343 RegisterOrConstant vtable_index,
1344 Register method_result) {
1345 assert(vtableEntry::size() * wordSize == 8,
1346 "adjust the scaling in the code below");
1347 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset());
1348
1349 if (vtable_index.is_register()) {
1350 lea(method_result, Address(recv_klass,
1351 vtable_index.as_register(),
1352 Address::lsl(LogBytesPerWord)));
1353 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1354 } else {
1355 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1356 ldr(method_result,
1357 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1358 }
1359 }
1360
1361 void MacroAssembler::check_klass_subtype(Register sub_klass,
1362 Register super_klass,
1363 Register temp_reg,
1364 Label& L_success) {
1365 Label L_failure;
1366 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
1367 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
1368 bind(L_failure);
1369 }
1370
1371
1372 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1373 Register super_klass,
1374 Register temp_reg,
1375 Label* L_success,
1376 Label* L_failure,
1377 Label* L_slow_path,
1378 Register super_check_offset) {
1379 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset);
1380 bool must_load_sco = ! super_check_offset->is_valid();
1381 if (must_load_sco) {
1382 assert(temp_reg != noreg, "supply either a temp or a register offset");
1383 }
1384
1385 Label L_fallthrough;
1386 int label_nulls = 0;
1387 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1388 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1389 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
1390 assert(label_nulls <= 1, "at most one null in the batch");
1391
1392 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1393 Address super_check_offset_addr(super_klass, sco_offset);
1394
1395 // Hacked jmp, which may only be used just before L_fallthrough.
1396 #define final_jmp(label) \
1397 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1398 else b(label) /*omit semi*/
1399
1400 // If the pointers are equal, we are done (e.g., String[] elements).
1401 // This self-check enables sharing of secondary supertype arrays among
1402 // non-primary types such as array-of-interface. Otherwise, each such
1403 // type would need its own customized SSA.
1404 // We move this check to the front of the fast path because many
1405 // type checks are in fact trivially successful in this manner,
1406 // so we get a nicely predicted branch right at the start of the check.
1407 cmp(sub_klass, super_klass);
1408 br(Assembler::EQ, *L_success);
1409
1410 // Check the supertype display:
1411 if (must_load_sco) {
1412 ldrw(temp_reg, super_check_offset_addr);
1413 super_check_offset = temp_reg;
1414 }
1415
1416 Address super_check_addr(sub_klass, super_check_offset);
1417 ldr(rscratch1, super_check_addr);
1418 cmp(super_klass, rscratch1); // load displayed supertype
1419 br(Assembler::EQ, *L_success);
1420
1421 // This check has worked decisively for primary supers.
1422 // Secondary supers are sought in the super_cache ('super_cache_addr').
1423 // (Secondary supers are interfaces and very deeply nested subtypes.)
1424 // This works in the same check above because of a tricky aliasing
1425 // between the super_cache and the primary super display elements.
1426 // (The 'super_check_addr' can address either, as the case requires.)
1427 // Note that the cache is updated below if it does not help us find
1428 // what we need immediately.
1429 // So if it was a primary super, we can just fail immediately.
1430 // Otherwise, it's the slow path for us (no success at this point).
1431
1432 sub(rscratch1, super_check_offset, in_bytes(Klass::secondary_super_cache_offset()));
1433 if (L_failure == &L_fallthrough) {
1434 cbz(rscratch1, *L_slow_path);
1435 } else {
1436 cbnz(rscratch1, *L_failure);
1437 final_jmp(*L_slow_path);
1438 }
1439
1440 bind(L_fallthrough);
1441
1442 #undef final_jmp
1443 }
1444
1445 // These two are taken from x86, but they look generally useful
1446
1447 // scans count pointer sized words at [addr] for occurrence of value,
1448 // generic
1449 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1450 Register scratch) {
1451 Label Lloop, Lexit;
1452 cbz(count, Lexit);
1453 bind(Lloop);
1454 ldr(scratch, post(addr, wordSize));
1455 cmp(value, scratch);
1456 br(EQ, Lexit);
1457 sub(count, count, 1);
1458 cbnz(count, Lloop);
1459 bind(Lexit);
1460 }
1461
1462 // scans count 4 byte words at [addr] for occurrence of value,
1463 // generic
1464 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1465 Register scratch) {
1466 Label Lloop, Lexit;
1467 cbz(count, Lexit);
1468 bind(Lloop);
1469 ldrw(scratch, post(addr, wordSize));
1470 cmpw(value, scratch);
1471 br(EQ, Lexit);
1472 sub(count, count, 1);
1473 cbnz(count, Lloop);
1474 bind(Lexit);
1475 }
1476
1477 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
1478 Register super_klass,
1479 Register temp_reg,
1480 Register temp2_reg,
1481 Label* L_success,
1482 Label* L_failure,
1483 bool set_cond_codes) {
1484 // NB! Callers may assume that, when temp2_reg is a valid register,
1485 // this code sets it to a nonzero value.
1486
1487 assert_different_registers(sub_klass, super_klass, temp_reg);
1488 if (temp2_reg != noreg)
1489 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1490 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1491
1492 Label L_fallthrough;
1493 int label_nulls = 0;
1494 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1495 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1496 assert(label_nulls <= 1, "at most one null in the batch");
1497
1498 // a couple of useful fields in sub_klass:
1499 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1500 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1501 Address secondary_supers_addr(sub_klass, ss_offset);
1502 Address super_cache_addr( sub_klass, sc_offset);
1503
1504 BLOCK_COMMENT("check_klass_subtype_slow_path");
1505
1506 // Do a linear scan of the secondary super-klass chain.
1507 // This code is rarely used, so simplicity is a virtue here.
1508 // The repne_scan instruction uses fixed registers, which we must spill.
1509 // Don't worry too much about pre-existing connections with the input regs.
1510
1511 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1512 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1513
1514 RegSet pushed_registers;
1515 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1516 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1517
1518 if (super_klass != r0) {
1519 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1520 }
1521
1522 push(pushed_registers, sp);
1523
1524 // Get super_klass value into r0 (even if it was in r5 or r2).
1525 if (super_klass != r0) {
1526 mov(r0, super_klass);
1527 }
1528
1529 #ifndef PRODUCT
1530 incrementw(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1531 #endif //PRODUCT
1532
1533 // We will consult the secondary-super array.
1534 ldr(r5, secondary_supers_addr);
1535 // Load the array length.
1536 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1537 // Skip to start of data.
1538 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1539
1540 cmp(sp, zr); // Clear Z flag; SP is never zero
1541 // Scan R2 words at [R5] for an occurrence of R0.
1542 // Set NZ/Z based on last compare.
1543 repne_scan(r5, r0, r2, rscratch1);
1544
1545 // Unspill the temp. registers:
1546 pop(pushed_registers, sp);
1547
1548 br(Assembler::NE, *L_failure);
1549
1550 // Success. Cache the super we found and proceed in triumph.
1551
1552 if (UseSecondarySupersCache) {
1553 str(super_klass, super_cache_addr);
1554 }
1555
1556 if (L_success != &L_fallthrough) {
1557 b(*L_success);
1558 }
1559
1560 #undef IS_A_TEMP
1561
1562 bind(L_fallthrough);
1563 }
1564
1565 // If Register r is invalid, remove a new register from
1566 // available_regs, and add new register to regs_to_push.
1567 Register MacroAssembler::allocate_if_noreg(Register r,
1568 RegSetIterator<Register> &available_regs,
1569 RegSet ®s_to_push) {
1570 if (!r->is_valid()) {
1571 r = *available_regs++;
1572 regs_to_push += r;
1573 }
1574 return r;
1575 }
1576
1577 // check_klass_subtype_slow_path_table() looks for super_klass in the
1578 // hash table belonging to super_klass, branching to L_success or
1579 // L_failure as appropriate. This is essentially a shim which
1580 // allocates registers as necessary then calls
1581 // lookup_secondary_supers_table() to do the work. Any of the temp
1582 // regs may be noreg, in which case this logic will chooses some
1583 // registers push and pop them from the stack.
1584 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
1585 Register super_klass,
1586 Register temp_reg,
1587 Register temp2_reg,
1588 Register temp3_reg,
1589 Register result_reg,
1590 FloatRegister vtemp,
1591 Label* L_success,
1592 Label* L_failure,
1593 bool set_cond_codes) {
1594 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
1595
1596 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1597
1598 Label L_fallthrough;
1599 int label_nulls = 0;
1600 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1601 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1602 assert(label_nulls <= 1, "at most one null in the batch");
1603
1604 BLOCK_COMMENT("check_klass_subtype_slow_path");
1605
1606 RegSetIterator<Register> available_regs
1607 = (RegSet::range(r0, r15) - temps - sub_klass - super_klass).begin();
1608
1609 RegSet pushed_regs;
1610
1611 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
1612 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
1613 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
1614 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
1615
1616 push(pushed_regs, sp);
1617
1618 lookup_secondary_supers_table_var(sub_klass,
1619 super_klass,
1620 temp_reg, temp2_reg, temp3_reg, vtemp, result_reg,
1621 nullptr);
1622 cmp(result_reg, zr);
1623
1624 // Unspill the temp. registers:
1625 pop(pushed_regs, sp);
1626
1627 // NB! Callers may assume that, when set_cond_codes is true, this
1628 // code sets temp2_reg to a nonzero value.
1629 if (set_cond_codes) {
1630 mov(temp2_reg, 1);
1631 }
1632
1633 br(Assembler::NE, *L_failure);
1634
1635 if (L_success != &L_fallthrough) {
1636 b(*L_success);
1637 }
1638
1639 bind(L_fallthrough);
1640 }
1641
1642 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1643 Register super_klass,
1644 Register temp_reg,
1645 Register temp2_reg,
1646 Label* L_success,
1647 Label* L_failure,
1648 bool set_cond_codes) {
1649 if (UseSecondarySupersTable) {
1650 check_klass_subtype_slow_path_table
1651 (sub_klass, super_klass, temp_reg, temp2_reg, /*temp3*/noreg, /*result*/noreg,
1652 /*vtemp*/fnoreg,
1653 L_success, L_failure, set_cond_codes);
1654 } else {
1655 check_klass_subtype_slow_path_linear
1656 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
1657 }
1658 }
1659
1660
1661 // Ensure that the inline code and the stub are using the same registers.
1662 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
1663 do { \
1664 assert(r_super_klass == r0 && \
1665 r_array_base == r1 && \
1666 r_array_length == r2 && \
1667 (r_array_index == r3 || r_array_index == noreg) && \
1668 (r_sub_klass == r4 || r_sub_klass == noreg) && \
1669 (r_bitmap == rscratch2 || r_bitmap == noreg) && \
1670 (result == r5 || result == noreg), "registers must match aarch64.ad"); \
1671 } while(0)
1672
1673 bool MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
1674 Register r_super_klass,
1675 Register temp1,
1676 Register temp2,
1677 Register temp3,
1678 FloatRegister vtemp,
1679 Register result,
1680 u1 super_klass_slot,
1681 bool stub_is_near) {
1682 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1683
1684 Label L_fallthrough;
1685
1686 BLOCK_COMMENT("lookup_secondary_supers_table {");
1687
1688 const Register
1689 r_array_base = temp1, // r1
1690 r_array_length = temp2, // r2
1691 r_array_index = temp3, // r3
1692 r_bitmap = rscratch2;
1693
1694 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1695
1696 u1 bit = super_klass_slot;
1697
1698 // Make sure that result is nonzero if the TBZ below misses.
1699 mov(result, 1);
1700
1701 // We're going to need the bitmap in a vector reg and in a core reg,
1702 // so load both now.
1703 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1704 if (bit != 0) {
1705 ldrd(vtemp, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1706 }
1707 // First check the bitmap to see if super_klass might be present. If
1708 // the bit is zero, we are certain that super_klass is not one of
1709 // the secondary supers.
1710 tbz(r_bitmap, bit, L_fallthrough);
1711
1712 // Get the first array index that can contain super_klass into r_array_index.
1713 if (bit != 0) {
1714 shld(vtemp, vtemp, Klass::SECONDARY_SUPERS_TABLE_MASK - bit);
1715 cnt(vtemp, T8B, vtemp);
1716 addv(vtemp, T8B, vtemp);
1717 fmovd(r_array_index, vtemp);
1718 } else {
1719 mov(r_array_index, (u1)1);
1720 }
1721 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1722
1723 // We will consult the secondary-super array.
1724 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1725
1726 // The value i in r_array_index is >= 1, so even though r_array_base
1727 // points to the length, we don't need to adjust it to point to the
1728 // data.
1729 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1730 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1731
1732 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1733 eor(result, result, r_super_klass);
1734 cbz(result, L_fallthrough); // Found a match
1735
1736 // Is there another entry to check? Consult the bitmap.
1737 tbz(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK, L_fallthrough);
1738
1739 // Linear probe.
1740 if (bit != 0) {
1741 ror(r_bitmap, r_bitmap, bit);
1742 }
1743
1744 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1745 // The next slot to be inspected, by the stub we're about to call,
1746 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1747 // have been checked.
1748 Address stub = RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub());
1749 if (stub_is_near) {
1750 bl(stub);
1751 } else {
1752 address call = trampoline_call(stub);
1753 if (call == nullptr) {
1754 return false; // trampoline allocation failed
1755 }
1756 }
1757
1758 BLOCK_COMMENT("} lookup_secondary_supers_table");
1759
1760 bind(L_fallthrough);
1761
1762 if (VerifySecondarySupers) {
1763 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1764 temp1, temp2, result); // r1, r2, r5
1765 }
1766 return true;
1767 }
1768
1769 // At runtime, return 0 in result if r_super_klass is a superclass of
1770 // r_sub_klass, otherwise return nonzero. Use this version of
1771 // lookup_secondary_supers_table() if you don't know ahead of time
1772 // which superclass will be searched for. Used by interpreter and
1773 // runtime stubs. It is larger and has somewhat greater latency than
1774 // the version above, which takes a constant super_klass_slot.
1775 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
1776 Register r_super_klass,
1777 Register temp1,
1778 Register temp2,
1779 Register temp3,
1780 FloatRegister vtemp,
1781 Register result,
1782 Label *L_success) {
1783 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1784
1785 Label L_fallthrough;
1786
1787 BLOCK_COMMENT("lookup_secondary_supers_table {");
1788
1789 const Register
1790 r_array_index = temp3,
1791 slot = rscratch1,
1792 r_bitmap = rscratch2;
1793
1794 ldrb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
1795
1796 // Make sure that result is nonzero if the test below misses.
1797 mov(result, 1);
1798
1799 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1800
1801 // First check the bitmap to see if super_klass might be present. If
1802 // the bit is zero, we are certain that super_klass is not one of
1803 // the secondary supers.
1804
1805 // This next instruction is equivalent to:
1806 // mov(tmp_reg, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1807 // sub(temp2, tmp_reg, slot);
1808 eor(temp2, slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1809 lslv(temp2, r_bitmap, temp2);
1810 tbz(temp2, Klass::SECONDARY_SUPERS_TABLE_SIZE - 1, L_fallthrough);
1811
1812 bool must_save_v0 = (vtemp == fnoreg);
1813 if (must_save_v0) {
1814 // temp1 and result are free, so use them to preserve vtemp
1815 vtemp = v0;
1816 mov(temp1, vtemp, D, 0);
1817 mov(result, vtemp, D, 1);
1818 }
1819
1820 // Get the first array index that can contain super_klass into r_array_index.
1821 mov(vtemp, D, 0, temp2);
1822 cnt(vtemp, T8B, vtemp);
1823 addv(vtemp, T8B, vtemp);
1824 mov(r_array_index, vtemp, D, 0);
1825
1826 if (must_save_v0) {
1827 mov(vtemp, D, 0, temp1 );
1828 mov(vtemp, D, 1, result);
1829 }
1830
1831 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1832
1833 const Register
1834 r_array_base = temp1,
1835 r_array_length = temp2;
1836
1837 // The value i in r_array_index is >= 1, so even though r_array_base
1838 // points to the length, we don't need to adjust it to point to the
1839 // data.
1840 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1841 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1842
1843 // We will consult the secondary-super array.
1844 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1845
1846 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1847 eor(result, result, r_super_klass);
1848 cbz(result, L_success ? *L_success : L_fallthrough); // Found a match
1849
1850 // Is there another entry to check? Consult the bitmap.
1851 rorv(r_bitmap, r_bitmap, slot);
1852 // rol(r_bitmap, r_bitmap, 1);
1853 tbz(r_bitmap, 1, L_fallthrough);
1854
1855 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1856 // The next slot to be inspected, by the logic we're about to call,
1857 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1858 // have been checked.
1859 lookup_secondary_supers_table_slow_path(r_super_klass, r_array_base, r_array_index,
1860 r_bitmap, r_array_length, result, /*is_stub*/false);
1861
1862 BLOCK_COMMENT("} lookup_secondary_supers_table");
1863
1864 bind(L_fallthrough);
1865
1866 if (VerifySecondarySupers) {
1867 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1868 temp1, temp2, result); // r1, r2, r5
1869 }
1870
1871 if (L_success) {
1872 cbz(result, *L_success);
1873 }
1874 }
1875
1876 // Called by code generated by check_klass_subtype_slow_path
1877 // above. This is called when there is a collision in the hashed
1878 // lookup in the secondary supers array.
1879 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
1880 Register r_array_base,
1881 Register r_array_index,
1882 Register r_bitmap,
1883 Register temp1,
1884 Register result,
1885 bool is_stub) {
1886 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, result, rscratch1);
1887
1888 const Register
1889 r_array_length = temp1,
1890 r_sub_klass = noreg; // unused
1891
1892 if (is_stub) {
1893 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1894 }
1895
1896 Label L_fallthrough, L_huge;
1897
1898 // Load the array length.
1899 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1900 // And adjust the array base to point to the data.
1901 // NB! Effectively increments current slot index by 1.
1902 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
1903 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1904
1905 // The bitmap is full to bursting.
1906 // Implicit invariant: BITMAP_FULL implies (length > 0)
1907 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
1908 cmpw(r_array_length, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 2));
1909 br(GT, L_huge);
1910
1911 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
1912 // current slot (at secondary_supers[r_array_index]) has not yet
1913 // been inspected, and r_array_index may be out of bounds if we
1914 // wrapped around the end of the array.
1915
1916 { // This is conventional linear probing, but instead of terminating
1917 // when a null entry is found in the table, we maintain a bitmap
1918 // in which a 0 indicates missing entries.
1919 // As long as the bitmap is not completely full,
1920 // array_length == popcount(bitmap). The array_length check above
1921 // guarantees there are 0s in the bitmap, so the loop eventually
1922 // terminates.
1923 Label L_loop;
1924 bind(L_loop);
1925
1926 // Check for wraparound.
1927 cmp(r_array_index, r_array_length);
1928 csel(r_array_index, zr, r_array_index, GE);
1929
1930 ldr(rscratch1, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1931 eor(result, rscratch1, r_super_klass);
1932 cbz(result, L_fallthrough);
1933
1934 tbz(r_bitmap, 2, L_fallthrough); // look-ahead check (Bit 2); result is non-zero
1935
1936 ror(r_bitmap, r_bitmap, 1);
1937 add(r_array_index, r_array_index, 1);
1938 b(L_loop);
1939 }
1940
1941 { // Degenerate case: more than 64 secondary supers.
1942 // FIXME: We could do something smarter here, maybe a vectorized
1943 // comparison or a binary search, but is that worth any added
1944 // complexity?
1945 bind(L_huge);
1946 cmp(sp, zr); // Clear Z flag; SP is never zero
1947 repne_scan(r_array_base, r_super_klass, r_array_length, rscratch1);
1948 cset(result, NE); // result == 0 iff we got a match.
1949 }
1950
1951 bind(L_fallthrough);
1952 }
1953
1954 // Make sure that the hashed lookup and a linear scan agree.
1955 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
1956 Register r_super_klass,
1957 Register temp1,
1958 Register temp2,
1959 Register result) {
1960 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, result, rscratch1);
1961
1962 const Register
1963 r_array_base = temp1,
1964 r_array_length = temp2,
1965 r_array_index = noreg, // unused
1966 r_bitmap = noreg; // unused
1967
1968 BLOCK_COMMENT("verify_secondary_supers_table {");
1969
1970 // We will consult the secondary-super array.
1971 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1972
1973 // Load the array length.
1974 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1975 // And adjust the array base to point to the data.
1976 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1977
1978 cmp(sp, zr); // Clear Z flag; SP is never zero
1979 // Scan R2 words at [R5] for an occurrence of R0.
1980 // Set NZ/Z based on last compare.
1981 repne_scan(/*addr*/r_array_base, /*value*/r_super_klass, /*count*/r_array_length, rscratch2);
1982 // rscratch1 == 0 iff we got a match.
1983 cset(rscratch1, NE);
1984
1985 Label passed;
1986 cmp(result, zr);
1987 cset(result, NE); // normalize result to 0/1 for comparison
1988
1989 cmp(rscratch1, result);
1990 br(EQ, passed);
1991 {
1992 mov(r0, r_super_klass); // r0 <- r0
1993 mov(r1, r_sub_klass); // r1 <- r4
1994 mov(r2, /*expected*/rscratch1); // r2 <- r8
1995 mov(r3, result); // r3 <- r5
1996 mov(r4, (address)("mismatch")); // r4 <- const
1997 rt_call(CAST_FROM_FN_PTR(address, Klass::on_secondary_supers_verification_failure), rscratch2);
1998 should_not_reach_here();
1999 }
2000 bind(passed);
2001
2002 BLOCK_COMMENT("} verify_secondary_supers_table");
2003 }
2004
2005 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) {
2006 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
2007 assert_different_registers(klass, rthread, scratch);
2008
2009 Label L_fallthrough, L_tmp;
2010 if (L_fast_path == nullptr) {
2011 L_fast_path = &L_fallthrough;
2012 } else if (L_slow_path == nullptr) {
2013 L_slow_path = &L_fallthrough;
2014 }
2015 // Fast path check: class is fully initialized
2016 lea(scratch, Address(klass, InstanceKlass::init_state_offset()));
2017 ldarb(scratch, scratch);
2018 cmp(scratch, InstanceKlass::fully_initialized);
2019 br(Assembler::EQ, *L_fast_path);
2020
2021 // Fast path check: current thread is initializer thread
2022 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
2023 cmp(rthread, scratch);
2024
2025 if (L_slow_path == &L_fallthrough) {
2026 br(Assembler::EQ, *L_fast_path);
2027 bind(*L_slow_path);
2028 } else if (L_fast_path == &L_fallthrough) {
2029 br(Assembler::NE, *L_slow_path);
2030 bind(*L_fast_path);
2031 } else {
2032 Unimplemented();
2033 }
2034 }
2035
2036 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
2037 if (!VerifyOops || VerifyAdapterSharing) {
2038 // Below address of the code string confuses VerifyAdapterSharing
2039 // because it may differ between otherwise equivalent adapters.
2040 return;
2041 }
2042
2043 // Pass register number to verify_oop_subroutine
2044 const char* b = nullptr;
2045 {
2046 ResourceMark rm;
2047 stringStream ss;
2048 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
2049 b = code_string(ss.as_string());
2050 }
2051 BLOCK_COMMENT("verify_oop {");
2052
2053 strip_return_address(); // This might happen within a stack frame.
2054 protect_return_address();
2055 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2056 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2057
2058 mov(r0, reg);
2059 movptr(rscratch1, (uintptr_t)(address)b);
2060
2061 // call indirectly to solve generation ordering problem
2062 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2063 ldr(rscratch2, Address(rscratch2));
2064 blr(rscratch2);
2065
2066 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2067 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2068 authenticate_return_address();
2069
2070 BLOCK_COMMENT("} verify_oop");
2071 }
2072
2073 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
2074 if (!VerifyOops || VerifyAdapterSharing) {
2075 // Below address of the code string confuses VerifyAdapterSharing
2076 // because it may differ between otherwise equivalent adapters.
2077 return;
2078 }
2079
2080 const char* b = nullptr;
2081 {
2082 ResourceMark rm;
2083 stringStream ss;
2084 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
2085 b = code_string(ss.as_string());
2086 }
2087 BLOCK_COMMENT("verify_oop_addr {");
2088
2089 strip_return_address(); // This might happen within a stack frame.
2090 protect_return_address();
2091 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2092 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2093
2094 // addr may contain sp so we will have to adjust it based on the
2095 // pushes that we just did.
2096 if (addr.uses(sp)) {
2097 lea(r0, addr);
2098 ldr(r0, Address(r0, 4 * wordSize));
2099 } else {
2100 ldr(r0, addr);
2101 }
2102 movptr(rscratch1, (uintptr_t)(address)b);
2103
2104 // call indirectly to solve generation ordering problem
2105 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2106 ldr(rscratch2, Address(rscratch2));
2107 blr(rscratch2);
2108
2109 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2110 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2111 authenticate_return_address();
2112
2113 BLOCK_COMMENT("} verify_oop_addr");
2114 }
2115
2116 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
2117 int extra_slot_offset) {
2118 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2119 int stackElementSize = Interpreter::stackElementSize;
2120 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
2121 #ifdef ASSERT
2122 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
2123 assert(offset1 - offset == stackElementSize, "correct arithmetic");
2124 #endif
2125 if (arg_slot.is_constant()) {
2126 return Address(esp, arg_slot.as_constant() * stackElementSize
2127 + offset);
2128 } else {
2129 add(rscratch1, esp, arg_slot.as_register(),
2130 ext::uxtx, exact_log2(stackElementSize));
2131 return Address(rscratch1, offset);
2132 }
2133 }
2134
2135 void MacroAssembler::call_VM_leaf_base(address entry_point,
2136 int number_of_arguments,
2137 Label *retaddr) {
2138 Label E, L;
2139
2140 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
2141
2142 mov(rscratch1, RuntimeAddress(entry_point));
2143 blr(rscratch1);
2144 if (retaddr)
2145 bind(*retaddr);
2146
2147 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
2148 }
2149
2150 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2151 call_VM_leaf_base(entry_point, number_of_arguments);
2152 }
2153
2154 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2155 pass_arg0(this, arg_0);
2156 call_VM_leaf_base(entry_point, 1);
2157 }
2158
2159 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2160 assert_different_registers(arg_1, c_rarg0);
2161 pass_arg0(this, arg_0);
2162 pass_arg1(this, arg_1);
2163 call_VM_leaf_base(entry_point, 2);
2164 }
2165
2166 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2167 Register arg_1, Register arg_2) {
2168 assert_different_registers(arg_1, c_rarg0);
2169 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2170 pass_arg0(this, arg_0);
2171 pass_arg1(this, arg_1);
2172 pass_arg2(this, arg_2);
2173 call_VM_leaf_base(entry_point, 3);
2174 }
2175
2176 void MacroAssembler::super_call_VM_leaf(address entry_point) {
2177 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2178 }
2179
2180 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2181 pass_arg0(this, arg_0);
2182 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2183 }
2184
2185 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2186
2187 assert_different_registers(arg_0, c_rarg1);
2188 pass_arg1(this, arg_1);
2189 pass_arg0(this, arg_0);
2190 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2191 }
2192
2193 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2194 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2195 assert_different_registers(arg_1, c_rarg2);
2196 pass_arg2(this, arg_2);
2197 pass_arg1(this, arg_1);
2198 pass_arg0(this, arg_0);
2199 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2200 }
2201
2202 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2203 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
2204 assert_different_registers(arg_1, c_rarg2, c_rarg3);
2205 assert_different_registers(arg_2, c_rarg3);
2206 pass_arg3(this, arg_3);
2207 pass_arg2(this, arg_2);
2208 pass_arg1(this, arg_1);
2209 pass_arg0(this, arg_0);
2210 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2211 }
2212
2213 void MacroAssembler::null_check(Register reg, int offset) {
2214 if (needs_explicit_null_check(offset)) {
2215 // provoke OS null exception if reg is null by
2216 // accessing M[reg] w/o changing any registers
2217 // NOTE: this is plenty to provoke a segv
2218 ldr(zr, Address(reg));
2219 } else {
2220 // nothing to do, (later) access of M[reg + offset]
2221 // will provoke OS null exception if reg is null
2222 }
2223 }
2224
2225 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2226 assert_different_registers(markword, rscratch2);
2227 mov(rscratch2, markWord::inline_type_mask_in_place);
2228 andr(markword, markword, rscratch2);
2229 mov(rscratch2, markWord::inline_type_pattern);
2230 cmp(markword, rscratch2);
2231 br(Assembler::EQ, is_inline_type);
2232 }
2233
2234 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null) {
2235 assert_different_registers(tmp, rscratch1);
2236 if (can_be_null) {
2237 cbz(object, not_inline_type);
2238 }
2239 const int is_inline_type_mask = markWord::inline_type_pattern;
2240 ldr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2241 mov(rscratch1, is_inline_type_mask);
2242 andr(tmp, tmp, rscratch1);
2243 cmp(tmp, rscratch1);
2244 br(Assembler::NE, not_inline_type);
2245 }
2246
2247 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2248 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2249 tbnz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, is_null_free_inline_type);
2250 }
2251
2252 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2253 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2254 tbz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, not_null_free_inline_type);
2255 }
2256
2257 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2258 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2259 tbnz(flags, ResolvedFieldEntry::is_flat_shift, is_flat);
2260 }
2261
2262 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) {
2263 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2264 tbnz(flags, ResolvedFieldEntry::has_null_marker_shift, has_null_marker);
2265 }
2266
2267 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2268 Label test_mark_word;
2269 // load mark word
2270 ldr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2271 // check displaced
2272 tst(temp_reg, markWord::unlocked_value);
2273 br(Assembler::NE, test_mark_word);
2274 // slow path use klass prototype
2275 load_prototype_header(temp_reg, oop);
2276
2277 bind(test_mark_word);
2278 andr(temp_reg, temp_reg, test_bit);
2279 if (jmp_set) {
2280 cbnz(temp_reg, jmp_label);
2281 } else {
2282 cbz(temp_reg, jmp_label);
2283 }
2284 }
2285
2286 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array) {
2287 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2288 }
2289
2290 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2291 Label&is_non_flat_array) {
2292 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2293 }
2294
2295 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array) {
2296 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2297 }
2298
2299 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2300 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2301 }
2302
2303 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2304 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2305 br(Assembler::NE, is_flat_array);
2306 }
2307
2308 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
2309 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2310 br(Assembler::EQ, is_non_flat_array);
2311 }
2312
2313 // MacroAssembler protected routines needed to implement
2314 // public methods
2315
2316 void MacroAssembler::mov(Register r, Address dest) {
2317 code_section()->relocate(pc(), dest.rspec());
2318 uint64_t imm64 = (uint64_t)dest.target();
2319 movptr(r, imm64);
2320 }
2321
2322 // Move a constant pointer into r. In AArch64 mode the virtual
2323 // address space is 48 bits in size, so we only need three
2324 // instructions to create a patchable instruction sequence that can
2325 // reach anywhere.
2326 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2327 #ifndef PRODUCT
2328 {
2329 char buffer[64];
2330 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2331 block_comment(buffer);
2332 }
2333 #endif
2334 assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
2335 movz(r, imm64 & 0xffff);
2336 imm64 >>= 16;
2337 movk(r, imm64 & 0xffff, 16);
2338 imm64 >>= 16;
2339 movk(r, imm64 & 0xffff, 32);
2340 }
2341
2342 // Macro to mov replicated immediate to vector register.
2343 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is,
2344 // the upper 56/48/32 bits must be zeros for B/H/S type.
2345 // Vd will get the following values for different arrangements in T
2346 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh
2347 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
2348 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh
2349 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
2350 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
2351 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
2352 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh
2353 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh
2354 // Clobbers rscratch1
2355 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) {
2356 assert(T != T1Q, "unsupported");
2357 if (T == T1D || T == T2D) {
2358 int imm = operand_valid_for_movi_immediate(imm64, T);
2359 if (-1 != imm) {
2360 movi(Vd, T, imm);
2361 } else {
2362 mov(rscratch1, imm64);
2363 dup(Vd, T, rscratch1);
2364 }
2365 return;
2366 }
2367
2368 #ifdef ASSERT
2369 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)");
2370 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)");
2371 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)");
2372 #endif
2373 int shift = operand_valid_for_movi_immediate(imm64, T);
2374 uint32_t imm32 = imm64 & 0xffffffffULL;
2375 if (shift >= 0) {
2376 movi(Vd, T, (imm32 >> shift) & 0xff, shift);
2377 } else {
2378 movw(rscratch1, imm32);
2379 dup(Vd, T, rscratch1);
2380 }
2381 }
2382
2383 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
2384 {
2385 #ifndef PRODUCT
2386 {
2387 char buffer[64];
2388 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, imm64);
2389 block_comment(buffer);
2390 }
2391 #endif
2392 if (operand_valid_for_logical_immediate(false, imm64)) {
2393 orr(dst, zr, imm64);
2394 } else {
2395 // we can use a combination of MOVZ or MOVN with
2396 // MOVK to build up the constant
2397 uint64_t imm_h[4];
2398 int zero_count = 0;
2399 int neg_count = 0;
2400 int i;
2401 for (i = 0; i < 4; i++) {
2402 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
2403 if (imm_h[i] == 0) {
2404 zero_count++;
2405 } else if (imm_h[i] == 0xffffL) {
2406 neg_count++;
2407 }
2408 }
2409 if (zero_count == 4) {
2410 // one MOVZ will do
2411 movz(dst, 0);
2412 } else if (neg_count == 4) {
2413 // one MOVN will do
2414 movn(dst, 0);
2415 } else if (zero_count == 3) {
2416 for (i = 0; i < 4; i++) {
2417 if (imm_h[i] != 0L) {
2418 movz(dst, (uint32_t)imm_h[i], (i << 4));
2419 break;
2420 }
2421 }
2422 } else if (neg_count == 3) {
2423 // one MOVN will do
2424 for (int i = 0; i < 4; i++) {
2425 if (imm_h[i] != 0xffffL) {
2426 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2427 break;
2428 }
2429 }
2430 } else if (zero_count == 2) {
2431 // one MOVZ and one MOVK will do
2432 for (i = 0; i < 3; i++) {
2433 if (imm_h[i] != 0L) {
2434 movz(dst, (uint32_t)imm_h[i], (i << 4));
2435 i++;
2436 break;
2437 }
2438 }
2439 for (;i < 4; i++) {
2440 if (imm_h[i] != 0L) {
2441 movk(dst, (uint32_t)imm_h[i], (i << 4));
2442 }
2443 }
2444 } else if (neg_count == 2) {
2445 // one MOVN and one MOVK will do
2446 for (i = 0; i < 4; i++) {
2447 if (imm_h[i] != 0xffffL) {
2448 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2449 i++;
2450 break;
2451 }
2452 }
2453 for (;i < 4; i++) {
2454 if (imm_h[i] != 0xffffL) {
2455 movk(dst, (uint32_t)imm_h[i], (i << 4));
2456 }
2457 }
2458 } else if (zero_count == 1) {
2459 // one MOVZ and two MOVKs will do
2460 for (i = 0; i < 4; i++) {
2461 if (imm_h[i] != 0L) {
2462 movz(dst, (uint32_t)imm_h[i], (i << 4));
2463 i++;
2464 break;
2465 }
2466 }
2467 for (;i < 4; i++) {
2468 if (imm_h[i] != 0x0L) {
2469 movk(dst, (uint32_t)imm_h[i], (i << 4));
2470 }
2471 }
2472 } else if (neg_count == 1) {
2473 // one MOVN and two MOVKs will do
2474 for (i = 0; i < 4; i++) {
2475 if (imm_h[i] != 0xffffL) {
2476 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2477 i++;
2478 break;
2479 }
2480 }
2481 for (;i < 4; i++) {
2482 if (imm_h[i] != 0xffffL) {
2483 movk(dst, (uint32_t)imm_h[i], (i << 4));
2484 }
2485 }
2486 } else {
2487 // use a MOVZ and 3 MOVKs (makes it easier to debug)
2488 movz(dst, (uint32_t)imm_h[0], 0);
2489 for (i = 1; i < 4; i++) {
2490 movk(dst, (uint32_t)imm_h[i], (i << 4));
2491 }
2492 }
2493 }
2494 }
2495
2496 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
2497 {
2498 #ifndef PRODUCT
2499 {
2500 char buffer[64];
2501 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX32, imm32);
2502 block_comment(buffer);
2503 }
2504 #endif
2505 if (operand_valid_for_logical_immediate(true, imm32)) {
2506 orrw(dst, zr, imm32);
2507 } else {
2508 // we can use MOVZ, MOVN or two calls to MOVK to build up the
2509 // constant
2510 uint32_t imm_h[2];
2511 imm_h[0] = imm32 & 0xffff;
2512 imm_h[1] = ((imm32 >> 16) & 0xffff);
2513 if (imm_h[0] == 0) {
2514 movzw(dst, imm_h[1], 16);
2515 } else if (imm_h[0] == 0xffff) {
2516 movnw(dst, imm_h[1] ^ 0xffff, 16);
2517 } else if (imm_h[1] == 0) {
2518 movzw(dst, imm_h[0], 0);
2519 } else if (imm_h[1] == 0xffff) {
2520 movnw(dst, imm_h[0] ^ 0xffff, 0);
2521 } else {
2522 // use a MOVZ and MOVK (makes it easier to debug)
2523 movzw(dst, imm_h[0], 0);
2524 movkw(dst, imm_h[1], 16);
2525 }
2526 }
2527 }
2528
2529 // Form an address from base + offset in Rd. Rd may or may
2530 // not actually be used: you must use the Address that is returned.
2531 // It is up to you to ensure that the shift provided matches the size
2532 // of your data.
2533 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
2534 if (Address::offset_ok_for_immed(byte_offset, shift))
2535 // It fits; no need for any heroics
2536 return Address(base, byte_offset);
2537
2538 // Don't do anything clever with negative or misaligned offsets
2539 unsigned mask = (1 << shift) - 1;
2540 if (byte_offset < 0 || byte_offset & mask) {
2541 mov(Rd, byte_offset);
2542 add(Rd, base, Rd);
2543 return Address(Rd);
2544 }
2545
2546 // See if we can do this with two 12-bit offsets
2547 {
2548 uint64_t word_offset = byte_offset >> shift;
2549 uint64_t masked_offset = word_offset & 0xfff000;
2550 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
2551 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
2552 add(Rd, base, masked_offset << shift);
2553 word_offset -= masked_offset;
2554 return Address(Rd, word_offset << shift);
2555 }
2556 }
2557
2558 // Do it the hard way
2559 mov(Rd, byte_offset);
2560 add(Rd, base, Rd);
2561 return Address(Rd);
2562 }
2563
2564 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
2565 bool want_remainder, Register scratch)
2566 {
2567 // Full implementation of Java idiv and irem. The function
2568 // returns the (pc) offset of the div instruction - may be needed
2569 // for implicit exceptions.
2570 //
2571 // constraint : ra/rb =/= scratch
2572 // normal case
2573 //
2574 // input : ra: dividend
2575 // rb: divisor
2576 //
2577 // result: either
2578 // quotient (= ra idiv rb)
2579 // remainder (= ra irem rb)
2580
2581 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2582
2583 int idivl_offset = offset();
2584 if (! want_remainder) {
2585 sdivw(result, ra, rb);
2586 } else {
2587 sdivw(scratch, ra, rb);
2588 Assembler::msubw(result, scratch, rb, ra);
2589 }
2590
2591 return idivl_offset;
2592 }
2593
2594 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
2595 bool want_remainder, Register scratch)
2596 {
2597 // Full implementation of Java ldiv and lrem. The function
2598 // returns the (pc) offset of the div instruction - may be needed
2599 // for implicit exceptions.
2600 //
2601 // constraint : ra/rb =/= scratch
2602 // normal case
2603 //
2604 // input : ra: dividend
2605 // rb: divisor
2606 //
2607 // result: either
2608 // quotient (= ra idiv rb)
2609 // remainder (= ra irem rb)
2610
2611 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2612
2613 int idivq_offset = offset();
2614 if (! want_remainder) {
2615 sdiv(result, ra, rb);
2616 } else {
2617 sdiv(scratch, ra, rb);
2618 Assembler::msub(result, scratch, rb, ra);
2619 }
2620
2621 return idivq_offset;
2622 }
2623
2624 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
2625 address prev = pc() - NativeMembar::instruction_size;
2626 address last = code()->last_insn();
2627 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) {
2628 NativeMembar *bar = NativeMembar_at(prev);
2629 if (AlwaysMergeDMB) {
2630 bar->set_kind(bar->get_kind() | order_constraint);
2631 BLOCK_COMMENT("merged membar(always)");
2632 return;
2633 }
2634 // Don't promote DMB ST|DMB LD to DMB (a full barrier) because
2635 // doing so would introduce a StoreLoad which the caller did not
2636 // intend
2637 if (bar->get_kind() == order_constraint
2638 || bar->get_kind() == AnyAny
2639 || order_constraint == AnyAny) {
2640 // We are merging two memory barrier instructions. On AArch64 we
2641 // can do this simply by ORing them together.
2642 bar->set_kind(bar->get_kind() | order_constraint);
2643 BLOCK_COMMENT("merged membar");
2644 return;
2645 } else {
2646 // A special case like "DMB ST;DMB LD;DMB ST", the last DMB can be skipped
2647 // We need check the last 2 instructions
2648 address prev2 = prev - NativeMembar::instruction_size;
2649 if (last != code()->last_label() && nativeInstruction_at(prev2)->is_Membar()) {
2650 NativeMembar *bar2 = NativeMembar_at(prev2);
2651 assert(bar2->get_kind() == order_constraint, "it should be merged before");
2652 BLOCK_COMMENT("merged membar(elided)");
2653 return;
2654 }
2655 }
2656 }
2657 code()->set_last_insn(pc());
2658 dmb(Assembler::barrier(order_constraint));
2659 }
2660
2661 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
2662 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
2663 merge_ldst(rt, adr, size_in_bytes, is_store);
2664 code()->clear_last_insn();
2665 return true;
2666 } else {
2667 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
2668 const uint64_t mask = size_in_bytes - 1;
2669 if (adr.getMode() == Address::base_plus_offset &&
2670 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
2671 code()->set_last_insn(pc());
2672 }
2673 return false;
2674 }
2675 }
2676
2677 void MacroAssembler::ldr(Register Rx, const Address &adr) {
2678 // We always try to merge two adjacent loads into one ldp.
2679 if (!try_merge_ldst(Rx, adr, 8, false)) {
2680 Assembler::ldr(Rx, adr);
2681 }
2682 }
2683
2684 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
2685 // We always try to merge two adjacent loads into one ldp.
2686 if (!try_merge_ldst(Rw, adr, 4, false)) {
2687 Assembler::ldrw(Rw, adr);
2688 }
2689 }
2690
2691 void MacroAssembler::str(Register Rx, const Address &adr) {
2692 // We always try to merge two adjacent stores into one stp.
2693 if (!try_merge_ldst(Rx, adr, 8, true)) {
2694 Assembler::str(Rx, adr);
2695 }
2696 }
2697
2698 void MacroAssembler::strw(Register Rw, const Address &adr) {
2699 // We always try to merge two adjacent stores into one stp.
2700 if (!try_merge_ldst(Rw, adr, 4, true)) {
2701 Assembler::strw(Rw, adr);
2702 }
2703 }
2704
2705 // MacroAssembler routines found actually to be needed
2706
2707 void MacroAssembler::push(Register src)
2708 {
2709 str(src, Address(pre(esp, -1 * wordSize)));
2710 }
2711
2712 void MacroAssembler::pop(Register dst)
2713 {
2714 ldr(dst, Address(post(esp, 1 * wordSize)));
2715 }
2716
2717 // Note: load_unsigned_short used to be called load_unsigned_word.
2718 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2719 int off = offset();
2720 ldrh(dst, src);
2721 return off;
2722 }
2723
2724 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2725 int off = offset();
2726 ldrb(dst, src);
2727 return off;
2728 }
2729
2730 int MacroAssembler::load_signed_short(Register dst, Address src) {
2731 int off = offset();
2732 ldrsh(dst, src);
2733 return off;
2734 }
2735
2736 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2737 int off = offset();
2738 ldrsb(dst, src);
2739 return off;
2740 }
2741
2742 int MacroAssembler::load_signed_short32(Register dst, Address src) {
2743 int off = offset();
2744 ldrshw(dst, src);
2745 return off;
2746 }
2747
2748 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
2749 int off = offset();
2750 ldrsbw(dst, src);
2751 return off;
2752 }
2753
2754 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2755 switch (size_in_bytes) {
2756 case 8: ldr(dst, src); break;
2757 case 4: ldrw(dst, src); break;
2758 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2759 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2760 default: ShouldNotReachHere();
2761 }
2762 }
2763
2764 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) {
2765 switch (size_in_bytes) {
2766 case 8: str(src, dst); break;
2767 case 4: strw(src, dst); break;
2768 case 2: strh(src, dst); break;
2769 case 1: strb(src, dst); break;
2770 default: ShouldNotReachHere();
2771 }
2772 }
2773
2774 void MacroAssembler::decrementw(Register reg, int value)
2775 {
2776 if (value < 0) { incrementw(reg, -value); return; }
2777 if (value == 0) { return; }
2778 if (value < (1 << 12)) { subw(reg, reg, value); return; }
2779 /* else */ {
2780 guarantee(reg != rscratch2, "invalid dst for register decrement");
2781 movw(rscratch2, (unsigned)value);
2782 subw(reg, reg, rscratch2);
2783 }
2784 }
2785
2786 void MacroAssembler::decrement(Register reg, int value)
2787 {
2788 if (value < 0) { increment(reg, -value); return; }
2789 if (value == 0) { return; }
2790 if (value < (1 << 12)) { sub(reg, reg, value); return; }
2791 /* else */ {
2792 assert(reg != rscratch2, "invalid dst for register decrement");
2793 mov(rscratch2, (uint64_t)value);
2794 sub(reg, reg, rscratch2);
2795 }
2796 }
2797
2798 void MacroAssembler::decrementw(Address dst, int value)
2799 {
2800 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
2801 if (dst.getMode() == Address::literal) {
2802 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2803 lea(rscratch2, dst);
2804 dst = Address(rscratch2);
2805 }
2806 ldrw(rscratch1, dst);
2807 decrementw(rscratch1, value);
2808 strw(rscratch1, dst);
2809 }
2810
2811 void MacroAssembler::decrement(Address dst, int value)
2812 {
2813 assert(!dst.uses(rscratch1), "invalid address for decrement");
2814 if (dst.getMode() == Address::literal) {
2815 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2816 lea(rscratch2, dst);
2817 dst = Address(rscratch2);
2818 }
2819 ldr(rscratch1, dst);
2820 decrement(rscratch1, value);
2821 str(rscratch1, dst);
2822 }
2823
2824 void MacroAssembler::incrementw(Register reg, int value)
2825 {
2826 if (value < 0) { decrementw(reg, -value); return; }
2827 if (value == 0) { return; }
2828 if (value < (1 << 12)) { addw(reg, reg, value); return; }
2829 /* else */ {
2830 assert(reg != rscratch2, "invalid dst for register increment");
2831 movw(rscratch2, (unsigned)value);
2832 addw(reg, reg, rscratch2);
2833 }
2834 }
2835
2836 void MacroAssembler::increment(Register reg, int value)
2837 {
2838 if (value < 0) { decrement(reg, -value); return; }
2839 if (value == 0) { return; }
2840 if (value < (1 << 12)) { add(reg, reg, value); return; }
2841 /* else */ {
2842 assert(reg != rscratch2, "invalid dst for register increment");
2843 movw(rscratch2, (unsigned)value);
2844 add(reg, reg, rscratch2);
2845 }
2846 }
2847
2848 void MacroAssembler::incrementw(Address dst, int value)
2849 {
2850 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2851 if (dst.getMode() == Address::literal) {
2852 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2853 lea(rscratch2, dst);
2854 dst = Address(rscratch2);
2855 }
2856 ldrw(rscratch1, dst);
2857 incrementw(rscratch1, value);
2858 strw(rscratch1, dst);
2859 }
2860
2861 void MacroAssembler::increment(Address dst, int value)
2862 {
2863 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2864 if (dst.getMode() == Address::literal) {
2865 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2866 lea(rscratch2, dst);
2867 dst = Address(rscratch2);
2868 }
2869 ldr(rscratch1, dst);
2870 increment(rscratch1, value);
2871 str(rscratch1, dst);
2872 }
2873
2874 // Push lots of registers in the bit set supplied. Don't push sp.
2875 // Return the number of words pushed
2876 int MacroAssembler::push(unsigned int bitset, Register stack) {
2877 int words_pushed = 0;
2878
2879 // Scan bitset to accumulate register pairs
2880 unsigned char regs[32];
2881 int count = 0;
2882 for (int reg = 0; reg <= 30; reg++) {
2883 if (1 & bitset)
2884 regs[count++] = reg;
2885 bitset >>= 1;
2886 }
2887 regs[count++] = zr->raw_encoding();
2888 count &= ~1; // Only push an even number of regs
2889
2890 if (count) {
2891 stp(as_Register(regs[0]), as_Register(regs[1]),
2892 Address(pre(stack, -count * wordSize)));
2893 words_pushed += 2;
2894 }
2895 for (int i = 2; i < count; i += 2) {
2896 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2897 Address(stack, i * wordSize));
2898 words_pushed += 2;
2899 }
2900
2901 assert(words_pushed == count, "oops, pushed != count");
2902
2903 return count;
2904 }
2905
2906 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2907 int words_pushed = 0;
2908
2909 // Scan bitset to accumulate register pairs
2910 unsigned char regs[32];
2911 int count = 0;
2912 for (int reg = 0; reg <= 30; reg++) {
2913 if (1 & bitset)
2914 regs[count++] = reg;
2915 bitset >>= 1;
2916 }
2917 regs[count++] = zr->raw_encoding();
2918 count &= ~1;
2919
2920 for (int i = 2; i < count; i += 2) {
2921 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2922 Address(stack, i * wordSize));
2923 words_pushed += 2;
2924 }
2925 if (count) {
2926 ldp(as_Register(regs[0]), as_Register(regs[1]),
2927 Address(post(stack, count * wordSize)));
2928 words_pushed += 2;
2929 }
2930
2931 assert(words_pushed == count, "oops, pushed != count");
2932
2933 return count;
2934 }
2935
2936 // Push lots of registers in the bit set supplied. Don't push sp.
2937 // Return the number of dwords pushed
2938 int MacroAssembler::push_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
2939 int words_pushed = 0;
2940 bool use_sve = false;
2941 int sve_vector_size_in_bytes = 0;
2942
2943 #ifdef COMPILER2
2944 use_sve = Matcher::supports_scalable_vector();
2945 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
2946 #endif
2947
2948 // Scan bitset to accumulate register pairs
2949 unsigned char regs[32];
2950 int count = 0;
2951 for (int reg = 0; reg <= 31; reg++) {
2952 if (1 & bitset)
2953 regs[count++] = reg;
2954 bitset >>= 1;
2955 }
2956
2957 if (count == 0) {
2958 return 0;
2959 }
2960
2961 if (mode == PushPopFull) {
2962 if (use_sve && sve_vector_size_in_bytes > 16) {
2963 mode = PushPopSVE;
2964 } else {
2965 mode = PushPopNeon;
2966 }
2967 }
2968
2969 #ifndef PRODUCT
2970 {
2971 char buffer[48];
2972 if (mode == PushPopSVE) {
2973 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d SVE registers", count);
2974 } else if (mode == PushPopNeon) {
2975 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d Neon registers", count);
2976 } else {
2977 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d fp registers", count);
2978 }
2979 block_comment(buffer);
2980 }
2981 #endif
2982
2983 if (mode == PushPopSVE) {
2984 sub(stack, stack, sve_vector_size_in_bytes * count);
2985 for (int i = 0; i < count; i++) {
2986 sve_str(as_FloatRegister(regs[i]), Address(stack, i));
2987 }
2988 return count * sve_vector_size_in_bytes / 8;
2989 }
2990
2991 if (mode == PushPopNeon) {
2992 if (count == 1) {
2993 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2)));
2994 return 2;
2995 }
2996
2997 bool odd = (count & 1) == 1;
2998 int push_slots = count + (odd ? 1 : 0);
2999
3000 // Always pushing full 128 bit registers.
3001 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2)));
3002 words_pushed += 2;
3003
3004 for (int i = 2; i + 1 < count; i += 2) {
3005 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3006 words_pushed += 2;
3007 }
3008
3009 if (odd) {
3010 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3011 words_pushed++;
3012 }
3013
3014 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3015 return count * 2;
3016 }
3017
3018 if (mode == PushPopFp) {
3019 bool odd = (count & 1) == 1;
3020 int push_slots = count + (odd ? 1 : 0);
3021
3022 if (count == 1) {
3023 // Stack pointer must be 16 bytes aligned
3024 strd(as_FloatRegister(regs[0]), Address(pre(stack, -push_slots * wordSize)));
3025 return 1;
3026 }
3027
3028 stpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize)));
3029 words_pushed += 2;
3030
3031 for (int i = 2; i + 1 < count; i += 2) {
3032 stpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3033 words_pushed += 2;
3034 }
3035
3036 if (odd) {
3037 // Stack pointer must be 16 bytes aligned
3038 strd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3039 words_pushed++;
3040 }
3041
3042 assert(words_pushed == count, "oops, pushed != count");
3043
3044 return count;
3045 }
3046
3047 return 0;
3048 }
3049
3050 // Return the number of dwords popped
3051 int MacroAssembler::pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
3052 int words_pushed = 0;
3053 bool use_sve = false;
3054 int sve_vector_size_in_bytes = 0;
3055
3056 #ifdef COMPILER2
3057 use_sve = Matcher::supports_scalable_vector();
3058 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
3059 #endif
3060 // Scan bitset to accumulate register pairs
3061 unsigned char regs[32];
3062 int count = 0;
3063 for (int reg = 0; reg <= 31; reg++) {
3064 if (1 & bitset)
3065 regs[count++] = reg;
3066 bitset >>= 1;
3067 }
3068
3069 if (count == 0) {
3070 return 0;
3071 }
3072
3073 if (mode == PushPopFull) {
3074 if (use_sve && sve_vector_size_in_bytes > 16) {
3075 mode = PushPopSVE;
3076 } else {
3077 mode = PushPopNeon;
3078 }
3079 }
3080
3081 #ifndef PRODUCT
3082 {
3083 char buffer[48];
3084 if (mode == PushPopSVE) {
3085 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d SVE registers", count);
3086 } else if (mode == PushPopNeon) {
3087 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d Neon registers", count);
3088 } else {
3089 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d fp registers", count);
3090 }
3091 block_comment(buffer);
3092 }
3093 #endif
3094
3095 if (mode == PushPopSVE) {
3096 for (int i = count - 1; i >= 0; i--) {
3097 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i));
3098 }
3099 add(stack, stack, sve_vector_size_in_bytes * count);
3100 return count * sve_vector_size_in_bytes / 8;
3101 }
3102
3103 if (mode == PushPopNeon) {
3104 if (count == 1) {
3105 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2)));
3106 return 2;
3107 }
3108
3109 bool odd = (count & 1) == 1;
3110 int push_slots = count + (odd ? 1 : 0);
3111
3112 if (odd) {
3113 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3114 words_pushed++;
3115 }
3116
3117 for (int i = 2; i + 1 < count; i += 2) {
3118 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3119 words_pushed += 2;
3120 }
3121
3122 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2)));
3123 words_pushed += 2;
3124
3125 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3126
3127 return count * 2;
3128 }
3129
3130 if (mode == PushPopFp) {
3131 bool odd = (count & 1) == 1;
3132 int push_slots = count + (odd ? 1 : 0);
3133
3134 if (count == 1) {
3135 ldrd(as_FloatRegister(regs[0]), Address(post(stack, push_slots * wordSize)));
3136 return 1;
3137 }
3138
3139 if (odd) {
3140 ldrd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3141 words_pushed++;
3142 }
3143
3144 for (int i = 2; i + 1 < count; i += 2) {
3145 ldpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3146 words_pushed += 2;
3147 }
3148
3149 ldpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize)));
3150 words_pushed += 2;
3151
3152 assert(words_pushed == count, "oops, pushed != count");
3153
3154 return count;
3155 }
3156
3157 return 0;
3158 }
3159
3160 // Return the number of dwords pushed
3161 int MacroAssembler::push_p(unsigned int bitset, Register stack) {
3162 bool use_sve = false;
3163 int sve_predicate_size_in_slots = 0;
3164
3165 #ifdef COMPILER2
3166 use_sve = Matcher::supports_scalable_vector();
3167 if (use_sve) {
3168 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3169 }
3170 #endif
3171
3172 if (!use_sve) {
3173 return 0;
3174 }
3175
3176 unsigned char regs[PRegister::number_of_registers];
3177 int count = 0;
3178 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3179 if (1 & bitset)
3180 regs[count++] = reg;
3181 bitset >>= 1;
3182 }
3183
3184 if (count == 0) {
3185 return 0;
3186 }
3187
3188 int total_push_bytes = align_up(sve_predicate_size_in_slots *
3189 VMRegImpl::stack_slot_size * count, 16);
3190 sub(stack, stack, total_push_bytes);
3191 for (int i = 0; i < count; i++) {
3192 sve_str(as_PRegister(regs[i]), Address(stack, i));
3193 }
3194 return total_push_bytes / 8;
3195 }
3196
3197 // Return the number of dwords popped
3198 int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
3199 bool use_sve = false;
3200 int sve_predicate_size_in_slots = 0;
3201
3202 #ifdef COMPILER2
3203 use_sve = Matcher::supports_scalable_vector();
3204 if (use_sve) {
3205 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3206 }
3207 #endif
3208
3209 if (!use_sve) {
3210 return 0;
3211 }
3212
3213 unsigned char regs[PRegister::number_of_registers];
3214 int count = 0;
3215 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3216 if (1 & bitset)
3217 regs[count++] = reg;
3218 bitset >>= 1;
3219 }
3220
3221 if (count == 0) {
3222 return 0;
3223 }
3224
3225 int total_pop_bytes = align_up(sve_predicate_size_in_slots *
3226 VMRegImpl::stack_slot_size * count, 16);
3227 for (int i = count - 1; i >= 0; i--) {
3228 sve_ldr(as_PRegister(regs[i]), Address(stack, i));
3229 }
3230 add(stack, stack, total_pop_bytes);
3231 return total_pop_bytes / 8;
3232 }
3233
3234 #ifdef ASSERT
3235 void MacroAssembler::verify_heapbase(const char* msg) {
3236 #if 0
3237 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
3238 assert (Universe::heap() != nullptr, "java heap should be initialized");
3239 if (!UseCompressedOops || Universe::ptr_base() == nullptr) {
3240 // rheapbase is allocated as general register
3241 return;
3242 }
3243 if (CheckCompressedOops) {
3244 Label ok;
3245 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
3246 cmpptr(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3247 br(Assembler::EQ, ok);
3248 stop(msg);
3249 bind(ok);
3250 pop(1 << rscratch1->encoding(), sp);
3251 }
3252 #endif
3253 }
3254 #endif
3255
3256 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
3257 assert_different_registers(value, tmp1, tmp2);
3258 Label done, tagged, weak_tagged;
3259
3260 cbz(value, done); // Use null as-is.
3261 tst(value, JNIHandles::tag_mask); // Test for tag.
3262 br(Assembler::NE, tagged);
3263
3264 // Resolve local handle
3265 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2);
3266 verify_oop(value);
3267 b(done);
3268
3269 bind(tagged);
3270 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1);
3271 tbnz(value, 0, weak_tagged); // Test for weak tag.
3272
3273 // Resolve global handle
3274 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3275 verify_oop(value);
3276 b(done);
3277
3278 bind(weak_tagged);
3279 // Resolve jweak.
3280 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3281 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2);
3282 verify_oop(value);
3283
3284 bind(done);
3285 }
3286
3287 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) {
3288 assert_different_registers(value, tmp1, tmp2);
3289 Label done;
3290
3291 cbz(value, done); // Use null as-is.
3292
3293 #ifdef ASSERT
3294 {
3295 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10);
3296 Label valid_global_tag;
3297 tbnz(value, 1, valid_global_tag); // Test for global tag
3298 stop("non global jobject using resolve_global_jobject");
3299 bind(valid_global_tag);
3300 }
3301 #endif
3302
3303 // Resolve global handle
3304 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3305 verify_oop(value);
3306
3307 bind(done);
3308 }
3309
3310 void MacroAssembler::stop(const char* msg) {
3311 // Skip AOT caching C strings in scratch buffer.
3312 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
3313 BLOCK_COMMENT(str);
3314 // load msg into r0 so we can access it from the signal handler
3315 // ExternalAddress enables saving and restoring via the code cache
3316 lea(c_rarg0, ExternalAddress((address) str));
3317 dcps1(0xdeae);
3318 }
3319
3320 void MacroAssembler::unimplemented(const char* what) {
3321 const char* buf = nullptr;
3322 {
3323 ResourceMark rm;
3324 stringStream ss;
3325 ss.print("unimplemented: %s", what);
3326 buf = code_string(ss.as_string());
3327 }
3328 stop(buf);
3329 }
3330
3331 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
3332 #ifdef ASSERT
3333 Label OK;
3334 br(cc, OK);
3335 stop(msg);
3336 bind(OK);
3337 #endif
3338 }
3339
3340 // If a constant does not fit in an immediate field, generate some
3341 // number of MOV instructions and then perform the operation.
3342 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
3343 add_sub_imm_insn insn1,
3344 add_sub_reg_insn insn2,
3345 bool is32) {
3346 assert(Rd != zr, "Rd = zr and not setting flags?");
3347 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3348 if (fits) {
3349 (this->*insn1)(Rd, Rn, imm);
3350 } else {
3351 if (g_uabs(imm) < (1 << 24)) {
3352 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
3353 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
3354 } else {
3355 assert_different_registers(Rd, Rn);
3356 mov(Rd, imm);
3357 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3358 }
3359 }
3360 }
3361
3362 // Separate vsn which sets the flags. Optimisations are more restricted
3363 // because we must set the flags correctly.
3364 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
3365 add_sub_imm_insn insn1,
3366 add_sub_reg_insn insn2,
3367 bool is32) {
3368 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3369 if (fits) {
3370 (this->*insn1)(Rd, Rn, imm);
3371 } else {
3372 assert_different_registers(Rd, Rn);
3373 assert(Rd != zr, "overflow in immediate operand");
3374 mov(Rd, imm);
3375 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3376 }
3377 }
3378
3379
3380 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
3381 if (increment.is_register()) {
3382 add(Rd, Rn, increment.as_register());
3383 } else {
3384 add(Rd, Rn, increment.as_constant());
3385 }
3386 }
3387
3388 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
3389 if (increment.is_register()) {
3390 addw(Rd, Rn, increment.as_register());
3391 } else {
3392 addw(Rd, Rn, increment.as_constant());
3393 }
3394 }
3395
3396 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
3397 if (decrement.is_register()) {
3398 sub(Rd, Rn, decrement.as_register());
3399 } else {
3400 sub(Rd, Rn, decrement.as_constant());
3401 }
3402 }
3403
3404 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
3405 if (decrement.is_register()) {
3406 subw(Rd, Rn, decrement.as_register());
3407 } else {
3408 subw(Rd, Rn, decrement.as_constant());
3409 }
3410 }
3411
3412 void MacroAssembler::reinit_heapbase()
3413 {
3414 if (UseCompressedOops) {
3415 if (Universe::is_fully_initialized()) {
3416 mov(rheapbase, CompressedOops::base());
3417 } else {
3418 lea(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3419 ldr(rheapbase, Address(rheapbase));
3420 }
3421 }
3422 }
3423
3424 // A generic CAS; success or failure is in the EQ flag. A weak CAS
3425 // doesn't retry and may fail spuriously. If the oldval is wanted,
3426 // Pass a register for the result, otherwise pass noreg.
3427
3428 // Clobbers rscratch1
3429 void MacroAssembler::cmpxchg(Register addr, Register expected,
3430 Register new_val,
3431 enum operand_size size,
3432 bool acquire, bool release,
3433 bool weak,
3434 Register result) {
3435 if (result == noreg) result = rscratch1;
3436 BLOCK_COMMENT("cmpxchg {");
3437 if (UseLSE) {
3438 mov(result, expected);
3439 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
3440 compare_eq(result, expected, size);
3441 #ifdef ASSERT
3442 // Poison rscratch1 which is written on !UseLSE branch
3443 mov(rscratch1, 0x1f1f1f1f1f1f1f1f);
3444 #endif
3445 } else {
3446 Label retry_load, done;
3447 prfm(Address(addr), PSTL1STRM);
3448 bind(retry_load);
3449 load_exclusive(result, addr, size, acquire);
3450 compare_eq(result, expected, size);
3451 br(Assembler::NE, done);
3452 store_exclusive(rscratch1, new_val, addr, size, release);
3453 if (weak) {
3454 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
3455 } else {
3456 cbnzw(rscratch1, retry_load);
3457 }
3458 bind(done);
3459 }
3460 BLOCK_COMMENT("} cmpxchg");
3461 }
3462
3463 // A generic comparison. Only compares for equality, clobbers rscratch1.
3464 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
3465 if (size == xword) {
3466 cmp(rm, rn);
3467 } else if (size == word) {
3468 cmpw(rm, rn);
3469 } else if (size == halfword) {
3470 eorw(rscratch1, rm, rn);
3471 ands(zr, rscratch1, 0xffff);
3472 } else if (size == byte) {
3473 eorw(rscratch1, rm, rn);
3474 ands(zr, rscratch1, 0xff);
3475 } else {
3476 ShouldNotReachHere();
3477 }
3478 }
3479
3480
3481 static bool different(Register a, RegisterOrConstant b, Register c) {
3482 if (b.is_constant())
3483 return a != c;
3484 else
3485 return a != b.as_register() && a != c && b.as_register() != c;
3486 }
3487
3488 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
3489 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
3490 if (UseLSE) { \
3491 prev = prev->is_valid() ? prev : zr; \
3492 if (incr.is_register()) { \
3493 AOP(sz, incr.as_register(), prev, addr); \
3494 } else { \
3495 mov(rscratch2, incr.as_constant()); \
3496 AOP(sz, rscratch2, prev, addr); \
3497 } \
3498 return; \
3499 } \
3500 Register result = rscratch2; \
3501 if (prev->is_valid()) \
3502 result = different(prev, incr, addr) ? prev : rscratch2; \
3503 \
3504 Label retry_load; \
3505 prfm(Address(addr), PSTL1STRM); \
3506 bind(retry_load); \
3507 LDXR(result, addr); \
3508 OP(rscratch1, result, incr); \
3509 STXR(rscratch2, rscratch1, addr); \
3510 cbnzw(rscratch2, retry_load); \
3511 if (prev->is_valid() && prev != result) { \
3512 IOP(prev, rscratch1, incr); \
3513 } \
3514 }
3515
3516 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
3517 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
3518 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
3519 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
3520
3521 #undef ATOMIC_OP
3522
3523 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
3524 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
3525 if (UseLSE) { \
3526 prev = prev->is_valid() ? prev : zr; \
3527 AOP(sz, newv, prev, addr); \
3528 return; \
3529 } \
3530 Register result = rscratch2; \
3531 if (prev->is_valid()) \
3532 result = different(prev, newv, addr) ? prev : rscratch2; \
3533 \
3534 Label retry_load; \
3535 prfm(Address(addr), PSTL1STRM); \
3536 bind(retry_load); \
3537 LDXR(result, addr); \
3538 STXR(rscratch1, newv, addr); \
3539 cbnzw(rscratch1, retry_load); \
3540 if (prev->is_valid() && prev != result) \
3541 mov(prev, result); \
3542 }
3543
3544 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
3545 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
3546 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
3547 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
3548 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
3549 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
3550
3551 #undef ATOMIC_XCHG
3552
3553 #ifndef PRODUCT
3554 extern "C" void findpc(intptr_t x);
3555 #endif
3556
3557 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
3558 {
3559 // In order to get locks to work, we need to fake a in_VM state
3560 if (ShowMessageBoxOnError ) {
3561 JavaThread* thread = JavaThread::current();
3562 JavaThreadState saved_state = thread->thread_state();
3563 thread->set_thread_state(_thread_in_vm);
3564 #ifndef PRODUCT
3565 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
3566 ttyLocker ttyl;
3567 BytecodeCounter::print();
3568 }
3569 #endif
3570 if (os::message_box(msg, "Execution stopped, print registers?")) {
3571 ttyLocker ttyl;
3572 tty->print_cr(" pc = 0x%016" PRIx64, pc);
3573 #ifndef PRODUCT
3574 tty->cr();
3575 findpc(pc);
3576 tty->cr();
3577 #endif
3578 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
3579 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
3580 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
3581 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
3582 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
3583 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
3584 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
3585 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
3586 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
3587 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
3588 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
3589 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
3590 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
3591 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
3592 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
3593 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
3594 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
3595 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
3596 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
3597 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
3598 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
3599 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
3600 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
3601 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
3602 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
3603 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
3604 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
3605 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
3606 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
3607 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
3608 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
3609 BREAKPOINT;
3610 }
3611 }
3612 fatal("DEBUG MESSAGE: %s", msg);
3613 }
3614
3615 RegSet MacroAssembler::call_clobbered_gp_registers() {
3616 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
3617 #ifndef R18_RESERVED
3618 regs += r18_tls;
3619 #endif
3620 return regs;
3621 }
3622
3623 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
3624 int step = 4 * wordSize;
3625 push(call_clobbered_gp_registers() - exclude, sp);
3626 sub(sp, sp, step);
3627 mov(rscratch1, -step);
3628 // Push v0-v7, v16-v31.
3629 for (int i = 31; i>= 4; i -= 4) {
3630 if (i <= v7->encoding() || i >= v16->encoding())
3631 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
3632 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
3633 }
3634 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
3635 as_FloatRegister(3), T1D, Address(sp));
3636 }
3637
3638 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
3639 for (int i = 0; i < 32; i += 4) {
3640 if (i <= v7->encoding() || i >= v16->encoding())
3641 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3642 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
3643 }
3644
3645 reinitialize_ptrue();
3646
3647 pop(call_clobbered_gp_registers() - exclude, sp);
3648 }
3649
3650 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
3651 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3652 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
3653 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3654 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3655 for (int i = 0; i < FloatRegister::number_of_registers; i++) {
3656 sve_str(as_FloatRegister(i), Address(sp, i));
3657 }
3658 } else {
3659 int step = (save_vectors ? 8 : 4) * wordSize;
3660 mov(rscratch1, -step);
3661 sub(sp, sp, step);
3662 for (int i = 28; i >= 4; i -= 4) {
3663 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3664 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
3665 }
3666 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
3667 }
3668 if (save_vectors && use_sve && total_predicate_in_bytes > 0) {
3669 sub(sp, sp, total_predicate_in_bytes);
3670 for (int i = 0; i < PRegister::number_of_registers; i++) {
3671 sve_str(as_PRegister(i), Address(sp, i));
3672 }
3673 }
3674 }
3675
3676 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
3677 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3678 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) {
3679 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) {
3680 sve_ldr(as_PRegister(i), Address(sp, i));
3681 }
3682 add(sp, sp, total_predicate_in_bytes);
3683 }
3684 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3685 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) {
3686 sve_ldr(as_FloatRegister(i), Address(sp, i));
3687 }
3688 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3689 } else {
3690 int step = (restore_vectors ? 8 : 4) * wordSize;
3691 for (int i = 0; i <= 28; i += 4)
3692 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3693 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
3694 }
3695
3696 // We may use predicate registers and rely on ptrue with SVE,
3697 // regardless of wide vector (> 8 bytes) used or not.
3698 if (use_sve) {
3699 reinitialize_ptrue();
3700 }
3701
3702 // integer registers except lr & sp
3703 pop(RegSet::range(r0, r17), sp);
3704 #ifdef R18_RESERVED
3705 ldp(zr, r19, Address(post(sp, 2 * wordSize)));
3706 pop(RegSet::range(r20, r29), sp);
3707 #else
3708 pop(RegSet::range(r18_tls, r29), sp);
3709 #endif
3710 }
3711
3712 /**
3713 * Helpers for multiply_to_len().
3714 */
3715 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
3716 Register src1, Register src2) {
3717 adds(dest_lo, dest_lo, src1);
3718 adc(dest_hi, dest_hi, zr);
3719 adds(dest_lo, dest_lo, src2);
3720 adc(final_dest_hi, dest_hi, zr);
3721 }
3722
3723 // Generate an address from (r + r1 extend offset). "size" is the
3724 // size of the operand. The result may be in rscratch2.
3725 Address MacroAssembler::offsetted_address(Register r, Register r1,
3726 Address::extend ext, int offset, int size) {
3727 if (offset || (ext.shift() % size != 0)) {
3728 lea(rscratch2, Address(r, r1, ext));
3729 return Address(rscratch2, offset);
3730 } else {
3731 return Address(r, r1, ext);
3732 }
3733 }
3734
3735 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
3736 {
3737 assert(offset >= 0, "spill to negative address?");
3738 // Offset reachable ?
3739 // Not aligned - 9 bits signed offset
3740 // Aligned - 12 bits unsigned offset shifted
3741 Register base = sp;
3742 if ((offset & (size-1)) && offset >= (1<<8)) {
3743 add(tmp, base, offset & ((1<<12)-1));
3744 base = tmp;
3745 offset &= -1u<<12;
3746 }
3747
3748 if (offset >= (1<<12) * size) {
3749 add(tmp, base, offset & (((1<<12)-1)<<12));
3750 base = tmp;
3751 offset &= ~(((1<<12)-1)<<12);
3752 }
3753
3754 return Address(base, offset);
3755 }
3756
3757 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) {
3758 assert(offset >= 0, "spill to negative address?");
3759
3760 Register base = sp;
3761
3762 // An immediate offset in the range 0 to 255 which is multiplied
3763 // by the current vector or predicate register size in bytes.
3764 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) {
3765 return Address(base, offset / sve_reg_size_in_bytes);
3766 }
3767
3768 add(tmp, base, offset);
3769 return Address(tmp);
3770 }
3771
3772 // Checks whether offset is aligned.
3773 // Returns true if it is, else false.
3774 bool MacroAssembler::merge_alignment_check(Register base,
3775 size_t size,
3776 int64_t cur_offset,
3777 int64_t prev_offset) const {
3778 if (AvoidUnalignedAccesses) {
3779 if (base == sp) {
3780 // Checks whether low offset if aligned to pair of registers.
3781 int64_t pair_mask = size * 2 - 1;
3782 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3783 return (offset & pair_mask) == 0;
3784 } else { // If base is not sp, we can't guarantee the access is aligned.
3785 return false;
3786 }
3787 } else {
3788 int64_t mask = size - 1;
3789 // Load/store pair instruction only supports element size aligned offset.
3790 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
3791 }
3792 }
3793
3794 // Checks whether current and previous loads/stores can be merged.
3795 // Returns true if it can be merged, else false.
3796 bool MacroAssembler::ldst_can_merge(Register rt,
3797 const Address &adr,
3798 size_t cur_size_in_bytes,
3799 bool is_store) const {
3800 address prev = pc() - NativeInstruction::instruction_size;
3801 address last = code()->last_insn();
3802
3803 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) {
3804 return false;
3805 }
3806
3807 if (adr.getMode() != Address::base_plus_offset || prev != last) {
3808 return false;
3809 }
3810
3811 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3812 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
3813
3814 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
3815 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
3816
3817 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
3818 return false;
3819 }
3820
3821 int64_t max_offset = 63 * prev_size_in_bytes;
3822 int64_t min_offset = -64 * prev_size_in_bytes;
3823
3824 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
3825
3826 // Only same base can be merged.
3827 if (adr.base() != prev_ldst->base()) {
3828 return false;
3829 }
3830
3831 int64_t cur_offset = adr.offset();
3832 int64_t prev_offset = prev_ldst->offset();
3833 size_t diff = abs(cur_offset - prev_offset);
3834 if (diff != prev_size_in_bytes) {
3835 return false;
3836 }
3837
3838 // Following cases can not be merged:
3839 // ldr x2, [x2, #8]
3840 // ldr x3, [x2, #16]
3841 // or:
3842 // ldr x2, [x3, #8]
3843 // ldr x2, [x3, #16]
3844 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
3845 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
3846 return false;
3847 }
3848
3849 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3850 // Offset range must be in ldp/stp instruction's range.
3851 if (low_offset > max_offset || low_offset < min_offset) {
3852 return false;
3853 }
3854
3855 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
3856 return true;
3857 }
3858
3859 return false;
3860 }
3861
3862 // Merge current load/store with previous load/store into ldp/stp.
3863 void MacroAssembler::merge_ldst(Register rt,
3864 const Address &adr,
3865 size_t cur_size_in_bytes,
3866 bool is_store) {
3867
3868 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
3869
3870 Register rt_low, rt_high;
3871 address prev = pc() - NativeInstruction::instruction_size;
3872 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3873
3874 int64_t offset;
3875
3876 if (adr.offset() < prev_ldst->offset()) {
3877 offset = adr.offset();
3878 rt_low = rt;
3879 rt_high = prev_ldst->target();
3880 } else {
3881 offset = prev_ldst->offset();
3882 rt_low = prev_ldst->target();
3883 rt_high = rt;
3884 }
3885
3886 Address adr_p = Address(prev_ldst->base(), offset);
3887 // Overwrite previous generated binary.
3888 code_section()->set_end(prev);
3889
3890 const size_t sz = prev_ldst->size_in_bytes();
3891 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
3892 if (!is_store) {
3893 BLOCK_COMMENT("merged ldr pair");
3894 if (sz == 8) {
3895 ldp(rt_low, rt_high, adr_p);
3896 } else {
3897 ldpw(rt_low, rt_high, adr_p);
3898 }
3899 } else {
3900 BLOCK_COMMENT("merged str pair");
3901 if (sz == 8) {
3902 stp(rt_low, rt_high, adr_p);
3903 } else {
3904 stpw(rt_low, rt_high, adr_p);
3905 }
3906 }
3907 }
3908
3909 /**
3910 * Multiply 64 bit by 64 bit first loop.
3911 */
3912 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
3913 Register y, Register y_idx, Register z,
3914 Register carry, Register product,
3915 Register idx, Register kdx) {
3916 //
3917 // jlong carry, x[], y[], z[];
3918 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3919 // huge_128 product = y[idx] * x[xstart] + carry;
3920 // z[kdx] = (jlong)product;
3921 // carry = (jlong)(product >>> 64);
3922 // }
3923 // z[xstart] = carry;
3924 //
3925
3926 Label L_first_loop, L_first_loop_exit;
3927 Label L_one_x, L_one_y, L_multiply;
3928
3929 subsw(xstart, xstart, 1);
3930 br(Assembler::MI, L_one_x);
3931
3932 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
3933 ldr(x_xstart, Address(rscratch1));
3934 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
3935
3936 bind(L_first_loop);
3937 subsw(idx, idx, 1);
3938 br(Assembler::MI, L_first_loop_exit);
3939 subsw(idx, idx, 1);
3940 br(Assembler::MI, L_one_y);
3941 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3942 ldr(y_idx, Address(rscratch1));
3943 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
3944 bind(L_multiply);
3945
3946 // AArch64 has a multiply-accumulate instruction that we can't use
3947 // here because it has no way to process carries, so we have to use
3948 // separate add and adc instructions. Bah.
3949 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
3950 mul(product, x_xstart, y_idx);
3951 adds(product, product, carry);
3952 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
3953
3954 subw(kdx, kdx, 2);
3955 ror(product, product, 32); // back to big-endian
3956 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
3957
3958 b(L_first_loop);
3959
3960 bind(L_one_y);
3961 ldrw(y_idx, Address(y, 0));
3962 b(L_multiply);
3963
3964 bind(L_one_x);
3965 ldrw(x_xstart, Address(x, 0));
3966 b(L_first_loop);
3967
3968 bind(L_first_loop_exit);
3969 }
3970
3971 /**
3972 * Multiply 128 bit by 128. Unrolled inner loop.
3973 *
3974 */
3975 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
3976 Register carry, Register carry2,
3977 Register idx, Register jdx,
3978 Register yz_idx1, Register yz_idx2,
3979 Register tmp, Register tmp3, Register tmp4,
3980 Register tmp6, Register product_hi) {
3981
3982 // jlong carry, x[], y[], z[];
3983 // int kdx = ystart+1;
3984 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
3985 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
3986 // jlong carry2 = (jlong)(tmp3 >>> 64);
3987 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
3988 // carry = (jlong)(tmp4 >>> 64);
3989 // z[kdx+idx+1] = (jlong)tmp3;
3990 // z[kdx+idx] = (jlong)tmp4;
3991 // }
3992 // idx += 2;
3993 // if (idx > 0) {
3994 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
3995 // z[kdx+idx] = (jlong)yz_idx1;
3996 // carry = (jlong)(yz_idx1 >>> 64);
3997 // }
3998 //
3999
4000 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
4001
4002 lsrw(jdx, idx, 2);
4003
4004 bind(L_third_loop);
4005
4006 subsw(jdx, jdx, 1);
4007 br(Assembler::MI, L_third_loop_exit);
4008 subw(idx, idx, 4);
4009
4010 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4011
4012 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
4013
4014 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4015
4016 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
4017 ror(yz_idx2, yz_idx2, 32);
4018
4019 ldp(rscratch2, rscratch1, Address(tmp6, 0));
4020
4021 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4022 umulh(tmp4, product_hi, yz_idx1);
4023
4024 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
4025 ror(rscratch2, rscratch2, 32);
4026
4027 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
4028 umulh(carry2, product_hi, yz_idx2);
4029
4030 // propagate sum of both multiplications into carry:tmp4:tmp3
4031 adds(tmp3, tmp3, carry);
4032 adc(tmp4, tmp4, zr);
4033 adds(tmp3, tmp3, rscratch1);
4034 adcs(tmp4, tmp4, tmp);
4035 adc(carry, carry2, zr);
4036 adds(tmp4, tmp4, rscratch2);
4037 adc(carry, carry, zr);
4038
4039 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
4040 ror(tmp4, tmp4, 32);
4041 stp(tmp4, tmp3, Address(tmp6, 0));
4042
4043 b(L_third_loop);
4044 bind (L_third_loop_exit);
4045
4046 andw (idx, idx, 0x3);
4047 cbz(idx, L_post_third_loop_done);
4048
4049 Label L_check_1;
4050 subsw(idx, idx, 2);
4051 br(Assembler::MI, L_check_1);
4052
4053 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4054 ldr(yz_idx1, Address(rscratch1, 0));
4055 ror(yz_idx1, yz_idx1, 32);
4056 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4057 umulh(tmp4, product_hi, yz_idx1);
4058 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4059 ldr(yz_idx2, Address(rscratch1, 0));
4060 ror(yz_idx2, yz_idx2, 32);
4061
4062 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
4063
4064 ror(tmp3, tmp3, 32);
4065 str(tmp3, Address(rscratch1, 0));
4066
4067 bind (L_check_1);
4068
4069 andw (idx, idx, 0x1);
4070 subsw(idx, idx, 1);
4071 br(Assembler::MI, L_post_third_loop_done);
4072 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4073 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
4074 umulh(carry2, tmp4, product_hi);
4075 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4076
4077 add2_with_carry(carry2, tmp3, tmp4, carry);
4078
4079 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4080 extr(carry, carry2, tmp3, 32);
4081
4082 bind(L_post_third_loop_done);
4083 }
4084
4085 /**
4086 * Code for BigInteger::multiplyToLen() intrinsic.
4087 *
4088 * r0: x
4089 * r1: xlen
4090 * r2: y
4091 * r3: ylen
4092 * r4: z
4093 * r5: tmp0
4094 * r10: tmp1
4095 * r11: tmp2
4096 * r12: tmp3
4097 * r13: tmp4
4098 * r14: tmp5
4099 * r15: tmp6
4100 * r16: tmp7
4101 *
4102 */
4103 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
4104 Register z, Register tmp0,
4105 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
4106 Register tmp5, Register tmp6, Register product_hi) {
4107
4108 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, product_hi);
4109
4110 const Register idx = tmp1;
4111 const Register kdx = tmp2;
4112 const Register xstart = tmp3;
4113
4114 const Register y_idx = tmp4;
4115 const Register carry = tmp5;
4116 const Register product = xlen;
4117 const Register x_xstart = tmp0;
4118
4119 // First Loop.
4120 //
4121 // final static long LONG_MASK = 0xffffffffL;
4122 // int xstart = xlen - 1;
4123 // int ystart = ylen - 1;
4124 // long carry = 0;
4125 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4126 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
4127 // z[kdx] = (int)product;
4128 // carry = product >>> 32;
4129 // }
4130 // z[xstart] = (int)carry;
4131 //
4132
4133 movw(idx, ylen); // idx = ylen;
4134 addw(kdx, xlen, ylen); // kdx = xlen+ylen;
4135 mov(carry, zr); // carry = 0;
4136
4137 Label L_done;
4138
4139 movw(xstart, xlen);
4140 subsw(xstart, xstart, 1);
4141 br(Assembler::MI, L_done);
4142
4143 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
4144
4145 Label L_second_loop;
4146 cbzw(kdx, L_second_loop);
4147
4148 Label L_carry;
4149 subw(kdx, kdx, 1);
4150 cbzw(kdx, L_carry);
4151
4152 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4153 lsr(carry, carry, 32);
4154 subw(kdx, kdx, 1);
4155
4156 bind(L_carry);
4157 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4158
4159 // Second and third (nested) loops.
4160 //
4161 // for (int i = xstart-1; i >= 0; i--) { // Second loop
4162 // carry = 0;
4163 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
4164 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
4165 // (z[k] & LONG_MASK) + carry;
4166 // z[k] = (int)product;
4167 // carry = product >>> 32;
4168 // }
4169 // z[i] = (int)carry;
4170 // }
4171 //
4172 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
4173
4174 const Register jdx = tmp1;
4175
4176 bind(L_second_loop);
4177 mov(carry, zr); // carry = 0;
4178 movw(jdx, ylen); // j = ystart+1
4179
4180 subsw(xstart, xstart, 1); // i = xstart-1;
4181 br(Assembler::MI, L_done);
4182
4183 str(z, Address(pre(sp, -4 * wordSize)));
4184
4185 Label L_last_x;
4186 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
4187 subsw(xstart, xstart, 1); // i = xstart-1;
4188 br(Assembler::MI, L_last_x);
4189
4190 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
4191 ldr(product_hi, Address(rscratch1));
4192 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
4193
4194 Label L_third_loop_prologue;
4195 bind(L_third_loop_prologue);
4196
4197 str(ylen, Address(sp, wordSize));
4198 stp(x, xstart, Address(sp, 2 * wordSize));
4199 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
4200 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
4201 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
4202 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
4203
4204 addw(tmp3, xlen, 1);
4205 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4206 subsw(tmp3, tmp3, 1);
4207 br(Assembler::MI, L_done);
4208
4209 lsr(carry, carry, 32);
4210 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4211 b(L_second_loop);
4212
4213 // Next infrequent code is moved outside loops.
4214 bind(L_last_x);
4215 ldrw(product_hi, Address(x, 0));
4216 b(L_third_loop_prologue);
4217
4218 bind(L_done);
4219 }
4220
4221 // Code for BigInteger::mulAdd intrinsic
4222 // out = r0
4223 // in = r1
4224 // offset = r2 (already out.length-offset)
4225 // len = r3
4226 // k = r4
4227 //
4228 // pseudo code from java implementation:
4229 // carry = 0;
4230 // offset = out.length-offset - 1;
4231 // for (int j=len-1; j >= 0; j--) {
4232 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
4233 // out[offset--] = (int)product;
4234 // carry = product >>> 32;
4235 // }
4236 // return (int)carry;
4237 void MacroAssembler::mul_add(Register out, Register in, Register offset,
4238 Register len, Register k) {
4239 Label LOOP, END;
4240 // pre-loop
4241 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
4242 csel(out, zr, out, Assembler::EQ);
4243 br(Assembler::EQ, END);
4244 add(in, in, len, LSL, 2); // in[j+1] address
4245 add(offset, out, offset, LSL, 2); // out[offset + 1] address
4246 mov(out, zr); // used to keep carry now
4247 BIND(LOOP);
4248 ldrw(rscratch1, Address(pre(in, -4)));
4249 madd(rscratch1, rscratch1, k, out);
4250 ldrw(rscratch2, Address(pre(offset, -4)));
4251 add(rscratch1, rscratch1, rscratch2);
4252 strw(rscratch1, Address(offset));
4253 lsr(out, rscratch1, 32);
4254 subs(len, len, 1);
4255 br(Assembler::NE, LOOP);
4256 BIND(END);
4257 }
4258
4259 /**
4260 * Emits code to update CRC-32 with a byte value according to constants in table
4261 *
4262 * @param [in,out]crc Register containing the crc.
4263 * @param [in]val Register containing the byte to fold into the CRC.
4264 * @param [in]table Register containing the table of crc constants.
4265 *
4266 * uint32_t crc;
4267 * val = crc_table[(val ^ crc) & 0xFF];
4268 * crc = val ^ (crc >> 8);
4269 *
4270 */
4271 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4272 eor(val, val, crc);
4273 andr(val, val, 0xff);
4274 ldrw(val, Address(table, val, Address::lsl(2)));
4275 eor(crc, val, crc, Assembler::LSR, 8);
4276 }
4277
4278 /**
4279 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
4280 *
4281 * @param [in,out]crc Register containing the crc.
4282 * @param [in]v Register containing the 32-bit to fold into the CRC.
4283 * @param [in]table0 Register containing table 0 of crc constants.
4284 * @param [in]table1 Register containing table 1 of crc constants.
4285 * @param [in]table2 Register containing table 2 of crc constants.
4286 * @param [in]table3 Register containing table 3 of crc constants.
4287 *
4288 * uint32_t crc;
4289 * v = crc ^ v
4290 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
4291 *
4292 */
4293 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
4294 Register table0, Register table1, Register table2, Register table3,
4295 bool upper) {
4296 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
4297 uxtb(tmp, v);
4298 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
4299 ubfx(tmp, v, 8, 8);
4300 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
4301 eor(crc, crc, tmp);
4302 ubfx(tmp, v, 16, 8);
4303 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
4304 eor(crc, crc, tmp);
4305 ubfx(tmp, v, 24, 8);
4306 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
4307 eor(crc, crc, tmp);
4308 }
4309
4310 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf,
4311 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4312 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4313 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4314
4315 subs(tmp0, len, 384);
4316 mvnw(crc, crc);
4317 br(Assembler::GE, CRC_by128_pre);
4318 BIND(CRC_less128);
4319 subs(len, len, 32);
4320 br(Assembler::GE, CRC_by32_loop);
4321 BIND(CRC_less32);
4322 adds(len, len, 32 - 4);
4323 br(Assembler::GE, CRC_by4_loop);
4324 adds(len, len, 4);
4325 br(Assembler::GT, CRC_by1_loop);
4326 b(L_exit);
4327
4328 BIND(CRC_by32_loop);
4329 ldp(tmp0, tmp1, Address(buf));
4330 crc32x(crc, crc, tmp0);
4331 ldp(tmp2, tmp3, Address(buf, 16));
4332 crc32x(crc, crc, tmp1);
4333 add(buf, buf, 32);
4334 crc32x(crc, crc, tmp2);
4335 subs(len, len, 32);
4336 crc32x(crc, crc, tmp3);
4337 br(Assembler::GE, CRC_by32_loop);
4338 cmn(len, (u1)32);
4339 br(Assembler::NE, CRC_less32);
4340 b(L_exit);
4341
4342 BIND(CRC_by4_loop);
4343 ldrw(tmp0, Address(post(buf, 4)));
4344 subs(len, len, 4);
4345 crc32w(crc, crc, tmp0);
4346 br(Assembler::GE, CRC_by4_loop);
4347 adds(len, len, 4);
4348 br(Assembler::LE, L_exit);
4349 BIND(CRC_by1_loop);
4350 ldrb(tmp0, Address(post(buf, 1)));
4351 subs(len, len, 1);
4352 crc32b(crc, crc, tmp0);
4353 br(Assembler::GT, CRC_by1_loop);
4354 b(L_exit);
4355
4356 BIND(CRC_by128_pre);
4357 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4358 4*256*sizeof(juint) + 8*sizeof(juint));
4359 mov(crc, 0);
4360 crc32x(crc, crc, tmp0);
4361 crc32x(crc, crc, tmp1);
4362
4363 cbnz(len, CRC_less128);
4364
4365 BIND(L_exit);
4366 mvnw(crc, crc);
4367 }
4368
4369 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
4370 Register len, Register tmp0, Register tmp1, Register tmp2,
4371 Register tmp3) {
4372 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4373 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4374
4375 mvnw(crc, crc);
4376
4377 subs(len, len, 128);
4378 br(Assembler::GE, CRC_by64_pre);
4379 BIND(CRC_less64);
4380 adds(len, len, 128-32);
4381 br(Assembler::GE, CRC_by32_loop);
4382 BIND(CRC_less32);
4383 adds(len, len, 32-4);
4384 br(Assembler::GE, CRC_by4_loop);
4385 adds(len, len, 4);
4386 br(Assembler::GT, CRC_by1_loop);
4387 b(L_exit);
4388
4389 BIND(CRC_by32_loop);
4390 ldp(tmp0, tmp1, Address(post(buf, 16)));
4391 subs(len, len, 32);
4392 crc32x(crc, crc, tmp0);
4393 ldr(tmp2, Address(post(buf, 8)));
4394 crc32x(crc, crc, tmp1);
4395 ldr(tmp3, Address(post(buf, 8)));
4396 crc32x(crc, crc, tmp2);
4397 crc32x(crc, crc, tmp3);
4398 br(Assembler::GE, CRC_by32_loop);
4399 cmn(len, (u1)32);
4400 br(Assembler::NE, CRC_less32);
4401 b(L_exit);
4402
4403 BIND(CRC_by4_loop);
4404 ldrw(tmp0, Address(post(buf, 4)));
4405 subs(len, len, 4);
4406 crc32w(crc, crc, tmp0);
4407 br(Assembler::GE, CRC_by4_loop);
4408 adds(len, len, 4);
4409 br(Assembler::LE, L_exit);
4410 BIND(CRC_by1_loop);
4411 ldrb(tmp0, Address(post(buf, 1)));
4412 subs(len, len, 1);
4413 crc32b(crc, crc, tmp0);
4414 br(Assembler::GT, CRC_by1_loop);
4415 b(L_exit);
4416
4417 BIND(CRC_by64_pre);
4418 sub(buf, buf, 8);
4419 ldp(tmp0, tmp1, Address(buf, 8));
4420 crc32x(crc, crc, tmp0);
4421 ldr(tmp2, Address(buf, 24));
4422 crc32x(crc, crc, tmp1);
4423 ldr(tmp3, Address(buf, 32));
4424 crc32x(crc, crc, tmp2);
4425 ldr(tmp0, Address(buf, 40));
4426 crc32x(crc, crc, tmp3);
4427 ldr(tmp1, Address(buf, 48));
4428 crc32x(crc, crc, tmp0);
4429 ldr(tmp2, Address(buf, 56));
4430 crc32x(crc, crc, tmp1);
4431 ldr(tmp3, Address(pre(buf, 64)));
4432
4433 b(CRC_by64_loop);
4434
4435 align(CodeEntryAlignment);
4436 BIND(CRC_by64_loop);
4437 subs(len, len, 64);
4438 crc32x(crc, crc, tmp2);
4439 ldr(tmp0, Address(buf, 8));
4440 crc32x(crc, crc, tmp3);
4441 ldr(tmp1, Address(buf, 16));
4442 crc32x(crc, crc, tmp0);
4443 ldr(tmp2, Address(buf, 24));
4444 crc32x(crc, crc, tmp1);
4445 ldr(tmp3, Address(buf, 32));
4446 crc32x(crc, crc, tmp2);
4447 ldr(tmp0, Address(buf, 40));
4448 crc32x(crc, crc, tmp3);
4449 ldr(tmp1, Address(buf, 48));
4450 crc32x(crc, crc, tmp0);
4451 ldr(tmp2, Address(buf, 56));
4452 crc32x(crc, crc, tmp1);
4453 ldr(tmp3, Address(pre(buf, 64)));
4454 br(Assembler::GE, CRC_by64_loop);
4455
4456 // post-loop
4457 crc32x(crc, crc, tmp2);
4458 crc32x(crc, crc, tmp3);
4459
4460 sub(len, len, 64);
4461 add(buf, buf, 8);
4462 cmn(len, (u1)128);
4463 br(Assembler::NE, CRC_less64);
4464 BIND(L_exit);
4465 mvnw(crc, crc);
4466 }
4467
4468 /**
4469 * @param crc register containing existing CRC (32-bit)
4470 * @param buf register pointing to input byte buffer (byte*)
4471 * @param len register containing number of bytes
4472 * @param table register that will contain address of CRC table
4473 * @param tmp scratch register
4474 */
4475 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
4476 Register table0, Register table1, Register table2, Register table3,
4477 Register tmp, Register tmp2, Register tmp3) {
4478 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
4479
4480 if (UseCryptoPmullForCRC32) {
4481 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4482 return;
4483 }
4484
4485 if (UseCRC32) {
4486 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
4487 return;
4488 }
4489
4490 mvnw(crc, crc);
4491
4492 {
4493 uint64_t offset;
4494 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4495 add(table0, table0, offset);
4496 }
4497 add(table1, table0, 1*256*sizeof(juint));
4498 add(table2, table0, 2*256*sizeof(juint));
4499 add(table3, table0, 3*256*sizeof(juint));
4500
4501 { // Neon code start
4502 cmp(len, (u1)64);
4503 br(Assembler::LT, L_by16);
4504 eor(v16, T16B, v16, v16);
4505
4506 Label L_fold;
4507
4508 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
4509
4510 ld1(v0, v1, T2D, post(buf, 32));
4511 ld1r(v4, T2D, post(tmp, 8));
4512 ld1r(v5, T2D, post(tmp, 8));
4513 ld1r(v6, T2D, post(tmp, 8));
4514 ld1r(v7, T2D, post(tmp, 8));
4515 mov(v16, S, 0, crc);
4516
4517 eor(v0, T16B, v0, v16);
4518 sub(len, len, 64);
4519
4520 BIND(L_fold);
4521 pmull(v22, T8H, v0, v5, T8B);
4522 pmull(v20, T8H, v0, v7, T8B);
4523 pmull(v23, T8H, v0, v4, T8B);
4524 pmull(v21, T8H, v0, v6, T8B);
4525
4526 pmull2(v18, T8H, v0, v5, T16B);
4527 pmull2(v16, T8H, v0, v7, T16B);
4528 pmull2(v19, T8H, v0, v4, T16B);
4529 pmull2(v17, T8H, v0, v6, T16B);
4530
4531 uzp1(v24, T8H, v20, v22);
4532 uzp2(v25, T8H, v20, v22);
4533 eor(v20, T16B, v24, v25);
4534
4535 uzp1(v26, T8H, v16, v18);
4536 uzp2(v27, T8H, v16, v18);
4537 eor(v16, T16B, v26, v27);
4538
4539 ushll2(v22, T4S, v20, T8H, 8);
4540 ushll(v20, T4S, v20, T4H, 8);
4541
4542 ushll2(v18, T4S, v16, T8H, 8);
4543 ushll(v16, T4S, v16, T4H, 8);
4544
4545 eor(v22, T16B, v23, v22);
4546 eor(v18, T16B, v19, v18);
4547 eor(v20, T16B, v21, v20);
4548 eor(v16, T16B, v17, v16);
4549
4550 uzp1(v17, T2D, v16, v20);
4551 uzp2(v21, T2D, v16, v20);
4552 eor(v17, T16B, v17, v21);
4553
4554 ushll2(v20, T2D, v17, T4S, 16);
4555 ushll(v16, T2D, v17, T2S, 16);
4556
4557 eor(v20, T16B, v20, v22);
4558 eor(v16, T16B, v16, v18);
4559
4560 uzp1(v17, T2D, v20, v16);
4561 uzp2(v21, T2D, v20, v16);
4562 eor(v28, T16B, v17, v21);
4563
4564 pmull(v22, T8H, v1, v5, T8B);
4565 pmull(v20, T8H, v1, v7, T8B);
4566 pmull(v23, T8H, v1, v4, T8B);
4567 pmull(v21, T8H, v1, v6, T8B);
4568
4569 pmull2(v18, T8H, v1, v5, T16B);
4570 pmull2(v16, T8H, v1, v7, T16B);
4571 pmull2(v19, T8H, v1, v4, T16B);
4572 pmull2(v17, T8H, v1, v6, T16B);
4573
4574 ld1(v0, v1, T2D, post(buf, 32));
4575
4576 uzp1(v24, T8H, v20, v22);
4577 uzp2(v25, T8H, v20, v22);
4578 eor(v20, T16B, v24, v25);
4579
4580 uzp1(v26, T8H, v16, v18);
4581 uzp2(v27, T8H, v16, v18);
4582 eor(v16, T16B, v26, v27);
4583
4584 ushll2(v22, T4S, v20, T8H, 8);
4585 ushll(v20, T4S, v20, T4H, 8);
4586
4587 ushll2(v18, T4S, v16, T8H, 8);
4588 ushll(v16, T4S, v16, T4H, 8);
4589
4590 eor(v22, T16B, v23, v22);
4591 eor(v18, T16B, v19, v18);
4592 eor(v20, T16B, v21, v20);
4593 eor(v16, T16B, v17, v16);
4594
4595 uzp1(v17, T2D, v16, v20);
4596 uzp2(v21, T2D, v16, v20);
4597 eor(v16, T16B, v17, v21);
4598
4599 ushll2(v20, T2D, v16, T4S, 16);
4600 ushll(v16, T2D, v16, T2S, 16);
4601
4602 eor(v20, T16B, v22, v20);
4603 eor(v16, T16B, v16, v18);
4604
4605 uzp1(v17, T2D, v20, v16);
4606 uzp2(v21, T2D, v20, v16);
4607 eor(v20, T16B, v17, v21);
4608
4609 shl(v16, T2D, v28, 1);
4610 shl(v17, T2D, v20, 1);
4611
4612 eor(v0, T16B, v0, v16);
4613 eor(v1, T16B, v1, v17);
4614
4615 subs(len, len, 32);
4616 br(Assembler::GE, L_fold);
4617
4618 mov(crc, 0);
4619 mov(tmp, v0, D, 0);
4620 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4621 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4622 mov(tmp, v0, D, 1);
4623 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4624 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4625 mov(tmp, v1, D, 0);
4626 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4627 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4628 mov(tmp, v1, D, 1);
4629 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4630 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4631
4632 add(len, len, 32);
4633 } // Neon code end
4634
4635 BIND(L_by16);
4636 subs(len, len, 16);
4637 br(Assembler::GE, L_by16_loop);
4638 adds(len, len, 16-4);
4639 br(Assembler::GE, L_by4_loop);
4640 adds(len, len, 4);
4641 br(Assembler::GT, L_by1_loop);
4642 b(L_exit);
4643
4644 BIND(L_by4_loop);
4645 ldrw(tmp, Address(post(buf, 4)));
4646 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
4647 subs(len, len, 4);
4648 br(Assembler::GE, L_by4_loop);
4649 adds(len, len, 4);
4650 br(Assembler::LE, L_exit);
4651 BIND(L_by1_loop);
4652 subs(len, len, 1);
4653 ldrb(tmp, Address(post(buf, 1)));
4654 update_byte_crc32(crc, tmp, table0);
4655 br(Assembler::GT, L_by1_loop);
4656 b(L_exit);
4657
4658 align(CodeEntryAlignment);
4659 BIND(L_by16_loop);
4660 subs(len, len, 16);
4661 ldp(tmp, tmp3, Address(post(buf, 16)));
4662 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4663 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4664 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
4665 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
4666 br(Assembler::GE, L_by16_loop);
4667 adds(len, len, 16-4);
4668 br(Assembler::GE, L_by4_loop);
4669 adds(len, len, 4);
4670 br(Assembler::GT, L_by1_loop);
4671 BIND(L_exit);
4672 mvnw(crc, crc);
4673 }
4674
4675 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
4676 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4677 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4678 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4679
4680 subs(tmp0, len, 384);
4681 br(Assembler::GE, CRC_by128_pre);
4682 BIND(CRC_less128);
4683 subs(len, len, 32);
4684 br(Assembler::GE, CRC_by32_loop);
4685 BIND(CRC_less32);
4686 adds(len, len, 32 - 4);
4687 br(Assembler::GE, CRC_by4_loop);
4688 adds(len, len, 4);
4689 br(Assembler::GT, CRC_by1_loop);
4690 b(L_exit);
4691
4692 BIND(CRC_by32_loop);
4693 ldp(tmp0, tmp1, Address(buf));
4694 crc32cx(crc, crc, tmp0);
4695 ldr(tmp2, Address(buf, 16));
4696 crc32cx(crc, crc, tmp1);
4697 ldr(tmp3, Address(buf, 24));
4698 crc32cx(crc, crc, tmp2);
4699 add(buf, buf, 32);
4700 subs(len, len, 32);
4701 crc32cx(crc, crc, tmp3);
4702 br(Assembler::GE, CRC_by32_loop);
4703 cmn(len, (u1)32);
4704 br(Assembler::NE, CRC_less32);
4705 b(L_exit);
4706
4707 BIND(CRC_by4_loop);
4708 ldrw(tmp0, Address(post(buf, 4)));
4709 subs(len, len, 4);
4710 crc32cw(crc, crc, tmp0);
4711 br(Assembler::GE, CRC_by4_loop);
4712 adds(len, len, 4);
4713 br(Assembler::LE, L_exit);
4714 BIND(CRC_by1_loop);
4715 ldrb(tmp0, Address(post(buf, 1)));
4716 subs(len, len, 1);
4717 crc32cb(crc, crc, tmp0);
4718 br(Assembler::GT, CRC_by1_loop);
4719 b(L_exit);
4720
4721 BIND(CRC_by128_pre);
4722 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4723 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50);
4724 mov(crc, 0);
4725 crc32cx(crc, crc, tmp0);
4726 crc32cx(crc, crc, tmp1);
4727
4728 cbnz(len, CRC_less128);
4729
4730 BIND(L_exit);
4731 }
4732
4733 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
4734 Register len, Register tmp0, Register tmp1, Register tmp2,
4735 Register tmp3) {
4736 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4737 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4738
4739 subs(len, len, 128);
4740 br(Assembler::GE, CRC_by64_pre);
4741 BIND(CRC_less64);
4742 adds(len, len, 128-32);
4743 br(Assembler::GE, CRC_by32_loop);
4744 BIND(CRC_less32);
4745 adds(len, len, 32-4);
4746 br(Assembler::GE, CRC_by4_loop);
4747 adds(len, len, 4);
4748 br(Assembler::GT, CRC_by1_loop);
4749 b(L_exit);
4750
4751 BIND(CRC_by32_loop);
4752 ldp(tmp0, tmp1, Address(post(buf, 16)));
4753 subs(len, len, 32);
4754 crc32cx(crc, crc, tmp0);
4755 ldr(tmp2, Address(post(buf, 8)));
4756 crc32cx(crc, crc, tmp1);
4757 ldr(tmp3, Address(post(buf, 8)));
4758 crc32cx(crc, crc, tmp2);
4759 crc32cx(crc, crc, tmp3);
4760 br(Assembler::GE, CRC_by32_loop);
4761 cmn(len, (u1)32);
4762 br(Assembler::NE, CRC_less32);
4763 b(L_exit);
4764
4765 BIND(CRC_by4_loop);
4766 ldrw(tmp0, Address(post(buf, 4)));
4767 subs(len, len, 4);
4768 crc32cw(crc, crc, tmp0);
4769 br(Assembler::GE, CRC_by4_loop);
4770 adds(len, len, 4);
4771 br(Assembler::LE, L_exit);
4772 BIND(CRC_by1_loop);
4773 ldrb(tmp0, Address(post(buf, 1)));
4774 subs(len, len, 1);
4775 crc32cb(crc, crc, tmp0);
4776 br(Assembler::GT, CRC_by1_loop);
4777 b(L_exit);
4778
4779 BIND(CRC_by64_pre);
4780 sub(buf, buf, 8);
4781 ldp(tmp0, tmp1, Address(buf, 8));
4782 crc32cx(crc, crc, tmp0);
4783 ldr(tmp2, Address(buf, 24));
4784 crc32cx(crc, crc, tmp1);
4785 ldr(tmp3, Address(buf, 32));
4786 crc32cx(crc, crc, tmp2);
4787 ldr(tmp0, Address(buf, 40));
4788 crc32cx(crc, crc, tmp3);
4789 ldr(tmp1, Address(buf, 48));
4790 crc32cx(crc, crc, tmp0);
4791 ldr(tmp2, Address(buf, 56));
4792 crc32cx(crc, crc, tmp1);
4793 ldr(tmp3, Address(pre(buf, 64)));
4794
4795 b(CRC_by64_loop);
4796
4797 align(CodeEntryAlignment);
4798 BIND(CRC_by64_loop);
4799 subs(len, len, 64);
4800 crc32cx(crc, crc, tmp2);
4801 ldr(tmp0, Address(buf, 8));
4802 crc32cx(crc, crc, tmp3);
4803 ldr(tmp1, Address(buf, 16));
4804 crc32cx(crc, crc, tmp0);
4805 ldr(tmp2, Address(buf, 24));
4806 crc32cx(crc, crc, tmp1);
4807 ldr(tmp3, Address(buf, 32));
4808 crc32cx(crc, crc, tmp2);
4809 ldr(tmp0, Address(buf, 40));
4810 crc32cx(crc, crc, tmp3);
4811 ldr(tmp1, Address(buf, 48));
4812 crc32cx(crc, crc, tmp0);
4813 ldr(tmp2, Address(buf, 56));
4814 crc32cx(crc, crc, tmp1);
4815 ldr(tmp3, Address(pre(buf, 64)));
4816 br(Assembler::GE, CRC_by64_loop);
4817
4818 // post-loop
4819 crc32cx(crc, crc, tmp2);
4820 crc32cx(crc, crc, tmp3);
4821
4822 sub(len, len, 64);
4823 add(buf, buf, 8);
4824 cmn(len, (u1)128);
4825 br(Assembler::NE, CRC_less64);
4826 BIND(L_exit);
4827 }
4828
4829 /**
4830 * @param crc register containing existing CRC (32-bit)
4831 * @param buf register pointing to input byte buffer (byte*)
4832 * @param len register containing number of bytes
4833 * @param table register that will contain address of CRC table
4834 * @param tmp scratch register
4835 */
4836 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
4837 Register table0, Register table1, Register table2, Register table3,
4838 Register tmp, Register tmp2, Register tmp3) {
4839 if (UseCryptoPmullForCRC32) {
4840 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4841 } else {
4842 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
4843 }
4844 }
4845
4846 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
4847 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) {
4848 Label CRC_by128_loop;
4849 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4850
4851 sub(len, len, 256);
4852 Register table = tmp0;
4853 {
4854 uint64_t offset;
4855 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4856 add(table, table, offset);
4857 }
4858 add(table, table, table_offset);
4859
4860 // Registers v0..v7 are used as data registers.
4861 // Registers v16..v31 are used as tmp registers.
4862 sub(buf, buf, 0x10);
4863 ldrq(v0, Address(buf, 0x10));
4864 ldrq(v1, Address(buf, 0x20));
4865 ldrq(v2, Address(buf, 0x30));
4866 ldrq(v3, Address(buf, 0x40));
4867 ldrq(v4, Address(buf, 0x50));
4868 ldrq(v5, Address(buf, 0x60));
4869 ldrq(v6, Address(buf, 0x70));
4870 ldrq(v7, Address(pre(buf, 0x80)));
4871
4872 movi(v31, T4S, 0);
4873 mov(v31, S, 0, crc);
4874 eor(v0, T16B, v0, v31);
4875
4876 // Register v16 contains constants from the crc table.
4877 ldrq(v16, Address(table));
4878 b(CRC_by128_loop);
4879
4880 align(OptoLoopAlignment);
4881 BIND(CRC_by128_loop);
4882 pmull (v17, T1Q, v0, v16, T1D);
4883 pmull2(v18, T1Q, v0, v16, T2D);
4884 ldrq(v0, Address(buf, 0x10));
4885 eor3(v0, T16B, v17, v18, v0);
4886
4887 pmull (v19, T1Q, v1, v16, T1D);
4888 pmull2(v20, T1Q, v1, v16, T2D);
4889 ldrq(v1, Address(buf, 0x20));
4890 eor3(v1, T16B, v19, v20, v1);
4891
4892 pmull (v21, T1Q, v2, v16, T1D);
4893 pmull2(v22, T1Q, v2, v16, T2D);
4894 ldrq(v2, Address(buf, 0x30));
4895 eor3(v2, T16B, v21, v22, v2);
4896
4897 pmull (v23, T1Q, v3, v16, T1D);
4898 pmull2(v24, T1Q, v3, v16, T2D);
4899 ldrq(v3, Address(buf, 0x40));
4900 eor3(v3, T16B, v23, v24, v3);
4901
4902 pmull (v25, T1Q, v4, v16, T1D);
4903 pmull2(v26, T1Q, v4, v16, T2D);
4904 ldrq(v4, Address(buf, 0x50));
4905 eor3(v4, T16B, v25, v26, v4);
4906
4907 pmull (v27, T1Q, v5, v16, T1D);
4908 pmull2(v28, T1Q, v5, v16, T2D);
4909 ldrq(v5, Address(buf, 0x60));
4910 eor3(v5, T16B, v27, v28, v5);
4911
4912 pmull (v29, T1Q, v6, v16, T1D);
4913 pmull2(v30, T1Q, v6, v16, T2D);
4914 ldrq(v6, Address(buf, 0x70));
4915 eor3(v6, T16B, v29, v30, v6);
4916
4917 // Reuse registers v23, v24.
4918 // Using them won't block the first instruction of the next iteration.
4919 pmull (v23, T1Q, v7, v16, T1D);
4920 pmull2(v24, T1Q, v7, v16, T2D);
4921 ldrq(v7, Address(pre(buf, 0x80)));
4922 eor3(v7, T16B, v23, v24, v7);
4923
4924 subs(len, len, 0x80);
4925 br(Assembler::GE, CRC_by128_loop);
4926
4927 // fold into 512 bits
4928 // Use v31 for constants because v16 can be still in use.
4929 ldrq(v31, Address(table, 0x10));
4930
4931 pmull (v17, T1Q, v0, v31, T1D);
4932 pmull2(v18, T1Q, v0, v31, T2D);
4933 eor3(v0, T16B, v17, v18, v4);
4934
4935 pmull (v19, T1Q, v1, v31, T1D);
4936 pmull2(v20, T1Q, v1, v31, T2D);
4937 eor3(v1, T16B, v19, v20, v5);
4938
4939 pmull (v21, T1Q, v2, v31, T1D);
4940 pmull2(v22, T1Q, v2, v31, T2D);
4941 eor3(v2, T16B, v21, v22, v6);
4942
4943 pmull (v23, T1Q, v3, v31, T1D);
4944 pmull2(v24, T1Q, v3, v31, T2D);
4945 eor3(v3, T16B, v23, v24, v7);
4946
4947 // fold into 128 bits
4948 // Use v17 for constants because v31 can be still in use.
4949 ldrq(v17, Address(table, 0x20));
4950 pmull (v25, T1Q, v0, v17, T1D);
4951 pmull2(v26, T1Q, v0, v17, T2D);
4952 eor3(v3, T16B, v3, v25, v26);
4953
4954 // Use v18 for constants because v17 can be still in use.
4955 ldrq(v18, Address(table, 0x30));
4956 pmull (v27, T1Q, v1, v18, T1D);
4957 pmull2(v28, T1Q, v1, v18, T2D);
4958 eor3(v3, T16B, v3, v27, v28);
4959
4960 // Use v19 for constants because v18 can be still in use.
4961 ldrq(v19, Address(table, 0x40));
4962 pmull (v29, T1Q, v2, v19, T1D);
4963 pmull2(v30, T1Q, v2, v19, T2D);
4964 eor3(v0, T16B, v3, v29, v30);
4965
4966 add(len, len, 0x80);
4967 add(buf, buf, 0x10);
4968
4969 mov(tmp0, v0, D, 0);
4970 mov(tmp1, v0, D, 1);
4971 }
4972
4973 void MacroAssembler::addptr(const Address &dst, int32_t src) {
4974 Address adr;
4975 switch(dst.getMode()) {
4976 case Address::base_plus_offset:
4977 // This is the expected mode, although we allow all the other
4978 // forms below.
4979 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
4980 break;
4981 default:
4982 lea(rscratch2, dst);
4983 adr = Address(rscratch2);
4984 break;
4985 }
4986 ldr(rscratch1, adr);
4987 add(rscratch1, rscratch1, src);
4988 str(rscratch1, adr);
4989 }
4990
4991 void MacroAssembler::cmpptr(Register src1, Address src2) {
4992 uint64_t offset;
4993 adrp(rscratch1, src2, offset);
4994 ldr(rscratch1, Address(rscratch1, offset));
4995 cmp(src1, rscratch1);
4996 }
4997
4998 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4999 cmp(obj1, obj2);
5000 }
5001
5002 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5003 load_method_holder(rresult, rmethod);
5004 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5005 }
5006
5007 void MacroAssembler::load_method_holder(Register holder, Register method) {
5008 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
5009 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5010 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5011 }
5012
5013 void MacroAssembler::load_metadata(Register dst, Register src) {
5014 if (UseCompactObjectHeaders) {
5015 load_narrow_klass_compact(dst, src);
5016 } else if (UseCompressedClassPointers) {
5017 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5018 } else {
5019 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5020 }
5021 }
5022
5023 // Loads the obj's Klass* into dst.
5024 // Preserves all registers (incl src, rscratch1 and rscratch2).
5025 // Input:
5026 // src - the oop we want to load the klass from.
5027 // dst - output narrow klass.
5028 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5029 assert(UseCompactObjectHeaders, "expects UseCompactObjectHeaders");
5030 ldr(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5031 lsr(dst, dst, markWord::klass_shift);
5032 }
5033
5034 void MacroAssembler::load_klass(Register dst, Register src) {
5035 if (UseCompactObjectHeaders) {
5036 load_narrow_klass_compact(dst, src);
5037 decode_klass_not_null(dst);
5038 } else if (UseCompressedClassPointers) {
5039 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5040 decode_klass_not_null(dst);
5041 } else {
5042 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5043 }
5044 }
5045
5046 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5047 if (RestoreMXCSROnJNICalls) {
5048 Label OK;
5049 get_fpcr(tmp1);
5050 mov(tmp2, tmp1);
5051 // Set FPCR to the state we need. We do want Round to Nearest. We
5052 // don't want non-IEEE rounding modes or floating-point traps.
5053 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5054 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5055 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5056 eor(tmp2, tmp1, tmp2);
5057 cbz(tmp2, OK); // Only reset FPCR if it's wrong
5058 set_fpcr(tmp1);
5059 bind(OK);
5060 }
5061 }
5062
5063 // ((OopHandle)result).resolve();
5064 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
5065 // OopHandle::resolve is an indirection.
5066 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
5067 }
5068
5069 // ((WeakHandle)result).resolve();
5070 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
5071 assert_different_registers(result, tmp1, tmp2);
5072 Label resolved;
5073
5074 // A null weak handle resolves to null.
5075 cbz(result, resolved);
5076
5077 // Only 64 bit platforms support GCs that require a tmp register
5078 // WeakHandle::resolve is an indirection like jweak.
5079 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5080 result, Address(result), tmp1, tmp2);
5081 bind(resolved);
5082 }
5083
5084 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) {
5085 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5086 ldr(dst, Address(rmethod, Method::const_offset()));
5087 ldr(dst, Address(dst, ConstMethod::constants_offset()));
5088 ldr(dst, Address(dst, ConstantPool::pool_holder_offset()));
5089 ldr(dst, Address(dst, mirror_offset));
5090 resolve_oop_handle(dst, tmp1, tmp2);
5091 }
5092
5093 void MacroAssembler::cmp_klass(Register obj, Register klass, Register tmp) {
5094 assert_different_registers(obj, klass, tmp);
5095 if (UseCompressedClassPointers) {
5096 if (UseCompactObjectHeaders) {
5097 load_narrow_klass_compact(tmp, obj);
5098 } else {
5099 ldrw(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5100 }
5101 if (CompressedKlassPointers::base() == nullptr) {
5102 cmp(klass, tmp, LSL, CompressedKlassPointers::shift());
5103 return;
5104 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5105 && CompressedKlassPointers::shift() == 0) {
5106 // Only the bottom 32 bits matter
5107 cmpw(klass, tmp);
5108 return;
5109 }
5110 decode_klass_not_null(tmp);
5111 } else {
5112 ldr(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5113 }
5114 cmp(klass, tmp);
5115 }
5116
5117 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5118 if (UseCompactObjectHeaders) {
5119 load_narrow_klass_compact(tmp1, obj1);
5120 load_narrow_klass_compact(tmp2, obj2);
5121 cmpw(tmp1, tmp2);
5122 } else if (UseCompressedClassPointers) {
5123 ldrw(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5124 ldrw(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5125 cmpw(tmp1, tmp2);
5126 } else {
5127 ldr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5128 ldr(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5129 cmp(tmp1, tmp2);
5130 }
5131 }
5132
5133 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5134 load_klass(dst, src);
5135 ldr(dst, Address(dst, Klass::prototype_header_offset()));
5136 }
5137
5138 void MacroAssembler::store_klass(Register dst, Register src) {
5139 // FIXME: Should this be a store release? concurrent gcs assumes
5140 // klass length is valid if klass field is not null.
5141 assert(!UseCompactObjectHeaders, "not with compact headers");
5142 if (UseCompressedClassPointers) {
5143 encode_klass_not_null(src);
5144 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5145 } else {
5146 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5147 }
5148 }
5149
5150 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5151 assert(!UseCompactObjectHeaders, "not with compact headers");
5152 if (UseCompressedClassPointers) {
5153 // Store to klass gap in destination
5154 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5155 }
5156 }
5157
5158 // Algorithm must match CompressedOops::encode.
5159 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5160 #ifdef ASSERT
5161 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5162 #endif
5163 verify_oop_msg(s, "broken oop in encode_heap_oop");
5164 if (CompressedOops::base() == nullptr) {
5165 if (CompressedOops::shift() != 0) {
5166 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5167 lsr(d, s, LogMinObjAlignmentInBytes);
5168 } else {
5169 mov(d, s);
5170 }
5171 } else {
5172 subs(d, s, rheapbase);
5173 csel(d, d, zr, Assembler::HS);
5174 lsr(d, d, LogMinObjAlignmentInBytes);
5175
5176 /* Old algorithm: is this any worse?
5177 Label nonnull;
5178 cbnz(r, nonnull);
5179 sub(r, r, rheapbase);
5180 bind(nonnull);
5181 lsr(r, r, LogMinObjAlignmentInBytes);
5182 */
5183 }
5184 }
5185
5186 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5187 #ifdef ASSERT
5188 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5189 if (CheckCompressedOops) {
5190 Label ok;
5191 cbnz(r, ok);
5192 stop("null oop passed to encode_heap_oop_not_null");
5193 bind(ok);
5194 }
5195 #endif
5196 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5197 if (CompressedOops::base() != nullptr) {
5198 sub(r, r, rheapbase);
5199 }
5200 if (CompressedOops::shift() != 0) {
5201 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5202 lsr(r, r, LogMinObjAlignmentInBytes);
5203 }
5204 }
5205
5206 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5207 #ifdef ASSERT
5208 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5209 if (CheckCompressedOops) {
5210 Label ok;
5211 cbnz(src, ok);
5212 stop("null oop passed to encode_heap_oop_not_null2");
5213 bind(ok);
5214 }
5215 #endif
5216 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5217
5218 Register data = src;
5219 if (CompressedOops::base() != nullptr) {
5220 sub(dst, src, rheapbase);
5221 data = dst;
5222 }
5223 if (CompressedOops::shift() != 0) {
5224 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5225 lsr(dst, data, LogMinObjAlignmentInBytes);
5226 data = dst;
5227 }
5228 if (data == src)
5229 mov(dst, src);
5230 }
5231
5232 void MacroAssembler::decode_heap_oop(Register d, Register s) {
5233 #ifdef ASSERT
5234 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5235 #endif
5236 if (CompressedOops::base() == nullptr) {
5237 if (CompressedOops::shift() != 0) {
5238 lsl(d, s, CompressedOops::shift());
5239 } else if (d != s) {
5240 mov(d, s);
5241 }
5242 } else {
5243 Label done;
5244 if (d != s)
5245 mov(d, s);
5246 cbz(s, done);
5247 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
5248 bind(done);
5249 }
5250 verify_oop_msg(d, "broken oop in decode_heap_oop");
5251 }
5252
5253 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5254 assert (UseCompressedOops, "should only be used for compressed headers");
5255 assert (Universe::heap() != nullptr, "java heap should be initialized");
5256 // Cannot assert, unverified entry point counts instructions (see .ad file)
5257 // vtableStubs also counts instructions in pd_code_size_limit.
5258 // Also do not verify_oop as this is called by verify_oop.
5259 if (CompressedOops::shift() != 0) {
5260 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5261 if (CompressedOops::base() != nullptr) {
5262 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5263 } else {
5264 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5265 }
5266 } else {
5267 assert (CompressedOops::base() == nullptr, "sanity");
5268 }
5269 }
5270
5271 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5272 assert (UseCompressedOops, "should only be used for compressed headers");
5273 assert (Universe::heap() != nullptr, "java heap should be initialized");
5274 // Cannot assert, unverified entry point counts instructions (see .ad file)
5275 // vtableStubs also counts instructions in pd_code_size_limit.
5276 // Also do not verify_oop as this is called by verify_oop.
5277 if (CompressedOops::shift() != 0) {
5278 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5279 if (CompressedOops::base() != nullptr) {
5280 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5281 } else {
5282 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5283 }
5284 } else {
5285 assert (CompressedOops::base() == nullptr, "sanity");
5286 if (dst != src) {
5287 mov(dst, src);
5288 }
5289 }
5290 }
5291
5292 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone);
5293
5294 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
5295 assert(Metaspace::initialized(), "metaspace not initialized yet");
5296 assert(_klass_decode_mode != KlassDecodeNone, "should be initialized");
5297 return _klass_decode_mode;
5298 }
5299
5300 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode(address base, int shift, const size_t range) {
5301 assert(UseCompressedClassPointers, "not using compressed class pointers");
5302
5303 // KlassDecodeMode shouldn't be set already.
5304 assert(_klass_decode_mode == KlassDecodeNone, "set once");
5305
5306 if (base == nullptr) {
5307 return KlassDecodeZero;
5308 }
5309
5310 if (operand_valid_for_logical_immediate(
5311 /*is32*/false, (uint64_t)base)) {
5312 const uint64_t range_mask = right_n_bits(log2i_ceil(range));
5313 if (((uint64_t)base & range_mask) == 0) {
5314 return KlassDecodeXor;
5315 }
5316 }
5317
5318 const uint64_t shifted_base =
5319 (uint64_t)base >> shift;
5320 if ((shifted_base & 0xffff0000ffffffff) == 0) {
5321 return KlassDecodeMovk;
5322 }
5323
5324 // No valid encoding.
5325 return KlassDecodeNone;
5326 }
5327
5328 // Check if one of the above decoding modes will work for given base, shift and range.
5329 bool MacroAssembler::check_klass_decode_mode(address base, int shift, const size_t range) {
5330 return klass_decode_mode(base, shift, range) != KlassDecodeNone;
5331 }
5332
5333 bool MacroAssembler::set_klass_decode_mode(address base, int shift, const size_t range) {
5334 _klass_decode_mode = klass_decode_mode(base, shift, range);
5335 return _klass_decode_mode != KlassDecodeNone;
5336 }
5337
5338 static Register pick_different_tmp(Register dst, Register src) {
5339 auto tmps = RegSet::of(r0, r1, r2) - RegSet::of(src, dst);
5340 return *tmps.begin();
5341 }
5342
5343 void MacroAssembler::encode_klass_not_null_for_aot(Register dst, Register src) {
5344 // we have to load the klass base from the AOT constants area but
5345 // not the shift because it is not allowed to change
5346 int shift = CompressedKlassPointers::shift();
5347 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5348 if (dst != src) {
5349 // we can load the base into dst, subtract it formthe src and shift down
5350 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5351 ldr(dst, dst);
5352 sub(dst, src, dst);
5353 lsr(dst, dst, shift);
5354 } else {
5355 // we need an extra register in order to load the coop base
5356 Register tmp = pick_different_tmp(dst, src);
5357 RegSet regs = RegSet::of(tmp);
5358 push(regs, sp);
5359 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5360 ldr(tmp, tmp);
5361 sub(dst, src, tmp);
5362 lsr(dst, dst, shift);
5363 pop(regs, sp);
5364 }
5365 }
5366
5367 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5368 if (AOTCodeCache::is_on_for_dump()) {
5369 encode_klass_not_null_for_aot(dst, src);
5370 return;
5371 }
5372
5373 switch (klass_decode_mode()) {
5374 case KlassDecodeZero:
5375 if (CompressedKlassPointers::shift() != 0) {
5376 lsr(dst, src, CompressedKlassPointers::shift());
5377 } else {
5378 if (dst != src) mov(dst, src);
5379 }
5380 break;
5381
5382 case KlassDecodeXor:
5383 if (CompressedKlassPointers::shift() != 0) {
5384 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5385 lsr(dst, dst, CompressedKlassPointers::shift());
5386 } else {
5387 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5388 }
5389 break;
5390
5391 case KlassDecodeMovk:
5392 if (CompressedKlassPointers::shift() != 0) {
5393 ubfx(dst, src, CompressedKlassPointers::shift(), 32);
5394 } else {
5395 movw(dst, src);
5396 }
5397 break;
5398
5399 case KlassDecodeNone:
5400 ShouldNotReachHere();
5401 break;
5402 }
5403 }
5404
5405 void MacroAssembler::encode_klass_not_null(Register r) {
5406 encode_klass_not_null(r, r);
5407 }
5408
5409 void MacroAssembler::decode_klass_not_null_for_aot(Register dst, Register src) {
5410 // we have to load the klass base from the AOT constants area but
5411 // not the shift because it is not allowed to change
5412 int shift = CompressedKlassPointers::shift();
5413 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5414 if (dst != src) {
5415 // we can load the base into dst then add the offset with a suitable shift
5416 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5417 ldr(dst, dst);
5418 add(dst, dst, src, LSL, shift);
5419 } else {
5420 // we need an extra register in order to load the coop base
5421 Register tmp = pick_different_tmp(dst, src);
5422 RegSet regs = RegSet::of(tmp);
5423 push(regs, sp);
5424 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5425 ldr(tmp, tmp);
5426 add(dst, tmp, src, LSL, shift);
5427 pop(regs, sp);
5428 }
5429 }
5430
5431 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5432 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5433
5434 if (AOTCodeCache::is_on_for_dump()) {
5435 decode_klass_not_null_for_aot(dst, src);
5436 return;
5437 }
5438
5439 switch (klass_decode_mode()) {
5440 case KlassDecodeZero:
5441 if (CompressedKlassPointers::shift() != 0) {
5442 lsl(dst, src, CompressedKlassPointers::shift());
5443 } else {
5444 if (dst != src) mov(dst, src);
5445 }
5446 break;
5447
5448 case KlassDecodeXor:
5449 if (CompressedKlassPointers::shift() != 0) {
5450 lsl(dst, src, CompressedKlassPointers::shift());
5451 eor(dst, dst, (uint64_t)CompressedKlassPointers::base());
5452 } else {
5453 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5454 }
5455 break;
5456
5457 case KlassDecodeMovk: {
5458 const uint64_t shifted_base =
5459 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5460
5461 if (dst != src) movw(dst, src);
5462 movk(dst, shifted_base >> 32, 32);
5463
5464 if (CompressedKlassPointers::shift() != 0) {
5465 lsl(dst, dst, CompressedKlassPointers::shift());
5466 }
5467
5468 break;
5469 }
5470
5471 case KlassDecodeNone:
5472 ShouldNotReachHere();
5473 break;
5474 }
5475 }
5476
5477 void MacroAssembler::decode_klass_not_null(Register r) {
5478 decode_klass_not_null(r, r);
5479 }
5480
5481 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5482 #ifdef ASSERT
5483 {
5484 ThreadInVMfromUnknown tiv;
5485 assert (UseCompressedOops, "should only be used for compressed oops");
5486 assert (Universe::heap() != nullptr, "java heap should be initialized");
5487 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5488 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5489 }
5490 #endif
5491 int oop_index = oop_recorder()->find_index(obj);
5492 InstructionMark im(this);
5493 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5494 code_section()->relocate(inst_mark(), rspec);
5495 movz(dst, 0xDEAD, 16);
5496 movk(dst, 0xBEEF);
5497 }
5498
5499 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5500 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5501 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5502 int index = oop_recorder()->find_index(k);
5503
5504 InstructionMark im(this);
5505 RelocationHolder rspec = metadata_Relocation::spec(index);
5506 code_section()->relocate(inst_mark(), rspec);
5507 narrowKlass nk = CompressedKlassPointers::encode(k);
5508 movz(dst, (nk >> 16), 16);
5509 movk(dst, nk & 0xffff);
5510 }
5511
5512 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
5513 Register dst, Address src,
5514 Register tmp1, Register tmp2) {
5515 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5516 decorators = AccessInternal::decorator_fixup(decorators, type);
5517 bool as_raw = (decorators & AS_RAW) != 0;
5518 if (as_raw) {
5519 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5520 } else {
5521 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5522 }
5523 }
5524
5525 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5526 Address dst, Register val,
5527 Register tmp1, Register tmp2, Register tmp3) {
5528 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5529 decorators = AccessInternal::decorator_fixup(decorators, type);
5530 bool as_raw = (decorators & AS_RAW) != 0;
5531 if (as_raw) {
5532 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5533 } else {
5534 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5535 }
5536 }
5537
5538 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
5539 Register inline_layout_info) {
5540 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5541 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
5542 }
5543
5544 void MacroAssembler::payload_offset(Register inline_klass, Register offset) {
5545 ldr(offset, Address(inline_klass, InlineKlass::adr_members_offset()));
5546 ldrw(offset, Address(offset, InlineKlass::payload_offset_offset()));
5547 }
5548
5549 void MacroAssembler::payload_address(Register oop, Register data, Register inline_klass) {
5550 // ((address) (void*) o) + vk->payload_offset();
5551 Register offset = (data == oop) ? rscratch1 : data;
5552 payload_offset(inline_klass, offset);
5553 if (data == oop) {
5554 add(data, data, offset);
5555 } else {
5556 lea(data, Address(oop, offset));
5557 }
5558 }
5559
5560 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
5561 Register index, Register data) {
5562 assert_different_registers(array, array_klass, index);
5563 assert_different_registers(rscratch1, array, index);
5564
5565 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
5566 ldrw(rscratch1, Address(array_klass, Klass::layout_helper_offset()));
5567
5568 // Klass::layout_helper_log2_element_size(lh)
5569 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
5570 lsr(rscratch1, rscratch1, Klass::_lh_log2_element_size_shift);
5571 andr(rscratch1, rscratch1, Klass::_lh_log2_element_size_mask);
5572 lslv(index, index, rscratch1);
5573
5574 add(data, array, index);
5575 add(data, data, arrayOopDesc::base_offset_in_bytes(T_FLAT_ELEMENT));
5576 }
5577
5578 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5579 Register tmp2, DecoratorSet decorators) {
5580 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5581 }
5582
5583 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5584 Register tmp2, DecoratorSet decorators) {
5585 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5586 }
5587
5588 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5589 Register tmp2, Register tmp3, DecoratorSet decorators) {
5590 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5591 }
5592
5593 // Used for storing nulls.
5594 void MacroAssembler::store_heap_oop_null(Address dst) {
5595 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5596 }
5597
5598 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
5599 assert(oop_recorder() != nullptr, "this assembler needs a Recorder");
5600 int index = oop_recorder()->allocate_metadata_index(obj);
5601 RelocationHolder rspec = metadata_Relocation::spec(index);
5602 return Address((address)obj, rspec);
5603 }
5604
5605 // Move an oop into a register.
5606 void MacroAssembler::movoop(Register dst, jobject obj) {
5607 int oop_index;
5608 if (obj == nullptr) {
5609 oop_index = oop_recorder()->allocate_oop_index(obj);
5610 } else {
5611 #ifdef ASSERT
5612 {
5613 ThreadInVMfromUnknown tiv;
5614 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5615 }
5616 #endif
5617 oop_index = oop_recorder()->find_index(obj);
5618 }
5619 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5620
5621 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
5622 mov(dst, Address((address)obj, rspec));
5623 } else {
5624 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
5625 ldr(dst, Address(dummy, rspec));
5626 }
5627 }
5628
5629 // Move a metadata address into a register.
5630 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
5631 int oop_index;
5632 if (obj == nullptr) {
5633 oop_index = oop_recorder()->allocate_metadata_index(obj);
5634 } else {
5635 oop_index = oop_recorder()->find_index(obj);
5636 }
5637 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5638 mov(dst, Address((address)obj, rspec));
5639 }
5640
5641 Address MacroAssembler::constant_oop_address(jobject obj) {
5642 #ifdef ASSERT
5643 {
5644 ThreadInVMfromUnknown tiv;
5645 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5646 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5647 }
5648 #endif
5649 int oop_index = oop_recorder()->find_index(obj);
5650 return Address((address)obj, oop_Relocation::spec(oop_index));
5651 }
5652
5653 // Object / value buffer allocation...
5654 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
5655 Register t1, Register t2,
5656 bool clear_fields, Label& alloc_failed)
5657 {
5658 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
5659 Register layout_size = t1;
5660 assert(new_obj == r0, "needs to be r0");
5661 assert_different_registers(klass, new_obj, t1, t2);
5662
5663 // get instance_size in InstanceKlass (scaled to a count of bytes)
5664 ldrw(layout_size, Address(klass, Klass::layout_helper_offset()));
5665 // test to see if it is malformed in some way
5666 tst(layout_size, Klass::_lh_instance_slow_path_bit);
5667 br(Assembler::NE, slow_case_no_pop);
5668
5669 // Allocate the instance:
5670 // If TLAB is enabled:
5671 // Try to allocate in the TLAB.
5672 // If fails, go to the slow path.
5673 // Initialize the allocation.
5674 // Exit.
5675 //
5676 // Go to slow path.
5677
5678 if (UseTLAB) {
5679 push(klass);
5680 tlab_allocate(new_obj, layout_size, 0, klass, t2, slow_case);
5681 if (ZeroTLAB || (!clear_fields)) {
5682 // the fields have been already cleared
5683 b(initialize_header);
5684 } else {
5685 // initialize both the header and fields
5686 b(initialize_object);
5687 }
5688
5689 if (clear_fields) {
5690 // The object is initialized before the header. If the object size is
5691 // zero, go directly to the header initialization.
5692 bind(initialize_object);
5693 int header_size = oopDesc::header_size() * HeapWordSize;
5694 assert(is_aligned(header_size, BytesPerLong), "oop header size must be 8-byte-aligned");
5695 subs(layout_size, layout_size, header_size);
5696 br(Assembler::EQ, initialize_header);
5697
5698 // Initialize topmost object field, divide size by 8, check if odd and
5699 // test if zero.
5700
5701 #ifdef ASSERT
5702 // make sure instance_size was multiple of 8
5703 Label L;
5704 tst(layout_size, 7);
5705 br(Assembler::EQ, L);
5706 stop("object size is not multiple of 8 - adjust this code");
5707 bind(L);
5708 // must be > 0, no extra check needed here
5709 #endif
5710
5711 lsr(layout_size, layout_size, LogBytesPerLong);
5712
5713 // initialize remaining object fields: instance_size was a multiple of 8
5714 {
5715 Label loop;
5716 Register base = t2;
5717
5718 bind(loop);
5719 add(rscratch1, new_obj, layout_size, Assembler::LSL, LogBytesPerLong);
5720 str(zr, Address(rscratch1, header_size - 1*oopSize));
5721 subs(layout_size, layout_size, 1);
5722 br(Assembler::NE, loop);
5723 }
5724 } // clear_fields
5725
5726 // initialize object header only.
5727 bind(initialize_header);
5728 pop(klass);
5729 Register mark_word = t2;
5730 if (UseCompactObjectHeaders || Arguments::is_valhalla_enabled()) {
5731 ldr(mark_word, Address(klass, Klass::prototype_header_offset()));
5732 str(mark_word, Address(new_obj, oopDesc::mark_offset_in_bytes()));
5733 } else {
5734 mov(mark_word, (intptr_t)markWord::prototype().value());
5735 str(mark_word, Address(new_obj, oopDesc::mark_offset_in_bytes()));
5736 }
5737 if (!UseCompactObjectHeaders) {
5738 store_klass_gap(new_obj, zr); // zero klass gap for compressed oops
5739 mov(t2, klass); // preserve klass
5740 store_klass(new_obj, t2); // src klass reg is potentially compressed
5741 }
5742 b(done);
5743 }
5744
5745 if (UseTLAB) {
5746 bind(slow_case);
5747 pop(klass);
5748 }
5749 bind(slow_case_no_pop);
5750 b(alloc_failed);
5751
5752 bind(done);
5753 }
5754
5755 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5756 void MacroAssembler::tlab_allocate(Register obj,
5757 Register var_size_in_bytes,
5758 int con_size_in_bytes,
5759 Register t1,
5760 Register t2,
5761 Label& slow_case) {
5762 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5763 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5764 }
5765
5766 void MacroAssembler::verify_tlab() {
5767 #ifdef ASSERT
5768 if (UseTLAB && VerifyOops) {
5769 Label next, ok;
5770
5771 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5772
5773 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5774 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5775 cmp(rscratch2, rscratch1);
5776 br(Assembler::HS, next);
5777 STOP("assert(top >= start)");
5778 should_not_reach_here();
5779
5780 bind(next);
5781 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5782 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5783 cmp(rscratch2, rscratch1);
5784 br(Assembler::HS, ok);
5785 STOP("assert(top <= end)");
5786 should_not_reach_here();
5787
5788 bind(ok);
5789 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5790 }
5791 #endif
5792 }
5793
5794 void MacroAssembler::get_inline_type_field_klass(Register holder_klass, Register index, Register inline_klass) {
5795 inline_layout_info(holder_klass, index, inline_klass);
5796 ldr(inline_klass, Address(inline_klass, InlineLayoutInfo::klass_offset()));
5797 }
5798
5799 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
5800 assert_different_registers(holder_klass, index, layout_info);
5801 InlineLayoutInfo array[2];
5802 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
5803 if (is_power_of_2(size)) {
5804 lsl(index, index, log2i_exact(size)); // Scale index by power of 2
5805 } else {
5806 mov(layout_info, size);
5807 mul(index, index, layout_info); // Scale the index to be the entry index * array_element_size
5808 }
5809 ldr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
5810 add(layout_info, layout_info, Array<InlineLayoutInfo>::base_offset_in_bytes());
5811 lea(layout_info, Address(layout_info, index));
5812 }
5813
5814 // Writes to stack successive pages until offset reached to check for
5815 // stack overflow + shadow pages. This clobbers tmp.
5816 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5817 assert_different_registers(tmp, size, rscratch1);
5818 mov(tmp, sp);
5819 // Bang stack for total size given plus shadow page size.
5820 // Bang one page at a time because large size can bang beyond yellow and
5821 // red zones.
5822 Label loop;
5823 mov(rscratch1, (int)os::vm_page_size());
5824 bind(loop);
5825 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5826 subsw(size, size, rscratch1);
5827 str(size, Address(tmp));
5828 br(Assembler::GT, loop);
5829
5830 // Bang down shadow pages too.
5831 // At this point, (tmp-0) is the last address touched, so don't
5832 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5833 // was post-decremented.) Skip this address by starting at i=1, and
5834 // touch a few more pages below. N.B. It is important to touch all
5835 // the way down to and including i=StackShadowPages.
5836 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) {
5837 // this could be any sized move but this is can be a debugging crumb
5838 // so the bigger the better.
5839 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5840 str(size, Address(tmp));
5841 }
5842 }
5843
5844 // Move the address of the polling page into dest.
5845 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) {
5846 ldr(dest, Address(rthread, JavaThread::polling_page_offset()));
5847 }
5848
5849 // Read the polling page. The address of the polling page must
5850 // already be in r.
5851 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
5852 address mark;
5853 {
5854 InstructionMark im(this);
5855 code_section()->relocate(inst_mark(), rtype);
5856 ldrw(zr, Address(r, 0));
5857 mark = inst_mark();
5858 }
5859 verify_cross_modify_fence_not_required();
5860 return mark;
5861 }
5862
5863 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
5864 relocInfo::relocType rtype = dest.rspec().reloc()->type();
5865 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
5866 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
5867 uint64_t dest_page = (uint64_t)dest.target() >> 12;
5868 int64_t offset_low = dest_page - low_page;
5869 int64_t offset_high = dest_page - high_page;
5870
5871 assert(is_valid_AArch64_address(dest.target()), "bad address");
5872 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
5873
5874 InstructionMark im(this);
5875 code_section()->relocate(inst_mark(), dest.rspec());
5876 // 8143067: Ensure that the adrp can reach the dest from anywhere within
5877 // the code cache so that if it is relocated we know it will still reach
5878 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
5879 _adrp(reg1, dest.target());
5880 } else {
5881 uint64_t target = (uint64_t)dest.target();
5882 uint64_t adrp_target
5883 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
5884
5885 _adrp(reg1, (address)adrp_target);
5886 movk(reg1, target >> 32, 32);
5887 }
5888 byte_offset = (uint64_t)dest.target() & 0xfff;
5889 }
5890
5891 void MacroAssembler::load_byte_map_base(Register reg) {
5892 CardTable::CardValue* byte_map_base =
5893 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base();
5894
5895 // Strictly speaking the byte_map_base isn't an address at all, and it might
5896 // even be negative. It is thus materialised as a constant.
5897 mov(reg, (uint64_t)byte_map_base);
5898 }
5899
5900 #ifdef ASSERT
5901 void MacroAssembler::build_frame(int framesize) {
5902 build_frame(framesize, false);
5903 }
5904 #endif
5905
5906 void MacroAssembler::build_frame(int framesize DEBUG_ONLY(COMMA bool zap_rfp_lr_spills)) {
5907 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5908 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5909 protect_return_address();
5910 if (framesize < ((1 << 9) + 2 * wordSize)) {
5911 sub(sp, sp, framesize);
5912 if (DEBUG_ONLY(zap_rfp_lr_spills ||) false) {
5913 mov_immediate64(rscratch1, ((uint64_t)badRegWordVal) << 32 | (uint64_t)badRegWordVal);
5914 stp(rscratch1, rscratch1, Address(sp, framesize - 2 * wordSize));
5915 } else {
5916 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5917 }
5918 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
5919 } else {
5920 if (DEBUG_ONLY(zap_rfp_lr_spills ||) false) {
5921 mov_immediate64(rscratch1, ((uint64_t)badRegWordVal) << 32 | (uint64_t)badRegWordVal);
5922 stp(rscratch1, rscratch1, Address(pre(sp, -2 * wordSize)));
5923 } else {
5924 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
5925 }
5926 if (PreserveFramePointer) mov(rfp, sp);
5927 if (framesize < ((1 << 12) + 2 * wordSize))
5928 sub(sp, sp, framesize - 2 * wordSize);
5929 else {
5930 mov(rscratch1, framesize - 2 * wordSize);
5931 sub(sp, sp, rscratch1);
5932 }
5933 }
5934 verify_cross_modify_fence_not_required();
5935 }
5936
5937 void MacroAssembler::remove_frame(int framesize) {
5938 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5939 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5940 if (framesize < ((1 << 9) + 2 * wordSize)) {
5941 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5942 add(sp, sp, framesize);
5943 } else {
5944 if (framesize < ((1 << 12) + 2 * wordSize))
5945 add(sp, sp, framesize - 2 * wordSize);
5946 else {
5947 mov(rscratch1, framesize - 2 * wordSize);
5948 add(sp, sp, rscratch1);
5949 }
5950 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5951 }
5952 authenticate_return_address();
5953 }
5954
5955 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
5956 if (needs_stack_repair) {
5957 // Remove the extension of the caller's frame used for inline type unpacking
5958 //
5959 // Right now the stack looks like this:
5960 //
5961 // | Arguments from caller |
5962 // |---------------------------| <-- caller's SP
5963 // | Saved LR #1 |
5964 // | Saved FP #1 |
5965 // |---------------------------|
5966 // | Extension space for |
5967 // | inline arg (un)packing |
5968 // |---------------------------| <-- start of this method's frame
5969 // | Saved LR #2 |
5970 // | Saved FP #2 |
5971 // |---------------------------| <-- FP
5972 // | sp_inc |
5973 // | method locals |
5974 // |---------------------------| <-- SP
5975 //
5976 // There are two copies of FP and LR on the stack. They will be identical at
5977 // first, but that can change.
5978 // If the caller has been deoptimized, LR #1 will be patched to point at the
5979 // deopt blob, and LR #2 will still point into the old method.
5980 // If the saved FP (x29) was not used as the frame pointer, but to store an
5981 // oop, the GC will be aware only of FP #1 as the spilled location of x29 and
5982 // will fix only this one. Overall, FP/LR #2 are not reliable and are simply
5983 // needed to add space between the extension space and the locals, as there
5984 // would be between the real arguments and the locals if we don't need to
5985 // do unpacking.
5986 //
5987 // When restoring, one must then load FP #1 into x29, and LR #1 into x30,
5988 // while keeping in mind that from the scalarized entry point, there will be
5989 // only one copy of each.
5990 //
5991 // The sp_inc stack slot holds the total size of the frame including the
5992 // extension space minus two words for the saved FP and LR. That is how to
5993 // find FP/LR #1. This size is expressed in bytes. Be careful when using it
5994 // from C++ in pointer arithmetic; you might need to divide it by wordSize.
5995 //
5996 // TODO 8371993 store fake values instead of LR/FP#2
5997
5998 int sp_inc_offset = initial_framesize - 3 * wordSize; // Immediately below saved LR and FP
5999
6000 ldr(rscratch1, Address(sp, sp_inc_offset));
6001 add(sp, sp, rscratch1);
6002 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6003 } else {
6004 remove_frame(initial_framesize);
6005 }
6006 }
6007
6008 void MacroAssembler::save_stack_increment(int sp_inc, int frame_size) {
6009 int real_frame_size = frame_size + sp_inc;
6010 assert(sp_inc == 0 || sp_inc > 2*wordSize, "invalid sp_inc value");
6011 assert(real_frame_size >= 2*wordSize, "frame size must include FP/LR space");
6012 assert((real_frame_size & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6013
6014 int sp_inc_offset = frame_size - 3 * wordSize; // Immediately below saved LR and FP
6015
6016 // Subtract two words for the saved FP and LR as these will be popped
6017 // separately. See remove_frame above.
6018 mov(rscratch1, real_frame_size - 2*wordSize);
6019 str(rscratch1, Address(sp, sp_inc_offset));
6020 }
6021
6022 // This method counts leading positive bytes (highest bit not set) in provided byte array
6023 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
6024 // Simple and most common case of aligned small array which is not at the
6025 // end of memory page is placed here. All other cases are in stub.
6026 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
6027 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
6028 assert_different_registers(ary1, len, result);
6029
6030 mov(result, len);
6031 cmpw(len, 0);
6032 br(LE, DONE);
6033 cmpw(len, 4 * wordSize);
6034 br(GE, STUB_LONG); // size > 32 then go to stub
6035
6036 int shift = 64 - exact_log2(os::vm_page_size());
6037 lsl(rscratch1, ary1, shift);
6038 mov(rscratch2, (size_t)(4 * wordSize) << shift);
6039 adds(rscratch2, rscratch1, rscratch2); // At end of page?
6040 br(CS, STUB); // at the end of page then go to stub
6041 subs(len, len, wordSize);
6042 br(LT, END);
6043
6044 BIND(LOOP);
6045 ldr(rscratch1, Address(post(ary1, wordSize)));
6046 tst(rscratch1, UPPER_BIT_MASK);
6047 br(NE, SET_RESULT);
6048 subs(len, len, wordSize);
6049 br(GE, LOOP);
6050 cmpw(len, -wordSize);
6051 br(EQ, DONE);
6052
6053 BIND(END);
6054 ldr(rscratch1, Address(ary1));
6055 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
6056 lslv(rscratch1, rscratch1, rscratch2);
6057 tst(rscratch1, UPPER_BIT_MASK);
6058 br(NE, SET_RESULT);
6059 b(DONE);
6060
6061 BIND(STUB);
6062 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives());
6063 assert(count_pos.target() != nullptr, "count_positives stub has not been generated");
6064 address tpc1 = trampoline_call(count_pos);
6065 if (tpc1 == nullptr) {
6066 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE));
6067 postcond(pc() == badAddress);
6068 return nullptr;
6069 }
6070 b(DONE);
6071
6072 BIND(STUB_LONG);
6073 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long());
6074 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated");
6075 address tpc2 = trampoline_call(count_pos_long);
6076 if (tpc2 == nullptr) {
6077 DEBUG_ONLY(reset_labels(SET_RESULT, DONE));
6078 postcond(pc() == badAddress);
6079 return nullptr;
6080 }
6081 b(DONE);
6082
6083 BIND(SET_RESULT);
6084
6085 add(len, len, wordSize);
6086 sub(result, result, len);
6087
6088 BIND(DONE);
6089 postcond(pc() != badAddress);
6090 return pc();
6091 }
6092
6093 // Clobbers: rscratch1, rscratch2, rflags
6094 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals)
6095 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
6096 Register tmp4, Register tmp5, Register result,
6097 Register cnt1, int elem_size) {
6098 Label DONE, SAME;
6099 Register tmp1 = rscratch1;
6100 Register tmp2 = rscratch2;
6101 int elem_per_word = wordSize/elem_size;
6102 int log_elem_size = exact_log2(elem_size);
6103 int klass_offset = arrayOopDesc::klass_offset_in_bytes();
6104 int length_offset = arrayOopDesc::length_offset_in_bytes();
6105 int base_offset
6106 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
6107 // When the length offset is not aligned to 8 bytes,
6108 // then we align it down. This is valid because the new
6109 // offset will always be the klass which is the same
6110 // for type arrays.
6111 int start_offset = align_down(length_offset, BytesPerWord);
6112 int extra_length = base_offset - start_offset;
6113 assert(start_offset == length_offset || start_offset == klass_offset,
6114 "start offset must be 8-byte-aligned or be the klass offset");
6115 assert(base_offset != start_offset, "must include the length field");
6116 extra_length = extra_length / elem_size; // We count in elements, not bytes.
6117 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
6118
6119 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
6120 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
6121
6122 #ifndef PRODUCT
6123 {
6124 const char kind = (elem_size == 2) ? 'U' : 'L';
6125 char comment[64];
6126 os::snprintf_checked(comment, sizeof comment, "array_equals%c{", kind);
6127 BLOCK_COMMENT(comment);
6128 }
6129 #endif
6130
6131 // if (a1 == a2)
6132 // return true;
6133 cmpoop(a1, a2); // May have read barriers for a1 and a2.
6134 br(EQ, SAME);
6135
6136 if (UseSimpleArrayEquals) {
6137 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
6138 // if (a1 == nullptr || a2 == nullptr)
6139 // return false;
6140 // a1 & a2 == 0 means (some-pointer is null) or
6141 // (very-rare-or-even-probably-impossible-pointer-values)
6142 // so, we can save one branch in most cases
6143 tst(a1, a2);
6144 mov(result, false);
6145 br(EQ, A_MIGHT_BE_NULL);
6146 // if (a1.length != a2.length)
6147 // return false;
6148 bind(A_IS_NOT_NULL);
6149 ldrw(cnt1, Address(a1, length_offset));
6150 // Increase loop counter by diff between base- and actual start-offset.
6151 addw(cnt1, cnt1, extra_length);
6152 lea(a1, Address(a1, start_offset));
6153 lea(a2, Address(a2, start_offset));
6154 // Check for short strings, i.e. smaller than wordSize.
6155 subs(cnt1, cnt1, elem_per_word);
6156 br(Assembler::LT, SHORT);
6157 // Main 8 byte comparison loop.
6158 bind(NEXT_WORD); {
6159 ldr(tmp1, Address(post(a1, wordSize)));
6160 ldr(tmp2, Address(post(a2, wordSize)));
6161 subs(cnt1, cnt1, elem_per_word);
6162 eor(tmp5, tmp1, tmp2);
6163 cbnz(tmp5, DONE);
6164 } br(GT, NEXT_WORD);
6165 // Last longword. In the case where length == 4 we compare the
6166 // same longword twice, but that's still faster than another
6167 // conditional branch.
6168 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6169 // length == 4.
6170 if (log_elem_size > 0)
6171 lsl(cnt1, cnt1, log_elem_size);
6172 ldr(tmp3, Address(a1, cnt1));
6173 ldr(tmp4, Address(a2, cnt1));
6174 eor(tmp5, tmp3, tmp4);
6175 cbnz(tmp5, DONE);
6176 b(SAME);
6177 bind(A_MIGHT_BE_NULL);
6178 // in case both a1 and a2 are not-null, proceed with loads
6179 cbz(a1, DONE);
6180 cbz(a2, DONE);
6181 b(A_IS_NOT_NULL);
6182 bind(SHORT);
6183
6184 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
6185 {
6186 ldrw(tmp1, Address(post(a1, 4)));
6187 ldrw(tmp2, Address(post(a2, 4)));
6188 eorw(tmp5, tmp1, tmp2);
6189 cbnzw(tmp5, DONE);
6190 }
6191 bind(TAIL03);
6192 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
6193 {
6194 ldrh(tmp3, Address(post(a1, 2)));
6195 ldrh(tmp4, Address(post(a2, 2)));
6196 eorw(tmp5, tmp3, tmp4);
6197 cbnzw(tmp5, DONE);
6198 }
6199 bind(TAIL01);
6200 if (elem_size == 1) { // Only needed when comparing byte arrays.
6201 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6202 {
6203 ldrb(tmp1, a1);
6204 ldrb(tmp2, a2);
6205 eorw(tmp5, tmp1, tmp2);
6206 cbnzw(tmp5, DONE);
6207 }
6208 }
6209 } else {
6210 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
6211 CSET_EQ, LAST_CHECK;
6212 mov(result, false);
6213 cbz(a1, DONE);
6214 ldrw(cnt1, Address(a1, length_offset));
6215 cbz(a2, DONE);
6216 // Increase loop counter by diff between base- and actual start-offset.
6217 addw(cnt1, cnt1, extra_length);
6218
6219 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
6220 // faster to perform another branch before comparing a1 and a2
6221 cmp(cnt1, (u1)elem_per_word);
6222 br(LE, SHORT); // short or same
6223 ldr(tmp3, Address(pre(a1, start_offset)));
6224 subs(zr, cnt1, stubBytesThreshold);
6225 br(GE, STUB);
6226 ldr(tmp4, Address(pre(a2, start_offset)));
6227 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6228
6229 // Main 16 byte comparison loop with 2 exits
6230 bind(NEXT_DWORD); {
6231 ldr(tmp1, Address(pre(a1, wordSize)));
6232 ldr(tmp2, Address(pre(a2, wordSize)));
6233 subs(cnt1, cnt1, 2 * elem_per_word);
6234 br(LE, TAIL);
6235 eor(tmp4, tmp3, tmp4);
6236 cbnz(tmp4, DONE);
6237 ldr(tmp3, Address(pre(a1, wordSize)));
6238 ldr(tmp4, Address(pre(a2, wordSize)));
6239 cmp(cnt1, (u1)elem_per_word);
6240 br(LE, TAIL2);
6241 cmp(tmp1, tmp2);
6242 } br(EQ, NEXT_DWORD);
6243 b(DONE);
6244
6245 bind(TAIL);
6246 eor(tmp4, tmp3, tmp4);
6247 eor(tmp2, tmp1, tmp2);
6248 lslv(tmp2, tmp2, tmp5);
6249 orr(tmp5, tmp4, tmp2);
6250 cmp(tmp5, zr);
6251 b(CSET_EQ);
6252
6253 bind(TAIL2);
6254 eor(tmp2, tmp1, tmp2);
6255 cbnz(tmp2, DONE);
6256 b(LAST_CHECK);
6257
6258 bind(STUB);
6259 ldr(tmp4, Address(pre(a2, start_offset)));
6260 if (elem_size == 2) { // convert to byte counter
6261 lsl(cnt1, cnt1, 1);
6262 }
6263 eor(tmp5, tmp3, tmp4);
6264 cbnz(tmp5, DONE);
6265 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
6266 assert(stub.target() != nullptr, "array_equals_long stub has not been generated");
6267 address tpc = trampoline_call(stub);
6268 if (tpc == nullptr) {
6269 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
6270 postcond(pc() == badAddress);
6271 return nullptr;
6272 }
6273 b(DONE);
6274
6275 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
6276 // so, if a2 == null => return false(0), else return true, so we can return a2
6277 mov(result, a2);
6278 b(DONE);
6279 bind(SHORT);
6280 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6281 ldr(tmp3, Address(a1, start_offset));
6282 ldr(tmp4, Address(a2, start_offset));
6283 bind(LAST_CHECK);
6284 eor(tmp4, tmp3, tmp4);
6285 lslv(tmp5, tmp4, tmp5);
6286 cmp(tmp5, zr);
6287 bind(CSET_EQ);
6288 cset(result, EQ);
6289 b(DONE);
6290 }
6291
6292 bind(SAME);
6293 mov(result, true);
6294 // That's it.
6295 bind(DONE);
6296
6297 BLOCK_COMMENT("} array_equals");
6298 postcond(pc() != badAddress);
6299 return pc();
6300 }
6301
6302 // Compare Strings
6303
6304 // For Strings we're passed the address of the first characters in a1
6305 // and a2 and the length in cnt1.
6306 // There are two implementations. For arrays >= 8 bytes, all
6307 // comparisons (including the final one, which may overlap) are
6308 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
6309 // halfword, then a short, and then a byte.
6310
6311 void MacroAssembler::string_equals(Register a1, Register a2,
6312 Register result, Register cnt1)
6313 {
6314 Label SAME, DONE, SHORT, NEXT_WORD;
6315 Register tmp1 = rscratch1;
6316 Register tmp2 = rscratch2;
6317 Register cnt2 = tmp2; // cnt2 only used in array length compare
6318
6319 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
6320
6321 #ifndef PRODUCT
6322 {
6323 char comment[64];
6324 os::snprintf_checked(comment, sizeof comment, "{string_equalsL");
6325 BLOCK_COMMENT(comment);
6326 }
6327 #endif
6328
6329 mov(result, false);
6330
6331 // Check for short strings, i.e. smaller than wordSize.
6332 subs(cnt1, cnt1, wordSize);
6333 br(Assembler::LT, SHORT);
6334 // Main 8 byte comparison loop.
6335 bind(NEXT_WORD); {
6336 ldr(tmp1, Address(post(a1, wordSize)));
6337 ldr(tmp2, Address(post(a2, wordSize)));
6338 subs(cnt1, cnt1, wordSize);
6339 eor(tmp1, tmp1, tmp2);
6340 cbnz(tmp1, DONE);
6341 } br(GT, NEXT_WORD);
6342 // Last longword. In the case where length == 4 we compare the
6343 // same longword twice, but that's still faster than another
6344 // conditional branch.
6345 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6346 // length == 4.
6347 ldr(tmp1, Address(a1, cnt1));
6348 ldr(tmp2, Address(a2, cnt1));
6349 eor(tmp2, tmp1, tmp2);
6350 cbnz(tmp2, DONE);
6351 b(SAME);
6352
6353 bind(SHORT);
6354 Label TAIL03, TAIL01;
6355
6356 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
6357 {
6358 ldrw(tmp1, Address(post(a1, 4)));
6359 ldrw(tmp2, Address(post(a2, 4)));
6360 eorw(tmp1, tmp1, tmp2);
6361 cbnzw(tmp1, DONE);
6362 }
6363 bind(TAIL03);
6364 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
6365 {
6366 ldrh(tmp1, Address(post(a1, 2)));
6367 ldrh(tmp2, Address(post(a2, 2)));
6368 eorw(tmp1, tmp1, tmp2);
6369 cbnzw(tmp1, DONE);
6370 }
6371 bind(TAIL01);
6372 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6373 {
6374 ldrb(tmp1, a1);
6375 ldrb(tmp2, a2);
6376 eorw(tmp1, tmp1, tmp2);
6377 cbnzw(tmp1, DONE);
6378 }
6379 // Arrays are equal.
6380 bind(SAME);
6381 mov(result, true);
6382
6383 // That's it.
6384 bind(DONE);
6385 BLOCK_COMMENT("} string_equals");
6386 }
6387
6388
6389 // The size of the blocks erased by the zero_blocks stub. We must
6390 // handle anything smaller than this ourselves in zero_words().
6391 const int MacroAssembler::zero_words_block_size = 8;
6392
6393 // zero_words() is used by C2 ClearArray patterns and by
6394 // C1_MacroAssembler. It is as small as possible, handling small word
6395 // counts locally and delegating anything larger to the zero_blocks
6396 // stub. It is expanded many times in compiled code, so it is
6397 // important to keep it short.
6398
6399 // ptr: Address of a buffer to be zeroed.
6400 // cnt: Count in HeapWords.
6401 //
6402 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
6403 address MacroAssembler::zero_words(Register ptr, Register cnt)
6404 {
6405 assert(is_power_of_2(zero_words_block_size), "adjust this");
6406
6407 BLOCK_COMMENT("zero_words {");
6408 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
6409 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6410 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6411
6412 subs(rscratch1, cnt, zero_words_block_size);
6413 Label around;
6414 br(LO, around);
6415 {
6416 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6417 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6418 // Make sure this is a C2 compilation. C1 allocates space only for
6419 // trampoline stubs generated by Call LIR ops, and in any case it
6420 // makes sense for a C1 compilation task to proceed as quickly as
6421 // possible.
6422 CompileTask* task;
6423 if (StubRoutines::aarch64::complete()
6424 && Thread::current()->is_Compiler_thread()
6425 && (task = ciEnv::current()->task())
6426 && is_c2_compile(task->comp_level())) {
6427 address tpc = trampoline_call(zero_blocks);
6428 if (tpc == nullptr) {
6429 DEBUG_ONLY(reset_labels(around));
6430 return nullptr;
6431 }
6432 } else {
6433 far_call(zero_blocks);
6434 }
6435 }
6436 bind(around);
6437
6438 // We have a few words left to do. zero_blocks has adjusted r10 and r11
6439 // for us.
6440 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
6441 Label l;
6442 tbz(cnt, exact_log2(i), l);
6443 for (int j = 0; j < i; j += 2) {
6444 stp(zr, zr, post(ptr, 2 * BytesPerWord));
6445 }
6446 bind(l);
6447 }
6448 {
6449 Label l;
6450 tbz(cnt, 0, l);
6451 str(zr, Address(ptr));
6452 bind(l);
6453 }
6454
6455 BLOCK_COMMENT("} zero_words");
6456 return pc();
6457 }
6458
6459 // base: Address of a buffer to be zeroed, 8 bytes aligned.
6460 // cnt: Immediate count in HeapWords.
6461 //
6462 // r10, r11, rscratch1, and rscratch2 are clobbered.
6463 address MacroAssembler::zero_words(Register base, uint64_t cnt)
6464 {
6465 assert(wordSize <= BlockZeroingLowLimit,
6466 "increase BlockZeroingLowLimit");
6467 address result = nullptr;
6468 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) {
6469 #ifndef PRODUCT
6470 {
6471 char buf[64];
6472 os::snprintf_checked(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt);
6473 BLOCK_COMMENT(buf);
6474 }
6475 #endif
6476 if (cnt >= 16) {
6477 uint64_t loops = cnt/16;
6478 if (loops > 1) {
6479 mov(rscratch2, loops - 1);
6480 }
6481 {
6482 Label loop;
6483 bind(loop);
6484 for (int i = 0; i < 16; i += 2) {
6485 stp(zr, zr, Address(base, i * BytesPerWord));
6486 }
6487 add(base, base, 16 * BytesPerWord);
6488 if (loops > 1) {
6489 subs(rscratch2, rscratch2, 1);
6490 br(GE, loop);
6491 }
6492 }
6493 }
6494 cnt %= 16;
6495 int i = cnt & 1; // store any odd word to start
6496 if (i) str(zr, Address(base));
6497 for (; i < (int)cnt; i += 2) {
6498 stp(zr, zr, Address(base, i * wordSize));
6499 }
6500 BLOCK_COMMENT("} zero_words");
6501 result = pc();
6502 } else {
6503 mov(r10, base); mov(r11, cnt);
6504 result = zero_words(r10, r11);
6505 }
6506 return result;
6507 }
6508
6509 // Zero blocks of memory by using DC ZVA.
6510 //
6511 // Aligns the base address first sufficiently for DC ZVA, then uses
6512 // DC ZVA repeatedly for every full block. cnt is the size to be
6513 // zeroed in HeapWords. Returns the count of words left to be zeroed
6514 // in cnt.
6515 //
6516 // NOTE: This is intended to be used in the zero_blocks() stub. If
6517 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
6518 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
6519 Register tmp = rscratch1;
6520 Register tmp2 = rscratch2;
6521 int zva_length = VM_Version::zva_length();
6522 Label initial_table_end, loop_zva;
6523 Label fini;
6524
6525 // Base must be 16 byte aligned. If not just return and let caller handle it
6526 tst(base, 0x0f);
6527 br(Assembler::NE, fini);
6528 // Align base with ZVA length.
6529 neg(tmp, base);
6530 andr(tmp, tmp, zva_length - 1);
6531
6532 // tmp: the number of bytes to be filled to align the base with ZVA length.
6533 add(base, base, tmp);
6534 sub(cnt, cnt, tmp, Assembler::ASR, 3);
6535 adr(tmp2, initial_table_end);
6536 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
6537 br(tmp2);
6538
6539 for (int i = -zva_length + 16; i < 0; i += 16)
6540 stp(zr, zr, Address(base, i));
6541 bind(initial_table_end);
6542
6543 sub(cnt, cnt, zva_length >> 3);
6544 bind(loop_zva);
6545 dc(Assembler::ZVA, base);
6546 subs(cnt, cnt, zva_length >> 3);
6547 add(base, base, zva_length);
6548 br(Assembler::GE, loop_zva);
6549 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
6550 bind(fini);
6551 }
6552
6553 // base: Address of a buffer to be filled, 8 bytes aligned.
6554 // cnt: Count in 8-byte unit.
6555 // value: Value to be filled with.
6556 // base will point to the end of the buffer after filling.
6557 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
6558 {
6559 // Algorithm:
6560 //
6561 // if (cnt == 0) {
6562 // return;
6563 // }
6564 // if ((p & 8) != 0) {
6565 // *p++ = v;
6566 // }
6567 //
6568 // scratch1 = cnt & 14;
6569 // cnt -= scratch1;
6570 // p += scratch1;
6571 // switch (scratch1 / 2) {
6572 // do {
6573 // cnt -= 16;
6574 // p[-16] = v;
6575 // p[-15] = v;
6576 // case 7:
6577 // p[-14] = v;
6578 // p[-13] = v;
6579 // case 6:
6580 // p[-12] = v;
6581 // p[-11] = v;
6582 // // ...
6583 // case 1:
6584 // p[-2] = v;
6585 // p[-1] = v;
6586 // case 0:
6587 // p += 16;
6588 // } while (cnt);
6589 // }
6590 // if ((cnt & 1) == 1) {
6591 // *p++ = v;
6592 // }
6593
6594 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
6595
6596 Label fini, skip, entry, loop;
6597 const int unroll = 8; // Number of stp instructions we'll unroll
6598
6599 cbz(cnt, fini);
6600 tbz(base, 3, skip);
6601 str(value, Address(post(base, 8)));
6602 sub(cnt, cnt, 1);
6603 bind(skip);
6604
6605 andr(rscratch1, cnt, (unroll-1) * 2);
6606 sub(cnt, cnt, rscratch1);
6607 add(base, base, rscratch1, Assembler::LSL, 3);
6608 adr(rscratch2, entry);
6609 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
6610 br(rscratch2);
6611
6612 bind(loop);
6613 add(base, base, unroll * 16);
6614 for (int i = -unroll; i < 0; i++)
6615 stp(value, value, Address(base, i * 16));
6616 bind(entry);
6617 subs(cnt, cnt, unroll * 2);
6618 br(Assembler::GE, loop);
6619
6620 tbz(cnt, 0, fini);
6621 str(value, Address(post(base, 8)));
6622 bind(fini);
6623 }
6624
6625 // Intrinsic for
6626 //
6627 // - sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6628 // Encodes char[] to byte[] in ISO-8859-1
6629 //
6630 // - java.lang.StringCoding#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6631 // Encodes byte[] (containing UTF-16) to byte[] in ISO-8859-1
6632 //
6633 // - java.lang.StringCoding#encodeAsciiArray0(char[] sa, int sp, byte[] da, int dp, int len)
6634 // Encodes char[] to byte[] in ASCII
6635 //
6636 // This version always returns the number of characters copied, and does not
6637 // clobber the 'len' register. A successful copy will complete with the post-
6638 // condition: 'res' == 'len', while an unsuccessful copy will exit with the
6639 // post-condition: 0 <= 'res' < 'len'.
6640 //
6641 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
6642 // degrade performance (on Ampere Altra - Neoverse N1), to an extent
6643 // beyond the acceptable, even though the footprint would be smaller.
6644 // Using 'umaxv' in the ASCII-case comes with a small penalty but does
6645 // avoid additional bloat.
6646 //
6647 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags
6648 void MacroAssembler::encode_iso_array(Register src, Register dst,
6649 Register len, Register res, bool ascii,
6650 FloatRegister vtmp0, FloatRegister vtmp1,
6651 FloatRegister vtmp2, FloatRegister vtmp3,
6652 FloatRegister vtmp4, FloatRegister vtmp5)
6653 {
6654 Register cnt = res;
6655 Register max = rscratch1;
6656 Register chk = rscratch2;
6657
6658 prfm(Address(src), PLDL1STRM);
6659 movw(cnt, len);
6660
6661 #define ASCII(insn) do { if (ascii) { insn; } } while (0)
6662
6663 Label LOOP_32, DONE_32, FAIL_32;
6664
6665 BIND(LOOP_32);
6666 {
6667 cmpw(cnt, 32);
6668 br(LT, DONE_32);
6669 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
6670 // Extract lower bytes.
6671 FloatRegister vlo0 = vtmp4;
6672 FloatRegister vlo1 = vtmp5;
6673 uzp1(vlo0, T16B, vtmp0, vtmp1);
6674 uzp1(vlo1, T16B, vtmp2, vtmp3);
6675 // Merge bits...
6676 orr(vtmp0, T16B, vtmp0, vtmp1);
6677 orr(vtmp2, T16B, vtmp2, vtmp3);
6678 // Extract merged upper bytes.
6679 FloatRegister vhix = vtmp0;
6680 uzp2(vhix, T16B, vtmp0, vtmp2);
6681 // ISO-check on hi-parts (all zero).
6682 // ASCII-check on lo-parts (no sign).
6683 FloatRegister vlox = vtmp1; // Merge lower bytes.
6684 ASCII(orr(vlox, T16B, vlo0, vlo1));
6685 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox));
6686 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox));
6687 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0));
6688 ASCII(orr(chk, chk, max));
6689 cbnz(chk, FAIL_32);
6690 subw(cnt, cnt, 32);
6691 st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
6692 b(LOOP_32);
6693 }
6694 BIND(FAIL_32);
6695 sub(src, src, 64);
6696 BIND(DONE_32);
6697
6698 Label LOOP_8, SKIP_8;
6699
6700 BIND(LOOP_8);
6701 {
6702 cmpw(cnt, 8);
6703 br(LT, SKIP_8);
6704 FloatRegister vhi = vtmp0;
6705 FloatRegister vlo = vtmp1;
6706 ld1(vtmp3, T8H, src);
6707 uzp1(vlo, T16B, vtmp3, vtmp3);
6708 uzp2(vhi, T16B, vtmp3, vtmp3);
6709 // ISO-check on hi-parts (all zero).
6710 // ASCII-check on lo-parts (no sign).
6711 ASCII(cm(LT, vtmp2, T16B, vlo));
6712 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2));
6713 ASCII(umov(max, vtmp2, B, 0));
6714 ASCII(orr(chk, chk, max));
6715 cbnz(chk, SKIP_8);
6716
6717 strd(vlo, Address(post(dst, 8)));
6718 subw(cnt, cnt, 8);
6719 add(src, src, 16);
6720 b(LOOP_8);
6721 }
6722 BIND(SKIP_8);
6723
6724 #undef ASCII
6725
6726 Label LOOP, DONE;
6727
6728 cbz(cnt, DONE);
6729 BIND(LOOP);
6730 {
6731 Register chr = rscratch1;
6732 ldrh(chr, Address(post(src, 2)));
6733 tst(chr, ascii ? 0xff80 : 0xff00);
6734 br(NE, DONE);
6735 strb(chr, Address(post(dst, 1)));
6736 subs(cnt, cnt, 1);
6737 br(GT, LOOP);
6738 }
6739 BIND(DONE);
6740 // Return index where we stopped.
6741 subw(res, len, cnt);
6742 }
6743
6744 // Inflate byte[] array to char[].
6745 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6
6746 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
6747 FloatRegister vtmp1, FloatRegister vtmp2,
6748 FloatRegister vtmp3, Register tmp4) {
6749 Label big, done, after_init, to_stub;
6750
6751 assert_different_registers(src, dst, len, tmp4, rscratch1);
6752
6753 fmovd(vtmp1, 0.0);
6754 lsrw(tmp4, len, 3);
6755 bind(after_init);
6756 cbnzw(tmp4, big);
6757 // Short string: less than 8 bytes.
6758 {
6759 Label loop, tiny;
6760
6761 cmpw(len, 4);
6762 br(LT, tiny);
6763 // Use SIMD to do 4 bytes.
6764 ldrs(vtmp2, post(src, 4));
6765 zip1(vtmp3, T8B, vtmp2, vtmp1);
6766 subw(len, len, 4);
6767 strd(vtmp3, post(dst, 8));
6768
6769 cbzw(len, done);
6770
6771 // Do the remaining bytes by steam.
6772 bind(loop);
6773 ldrb(tmp4, post(src, 1));
6774 strh(tmp4, post(dst, 2));
6775 subw(len, len, 1);
6776
6777 bind(tiny);
6778 cbnz(len, loop);
6779
6780 b(done);
6781 }
6782
6783 if (SoftwarePrefetchHintDistance >= 0) {
6784 bind(to_stub);
6785 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
6786 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated");
6787 address tpc = trampoline_call(stub);
6788 if (tpc == nullptr) {
6789 DEBUG_ONLY(reset_labels(big, done));
6790 postcond(pc() == badAddress);
6791 return nullptr;
6792 }
6793 b(after_init);
6794 }
6795
6796 // Unpack the bytes 8 at a time.
6797 bind(big);
6798 {
6799 Label loop, around, loop_last, loop_start;
6800
6801 if (SoftwarePrefetchHintDistance >= 0) {
6802 const int large_loop_threshold = (64 + 16)/8;
6803 ldrd(vtmp2, post(src, 8));
6804 andw(len, len, 7);
6805 cmp(tmp4, (u1)large_loop_threshold);
6806 br(GE, to_stub);
6807 b(loop_start);
6808
6809 bind(loop);
6810 ldrd(vtmp2, post(src, 8));
6811 bind(loop_start);
6812 subs(tmp4, tmp4, 1);
6813 br(EQ, loop_last);
6814 zip1(vtmp2, T16B, vtmp2, vtmp1);
6815 ldrd(vtmp3, post(src, 8));
6816 st1(vtmp2, T8H, post(dst, 16));
6817 subs(tmp4, tmp4, 1);
6818 zip1(vtmp3, T16B, vtmp3, vtmp1);
6819 st1(vtmp3, T8H, post(dst, 16));
6820 br(NE, loop);
6821 b(around);
6822 bind(loop_last);
6823 zip1(vtmp2, T16B, vtmp2, vtmp1);
6824 st1(vtmp2, T8H, post(dst, 16));
6825 bind(around);
6826 cbz(len, done);
6827 } else {
6828 andw(len, len, 7);
6829 bind(loop);
6830 ldrd(vtmp2, post(src, 8));
6831 sub(tmp4, tmp4, 1);
6832 zip1(vtmp3, T16B, vtmp2, vtmp1);
6833 st1(vtmp3, T8H, post(dst, 16));
6834 cbnz(tmp4, loop);
6835 }
6836 }
6837
6838 // Do the tail of up to 8 bytes.
6839 add(src, src, len);
6840 ldrd(vtmp3, Address(src, -8));
6841 add(dst, dst, len, ext::uxtw, 1);
6842 zip1(vtmp3, T16B, vtmp3, vtmp1);
6843 strq(vtmp3, Address(dst, -16));
6844
6845 bind(done);
6846 postcond(pc() != badAddress);
6847 return pc();
6848 }
6849
6850 // Compress char[] array to byte[].
6851 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
6852 // Return the array length if every element in array can be encoded,
6853 // otherwise, the index of first non-latin1 (> 0xff) character.
6854 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
6855 Register res,
6856 FloatRegister tmp0, FloatRegister tmp1,
6857 FloatRegister tmp2, FloatRegister tmp3,
6858 FloatRegister tmp4, FloatRegister tmp5) {
6859 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
6860 }
6861
6862 // java.math.round(double a)
6863 // Returns the closest long to the argument, with ties rounding to
6864 // positive infinity. This requires some fiddling for corner
6865 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5).
6866 void MacroAssembler::java_round_double(Register dst, FloatRegister src,
6867 FloatRegister ftmp) {
6868 Label DONE;
6869 BLOCK_COMMENT("java_round_double: { ");
6870 fmovd(rscratch1, src);
6871 // Use RoundToNearestTiesAway unless src small and -ve.
6872 fcvtasd(dst, src);
6873 // Test if src >= 0 || abs(src) >= 0x1.0p52
6874 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit
6875 mov(rscratch2, julong_cast(0x1.0p52));
6876 cmp(rscratch1, rscratch2);
6877 br(HS, DONE); {
6878 // src < 0 && abs(src) < 0x1.0p52
6879 // src may have a fractional part, so add 0.5
6880 fmovd(ftmp, 0.5);
6881 faddd(ftmp, src, ftmp);
6882 // Convert double to jlong, use RoundTowardsNegative
6883 fcvtmsd(dst, ftmp);
6884 }
6885 bind(DONE);
6886 BLOCK_COMMENT("} java_round_double");
6887 }
6888
6889 void MacroAssembler::java_round_float(Register dst, FloatRegister src,
6890 FloatRegister ftmp) {
6891 Label DONE;
6892 BLOCK_COMMENT("java_round_float: { ");
6893 fmovs(rscratch1, src);
6894 // Use RoundToNearestTiesAway unless src small and -ve.
6895 fcvtassw(dst, src);
6896 // Test if src >= 0 || abs(src) >= 0x1.0p23
6897 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit
6898 mov(rscratch2, jint_cast(0x1.0p23f));
6899 cmp(rscratch1, rscratch2);
6900 br(HS, DONE); {
6901 // src < 0 && |src| < 0x1.0p23
6902 // src may have a fractional part, so add 0.5
6903 fmovs(ftmp, 0.5f);
6904 fadds(ftmp, src, ftmp);
6905 // Convert float to jint, use RoundTowardsNegative
6906 fcvtmssw(dst, ftmp);
6907 }
6908 bind(DONE);
6909 BLOCK_COMMENT("} java_round_float");
6910 }
6911
6912 // get_thread() can be called anywhere inside generated code so we
6913 // need to save whatever non-callee save context might get clobbered
6914 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
6915 // the call setup code.
6916 //
6917 // On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags.
6918 // On other systems, the helper is a usual C function.
6919 //
6920 void MacroAssembler::get_thread(Register dst) {
6921 RegSet saved_regs =
6922 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6923 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6924
6925 protect_return_address();
6926 push(saved_regs, sp);
6927
6928 mov(lr, ExternalAddress(CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)));
6929 blr(lr);
6930 if (dst != c_rarg0) {
6931 mov(dst, c_rarg0);
6932 }
6933
6934 pop(saved_regs, sp);
6935 authenticate_return_address();
6936 }
6937
6938 #ifdef COMPILER2
6939 // C2 compiled method's prolog code
6940 // Moved here from aarch64.ad to support Valhalla code belows
6941 void MacroAssembler::verified_entry(Compile* C, int sp_inc) {
6942 if (C->clinit_barrier_on_entry()) {
6943 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
6944
6945 Label L_skip_barrier;
6946
6947 mov_metadata(rscratch2, C->method()->holder()->constant_encoding());
6948 clinit_barrier(rscratch2, rscratch1, &L_skip_barrier);
6949 far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
6950 bind(L_skip_barrier);
6951 }
6952
6953 if (C->max_vector_size() > 0) {
6954 reinitialize_ptrue();
6955 }
6956
6957 int bangsize = C->output()->bang_size_in_bytes();
6958 if (C->output()->need_stack_bang(bangsize))
6959 generate_stack_overflow_check(bangsize);
6960
6961 // n.b. frame size includes space for return pc and rfp
6962 const long framesize = C->output()->frame_size_in_bytes();
6963 build_frame(framesize DEBUG_ONLY(COMMA sp_inc != 0));
6964
6965 if (C->needs_stack_repair()) {
6966 save_stack_increment(sp_inc, framesize);
6967 }
6968
6969 if (VerifyStackAtCalls) {
6970 Unimplemented();
6971 }
6972 }
6973 #endif // COMPILER2
6974
6975 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6976 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6977 // An inline type might be returned. If fields are in registers we
6978 // need to allocate an inline type instance and initialize it with
6979 // the value of the fields.
6980 Label skip;
6981 // We only need a new buffered inline type if a new one is not returned
6982 tbz(r0, 0, skip);
6983 int call_offset = -1;
6984
6985 // Be careful not to clobber r1-7 which hold returned fields
6986 // Also do not use callee-saved registers as these may be live in the interpreter
6987 Register tmp1 = r13, tmp2 = r14, klass = r15, r0_preserved = r12;
6988
6989 // The following code is similar to allocate_instance but has some slight differences,
6990 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6991 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these.
6992 Label slow_case;
6993 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6994 mov(r0_preserved, r0); // save r0 for slow_case since *_allocate may corrupt it when allocation failed
6995
6996 if (vk != nullptr) {
6997 // Called from C1, where the return type is statically known.
6998 movptr(klass, (intptr_t)vk->get_InlineKlass());
6999 jint lh = vk->layout_helper();
7000 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
7001 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
7002 tlab_allocate(r0, noreg, lh, tmp1, tmp2, slow_case);
7003 } else {
7004 b(slow_case);
7005 }
7006 } else {
7007 // Call from interpreter. R0 contains ((the InlineKlass* of the return type) | 0x01)
7008 andr(klass, r0, -2);
7009 if (UseTLAB) {
7010 ldrw(tmp2, Address(klass, Klass::layout_helper_offset()));
7011 tst(tmp2, Klass::_lh_instance_slow_path_bit);
7012 br(Assembler::NE, slow_case);
7013 tlab_allocate(r0, tmp2, 0, tmp1, tmp2, slow_case);
7014 } else {
7015 b(slow_case);
7016 }
7017 }
7018 if (UseTLAB) {
7019 // 2. Initialize buffered inline instance header
7020 Register buffer_obj = r0;
7021 if (UseCompactObjectHeaders) {
7022 ldr(rscratch1, Address(klass, Klass::prototype_header_offset()));
7023 str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes()));
7024 } else {
7025 mov(rscratch1, (intptr_t)markWord::inline_type_prototype().value());
7026 str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes()));
7027 store_klass_gap(buffer_obj, zr);
7028 if (vk == nullptr) {
7029 // store_klass corrupts klass, so save it for later use (interpreter case only).
7030 mov(tmp1, klass);
7031 }
7032 store_klass(buffer_obj, klass);
7033 klass = tmp1;
7034 }
7035 // 3. Initialize its fields with an inline class specific handler
7036 if (vk != nullptr) {
7037 far_call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
7038 } else {
7039 ldr(tmp1, Address(klass, InlineKlass::adr_members_offset()));
7040 ldr(tmp1, Address(tmp1, InlineKlass::pack_handler_offset()));
7041 blr(tmp1);
7042 }
7043
7044 membar(Assembler::StoreStore);
7045 b(skip);
7046 } else {
7047 // Must have already branched to slow_case above.
7048 DEBUG_ONLY(should_not_reach_here());
7049 }
7050 bind(slow_case);
7051 // We failed to allocate a new inline type, fall back to a runtime
7052 // call. Some oop field may be live in some registers but we can't
7053 // tell. That runtime call will take care of preserving them
7054 // across a GC if there's one.
7055 mov(r0, r0_preserved);
7056
7057 if (from_interpreter) {
7058 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
7059 } else {
7060 far_call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
7061 call_offset = offset();
7062 }
7063 membar(Assembler::StoreStore);
7064
7065 bind(skip);
7066 return call_offset;
7067 }
7068
7069 // Move a value between registers/stack slots and update the reg_state
7070 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
7071 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
7072 if (reg_state[to->value()] == reg_written) {
7073 return true; // Already written
7074 }
7075
7076 if (from != to && bt != T_VOID) {
7077 if (reg_state[to->value()] == reg_readonly) {
7078 return false; // Not yet writable
7079 }
7080 if (from->is_reg()) {
7081 if (to->is_reg()) {
7082 if (from->is_Register() && to->is_Register()) {
7083 mov(to->as_Register(), from->as_Register());
7084 } else if (from->is_FloatRegister() && to->is_FloatRegister()) {
7085 fmovd(to->as_FloatRegister(), from->as_FloatRegister());
7086 } else {
7087 ShouldNotReachHere();
7088 }
7089 } else {
7090 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
7091 Address to_addr = Address(sp, st_off);
7092 if (from->is_FloatRegister()) {
7093 if (bt == T_DOUBLE) {
7094 strd(from->as_FloatRegister(), to_addr);
7095 } else {
7096 assert(bt == T_FLOAT, "must be float");
7097 strs(from->as_FloatRegister(), to_addr);
7098 }
7099 } else {
7100 str(from->as_Register(), to_addr);
7101 }
7102 }
7103 } else {
7104 Address from_addr = Address(sp, from->reg2stack() * VMRegImpl::stack_slot_size);
7105 if (to->is_reg()) {
7106 if (to->is_FloatRegister()) {
7107 if (bt == T_DOUBLE) {
7108 ldrd(to->as_FloatRegister(), from_addr);
7109 } else {
7110 assert(bt == T_FLOAT, "must be float");
7111 ldrs(to->as_FloatRegister(), from_addr);
7112 }
7113 } else {
7114 ldr(to->as_Register(), from_addr);
7115 }
7116 } else {
7117 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
7118 ldr(rscratch1, from_addr);
7119 str(rscratch1, Address(sp, st_off));
7120 }
7121 }
7122 }
7123
7124 // Update register states
7125 reg_state[from->value()] = reg_writable;
7126 reg_state[to->value()] = reg_written;
7127 return true;
7128 }
7129
7130 // Calculate the extra stack space required for packing or unpacking inline
7131 // args and adjust the stack pointer
7132 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
7133 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
7134 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
7135 assert(sp_inc > 0, "sanity");
7136
7137 // Save a copy of the FP and LR here for deoptimization patching and frame walking
7138 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
7139
7140 // Adjust the stack pointer. This will be repaired on return by MacroAssembler::remove_frame
7141 if (sp_inc < (1 << 9)) {
7142 sub(sp, sp, sp_inc); // Fits in an immediate
7143 } else {
7144 mov(rscratch1, sp_inc);
7145 sub(sp, sp, rscratch1);
7146 }
7147
7148 return sp_inc + 2 * wordSize; // Account for the FP/LR space
7149 }
7150
7151 // Read all fields from an inline type oop and store the values in registers/stack slots
7152 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
7153 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
7154 RegState reg_state[]) {
7155 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
7156 assert(from->is_valid(), "source must be valid");
7157 bool progress = false;
7158 #ifdef ASSERT
7159 const int start_offset = offset();
7160 #endif
7161
7162 Label L_null, L_notNull;
7163 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
7164 // TODO 8366717 We need to make sure that r14 (and potentially other long-life regs) are kept live in slowpath runtime calls in GC barriers
7165 Register tmp1 = r10;
7166 Register tmp2 = r11;
7167 Register fromReg = noreg;
7168 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, -1);
7169 bool done = true;
7170 bool mark_done = true;
7171 VMReg toReg;
7172 BasicType bt;
7173 // Check if argument requires a null check
7174 bool null_check = false;
7175 VMReg nullCheckReg;
7176 while (stream.next(nullCheckReg, bt)) {
7177 if (sig->at(stream.sig_index())._offset == -1) {
7178 null_check = true;
7179 break;
7180 }
7181 }
7182 stream.reset(sig_index, to_index);
7183 while (stream.next(toReg, bt)) {
7184 assert(toReg->is_valid(), "destination must be valid");
7185 int idx = (int)toReg->value();
7186 if (reg_state[idx] == reg_readonly) {
7187 if (idx != from->value()) {
7188 mark_done = false;
7189 }
7190 done = false;
7191 continue;
7192 } else if (reg_state[idx] == reg_written) {
7193 continue;
7194 }
7195 assert(reg_state[idx] == reg_writable, "must be writable");
7196 reg_state[idx] = reg_written;
7197 progress = true;
7198
7199 if (fromReg == noreg) {
7200 if (from->is_reg()) {
7201 fromReg = from->as_Register();
7202 } else {
7203 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size;
7204 ldr(tmp1, Address(sp, st_off));
7205 fromReg = tmp1;
7206 }
7207 if (null_check) {
7208 // Nullable inline type argument, emit null check
7209 cbz(fromReg, L_null);
7210 }
7211 }
7212 int off = sig->at(stream.sig_index())._offset;
7213 if (off == -1) {
7214 assert(null_check, "Missing null check at");
7215 if (toReg->is_stack()) {
7216 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7217 mov(tmp2, 1);
7218 str(tmp2, Address(sp, st_off));
7219 } else {
7220 mov(toReg->as_Register(), 1);
7221 }
7222 continue;
7223 }
7224 assert(off > 0, "offset in object should be positive");
7225 Address fromAddr = Address(fromReg, off);
7226 if (!toReg->is_FloatRegister()) {
7227 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
7228 if (is_reference_type(bt)) {
7229 load_heap_oop(dst, fromAddr, rscratch1, rscratch2);
7230 } else {
7231 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
7232 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
7233 }
7234 if (toReg->is_stack()) {
7235 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7236 str(dst, Address(sp, st_off));
7237 }
7238 } else if (bt == T_DOUBLE) {
7239 ldrd(toReg->as_FloatRegister(), fromAddr);
7240 } else {
7241 assert(bt == T_FLOAT, "must be float");
7242 ldrs(toReg->as_FloatRegister(), fromAddr);
7243 }
7244 }
7245 if (progress && null_check) {
7246 if (done) {
7247 b(L_notNull);
7248 bind(L_null);
7249 // Set null marker to zero to signal that the argument is null.
7250 // Also set all oop fields to zero to make the GC happy.
7251 stream.reset(sig_index, to_index);
7252 while (stream.next(toReg, bt)) {
7253 if (sig->at(stream.sig_index())._offset == -1 ||
7254 bt == T_OBJECT || bt == T_ARRAY) {
7255 if (toReg->is_stack()) {
7256 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7257 str(zr, Address(sp, st_off));
7258 } else {
7259 mov(toReg->as_Register(), zr);
7260 }
7261 }
7262 }
7263 bind(L_notNull);
7264 } else {
7265 bind(L_null);
7266 }
7267 }
7268
7269 // TODO 8366717 This is probably okay but looks fishy because stream is reset in the "Set null marker to zero" case just above. Same on x64.
7270 sig_index = stream.sig_index();
7271 to_index = stream.regs_index();
7272
7273 if (mark_done && reg_state[from->value()] != reg_written) {
7274 // This is okay because no one else will write to that slot
7275 reg_state[from->value()] = reg_writable;
7276 }
7277 from_index--;
7278 assert(progress || (start_offset == offset()), "should not emit code");
7279 return done;
7280 }
7281
7282 // Pack fields back into an inline type oop
7283 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
7284 VMRegPair* from, int from_count, int& from_index, VMReg to,
7285 RegState reg_state[], Register val_array) {
7286 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
7287 assert(to->is_valid(), "destination must be valid");
7288
7289 if (reg_state[to->value()] == reg_written) {
7290 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7291 return true; // Already written
7292 }
7293
7294 // The GC barrier expanded by store_heap_oop below may call into the
7295 // runtime so use callee-saved registers for any values that need to be
7296 // preserved. The GC barrier assembler should take care of saving the
7297 // Java argument registers.
7298 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
7299 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
7300 Register val_obj_tmp = r21;
7301 Register from_reg_tmp = r22;
7302 Register tmp1 = r14;
7303 Register tmp2 = r13;
7304 Register tmp3 = r12;
7305 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
7306
7307 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
7308
7309 if (reg_state[to->value()] == reg_readonly) {
7310 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
7311 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7312 return false; // Not yet writable
7313 }
7314 val_obj = val_obj_tmp;
7315 }
7316
7317 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
7318 load_heap_oop(val_obj, Address(val_array, index), tmp1, tmp2);
7319
7320 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
7321 VMReg fromReg;
7322 BasicType bt;
7323 Label L_null;
7324 while (stream.next(fromReg, bt)) {
7325 assert(fromReg->is_valid(), "source must be valid");
7326 reg_state[fromReg->value()] = reg_writable;
7327
7328 int off = sig->at(stream.sig_index())._offset;
7329 if (off == -1) {
7330 // Nullable inline type argument, emit null check
7331 Label L_notNull;
7332 if (fromReg->is_stack()) {
7333 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7334 ldrb(tmp2, Address(sp, ld_off));
7335 cbnz(tmp2, L_notNull);
7336 } else {
7337 cbnz(fromReg->as_Register(), L_notNull);
7338 }
7339 mov(val_obj, 0);
7340 b(L_null);
7341 bind(L_notNull);
7342 continue;
7343 }
7344
7345 assert(off > 0, "offset in object should be positive");
7346 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
7347
7348 // Pack the scalarized field into the value object.
7349 Address dst(val_obj, off);
7350 if (!fromReg->is_FloatRegister()) {
7351 Register src;
7352 if (fromReg->is_stack()) {
7353 src = from_reg_tmp;
7354 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7355 load_sized_value(src, Address(sp, ld_off), size_in_bytes, /* is_signed */ false);
7356 } else {
7357 src = fromReg->as_Register();
7358 }
7359 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
7360 if (is_reference_type(bt)) {
7361 store_heap_oop(dst, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
7362 } else {
7363 store_sized_value(dst, src, size_in_bytes);
7364 }
7365 } else if (bt == T_DOUBLE) {
7366 strd(fromReg->as_FloatRegister(), dst);
7367 } else {
7368 assert(bt == T_FLOAT, "must be float");
7369 strs(fromReg->as_FloatRegister(), dst);
7370 }
7371 }
7372 bind(L_null);
7373 sig_index = stream.sig_index();
7374 from_index = stream.regs_index();
7375
7376 assert(reg_state[to->value()] == reg_writable, "must have already been read");
7377 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
7378 assert(success, "to register must be writeable");
7379 return true;
7380 }
7381
7382 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
7383 return (reg->is_FloatRegister()) ? v8->as_VMReg() : r14->as_VMReg();
7384 }
7385
7386 void MacroAssembler::cache_wb(Address line) {
7387 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
7388 assert(line.index() == noreg, "index should be noreg");
7389 assert(line.offset() == 0, "offset should be 0");
7390 // would like to assert this
7391 // assert(line._ext.shift == 0, "shift should be zero");
7392 if (VM_Version::supports_dcpop()) {
7393 // writeback using clear virtual address to point of persistence
7394 dc(Assembler::CVAP, line.base());
7395 } else {
7396 // no need to generate anything as Unsafe.writebackMemory should
7397 // never invoke this stub
7398 }
7399 }
7400
7401 void MacroAssembler::cache_wbsync(bool is_pre) {
7402 // we only need a barrier post sync
7403 if (!is_pre) {
7404 membar(Assembler::AnyAny);
7405 }
7406 }
7407
7408 void MacroAssembler::verify_sve_vector_length(Register tmp) {
7409 if (!UseSVE || VM_Version::get_max_supported_sve_vector_length() == FloatRegister::sve_vl_min) {
7410 return;
7411 }
7412 // Make sure that native code does not change SVE vector length.
7413 Label verify_ok;
7414 movw(tmp, zr);
7415 sve_inc(tmp, B);
7416 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length());
7417 br(EQ, verify_ok);
7418 stop("Error: SVE vector length has changed since jvm startup");
7419 bind(verify_ok);
7420 }
7421
7422 void MacroAssembler::verify_ptrue() {
7423 Label verify_ok;
7424 if (!UseSVE) {
7425 return;
7426 }
7427 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
7428 sve_dec(rscratch1, B);
7429 cbz(rscratch1, verify_ok);
7430 stop("Error: the preserved predicate register (p7) elements are not all true");
7431 bind(verify_ok);
7432 }
7433
7434 void MacroAssembler::safepoint_isb() {
7435 isb();
7436 #ifndef PRODUCT
7437 if (VerifyCrossModifyFence) {
7438 // Clear the thread state.
7439 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
7440 }
7441 #endif
7442 }
7443
7444 #ifndef PRODUCT
7445 void MacroAssembler::verify_cross_modify_fence_not_required() {
7446 if (VerifyCrossModifyFence) {
7447 // Check if thread needs a cross modify fence.
7448 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
7449 Label fence_not_required;
7450 cbz(rscratch1, fence_not_required);
7451 // If it does then fail.
7452 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure)));
7453 mov(c_rarg0, rthread);
7454 blr(rscratch1);
7455 bind(fence_not_required);
7456 }
7457 }
7458 #endif
7459
7460 void MacroAssembler::spin_wait() {
7461 block_comment("spin_wait {");
7462 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
7463 switch (VM_Version::spin_wait_desc().inst()) {
7464 case SpinWait::NOP:
7465 nop();
7466 break;
7467 case SpinWait::ISB:
7468 isb();
7469 break;
7470 case SpinWait::YIELD:
7471 yield();
7472 break;
7473 case SpinWait::SB:
7474 assert(VM_Version::supports_sb(), "current CPU does not support SB instruction");
7475 sb();
7476 break;
7477 default:
7478 ShouldNotReachHere();
7479 }
7480 }
7481 block_comment("}");
7482 }
7483
7484 // Stack frame creation/removal
7485
7486 void MacroAssembler::enter(bool strip_ret_addr) {
7487 if (strip_ret_addr) {
7488 // Addresses can only be signed once. If there are multiple nested frames being created
7489 // in the same function, then the return address needs stripping first.
7490 strip_return_address();
7491 }
7492 protect_return_address();
7493 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
7494 mov(rfp, sp);
7495 }
7496
7497 void MacroAssembler::leave() {
7498 mov(sp, rfp);
7499 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
7500 authenticate_return_address();
7501 }
7502
7503 // ROP Protection
7504 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/
7505 // destroying stack frames or whenever directly loading/storing the LR to memory.
7506 // If ROP protection is not set then these functions are no-ops.
7507 // For more details on PAC see pauth_aarch64.hpp.
7508
7509 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory.
7510 // Uses value zero as the modifier.
7511 //
7512 void MacroAssembler::protect_return_address() {
7513 if (VM_Version::use_rop_protection()) {
7514 check_return_address();
7515 paciaz();
7516 }
7517 }
7518
7519 // Sign the return value in the given register. Use before updating the LR in the existing stack
7520 // frame for the current function.
7521 // Uses value zero as the modifier.
7522 //
7523 void MacroAssembler::protect_return_address(Register return_reg) {
7524 if (VM_Version::use_rop_protection()) {
7525 check_return_address(return_reg);
7526 paciza(return_reg);
7527 }
7528 }
7529
7530 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory.
7531 // Uses value zero as the modifier.
7532 //
7533 void MacroAssembler::authenticate_return_address() {
7534 if (VM_Version::use_rop_protection()) {
7535 autiaz();
7536 check_return_address();
7537 }
7538 }
7539
7540 // Authenticate the return value in the given register. Use before updating the LR in the existing
7541 // stack frame for the current function.
7542 // Uses value zero as the modifier.
7543 //
7544 void MacroAssembler::authenticate_return_address(Register return_reg) {
7545 if (VM_Version::use_rop_protection()) {
7546 autiza(return_reg);
7547 check_return_address(return_reg);
7548 }
7549 }
7550
7551 // Strip any PAC data from LR without performing any authentication. Use with caution - only if
7552 // there is no guaranteed way of authenticating the LR.
7553 //
7554 void MacroAssembler::strip_return_address() {
7555 if (VM_Version::use_rop_protection()) {
7556 xpaclri();
7557 }
7558 }
7559
7560 #ifndef PRODUCT
7561 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only
7562 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point
7563 // it is difficult to debug back to the callee function.
7564 // This function simply loads from the address in the given register.
7565 // Use directly after authentication to catch authentication failures.
7566 // Also use before signing to check that the pointer is valid and hasn't already been signed.
7567 //
7568 void MacroAssembler::check_return_address(Register return_reg) {
7569 if (VM_Version::use_rop_protection()) {
7570 ldr(zr, Address(return_reg));
7571 }
7572 }
7573 #endif
7574
7575 // The java_calling_convention describes stack locations as ideal slots on
7576 // a frame with no abi restrictions. Since we must observe abi restrictions
7577 // (like the placement of the register window) the slots must be biased by
7578 // the following value.
7579 static int reg2offset_in(VMReg r) {
7580 // Account for saved rfp and lr
7581 // This should really be in_preserve_stack_slots
7582 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
7583 }
7584
7585 static int reg2offset_out(VMReg r) {
7586 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
7587 }
7588
7589 // On 64bit we will store integer like items to the stack as
7590 // 64bits items (AArch64 ABI) even though java would only store
7591 // 32bits for a parameter. On 32bit it will simply be 32bits
7592 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
7593 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
7594 if (src.first()->is_stack()) {
7595 if (dst.first()->is_stack()) {
7596 // stack to stack
7597 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7598 str(tmp, Address(sp, reg2offset_out(dst.first())));
7599 } else {
7600 // stack to reg
7601 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
7602 }
7603 } else if (dst.first()->is_stack()) {
7604 // reg to stack
7605 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
7606 } else {
7607 if (dst.first() != src.first()) {
7608 sxtw(dst.first()->as_Register(), src.first()->as_Register());
7609 }
7610 }
7611 }
7612
7613 // An oop arg. Must pass a handle not the oop itself
7614 void MacroAssembler::object_move(
7615 OopMap* map,
7616 int oop_handle_offset,
7617 int framesize_in_slots,
7618 VMRegPair src,
7619 VMRegPair dst,
7620 bool is_receiver,
7621 int* receiver_offset) {
7622
7623 // must pass a handle. First figure out the location we use as a handle
7624
7625 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register();
7626
7627 // See if oop is null if it is we need no handle
7628
7629 if (src.first()->is_stack()) {
7630
7631 // Oop is already on the stack as an argument
7632 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
7633 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
7634 if (is_receiver) {
7635 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
7636 }
7637
7638 ldr(rscratch1, Address(rfp, reg2offset_in(src.first())));
7639 lea(rHandle, Address(rfp, reg2offset_in(src.first())));
7640 // conditionally move a null
7641 cmp(rscratch1, zr);
7642 csel(rHandle, zr, rHandle, Assembler::EQ);
7643 } else {
7644
7645 // Oop is in an a register we must store it to the space we reserve
7646 // on the stack for oop_handles and pass a handle if oop is non-null
7647
7648 const Register rOop = src.first()->as_Register();
7649 int oop_slot;
7650 if (rOop == j_rarg0)
7651 oop_slot = 0;
7652 else if (rOop == j_rarg1)
7653 oop_slot = 1;
7654 else if (rOop == j_rarg2)
7655 oop_slot = 2;
7656 else if (rOop == j_rarg3)
7657 oop_slot = 3;
7658 else if (rOop == j_rarg4)
7659 oop_slot = 4;
7660 else if (rOop == j_rarg5)
7661 oop_slot = 5;
7662 else if (rOop == j_rarg6)
7663 oop_slot = 6;
7664 else {
7665 assert(rOop == j_rarg7, "wrong register");
7666 oop_slot = 7;
7667 }
7668
7669 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
7670 int offset = oop_slot*VMRegImpl::stack_slot_size;
7671
7672 map->set_oop(VMRegImpl::stack2reg(oop_slot));
7673 // Store oop in handle area, may be null
7674 str(rOop, Address(sp, offset));
7675 if (is_receiver) {
7676 *receiver_offset = offset;
7677 }
7678
7679 cmp(rOop, zr);
7680 lea(rHandle, Address(sp, offset));
7681 // conditionally move a null
7682 csel(rHandle, zr, rHandle, Assembler::EQ);
7683 }
7684
7685 // If arg is on the stack then place it otherwise it is already in correct reg.
7686 if (dst.first()->is_stack()) {
7687 str(rHandle, Address(sp, reg2offset_out(dst.first())));
7688 }
7689 }
7690
7691 // A float arg may have to do float reg int reg conversion
7692 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
7693 if (src.first()->is_stack()) {
7694 if (dst.first()->is_stack()) {
7695 ldrw(tmp, Address(rfp, reg2offset_in(src.first())));
7696 strw(tmp, Address(sp, reg2offset_out(dst.first())));
7697 } else {
7698 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7699 }
7700 } else if (src.first() != dst.first()) {
7701 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7702 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7703 else
7704 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7705 }
7706 }
7707
7708 // A long move
7709 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
7710 if (src.first()->is_stack()) {
7711 if (dst.first()->is_stack()) {
7712 // stack to stack
7713 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7714 str(tmp, Address(sp, reg2offset_out(dst.first())));
7715 } else {
7716 // stack to reg
7717 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
7718 }
7719 } else if (dst.first()->is_stack()) {
7720 // reg to stack
7721 // Do we really have to sign extend???
7722 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
7723 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
7724 } else {
7725 if (dst.first() != src.first()) {
7726 mov(dst.first()->as_Register(), src.first()->as_Register());
7727 }
7728 }
7729 }
7730
7731
7732 // A double move
7733 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
7734 if (src.first()->is_stack()) {
7735 if (dst.first()->is_stack()) {
7736 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7737 str(tmp, Address(sp, reg2offset_out(dst.first())));
7738 } else {
7739 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7740 }
7741 } else if (src.first() != dst.first()) {
7742 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7743 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7744 else
7745 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7746 }
7747 }
7748
7749 // Implements fast-locking.
7750 //
7751 // - obj: the object to be locked
7752 // - t1, t2, t3: temporary registers, will be destroyed
7753 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding).
7754 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow) {
7755 assert_different_registers(basic_lock, obj, t1, t2, t3, rscratch1);
7756
7757 Label push;
7758 const Register top = t1;
7759 const Register mark = t2;
7760 const Register t = t3;
7761
7762 // Preload the markWord. It is important that this is the first
7763 // instruction emitted as it is part of C1's null check semantics.
7764 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7765
7766 if (UseObjectMonitorTable) {
7767 // Clear cache in case fast locking succeeds or we need to take the slow-path.
7768 str(zr, Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))));
7769 }
7770
7771 if (DiagnoseSyncOnValueBasedClasses != 0) {
7772 load_klass(t1, obj);
7773 ldrb(t1, Address(t1, Klass::misc_flags_offset()));
7774 tst(t1, KlassFlags::_misc_is_value_based_class);
7775 br(Assembler::NE, slow);
7776 }
7777
7778 // Check if the lock-stack is full.
7779 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7780 cmpw(top, (unsigned)LockStack::end_offset());
7781 br(Assembler::GE, slow);
7782
7783 // Check for recursion.
7784 subw(t, top, oopSize);
7785 ldr(t, Address(rthread, t));
7786 cmp(obj, t);
7787 br(Assembler::EQ, push);
7788
7789 // Check header for monitor (0b10).
7790 tst(mark, markWord::monitor_value);
7791 br(Assembler::NE, slow);
7792
7793 // Try to lock. Transition lock bits 0b01 => 0b00
7794 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7795 orr(mark, mark, markWord::unlocked_value);
7796 // Mask inline_type bit such that we go to the slow path if object is an inline type
7797 andr(mark, mark, ~((int) markWord::inline_type_bit_in_place));
7798
7799 eor(t, mark, markWord::unlocked_value);
7800 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
7801 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
7802 br(Assembler::NE, slow);
7803
7804 bind(push);
7805 // After successful lock, push object on lock-stack.
7806 str(obj, Address(rthread, top));
7807 addw(top, top, oopSize);
7808 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7809 }
7810
7811 // Implements fast-unlocking.
7812 //
7813 // - obj: the object to be unlocked
7814 // - t1, t2, t3: temporary registers
7815 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
7816 void MacroAssembler::fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
7817 // cmpxchg clobbers rscratch1.
7818 assert_different_registers(obj, t1, t2, t3, rscratch1);
7819
7820 #ifdef ASSERT
7821 {
7822 // Check for lock-stack underflow.
7823 Label stack_ok;
7824 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
7825 cmpw(t1, (unsigned)LockStack::start_offset());
7826 br(Assembler::GE, stack_ok);
7827 STOP("Lock-stack underflow");
7828 bind(stack_ok);
7829 }
7830 #endif
7831
7832 Label unlocked, push_and_slow;
7833 const Register top = t1;
7834 const Register mark = t2;
7835 const Register t = t3;
7836
7837 // Check if obj is top of lock-stack.
7838 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7839 subw(top, top, oopSize);
7840 ldr(t, Address(rthread, top));
7841 cmp(obj, t);
7842 br(Assembler::NE, slow);
7843
7844 // Pop lock-stack.
7845 DEBUG_ONLY(str(zr, Address(rthread, top));)
7846 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7847
7848 // Check if recursive.
7849 subw(t, top, oopSize);
7850 ldr(t, Address(rthread, t));
7851 cmp(obj, t);
7852 br(Assembler::EQ, unlocked);
7853
7854 // Not recursive. Check header for monitor (0b10).
7855 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7856 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow);
7857
7858 #ifdef ASSERT
7859 // Check header not unlocked (0b01).
7860 Label not_unlocked;
7861 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked);
7862 stop("fast_unlock already unlocked");
7863 bind(not_unlocked);
7864 #endif
7865
7866 // Try to unlock. Transition lock bits 0b00 => 0b01
7867 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7868 orr(t, mark, markWord::unlocked_value);
7869 cmpxchg(obj, mark, t, Assembler::xword,
7870 /*acquire*/ false, /*release*/ true, /*weak*/ false, noreg);
7871 br(Assembler::EQ, unlocked);
7872
7873 bind(push_and_slow);
7874 // Restore lock-stack and handle the unlock in runtime.
7875 DEBUG_ONLY(str(obj, Address(rthread, top));)
7876 addw(top, top, oopSize);
7877 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7878 b(slow);
7879
7880 bind(unlocked);
7881 }