1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "cds/archiveBuilder.hpp"
29 #include "ci/ciEnv.hpp"
30 #include "ci/ciInlineKlass.hpp"
31 #include "code/compiledIC.hpp"
32 #include "compiler/compileTask.hpp"
33 #include "compiler/disassembler.hpp"
34 #include "compiler/oopMap.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/barrierSetAssembler.hpp"
37 #include "gc/shared/cardTableBarrierSet.hpp"
38 #include "gc/shared/cardTable.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/tlab_globals.hpp"
41 #include "interpreter/bytecodeHistogram.hpp"
42 #include "interpreter/interpreter.hpp"
43 #include "interpreter/interpreterRuntime.hpp"
44 #include "jvm.h"
45 #include "memory/resourceArea.hpp"
46 #include "memory/universe.hpp"
47 #include "nativeInst_aarch64.hpp"
48 #include "oops/accessDecorators.hpp"
49 #include "oops/compressedKlass.inline.hpp"
50 #include "oops/compressedOops.inline.hpp"
51 #include "oops/klass.inline.hpp"
52 #include "oops/resolvedFieldEntry.hpp"
53 #include "runtime/arguments.hpp"
54 #include "runtime/continuation.hpp"
55 #include "runtime/globals.hpp"
56 #include "runtime/icache.hpp"
57 #include "runtime/interfaceSupport.inline.hpp"
58 #include "runtime/javaThread.hpp"
59 #include "runtime/jniHandles.inline.hpp"
60 #include "runtime/sharedRuntime.hpp"
61 #include "runtime/signature_cc.hpp"
62 #include "runtime/stubRoutines.hpp"
63 #include "utilities/globalDefinitions.hpp"
64 #include "utilities/integerCast.hpp"
65 #include "utilities/powerOfTwo.hpp"
66 #include "vmreg_aarch64.inline.hpp"
67 #ifdef COMPILER1
68 #include "c1/c1_LIRAssembler.hpp"
69 #endif
70 #ifdef COMPILER2
71 #include "oops/oop.hpp"
72 #include "opto/compile.hpp"
73 #include "opto/node.hpp"
74 #include "opto/output.hpp"
75 #endif
76
77 #include <sys/types.h>
78
79 #ifdef PRODUCT
80 #define BLOCK_COMMENT(str) /* nothing */
81 #else
82 #define BLOCK_COMMENT(str) block_comment(str)
83 #endif
84 #define STOP(str) stop(str);
85 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
86
87 #ifdef ASSERT
88 extern "C" void disnm(intptr_t p);
89 #endif
90 // Target-dependent relocation processing
91 //
92 // Instruction sequences whose target may need to be retrieved or
93 // patched are distinguished by their leading instruction, sorting
94 // them into three main instruction groups and related subgroups.
95 //
96 // 1) Branch, Exception and System (insn count = 1)
97 // 1a) Unconditional branch (immediate):
98 // b/bl imm19
99 // 1b) Compare & branch (immediate):
100 // cbz/cbnz Rt imm19
101 // 1c) Test & branch (immediate):
102 // tbz/tbnz Rt imm14
103 // 1d) Conditional branch (immediate):
104 // b.cond imm19
105 //
106 // 2) Loads and Stores (insn count = 1)
107 // 2a) Load register literal:
108 // ldr Rt imm19
109 //
110 // 3) Data Processing Immediate (insn count = 2 or 3)
111 // 3a) PC-rel. addressing
112 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12
113 // adr/adrp Rx imm21; add Ry Rx #imm12
114 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page]
115 // adr/adrp Rx imm21
116 // adr/adrp Rx imm21; movk Rx #imm16<<32
117 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page
118 // The latter form can only happen when the target is an
119 // ExternalAddress, and (by definition) ExternalAddresses don't
120 // move. Because of that property, there is never any need to
121 // patch the last of the three instructions. However,
122 // MacroAssembler::target_addr_for_insn takes all three
123 // instructions into account and returns the correct address.
124 // 3b) Move wide (immediate)
125 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32;
126 //
127 // A switch on a subset of the instruction's bits provides an
128 // efficient dispatch to these subcases.
129 //
130 // insn[28:26] -> main group ('x' == don't care)
131 // 00x -> UNALLOCATED
132 // 100 -> Data Processing Immediate
133 // 101 -> Branch, Exception and System
134 // x1x -> Loads and Stores
135 //
136 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care).
137 // n.b. in some cases extra bits need to be checked to verify the
138 // instruction is as expected
139 //
140 // 1) ... xx101x Branch, Exception and System
141 // 1a) 00___x Unconditional branch (immediate)
142 // 1b) 01___0 Compare & branch (immediate)
143 // 1c) 01___1 Test & branch (immediate)
144 // 1d) 10___0 Conditional branch (immediate)
145 // other Should not happen
146 //
147 // 2) ... xxx1x0 Loads and Stores
148 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0)
149 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0)
150 // strictly should be 64 bit non-FP/SIMD i.e.
151 // 0101_000 (i.e. requires insn[31:24] == 01011000)
152 //
153 // 3) ... xx100x Data Processing Immediate
154 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0)
155 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01)
156 // strictly should be 64 bit movz #imm16<<0
157 // 110___10100 (i.e. requires insn[31:21] == 11010010100)
158 //
159
160 static uint32_t insn_at(address insn_addr, int n) {
161 return ((uint32_t*)insn_addr)[n];
162 }
163
164 template<typename T>
165 class RelocActions : public AllStatic {
166
167 public:
168
169 static int ALWAYSINLINE run(address insn_addr, address &target) {
170 int instructions = 1;
171 uint32_t insn = insn_at(insn_addr, 0);
172
173 uint32_t dispatch = Instruction_aarch64::extract(insn, 30, 25);
174 switch(dispatch) {
175 case 0b001010:
176 case 0b001011: {
177 instructions = T::unconditionalBranch(insn_addr, target);
178 break;
179 }
180 case 0b101010: // Conditional branch (immediate)
181 case 0b011010: { // Compare & branch (immediate)
182 instructions = T::conditionalBranch(insn_addr, target);
183 break;
184 }
185 case 0b011011: {
186 instructions = T::testAndBranch(insn_addr, target);
187 break;
188 }
189 case 0b001100:
190 case 0b001110:
191 case 0b011100:
192 case 0b011110:
193 case 0b101100:
194 case 0b101110:
195 case 0b111100:
196 case 0b111110: {
197 // load/store
198 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
199 // Load register (literal)
200 instructions = T::loadStore(insn_addr, target);
201 break;
202 } else {
203 // nothing to do
204 assert(target == nullptr, "did not expect to relocate target for polling page load");
205 }
206 break;
207 }
208 case 0b001000:
209 case 0b011000:
210 case 0b101000:
211 case 0b111000: {
212 // adr/adrp
213 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
214 int shift = Instruction_aarch64::extract(insn, 31, 31);
215 if (shift) {
216 uint32_t insn2 = insn_at(insn_addr, 1);
217 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
218 Instruction_aarch64::extract(insn, 4, 0) ==
219 Instruction_aarch64::extract(insn2, 9, 5)) {
220 instructions = T::adrp(insn_addr, target, T::adrpMem);
221 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
222 Instruction_aarch64::extract(insn, 4, 0) ==
223 Instruction_aarch64::extract(insn2, 4, 0)) {
224 instructions = T::adrp(insn_addr, target, T::adrpAdd);
225 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
226 Instruction_aarch64::extract(insn, 4, 0) ==
227 Instruction_aarch64::extract(insn2, 4, 0)) {
228 instructions = T::adrp(insn_addr, target, T::adrpMovk);
229 } else {
230 ShouldNotReachHere();
231 }
232 } else {
233 instructions = T::adr(insn_addr, target);
234 }
235 break;
236 }
237 case 0b001001:
238 case 0b011001:
239 case 0b101001:
240 case 0b111001: {
241 instructions = T::immediate(insn_addr, target);
242 break;
243 }
244 default: {
245 ShouldNotReachHere();
246 }
247 }
248
249 T::verify(insn_addr, target);
250 return instructions * NativeInstruction::instruction_size;
251 }
252 };
253
254 class Patcher : public AllStatic {
255 public:
256 static int unconditionalBranch(address insn_addr, address &target) {
257 intptr_t offset = (target - insn_addr) >> 2;
258 Instruction_aarch64::spatch(insn_addr, 25, 0, offset);
259 return 1;
260 }
261 static int conditionalBranch(address insn_addr, address &target) {
262 intptr_t offset = (target - insn_addr) >> 2;
263 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
264 return 1;
265 }
266 static int testAndBranch(address insn_addr, address &target) {
267 intptr_t offset = (target - insn_addr) >> 2;
268 Instruction_aarch64::spatch(insn_addr, 18, 5, offset);
269 return 1;
270 }
271 static int loadStore(address insn_addr, address &target) {
272 intptr_t offset = (target - insn_addr) >> 2;
273 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
274 return 1;
275 }
276 static int adr(address insn_addr, address &target) {
277 #ifdef ASSERT
278 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
279 #endif
280 // PC-rel. addressing
281 ptrdiff_t offset = target - insn_addr;
282 int offset_lo = offset & 3;
283 offset >>= 2;
284 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
285 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
286 return 1;
287 }
288 template<typename U>
289 static int adrp(address insn_addr, address &target, U inner) {
290 int instructions = 1;
291 #ifdef ASSERT
292 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
293 #endif
294 ptrdiff_t offset = target - insn_addr;
295 instructions = 2;
296 precond(inner != nullptr);
297 // Give the inner reloc a chance to modify the target.
298 address adjusted_target = target;
299 instructions = inner(insn_addr, adjusted_target);
300 uintptr_t pc_page = (uintptr_t)insn_addr >> 12;
301 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12;
302 offset = adr_page - pc_page;
303 int offset_lo = offset & 3;
304 offset >>= 2;
305 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
306 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
307 return instructions;
308 }
309 static int adrpMem(address insn_addr, address &target) {
310 uintptr_t dest = (uintptr_t)target;
311 int offset_lo = dest & 0xfff;
312 uint32_t insn2 = insn_at(insn_addr, 1);
313 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
314 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size);
315 guarantee(((dest >> size) << size) == dest, "misaligned target");
316 return 2;
317 }
318 static int adrpAdd(address insn_addr, address &target) {
319 uintptr_t dest = (uintptr_t)target;
320 int offset_lo = dest & 0xfff;
321 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo);
322 return 2;
323 }
324 static int adrpMovk(address insn_addr, address &target) {
325 uintptr_t dest = uintptr_t(target);
326 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32);
327 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL);
328 target = address(dest);
329 return 2;
330 }
331 static int immediate(address insn_addr, address &target) {
332 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010100, "must be");
333 uint64_t dest = (uint64_t)target;
334 // Move wide constant
335 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
336 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
337 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
338 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
339 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
340 return 3;
341 }
342 static void verify(address insn_addr, address &target) {
343 #ifdef ASSERT
344 address address_is = MacroAssembler::target_addr_for_insn(insn_addr);
345 if (!(address_is == target)) {
346 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target);
347 disnm((intptr_t)insn_addr);
348 assert(address_is == target, "should be");
349 }
350 #endif
351 }
352 };
353
354 // If insn1 and insn2 use the same register to form an address, either
355 // by an offsetted LDR or a simple ADD, return the offset. If the
356 // second instruction is an LDR, the offset may be scaled.
357 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) {
358 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
359 Instruction_aarch64::extract(insn1, 4, 0) ==
360 Instruction_aarch64::extract(insn2, 9, 5)) {
361 // Load/store register (unsigned immediate)
362 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
363 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
364 byte_offset <<= size;
365 return true;
366 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
367 Instruction_aarch64::extract(insn1, 4, 0) ==
368 Instruction_aarch64::extract(insn2, 4, 0)) {
369 // add (immediate)
370 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
371 return true;
372 }
373 return false;
374 }
375
376 class AArch64Decoder : public AllStatic {
377 public:
378
379 static int loadStore(address insn_addr, address &target) {
380 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
381 target = insn_addr + (offset << 2);
382 return 1;
383 }
384 static int unconditionalBranch(address insn_addr, address &target) {
385 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 25, 0);
386 target = insn_addr + (offset << 2);
387 return 1;
388 }
389 static int conditionalBranch(address insn_addr, address &target) {
390 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
391 target = address(((uint64_t)insn_addr + (offset << 2)));
392 return 1;
393 }
394 static int testAndBranch(address insn_addr, address &target) {
395 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 18, 5);
396 target = address(((uint64_t)insn_addr + (offset << 2)));
397 return 1;
398 }
399 static int adr(address insn_addr, address &target) {
400 // PC-rel. addressing
401 uint32_t insn = insn_at(insn_addr, 0);
402 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
403 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
404 target = address((uint64_t)insn_addr + offset);
405 return 1;
406 }
407 template<typename U>
408 static int adrp(address insn_addr, address &target, U inner) {
409 uint32_t insn = insn_at(insn_addr, 0);
410 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
411 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
412 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
413 int shift = 12;
414 offset <<= shift;
415 uint64_t target_page = ((uint64_t)insn_addr) + offset;
416 target_page &= ((uint64_t)-1) << shift;
417 target = address(target_page);
418 precond(inner != nullptr);
419 inner(insn_addr, target);
420 return 2;
421 }
422 static int adrpMem(address insn_addr, address &target) {
423 uint32_t insn2 = insn_at(insn_addr, 1);
424 // Load/store register (unsigned immediate)
425 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
426 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
427 byte_offset <<= size;
428 target += byte_offset;
429 return 2;
430 }
431 static int adrpAdd(address insn_addr, address &target) {
432 uint32_t insn2 = insn_at(insn_addr, 1);
433 // add (immediate)
434 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
435 target += byte_offset;
436 return 2;
437 }
438 static int adrpMovk(address insn_addr, address &target) {
439 uint32_t insn2 = insn_at(insn_addr, 1);
440 uint64_t dest = uint64_t(target);
441 dest = (dest & 0xffff0000ffffffff) |
442 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
443 target = address(dest);
444
445 // We know the destination 4k page. Maybe we have a third
446 // instruction.
447 uint32_t insn = insn_at(insn_addr, 0);
448 uint32_t insn3 = insn_at(insn_addr, 2);
449 ptrdiff_t byte_offset;
450 if (offset_for(insn, insn3, byte_offset)) {
451 target += byte_offset;
452 return 3;
453 } else {
454 return 2;
455 }
456 }
457 static int immediate(address insn_addr, address &target) {
458 uint32_t *insns = (uint32_t *)insn_addr;
459 assert(Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010100, "must be");
460 // Move wide constant: movz, movk, movk. See movptr().
461 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
462 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
463 target = address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5))
464 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
465 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
466 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
467 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
468 return 3;
469 }
470 static void verify(address insn_addr, address &target) {
471 }
472 };
473
474 address MacroAssembler::target_addr_for_insn(address insn_addr) {
475 address target;
476 RelocActions<AArch64Decoder>::run(insn_addr, target);
477 return target;
478 }
479
480 // Patch any kind of instruction; there may be several instructions.
481 // Return the total length (in bytes) of the instructions.
482 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) {
483 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
484 return RelocActions<Patcher>::run(insn_addr, target);
485 }
486
487 int MacroAssembler::patch_oop(address insn_addr, address o) {
488 int instructions;
489 unsigned insn = *(unsigned*)insn_addr;
490 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
491
492 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
493
494 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
495 // narrow OOPs by setting the upper 16 bits in the first
496 // instruction.
497 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
498 // Move narrow OOP
499 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
500 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
501 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
502 instructions = 2;
503 } else {
504 // Move wide OOP
505 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
506 uintptr_t dest = (uintptr_t)o;
507 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
508 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
509 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
510 instructions = 3;
511 }
512 return instructions * NativeInstruction::instruction_size;
513 }
514
515 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp) {
516 ldr(tmp, Address(rthread, JavaThread::polling_word_offset()));
517 if (at_return) {
518 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
519 // we may safely use the sp instead to perform the stack watermark check.
520 cmp(in_nmethod ? sp : rfp, tmp);
521 br(Assembler::HI, slow_path);
522 } else {
523 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path);
524 }
525 }
526
527 void MacroAssembler::rt_call(address dest, Register tmp) {
528 CodeBlob *cb = CodeCache::find_blob(dest);
529 if (cb) {
530 far_call(RuntimeAddress(dest));
531 } else {
532 lea(tmp, RuntimeAddress(dest));
533 blr(tmp);
534 }
535 }
536
537 void MacroAssembler::push_cont_fastpath(Register java_thread) {
538 if (!Continuations::enabled()) return;
539 Label done;
540 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
541 cmp(sp, rscratch1);
542 br(Assembler::LS, done);
543 mov(rscratch1, sp); // we can't use sp as the source in str
544 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
545 bind(done);
546 }
547
548 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
549 if (!Continuations::enabled()) return;
550 Label done;
551 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
552 cmp(sp, rscratch1);
553 br(Assembler::LO, done);
554 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset()));
555 bind(done);
556 }
557
558 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
559 // we must set sp to zero to clear frame
560 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
561
562 // must clear fp, so that compiled frames are not confused; it is
563 // possible that we need it only for debugging
564 if (clear_fp) {
565 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
566 }
567
568 // Always clear the pc because it could have been set by make_walkable()
569 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
570 }
571
572 // Calls to C land
573 //
574 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
575 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
576 // has to be reset to 0. This is required to allow proper stack traversal.
577 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
578 Register last_java_fp,
579 Register last_java_pc,
580 Register scratch) {
581
582 if (last_java_pc->is_valid()) {
583 str(last_java_pc, Address(rthread,
584 JavaThread::frame_anchor_offset()
585 + JavaFrameAnchor::last_Java_pc_offset()));
586 }
587
588 // determine last_java_sp register
589 if (last_java_sp == sp) {
590 mov(scratch, sp);
591 last_java_sp = scratch;
592 } else if (!last_java_sp->is_valid()) {
593 last_java_sp = esp;
594 }
595
596 // last_java_fp is optional
597 if (last_java_fp->is_valid()) {
598 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
599 }
600
601 // We must set sp last.
602 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
603 }
604
605 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
606 Register last_java_fp,
607 address last_java_pc,
608 Register scratch) {
609 assert(last_java_pc != nullptr, "must provide a valid PC");
610
611 adr(scratch, last_java_pc);
612 str(scratch, Address(rthread,
613 JavaThread::frame_anchor_offset()
614 + JavaFrameAnchor::last_Java_pc_offset()));
615
616 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
617 }
618
619 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
620 Register last_java_fp,
621 Label &L,
622 Register scratch) {
623 if (L.is_bound()) {
624 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
625 } else {
626 InstructionMark im(this);
627 L.add_patch_at(code(), locator());
628 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch);
629 }
630 }
631
632 bool MacroAssembler::target_needs_far_branch(address addr) {
633 if (AOTCodeCache::is_on_for_dump()) {
634 return true;
635 }
636 if (!far_branches()) {
637 return false;
638 }
639 if (CodeCache::is_non_nmethod(addr) &&
640 CodeCache::max_distance_to_non_nmethod() <= branch_range) {
641 return false;
642 }
643 return true;
644 }
645
646 void MacroAssembler::far_call(Address entry, Register tmp) {
647 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
648 assert(CodeCache::find_blob(entry.target()) != nullptr,
649 "destination of far call not found in code cache");
650 assert(entry.rspec().type() == relocInfo::external_word_type
651 || entry.rspec().type() == relocInfo::runtime_call_type
652 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
653 if (target_needs_far_branch(entry.target())) {
654 uint64_t offset;
655 // We can use ADRP here because we know that the total size of
656 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
657 adrp(tmp, entry, offset);
658 add(tmp, tmp, offset);
659 blr(tmp);
660 } else {
661 bl(entry);
662 }
663 }
664
665 int MacroAssembler::far_jump(Address entry, Register tmp) {
666 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
667 assert(CodeCache::find_blob(entry.target()) != nullptr,
668 "destination of far call not found in code cache");
669 assert(entry.rspec().type() == relocInfo::external_word_type
670 || entry.rspec().type() == relocInfo::runtime_call_type
671 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
672 address start = pc();
673 if (target_needs_far_branch(entry.target())) {
674 uint64_t offset;
675 // We can use ADRP here because we know that the total size of
676 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
677 adrp(tmp, entry, offset);
678 add(tmp, tmp, offset);
679 br(tmp);
680 } else {
681 b(entry);
682 }
683 return pc() - start;
684 }
685
686 void MacroAssembler::reserved_stack_check() {
687 // testing if reserved zone needs to be enabled
688 Label no_reserved_zone_enabling;
689
690 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
691 cmp(sp, rscratch1);
692 br(Assembler::LO, no_reserved_zone_enabling);
693
694 enter(); // LR and FP are live.
695 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)));
696 mov(c_rarg0, rthread);
697 blr(rscratch1);
698 leave();
699
700 // We have already removed our own frame.
701 // throw_delayed_StackOverflowError will think that it's been
702 // called by our caller.
703 lea(rscratch1, RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
704 br(rscratch1);
705 should_not_reach_here();
706
707 bind(no_reserved_zone_enabling);
708 }
709
710 static void pass_arg0(MacroAssembler* masm, Register arg) {
711 if (c_rarg0 != arg ) {
712 masm->mov(c_rarg0, arg);
713 }
714 }
715
716 static void pass_arg1(MacroAssembler* masm, Register arg) {
717 if (c_rarg1 != arg ) {
718 masm->mov(c_rarg1, arg);
719 }
720 }
721
722 static void pass_arg2(MacroAssembler* masm, Register arg) {
723 if (c_rarg2 != arg ) {
724 masm->mov(c_rarg2, arg);
725 }
726 }
727
728 static void pass_arg3(MacroAssembler* masm, Register arg) {
729 if (c_rarg3 != arg ) {
730 masm->mov(c_rarg3, arg);
731 }
732 }
733
734 void MacroAssembler::call_VM_base(Register oop_result,
735 Register java_thread,
736 Register last_java_sp,
737 Label* return_pc,
738 address entry_point,
739 int number_of_arguments,
740 bool check_exceptions) {
741 // determine java_thread register
742 if (!java_thread->is_valid()) {
743 java_thread = rthread;
744 }
745
746 // determine last_java_sp register
747 if (!last_java_sp->is_valid()) {
748 last_java_sp = esp;
749 }
750
751 // debugging support
752 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
753 assert(java_thread == rthread, "unexpected register");
754 #ifdef ASSERT
755 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
756 // if (!TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
757 #endif // ASSERT
758
759 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
760 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
761
762 // push java thread (becomes first argument of C function)
763
764 mov(c_rarg0, java_thread);
765
766 // set last Java frame before call
767 assert(last_java_sp != rfp, "can't use rfp");
768
769 Label l;
770 set_last_Java_frame(last_java_sp, rfp, return_pc != nullptr ? *return_pc : l, rscratch1);
771
772 // do the call, remove parameters
773 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
774
775 // lr could be poisoned with PAC signature during throw_pending_exception
776 // if it was tail-call optimized by compiler, since lr is not callee-saved
777 // reload it with proper value
778 adr(lr, l);
779
780 // reset last Java frame
781 // Only interpreter should have to clear fp
782 reset_last_Java_frame(true);
783
784 // C++ interp handles this in the interpreter
785 check_and_handle_popframe(java_thread);
786 check_and_handle_earlyret(java_thread);
787
788 if (check_exceptions) {
789 // check for pending exceptions (java_thread is set upon return)
790 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
791 Label ok;
792 cbz(rscratch1, ok);
793 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
794 br(rscratch1);
795 bind(ok);
796 }
797
798 // get oop result if there is one and reset the value in the thread
799 if (oop_result->is_valid()) {
800 get_vm_result_oop(oop_result, java_thread);
801 }
802 }
803
804 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
805 call_VM_base(oop_result, noreg, noreg, nullptr, entry_point, number_of_arguments, check_exceptions);
806 }
807
808 // Check the entry target is always reachable from any branch.
809 static bool is_always_within_branch_range(Address entry) {
810 if (AOTCodeCache::is_on_for_dump()) {
811 return false;
812 }
813 const address target = entry.target();
814
815 if (!CodeCache::contains(target)) {
816 // We always use trampolines for callees outside CodeCache.
817 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target");
818 return false;
819 }
820
821 if (!MacroAssembler::far_branches()) {
822 return true;
823 }
824
825 if (entry.rspec().type() == relocInfo::runtime_call_type) {
826 // Runtime calls are calls of a non-compiled method (stubs, adapters).
827 // Non-compiled methods stay forever in CodeCache.
828 // We check whether the longest possible branch is within the branch range.
829 assert(CodeCache::find_blob(target) != nullptr &&
830 !CodeCache::find_blob(target)->is_nmethod(),
831 "runtime call of compiled method");
832 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size;
833 const address left_longest_branch_start = CodeCache::low_bound();
834 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) &&
835 Assembler::reachable_from_branch_at(right_longest_branch_start, target);
836 return is_reachable;
837 }
838
839 return false;
840 }
841
842 // Maybe emit a call via a trampoline. If the code cache is small
843 // trampolines won't be emitted.
844 address MacroAssembler::trampoline_call(Address entry) {
845 assert(entry.rspec().type() == relocInfo::runtime_call_type
846 || entry.rspec().type() == relocInfo::opt_virtual_call_type
847 || entry.rspec().type() == relocInfo::static_call_type
848 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
849
850 address target = entry.target();
851
852 if (!is_always_within_branch_range(entry)) {
853 if (!in_scratch_emit_size()) {
854 // We don't want to emit a trampoline if C2 is generating dummy
855 // code during its branch shortening phase.
856 if (entry.rspec().type() == relocInfo::runtime_call_type) {
857 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs");
858 code()->share_trampoline_for(entry.target(), offset());
859 } else {
860 address stub = emit_trampoline_stub(offset(), target);
861 if (stub == nullptr) {
862 postcond(pc() == badAddress);
863 return nullptr; // CodeCache is full
864 }
865 }
866 }
867 target = pc();
868 }
869
870 address call_pc = pc();
871 relocate(entry.rspec());
872 bl(target);
873
874 postcond(pc() != badAddress);
875 return call_pc;
876 }
877
878 // Emit a trampoline stub for a call to a target which is too far away.
879 //
880 // code sequences:
881 //
882 // call-site:
883 // branch-and-link to <destination> or <trampoline stub>
884 //
885 // Related trampoline stub for this call site in the stub section:
886 // load the call target from the constant pool
887 // branch (LR still points to the call site above)
888
889 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
890 address dest) {
891 // Max stub size: alignment nop, TrampolineStub.
892 address stub = start_a_stub(max_trampoline_stub_size());
893 if (stub == nullptr) {
894 return nullptr; // CodeBuffer::expand failed
895 }
896
897 // Create a trampoline stub relocation which relates this trampoline stub
898 // with the call instruction at insts_call_instruction_offset in the
899 // instructions code-section.
900 align(wordSize);
901 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
902 + insts_call_instruction_offset));
903 const int stub_start_offset = offset();
904
905 // Now, create the trampoline stub's code:
906 // - load the call
907 // - call
908 Label target;
909 ldr(rscratch1, target);
910 br(rscratch1);
911 bind(target);
912 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
913 "should be");
914 emit_int64((int64_t)dest);
915
916 const address stub_start_addr = addr_at(stub_start_offset);
917
918 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
919
920 end_a_stub();
921 return stub_start_addr;
922 }
923
924 int MacroAssembler::max_trampoline_stub_size() {
925 // Max stub size: alignment nop, TrampolineStub.
926 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size;
927 }
928
929 void MacroAssembler::emit_static_call_stub() {
930 // CompiledDirectCall::set_to_interpreted knows the
931 // exact layout of this stub.
932
933 isb();
934 mov_metadata(rmethod, nullptr);
935
936 // Jump to the entry point of the c2i stub.
937 if (codestub_branch_needs_far_jump()) {
938 movptr(rscratch1, 0);
939 br(rscratch1);
940 } else {
941 b(pc());
942 }
943 }
944
945 int MacroAssembler::static_call_stub_size() {
946 // During AOT production run AOT and JIT compiled code
947 // are used at the same time. We need this size
948 // to be the same for both types of code.
949 if (!codestub_branch_needs_far_jump() && !AOTCodeCache::is_on_for_use()) {
950 // isb; movk; movz; movz; b
951 return 5 * NativeInstruction::instruction_size;
952 }
953 // isb; movk; movz; movz; movk; movz; movz; br
954 return 8 * NativeInstruction::instruction_size;
955 }
956
957 void MacroAssembler::c2bool(Register x) {
958 // implements x == 0 ? 0 : 1
959 // note: must only look at least-significant byte of x
960 // since C-style booleans are stored in one byte
961 // only! (was bug)
962 tst(x, 0xff);
963 cset(x, Assembler::NE);
964 }
965
966 address MacroAssembler::ic_call(address entry, jint method_index) {
967 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
968 movptr(rscratch2, (intptr_t)Universe::non_oop_word());
969 return trampoline_call(Address(entry, rh));
970 }
971
972 int MacroAssembler::ic_check_size() {
973 int extra_instructions = UseCompactObjectHeaders ? 1 : 0;
974 if (target_needs_far_branch(CAST_FROM_FN_PTR(address, SharedRuntime::get_ic_miss_stub()))) {
975 return NativeInstruction::instruction_size * (7 + extra_instructions);
976 } else {
977 return NativeInstruction::instruction_size * (5 + extra_instructions);
978 }
979 }
980
981 int MacroAssembler::ic_check(int end_alignment) {
982 Register receiver = j_rarg0;
983 Register data = rscratch2;
984 Register tmp1 = rscratch1;
985 Register tmp2 = r10;
986
987 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
988 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
989 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
990 // before the inline cache check here, and not after
991 align(end_alignment, offset() + ic_check_size());
992
993 int uep_offset = offset();
994
995 if (UseCompactObjectHeaders) {
996 load_narrow_klass_compact(tmp1, receiver);
997 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
998 cmpw(tmp1, tmp2);
999 } else {
1000 ldrw(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1001 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1002 cmpw(tmp1, tmp2);
1003 }
1004
1005 Label dont;
1006 br(Assembler::EQ, dont);
1007 far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1008 bind(dont);
1009 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1010
1011 return uep_offset;
1012 }
1013
1014 // Implementation of call_VM versions
1015
1016 void MacroAssembler::call_VM(Register oop_result,
1017 address entry_point,
1018 bool check_exceptions) {
1019 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1020 }
1021
1022 void MacroAssembler::call_VM(Register oop_result,
1023 address entry_point,
1024 Register arg_1,
1025 bool check_exceptions) {
1026 pass_arg1(this, arg_1);
1027 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1028 }
1029
1030 void MacroAssembler::call_VM(Register oop_result,
1031 address entry_point,
1032 Register arg_1,
1033 Register arg_2,
1034 bool check_exceptions) {
1035 assert_different_registers(arg_1, c_rarg2);
1036 pass_arg2(this, arg_2);
1037 pass_arg1(this, arg_1);
1038 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1039 }
1040
1041 void MacroAssembler::call_VM(Register oop_result,
1042 address entry_point,
1043 Register arg_1,
1044 Register arg_2,
1045 Register arg_3,
1046 bool check_exceptions) {
1047 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1048 assert_different_registers(arg_2, c_rarg3);
1049 pass_arg3(this, arg_3);
1050
1051 pass_arg2(this, arg_2);
1052
1053 pass_arg1(this, arg_1);
1054 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1055 }
1056
1057 void MacroAssembler::call_VM(Register oop_result,
1058 Register last_java_sp,
1059 address entry_point,
1060 int number_of_arguments,
1061 bool check_exceptions) {
1062 call_VM_base(oop_result, rthread, last_java_sp, nullptr, entry_point, number_of_arguments, check_exceptions);
1063 }
1064
1065 void MacroAssembler::call_VM(Register oop_result,
1066 Register last_java_sp,
1067 address entry_point,
1068 Register arg_1,
1069 bool check_exceptions) {
1070 pass_arg1(this, arg_1);
1071 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1072 }
1073
1074 void MacroAssembler::call_VM(Register oop_result,
1075 Register last_java_sp,
1076 address entry_point,
1077 Register arg_1,
1078 Register arg_2,
1079 bool check_exceptions) {
1080
1081 assert_different_registers(arg_1, c_rarg2);
1082 pass_arg2(this, arg_2);
1083 pass_arg1(this, arg_1);
1084 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1085 }
1086
1087 void MacroAssembler::call_VM(Register oop_result,
1088 Register last_java_sp,
1089 address entry_point,
1090 Register arg_1,
1091 Register arg_2,
1092 Register arg_3,
1093 bool check_exceptions) {
1094 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1095 assert_different_registers(arg_2, c_rarg3);
1096 pass_arg3(this, arg_3);
1097 pass_arg2(this, arg_2);
1098 pass_arg1(this, arg_1);
1099 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1100 }
1101
1102
1103 void MacroAssembler::get_vm_result_oop(Register oop_result, Register java_thread) {
1104 ldr(oop_result, Address(java_thread, JavaThread::vm_result_oop_offset()));
1105 str(zr, Address(java_thread, JavaThread::vm_result_oop_offset()));
1106 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1107 }
1108
1109 void MacroAssembler::get_vm_result_metadata(Register metadata_result, Register java_thread) {
1110 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1111 str(zr, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1112 }
1113
1114 void MacroAssembler::align(int modulus) {
1115 align(modulus, offset());
1116 }
1117
1118 // Ensure that the code at target bytes offset from the current offset() is aligned
1119 // according to modulus.
1120 void MacroAssembler::align(int modulus, int target) {
1121 int delta = target - offset();
1122 while ((offset() + delta) % modulus != 0) nop();
1123 }
1124
1125 void MacroAssembler::post_call_nop() {
1126 if (!Continuations::enabled()) {
1127 return;
1128 }
1129 InstructionMark im(this);
1130 relocate(post_call_nop_Relocation::spec());
1131 InlineSkippedInstructionsCounter skipCounter(this);
1132 nop();
1133 movk(zr, 0);
1134 movk(zr, 0);
1135 }
1136
1137 // these are no-ops overridden by InterpreterMacroAssembler
1138
1139 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1140
1141 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1142
1143 // Look up the method for a megamorphic invokeinterface call.
1144 // The target method is determined by <intf_klass, itable_index>.
1145 // The receiver klass is in recv_klass.
1146 // On success, the result will be in method_result, and execution falls through.
1147 // On failure, execution transfers to the given label.
1148 void MacroAssembler::lookup_interface_method(Register recv_klass,
1149 Register intf_klass,
1150 RegisterOrConstant itable_index,
1151 Register method_result,
1152 Register scan_temp,
1153 Label& L_no_such_interface,
1154 bool return_method) {
1155 assert_different_registers(recv_klass, intf_klass, scan_temp);
1156 assert_different_registers(method_result, intf_klass, scan_temp);
1157 assert(recv_klass != method_result || !return_method,
1158 "recv_klass can be destroyed when method isn't needed");
1159 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1160 "caller must use same register for non-constant itable index as for method");
1161
1162 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1163 int vtable_base = in_bytes(Klass::vtable_start_offset());
1164 int itentry_off = in_bytes(itableMethodEntry::method_offset());
1165 int scan_step = itableOffsetEntry::size() * wordSize;
1166 int vte_size = vtableEntry::size_in_bytes();
1167 assert(vte_size == wordSize, "else adjust times_vte_scale");
1168
1169 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1170
1171 // Could store the aligned, prescaled offset in the klass.
1172 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
1173 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
1174 add(scan_temp, scan_temp, vtable_base);
1175
1176 if (return_method) {
1177 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1178 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1179 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1180 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
1181 if (itentry_off)
1182 add(recv_klass, recv_klass, itentry_off);
1183 }
1184
1185 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
1186 // if (scan->interface() == intf) {
1187 // result = (klass + scan->offset() + itable_index);
1188 // }
1189 // }
1190 Label search, found_method;
1191
1192 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1193 cmp(intf_klass, method_result);
1194 br(Assembler::EQ, found_method);
1195 bind(search);
1196 // Check that the previous entry is non-null. A null entry means that
1197 // the receiver class doesn't implement the interface, and wasn't the
1198 // same as when the caller was compiled.
1199 cbz(method_result, L_no_such_interface);
1200 if (itableOffsetEntry::interface_offset() != 0) {
1201 add(scan_temp, scan_temp, scan_step);
1202 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1203 } else {
1204 ldr(method_result, Address(pre(scan_temp, scan_step)));
1205 }
1206 cmp(intf_klass, method_result);
1207 br(Assembler::NE, search);
1208
1209 bind(found_method);
1210
1211 // Got a hit.
1212 if (return_method) {
1213 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
1214 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1215 }
1216 }
1217
1218 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
1219 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
1220 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
1221 // The target method is determined by <holder_klass, itable_index>.
1222 // The receiver klass is in recv_klass.
1223 // On success, the result will be in method_result, and execution falls through.
1224 // On failure, execution transfers to the given label.
1225 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
1226 Register holder_klass,
1227 Register resolved_klass,
1228 Register method_result,
1229 Register temp_itbl_klass,
1230 Register scan_temp,
1231 int itable_index,
1232 Label& L_no_such_interface) {
1233 // 'method_result' is only used as output register at the very end of this method.
1234 // Until then we can reuse it as 'holder_offset'.
1235 Register holder_offset = method_result;
1236 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset);
1237
1238 int vtable_start_offset = in_bytes(Klass::vtable_start_offset());
1239 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize;
1240 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
1241 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
1242
1243 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found;
1244
1245 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1246 add(recv_klass, recv_klass, vtable_start_offset + ioffset);
1247 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len;
1248 // temp_itbl_klass = itable[0]._interface;
1249 int vtblEntrySize = vtableEntry::size_in_bytes();
1250 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3");
1251 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1252 mov(holder_offset, zr);
1253 // scan_temp = &(itable[0]._interface)
1254 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1255
1256 // Initial checks:
1257 // - if (holder_klass != resolved_klass), go to "scan for resolved"
1258 // - if (itable[0] == holder_klass), shortcut to "holder found"
1259 // - if (itable[0] == 0), no such interface
1260 cmp(resolved_klass, holder_klass);
1261 br(Assembler::NE, L_loop_search_resolved_entry);
1262 cmp(holder_klass, temp_itbl_klass);
1263 br(Assembler::EQ, L_holder_found);
1264 cbz(temp_itbl_klass, L_no_such_interface);
1265
1266 // Loop: Look for holder_klass record in itable
1267 // do {
1268 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1269 // if (temp_itbl_klass == holder_klass) {
1270 // goto L_holder_found; // Found!
1271 // }
1272 // } while (temp_itbl_klass != 0);
1273 // goto L_no_such_interface // Not found.
1274 Label L_search_holder;
1275 bind(L_search_holder);
1276 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1277 cmp(holder_klass, temp_itbl_klass);
1278 br(Assembler::EQ, L_holder_found);
1279 cbnz(temp_itbl_klass, L_search_holder);
1280
1281 b(L_no_such_interface);
1282
1283 // Loop: Look for resolved_class record in itable
1284 // while (true) {
1285 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1286 // if (temp_itbl_klass == 0) {
1287 // goto L_no_such_interface;
1288 // }
1289 // if (temp_itbl_klass == resolved_klass) {
1290 // goto L_resolved_found; // Found!
1291 // }
1292 // if (temp_itbl_klass == holder_klass) {
1293 // holder_offset = scan_temp;
1294 // }
1295 // }
1296 //
1297 Label L_loop_search_resolved;
1298 bind(L_loop_search_resolved);
1299 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1300 bind(L_loop_search_resolved_entry);
1301 cbz(temp_itbl_klass, L_no_such_interface);
1302 cmp(resolved_klass, temp_itbl_klass);
1303 br(Assembler::EQ, L_resolved_found);
1304 cmp(holder_klass, temp_itbl_klass);
1305 br(Assembler::NE, L_loop_search_resolved);
1306 mov(holder_offset, scan_temp);
1307 b(L_loop_search_resolved);
1308
1309 // See if we already have a holder klass. If not, go and scan for it.
1310 bind(L_resolved_found);
1311 cbz(holder_offset, L_search_holder);
1312 mov(scan_temp, holder_offset);
1313
1314 // Finally, scan_temp contains holder_klass vtable offset
1315 bind(L_holder_found);
1316 ldrw(method_result, Address(scan_temp, ooffset - ioffset));
1317 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset())
1318 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass
1319 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0)));
1320 }
1321
1322 // virtual method calling
1323 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1324 RegisterOrConstant vtable_index,
1325 Register method_result) {
1326 assert(vtableEntry::size() * wordSize == 8,
1327 "adjust the scaling in the code below");
1328 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset());
1329
1330 if (vtable_index.is_register()) {
1331 lea(method_result, Address(recv_klass,
1332 vtable_index.as_register(),
1333 Address::lsl(LogBytesPerWord)));
1334 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1335 } else {
1336 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1337 ldr(method_result,
1338 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1339 }
1340 }
1341
1342 void MacroAssembler::check_klass_subtype(Register sub_klass,
1343 Register super_klass,
1344 Register temp_reg,
1345 Label& L_success) {
1346 Label L_failure;
1347 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
1348 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
1349 bind(L_failure);
1350 }
1351
1352
1353 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1354 Register super_klass,
1355 Register temp_reg,
1356 Label* L_success,
1357 Label* L_failure,
1358 Label* L_slow_path,
1359 Register super_check_offset) {
1360 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset);
1361 bool must_load_sco = ! super_check_offset->is_valid();
1362 if (must_load_sco) {
1363 assert(temp_reg != noreg, "supply either a temp or a register offset");
1364 }
1365
1366 Label L_fallthrough;
1367 int label_nulls = 0;
1368 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1369 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1370 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
1371 assert(label_nulls <= 1, "at most one null in the batch");
1372
1373 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1374 Address super_check_offset_addr(super_klass, sco_offset);
1375
1376 // Hacked jmp, which may only be used just before L_fallthrough.
1377 #define final_jmp(label) \
1378 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1379 else b(label) /*omit semi*/
1380
1381 // If the pointers are equal, we are done (e.g., String[] elements).
1382 // This self-check enables sharing of secondary supertype arrays among
1383 // non-primary types such as array-of-interface. Otherwise, each such
1384 // type would need its own customized SSA.
1385 // We move this check to the front of the fast path because many
1386 // type checks are in fact trivially successful in this manner,
1387 // so we get a nicely predicted branch right at the start of the check.
1388 cmp(sub_klass, super_klass);
1389 br(Assembler::EQ, *L_success);
1390
1391 // Check the supertype display:
1392 if (must_load_sco) {
1393 ldrw(temp_reg, super_check_offset_addr);
1394 super_check_offset = temp_reg;
1395 }
1396
1397 Address super_check_addr(sub_klass, super_check_offset);
1398 ldr(rscratch1, super_check_addr);
1399 cmp(super_klass, rscratch1); // load displayed supertype
1400 br(Assembler::EQ, *L_success);
1401
1402 // This check has worked decisively for primary supers.
1403 // Secondary supers are sought in the super_cache ('super_cache_addr').
1404 // (Secondary supers are interfaces and very deeply nested subtypes.)
1405 // This works in the same check above because of a tricky aliasing
1406 // between the super_cache and the primary super display elements.
1407 // (The 'super_check_addr' can address either, as the case requires.)
1408 // Note that the cache is updated below if it does not help us find
1409 // what we need immediately.
1410 // So if it was a primary super, we can just fail immediately.
1411 // Otherwise, it's the slow path for us (no success at this point).
1412
1413 sub(rscratch1, super_check_offset, in_bytes(Klass::secondary_super_cache_offset()));
1414 if (L_failure == &L_fallthrough) {
1415 cbz(rscratch1, *L_slow_path);
1416 } else {
1417 cbnz(rscratch1, *L_failure);
1418 final_jmp(*L_slow_path);
1419 }
1420
1421 bind(L_fallthrough);
1422
1423 #undef final_jmp
1424 }
1425
1426 // These two are taken from x86, but they look generally useful
1427
1428 // scans count pointer sized words at [addr] for occurrence of value,
1429 // generic
1430 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1431 Register scratch) {
1432 Label Lloop, Lexit;
1433 cbz(count, Lexit);
1434 bind(Lloop);
1435 ldr(scratch, post(addr, wordSize));
1436 cmp(value, scratch);
1437 br(EQ, Lexit);
1438 sub(count, count, 1);
1439 cbnz(count, Lloop);
1440 bind(Lexit);
1441 }
1442
1443 // scans count 4 byte words at [addr] for occurrence of value,
1444 // generic
1445 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1446 Register scratch) {
1447 Label Lloop, Lexit;
1448 cbz(count, Lexit);
1449 bind(Lloop);
1450 ldrw(scratch, post(addr, wordSize));
1451 cmpw(value, scratch);
1452 br(EQ, Lexit);
1453 sub(count, count, 1);
1454 cbnz(count, Lloop);
1455 bind(Lexit);
1456 }
1457
1458 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
1459 Register super_klass,
1460 Register temp_reg,
1461 Register temp2_reg,
1462 Label* L_success,
1463 Label* L_failure,
1464 bool set_cond_codes) {
1465 // NB! Callers may assume that, when temp2_reg is a valid register,
1466 // this code sets it to a nonzero value.
1467
1468 assert_different_registers(sub_klass, super_klass, temp_reg);
1469 if (temp2_reg != noreg)
1470 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1471 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1472
1473 Label L_fallthrough;
1474 int label_nulls = 0;
1475 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1476 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1477 assert(label_nulls <= 1, "at most one null in the batch");
1478
1479 // a couple of useful fields in sub_klass:
1480 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1481 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1482 Address secondary_supers_addr(sub_klass, ss_offset);
1483 Address super_cache_addr( sub_klass, sc_offset);
1484
1485 BLOCK_COMMENT("check_klass_subtype_slow_path");
1486
1487 // Do a linear scan of the secondary super-klass chain.
1488 // This code is rarely used, so simplicity is a virtue here.
1489 // The repne_scan instruction uses fixed registers, which we must spill.
1490 // Don't worry too much about pre-existing connections with the input regs.
1491
1492 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1493 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1494
1495 RegSet pushed_registers;
1496 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1497 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1498
1499 if (super_klass != r0) {
1500 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1501 }
1502
1503 push(pushed_registers, sp);
1504
1505 // Get super_klass value into r0 (even if it was in r5 or r2).
1506 if (super_klass != r0) {
1507 mov(r0, super_klass);
1508 }
1509
1510 #ifndef PRODUCT
1511 incrementw(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1512 #endif //PRODUCT
1513
1514 // We will consult the secondary-super array.
1515 ldr(r5, secondary_supers_addr);
1516 // Load the array length.
1517 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1518 // Skip to start of data.
1519 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1520
1521 cmp(sp, zr); // Clear Z flag; SP is never zero
1522 // Scan R2 words at [R5] for an occurrence of R0.
1523 // Set NZ/Z based on last compare.
1524 repne_scan(r5, r0, r2, rscratch1);
1525
1526 // Unspill the temp. registers:
1527 pop(pushed_registers, sp);
1528
1529 br(Assembler::NE, *L_failure);
1530
1531 // Success. Cache the super we found and proceed in triumph.
1532
1533 if (UseSecondarySupersCache) {
1534 str(super_klass, super_cache_addr);
1535 }
1536
1537 if (L_success != &L_fallthrough) {
1538 b(*L_success);
1539 }
1540
1541 #undef IS_A_TEMP
1542
1543 bind(L_fallthrough);
1544 }
1545
1546 // If Register r is invalid, remove a new register from
1547 // available_regs, and add new register to regs_to_push.
1548 Register MacroAssembler::allocate_if_noreg(Register r,
1549 RegSetIterator<Register> &available_regs,
1550 RegSet ®s_to_push) {
1551 if (!r->is_valid()) {
1552 r = *available_regs++;
1553 regs_to_push += r;
1554 }
1555 return r;
1556 }
1557
1558 // check_klass_subtype_slow_path_table() looks for super_klass in the
1559 // hash table belonging to super_klass, branching to L_success or
1560 // L_failure as appropriate. This is essentially a shim which
1561 // allocates registers as necessary then calls
1562 // lookup_secondary_supers_table() to do the work. Any of the temp
1563 // regs may be noreg, in which case this logic will chooses some
1564 // registers push and pop them from the stack.
1565 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
1566 Register super_klass,
1567 Register temp_reg,
1568 Register temp2_reg,
1569 Register temp3_reg,
1570 Register result_reg,
1571 FloatRegister vtemp,
1572 Label* L_success,
1573 Label* L_failure,
1574 bool set_cond_codes) {
1575 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
1576
1577 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1578
1579 Label L_fallthrough;
1580 int label_nulls = 0;
1581 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1582 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1583 assert(label_nulls <= 1, "at most one null in the batch");
1584
1585 BLOCK_COMMENT("check_klass_subtype_slow_path");
1586
1587 RegSetIterator<Register> available_regs
1588 = (RegSet::range(r0, r15) - temps - sub_klass - super_klass).begin();
1589
1590 RegSet pushed_regs;
1591
1592 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
1593 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
1594 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
1595 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
1596
1597 push(pushed_regs, sp);
1598
1599 lookup_secondary_supers_table_var(sub_klass,
1600 super_klass,
1601 temp_reg, temp2_reg, temp3_reg, vtemp, result_reg,
1602 nullptr);
1603 cmp(result_reg, zr);
1604
1605 // Unspill the temp. registers:
1606 pop(pushed_regs, sp);
1607
1608 // NB! Callers may assume that, when set_cond_codes is true, this
1609 // code sets temp2_reg to a nonzero value.
1610 if (set_cond_codes) {
1611 mov(temp2_reg, 1);
1612 }
1613
1614 br(Assembler::NE, *L_failure);
1615
1616 if (L_success != &L_fallthrough) {
1617 b(*L_success);
1618 }
1619
1620 bind(L_fallthrough);
1621 }
1622
1623 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1624 Register super_klass,
1625 Register temp_reg,
1626 Register temp2_reg,
1627 Label* L_success,
1628 Label* L_failure,
1629 bool set_cond_codes) {
1630 if (UseSecondarySupersTable) {
1631 check_klass_subtype_slow_path_table
1632 (sub_klass, super_klass, temp_reg, temp2_reg, /*temp3*/noreg, /*result*/noreg,
1633 /*vtemp*/fnoreg,
1634 L_success, L_failure, set_cond_codes);
1635 } else {
1636 check_klass_subtype_slow_path_linear
1637 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
1638 }
1639 }
1640
1641
1642 // Ensure that the inline code and the stub are using the same registers.
1643 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
1644 do { \
1645 assert(r_super_klass == r0 && \
1646 r_array_base == r1 && \
1647 r_array_length == r2 && \
1648 (r_array_index == r3 || r_array_index == noreg) && \
1649 (r_sub_klass == r4 || r_sub_klass == noreg) && \
1650 (r_bitmap == rscratch2 || r_bitmap == noreg) && \
1651 (result == r5 || result == noreg), "registers must match aarch64.ad"); \
1652 } while(0)
1653
1654 bool MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
1655 Register r_super_klass,
1656 Register temp1,
1657 Register temp2,
1658 Register temp3,
1659 FloatRegister vtemp,
1660 Register result,
1661 u1 super_klass_slot,
1662 bool stub_is_near) {
1663 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1664
1665 Label L_fallthrough;
1666
1667 BLOCK_COMMENT("lookup_secondary_supers_table {");
1668
1669 const Register
1670 r_array_base = temp1, // r1
1671 r_array_length = temp2, // r2
1672 r_array_index = temp3, // r3
1673 r_bitmap = rscratch2;
1674
1675 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1676
1677 u1 bit = super_klass_slot;
1678
1679 // Make sure that result is nonzero if the TBZ below misses.
1680 mov(result, 1);
1681
1682 // We're going to need the bitmap in a vector reg and in a core reg,
1683 // so load both now.
1684 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1685 if (bit != 0) {
1686 ldrd(vtemp, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1687 }
1688 // First check the bitmap to see if super_klass might be present. If
1689 // the bit is zero, we are certain that super_klass is not one of
1690 // the secondary supers.
1691 tbz(r_bitmap, bit, L_fallthrough);
1692
1693 // Get the first array index that can contain super_klass into r_array_index.
1694 if (bit != 0) {
1695 shld(vtemp, vtemp, Klass::SECONDARY_SUPERS_TABLE_MASK - bit);
1696 cnt(vtemp, T8B, vtemp);
1697 addv(vtemp, T8B, vtemp);
1698 fmovd(r_array_index, vtemp);
1699 } else {
1700 mov(r_array_index, (u1)1);
1701 }
1702 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1703
1704 // We will consult the secondary-super array.
1705 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1706
1707 // The value i in r_array_index is >= 1, so even though r_array_base
1708 // points to the length, we don't need to adjust it to point to the
1709 // data.
1710 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1711 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1712
1713 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1714 eor(result, result, r_super_klass);
1715 cbz(result, L_fallthrough); // Found a match
1716
1717 // Is there another entry to check? Consult the bitmap.
1718 tbz(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK, L_fallthrough);
1719
1720 // Linear probe.
1721 if (bit != 0) {
1722 ror(r_bitmap, r_bitmap, bit);
1723 }
1724
1725 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1726 // The next slot to be inspected, by the stub we're about to call,
1727 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1728 // have been checked.
1729 Address stub = RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub());
1730 if (stub_is_near) {
1731 bl(stub);
1732 } else {
1733 address call = trampoline_call(stub);
1734 if (call == nullptr) {
1735 return false; // trampoline allocation failed
1736 }
1737 }
1738
1739 BLOCK_COMMENT("} lookup_secondary_supers_table");
1740
1741 bind(L_fallthrough);
1742
1743 if (VerifySecondarySupers) {
1744 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1745 temp1, temp2, result); // r1, r2, r5
1746 }
1747 return true;
1748 }
1749
1750 // At runtime, return 0 in result if r_super_klass is a superclass of
1751 // r_sub_klass, otherwise return nonzero. Use this version of
1752 // lookup_secondary_supers_table() if you don't know ahead of time
1753 // which superclass will be searched for. Used by interpreter and
1754 // runtime stubs. It is larger and has somewhat greater latency than
1755 // the version above, which takes a constant super_klass_slot.
1756 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
1757 Register r_super_klass,
1758 Register temp1,
1759 Register temp2,
1760 Register temp3,
1761 FloatRegister vtemp,
1762 Register result,
1763 Label *L_success) {
1764 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1765
1766 Label L_fallthrough;
1767
1768 BLOCK_COMMENT("lookup_secondary_supers_table {");
1769
1770 const Register
1771 r_array_index = temp3,
1772 slot = rscratch1,
1773 r_bitmap = rscratch2;
1774
1775 ldrb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
1776
1777 // Make sure that result is nonzero if the test below misses.
1778 mov(result, 1);
1779
1780 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1781
1782 // First check the bitmap to see if super_klass might be present. If
1783 // the bit is zero, we are certain that super_klass is not one of
1784 // the secondary supers.
1785
1786 // This next instruction is equivalent to:
1787 // mov(tmp_reg, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1788 // sub(temp2, tmp_reg, slot);
1789 eor(temp2, slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1790 lslv(temp2, r_bitmap, temp2);
1791 tbz(temp2, Klass::SECONDARY_SUPERS_TABLE_SIZE - 1, L_fallthrough);
1792
1793 bool must_save_v0 = (vtemp == fnoreg);
1794 if (must_save_v0) {
1795 // temp1 and result are free, so use them to preserve vtemp
1796 vtemp = v0;
1797 mov(temp1, vtemp, D, 0);
1798 mov(result, vtemp, D, 1);
1799 }
1800
1801 // Get the first array index that can contain super_klass into r_array_index.
1802 mov(vtemp, D, 0, temp2);
1803 cnt(vtemp, T8B, vtemp);
1804 addv(vtemp, T8B, vtemp);
1805 mov(r_array_index, vtemp, D, 0);
1806
1807 if (must_save_v0) {
1808 mov(vtemp, D, 0, temp1 );
1809 mov(vtemp, D, 1, result);
1810 }
1811
1812 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1813
1814 const Register
1815 r_array_base = temp1,
1816 r_array_length = temp2;
1817
1818 // The value i in r_array_index is >= 1, so even though r_array_base
1819 // points to the length, we don't need to adjust it to point to the
1820 // data.
1821 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1822 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1823
1824 // We will consult the secondary-super array.
1825 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1826
1827 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1828 eor(result, result, r_super_klass);
1829 cbz(result, L_success ? *L_success : L_fallthrough); // Found a match
1830
1831 // Is there another entry to check? Consult the bitmap.
1832 rorv(r_bitmap, r_bitmap, slot);
1833 // rol(r_bitmap, r_bitmap, 1);
1834 tbz(r_bitmap, 1, L_fallthrough);
1835
1836 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1837 // The next slot to be inspected, by the logic we're about to call,
1838 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1839 // have been checked.
1840 lookup_secondary_supers_table_slow_path(r_super_klass, r_array_base, r_array_index,
1841 r_bitmap, r_array_length, result, /*is_stub*/false);
1842
1843 BLOCK_COMMENT("} lookup_secondary_supers_table");
1844
1845 bind(L_fallthrough);
1846
1847 if (VerifySecondarySupers) {
1848 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1849 temp1, temp2, result); // r1, r2, r5
1850 }
1851
1852 if (L_success) {
1853 cbz(result, *L_success);
1854 }
1855 }
1856
1857 // Called by code generated by check_klass_subtype_slow_path
1858 // above. This is called when there is a collision in the hashed
1859 // lookup in the secondary supers array.
1860 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
1861 Register r_array_base,
1862 Register r_array_index,
1863 Register r_bitmap,
1864 Register temp1,
1865 Register result,
1866 bool is_stub) {
1867 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, result, rscratch1);
1868
1869 const Register
1870 r_array_length = temp1,
1871 r_sub_klass = noreg; // unused
1872
1873 if (is_stub) {
1874 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1875 }
1876
1877 Label L_fallthrough, L_huge;
1878
1879 // Load the array length.
1880 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1881 // And adjust the array base to point to the data.
1882 // NB! Effectively increments current slot index by 1.
1883 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
1884 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1885
1886 // The bitmap is full to bursting.
1887 // Implicit invariant: BITMAP_FULL implies (length > 0)
1888 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
1889 cmpw(r_array_length, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 2));
1890 br(GT, L_huge);
1891
1892 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
1893 // current slot (at secondary_supers[r_array_index]) has not yet
1894 // been inspected, and r_array_index may be out of bounds if we
1895 // wrapped around the end of the array.
1896
1897 { // This is conventional linear probing, but instead of terminating
1898 // when a null entry is found in the table, we maintain a bitmap
1899 // in which a 0 indicates missing entries.
1900 // As long as the bitmap is not completely full,
1901 // array_length == popcount(bitmap). The array_length check above
1902 // guarantees there are 0s in the bitmap, so the loop eventually
1903 // terminates.
1904 Label L_loop;
1905 bind(L_loop);
1906
1907 // Check for wraparound.
1908 cmp(r_array_index, r_array_length);
1909 csel(r_array_index, zr, r_array_index, GE);
1910
1911 ldr(rscratch1, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1912 eor(result, rscratch1, r_super_klass);
1913 cbz(result, L_fallthrough);
1914
1915 tbz(r_bitmap, 2, L_fallthrough); // look-ahead check (Bit 2); result is non-zero
1916
1917 ror(r_bitmap, r_bitmap, 1);
1918 add(r_array_index, r_array_index, 1);
1919 b(L_loop);
1920 }
1921
1922 { // Degenerate case: more than 64 secondary supers.
1923 // FIXME: We could do something smarter here, maybe a vectorized
1924 // comparison or a binary search, but is that worth any added
1925 // complexity?
1926 bind(L_huge);
1927 cmp(sp, zr); // Clear Z flag; SP is never zero
1928 repne_scan(r_array_base, r_super_klass, r_array_length, rscratch1);
1929 cset(result, NE); // result == 0 iff we got a match.
1930 }
1931
1932 bind(L_fallthrough);
1933 }
1934
1935 // Make sure that the hashed lookup and a linear scan agree.
1936 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
1937 Register r_super_klass,
1938 Register temp1,
1939 Register temp2,
1940 Register result) {
1941 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, result, rscratch1);
1942
1943 const Register
1944 r_array_base = temp1,
1945 r_array_length = temp2;
1946
1947 BLOCK_COMMENT("verify_secondary_supers_table {");
1948
1949 // We will consult the secondary-super array.
1950 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1951
1952 // Load the array length.
1953 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1954 // And adjust the array base to point to the data.
1955 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1956
1957 cmp(sp, zr); // Clear Z flag; SP is never zero
1958 // Scan R2 words at [R5] for an occurrence of R0.
1959 // Set NZ/Z based on last compare.
1960 repne_scan(/*addr*/r_array_base, /*value*/r_super_klass, /*count*/r_array_length, rscratch2);
1961 // rscratch1 == 0 iff we got a match.
1962 cset(rscratch1, NE);
1963
1964 Label passed;
1965 cmp(result, zr);
1966 cset(result, NE); // normalize result to 0/1 for comparison
1967
1968 cmp(rscratch1, result);
1969 br(EQ, passed);
1970 {
1971 mov(r0, r_super_klass); // r0 <- r0
1972 mov(r1, r_sub_klass); // r1 <- r4
1973 mov(r2, /*expected*/rscratch1); // r2 <- r8
1974 mov(r3, result); // r3 <- r5
1975 mov(r4, (address)("mismatch")); // r4 <- const
1976 rt_call(CAST_FROM_FN_PTR(address, Klass::on_secondary_supers_verification_failure), rscratch2);
1977 should_not_reach_here();
1978 }
1979 bind(passed);
1980
1981 BLOCK_COMMENT("} verify_secondary_supers_table");
1982 }
1983
1984 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) {
1985 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
1986 assert_different_registers(klass, rthread, scratch);
1987
1988 Label L_fallthrough, L_tmp;
1989 if (L_fast_path == nullptr) {
1990 L_fast_path = &L_fallthrough;
1991 } else if (L_slow_path == nullptr) {
1992 L_slow_path = &L_fallthrough;
1993 }
1994 // Fast path check: class is fully initialized
1995 lea(scratch, Address(klass, InstanceKlass::init_state_offset()));
1996 ldarb(scratch, scratch);
1997 cmp(scratch, InstanceKlass::fully_initialized);
1998 br(Assembler::EQ, *L_fast_path);
1999
2000 // Fast path check: current thread is initializer thread
2001 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
2002 cmp(rthread, scratch);
2003
2004 if (L_slow_path == &L_fallthrough) {
2005 br(Assembler::EQ, *L_fast_path);
2006 bind(*L_slow_path);
2007 } else if (L_fast_path == &L_fallthrough) {
2008 br(Assembler::NE, *L_slow_path);
2009 bind(*L_fast_path);
2010 } else {
2011 Unimplemented();
2012 }
2013 }
2014
2015 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
2016 if (!VerifyOops || VerifyAdapterSharing) {
2017 // Below address of the code string confuses VerifyAdapterSharing
2018 // because it may differ between otherwise equivalent adapters.
2019 return;
2020 }
2021
2022 // Pass register number to verify_oop_subroutine
2023 const char* b = nullptr;
2024 {
2025 ResourceMark rm;
2026 stringStream ss;
2027 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
2028 b = code_string(ss.as_string());
2029 }
2030 BLOCK_COMMENT("verify_oop {");
2031
2032 strip_return_address(); // This might happen within a stack frame.
2033 protect_return_address();
2034 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2035 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2036
2037 mov(r0, reg);
2038 movptr(rscratch1, (uintptr_t)(address)b);
2039
2040 // call indirectly to solve generation ordering problem
2041 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2042 ldr(rscratch2, Address(rscratch2));
2043 blr(rscratch2);
2044
2045 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2046 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2047 authenticate_return_address();
2048
2049 BLOCK_COMMENT("} verify_oop");
2050 }
2051
2052 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
2053 if (!VerifyOops || VerifyAdapterSharing) {
2054 // Below address of the code string confuses VerifyAdapterSharing
2055 // because it may differ between otherwise equivalent adapters.
2056 return;
2057 }
2058
2059 const char* b = nullptr;
2060 {
2061 ResourceMark rm;
2062 stringStream ss;
2063 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
2064 b = code_string(ss.as_string());
2065 }
2066 BLOCK_COMMENT("verify_oop_addr {");
2067
2068 strip_return_address(); // This might happen within a stack frame.
2069 protect_return_address();
2070 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2071 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2072
2073 // addr may contain sp so we will have to adjust it based on the
2074 // pushes that we just did.
2075 if (addr.uses(sp)) {
2076 lea(r0, addr);
2077 ldr(r0, Address(r0, 4 * wordSize));
2078 } else {
2079 ldr(r0, addr);
2080 }
2081 movptr(rscratch1, (uintptr_t)(address)b);
2082
2083 // call indirectly to solve generation ordering problem
2084 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2085 ldr(rscratch2, Address(rscratch2));
2086 blr(rscratch2);
2087
2088 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2089 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2090 authenticate_return_address();
2091
2092 BLOCK_COMMENT("} verify_oop_addr");
2093 }
2094
2095 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
2096 int extra_slot_offset) {
2097 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2098 int stackElementSize = Interpreter::stackElementSize;
2099 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
2100 #ifdef ASSERT
2101 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
2102 assert(offset1 - offset == stackElementSize, "correct arithmetic");
2103 #endif
2104 if (arg_slot.is_constant()) {
2105 return Address(esp, arg_slot.as_constant() * stackElementSize
2106 + offset);
2107 } else {
2108 add(rscratch1, esp, arg_slot.as_register(),
2109 ext::uxtx, exact_log2(stackElementSize));
2110 return Address(rscratch1, offset);
2111 }
2112 }
2113
2114 // Handle the receiver type profile update given the "recv" klass.
2115 //
2116 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
2117 // If there are no matching or claimable receiver entries in RD, updates
2118 // the polymorphic counter.
2119 //
2120 // This code expected to run by either the interpreter or JIT-ed code, without
2121 // extra synchronization. For safety, receiver cells are claimed atomically, which
2122 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
2123 // counter updates are not atomic.
2124 //
2125 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
2126 assert_different_registers(recv, mdp, rscratch1, rscratch2);
2127
2128 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
2129 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
2130 int poly_count_offset = in_bytes(CounterData::count_offset());
2131 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
2132 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
2133
2134 // Adjust for MDP offsets.
2135 base_receiver_offset += mdp_offset;
2136 end_receiver_offset += mdp_offset;
2137 poly_count_offset += mdp_offset;
2138
2139 #ifdef ASSERT
2140 // We are about to walk the MDO slots without asking for offsets.
2141 // Check that our math hits all the right spots.
2142 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
2143 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
2144 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
2145 int offset = base_receiver_offset + receiver_step*c;
2146 int count_offset = offset + receiver_to_count_step;
2147 assert(offset == real_recv_offset, "receiver slot math");
2148 assert(count_offset == real_count_offset, "receiver count math");
2149 }
2150 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
2151 assert(poly_count_offset == real_poly_count_offset, "poly counter math");
2152 #endif
2153
2154 // Corner case: no profile table. Increment poly counter and exit.
2155 if (ReceiverTypeData::row_limit() == 0) {
2156 increment(Address(mdp, poly_count_offset), DataLayout::counter_increment);
2157 return;
2158 }
2159
2160 Register offset = rscratch2;
2161
2162 Label L_loop_search_receiver, L_loop_search_empty;
2163 Label L_restart, L_found_recv, L_found_empty, L_count_update;
2164
2165 // The code here recognizes three major cases:
2166 // A. Fastest: receiver found in the table
2167 // B. Fast: no receiver in the table, and the table is full
2168 // C. Slow: no receiver in the table, free slots in the table
2169 //
2170 // The case A performance is most important, as perfectly-behaved code would end up
2171 // there, especially with larger TypeProfileWidth. The case B performance is
2172 // important as well, this is where bulk of code would land for normally megamorphic
2173 // cases. The case C performance is not essential, its job is to deal with installation
2174 // races, we optimize for code density instead. Case C needs to make sure that receiver
2175 // rows are only claimed once. This makes sure we never overwrite a row for another
2176 // receiver and never duplicate the receivers in the list, making profile type-accurate.
2177 //
2178 // It is very tempting to handle these cases in a single loop, and claim the first slot
2179 // without checking the rest of the table. But, profiling code should tolerate free slots
2180 // in the table, as class unloading can clear them. After such cleanup, the receiver
2181 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
2182 // to complete, before trying to install new slots. Splitting the code in several tight
2183 // loops also helpfully optimizes for cases A and B.
2184 //
2185 // This code is effectively:
2186 //
2187 // restart:
2188 // // Fastest: receiver is already installed
2189 // for (i = 0; i < receiver_count(); i++) {
2190 // if (receiver(i) == recv) goto found_recv(i);
2191 // }
2192 //
2193 // // Fast: no receiver, but profile is not full
2194 // for (i = 0; i < receiver_count(); i++) {
2195 // if (receiver(i) == null) goto found_null(i);
2196 // }
2197 //
2198 // // Slow: profile is full, polymorphic case
2199 // count++;
2200 // return
2201 //
2202 // // Slow: try to install receiver
2203 // found_null(i):
2204 // CAS(&receiver(i), null, recv);
2205 // goto restart
2206 //
2207 // found_recv(i):
2208 // *receiver_count(i)++
2209 //
2210
2211 bind(L_restart);
2212
2213 // Fastest: receiver is already installed
2214 mov(offset, base_receiver_offset);
2215 bind(L_loop_search_receiver);
2216 ldr(rscratch1, Address(mdp, offset));
2217 cmp(rscratch1, recv);
2218 br(Assembler::EQ, L_found_recv);
2219 add(offset, offset, receiver_step);
2220 sub(rscratch1, offset, end_receiver_offset);
2221 cbnz(rscratch1, L_loop_search_receiver);
2222
2223 // Fast: no receiver, but profile is not full
2224 mov(offset, base_receiver_offset);
2225 bind(L_loop_search_empty);
2226 ldr(rscratch1, Address(mdp, offset));
2227 cbz(rscratch1, L_found_empty);
2228 add(offset, offset, receiver_step);
2229 sub(rscratch1, offset, end_receiver_offset);
2230 cbnz(rscratch1, L_loop_search_empty);
2231
2232 // Slow: Receiver is not found and table is full.
2233 // Increment polymorphic counter instead of receiver slot.
2234 mov(offset, poly_count_offset);
2235 b(L_count_update);
2236
2237 // Slowest: try to install receiver
2238 bind(L_found_empty);
2239
2240 // Atomically swing receiver slot: null -> recv.
2241 //
2242 // The update uses CAS, which clobbers rscratch1. Therefore, rscratch2
2243 // is used to hold the destination address. This is safe because the
2244 // offset is no longer needed after the address is computed.
2245
2246 lea(rscratch2, Address(mdp, offset));
2247 cmpxchg_weak(/*addr*/ rscratch2, /*expected*/ zr, /*new*/ recv, Assembler::xword, memory_order_relaxed);
2248
2249 // CAS success means the slot now has the receiver we want. CAS failure means
2250 // something had claimed the slot concurrently: it can be the same receiver we want,
2251 // or something else. Since this is a slow path, we can optimize for code density,
2252 // and just restart the search from the beginning.
2253 b(L_restart);
2254
2255 // Found a receiver, convert its slot offset to corresponding count offset.
2256 bind(L_found_recv);
2257 add(offset, offset, receiver_to_count_step);
2258
2259 // Finally, update the counter
2260 bind(L_count_update);
2261 increment(Address(mdp, offset), DataLayout::counter_increment);
2262 }
2263
2264
2265 void MacroAssembler::call_VM_leaf_base(address entry_point,
2266 int number_of_arguments,
2267 Label *retaddr) {
2268 Label E, L;
2269
2270 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
2271
2272 mov(rscratch1, RuntimeAddress(entry_point));
2273 blr(rscratch1);
2274 if (retaddr)
2275 bind(*retaddr);
2276
2277 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
2278 }
2279
2280 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2281 call_VM_leaf_base(entry_point, number_of_arguments);
2282 }
2283
2284 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2285 pass_arg0(this, arg_0);
2286 call_VM_leaf_base(entry_point, 1);
2287 }
2288
2289 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2290 assert_different_registers(arg_1, c_rarg0);
2291 pass_arg0(this, arg_0);
2292 pass_arg1(this, arg_1);
2293 call_VM_leaf_base(entry_point, 2);
2294 }
2295
2296 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2297 Register arg_1, Register arg_2) {
2298 assert_different_registers(arg_1, c_rarg0);
2299 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2300 pass_arg0(this, arg_0);
2301 pass_arg1(this, arg_1);
2302 pass_arg2(this, arg_2);
2303 call_VM_leaf_base(entry_point, 3);
2304 }
2305
2306 void MacroAssembler::super_call_VM_leaf(address entry_point) {
2307 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2308 }
2309
2310 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2311 pass_arg0(this, arg_0);
2312 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2313 }
2314
2315 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2316
2317 assert_different_registers(arg_0, c_rarg1);
2318 pass_arg1(this, arg_1);
2319 pass_arg0(this, arg_0);
2320 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2321 }
2322
2323 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2324 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2325 assert_different_registers(arg_1, c_rarg2);
2326 pass_arg2(this, arg_2);
2327 pass_arg1(this, arg_1);
2328 pass_arg0(this, arg_0);
2329 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2330 }
2331
2332 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2333 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
2334 assert_different_registers(arg_1, c_rarg2, c_rarg3);
2335 assert_different_registers(arg_2, c_rarg3);
2336 pass_arg3(this, arg_3);
2337 pass_arg2(this, arg_2);
2338 pass_arg1(this, arg_1);
2339 pass_arg0(this, arg_0);
2340 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2341 }
2342
2343 void MacroAssembler::null_check(Register reg, int offset) {
2344 if (needs_explicit_null_check(offset)) {
2345 // provoke OS null exception if reg is null by
2346 // accessing M[reg] w/o changing any registers
2347 // NOTE: this is plenty to provoke a segv
2348 ldr(zr, Address(reg));
2349 } else {
2350 // nothing to do, (later) access of M[reg + offset]
2351 // will provoke OS null exception if reg is null
2352 }
2353 }
2354
2355 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2356 assert_different_registers(markword, rscratch2);
2357 mov(rscratch2, markWord::inline_type_pattern_mask);
2358 andr(markword, markword, rscratch2);
2359 mov(rscratch2, markWord::inline_type_pattern);
2360 cmp(markword, rscratch2);
2361 br(Assembler::EQ, is_inline_type);
2362 }
2363
2364 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null) {
2365 assert_different_registers(tmp, rscratch1);
2366 if (can_be_null) {
2367 cbz(object, not_inline_type);
2368 }
2369 const int is_inline_type_mask = markWord::inline_type_pattern;
2370 ldr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2371 mov(rscratch1, is_inline_type_mask);
2372 andr(tmp, tmp, rscratch1);
2373 cmp(tmp, rscratch1);
2374 br(Assembler::NE, not_inline_type);
2375 }
2376
2377 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2378 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2379 tbnz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, is_null_free_inline_type);
2380 }
2381
2382 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2383 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2384 tbz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, not_null_free_inline_type);
2385 }
2386
2387 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2388 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2389 tbnz(flags, ResolvedFieldEntry::is_flat_shift, is_flat);
2390 }
2391
2392 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2393 // load mark word
2394 ldr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2395 if (!UseObjectMonitorTable) {
2396 Label test_mark_word;
2397 // check displaced
2398 tst(temp_reg, markWord::unlocked_value);
2399 br(Assembler::NE, test_mark_word);
2400 // slow path use klass prototype
2401 load_prototype_header(temp_reg, oop);
2402
2403 bind(test_mark_word);
2404 }
2405 andr(temp_reg, temp_reg, test_bit);
2406 if (jmp_set) {
2407 cbnz(temp_reg, jmp_label);
2408 } else {
2409 cbz(temp_reg, jmp_label);
2410 }
2411 }
2412
2413 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array) {
2414 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2415 }
2416
2417 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2418 Label&is_non_flat_array) {
2419 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2420 }
2421
2422 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array) {
2423 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2424 }
2425
2426 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2427 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2428 }
2429
2430 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2431 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2432 br(Assembler::NE, is_flat_array);
2433 }
2434
2435 // MacroAssembler protected routines needed to implement
2436 // public methods
2437
2438 void MacroAssembler::mov(Register r, Address dest) {
2439 code_section()->relocate(pc(), dest.rspec());
2440 uint64_t imm64 = (uint64_t)dest.target();
2441 movptr(r, imm64);
2442 }
2443
2444 // Move a constant pointer into r. In AArch64 mode the virtual
2445 // address space is 48 bits in size, so we only need three
2446 // instructions to create a patchable instruction sequence that can
2447 // reach anywhere.
2448 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2449 #ifndef PRODUCT
2450 {
2451 char buffer[64];
2452 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2453 block_comment(buffer);
2454 }
2455 #endif
2456 assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
2457 movz(r, imm64 & 0xffff);
2458 imm64 >>= 16;
2459 movk(r, imm64 & 0xffff, 16);
2460 imm64 >>= 16;
2461 movk(r, imm64 & 0xffff, 32);
2462 }
2463
2464 // Macro to mov replicated immediate to vector register.
2465 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is,
2466 // the upper 56/48/32 bits must be zeros for B/H/S type.
2467 // Vd will get the following values for different arrangements in T
2468 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh
2469 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
2470 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh
2471 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
2472 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
2473 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
2474 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh
2475 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh
2476 // Clobbers rscratch1
2477 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) {
2478 assert(T != T1Q, "unsupported");
2479 if (T == T1D || T == T2D) {
2480 int imm = operand_valid_for_movi_immediate(imm64, T);
2481 if (-1 != imm) {
2482 movi(Vd, T, imm);
2483 } else {
2484 mov(rscratch1, imm64);
2485 dup(Vd, T, rscratch1);
2486 }
2487 return;
2488 }
2489
2490 #ifdef ASSERT
2491 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)");
2492 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)");
2493 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)");
2494 #endif
2495 int shift = operand_valid_for_movi_immediate(imm64, T);
2496 uint32_t imm32 = imm64 & 0xffffffffULL;
2497 if (shift >= 0) {
2498 movi(Vd, T, (imm32 >> shift) & 0xff, shift);
2499 } else {
2500 movw(rscratch1, imm32);
2501 dup(Vd, T, rscratch1);
2502 }
2503 }
2504
2505 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
2506 {
2507 #ifndef PRODUCT
2508 {
2509 char buffer[64];
2510 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, imm64);
2511 block_comment(buffer);
2512 }
2513 #endif
2514 if (operand_valid_for_logical_immediate(false, imm64)) {
2515 orr(dst, zr, imm64);
2516 } else {
2517 // we can use a combination of MOVZ or MOVN with
2518 // MOVK to build up the constant
2519 uint64_t imm_h[4];
2520 int zero_count = 0;
2521 int neg_count = 0;
2522 int i;
2523 for (i = 0; i < 4; i++) {
2524 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
2525 if (imm_h[i] == 0) {
2526 zero_count++;
2527 } else if (imm_h[i] == 0xffffL) {
2528 neg_count++;
2529 }
2530 }
2531 if (zero_count == 4) {
2532 // one MOVZ will do
2533 movz(dst, 0);
2534 } else if (neg_count == 4) {
2535 // one MOVN will do
2536 movn(dst, 0);
2537 } else if (zero_count == 3) {
2538 for (i = 0; i < 4; i++) {
2539 if (imm_h[i] != 0L) {
2540 movz(dst, (uint32_t)imm_h[i], (i << 4));
2541 break;
2542 }
2543 }
2544 } else if (neg_count == 3) {
2545 // one MOVN will do
2546 for (int i = 0; i < 4; i++) {
2547 if (imm_h[i] != 0xffffL) {
2548 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2549 break;
2550 }
2551 }
2552 } else if (zero_count == 2) {
2553 // one MOVZ and one MOVK will do
2554 for (i = 0; i < 3; i++) {
2555 if (imm_h[i] != 0L) {
2556 movz(dst, (uint32_t)imm_h[i], (i << 4));
2557 i++;
2558 break;
2559 }
2560 }
2561 for (;i < 4; i++) {
2562 if (imm_h[i] != 0L) {
2563 movk(dst, (uint32_t)imm_h[i], (i << 4));
2564 }
2565 }
2566 } else if (neg_count == 2) {
2567 // one MOVN and one MOVK will do
2568 for (i = 0; i < 4; i++) {
2569 if (imm_h[i] != 0xffffL) {
2570 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2571 i++;
2572 break;
2573 }
2574 }
2575 for (;i < 4; i++) {
2576 if (imm_h[i] != 0xffffL) {
2577 movk(dst, (uint32_t)imm_h[i], (i << 4));
2578 }
2579 }
2580 } else if (zero_count == 1) {
2581 // one MOVZ and two MOVKs will do
2582 for (i = 0; i < 4; i++) {
2583 if (imm_h[i] != 0L) {
2584 movz(dst, (uint32_t)imm_h[i], (i << 4));
2585 i++;
2586 break;
2587 }
2588 }
2589 for (;i < 4; i++) {
2590 if (imm_h[i] != 0x0L) {
2591 movk(dst, (uint32_t)imm_h[i], (i << 4));
2592 }
2593 }
2594 } else if (neg_count == 1) {
2595 // one MOVN and two MOVKs will do
2596 for (i = 0; i < 4; i++) {
2597 if (imm_h[i] != 0xffffL) {
2598 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2599 i++;
2600 break;
2601 }
2602 }
2603 for (;i < 4; i++) {
2604 if (imm_h[i] != 0xffffL) {
2605 movk(dst, (uint32_t)imm_h[i], (i << 4));
2606 }
2607 }
2608 } else {
2609 // use a MOVZ and 3 MOVKs (makes it easier to debug)
2610 movz(dst, (uint32_t)imm_h[0], 0);
2611 for (i = 1; i < 4; i++) {
2612 movk(dst, (uint32_t)imm_h[i], (i << 4));
2613 }
2614 }
2615 }
2616 }
2617
2618 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
2619 {
2620 #ifndef PRODUCT
2621 {
2622 char buffer[64];
2623 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX32, imm32);
2624 block_comment(buffer);
2625 }
2626 #endif
2627 if (operand_valid_for_logical_immediate(true, imm32)) {
2628 orrw(dst, zr, imm32);
2629 } else {
2630 // we can use MOVZ, MOVN or two calls to MOVK to build up the
2631 // constant
2632 uint32_t imm_h[2];
2633 imm_h[0] = imm32 & 0xffff;
2634 imm_h[1] = ((imm32 >> 16) & 0xffff);
2635 if (imm_h[0] == 0) {
2636 movzw(dst, imm_h[1], 16);
2637 } else if (imm_h[0] == 0xffff) {
2638 movnw(dst, imm_h[1] ^ 0xffff, 16);
2639 } else if (imm_h[1] == 0) {
2640 movzw(dst, imm_h[0], 0);
2641 } else if (imm_h[1] == 0xffff) {
2642 movnw(dst, imm_h[0] ^ 0xffff, 0);
2643 } else {
2644 // use a MOVZ and MOVK (makes it easier to debug)
2645 movzw(dst, imm_h[0], 0);
2646 movkw(dst, imm_h[1], 16);
2647 }
2648 }
2649 }
2650
2651 // Form an address from base + offset in Rd. Rd may or may
2652 // not actually be used: you must use the Address that is returned.
2653 // It is up to you to ensure that the shift provided matches the size
2654 // of your data.
2655 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
2656 if (Address::offset_ok_for_immed(byte_offset, shift))
2657 // It fits; no need for any heroics
2658 return Address(base, byte_offset);
2659
2660 // Don't do anything clever with negative or misaligned offsets
2661 unsigned mask = (1 << shift) - 1;
2662 if (byte_offset < 0 || byte_offset & mask) {
2663 mov(Rd, byte_offset);
2664 add(Rd, base, Rd);
2665 return Address(Rd);
2666 }
2667
2668 // See if we can do this with two 12-bit offsets
2669 {
2670 uint64_t word_offset = byte_offset >> shift;
2671 uint64_t masked_offset = word_offset & 0xfff000;
2672 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
2673 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
2674 add(Rd, base, masked_offset << shift);
2675 word_offset -= masked_offset;
2676 return Address(Rd, word_offset << shift);
2677 }
2678 }
2679
2680 // Do it the hard way
2681 mov(Rd, byte_offset);
2682 add(Rd, base, Rd);
2683 return Address(Rd);
2684 }
2685
2686 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
2687 bool want_remainder, Register scratch)
2688 {
2689 // Full implementation of Java idiv and irem. The function
2690 // returns the (pc) offset of the div instruction - may be needed
2691 // for implicit exceptions.
2692 //
2693 // constraint : ra/rb =/= scratch
2694 // normal case
2695 //
2696 // input : ra: dividend
2697 // rb: divisor
2698 //
2699 // result: either
2700 // quotient (= ra idiv rb)
2701 // remainder (= ra irem rb)
2702
2703 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2704
2705 int idivl_offset = offset();
2706 if (! want_remainder) {
2707 sdivw(result, ra, rb);
2708 } else {
2709 sdivw(scratch, ra, rb);
2710 Assembler::msubw(result, scratch, rb, ra);
2711 }
2712
2713 return idivl_offset;
2714 }
2715
2716 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
2717 bool want_remainder, Register scratch)
2718 {
2719 // Full implementation of Java ldiv and lrem. The function
2720 // returns the (pc) offset of the div instruction - may be needed
2721 // for implicit exceptions.
2722 //
2723 // constraint : ra/rb =/= scratch
2724 // normal case
2725 //
2726 // input : ra: dividend
2727 // rb: divisor
2728 //
2729 // result: either
2730 // quotient (= ra idiv rb)
2731 // remainder (= ra irem rb)
2732
2733 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2734
2735 int idivq_offset = offset();
2736 if (! want_remainder) {
2737 sdiv(result, ra, rb);
2738 } else {
2739 sdiv(scratch, ra, rb);
2740 Assembler::msub(result, scratch, rb, ra);
2741 }
2742
2743 return idivq_offset;
2744 }
2745
2746 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
2747 address prev = pc() - NativeMembar::instruction_size;
2748 address last = code()->last_merge_candidate();
2749 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) {
2750 NativeMembar *bar = NativeMembar_at(prev);
2751 if (AlwaysMergeDMB) {
2752 bar->set_kind(bar->get_kind() | order_constraint);
2753 BLOCK_COMMENT("merged membar(always)");
2754 return;
2755 }
2756 // Don't promote DMB ST|DMB LD to DMB (a full barrier) because
2757 // doing so would introduce a StoreLoad which the caller did not
2758 // intend
2759 if (bar->get_kind() == order_constraint
2760 || bar->get_kind() == AnyAny
2761 || order_constraint == AnyAny) {
2762 // We are merging two memory barrier instructions. On AArch64 we
2763 // can do this simply by ORing them together.
2764 bar->set_kind(bar->get_kind() | order_constraint);
2765 BLOCK_COMMENT("merged membar");
2766 return;
2767 } else {
2768 // A special case like "DMB ST;DMB LD;DMB ST", the last DMB can be skipped.
2769 // We need to check the second-to-last instruction, only if it is inside
2770 // the current code section.
2771 address prev2 = prev - NativeMembar::instruction_size;
2772 if (prev2 >= begin() && last != code()->last_label() && nativeInstruction_at(prev2)->is_Membar()) {
2773 NativeMembar *bar2 = NativeMembar_at(prev2);
2774 assert(bar2->get_kind() == order_constraint, "it should be merged before");
2775 BLOCK_COMMENT("merged membar(elided)");
2776 return;
2777 }
2778 }
2779 }
2780 code()->set_last_merge_candidate(pc());
2781 dmb(Assembler::barrier(order_constraint));
2782 }
2783
2784 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
2785 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
2786 merge_ldst(rt, adr, size_in_bytes, is_store);
2787 code()->clear_last_merge_candidate();
2788 return true;
2789 } else {
2790 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
2791 const uint64_t mask = size_in_bytes - 1;
2792 if (adr.getMode() == Address::base_plus_offset &&
2793 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
2794 code()->set_last_merge_candidate(pc());
2795 }
2796 return false;
2797 }
2798 }
2799
2800 void MacroAssembler::ldr(Register Rx, const Address &adr) {
2801 // We always try to merge two adjacent loads into one ldp.
2802 if (!try_merge_ldst(Rx, adr, 8, false)) {
2803 Assembler::ldr(Rx, adr);
2804 }
2805 }
2806
2807 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
2808 // We always try to merge two adjacent loads into one ldp.
2809 if (!try_merge_ldst(Rw, adr, 4, false)) {
2810 Assembler::ldrw(Rw, adr);
2811 }
2812 }
2813
2814 void MacroAssembler::str(Register Rx, const Address &adr) {
2815 // We always try to merge two adjacent stores into one stp.
2816 if (!try_merge_ldst(Rx, adr, 8, true)) {
2817 Assembler::str(Rx, adr);
2818 }
2819 }
2820
2821 void MacroAssembler::strw(Register Rw, const Address &adr) {
2822 // We always try to merge two adjacent stores into one stp.
2823 if (!try_merge_ldst(Rw, adr, 4, true)) {
2824 Assembler::strw(Rw, adr);
2825 }
2826 }
2827
2828 // MacroAssembler routines found actually to be needed
2829
2830 void MacroAssembler::push(Register src)
2831 {
2832 str(src, Address(pre(esp, -1 * wordSize)));
2833 }
2834
2835 void MacroAssembler::pop(Register dst)
2836 {
2837 ldr(dst, Address(post(esp, 1 * wordSize)));
2838 }
2839
2840 // Note: load_unsigned_short used to be called load_unsigned_word.
2841 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2842 int off = offset();
2843 ldrh(dst, src);
2844 return off;
2845 }
2846
2847 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2848 int off = offset();
2849 ldrb(dst, src);
2850 return off;
2851 }
2852
2853 int MacroAssembler::load_signed_short(Register dst, Address src) {
2854 int off = offset();
2855 ldrsh(dst, src);
2856 return off;
2857 }
2858
2859 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2860 int off = offset();
2861 ldrsb(dst, src);
2862 return off;
2863 }
2864
2865 int MacroAssembler::load_signed_short32(Register dst, Address src) {
2866 int off = offset();
2867 ldrshw(dst, src);
2868 return off;
2869 }
2870
2871 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
2872 int off = offset();
2873 ldrsbw(dst, src);
2874 return off;
2875 }
2876
2877 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2878 switch (size_in_bytes) {
2879 case 8: ldr(dst, src); break;
2880 case 4: ldrw(dst, src); break;
2881 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2882 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2883 default: ShouldNotReachHere();
2884 }
2885 }
2886
2887 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) {
2888 switch (size_in_bytes) {
2889 case 8: str(src, dst); break;
2890 case 4: strw(src, dst); break;
2891 case 2: strh(src, dst); break;
2892 case 1: strb(src, dst); break;
2893 default: ShouldNotReachHere();
2894 }
2895 }
2896
2897 void MacroAssembler::narrow_subword_type(Register reg, BasicType bt) {
2898 assert(is_subword_type(bt), "required");
2899 switch (bt) {
2900 case T_BOOLEAN: andw(reg, reg, 1); break;
2901 case T_BYTE: sxtbw(reg, reg); break;
2902 case T_CHAR: uxthw(reg, reg); break;
2903 case T_SHORT: sxthw(reg, reg); break;
2904 default: ShouldNotReachHere();
2905 }
2906 }
2907
2908 void MacroAssembler::decrementw(Register reg, int value)
2909 {
2910 if (value < 0) { incrementw(reg, -value); return; }
2911 if (value == 0) { return; }
2912 if (value < (1 << 24)) { subw(reg, reg, value); return; }
2913 /* else */ {
2914 guarantee(reg != rscratch2, "invalid dst for register decrement");
2915 movw(rscratch2, (unsigned)value);
2916 subw(reg, reg, rscratch2);
2917 }
2918 }
2919
2920 void MacroAssembler::decrement(Register reg, int value)
2921 {
2922 if (value < 0) { increment(reg, -value); return; }
2923 if (value == 0) { return; }
2924 if (value < (1 << 24)) { sub(reg, reg, value); return; }
2925 /* else */ {
2926 assert(reg != rscratch2, "invalid dst for register decrement");
2927 mov(rscratch2, (uint64_t)value);
2928 sub(reg, reg, rscratch2);
2929 }
2930 }
2931
2932 void MacroAssembler::decrementw(Address dst, int value)
2933 {
2934 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
2935 if (dst.getMode() == Address::literal) {
2936 assert(abs(value) < (1 << 24), "invalid value and address mode combination");
2937 lea(rscratch2, dst);
2938 dst = Address(rscratch2);
2939 }
2940 ldrw(rscratch1, dst);
2941 decrementw(rscratch1, value);
2942 strw(rscratch1, dst);
2943 }
2944
2945 void MacroAssembler::decrement(Address dst, int value)
2946 {
2947 assert(!dst.uses(rscratch1), "invalid address for decrement");
2948 if (dst.getMode() == Address::literal) {
2949 assert(abs(value) < (1 << 24), "invalid value and address mode combination");
2950 lea(rscratch2, dst);
2951 dst = Address(rscratch2);
2952 }
2953 ldr(rscratch1, dst);
2954 decrement(rscratch1, value);
2955 str(rscratch1, dst);
2956 }
2957
2958 void MacroAssembler::incrementw(Register reg, int value)
2959 {
2960 if (value < 0) { decrementw(reg, -value); return; }
2961 if (value == 0) { return; }
2962 if (value < (1 << 24)) { addw(reg, reg, value); return; }
2963 /* else */ {
2964 assert(reg != rscratch2, "invalid dst for register increment");
2965 movw(rscratch2, (unsigned)value);
2966 addw(reg, reg, rscratch2);
2967 }
2968 }
2969
2970 void MacroAssembler::increment(Register reg, int value)
2971 {
2972 if (value < 0) { decrement(reg, -value); return; }
2973 if (value == 0) { return; }
2974 if (value < (1 << 24)) { add(reg, reg, value); return; }
2975 /* else */ {
2976 assert(reg != rscratch2, "invalid dst for register increment");
2977 movw(rscratch2, (unsigned)value);
2978 add(reg, reg, rscratch2);
2979 }
2980 }
2981
2982 void MacroAssembler::incrementw(Address dst, int value, Register result)
2983 {
2984 assert(!dst.uses(result), "invalid dst for address increment");
2985 assert(result->is_valid(), "must be");
2986 assert_different_registers(result, rscratch2);
2987 if (dst.getMode() == Address::literal) {
2988 assert(abs(value) < (1 << 24), "invalid value and address mode combination");
2989 lea(rscratch2, dst);
2990 dst = Address(rscratch2);
2991 }
2992 ldrw(result, dst);
2993 incrementw(result, value);
2994 strw(result, dst);
2995 }
2996
2997 void MacroAssembler::increment(Address dst, int value, Register result)
2998 {
2999 assert(!dst.uses(result), "invalid dst for address increment");
3000 assert(result->is_valid(), "must be");
3001 assert_different_registers(result, rscratch2);
3002 if (dst.getMode() == Address::literal) {
3003 assert(abs(value) < (1 << 24), "invalid value and address mode combination");
3004 lea(rscratch2, dst);
3005 dst = Address(rscratch2);
3006 }
3007 ldr(result, dst);
3008 increment(result, value);
3009 str(result, dst);
3010 }
3011
3012 // Push lots of registers in the bit set supplied. Don't push sp.
3013 // Return the number of words pushed
3014 int MacroAssembler::push(RegSet regset, Register stack) {
3015 if (regset.bits() == 0) {
3016 return 0;
3017 }
3018 auto bitset = integer_cast<unsigned int>(regset.bits());
3019 int words_pushed = 0;
3020
3021 // Scan bitset to accumulate register pairs
3022 unsigned char regs[32];
3023 int count = 0;
3024 for (int reg = 0; reg <= 30; reg++) {
3025 if (1 & bitset)
3026 regs[count++] = reg;
3027 bitset >>= 1;
3028 }
3029 regs[count++] = zr->raw_encoding();
3030 count &= ~1; // Only push an even number of regs
3031
3032 if (count) {
3033 stp(as_Register(regs[0]), as_Register(regs[1]),
3034 Address(pre(stack, -count * wordSize)));
3035 words_pushed += 2;
3036 }
3037 for (int i = 2; i < count; i += 2) {
3038 stp(as_Register(regs[i]), as_Register(regs[i+1]),
3039 Address(stack, i * wordSize));
3040 words_pushed += 2;
3041 }
3042
3043 assert(words_pushed == count, "oops, pushed != count");
3044
3045 return count;
3046 }
3047
3048 int MacroAssembler::pop(RegSet regset, Register stack) {
3049 if (regset.bits() == 0) {
3050 return 0;
3051 }
3052 auto bitset = integer_cast<unsigned int>(regset.bits());
3053 int words_pushed = 0;
3054
3055 // Scan bitset to accumulate register pairs
3056 unsigned char regs[32];
3057 int count = 0;
3058 for (int reg = 0; reg <= 30; reg++) {
3059 if (1 & bitset)
3060 regs[count++] = reg;
3061 bitset >>= 1;
3062 }
3063 regs[count++] = zr->raw_encoding();
3064 count &= ~1;
3065
3066 for (int i = 2; i < count; i += 2) {
3067 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
3068 Address(stack, i * wordSize));
3069 words_pushed += 2;
3070 }
3071 if (count) {
3072 ldp(as_Register(regs[0]), as_Register(regs[1]),
3073 Address(post(stack, count * wordSize)));
3074 words_pushed += 2;
3075 }
3076
3077 assert(words_pushed == count, "oops, pushed != count");
3078
3079 return count;
3080 }
3081
3082 // Push lots of registers in the bit set supplied. Don't push sp.
3083 // Return the number of dwords pushed
3084 int MacroAssembler::push_fp(FloatRegSet regset, Register stack, FpPushPopMode mode) {
3085 if (regset.bits() == 0) {
3086 return 0;
3087 }
3088 auto bitset = integer_cast<unsigned int>(regset.bits());
3089 int words_pushed = 0;
3090 bool use_sve = false;
3091 int sve_vector_size_in_bytes = 0;
3092
3093 #ifdef COMPILER2
3094 use_sve = Matcher::supports_scalable_vector();
3095 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
3096 #endif
3097
3098 // Scan bitset to accumulate register pairs
3099 unsigned char regs[32];
3100 int count = 0;
3101 for (int reg = 0; reg <= 31; reg++) {
3102 if (1 & bitset)
3103 regs[count++] = reg;
3104 bitset >>= 1;
3105 }
3106
3107 if (count == 0) {
3108 return 0;
3109 }
3110
3111 if (mode == PushPopFull) {
3112 if (use_sve && sve_vector_size_in_bytes > 16) {
3113 mode = PushPopSVE;
3114 } else {
3115 mode = PushPopNeon;
3116 }
3117 }
3118
3119 #ifndef PRODUCT
3120 {
3121 char buffer[48];
3122 if (mode == PushPopSVE) {
3123 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d SVE registers", count);
3124 } else if (mode == PushPopNeon) {
3125 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d Neon registers", count);
3126 } else {
3127 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d fp registers", count);
3128 }
3129 block_comment(buffer);
3130 }
3131 #endif
3132
3133 if (mode == PushPopSVE) {
3134 sub(stack, stack, sve_vector_size_in_bytes * count);
3135 for (int i = 0; i < count; i++) {
3136 sve_str(as_FloatRegister(regs[i]), Address(stack, i));
3137 }
3138 return count * sve_vector_size_in_bytes / 8;
3139 }
3140
3141 if (mode == PushPopNeon) {
3142 if (count == 1) {
3143 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2)));
3144 return 2;
3145 }
3146
3147 bool odd = (count & 1) == 1;
3148 int push_slots = count + (odd ? 1 : 0);
3149
3150 // Always pushing full 128 bit registers.
3151 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2)));
3152 words_pushed += 2;
3153
3154 for (int i = 2; i + 1 < count; i += 2) {
3155 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3156 words_pushed += 2;
3157 }
3158
3159 if (odd) {
3160 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3161 words_pushed++;
3162 }
3163
3164 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3165 return count * 2;
3166 }
3167
3168 if (mode == PushPopFp) {
3169 bool odd = (count & 1) == 1;
3170 int push_slots = count + (odd ? 1 : 0);
3171
3172 if (count == 1) {
3173 // Stack pointer must be 16 bytes aligned
3174 strd(as_FloatRegister(regs[0]), Address(pre(stack, -push_slots * wordSize)));
3175 return 1;
3176 }
3177
3178 stpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize)));
3179 words_pushed += 2;
3180
3181 for (int i = 2; i + 1 < count; i += 2) {
3182 stpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3183 words_pushed += 2;
3184 }
3185
3186 if (odd) {
3187 // Stack pointer must be 16 bytes aligned
3188 strd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3189 words_pushed++;
3190 }
3191
3192 assert(words_pushed == count, "oops, pushed != count");
3193
3194 return count;
3195 }
3196
3197 return 0;
3198 }
3199
3200 // Return the number of dwords popped
3201 int MacroAssembler::pop_fp(FloatRegSet regset, Register stack, FpPushPopMode mode) {
3202 if (regset.bits() == 0) {
3203 return 0;
3204 }
3205 auto bitset = integer_cast<unsigned int>(regset.bits());
3206 int words_pushed = 0;
3207 bool use_sve = false;
3208 int sve_vector_size_in_bytes = 0;
3209
3210 #ifdef COMPILER2
3211 use_sve = Matcher::supports_scalable_vector();
3212 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
3213 #endif
3214 // Scan bitset to accumulate register pairs
3215 unsigned char regs[32];
3216 int count = 0;
3217 for (int reg = 0; reg <= 31; reg++) {
3218 if (1 & bitset)
3219 regs[count++] = reg;
3220 bitset >>= 1;
3221 }
3222
3223 if (count == 0) {
3224 return 0;
3225 }
3226
3227 if (mode == PushPopFull) {
3228 if (use_sve && sve_vector_size_in_bytes > 16) {
3229 mode = PushPopSVE;
3230 } else {
3231 mode = PushPopNeon;
3232 }
3233 }
3234
3235 #ifndef PRODUCT
3236 {
3237 char buffer[48];
3238 if (mode == PushPopSVE) {
3239 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d SVE registers", count);
3240 } else if (mode == PushPopNeon) {
3241 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d Neon registers", count);
3242 } else {
3243 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d fp registers", count);
3244 }
3245 block_comment(buffer);
3246 }
3247 #endif
3248
3249 if (mode == PushPopSVE) {
3250 for (int i = count - 1; i >= 0; i--) {
3251 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i));
3252 }
3253 add(stack, stack, sve_vector_size_in_bytes * count);
3254 return count * sve_vector_size_in_bytes / 8;
3255 }
3256
3257 if (mode == PushPopNeon) {
3258 if (count == 1) {
3259 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2)));
3260 return 2;
3261 }
3262
3263 bool odd = (count & 1) == 1;
3264 int push_slots = count + (odd ? 1 : 0);
3265
3266 if (odd) {
3267 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3268 words_pushed++;
3269 }
3270
3271 for (int i = 2; i + 1 < count; i += 2) {
3272 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3273 words_pushed += 2;
3274 }
3275
3276 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2)));
3277 words_pushed += 2;
3278
3279 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3280
3281 return count * 2;
3282 }
3283
3284 if (mode == PushPopFp) {
3285 bool odd = (count & 1) == 1;
3286 int push_slots = count + (odd ? 1 : 0);
3287
3288 if (count == 1) {
3289 ldrd(as_FloatRegister(regs[0]), Address(post(stack, push_slots * wordSize)));
3290 return 1;
3291 }
3292
3293 if (odd) {
3294 ldrd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3295 words_pushed++;
3296 }
3297
3298 for (int i = 2; i + 1 < count; i += 2) {
3299 ldpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3300 words_pushed += 2;
3301 }
3302
3303 ldpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize)));
3304 words_pushed += 2;
3305
3306 assert(words_pushed == count, "oops, pushed != count");
3307
3308 return count;
3309 }
3310
3311 return 0;
3312 }
3313
3314 // Return the number of dwords pushed
3315 int MacroAssembler::push_p(PRegSet regset, Register stack) {
3316 if (regset.bits() == 0) {
3317 return 0;
3318 }
3319 auto bitset = integer_cast<unsigned int>(regset.bits());
3320 bool use_sve = false;
3321 int sve_predicate_size_in_slots = 0;
3322
3323 #ifdef COMPILER2
3324 use_sve = Matcher::supports_scalable_vector();
3325 if (use_sve) {
3326 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3327 }
3328 #endif
3329
3330 if (!use_sve) {
3331 return 0;
3332 }
3333
3334 unsigned char regs[PRegister::number_of_registers];
3335 int count = 0;
3336 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3337 if (1 & bitset)
3338 regs[count++] = reg;
3339 bitset >>= 1;
3340 }
3341
3342 if (count == 0) {
3343 return 0;
3344 }
3345
3346 int total_push_bytes = align_up(sve_predicate_size_in_slots *
3347 VMRegImpl::stack_slot_size * count, 16);
3348 sub(stack, stack, total_push_bytes);
3349 for (int i = 0; i < count; i++) {
3350 sve_str(as_PRegister(regs[i]), Address(stack, i));
3351 }
3352 return total_push_bytes / 8;
3353 }
3354
3355 // Return the number of dwords popped
3356 int MacroAssembler::pop_p(PRegSet regset, Register stack) {
3357 if (regset.bits() == 0) {
3358 return 0;
3359 }
3360 auto bitset = integer_cast<unsigned int>(regset.bits());
3361 bool use_sve = false;
3362 int sve_predicate_size_in_slots = 0;
3363
3364 #ifdef COMPILER2
3365 use_sve = Matcher::supports_scalable_vector();
3366 if (use_sve) {
3367 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3368 }
3369 #endif
3370
3371 if (!use_sve) {
3372 return 0;
3373 }
3374
3375 unsigned char regs[PRegister::number_of_registers];
3376 int count = 0;
3377 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3378 if (1 & bitset)
3379 regs[count++] = reg;
3380 bitset >>= 1;
3381 }
3382
3383 if (count == 0) {
3384 return 0;
3385 }
3386
3387 int total_pop_bytes = align_up(sve_predicate_size_in_slots *
3388 VMRegImpl::stack_slot_size * count, 16);
3389 for (int i = count - 1; i >= 0; i--) {
3390 sve_ldr(as_PRegister(regs[i]), Address(stack, i));
3391 }
3392 add(stack, stack, total_pop_bytes);
3393 return total_pop_bytes / 8;
3394 }
3395
3396 #ifdef ASSERT
3397 void MacroAssembler::verify_heapbase(const char* msg) {
3398 #if 0
3399 assert (Universe::heap() != nullptr, "java heap should be initialized");
3400 if (!UseCompressedOops || Universe::ptr_base() == nullptr) {
3401 // rheapbase is allocated as general register
3402 return;
3403 }
3404 if (CheckCompressedOops) {
3405 Label ok;
3406 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
3407 cmpptr(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3408 br(Assembler::EQ, ok);
3409 stop(msg);
3410 bind(ok);
3411 pop(1 << rscratch1->encoding(), sp);
3412 }
3413 #endif
3414 }
3415 #endif
3416
3417 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
3418 assert_different_registers(value, tmp1, tmp2);
3419 Label done, tagged, weak_tagged;
3420
3421 cbz(value, done); // Use null as-is.
3422 tst(value, JNIHandles::tag_mask); // Test for tag.
3423 br(Assembler::NE, tagged);
3424
3425 // Resolve local handle
3426 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2);
3427 verify_oop(value);
3428 b(done);
3429
3430 bind(tagged);
3431 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1);
3432 tbnz(value, 0, weak_tagged); // Test for weak tag.
3433
3434 // Resolve global handle
3435 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3436 verify_oop(value);
3437 b(done);
3438
3439 bind(weak_tagged);
3440 // Resolve jweak.
3441 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3442 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2);
3443 verify_oop(value);
3444
3445 bind(done);
3446 }
3447
3448 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) {
3449 assert_different_registers(value, tmp1, tmp2);
3450 Label done;
3451
3452 cbz(value, done); // Use null as-is.
3453
3454 #ifdef ASSERT
3455 {
3456 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10);
3457 Label valid_global_tag;
3458 tbnz(value, 1, valid_global_tag); // Test for global tag
3459 stop("non global jobject using resolve_global_jobject");
3460 bind(valid_global_tag);
3461 }
3462 #endif
3463
3464 // Resolve global handle
3465 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3466 verify_oop(value);
3467
3468 bind(done);
3469 }
3470
3471 void MacroAssembler::stop(const char* msg) {
3472 // Skip AOT caching C strings in scratch buffer.
3473 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
3474 BLOCK_COMMENT(str);
3475 // load msg into r0 so we can access it from the signal handler
3476 // ExternalAddress enables saving and restoring via the code cache
3477 lea(c_rarg0, ExternalAddress((address) str));
3478 dcps1(0xdeae);
3479 }
3480
3481 void MacroAssembler::unimplemented(const char* what) {
3482 const char* buf = nullptr;
3483 {
3484 ResourceMark rm;
3485 stringStream ss;
3486 ss.print("unimplemented: %s", what);
3487 buf = code_string(ss.as_string());
3488 }
3489 stop(buf);
3490 }
3491
3492 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
3493 #ifdef ASSERT
3494 Label OK;
3495 br(cc, OK);
3496 stop(msg);
3497 bind(OK);
3498 #endif
3499 }
3500
3501 // If a constant does not fit in an immediate field, generate some
3502 // number of MOV instructions and then perform the operation.
3503 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
3504 add_sub_imm_insn insn1,
3505 add_sub_reg_insn insn2,
3506 bool is32) {
3507 assert(Rd != zr, "Rd = zr and not setting flags?");
3508 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3509 if (fits) {
3510 (this->*insn1)(Rd, Rn, imm);
3511 } else {
3512 if (g_uabs(imm) < (1 << 24)) {
3513 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
3514 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
3515 } else {
3516 assert_different_registers(Rd, Rn);
3517 mov(Rd, imm);
3518 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3519 }
3520 }
3521 }
3522
3523 // Separate vsn which sets the flags. Optimisations are more restricted
3524 // because we must set the flags correctly.
3525 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
3526 add_sub_imm_insn insn1,
3527 add_sub_reg_insn insn2,
3528 bool is32) {
3529 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3530 if (fits) {
3531 (this->*insn1)(Rd, Rn, imm);
3532 } else {
3533 assert_different_registers(Rd, Rn);
3534 assert(Rd != zr, "overflow in immediate operand");
3535 mov(Rd, imm);
3536 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3537 }
3538 }
3539
3540
3541 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
3542 if (increment.is_register()) {
3543 add(Rd, Rn, increment.as_register());
3544 } else {
3545 add(Rd, Rn, increment.as_constant());
3546 }
3547 }
3548
3549 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
3550 if (increment.is_register()) {
3551 addw(Rd, Rn, increment.as_register());
3552 } else {
3553 addw(Rd, Rn, increment.as_constant());
3554 }
3555 }
3556
3557 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
3558 if (decrement.is_register()) {
3559 sub(Rd, Rn, decrement.as_register());
3560 } else {
3561 sub(Rd, Rn, decrement.as_constant());
3562 }
3563 }
3564
3565 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
3566 if (decrement.is_register()) {
3567 subw(Rd, Rn, decrement.as_register());
3568 } else {
3569 subw(Rd, Rn, decrement.as_constant());
3570 }
3571 }
3572
3573 void MacroAssembler::reinit_heapbase()
3574 {
3575 if (UseCompressedOops) {
3576 if (Universe::is_fully_initialized() && !AOTCodeCache::is_on_for_dump()) {
3577 mov(rheapbase, CompressedOops::base());
3578 } else {
3579 lea(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3580 ldr(rheapbase, Address(rheapbase));
3581 }
3582 }
3583 }
3584
3585 // A generic CAS; success or failure is in the EQ flag. A weak CAS
3586 // doesn't retry and may fail spuriously. If the oldval is wanted,
3587 // Pass a register for the result, otherwise pass noreg.
3588
3589 // Clobbers rscratch1
3590 void MacroAssembler::cmpxchg(Register addr, Register expected,
3591 Register new_val,
3592 enum operand_size size,
3593 enum atomic_memory_order order,
3594 bool weak,
3595 Register result) {
3596 bool acquire, release;
3597
3598 switch (order) {
3599 case memory_order_relaxed:
3600 acquire = false;
3601 release = false;
3602 break;
3603 case memory_order_acquire:
3604 acquire = true;
3605 release = false;
3606 break;
3607 case memory_order_release:
3608 acquire = false;
3609 release = true;
3610 break;
3611 case memory_order_acq_rel:
3612 case memory_order_seq_cst:
3613 acquire = true;
3614 release = true;
3615 break;
3616 default:
3617 ShouldNotReachHere();
3618 }
3619
3620 if (result == noreg) result = rscratch1;
3621 BLOCK_COMMENT("cmpxchg {");
3622 if (UseLSE) {
3623 mov(result, expected);
3624 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
3625 compare_eq(result, expected, size);
3626 #ifdef ASSERT
3627 // Poison rscratch1 which is written on !UseLSE branch
3628 mov(rscratch1, 0x1f1f1f1f1f1f1f1f);
3629 #endif
3630 } else {
3631 Label retry_load, done;
3632 prfm(Address(addr), PSTL1STRM);
3633 bind(retry_load);
3634 load_exclusive(result, addr, size, acquire);
3635 compare_eq(result, expected, size);
3636 br(Assembler::NE, done);
3637 store_exclusive(rscratch1, new_val, addr, size, release);
3638 if (weak) {
3639 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
3640 } else {
3641 cbnzw(rscratch1, retry_load);
3642 }
3643 bind(done);
3644 }
3645 BLOCK_COMMENT("} cmpxchg");
3646 }
3647
3648 // A generic comparison. Only compares for equality, clobbers rscratch1.
3649 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
3650 if (size == xword) {
3651 cmp(rm, rn);
3652 } else if (size == word) {
3653 cmpw(rm, rn);
3654 } else if (size == halfword) {
3655 eorw(rscratch1, rm, rn);
3656 ands(zr, rscratch1, 0xffff);
3657 } else if (size == byte) {
3658 eorw(rscratch1, rm, rn);
3659 ands(zr, rscratch1, 0xff);
3660 } else {
3661 ShouldNotReachHere();
3662 }
3663 }
3664
3665
3666 static bool different(Register a, RegisterOrConstant b, Register c) {
3667 if (b.is_constant())
3668 return a != c;
3669 else
3670 return a != b.as_register() && a != c && b.as_register() != c;
3671 }
3672
3673 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
3674 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
3675 if (UseLSE) { \
3676 prev = prev->is_valid() ? prev : zr; \
3677 if (incr.is_register()) { \
3678 AOP(sz, incr.as_register(), prev, addr); \
3679 } else { \
3680 mov(rscratch2, incr.as_constant()); \
3681 AOP(sz, rscratch2, prev, addr); \
3682 } \
3683 return; \
3684 } \
3685 Register result = rscratch2; \
3686 if (prev->is_valid()) \
3687 result = different(prev, incr, addr) ? prev : rscratch2; \
3688 \
3689 Label retry_load; \
3690 prfm(Address(addr), PSTL1STRM); \
3691 bind(retry_load); \
3692 LDXR(result, addr); \
3693 OP(rscratch1, result, incr); \
3694 STXR(rscratch2, rscratch1, addr); \
3695 cbnzw(rscratch2, retry_load); \
3696 if (prev->is_valid() && prev != result) { \
3697 IOP(prev, rscratch1, incr); \
3698 } \
3699 }
3700
3701 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
3702 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
3703 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
3704 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
3705
3706 #undef ATOMIC_OP
3707
3708 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
3709 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
3710 if (UseLSE) { \
3711 prev = prev->is_valid() ? prev : zr; \
3712 AOP(sz, newv, prev, addr); \
3713 return; \
3714 } \
3715 Register result = rscratch2; \
3716 if (prev->is_valid()) \
3717 result = different(prev, newv, addr) ? prev : rscratch2; \
3718 \
3719 Label retry_load; \
3720 prfm(Address(addr), PSTL1STRM); \
3721 bind(retry_load); \
3722 LDXR(result, addr); \
3723 STXR(rscratch1, newv, addr); \
3724 cbnzw(rscratch1, retry_load); \
3725 if (prev->is_valid() && prev != result) \
3726 mov(prev, result); \
3727 }
3728
3729 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
3730 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
3731 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
3732 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
3733 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
3734 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
3735
3736 #undef ATOMIC_XCHG
3737
3738 #ifndef PRODUCT
3739 extern "C" void findpc(intptr_t x);
3740 #endif
3741
3742 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
3743 {
3744 // In order to get locks to work, we need to fake a in_VM state
3745 if (ShowMessageBoxOnError) {
3746 JavaThread* thread = JavaThread::current();
3747 thread->set_thread_state(_thread_in_vm);
3748 #ifndef PRODUCT
3749 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
3750 ttyLocker ttyl;
3751 BytecodeCounter::print();
3752 }
3753 #endif
3754 if (os::message_box(msg, "Execution stopped, print registers?")) {
3755 ttyLocker ttyl;
3756 tty->print_cr(" pc = 0x%016" PRIx64, pc);
3757 #ifndef PRODUCT
3758 tty->cr();
3759 findpc(pc);
3760 tty->cr();
3761 #endif
3762 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
3763 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
3764 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
3765 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
3766 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
3767 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
3768 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
3769 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
3770 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
3771 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
3772 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
3773 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
3774 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
3775 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
3776 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
3777 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
3778 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
3779 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
3780 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
3781 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
3782 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
3783 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
3784 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
3785 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
3786 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
3787 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
3788 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
3789 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
3790 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
3791 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
3792 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
3793 BREAKPOINT;
3794 }
3795 }
3796 fatal("DEBUG MESSAGE: %s", msg);
3797 }
3798
3799 RegSet MacroAssembler::call_clobbered_gp_registers() {
3800 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
3801 #ifndef R18_RESERVED
3802 regs += r18_tls;
3803 #endif
3804 return regs;
3805 }
3806
3807 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
3808 int step = 4 * wordSize;
3809 push(call_clobbered_gp_registers() - exclude, sp);
3810 sub(sp, sp, step);
3811 mov(rscratch1, -step);
3812 // Push v0-v7, v16-v31.
3813 for (int i = 31; i>= 4; i -= 4) {
3814 if (i <= v7->encoding() || i >= v16->encoding())
3815 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
3816 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
3817 }
3818 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
3819 as_FloatRegister(3), T1D, Address(sp));
3820 }
3821
3822 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
3823 for (int i = 0; i < 32; i += 4) {
3824 if (i <= v7->encoding() || i >= v16->encoding())
3825 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3826 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
3827 }
3828
3829 reinitialize_ptrue();
3830
3831 pop(call_clobbered_gp_registers() - exclude, sp);
3832 }
3833
3834 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
3835 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3836 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
3837 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3838 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3839 for (int i = 0; i < FloatRegister::number_of_registers; i++) {
3840 sve_str(as_FloatRegister(i), Address(sp, i));
3841 }
3842 } else {
3843 int step = (save_vectors ? 8 : 4) * wordSize;
3844 mov(rscratch1, -step);
3845 sub(sp, sp, step);
3846 for (int i = 28; i >= 4; i -= 4) {
3847 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3848 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
3849 }
3850 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
3851 }
3852 if (save_vectors && use_sve && total_predicate_in_bytes > 0) {
3853 sub(sp, sp, total_predicate_in_bytes);
3854 for (int i = 0; i < PRegister::number_of_registers; i++) {
3855 sve_str(as_PRegister(i), Address(sp, i));
3856 }
3857 }
3858 }
3859
3860 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
3861 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3862 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) {
3863 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) {
3864 sve_ldr(as_PRegister(i), Address(sp, i));
3865 }
3866 add(sp, sp, total_predicate_in_bytes);
3867 }
3868 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3869 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) {
3870 sve_ldr(as_FloatRegister(i), Address(sp, i));
3871 }
3872 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3873 } else {
3874 int step = (restore_vectors ? 8 : 4) * wordSize;
3875 for (int i = 0; i <= 28; i += 4)
3876 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3877 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
3878 }
3879
3880 // We may use predicate registers and rely on ptrue with SVE,
3881 // regardless of wide vector (> 8 bytes) used or not.
3882 if (use_sve) {
3883 reinitialize_ptrue();
3884 }
3885
3886 // integer registers except lr & sp
3887 pop(RegSet::range(r0, r17), sp);
3888 #ifdef R18_RESERVED
3889 ldp(zr, r19, Address(post(sp, 2 * wordSize)));
3890 pop(RegSet::range(r20, r29), sp);
3891 #else
3892 pop(RegSet::range(r18_tls, r29), sp);
3893 #endif
3894 }
3895
3896 /**
3897 * Helpers for multiply_to_len().
3898 */
3899 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
3900 Register src1, Register src2) {
3901 adds(dest_lo, dest_lo, src1);
3902 adc(dest_hi, dest_hi, zr);
3903 adds(dest_lo, dest_lo, src2);
3904 adc(final_dest_hi, dest_hi, zr);
3905 }
3906
3907 // Generate an address from (r + r1 extend offset). "size" is the
3908 // size of the operand. The result may be in rscratch2.
3909 Address MacroAssembler::offsetted_address(Register r, Register r1,
3910 Address::extend ext, int offset, int size) {
3911 if (offset || (ext.shift() % size != 0)) {
3912 lea(rscratch2, Address(r, r1, ext));
3913 return Address(rscratch2, offset);
3914 } else {
3915 return Address(r, r1, ext);
3916 }
3917 }
3918
3919 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
3920 {
3921 assert(offset >= 0, "spill to negative address?");
3922 // Offset reachable ?
3923 // Not aligned - 9 bits signed offset
3924 // Aligned - 12 bits unsigned offset shifted
3925 Register base = sp;
3926 if ((offset & (size-1)) && offset >= (1<<8)) {
3927 add(tmp, base, offset & ((1<<12)-1));
3928 base = tmp;
3929 offset &= -1u<<12;
3930 }
3931
3932 if (offset >= (1<<12) * size) {
3933 add(tmp, base, offset & (((1<<12)-1)<<12));
3934 base = tmp;
3935 offset &= ~(((1<<12)-1)<<12);
3936 }
3937
3938 return Address(base, offset);
3939 }
3940
3941 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) {
3942 assert(offset >= 0, "spill to negative address?");
3943
3944 Register base = sp;
3945
3946 // An immediate offset in the range 0 to 255 which is multiplied
3947 // by the current vector or predicate register size in bytes.
3948 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) {
3949 return Address(base, offset / sve_reg_size_in_bytes);
3950 }
3951
3952 add(tmp, base, offset);
3953 return Address(tmp);
3954 }
3955
3956 // Checks whether offset is aligned.
3957 // Returns true if it is, else false.
3958 bool MacroAssembler::merge_alignment_check(Register base,
3959 size_t size,
3960 int64_t cur_offset,
3961 int64_t prev_offset) const {
3962 if (AvoidUnalignedAccesses) {
3963 if (base == sp) {
3964 // Checks whether low offset if aligned to pair of registers.
3965 int64_t pair_mask = size * 2 - 1;
3966 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3967 return (offset & pair_mask) == 0;
3968 } else { // If base is not sp, we can't guarantee the access is aligned.
3969 return false;
3970 }
3971 } else {
3972 int64_t mask = size - 1;
3973 // Load/store pair instruction only supports element size aligned offset.
3974 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
3975 }
3976 }
3977
3978 // Checks whether current and previous loads/stores can be merged.
3979 // Returns true if it can be merged, else false.
3980 bool MacroAssembler::ldst_can_merge(Register rt,
3981 const Address &adr,
3982 size_t cur_size_in_bytes,
3983 bool is_store) const {
3984 address prev = pc() - NativeInstruction::instruction_size;
3985 address last = code()->last_merge_candidate();
3986
3987 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) {
3988 return false;
3989 }
3990
3991 if (adr.getMode() != Address::base_plus_offset || prev != last) {
3992 return false;
3993 }
3994
3995 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3996 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
3997
3998 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
3999 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
4000
4001 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
4002 return false;
4003 }
4004
4005 int64_t max_offset = 63 * prev_size_in_bytes;
4006 int64_t min_offset = -64 * prev_size_in_bytes;
4007
4008 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
4009
4010 // Only same base can be merged.
4011 if (adr.base() != prev_ldst->base()) {
4012 return false;
4013 }
4014
4015 int64_t cur_offset = adr.offset();
4016 int64_t prev_offset = prev_ldst->offset();
4017 size_t diff = abs(cur_offset - prev_offset);
4018 if (diff != prev_size_in_bytes) {
4019 return false;
4020 }
4021
4022 // Following cases can not be merged:
4023 // ldr x2, [x2, #8]
4024 // ldr x3, [x2, #16]
4025 // or:
4026 // ldr x2, [x3, #8]
4027 // ldr x2, [x3, #16]
4028 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
4029 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
4030 return false;
4031 }
4032
4033 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
4034 // Offset range must be in ldp/stp instruction's range.
4035 if (low_offset > max_offset || low_offset < min_offset) {
4036 return false;
4037 }
4038
4039 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
4040 return true;
4041 }
4042
4043 return false;
4044 }
4045
4046 // Merge current load/store with previous load/store into ldp/stp.
4047 void MacroAssembler::merge_ldst(Register rt,
4048 const Address &adr,
4049 size_t cur_size_in_bytes,
4050 bool is_store) {
4051
4052 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
4053
4054 Register rt_low, rt_high;
4055 address prev = pc() - NativeInstruction::instruction_size;
4056 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
4057
4058 int64_t offset;
4059
4060 if (adr.offset() < prev_ldst->offset()) {
4061 offset = adr.offset();
4062 rt_low = rt;
4063 rt_high = prev_ldst->target();
4064 } else {
4065 offset = prev_ldst->offset();
4066 rt_low = prev_ldst->target();
4067 rt_high = rt;
4068 }
4069
4070 Address adr_p = Address(prev_ldst->base(), offset);
4071 // Overwrite previous generated binary.
4072 code_section()->set_end(prev);
4073
4074 const size_t sz = prev_ldst->size_in_bytes();
4075 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
4076 if (!is_store) {
4077 BLOCK_COMMENT("merged ldr pair");
4078 if (sz == 8) {
4079 ldp(rt_low, rt_high, adr_p);
4080 } else {
4081 ldpw(rt_low, rt_high, adr_p);
4082 }
4083 } else {
4084 BLOCK_COMMENT("merged str pair");
4085 if (sz == 8) {
4086 stp(rt_low, rt_high, adr_p);
4087 } else {
4088 stpw(rt_low, rt_high, adr_p);
4089 }
4090 }
4091 }
4092
4093 /**
4094 * Multiply 64 bit by 64 bit first loop.
4095 */
4096 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
4097 Register y, Register y_idx, Register z,
4098 Register carry, Register product,
4099 Register idx, Register kdx) {
4100 //
4101 // jlong carry, x[], y[], z[];
4102 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4103 // huge_128 product = y[idx] * x[xstart] + carry;
4104 // z[kdx] = (jlong)product;
4105 // carry = (jlong)(product >>> 64);
4106 // }
4107 // z[xstart] = carry;
4108 //
4109
4110 Label L_first_loop, L_first_loop_exit;
4111 Label L_one_x, L_one_y, L_multiply;
4112
4113 subsw(xstart, xstart, 1);
4114 br(Assembler::MI, L_one_x);
4115
4116 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
4117 ldr(x_xstart, Address(rscratch1));
4118 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
4119
4120 bind(L_first_loop);
4121 subsw(idx, idx, 1);
4122 br(Assembler::MI, L_first_loop_exit);
4123 subsw(idx, idx, 1);
4124 br(Assembler::MI, L_one_y);
4125 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4126 ldr(y_idx, Address(rscratch1));
4127 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
4128 bind(L_multiply);
4129
4130 // AArch64 has a multiply-accumulate instruction that we can't use
4131 // here because it has no way to process carries, so we have to use
4132 // separate add and adc instructions. Bah.
4133 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
4134 mul(product, x_xstart, y_idx);
4135 adds(product, product, carry);
4136 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
4137
4138 subw(kdx, kdx, 2);
4139 ror(product, product, 32); // back to big-endian
4140 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
4141
4142 b(L_first_loop);
4143
4144 bind(L_one_y);
4145 ldrw(y_idx, Address(y, 0));
4146 b(L_multiply);
4147
4148 bind(L_one_x);
4149 ldrw(x_xstart, Address(x, 0));
4150 b(L_first_loop);
4151
4152 bind(L_first_loop_exit);
4153 }
4154
4155 /**
4156 * Multiply 128 bit by 128. Unrolled inner loop.
4157 *
4158 */
4159 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
4160 Register carry, Register carry2,
4161 Register idx, Register jdx,
4162 Register yz_idx1, Register yz_idx2,
4163 Register tmp, Register tmp3, Register tmp4,
4164 Register tmp6, Register product_hi) {
4165
4166 // jlong carry, x[], y[], z[];
4167 // int kdx = ystart+1;
4168 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
4169 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
4170 // jlong carry2 = (jlong)(tmp3 >>> 64);
4171 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
4172 // carry = (jlong)(tmp4 >>> 64);
4173 // z[kdx+idx+1] = (jlong)tmp3;
4174 // z[kdx+idx] = (jlong)tmp4;
4175 // }
4176 // idx += 2;
4177 // if (idx > 0) {
4178 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
4179 // z[kdx+idx] = (jlong)yz_idx1;
4180 // carry = (jlong)(yz_idx1 >>> 64);
4181 // }
4182 //
4183
4184 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
4185
4186 lsrw(jdx, idx, 2);
4187
4188 bind(L_third_loop);
4189
4190 subsw(jdx, jdx, 1);
4191 br(Assembler::MI, L_third_loop_exit);
4192 subw(idx, idx, 4);
4193
4194 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4195
4196 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
4197
4198 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4199
4200 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
4201 ror(yz_idx2, yz_idx2, 32);
4202
4203 ldp(rscratch2, rscratch1, Address(tmp6, 0));
4204
4205 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4206 umulh(tmp4, product_hi, yz_idx1);
4207
4208 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
4209 ror(rscratch2, rscratch2, 32);
4210
4211 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
4212 umulh(carry2, product_hi, yz_idx2);
4213
4214 // propagate sum of both multiplications into carry:tmp4:tmp3
4215 adds(tmp3, tmp3, carry);
4216 adc(tmp4, tmp4, zr);
4217 adds(tmp3, tmp3, rscratch1);
4218 adcs(tmp4, tmp4, tmp);
4219 adc(carry, carry2, zr);
4220 adds(tmp4, tmp4, rscratch2);
4221 adc(carry, carry, zr);
4222
4223 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
4224 ror(tmp4, tmp4, 32);
4225 stp(tmp4, tmp3, Address(tmp6, 0));
4226
4227 b(L_third_loop);
4228 bind (L_third_loop_exit);
4229
4230 andw (idx, idx, 0x3);
4231 cbz(idx, L_post_third_loop_done);
4232
4233 Label L_check_1;
4234 subsw(idx, idx, 2);
4235 br(Assembler::MI, L_check_1);
4236
4237 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4238 ldr(yz_idx1, Address(rscratch1, 0));
4239 ror(yz_idx1, yz_idx1, 32);
4240 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4241 umulh(tmp4, product_hi, yz_idx1);
4242 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4243 ldr(yz_idx2, Address(rscratch1, 0));
4244 ror(yz_idx2, yz_idx2, 32);
4245
4246 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
4247
4248 ror(tmp3, tmp3, 32);
4249 str(tmp3, Address(rscratch1, 0));
4250
4251 bind (L_check_1);
4252
4253 andw (idx, idx, 0x1);
4254 subsw(idx, idx, 1);
4255 br(Assembler::MI, L_post_third_loop_done);
4256 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4257 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
4258 umulh(carry2, tmp4, product_hi);
4259 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4260
4261 add2_with_carry(carry2, tmp3, tmp4, carry);
4262
4263 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4264 extr(carry, carry2, tmp3, 32);
4265
4266 bind(L_post_third_loop_done);
4267 }
4268
4269 /**
4270 * Code for BigInteger::multiplyToLen() intrinsic.
4271 *
4272 * r0: x
4273 * r1: xlen
4274 * r2: y
4275 * r3: ylen
4276 * r4: z
4277 * r5: tmp0
4278 * r10: tmp1
4279 * r11: tmp2
4280 * r12: tmp3
4281 * r13: tmp4
4282 * r14: tmp5
4283 * r15: tmp6
4284 * r16: tmp7
4285 *
4286 */
4287 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
4288 Register z, Register tmp0,
4289 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
4290 Register tmp5, Register tmp6, Register product_hi) {
4291
4292 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, product_hi);
4293
4294 const Register idx = tmp1;
4295 const Register kdx = tmp2;
4296 const Register xstart = tmp3;
4297
4298 const Register y_idx = tmp4;
4299 const Register carry = tmp5;
4300 const Register product = xlen;
4301 const Register x_xstart = tmp0;
4302
4303 // First Loop.
4304 //
4305 // final static long LONG_MASK = 0xffffffffL;
4306 // int xstart = xlen - 1;
4307 // int ystart = ylen - 1;
4308 // long carry = 0;
4309 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4310 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
4311 // z[kdx] = (int)product;
4312 // carry = product >>> 32;
4313 // }
4314 // z[xstart] = (int)carry;
4315 //
4316
4317 movw(idx, ylen); // idx = ylen;
4318 addw(kdx, xlen, ylen); // kdx = xlen+ylen;
4319 mov(carry, zr); // carry = 0;
4320
4321 Label L_done;
4322
4323 movw(xstart, xlen);
4324 subsw(xstart, xstart, 1);
4325 br(Assembler::MI, L_done);
4326
4327 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
4328
4329 Label L_second_loop;
4330 cbzw(kdx, L_second_loop);
4331
4332 Label L_carry;
4333 subw(kdx, kdx, 1);
4334 cbzw(kdx, L_carry);
4335
4336 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4337 lsr(carry, carry, 32);
4338 subw(kdx, kdx, 1);
4339
4340 bind(L_carry);
4341 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4342
4343 // Second and third (nested) loops.
4344 //
4345 // for (int i = xstart-1; i >= 0; i--) { // Second loop
4346 // carry = 0;
4347 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
4348 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
4349 // (z[k] & LONG_MASK) + carry;
4350 // z[k] = (int)product;
4351 // carry = product >>> 32;
4352 // }
4353 // z[i] = (int)carry;
4354 // }
4355 //
4356 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
4357
4358 const Register jdx = tmp1;
4359
4360 bind(L_second_loop);
4361 mov(carry, zr); // carry = 0;
4362 movw(jdx, ylen); // j = ystart+1
4363
4364 subsw(xstart, xstart, 1); // i = xstart-1;
4365 br(Assembler::MI, L_done);
4366
4367 str(z, Address(pre(sp, -4 * wordSize)));
4368
4369 Label L_last_x;
4370 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
4371 subsw(xstart, xstart, 1); // i = xstart-1;
4372 br(Assembler::MI, L_last_x);
4373
4374 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
4375 ldr(product_hi, Address(rscratch1));
4376 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
4377
4378 Label L_third_loop_prologue;
4379 bind(L_third_loop_prologue);
4380
4381 str(ylen, Address(sp, wordSize));
4382 stp(x, xstart, Address(sp, 2 * wordSize));
4383 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
4384 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
4385 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
4386 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
4387
4388 addw(tmp3, xlen, 1);
4389 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4390 subsw(tmp3, tmp3, 1);
4391 br(Assembler::MI, L_done);
4392
4393 lsr(carry, carry, 32);
4394 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4395 b(L_second_loop);
4396
4397 // Next infrequent code is moved outside loops.
4398 bind(L_last_x);
4399 ldrw(product_hi, Address(x, 0));
4400 b(L_third_loop_prologue);
4401
4402 bind(L_done);
4403 }
4404
4405 // Code for BigInteger::mulAdd intrinsic
4406 // out = r0
4407 // in = r1
4408 // offset = r2 (already out.length-offset)
4409 // len = r3
4410 // k = r4
4411 //
4412 // pseudo code from java implementation:
4413 // carry = 0;
4414 // offset = out.length-offset - 1;
4415 // for (int j=len-1; j >= 0; j--) {
4416 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
4417 // out[offset--] = (int)product;
4418 // carry = product >>> 32;
4419 // }
4420 // return (int)carry;
4421 void MacroAssembler::mul_add(Register out, Register in, Register offset,
4422 Register len, Register k) {
4423 Label LOOP, END;
4424 // pre-loop
4425 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
4426 csel(out, zr, out, Assembler::EQ);
4427 br(Assembler::EQ, END);
4428 add(in, in, len, LSL, 2); // in[j+1] address
4429 add(offset, out, offset, LSL, 2); // out[offset + 1] address
4430 mov(out, zr); // used to keep carry now
4431 BIND(LOOP);
4432 ldrw(rscratch1, Address(pre(in, -4)));
4433 madd(rscratch1, rscratch1, k, out);
4434 ldrw(rscratch2, Address(pre(offset, -4)));
4435 add(rscratch1, rscratch1, rscratch2);
4436 strw(rscratch1, Address(offset));
4437 lsr(out, rscratch1, 32);
4438 subs(len, len, 1);
4439 br(Assembler::NE, LOOP);
4440 BIND(END);
4441 }
4442
4443 /**
4444 * Emits code to update CRC-32 with a byte value according to constants in table
4445 *
4446 * @param [in,out]crc Register containing the crc.
4447 * @param [in]val Register containing the byte to fold into the CRC.
4448 * @param [in]table Register containing the table of crc constants.
4449 *
4450 * uint32_t crc;
4451 * val = crc_table[(val ^ crc) & 0xFF];
4452 * crc = val ^ (crc >> 8);
4453 *
4454 */
4455 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4456 eor(val, val, crc);
4457 andr(val, val, 0xff);
4458 ldrw(val, Address(table, val, Address::lsl(2)));
4459 eor(crc, val, crc, Assembler::LSR, 8);
4460 }
4461
4462 /**
4463 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
4464 *
4465 * @param [in,out]crc Register containing the crc.
4466 * @param [in]v Register containing the 32-bit to fold into the CRC.
4467 * @param [in]table0 Register containing table 0 of crc constants.
4468 * @param [in]table1 Register containing table 1 of crc constants.
4469 * @param [in]table2 Register containing table 2 of crc constants.
4470 * @param [in]table3 Register containing table 3 of crc constants.
4471 *
4472 * uint32_t crc;
4473 * v = crc ^ v
4474 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
4475 *
4476 */
4477 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
4478 Register table0, Register table1, Register table2, Register table3,
4479 bool upper) {
4480 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
4481 uxtb(tmp, v);
4482 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
4483 ubfx(tmp, v, 8, 8);
4484 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
4485 eor(crc, crc, tmp);
4486 ubfx(tmp, v, 16, 8);
4487 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
4488 eor(crc, crc, tmp);
4489 ubfx(tmp, v, 24, 8);
4490 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
4491 eor(crc, crc, tmp);
4492 }
4493
4494 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf,
4495 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4496 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4497 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4498
4499 subs(tmp0, len, 384);
4500 mvnw(crc, crc);
4501 br(Assembler::GE, CRC_by128_pre);
4502 BIND(CRC_less128);
4503 subs(len, len, 32);
4504 br(Assembler::GE, CRC_by32_loop);
4505 BIND(CRC_less32);
4506 adds(len, len, 32 - 4);
4507 br(Assembler::GE, CRC_by4_loop);
4508 adds(len, len, 4);
4509 br(Assembler::GT, CRC_by1_loop);
4510 b(L_exit);
4511
4512 BIND(CRC_by32_loop);
4513 ldp(tmp0, tmp1, Address(buf));
4514 crc32x(crc, crc, tmp0);
4515 ldp(tmp2, tmp3, Address(buf, 16));
4516 crc32x(crc, crc, tmp1);
4517 add(buf, buf, 32);
4518 crc32x(crc, crc, tmp2);
4519 subs(len, len, 32);
4520 crc32x(crc, crc, tmp3);
4521 br(Assembler::GE, CRC_by32_loop);
4522 cmn(len, (u1)32);
4523 br(Assembler::NE, CRC_less32);
4524 b(L_exit);
4525
4526 BIND(CRC_by4_loop);
4527 ldrw(tmp0, Address(post(buf, 4)));
4528 subs(len, len, 4);
4529 crc32w(crc, crc, tmp0);
4530 br(Assembler::GE, CRC_by4_loop);
4531 adds(len, len, 4);
4532 br(Assembler::LE, L_exit);
4533 BIND(CRC_by1_loop);
4534 ldrb(tmp0, Address(post(buf, 1)));
4535 subs(len, len, 1);
4536 crc32b(crc, crc, tmp0);
4537 br(Assembler::GT, CRC_by1_loop);
4538 b(L_exit);
4539
4540 BIND(CRC_by128_pre);
4541 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4542 4*256*sizeof(juint) + 8*sizeof(juint));
4543 mov(crc, 0);
4544 crc32x(crc, crc, tmp0);
4545 crc32x(crc, crc, tmp1);
4546
4547 cbnz(len, CRC_less128);
4548
4549 BIND(L_exit);
4550 mvnw(crc, crc);
4551 }
4552
4553 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
4554 Register len, Register tmp0, Register tmp1, Register tmp2,
4555 Register tmp3) {
4556 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4557 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4558
4559 mvnw(crc, crc);
4560
4561 subs(len, len, 128);
4562 br(Assembler::GE, CRC_by64_pre);
4563 BIND(CRC_less64);
4564 adds(len, len, 128-32);
4565 br(Assembler::GE, CRC_by32_loop);
4566 BIND(CRC_less32);
4567 adds(len, len, 32-4);
4568 br(Assembler::GE, CRC_by4_loop);
4569 adds(len, len, 4);
4570 br(Assembler::GT, CRC_by1_loop);
4571 b(L_exit);
4572
4573 BIND(CRC_by32_loop);
4574 ldp(tmp0, tmp1, Address(post(buf, 16)));
4575 subs(len, len, 32);
4576 crc32x(crc, crc, tmp0);
4577 ldr(tmp2, Address(post(buf, 8)));
4578 crc32x(crc, crc, tmp1);
4579 ldr(tmp3, Address(post(buf, 8)));
4580 crc32x(crc, crc, tmp2);
4581 crc32x(crc, crc, tmp3);
4582 br(Assembler::GE, CRC_by32_loop);
4583 cmn(len, (u1)32);
4584 br(Assembler::NE, CRC_less32);
4585 b(L_exit);
4586
4587 BIND(CRC_by4_loop);
4588 ldrw(tmp0, Address(post(buf, 4)));
4589 subs(len, len, 4);
4590 crc32w(crc, crc, tmp0);
4591 br(Assembler::GE, CRC_by4_loop);
4592 adds(len, len, 4);
4593 br(Assembler::LE, L_exit);
4594 BIND(CRC_by1_loop);
4595 ldrb(tmp0, Address(post(buf, 1)));
4596 subs(len, len, 1);
4597 crc32b(crc, crc, tmp0);
4598 br(Assembler::GT, CRC_by1_loop);
4599 b(L_exit);
4600
4601 BIND(CRC_by64_pre);
4602 sub(buf, buf, 8);
4603 ldp(tmp0, tmp1, Address(buf, 8));
4604 crc32x(crc, crc, tmp0);
4605 ldr(tmp2, Address(buf, 24));
4606 crc32x(crc, crc, tmp1);
4607 ldr(tmp3, Address(buf, 32));
4608 crc32x(crc, crc, tmp2);
4609 ldr(tmp0, Address(buf, 40));
4610 crc32x(crc, crc, tmp3);
4611 ldr(tmp1, Address(buf, 48));
4612 crc32x(crc, crc, tmp0);
4613 ldr(tmp2, Address(buf, 56));
4614 crc32x(crc, crc, tmp1);
4615 ldr(tmp3, Address(pre(buf, 64)));
4616
4617 b(CRC_by64_loop);
4618
4619 align(CodeEntryAlignment);
4620 BIND(CRC_by64_loop);
4621 subs(len, len, 64);
4622 crc32x(crc, crc, tmp2);
4623 ldr(tmp0, Address(buf, 8));
4624 crc32x(crc, crc, tmp3);
4625 ldr(tmp1, Address(buf, 16));
4626 crc32x(crc, crc, tmp0);
4627 ldr(tmp2, Address(buf, 24));
4628 crc32x(crc, crc, tmp1);
4629 ldr(tmp3, Address(buf, 32));
4630 crc32x(crc, crc, tmp2);
4631 ldr(tmp0, Address(buf, 40));
4632 crc32x(crc, crc, tmp3);
4633 ldr(tmp1, Address(buf, 48));
4634 crc32x(crc, crc, tmp0);
4635 ldr(tmp2, Address(buf, 56));
4636 crc32x(crc, crc, tmp1);
4637 ldr(tmp3, Address(pre(buf, 64)));
4638 br(Assembler::GE, CRC_by64_loop);
4639
4640 // post-loop
4641 crc32x(crc, crc, tmp2);
4642 crc32x(crc, crc, tmp3);
4643
4644 sub(len, len, 64);
4645 add(buf, buf, 8);
4646 cmn(len, (u1)128);
4647 br(Assembler::NE, CRC_less64);
4648 BIND(L_exit);
4649 mvnw(crc, crc);
4650 }
4651
4652 /**
4653 * @param crc register containing existing CRC (32-bit)
4654 * @param buf register pointing to input byte buffer (byte*)
4655 * @param len register containing number of bytes
4656 * @param table register that will contain address of CRC table
4657 * @param tmp scratch register
4658 */
4659 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
4660 Register table0, Register table1, Register table2, Register table3,
4661 Register tmp, Register tmp2, Register tmp3) {
4662 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
4663
4664 if (UseCryptoPmullForCRC32) {
4665 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4666 return;
4667 }
4668
4669 if (UseCRC32) {
4670 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
4671 return;
4672 }
4673
4674 mvnw(crc, crc);
4675
4676 {
4677 uint64_t offset;
4678 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4679 add(table0, table0, offset);
4680 }
4681 add(table1, table0, 1*256*sizeof(juint));
4682 add(table2, table0, 2*256*sizeof(juint));
4683 add(table3, table0, 3*256*sizeof(juint));
4684
4685 { // Neon code start
4686 cmp(len, (u1)64);
4687 br(Assembler::LT, L_by16);
4688 eor(v16, T16B, v16, v16);
4689
4690 Label L_fold;
4691
4692 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
4693
4694 ld1(v0, v1, T2D, post(buf, 32));
4695 ld1r(v4, T2D, post(tmp, 8));
4696 ld1r(v5, T2D, post(tmp, 8));
4697 ld1r(v6, T2D, post(tmp, 8));
4698 ld1r(v7, T2D, post(tmp, 8));
4699 mov(v16, S, 0, crc);
4700
4701 eor(v0, T16B, v0, v16);
4702 sub(len, len, 64);
4703
4704 BIND(L_fold);
4705 pmull(v22, T8H, v0, v5, T8B);
4706 pmull(v20, T8H, v0, v7, T8B);
4707 pmull(v23, T8H, v0, v4, T8B);
4708 pmull(v21, T8H, v0, v6, T8B);
4709
4710 pmull2(v18, T8H, v0, v5, T16B);
4711 pmull2(v16, T8H, v0, v7, T16B);
4712 pmull2(v19, T8H, v0, v4, T16B);
4713 pmull2(v17, T8H, v0, v6, T16B);
4714
4715 uzp1(v24, T8H, v20, v22);
4716 uzp2(v25, T8H, v20, v22);
4717 eor(v20, T16B, v24, v25);
4718
4719 uzp1(v26, T8H, v16, v18);
4720 uzp2(v27, T8H, v16, v18);
4721 eor(v16, T16B, v26, v27);
4722
4723 ushll2(v22, T4S, v20, T8H, 8);
4724 ushll(v20, T4S, v20, T4H, 8);
4725
4726 ushll2(v18, T4S, v16, T8H, 8);
4727 ushll(v16, T4S, v16, T4H, 8);
4728
4729 eor(v22, T16B, v23, v22);
4730 eor(v18, T16B, v19, v18);
4731 eor(v20, T16B, v21, v20);
4732 eor(v16, T16B, v17, v16);
4733
4734 uzp1(v17, T2D, v16, v20);
4735 uzp2(v21, T2D, v16, v20);
4736 eor(v17, T16B, v17, v21);
4737
4738 ushll2(v20, T2D, v17, T4S, 16);
4739 ushll(v16, T2D, v17, T2S, 16);
4740
4741 eor(v20, T16B, v20, v22);
4742 eor(v16, T16B, v16, v18);
4743
4744 uzp1(v17, T2D, v20, v16);
4745 uzp2(v21, T2D, v20, v16);
4746 eor(v28, T16B, v17, v21);
4747
4748 pmull(v22, T8H, v1, v5, T8B);
4749 pmull(v20, T8H, v1, v7, T8B);
4750 pmull(v23, T8H, v1, v4, T8B);
4751 pmull(v21, T8H, v1, v6, T8B);
4752
4753 pmull2(v18, T8H, v1, v5, T16B);
4754 pmull2(v16, T8H, v1, v7, T16B);
4755 pmull2(v19, T8H, v1, v4, T16B);
4756 pmull2(v17, T8H, v1, v6, T16B);
4757
4758 ld1(v0, v1, T2D, post(buf, 32));
4759
4760 uzp1(v24, T8H, v20, v22);
4761 uzp2(v25, T8H, v20, v22);
4762 eor(v20, T16B, v24, v25);
4763
4764 uzp1(v26, T8H, v16, v18);
4765 uzp2(v27, T8H, v16, v18);
4766 eor(v16, T16B, v26, v27);
4767
4768 ushll2(v22, T4S, v20, T8H, 8);
4769 ushll(v20, T4S, v20, T4H, 8);
4770
4771 ushll2(v18, T4S, v16, T8H, 8);
4772 ushll(v16, T4S, v16, T4H, 8);
4773
4774 eor(v22, T16B, v23, v22);
4775 eor(v18, T16B, v19, v18);
4776 eor(v20, T16B, v21, v20);
4777 eor(v16, T16B, v17, v16);
4778
4779 uzp1(v17, T2D, v16, v20);
4780 uzp2(v21, T2D, v16, v20);
4781 eor(v16, T16B, v17, v21);
4782
4783 ushll2(v20, T2D, v16, T4S, 16);
4784 ushll(v16, T2D, v16, T2S, 16);
4785
4786 eor(v20, T16B, v22, v20);
4787 eor(v16, T16B, v16, v18);
4788
4789 uzp1(v17, T2D, v20, v16);
4790 uzp2(v21, T2D, v20, v16);
4791 eor(v20, T16B, v17, v21);
4792
4793 shl(v16, T2D, v28, 1);
4794 shl(v17, T2D, v20, 1);
4795
4796 eor(v0, T16B, v0, v16);
4797 eor(v1, T16B, v1, v17);
4798
4799 subs(len, len, 32);
4800 br(Assembler::GE, L_fold);
4801
4802 mov(crc, 0);
4803 mov(tmp, v0, D, 0);
4804 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4805 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4806 mov(tmp, v0, D, 1);
4807 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4808 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4809 mov(tmp, v1, D, 0);
4810 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4811 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4812 mov(tmp, v1, D, 1);
4813 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4814 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4815
4816 add(len, len, 32);
4817 } // Neon code end
4818
4819 BIND(L_by16);
4820 subs(len, len, 16);
4821 br(Assembler::GE, L_by16_loop);
4822 adds(len, len, 16-4);
4823 br(Assembler::GE, L_by4_loop);
4824 adds(len, len, 4);
4825 br(Assembler::GT, L_by1_loop);
4826 b(L_exit);
4827
4828 BIND(L_by4_loop);
4829 ldrw(tmp, Address(post(buf, 4)));
4830 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
4831 subs(len, len, 4);
4832 br(Assembler::GE, L_by4_loop);
4833 adds(len, len, 4);
4834 br(Assembler::LE, L_exit);
4835 BIND(L_by1_loop);
4836 subs(len, len, 1);
4837 ldrb(tmp, Address(post(buf, 1)));
4838 update_byte_crc32(crc, tmp, table0);
4839 br(Assembler::GT, L_by1_loop);
4840 b(L_exit);
4841
4842 align(CodeEntryAlignment);
4843 BIND(L_by16_loop);
4844 subs(len, len, 16);
4845 ldp(tmp, tmp3, Address(post(buf, 16)));
4846 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4847 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4848 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
4849 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
4850 br(Assembler::GE, L_by16_loop);
4851 adds(len, len, 16-4);
4852 br(Assembler::GE, L_by4_loop);
4853 adds(len, len, 4);
4854 br(Assembler::GT, L_by1_loop);
4855 BIND(L_exit);
4856 mvnw(crc, crc);
4857 }
4858
4859 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
4860 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4861 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4862 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4863
4864 subs(tmp0, len, 384);
4865 br(Assembler::GE, CRC_by128_pre);
4866 BIND(CRC_less128);
4867 subs(len, len, 32);
4868 br(Assembler::GE, CRC_by32_loop);
4869 BIND(CRC_less32);
4870 adds(len, len, 32 - 4);
4871 br(Assembler::GE, CRC_by4_loop);
4872 adds(len, len, 4);
4873 br(Assembler::GT, CRC_by1_loop);
4874 b(L_exit);
4875
4876 BIND(CRC_by32_loop);
4877 ldp(tmp0, tmp1, Address(buf));
4878 crc32cx(crc, crc, tmp0);
4879 ldr(tmp2, Address(buf, 16));
4880 crc32cx(crc, crc, tmp1);
4881 ldr(tmp3, Address(buf, 24));
4882 crc32cx(crc, crc, tmp2);
4883 add(buf, buf, 32);
4884 subs(len, len, 32);
4885 crc32cx(crc, crc, tmp3);
4886 br(Assembler::GE, CRC_by32_loop);
4887 cmn(len, (u1)32);
4888 br(Assembler::NE, CRC_less32);
4889 b(L_exit);
4890
4891 BIND(CRC_by4_loop);
4892 ldrw(tmp0, Address(post(buf, 4)));
4893 subs(len, len, 4);
4894 crc32cw(crc, crc, tmp0);
4895 br(Assembler::GE, CRC_by4_loop);
4896 adds(len, len, 4);
4897 br(Assembler::LE, L_exit);
4898 BIND(CRC_by1_loop);
4899 ldrb(tmp0, Address(post(buf, 1)));
4900 subs(len, len, 1);
4901 crc32cb(crc, crc, tmp0);
4902 br(Assembler::GT, CRC_by1_loop);
4903 b(L_exit);
4904
4905 BIND(CRC_by128_pre);
4906 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4907 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50);
4908 mov(crc, 0);
4909 crc32cx(crc, crc, tmp0);
4910 crc32cx(crc, crc, tmp1);
4911
4912 cbnz(len, CRC_less128);
4913
4914 BIND(L_exit);
4915 }
4916
4917 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
4918 Register len, Register tmp0, Register tmp1, Register tmp2,
4919 Register tmp3) {
4920 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4921 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4922
4923 subs(len, len, 128);
4924 br(Assembler::GE, CRC_by64_pre);
4925 BIND(CRC_less64);
4926 adds(len, len, 128-32);
4927 br(Assembler::GE, CRC_by32_loop);
4928 BIND(CRC_less32);
4929 adds(len, len, 32-4);
4930 br(Assembler::GE, CRC_by4_loop);
4931 adds(len, len, 4);
4932 br(Assembler::GT, CRC_by1_loop);
4933 b(L_exit);
4934
4935 BIND(CRC_by32_loop);
4936 ldp(tmp0, tmp1, Address(post(buf, 16)));
4937 subs(len, len, 32);
4938 crc32cx(crc, crc, tmp0);
4939 ldr(tmp2, Address(post(buf, 8)));
4940 crc32cx(crc, crc, tmp1);
4941 ldr(tmp3, Address(post(buf, 8)));
4942 crc32cx(crc, crc, tmp2);
4943 crc32cx(crc, crc, tmp3);
4944 br(Assembler::GE, CRC_by32_loop);
4945 cmn(len, (u1)32);
4946 br(Assembler::NE, CRC_less32);
4947 b(L_exit);
4948
4949 BIND(CRC_by4_loop);
4950 ldrw(tmp0, Address(post(buf, 4)));
4951 subs(len, len, 4);
4952 crc32cw(crc, crc, tmp0);
4953 br(Assembler::GE, CRC_by4_loop);
4954 adds(len, len, 4);
4955 br(Assembler::LE, L_exit);
4956 BIND(CRC_by1_loop);
4957 ldrb(tmp0, Address(post(buf, 1)));
4958 subs(len, len, 1);
4959 crc32cb(crc, crc, tmp0);
4960 br(Assembler::GT, CRC_by1_loop);
4961 b(L_exit);
4962
4963 BIND(CRC_by64_pre);
4964 sub(buf, buf, 8);
4965 ldp(tmp0, tmp1, Address(buf, 8));
4966 crc32cx(crc, crc, tmp0);
4967 ldr(tmp2, Address(buf, 24));
4968 crc32cx(crc, crc, tmp1);
4969 ldr(tmp3, Address(buf, 32));
4970 crc32cx(crc, crc, tmp2);
4971 ldr(tmp0, Address(buf, 40));
4972 crc32cx(crc, crc, tmp3);
4973 ldr(tmp1, Address(buf, 48));
4974 crc32cx(crc, crc, tmp0);
4975 ldr(tmp2, Address(buf, 56));
4976 crc32cx(crc, crc, tmp1);
4977 ldr(tmp3, Address(pre(buf, 64)));
4978
4979 b(CRC_by64_loop);
4980
4981 align(CodeEntryAlignment);
4982 BIND(CRC_by64_loop);
4983 subs(len, len, 64);
4984 crc32cx(crc, crc, tmp2);
4985 ldr(tmp0, Address(buf, 8));
4986 crc32cx(crc, crc, tmp3);
4987 ldr(tmp1, Address(buf, 16));
4988 crc32cx(crc, crc, tmp0);
4989 ldr(tmp2, Address(buf, 24));
4990 crc32cx(crc, crc, tmp1);
4991 ldr(tmp3, Address(buf, 32));
4992 crc32cx(crc, crc, tmp2);
4993 ldr(tmp0, Address(buf, 40));
4994 crc32cx(crc, crc, tmp3);
4995 ldr(tmp1, Address(buf, 48));
4996 crc32cx(crc, crc, tmp0);
4997 ldr(tmp2, Address(buf, 56));
4998 crc32cx(crc, crc, tmp1);
4999 ldr(tmp3, Address(pre(buf, 64)));
5000 br(Assembler::GE, CRC_by64_loop);
5001
5002 // post-loop
5003 crc32cx(crc, crc, tmp2);
5004 crc32cx(crc, crc, tmp3);
5005
5006 sub(len, len, 64);
5007 add(buf, buf, 8);
5008 cmn(len, (u1)128);
5009 br(Assembler::NE, CRC_less64);
5010 BIND(L_exit);
5011 }
5012
5013 /**
5014 * @param crc register containing existing CRC (32-bit)
5015 * @param buf register pointing to input byte buffer (byte*)
5016 * @param len register containing number of bytes
5017 * @param table register that will contain address of CRC table
5018 * @param tmp scratch register
5019 */
5020 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
5021 Register table0, Register table1, Register table2, Register table3,
5022 Register tmp, Register tmp2, Register tmp3) {
5023 if (UseCryptoPmullForCRC32) {
5024 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
5025 } else {
5026 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
5027 }
5028 }
5029
5030 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
5031 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) {
5032 Label CRC_by128_loop;
5033 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
5034
5035 sub(len, len, 256);
5036 Register table = tmp0;
5037 {
5038 uint64_t offset;
5039 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset);
5040 add(table, table, offset);
5041 }
5042 add(table, table, table_offset);
5043
5044 // Registers v0..v7 are used as data registers.
5045 // Registers v16..v31 are used as tmp registers.
5046 sub(buf, buf, 0x10);
5047 ldrq(v0, Address(buf, 0x10));
5048 ldrq(v1, Address(buf, 0x20));
5049 ldrq(v2, Address(buf, 0x30));
5050 ldrq(v3, Address(buf, 0x40));
5051 ldrq(v4, Address(buf, 0x50));
5052 ldrq(v5, Address(buf, 0x60));
5053 ldrq(v6, Address(buf, 0x70));
5054 ldrq(v7, Address(pre(buf, 0x80)));
5055
5056 movi(v31, T4S, 0);
5057 mov(v31, S, 0, crc);
5058 eor(v0, T16B, v0, v31);
5059
5060 // Register v16 contains constants from the crc table.
5061 ldrq(v16, Address(table));
5062 b(CRC_by128_loop);
5063
5064 align(OptoLoopAlignment);
5065 BIND(CRC_by128_loop);
5066 pmull (v17, T1Q, v0, v16, T1D);
5067 pmull2(v18, T1Q, v0, v16, T2D);
5068 ldrq(v0, Address(buf, 0x10));
5069 eor3(v0, T16B, v17, v18, v0);
5070
5071 pmull (v19, T1Q, v1, v16, T1D);
5072 pmull2(v20, T1Q, v1, v16, T2D);
5073 ldrq(v1, Address(buf, 0x20));
5074 eor3(v1, T16B, v19, v20, v1);
5075
5076 pmull (v21, T1Q, v2, v16, T1D);
5077 pmull2(v22, T1Q, v2, v16, T2D);
5078 ldrq(v2, Address(buf, 0x30));
5079 eor3(v2, T16B, v21, v22, v2);
5080
5081 pmull (v23, T1Q, v3, v16, T1D);
5082 pmull2(v24, T1Q, v3, v16, T2D);
5083 ldrq(v3, Address(buf, 0x40));
5084 eor3(v3, T16B, v23, v24, v3);
5085
5086 pmull (v25, T1Q, v4, v16, T1D);
5087 pmull2(v26, T1Q, v4, v16, T2D);
5088 ldrq(v4, Address(buf, 0x50));
5089 eor3(v4, T16B, v25, v26, v4);
5090
5091 pmull (v27, T1Q, v5, v16, T1D);
5092 pmull2(v28, T1Q, v5, v16, T2D);
5093 ldrq(v5, Address(buf, 0x60));
5094 eor3(v5, T16B, v27, v28, v5);
5095
5096 pmull (v29, T1Q, v6, v16, T1D);
5097 pmull2(v30, T1Q, v6, v16, T2D);
5098 ldrq(v6, Address(buf, 0x70));
5099 eor3(v6, T16B, v29, v30, v6);
5100
5101 // Reuse registers v23, v24.
5102 // Using them won't block the first instruction of the next iteration.
5103 pmull (v23, T1Q, v7, v16, T1D);
5104 pmull2(v24, T1Q, v7, v16, T2D);
5105 ldrq(v7, Address(pre(buf, 0x80)));
5106 eor3(v7, T16B, v23, v24, v7);
5107
5108 subs(len, len, 0x80);
5109 br(Assembler::GE, CRC_by128_loop);
5110
5111 // fold into 512 bits
5112 // Use v31 for constants because v16 can be still in use.
5113 ldrq(v31, Address(table, 0x10));
5114
5115 pmull (v17, T1Q, v0, v31, T1D);
5116 pmull2(v18, T1Q, v0, v31, T2D);
5117 eor3(v0, T16B, v17, v18, v4);
5118
5119 pmull (v19, T1Q, v1, v31, T1D);
5120 pmull2(v20, T1Q, v1, v31, T2D);
5121 eor3(v1, T16B, v19, v20, v5);
5122
5123 pmull (v21, T1Q, v2, v31, T1D);
5124 pmull2(v22, T1Q, v2, v31, T2D);
5125 eor3(v2, T16B, v21, v22, v6);
5126
5127 pmull (v23, T1Q, v3, v31, T1D);
5128 pmull2(v24, T1Q, v3, v31, T2D);
5129 eor3(v3, T16B, v23, v24, v7);
5130
5131 // fold into 128 bits
5132 // Use v17 for constants because v31 can be still in use.
5133 ldrq(v17, Address(table, 0x20));
5134 pmull (v25, T1Q, v0, v17, T1D);
5135 pmull2(v26, T1Q, v0, v17, T2D);
5136 eor3(v3, T16B, v3, v25, v26);
5137
5138 // Use v18 for constants because v17 can be still in use.
5139 ldrq(v18, Address(table, 0x30));
5140 pmull (v27, T1Q, v1, v18, T1D);
5141 pmull2(v28, T1Q, v1, v18, T2D);
5142 eor3(v3, T16B, v3, v27, v28);
5143
5144 // Use v19 for constants because v18 can be still in use.
5145 ldrq(v19, Address(table, 0x40));
5146 pmull (v29, T1Q, v2, v19, T1D);
5147 pmull2(v30, T1Q, v2, v19, T2D);
5148 eor3(v0, T16B, v3, v29, v30);
5149
5150 add(len, len, 0x80);
5151 add(buf, buf, 0x10);
5152
5153 mov(tmp0, v0, D, 0);
5154 mov(tmp1, v0, D, 1);
5155 }
5156
5157 void MacroAssembler::addptr(const Address &dst, int32_t src) {
5158 Address adr;
5159 switch(dst.getMode()) {
5160 case Address::base_plus_offset:
5161 // This is the expected mode, although we allow all the other
5162 // forms below.
5163 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
5164 break;
5165 default:
5166 lea(rscratch2, dst);
5167 adr = Address(rscratch2);
5168 break;
5169 }
5170 ldr(rscratch1, adr);
5171 add(rscratch1, rscratch1, src);
5172 str(rscratch1, adr);
5173 }
5174
5175 void MacroAssembler::cmpptr(Register src1, Address src2) {
5176 uint64_t offset;
5177 adrp(rscratch1, src2, offset);
5178 ldr(rscratch1, Address(rscratch1, offset));
5179 cmp(src1, rscratch1);
5180 }
5181
5182 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
5183 cmp(obj1, obj2);
5184 }
5185
5186 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5187 load_method_holder(rresult, rmethod);
5188 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5189 }
5190
5191 void MacroAssembler::load_method_holder(Register holder, Register method) {
5192 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
5193 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5194 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5195 }
5196
5197 void MacroAssembler::load_metadata(Register dst, Register src) {
5198 if (UseCompactObjectHeaders) {
5199 load_narrow_klass_compact(dst, src);
5200 } else {
5201 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5202 }
5203 }
5204
5205 // Loads the obj's narrow Klass from a compact object header (+COH) into dst.
5206 // Preserves all registers (incl src, rscratch1 and rscratch2).
5207 // Input:
5208 // src - the oop we want to load the klass from.
5209 // dst - output narrow klass.
5210 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5211 assert(UseCompactObjectHeaders, "expects UseCompactObjectHeaders");
5212 ldr(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5213 lsr(dst, dst, markWord::klass_shift);
5214 }
5215
5216 // Loads the obj's narrow Klass from any header (compact or not) into dst.
5217 void MacroAssembler::load_narrow_klass(Register dst, Register src) {
5218 if (UseCompactObjectHeaders) {
5219 load_narrow_klass_compact(dst, src);
5220 } else {
5221 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5222 }
5223 }
5224
5225 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5226 load_narrow_klass(dst, src);
5227 decode_klass_not_null(dst, dst, tmp);
5228 }
5229
5230 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5231 if (RestoreMXCSROnJNICalls) {
5232 Label OK;
5233 get_fpcr(tmp1);
5234 mov(tmp2, tmp1);
5235 // Set FPCR to the state we need. We do want Round to Nearest. We
5236 // don't want non-IEEE rounding modes or floating-point traps.
5237 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5238 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5239 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5240 eor(tmp2, tmp1, tmp2);
5241 cbz(tmp2, OK); // Only reset FPCR if it's wrong
5242 set_fpcr(tmp1);
5243 bind(OK);
5244 }
5245 }
5246
5247 // ((OopHandle)result).resolve();
5248 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
5249 // OopHandle::resolve is an indirection.
5250 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
5251 }
5252
5253 // ((WeakHandle)result).resolve();
5254 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
5255 assert_different_registers(result, tmp1, tmp2);
5256 Label resolved;
5257
5258 // A null weak handle resolves to null.
5259 cbz(result, resolved);
5260
5261 // Only 64 bit platforms support GCs that require a tmp register
5262 // WeakHandle::resolve is an indirection like jweak.
5263 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5264 result, Address(result), tmp1, tmp2);
5265 bind(resolved);
5266 }
5267
5268 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) {
5269 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5270 ldr(dst, Address(rmethod, Method::const_offset()));
5271 ldr(dst, Address(dst, ConstMethod::constants_offset()));
5272 ldr(dst, Address(dst, ConstantPool::pool_holder_offset()));
5273 ldr(dst, Address(dst, mirror_offset));
5274 resolve_oop_handle(dst, tmp1, tmp2);
5275 }
5276
5277 void MacroAssembler::cmp_klass(Register obj, Register klass, Register tmp, Register tmp2) {
5278 assert_different_registers(obj, klass, tmp, tmp2);
5279 if (UseCompactObjectHeaders) {
5280 load_narrow_klass_compact(tmp, obj);
5281 } else {
5282 ldrw(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5283 }
5284 if (CompressedKlassPointers::base() == nullptr) {
5285 cmp(klass, tmp, LSL, CompressedKlassPointers::shift());
5286 return;
5287 } else if (!AOTCodeCache::is_on_for_dump() &&
5288 ((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5289 && CompressedKlassPointers::shift() == 0) {
5290 // Only the bottom 32 bits matter
5291 cmpw(klass, tmp);
5292 return;
5293 }
5294 decode_klass_not_null(tmp, tmp, tmp2);
5295 cmp(klass, tmp);
5296 }
5297
5298 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5299 if (UseCompactObjectHeaders) {
5300 load_narrow_klass_compact(tmp1, obj1);
5301 load_narrow_klass_compact(tmp2, obj2);
5302 } else {
5303 ldrw(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5304 ldrw(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5305 }
5306 cmpw(tmp1, tmp2);
5307 }
5308
5309 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5310 Register tmp = (dst == rscratch1) ? rscratch2 : rscratch1;
5311 load_klass(dst, src, tmp);
5312 ldr(dst, Address(dst, Klass::prototype_header_offset()));
5313 }
5314
5315 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5316 // FIXME: Should this be a store release? concurrent gcs assumes
5317 // klass length is valid if klass field is not null.
5318 assert(!UseCompactObjectHeaders, "not with compact headers");
5319 encode_klass_not_null(src, src, tmp);
5320 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5321 }
5322
5323 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5324 assert(!UseCompactObjectHeaders, "not with compact headers");
5325 // Store to klass gap in destination
5326 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5327 }
5328
5329 // Algorithm must match CompressedOops::encode.
5330 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5331 #ifdef ASSERT
5332 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5333 #endif
5334 verify_oop_msg(s, "broken oop in encode_heap_oop");
5335 if (CompressedOops::base() == nullptr) {
5336 if (CompressedOops::shift() != 0) {
5337 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5338 lsr(d, s, LogMinObjAlignmentInBytes);
5339 } else {
5340 mov(d, s);
5341 }
5342 } else {
5343 subs(d, s, rheapbase);
5344 csel(d, d, zr, Assembler::HS);
5345 lsr(d, d, LogMinObjAlignmentInBytes);
5346
5347 /* Old algorithm: is this any worse?
5348 Label nonnull;
5349 cbnz(r, nonnull);
5350 sub(r, r, rheapbase);
5351 bind(nonnull);
5352 lsr(r, r, LogMinObjAlignmentInBytes);
5353 */
5354 }
5355 }
5356
5357 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5358 #ifdef ASSERT
5359 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5360 if (CheckCompressedOops) {
5361 Label ok;
5362 cbnz(r, ok);
5363 stop("null oop passed to encode_heap_oop_not_null");
5364 bind(ok);
5365 }
5366 #endif
5367 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5368 if (CompressedOops::base() != nullptr) {
5369 sub(r, r, rheapbase);
5370 }
5371 if (CompressedOops::shift() != 0) {
5372 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5373 lsr(r, r, LogMinObjAlignmentInBytes);
5374 }
5375 }
5376
5377 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5378 #ifdef ASSERT
5379 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5380 if (CheckCompressedOops) {
5381 Label ok;
5382 cbnz(src, ok);
5383 stop("null oop passed to encode_heap_oop_not_null2");
5384 bind(ok);
5385 }
5386 #endif
5387 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5388
5389 Register data = src;
5390 if (CompressedOops::base() != nullptr) {
5391 sub(dst, src, rheapbase);
5392 data = dst;
5393 }
5394 if (CompressedOops::shift() != 0) {
5395 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5396 lsr(dst, data, LogMinObjAlignmentInBytes);
5397 data = dst;
5398 }
5399 if (data == src)
5400 mov(dst, src);
5401 }
5402
5403 void MacroAssembler::decode_heap_oop(Register d, Register s) {
5404 #ifdef ASSERT
5405 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5406 #endif
5407 if (CompressedOops::base() == nullptr) {
5408 if (CompressedOops::shift() != 0) {
5409 lsl(d, s, CompressedOops::shift());
5410 } else if (d != s) {
5411 mov(d, s);
5412 }
5413 } else {
5414 Label done;
5415 if (d != s)
5416 mov(d, s);
5417 cbz(s, done);
5418 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
5419 bind(done);
5420 }
5421 verify_oop_msg(d, "broken oop in decode_heap_oop");
5422 }
5423
5424 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5425 assert (UseCompressedOops, "should only be used for compressed headers");
5426 assert (Universe::heap() != nullptr, "java heap should be initialized");
5427 // Cannot assert, unverified entry point counts instructions (see .ad file)
5428 // vtableStubs also counts instructions in pd_code_size_limit.
5429 // Also do not verify_oop as this is called by verify_oop.
5430 if (CompressedOops::shift() != 0) {
5431 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5432 if (CompressedOops::base() != nullptr) {
5433 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5434 } else {
5435 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5436 }
5437 } else {
5438 assert (CompressedOops::base() == nullptr, "sanity");
5439 }
5440 }
5441
5442 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5443 assert (UseCompressedOops, "should only be used for compressed headers");
5444 assert (Universe::heap() != nullptr, "java heap should be initialized");
5445 // Cannot assert, unverified entry point counts instructions (see .ad file)
5446 // vtableStubs also counts instructions in pd_code_size_limit.
5447 // Also do not verify_oop as this is called by verify_oop.
5448 if (CompressedOops::shift() != 0) {
5449 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5450 if (CompressedOops::base() != nullptr) {
5451 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5452 } else {
5453 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5454 }
5455 } else {
5456 assert (CompressedOops::base() == nullptr, "sanity");
5457 if (dst != src) {
5458 mov(dst, src);
5459 }
5460 }
5461 }
5462
5463 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone);
5464
5465 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
5466 assert(Metaspace::initialized(), "metaspace not initialized yet");
5467 assert(_klass_decode_mode != KlassDecodeNone, "should be initialized");
5468 return _klass_decode_mode;
5469 }
5470
5471 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode(address base, int shift, const size_t range) {
5472
5473 if (base == nullptr) {
5474 return KlassDecodeZero;
5475 }
5476
5477 if (operand_valid_for_logical_immediate(
5478 /*is32*/false, (uint64_t)base)) {
5479 const uint64_t range_mask = right_n_bits(log2i_ceil(range));
5480 if (((uint64_t)base & range_mask) == 0) {
5481 return KlassDecodeXor;
5482 }
5483 }
5484
5485 const uint64_t shifted_base =
5486 (uint64_t)base >> shift;
5487 if ((shifted_base & 0xffff0000ffffffff) == 0) {
5488 return KlassDecodeMovk;
5489 }
5490
5491 return KlassDecodeFallback;
5492 }
5493
5494 void MacroAssembler::initialize_klass_decode_mode(address base, int shift, const size_t range) {
5495 // KlassDecodeMode shouldn't be set already.
5496 assert(_klass_decode_mode == KlassDecodeNone, "set once");
5497 _klass_decode_mode = klass_decode_mode(base, shift, range);
5498 log_info(metaspace)("Klass Decode Mode: %d", (int)_klass_decode_mode);
5499 }
5500
5501 void MacroAssembler::encode_klass_not_null(Register dst, Register src, Register tmp) {
5502 emit_encode_klass_not_null(dst, src, tmp, CompressedKlassPointers::base(),
5503 CompressedKlassPointers::shift(), klass_decode_mode());
5504 }
5505
5506 void MacroAssembler::emit_encode_klass_not_null(Register dst, Register src, Register tmp,
5507 address base, int shift, KlassDecodeMode decode_mode) {
5508
5509 assert_different_registers(tmp, src);
5510 assert(tmp != noreg, "valid tmp required");
5511
5512 if (AOTCodeCache::is_on_for_dump()) {
5513 // We are generating code during AOT buildup that will run in *future* processes
5514 // with likely different encoding settings. Therefore, we have to load the
5515 // encoding base dynamically, we cannot just bake it in as immediate.
5516 // Note that we only need to do this for base. The encoding shift would be the
5517 // same between build time and runtime: the standard precomputed shift.
5518 assert(shift == ArchiveBuilder::precomputed_narrow_klass_shift(), "unexpected compressed klass shift!");
5519 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5520 ldr(tmp, tmp);
5521 sub(dst, src, tmp);
5522 lsr(dst, dst, shift);
5523 return;
5524 }
5525
5526 switch (decode_mode) {
5527 case KlassDecodeZero:
5528 lsr(dst, src, shift);
5529 break;
5530
5531 case KlassDecodeXor:
5532 eor(dst, src, (uint64_t)base);
5533 lsr(dst, dst, shift);
5534 break;
5535
5536 case KlassDecodeMovk:
5537 if (shift != 0) {
5538 ubfx(dst, src, shift, 32);
5539 } else {
5540 movw(dst, src);
5541 }
5542 break;
5543
5544 case KlassDecodeFallback: {
5545 mov(tmp, base);
5546 sub(dst, src, tmp);
5547 lsr(dst, dst, shift);
5548 break;
5549 }
5550
5551 case KlassDecodeNone:
5552 ShouldNotReachHere();
5553 break;
5554 }
5555
5556 #ifdef ASSERT
5557 if (tmp != dst) {
5558 mov(tmp, 0xdead);
5559 }
5560 #endif // ASSERT
5561
5562 }
5563
5564 void MacroAssembler::decode_klass_not_null(Register dst, Register src, Register tmp) {
5565 emit_decode_klass_not_null(dst, src, tmp,
5566 CompressedKlassPointers::base(),
5567 CompressedKlassPointers::shift(),
5568 klass_decode_mode());
5569 }
5570
5571 void MacroAssembler::emit_decode_klass_not_null(Register dst, Register src, Register tmp,
5572 address base, int shift, KlassDecodeMode decode_mode) {
5573
5574 assert_different_registers(tmp, src);
5575 assert(tmp != noreg, "valid tmp required");
5576
5577 if (AOTCodeCache::is_on_for_dump()) {
5578 // We are generating code during AOT buildup that will run in *future* processes
5579 // with likely different encoding settings. Therefore, we have to load the
5580 // encoding base dynamically, we cannot just bake it in as immediate.
5581 // Note that we only need to do this for base. The encoding shift would be the
5582 // same between build time and runtime: the standard precomputed shift.
5583 assert(shift == ArchiveBuilder::precomputed_narrow_klass_shift(), "unexpected compressed klass shift!");
5584 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5585 ldr(tmp, tmp);
5586 add(dst, tmp, src, LSL, shift);
5587 return;
5588 }
5589
5590 switch (decode_mode) {
5591 case KlassDecodeZero: // 0-1 instructions
5592 lsl(dst, src, shift);
5593 break;
5594
5595 case KlassDecodeXor: // 1-2 instructions
5596 lsl(dst, src, shift);
5597 eor(dst, dst, (uint64_t)base);
5598 break;
5599
5600 case KlassDecodeMovk: { // 1-3 instructions
5601 const uint64_t shifted_base =
5602 (uint64_t)base >> shift;
5603
5604 if (dst != src) movw(dst, src);
5605 movk(dst, shifted_base >> 32, 32);
5606 lsl(dst, dst, shift);
5607 break;
5608 }
5609
5610 case KlassDecodeFallback: { // 3-4 instructions
5611 mov(tmp, base);
5612 add(dst, tmp, src, LSL, shift);
5613 break;
5614 }
5615
5616 case KlassDecodeNone:
5617 ShouldNotReachHere();
5618 break;
5619 }
5620
5621 #ifdef ASSERT
5622 // Always clobber tmp
5623 if (tmp != dst) {
5624 mov(tmp, 0xdead);
5625 }
5626 #endif // ASSERT
5627
5628 }
5629
5630 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5631 #ifdef ASSERT
5632 {
5633 ThreadInVMfromUnknown tiv;
5634 assert (UseCompressedOops, "should only be used for compressed oops");
5635 assert (Universe::heap() != nullptr, "java heap should be initialized");
5636 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5637 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5638 }
5639 #endif
5640 int oop_index = oop_recorder()->find_index(obj);
5641 InstructionMark im(this);
5642 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5643 code_section()->relocate(inst_mark(), rspec);
5644 movz(dst, 0xDEAD, 16);
5645 movk(dst, 0xBEEF);
5646 }
5647
5648 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5649 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5650 int index = oop_recorder()->find_index(k);
5651
5652 InstructionMark im(this);
5653 RelocationHolder rspec = metadata_Relocation::spec(index);
5654 code_section()->relocate(inst_mark(), rspec);
5655 narrowKlass nk = CompressedKlassPointers::encode(k);
5656 movz(dst, (nk >> 16), 16);
5657 movk(dst, nk & 0xffff);
5658 }
5659
5660 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
5661 Register dst, Address src,
5662 Register tmp1, Register tmp2) {
5663 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5664 decorators = AccessInternal::decorator_fixup(decorators, type);
5665 bool as_raw = (decorators & AS_RAW) != 0;
5666 if (as_raw) {
5667 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5668 } else {
5669 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5670 }
5671 }
5672
5673 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5674 Address dst, Register val,
5675 Register tmp1, Register tmp2, Register tmp3) {
5676 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5677 decorators = AccessInternal::decorator_fixup(decorators, type);
5678 bool as_raw = (decorators & AS_RAW) != 0;
5679 if (as_raw) {
5680 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5681 } else {
5682 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5683 }
5684 }
5685
5686 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
5687 Register inline_layout_info) {
5688 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5689 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
5690 }
5691
5692 void MacroAssembler::payload_offset(Register inline_klass, Register offset) {
5693 ldr(offset, Address(inline_klass, InlineKlass::adr_members_offset()));
5694 ldrw(offset, Address(offset, InlineKlass::payload_offset_offset()));
5695 }
5696
5697 void MacroAssembler::payload_address(Register oop, Register data, Register inline_klass) {
5698 // ((address) (void*) o) + vk->payload_offset();
5699 Register offset = (data == oop) ? rscratch1 : data;
5700 payload_offset(inline_klass, offset);
5701 if (data == oop) {
5702 add(data, data, offset);
5703 } else {
5704 lea(data, Address(oop, offset));
5705 }
5706 }
5707
5708 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5709 Register tmp2, DecoratorSet decorators) {
5710 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5711 }
5712
5713 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5714 Register tmp2, DecoratorSet decorators) {
5715 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5716 }
5717
5718 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5719 Register tmp2, Register tmp3, DecoratorSet decorators) {
5720 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5721 }
5722
5723 // Used for storing nulls.
5724 void MacroAssembler::store_heap_oop_null(Address dst) {
5725 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5726 }
5727
5728 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
5729 assert(oop_recorder() != nullptr, "this assembler needs a Recorder");
5730 int index = oop_recorder()->allocate_metadata_index(obj);
5731 RelocationHolder rspec = metadata_Relocation::spec(index);
5732 return Address((address)obj, rspec);
5733 }
5734
5735 // Move an oop into a register.
5736 void MacroAssembler::movoop(Register dst, jobject obj) {
5737 int oop_index;
5738 if (obj == nullptr) {
5739 oop_index = oop_recorder()->allocate_oop_index(obj);
5740 } else {
5741 #ifdef ASSERT
5742 {
5743 ThreadInVMfromUnknown tiv;
5744 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5745 }
5746 #endif
5747 oop_index = oop_recorder()->find_index(obj);
5748 }
5749 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5750
5751 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
5752 mov(dst, Address((address)obj, rspec));
5753 } else {
5754 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
5755 ldr(dst, Address(dummy, rspec));
5756 }
5757 }
5758
5759 // Move a metadata address into a register.
5760 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
5761 int oop_index;
5762 if (obj == nullptr) {
5763 oop_index = oop_recorder()->allocate_metadata_index(obj);
5764 } else {
5765 oop_index = oop_recorder()->find_index(obj);
5766 }
5767 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5768 mov(dst, Address((address)obj, rspec));
5769 }
5770
5771 Address MacroAssembler::constant_oop_address(jobject obj) {
5772 #ifdef ASSERT
5773 {
5774 ThreadInVMfromUnknown tiv;
5775 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5776 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5777 }
5778 #endif
5779 int oop_index = oop_recorder()->find_index(obj);
5780 return Address((address)obj, oop_Relocation::spec(oop_index));
5781 }
5782
5783 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5784 void MacroAssembler::tlab_allocate(Register obj,
5785 Register var_size_in_bytes,
5786 int con_size_in_bytes,
5787 Register t1,
5788 Register t2,
5789 Label& slow_case) {
5790 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5791 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5792 }
5793
5794 void MacroAssembler::verify_tlab() {
5795 #ifdef ASSERT
5796 if (UseTLAB && VerifyOops) {
5797 Label next, ok;
5798
5799 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5800
5801 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5802 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5803 cmp(rscratch2, rscratch1);
5804 br(Assembler::HS, next);
5805 STOP("assert(top >= start)");
5806 should_not_reach_here();
5807
5808 bind(next);
5809 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5810 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5811 cmp(rscratch2, rscratch1);
5812 br(Assembler::HS, ok);
5813 STOP("assert(top <= end)");
5814 should_not_reach_here();
5815
5816 bind(ok);
5817 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5818 }
5819 #endif
5820 }
5821
5822 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
5823 assert_different_registers(holder_klass, index, layout_info);
5824 InlineLayoutInfo array[2];
5825 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
5826 if (is_power_of_2(size)) {
5827 lsl(index, index, log2i_exact(size)); // Scale index by power of 2
5828 } else {
5829 mov(layout_info, size);
5830 mul(index, index, layout_info); // Scale the index to be the entry index * array_element_size
5831 }
5832 ldr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
5833 add(layout_info, layout_info, Array<InlineLayoutInfo>::base_offset_in_bytes());
5834 lea(layout_info, Address(layout_info, index));
5835 }
5836
5837 // Writes to stack successive pages until offset reached to check for
5838 // stack overflow + shadow pages. This clobbers tmp.
5839 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5840 assert_different_registers(tmp, size, rscratch1);
5841 mov(tmp, sp);
5842 // Bang stack for total size given plus shadow page size.
5843 // Bang one page at a time because large size can bang beyond yellow and
5844 // red zones.
5845 Label loop;
5846 mov(rscratch1, (int)os::vm_page_size());
5847 bind(loop);
5848 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5849 subsw(size, size, rscratch1);
5850 str(size, Address(tmp));
5851 br(Assembler::GT, loop);
5852
5853 // Bang down shadow pages too.
5854 // At this point, (tmp-0) is the last address touched, so don't
5855 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5856 // was post-decremented.) Skip this address by starting at i=1, and
5857 // touch a few more pages below. N.B. It is important to touch all
5858 // the way down to and including i=StackShadowPages.
5859 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) {
5860 // this could be any sized move but this is can be a debugging crumb
5861 // so the bigger the better.
5862 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5863 str(size, Address(tmp));
5864 }
5865 }
5866
5867 // Move the address of the polling page into dest.
5868 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) {
5869 ldr(dest, Address(rthread, JavaThread::polling_page_offset()));
5870 }
5871
5872 // Read the polling page. The address of the polling page must
5873 // already be in r.
5874 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
5875 address mark;
5876 {
5877 InstructionMark im(this);
5878 code_section()->relocate(inst_mark(), rtype);
5879 ldrw(zr, Address(r, 0));
5880 mark = inst_mark();
5881 }
5882 verify_cross_modify_fence_not_required();
5883 return mark;
5884 }
5885
5886 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
5887 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
5888 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
5889 uint64_t dest_page = (uint64_t)dest.target() >> 12;
5890 int64_t offset_low = dest_page - low_page;
5891 int64_t offset_high = dest_page - high_page;
5892
5893 assert(is_valid_AArch64_address(dest.target()), "bad address");
5894 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
5895
5896 InstructionMark im(this);
5897 code_section()->relocate(inst_mark(), dest.rspec());
5898 // 8143067: Ensure that the adrp can reach the dest from anywhere within
5899 // the code cache so that if it is relocated we know it will still reach
5900 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
5901 _adrp(reg1, dest.target());
5902 } else {
5903 uint64_t target = (uint64_t)dest.target();
5904 uint64_t adrp_target
5905 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
5906
5907 _adrp(reg1, (address)adrp_target);
5908 movk(reg1, target >> 32, 32);
5909 }
5910 byte_offset = (uint64_t)dest.target() & 0xfff;
5911 }
5912
5913 void MacroAssembler::load_byte_map_base(Register reg) {
5914 #if INCLUDE_CDS
5915 if (AOTCodeCache::is_on_for_dump()) {
5916 address byte_map_base_adr = AOTRuntimeConstants::card_table_base_address();
5917 lea(reg, ExternalAddress(byte_map_base_adr));
5918 ldr(reg, Address(reg));
5919 return;
5920 }
5921 #endif
5922 CardTableBarrierSet* ctbs = CardTableBarrierSet::barrier_set();
5923
5924 // Strictly speaking the card table base isn't an address at all, and it might
5925 // even be negative. It is thus materialised as a constant.
5926 mov(reg, (uint64_t)ctbs->card_table_base_const());
5927 }
5928
5929 void MacroAssembler::load_aotrc_address(Register reg, address a) {
5930 #if INCLUDE_CDS
5931 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
5932 if (AOTCodeCache::is_on_for_dump()) {
5933 // all aotrc field addresses should be registered in the AOTCodeCache address table
5934 lea(reg, ExternalAddress(a));
5935 } else {
5936 mov(reg, (uint64_t)a);
5937 }
5938 #else
5939 ShouldNotReachHere();
5940 #endif
5941 }
5942
5943 #ifdef ASSERT
5944 void MacroAssembler::build_frame(int framesize) {
5945 build_frame(framesize, false);
5946 }
5947 #endif
5948
5949 void MacroAssembler::build_frame(int framesize DEBUG_ONLY(COMMA bool zap_rfp_lr_spills)) {
5950 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5951 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5952 protect_return_address();
5953 if (framesize < ((1 << 9) + 2 * wordSize)) {
5954 sub(sp, sp, framesize);
5955 if (DEBUG_ONLY(zap_rfp_lr_spills ||) false) {
5956 mov_immediate64(rscratch1, ((uint64_t)badRegWordVal) << 32 | (uint64_t)badRegWordVal);
5957 stp(rscratch1, rscratch1, Address(sp, framesize - 2 * wordSize));
5958 } else {
5959 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5960 }
5961 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
5962 } else {
5963 if (DEBUG_ONLY(zap_rfp_lr_spills ||) false) {
5964 mov_immediate64(rscratch1, ((uint64_t)badRegWordVal) << 32 | (uint64_t)badRegWordVal);
5965 stp(rscratch1, rscratch1, Address(pre(sp, -2 * wordSize)));
5966 } else {
5967 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
5968 }
5969 if (PreserveFramePointer) mov(rfp, sp);
5970 if (framesize < ((1 << 12) + 2 * wordSize))
5971 sub(sp, sp, framesize - 2 * wordSize);
5972 else {
5973 mov(rscratch1, framesize - 2 * wordSize);
5974 sub(sp, sp, rscratch1);
5975 }
5976 }
5977 verify_cross_modify_fence_not_required();
5978 }
5979
5980 void MacroAssembler::remove_frame(int framesize) {
5981 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5982 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5983 if (framesize < ((1 << 9) + 2 * wordSize)) {
5984 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5985 add(sp, sp, framesize);
5986 } else {
5987 if (framesize < ((1 << 12) + 2 * wordSize))
5988 add(sp, sp, framesize - 2 * wordSize);
5989 else {
5990 mov(rscratch1, framesize - 2 * wordSize);
5991 add(sp, sp, rscratch1);
5992 }
5993 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5994 }
5995 authenticate_return_address();
5996 }
5997
5998 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
5999 if (needs_stack_repair) {
6000 // The method has a scalarized entry point (where fields of value object arguments
6001 // are passed through registers and stack), and a non-scalarized entry point (where
6002 // value object arguments are given as oops). The non-scalarized entry point will
6003 // first load each field of value object arguments and store them in registers and on
6004 // the stack in a way compatible with the scalarized entry point. To do so, some extra
6005 // stack space might be reserved (if argument registers are not enough). On leaving the
6006 // method, this space must be freed.
6007 //
6008 // In case we used the non-scalarized entry point the stack looks like this:
6009 //
6010 // | Arguments from caller |
6011 // |---------------------------| <-- caller's SP
6012 // | Saved LR #1 |
6013 // | Saved FP #1 |
6014 // |---------------------------|
6015 // | Extension space for |
6016 // | inline arg (un)packing |
6017 // |---------------------------| <-- start of this method's frame
6018 // | Saved LR #2 |
6019 // | Saved FP #2 |
6020 // |---------------------------| <-- FP (with -XX:+PreserveFramePointer)
6021 // | sp_inc |
6022 // | method locals |
6023 // |---------------------------| <-- SP
6024 //
6025 // There are two copies of FP and LR on the stack. They will be identical at
6026 // first, but that can change.
6027 // If the caller has been deoptimized, LR #1 will be patched to point at the
6028 // deopt blob, and LR #2 will still point into the old method.
6029 // If the saved FP (x29) was not used as the frame pointer, but to store an
6030 // oop, the GC will be aware only of FP #1 as the spilled location of x29 and
6031 // will fix only this one. Overall, FP/LR #2 are not reliable and are simply
6032 // needed to add space between the extension space and the locals, as there
6033 // would be between the real arguments and the locals if we don't need to
6034 // do unpacking (from the scalarized entry point).
6035 //
6036 // When restoring, one must then load FP #1 into x29, and LR #1 into x30,
6037 // while keeping in mind that from the scalarized entry point, there will be
6038 // only one copy of each. Indeed, in the case we used the scalarized calling
6039 // convention, the stack looks like this:
6040 //
6041 // | Arguments from caller |
6042 // |---------------------------| <-- caller's SP / start of this method's frame
6043 // | Saved LR |
6044 // | Saved FP |
6045 // |---------------------------| <-- FP (with -XX:+PreserveFramePointer)
6046 // | sp_inc |
6047 // | method locals |
6048 // |---------------------------| <-- SP
6049 //
6050 // The sp_inc stack slot holds the total size of the frame including the
6051 // extension space minus two words for the saved FP and LR. That is how to
6052 // find FP/LR #1. This size is expressed in bytes. Be careful when using it
6053 // from C++ in pointer arithmetic; you might need to divide it by wordSize.
6054 //
6055 // One can find sp_inc since the start the method's frame is SP + initial_framesize.
6056
6057 int sp_inc_offset = initial_framesize - 3 * wordSize; // Immediately below saved LR and FP
6058
6059 ldr(rscratch1, Address(sp, sp_inc_offset));
6060 add(sp, sp, rscratch1);
6061 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6062 } else {
6063 remove_frame(initial_framesize);
6064 }
6065 }
6066
6067 void MacroAssembler::save_stack_increment(int sp_inc, int frame_size) {
6068 int real_frame_size = frame_size + sp_inc;
6069 assert(sp_inc == 0 || sp_inc > 2*wordSize, "invalid sp_inc value");
6070 assert(real_frame_size >= 2*wordSize, "frame size must include FP/LR space");
6071 assert((real_frame_size & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6072
6073 int sp_inc_offset = frame_size - 3 * wordSize; // Immediately below saved LR and FP
6074
6075 // Subtract two words for the saved FP and LR as these will be popped
6076 // separately. See remove_frame above.
6077 mov(rscratch1, real_frame_size - 2*wordSize);
6078 str(rscratch1, Address(sp, sp_inc_offset));
6079 }
6080
6081 // This method counts leading positive bytes (highest bit not set) in provided byte array
6082 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
6083 // Simple and most common case of aligned small array which is not at the
6084 // end of memory page is placed here. All other cases are in stub.
6085 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
6086 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
6087 assert_different_registers(ary1, len, result);
6088
6089 mov(result, len);
6090 cmpw(len, 0);
6091 br(LE, DONE);
6092 cmpw(len, 4 * wordSize);
6093 br(GE, STUB_LONG); // size > 32 then go to stub
6094
6095 int shift = 64 - exact_log2(os::vm_page_size());
6096 lsl(rscratch1, ary1, shift);
6097 mov(rscratch2, (size_t)(4 * wordSize) << shift);
6098 adds(rscratch2, rscratch1, rscratch2); // At end of page?
6099 br(CS, STUB); // at the end of page then go to stub
6100 subs(len, len, wordSize);
6101 br(LT, END);
6102
6103 BIND(LOOP);
6104 ldr(rscratch1, Address(post(ary1, wordSize)));
6105 tst(rscratch1, UPPER_BIT_MASK);
6106 br(NE, SET_RESULT);
6107 subs(len, len, wordSize);
6108 br(GE, LOOP);
6109 cmpw(len, -wordSize);
6110 br(EQ, DONE);
6111
6112 BIND(END);
6113 ldr(rscratch1, Address(ary1));
6114 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
6115 lslv(rscratch1, rscratch1, rscratch2);
6116 tst(rscratch1, UPPER_BIT_MASK);
6117 br(NE, SET_RESULT);
6118 b(DONE);
6119
6120 BIND(STUB);
6121 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives());
6122 assert(count_pos.target() != nullptr, "count_positives stub has not been generated");
6123 address tpc1 = trampoline_call(count_pos);
6124 if (tpc1 == nullptr) {
6125 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE));
6126 postcond(pc() == badAddress);
6127 return nullptr;
6128 }
6129 b(DONE);
6130
6131 BIND(STUB_LONG);
6132 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long());
6133 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated");
6134 address tpc2 = trampoline_call(count_pos_long);
6135 if (tpc2 == nullptr) {
6136 DEBUG_ONLY(reset_labels(SET_RESULT, DONE));
6137 postcond(pc() == badAddress);
6138 return nullptr;
6139 }
6140 b(DONE);
6141
6142 BIND(SET_RESULT);
6143
6144 add(len, len, wordSize);
6145 sub(result, result, len);
6146
6147 BIND(DONE);
6148 postcond(pc() != badAddress);
6149 return pc();
6150 }
6151
6152 // Clobbers: rscratch1, rscratch2, rflags
6153 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals)
6154 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
6155 Register tmp4, Register tmp5, Register result,
6156 Register cnt1, int elem_size) {
6157 Label DONE, SAME;
6158 Register tmp1 = rscratch1;
6159 Register tmp2 = rscratch2;
6160 int elem_per_word = wordSize/elem_size;
6161 int log_elem_size = exact_log2(elem_size);
6162 int klass_offset = arrayOopDesc::klass_offset_in_bytes();
6163 int length_offset = arrayOopDesc::length_offset_in_bytes();
6164 int base_offset
6165 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
6166 // When the length offset is not aligned to 8 bytes,
6167 // then we align it down. This is valid because the new
6168 // offset will always be the klass which is the same
6169 // for type arrays.
6170 int start_offset = align_down(length_offset, BytesPerWord);
6171 int extra_length = base_offset - start_offset;
6172 assert(start_offset == length_offset || start_offset == klass_offset,
6173 "start offset must be 8-byte-aligned or be the klass offset");
6174 assert(base_offset != start_offset, "must include the length field");
6175 extra_length = extra_length / elem_size; // We count in elements, not bytes.
6176 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
6177
6178 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
6179 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
6180
6181 #ifndef PRODUCT
6182 {
6183 const char kind = (elem_size == 2) ? 'U' : 'L';
6184 char comment[64];
6185 os::snprintf_checked(comment, sizeof comment, "array_equals%c{", kind);
6186 BLOCK_COMMENT(comment);
6187 }
6188 #endif
6189
6190 // if (a1 == a2)
6191 // return true;
6192 cmpoop(a1, a2); // May have read barriers for a1 and a2.
6193 br(EQ, SAME);
6194
6195 if (UseSimpleArrayEquals) {
6196 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
6197 // if (a1 == nullptr || a2 == nullptr)
6198 // return false;
6199 // a1 & a2 == 0 means (some-pointer is null) or
6200 // (very-rare-or-even-probably-impossible-pointer-values)
6201 // so, we can save one branch in most cases
6202 tst(a1, a2);
6203 mov(result, false);
6204 br(EQ, A_MIGHT_BE_NULL);
6205 // if (a1.length != a2.length)
6206 // return false;
6207 bind(A_IS_NOT_NULL);
6208 ldrw(cnt1, Address(a1, length_offset));
6209 ldrw(tmp5, Address(a2, length_offset));
6210 cmp(cnt1, tmp5);
6211 br(NE, DONE); // If lengths differ, return false
6212 // Increase loop counter by diff between base- and actual start-offset.
6213 addw(cnt1, cnt1, extra_length);
6214 lea(a1, Address(a1, start_offset));
6215 lea(a2, Address(a2, start_offset));
6216 // Check for short strings, i.e. smaller than wordSize.
6217 subs(cnt1, cnt1, elem_per_word);
6218 br(Assembler::LT, SHORT);
6219 // Main 8 byte comparison loop.
6220 bind(NEXT_WORD); {
6221 ldr(tmp1, Address(post(a1, wordSize)));
6222 ldr(tmp2, Address(post(a2, wordSize)));
6223 subs(cnt1, cnt1, elem_per_word);
6224 eor(tmp5, tmp1, tmp2);
6225 cbnz(tmp5, DONE);
6226 } br(GT, NEXT_WORD);
6227 // Last longword. In the case where length == 4 we compare the
6228 // same longword twice, but that's still faster than another
6229 // conditional branch.
6230 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6231 // length == 4.
6232 if (log_elem_size > 0)
6233 lsl(cnt1, cnt1, log_elem_size);
6234 ldr(tmp3, Address(a1, cnt1));
6235 ldr(tmp4, Address(a2, cnt1));
6236 eor(tmp5, tmp3, tmp4);
6237 cbnz(tmp5, DONE);
6238 b(SAME);
6239 bind(A_MIGHT_BE_NULL);
6240 // in case both a1 and a2 are not-null, proceed with loads
6241 cbz(a1, DONE);
6242 cbz(a2, DONE);
6243 b(A_IS_NOT_NULL);
6244 bind(SHORT);
6245
6246 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
6247 {
6248 ldrw(tmp1, Address(post(a1, 4)));
6249 ldrw(tmp2, Address(post(a2, 4)));
6250 eorw(tmp5, tmp1, tmp2);
6251 cbnzw(tmp5, DONE);
6252 }
6253 bind(TAIL03);
6254 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
6255 {
6256 ldrh(tmp3, Address(post(a1, 2)));
6257 ldrh(tmp4, Address(post(a2, 2)));
6258 eorw(tmp5, tmp3, tmp4);
6259 cbnzw(tmp5, DONE);
6260 }
6261 bind(TAIL01);
6262 if (elem_size == 1) { // Only needed when comparing byte arrays.
6263 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6264 {
6265 ldrb(tmp1, a1);
6266 ldrb(tmp2, a2);
6267 eorw(tmp5, tmp1, tmp2);
6268 cbnzw(tmp5, DONE);
6269 }
6270 }
6271 } else {
6272 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
6273 CSET_EQ, LAST_CHECK;
6274 mov(result, false);
6275 cbz(a1, DONE);
6276 ldrw(cnt1, Address(a1, length_offset));
6277 cbz(a2, DONE);
6278 ldrw(tmp5, Address(a2, length_offset));
6279 cmp(cnt1, tmp5);
6280 br(NE, DONE); // If lengths differ, return false
6281 // Increase loop counter by diff between base- and actual start-offset.
6282 addw(cnt1, cnt1, extra_length);
6283
6284 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
6285 // faster to perform another branch before comparing a1 and a2
6286 cmp(cnt1, (u1)elem_per_word);
6287 br(LE, SHORT); // short or same
6288 ldr(tmp3, Address(pre(a1, start_offset)));
6289 subs(zr, cnt1, stubBytesThreshold);
6290 br(GE, STUB);
6291 ldr(tmp4, Address(pre(a2, start_offset)));
6292 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6293
6294 // Main 16 byte comparison loop with 2 exits
6295 bind(NEXT_DWORD); {
6296 ldr(tmp1, Address(pre(a1, wordSize)));
6297 ldr(tmp2, Address(pre(a2, wordSize)));
6298 subs(cnt1, cnt1, 2 * elem_per_word);
6299 br(LE, TAIL);
6300 eor(tmp4, tmp3, tmp4);
6301 cbnz(tmp4, DONE);
6302 ldr(tmp3, Address(pre(a1, wordSize)));
6303 ldr(tmp4, Address(pre(a2, wordSize)));
6304 cmp(cnt1, (u1)elem_per_word);
6305 br(LE, TAIL2);
6306 cmp(tmp1, tmp2);
6307 } br(EQ, NEXT_DWORD);
6308 b(DONE);
6309
6310 bind(TAIL);
6311 eor(tmp4, tmp3, tmp4);
6312 eor(tmp2, tmp1, tmp2);
6313 lslv(tmp2, tmp2, tmp5);
6314 orr(tmp5, tmp4, tmp2);
6315 cmp(tmp5, zr);
6316 b(CSET_EQ);
6317
6318 bind(TAIL2);
6319 eor(tmp2, tmp1, tmp2);
6320 cbnz(tmp2, DONE);
6321 b(LAST_CHECK);
6322
6323 bind(STUB);
6324 ldr(tmp4, Address(pre(a2, start_offset)));
6325 if (elem_size == 2) { // convert to byte counter
6326 lsl(cnt1, cnt1, 1);
6327 }
6328 eor(tmp5, tmp3, tmp4);
6329 cbnz(tmp5, DONE);
6330 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
6331 assert(stub.target() != nullptr, "array_equals_long stub has not been generated");
6332 address tpc = trampoline_call(stub);
6333 if (tpc == nullptr) {
6334 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
6335 postcond(pc() == badAddress);
6336 return nullptr;
6337 }
6338 b(DONE);
6339
6340 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
6341 // so, if a2 == null => return false(0), else return true, so we can return a2
6342 mov(result, a2);
6343 b(DONE);
6344 bind(SHORT);
6345 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6346 ldr(tmp3, Address(a1, start_offset));
6347 ldr(tmp4, Address(a2, start_offset));
6348 bind(LAST_CHECK);
6349 eor(tmp4, tmp3, tmp4);
6350 lslv(tmp5, tmp4, tmp5);
6351 cmp(tmp5, zr);
6352 bind(CSET_EQ);
6353 cset(result, EQ);
6354 b(DONE);
6355 }
6356
6357 bind(SAME);
6358 mov(result, true);
6359 // That's it.
6360 bind(DONE);
6361
6362 BLOCK_COMMENT("} array_equals");
6363 postcond(pc() != badAddress);
6364 return pc();
6365 }
6366
6367 // Compare Strings
6368
6369 // For Strings we're passed the address of the first characters in a1
6370 // and a2 and the length in cnt1.
6371 // There are two implementations. For arrays >= 8 bytes, all
6372 // comparisons (including the final one, which may overlap) are
6373 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
6374 // halfword, then a short, and then a byte.
6375
6376 void MacroAssembler::string_equals(Register a1, Register a2,
6377 Register result, Register cnt1)
6378 {
6379 Label SAME, DONE, SHORT, NEXT_WORD;
6380 Register tmp1 = rscratch1;
6381 Register tmp2 = rscratch2;
6382
6383 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
6384
6385 #ifndef PRODUCT
6386 {
6387 char comment[64];
6388 os::snprintf_checked(comment, sizeof comment, "{string_equalsL");
6389 BLOCK_COMMENT(comment);
6390 }
6391 #endif
6392
6393 mov(result, false);
6394
6395 // Check for short strings, i.e. smaller than wordSize.
6396 subs(cnt1, cnt1, wordSize);
6397 br(Assembler::LT, SHORT);
6398 // Main 8 byte comparison loop.
6399 bind(NEXT_WORD); {
6400 ldr(tmp1, Address(post(a1, wordSize)));
6401 ldr(tmp2, Address(post(a2, wordSize)));
6402 subs(cnt1, cnt1, wordSize);
6403 eor(tmp1, tmp1, tmp2);
6404 cbnz(tmp1, DONE);
6405 } br(GT, NEXT_WORD);
6406 // Last longword. In the case where length == 4 we compare the
6407 // same longword twice, but that's still faster than another
6408 // conditional branch.
6409 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6410 // length == 4.
6411 ldr(tmp1, Address(a1, cnt1));
6412 ldr(tmp2, Address(a2, cnt1));
6413 eor(tmp2, tmp1, tmp2);
6414 cbnz(tmp2, DONE);
6415 b(SAME);
6416
6417 bind(SHORT);
6418 Label TAIL03, TAIL01;
6419
6420 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
6421 {
6422 ldrw(tmp1, Address(post(a1, 4)));
6423 ldrw(tmp2, Address(post(a2, 4)));
6424 eorw(tmp1, tmp1, tmp2);
6425 cbnzw(tmp1, DONE);
6426 }
6427 bind(TAIL03);
6428 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
6429 {
6430 ldrh(tmp1, Address(post(a1, 2)));
6431 ldrh(tmp2, Address(post(a2, 2)));
6432 eorw(tmp1, tmp1, tmp2);
6433 cbnzw(tmp1, DONE);
6434 }
6435 bind(TAIL01);
6436 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6437 {
6438 ldrb(tmp1, a1);
6439 ldrb(tmp2, a2);
6440 eorw(tmp1, tmp1, tmp2);
6441 cbnzw(tmp1, DONE);
6442 }
6443 // Arrays are equal.
6444 bind(SAME);
6445 mov(result, true);
6446
6447 // That's it.
6448 bind(DONE);
6449 BLOCK_COMMENT("} string_equals");
6450 }
6451
6452
6453 // The size of the blocks erased by the zero_blocks stub. We must
6454 // handle anything smaller than this ourselves in zero_words().
6455 const int MacroAssembler::zero_words_block_size = 8;
6456
6457 // zero_words() is used by C2 ClearArray patterns and by
6458 // C1_MacroAssembler. It is as small as possible, handling small word
6459 // counts locally and delegating anything larger to the zero_blocks
6460 // stub. It is expanded many times in compiled code, so it is
6461 // important to keep it short.
6462
6463 // ptr: Address of a buffer to be zeroed.
6464 // cnt: Count in HeapWords.
6465 //
6466 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
6467 address MacroAssembler::zero_words(Register ptr, Register cnt)
6468 {
6469 assert(is_power_of_2(zero_words_block_size), "adjust this");
6470
6471 BLOCK_COMMENT("zero_words {");
6472 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
6473 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6474 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6475
6476 subs(rscratch1, cnt, zero_words_block_size);
6477 Label around;
6478 br(LO, around);
6479 {
6480 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6481 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6482 // Make sure this is a C2 compilation. C1 allocates space only for
6483 // trampoline stubs generated by Call LIR ops, and in any case it
6484 // makes sense for a C1 compilation task to proceed as quickly as
6485 // possible.
6486 CompileTask* task;
6487 if (StubRoutines::aarch64::complete()
6488 && Thread::current()->is_Compiler_thread()
6489 && (task = ciEnv::current()->task())
6490 && is_c2_compile(task->comp_level())) {
6491 address tpc = trampoline_call(zero_blocks);
6492 if (tpc == nullptr) {
6493 DEBUG_ONLY(reset_labels(around));
6494 return nullptr;
6495 }
6496 } else {
6497 far_call(zero_blocks);
6498 }
6499 }
6500 bind(around);
6501
6502 // We have a few words left to do. zero_blocks has adjusted r10 and r11
6503 // for us.
6504 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
6505 Label l;
6506 tbz(cnt, exact_log2(i), l);
6507 for (int j = 0; j < i; j += 2) {
6508 stp(zr, zr, post(ptr, 2 * BytesPerWord));
6509 }
6510 bind(l);
6511 }
6512 {
6513 Label l;
6514 tbz(cnt, 0, l);
6515 str(zr, Address(ptr));
6516 bind(l);
6517 }
6518
6519 BLOCK_COMMENT("} zero_words");
6520 return pc();
6521 }
6522
6523 // base: Address of a buffer to be zeroed, 8 bytes aligned.
6524 // cnt: Immediate count in HeapWords.
6525 //
6526 // r10, r11, rscratch1, and rscratch2 are clobbered.
6527 address MacroAssembler::zero_words(Register base, uint64_t cnt)
6528 {
6529 assert(wordSize <= BlockZeroingLowLimit,
6530 "increase BlockZeroingLowLimit");
6531 address result = nullptr;
6532 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) {
6533 #ifndef PRODUCT
6534 {
6535 char buf[64];
6536 os::snprintf_checked(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt);
6537 BLOCK_COMMENT(buf);
6538 }
6539 #endif
6540 if (cnt >= 16) {
6541 uint64_t loops = cnt/16;
6542 if (loops > 1) {
6543 mov(rscratch2, loops - 1);
6544 }
6545 {
6546 Label loop;
6547 bind(loop);
6548 for (int i = 0; i < 16; i += 2) {
6549 stp(zr, zr, Address(base, i * BytesPerWord));
6550 }
6551 add(base, base, 16 * BytesPerWord);
6552 if (loops > 1) {
6553 subs(rscratch2, rscratch2, 1);
6554 br(GE, loop);
6555 }
6556 }
6557 }
6558 cnt %= 16;
6559 int i = cnt & 1; // store any odd word to start
6560 if (i) str(zr, Address(base));
6561 for (; i < (int)cnt; i += 2) {
6562 stp(zr, zr, Address(base, i * wordSize));
6563 }
6564 BLOCK_COMMENT("} zero_words");
6565 result = pc();
6566 } else {
6567 mov(r10, base); mov(r11, cnt);
6568 result = zero_words(r10, r11);
6569 }
6570 return result;
6571 }
6572
6573 // Zero blocks of memory by using DC ZVA.
6574 //
6575 // Aligns the base address first sufficiently for DC ZVA, then uses
6576 // DC ZVA repeatedly for every full block. cnt is the size to be
6577 // zeroed in HeapWords. Returns the count of words left to be zeroed
6578 // in cnt.
6579 //
6580 // NOTE: This is intended to be used in the zero_blocks() stub. If
6581 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
6582 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
6583 Register tmp = rscratch1;
6584 Register tmp2 = rscratch2;
6585 int zva_length = VM_Version::zva_length();
6586 Label initial_table_end, loop_zva;
6587 Label fini;
6588
6589 // Base must be 16 byte aligned. If not just return and let caller handle it
6590 tst(base, 0x0f);
6591 br(Assembler::NE, fini);
6592 // Align base with ZVA length.
6593 neg(tmp, base);
6594 andr(tmp, tmp, zva_length - 1);
6595
6596 // tmp: the number of bytes to be filled to align the base with ZVA length.
6597 add(base, base, tmp);
6598 sub(cnt, cnt, tmp, Assembler::ASR, 3);
6599 adr(tmp2, initial_table_end);
6600 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
6601 br(tmp2);
6602
6603 for (int i = -zva_length + 16; i < 0; i += 16)
6604 stp(zr, zr, Address(base, i));
6605 bind(initial_table_end);
6606
6607 sub(cnt, cnt, zva_length >> 3);
6608 bind(loop_zva);
6609 dc(Assembler::ZVA, base);
6610 subs(cnt, cnt, zva_length >> 3);
6611 add(base, base, zva_length);
6612 br(Assembler::GE, loop_zva);
6613 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
6614 bind(fini);
6615 }
6616
6617 // base: Address of a buffer to be filled, 8 bytes aligned.
6618 // cnt: Count in 8-byte unit.
6619 // value: Value to be filled with.
6620 // base will point to the end of the buffer after filling.
6621 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
6622 {
6623 // Algorithm:
6624 //
6625 // if (cnt == 0) {
6626 // return;
6627 // }
6628 // if ((p & 8) != 0) {
6629 // *p++ = v;
6630 // }
6631 //
6632 // scratch1 = cnt & 14;
6633 // cnt -= scratch1;
6634 // p += scratch1;
6635 // switch (scratch1 / 2) {
6636 // do {
6637 // cnt -= 16;
6638 // p[-16] = v;
6639 // p[-15] = v;
6640 // case 7:
6641 // p[-14] = v;
6642 // p[-13] = v;
6643 // case 6:
6644 // p[-12] = v;
6645 // p[-11] = v;
6646 // // ...
6647 // case 1:
6648 // p[-2] = v;
6649 // p[-1] = v;
6650 // case 0:
6651 // p += 16;
6652 // } while (cnt);
6653 // }
6654 // if ((cnt & 1) == 1) {
6655 // *p++ = v;
6656 // }
6657
6658 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
6659
6660 Label fini, skip, entry, loop;
6661 const int unroll = 8; // Number of stp instructions we'll unroll
6662
6663 cbz(cnt, fini);
6664 tbz(base, 3, skip);
6665 str(value, Address(post(base, 8)));
6666 sub(cnt, cnt, 1);
6667 bind(skip);
6668
6669 andr(rscratch1, cnt, (unroll-1) * 2);
6670 sub(cnt, cnt, rscratch1);
6671 add(base, base, rscratch1, Assembler::LSL, 3);
6672 adr(rscratch2, entry);
6673 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
6674 br(rscratch2);
6675
6676 bind(loop);
6677 add(base, base, unroll * 16);
6678 for (int i = -unroll; i < 0; i++)
6679 stp(value, value, Address(base, i * 16));
6680 bind(entry);
6681 subs(cnt, cnt, unroll * 2);
6682 br(Assembler::GE, loop);
6683
6684 tbz(cnt, 0, fini);
6685 str(value, Address(post(base, 8)));
6686 bind(fini);
6687 }
6688
6689 // Intrinsic for
6690 //
6691 // - sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6692 // Encodes char[] to byte[] in ISO-8859-1
6693 //
6694 // - java.lang.StringCoding#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6695 // Encodes byte[] (containing UTF-16) to byte[] in ISO-8859-1
6696 //
6697 // - java.lang.StringCoding#encodeAsciiArray0(char[] sa, int sp, byte[] da, int dp, int len)
6698 // Encodes char[] to byte[] in ASCII
6699 //
6700 // This version always returns the number of characters copied, and does not
6701 // clobber the 'len' register. A successful copy will complete with the post-
6702 // condition: 'res' == 'len', while an unsuccessful copy will exit with the
6703 // post-condition: 0 <= 'res' < 'len'.
6704 //
6705 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
6706 // degrade performance (on Ampere Altra - Neoverse N1), to an extent
6707 // beyond the acceptable, even though the footprint would be smaller.
6708 // Using 'umaxv' in the ASCII-case comes with a small penalty but does
6709 // avoid additional bloat.
6710 //
6711 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags
6712 void MacroAssembler::encode_iso_array(Register src, Register dst,
6713 Register len, Register res, bool ascii,
6714 FloatRegister vtmp0, FloatRegister vtmp1,
6715 FloatRegister vtmp2, FloatRegister vtmp3,
6716 FloatRegister vtmp4, FloatRegister vtmp5)
6717 {
6718 Register cnt = res;
6719 Register max = rscratch1;
6720 Register chk = rscratch2;
6721
6722 prfm(Address(src), PLDL1STRM);
6723 movw(cnt, len);
6724
6725 #define ASCII(insn) do { if (ascii) { insn; } } while (0)
6726
6727 Label LOOP_32, DONE_32, FAIL_32;
6728
6729 BIND(LOOP_32);
6730 {
6731 cmpw(cnt, 32);
6732 br(LT, DONE_32);
6733 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
6734 // Extract lower bytes.
6735 FloatRegister vlo0 = vtmp4;
6736 FloatRegister vlo1 = vtmp5;
6737 uzp1(vlo0, T16B, vtmp0, vtmp1);
6738 uzp1(vlo1, T16B, vtmp2, vtmp3);
6739 // Merge bits...
6740 orr(vtmp0, T16B, vtmp0, vtmp1);
6741 orr(vtmp2, T16B, vtmp2, vtmp3);
6742 // Extract merged upper bytes.
6743 FloatRegister vhix = vtmp0;
6744 uzp2(vhix, T16B, vtmp0, vtmp2);
6745 // ISO-check on hi-parts (all zero).
6746 // ASCII-check on lo-parts (no sign).
6747 FloatRegister vlox = vtmp1; // Merge lower bytes.
6748 ASCII(orr(vlox, T16B, vlo0, vlo1));
6749 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox));
6750 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox));
6751 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0));
6752 ASCII(orr(chk, chk, max));
6753 cbnz(chk, FAIL_32);
6754 subw(cnt, cnt, 32);
6755 st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
6756 b(LOOP_32);
6757 }
6758 BIND(FAIL_32);
6759 sub(src, src, 64);
6760 BIND(DONE_32);
6761
6762 Label LOOP_8, SKIP_8;
6763
6764 BIND(LOOP_8);
6765 {
6766 cmpw(cnt, 8);
6767 br(LT, SKIP_8);
6768 FloatRegister vhi = vtmp0;
6769 FloatRegister vlo = vtmp1;
6770 ld1(vtmp3, T8H, src);
6771 uzp1(vlo, T16B, vtmp3, vtmp3);
6772 uzp2(vhi, T16B, vtmp3, vtmp3);
6773 // ISO-check on hi-parts (all zero).
6774 // ASCII-check on lo-parts (no sign).
6775 ASCII(cm(LT, vtmp2, T16B, vlo));
6776 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2));
6777 ASCII(umov(max, vtmp2, B, 0));
6778 ASCII(orr(chk, chk, max));
6779 cbnz(chk, SKIP_8);
6780
6781 strd(vlo, Address(post(dst, 8)));
6782 subw(cnt, cnt, 8);
6783 add(src, src, 16);
6784 b(LOOP_8);
6785 }
6786 BIND(SKIP_8);
6787
6788 #undef ASCII
6789
6790 Label LOOP, DONE;
6791
6792 cbz(cnt, DONE);
6793 BIND(LOOP);
6794 {
6795 Register chr = rscratch1;
6796 ldrh(chr, Address(post(src, 2)));
6797 tst(chr, ascii ? 0xff80 : 0xff00);
6798 br(NE, DONE);
6799 strb(chr, Address(post(dst, 1)));
6800 subs(cnt, cnt, 1);
6801 br(GT, LOOP);
6802 }
6803 BIND(DONE);
6804 // Return index where we stopped.
6805 subw(res, len, cnt);
6806 }
6807
6808 // Inflate byte[] array to char[].
6809 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6
6810 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
6811 FloatRegister vtmp1, FloatRegister vtmp2,
6812 FloatRegister vtmp3, Register tmp4) {
6813 Label big, done, after_init, to_stub;
6814
6815 assert_different_registers(src, dst, len, tmp4, rscratch1);
6816
6817 fmovd(vtmp1, 0.0);
6818 lsrw(tmp4, len, 3);
6819 bind(after_init);
6820 cbnzw(tmp4, big);
6821 // Short string: less than 8 bytes.
6822 {
6823 Label loop, tiny;
6824
6825 cmpw(len, 4);
6826 br(LT, tiny);
6827 // Use SIMD to do 4 bytes.
6828 ldrs(vtmp2, post(src, 4));
6829 zip1(vtmp3, T8B, vtmp2, vtmp1);
6830 subw(len, len, 4);
6831 strd(vtmp3, post(dst, 8));
6832
6833 cbzw(len, done);
6834
6835 // Do the remaining bytes by steam.
6836 bind(loop);
6837 ldrb(tmp4, post(src, 1));
6838 strh(tmp4, post(dst, 2));
6839 subw(len, len, 1);
6840
6841 bind(tiny);
6842 cbnz(len, loop);
6843
6844 b(done);
6845 }
6846
6847 if (SoftwarePrefetchHintDistance >= 0) {
6848 bind(to_stub);
6849 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
6850 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated");
6851 address tpc = trampoline_call(stub);
6852 if (tpc == nullptr) {
6853 DEBUG_ONLY(reset_labels(big, done));
6854 postcond(pc() == badAddress);
6855 return nullptr;
6856 }
6857 b(after_init);
6858 }
6859
6860 // Unpack the bytes 8 at a time.
6861 bind(big);
6862 {
6863 Label loop, around, loop_last, loop_start;
6864
6865 if (SoftwarePrefetchHintDistance >= 0) {
6866 const int large_loop_threshold = (64 + 16)/8;
6867 ldrd(vtmp2, post(src, 8));
6868 andw(len, len, 7);
6869 cmp(tmp4, (u1)large_loop_threshold);
6870 br(GE, to_stub);
6871 b(loop_start);
6872
6873 bind(loop);
6874 ldrd(vtmp2, post(src, 8));
6875 bind(loop_start);
6876 subs(tmp4, tmp4, 1);
6877 br(EQ, loop_last);
6878 zip1(vtmp2, T16B, vtmp2, vtmp1);
6879 ldrd(vtmp3, post(src, 8));
6880 st1(vtmp2, T8H, post(dst, 16));
6881 subs(tmp4, tmp4, 1);
6882 zip1(vtmp3, T16B, vtmp3, vtmp1);
6883 st1(vtmp3, T8H, post(dst, 16));
6884 br(NE, loop);
6885 b(around);
6886 bind(loop_last);
6887 zip1(vtmp2, T16B, vtmp2, vtmp1);
6888 st1(vtmp2, T8H, post(dst, 16));
6889 bind(around);
6890 cbz(len, done);
6891 } else {
6892 andw(len, len, 7);
6893 bind(loop);
6894 ldrd(vtmp2, post(src, 8));
6895 sub(tmp4, tmp4, 1);
6896 zip1(vtmp3, T16B, vtmp2, vtmp1);
6897 st1(vtmp3, T8H, post(dst, 16));
6898 cbnz(tmp4, loop);
6899 }
6900 }
6901
6902 // Do the tail of up to 8 bytes.
6903 add(src, src, len);
6904 ldrd(vtmp3, Address(src, -8));
6905 add(dst, dst, len, ext::uxtw, 1);
6906 zip1(vtmp3, T16B, vtmp3, vtmp1);
6907 strq(vtmp3, Address(dst, -16));
6908
6909 bind(done);
6910 postcond(pc() != badAddress);
6911 return pc();
6912 }
6913
6914 // Compress char[] array to byte[].
6915 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
6916 // Return the array length if every element in array can be encoded,
6917 // otherwise, the index of first non-latin1 (> 0xff) character.
6918 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
6919 Register res,
6920 FloatRegister tmp0, FloatRegister tmp1,
6921 FloatRegister tmp2, FloatRegister tmp3,
6922 FloatRegister tmp4, FloatRegister tmp5) {
6923 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
6924 }
6925
6926 // java.math.round(double a)
6927 // Returns the closest long to the argument, with ties rounding to
6928 // positive infinity. This requires some fiddling for corner
6929 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5).
6930 void MacroAssembler::java_round_double(Register dst, FloatRegister src,
6931 FloatRegister ftmp) {
6932 Label DONE;
6933 BLOCK_COMMENT("java_round_double: { ");
6934 fmovd(rscratch1, src);
6935 // Use RoundToNearestTiesAway unless src small and -ve.
6936 fcvtasd(dst, src);
6937 // Test if src >= 0 || abs(src) >= 0x1.0p52
6938 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit
6939 mov(rscratch2, julong_cast(0x1.0p52));
6940 cmp(rscratch1, rscratch2);
6941 br(HS, DONE); {
6942 // src < 0 && abs(src) < 0x1.0p52
6943 // src may have a fractional part, so add 0.5
6944 fmovd(ftmp, 0.5);
6945 faddd(ftmp, src, ftmp);
6946 // Convert double to jlong, use RoundTowardsNegative
6947 fcvtmsd(dst, ftmp);
6948 }
6949 bind(DONE);
6950 BLOCK_COMMENT("} java_round_double");
6951 }
6952
6953 void MacroAssembler::java_round_float(Register dst, FloatRegister src,
6954 FloatRegister ftmp) {
6955 Label DONE;
6956 BLOCK_COMMENT("java_round_float: { ");
6957 fmovs(rscratch1, src);
6958 // Use RoundToNearestTiesAway unless src small and -ve.
6959 fcvtassw(dst, src);
6960 // Test if src >= 0 || abs(src) >= 0x1.0p23
6961 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit
6962 mov(rscratch2, jint_cast(0x1.0p23f));
6963 cmp(rscratch1, rscratch2);
6964 br(HS, DONE); {
6965 // src < 0 && |src| < 0x1.0p23
6966 // src may have a fractional part, so add 0.5
6967 fmovs(ftmp, 0.5f);
6968 fadds(ftmp, src, ftmp);
6969 // Convert float to jint, use RoundTowardsNegative
6970 fcvtmssw(dst, ftmp);
6971 }
6972 bind(DONE);
6973 BLOCK_COMMENT("} java_round_float");
6974 }
6975
6976 // get_thread() can be called anywhere inside generated code so we
6977 // need to save whatever non-callee save context might get clobbered
6978 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
6979 // the call setup code.
6980 //
6981 // On Linux and Windows, aarch64_get_thread_helper() is implemented in
6982 // assembly and clobbers only r0, r1, and flags.
6983 // On other systems, the helper is a usual C function.
6984 //
6985 void MacroAssembler::get_thread(Register dst) {
6986 RegSet saved_regs =
6987 BSD_ONLY(RegSet::range(r0, r17) + lr - dst)
6988 NOT_BSD (RegSet::range(r0, r1) + lr - dst);
6989
6990 protect_return_address();
6991 push(saved_regs, sp);
6992
6993 mov(lr, ExternalAddress(CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)));
6994 blr(lr);
6995 if (dst != c_rarg0) {
6996 mov(dst, c_rarg0);
6997 }
6998
6999 pop(saved_regs, sp);
7000 authenticate_return_address();
7001 }
7002
7003 #ifdef COMPILER2
7004 // C2 compiled method's prolog code
7005 // Moved here from aarch64.ad to support Valhalla code below
7006 void MacroAssembler::verified_entry(Compile* C, int sp_inc) {
7007 if (C->clinit_barrier_on_entry()) {
7008 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
7009
7010 Label L_skip_barrier;
7011
7012 mov_metadata(rscratch2, C->method()->holder()->constant_encoding());
7013 clinit_barrier(rscratch2, rscratch1, &L_skip_barrier);
7014 far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
7015 bind(L_skip_barrier);
7016 }
7017
7018 if (C->max_vector_size() > 0) {
7019 reinitialize_ptrue();
7020 }
7021
7022 int bangsize = C->output()->bang_size_in_bytes();
7023 if (C->output()->need_stack_bang(bangsize))
7024 generate_stack_overflow_check(bangsize);
7025
7026 // n.b. frame size includes space for return pc and rfp
7027 const long framesize = C->output()->frame_size_in_bytes();
7028 build_frame(framesize DEBUG_ONLY(COMMA sp_inc != 0));
7029
7030 if (C->needs_stack_repair()) {
7031 save_stack_increment(sp_inc, framesize);
7032 }
7033
7034 if (VerifyStackAtCalls) {
7035 Unimplemented();
7036 }
7037 }
7038 #endif // COMPILER2
7039
7040 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
7041 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
7042 // An inline type might be returned. If fields are in registers we
7043 // need to allocate an inline type instance and initialize it with
7044 // the value of the fields.
7045 Label skip;
7046 // We only need a new buffered inline type if a new one is not returned
7047 tbz(r0, 0, skip);
7048 int call_offset = -1;
7049
7050 // Be careful not to clobber r1-7 which hold returned fields
7051 // Also do not use callee-saved registers as these may be live in the interpreter
7052 Register tmp1 = r13, tmp2 = r14, klass = r15, r0_preserved = r12;
7053
7054 // The following code is similar to the instance allocation code in TemplateTable::_new
7055 // but has some slight differences,
7056 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
7057 // allocating is not necessary if vk != nullptr, etc.
7058 Label slow_case;
7059 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
7060 mov(r0_preserved, r0); // save r0 for slow_case since *_allocate may corrupt it when allocation failed
7061
7062 if (vk != nullptr) {
7063 // Called from C1, where the return type is statically known.
7064 movptr(klass, (intptr_t)vk->get_InlineKlass());
7065 jint lh = vk->layout_helper();
7066 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
7067 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
7068 tlab_allocate(r0, noreg, lh, tmp1, tmp2, slow_case);
7069 } else {
7070 b(slow_case);
7071 }
7072 } else {
7073 // Call from interpreter. R0 contains ((the InlineKlass* of the return type) | 0x01)
7074 andr(klass, r0, -2);
7075 if (UseTLAB) {
7076 ldrw(tmp2, Address(klass, Klass::layout_helper_offset()));
7077 tst(tmp2, Klass::_lh_instance_slow_path_bit);
7078 br(Assembler::NE, slow_case);
7079 tlab_allocate(r0, tmp2, 0, tmp1, tmp2, slow_case);
7080 } else {
7081 b(slow_case);
7082 }
7083 }
7084 if (UseTLAB) {
7085 // 2. Initialize buffered inline instance header
7086 Register buffer_obj = r0;
7087 if (UseCompactObjectHeaders) {
7088 ldr(rscratch1, Address(klass, Klass::prototype_header_offset()));
7089 str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes()));
7090 } else {
7091 mov(rscratch1, (intptr_t)markWord::inline_type_prototype().value());
7092 str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes()));
7093 store_klass_gap(buffer_obj, zr);
7094 if (vk == nullptr) {
7095 // store_klass corrupts klass, so save it for later use (interpreter case only).
7096 mov(tmp1, klass);
7097 }
7098 store_klass(buffer_obj, klass, rscratch1);
7099 klass = tmp1;
7100 }
7101 // 3. Initialize its fields with an inline class specific handler
7102 if (vk != nullptr) {
7103 far_call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
7104 } else {
7105 ldr(tmp1, Address(klass, InlineKlass::adr_members_offset()));
7106 ldr(tmp1, Address(tmp1, InlineKlass::pack_handler_offset()));
7107 blr(tmp1);
7108 }
7109
7110 membar(Assembler::StoreStore);
7111 b(skip);
7112 } else {
7113 // Must have already branched to slow_case above.
7114 DEBUG_ONLY(should_not_reach_here());
7115 }
7116 bind(slow_case);
7117 // We failed to allocate a new inline type, fall back to a runtime
7118 // call. Some oop field may be live in some registers but we can't
7119 // tell. That runtime call will take care of preserving them
7120 // across a GC if there's one.
7121 mov(r0, r0_preserved);
7122
7123 if (from_interpreter) {
7124 super_call_VM_leaf(SharedRuntime::store_inline_type_fields_to_buf_entry());
7125 } else {
7126 far_call(RuntimeAddress(SharedRuntime::store_inline_type_fields_to_buf_entry()));
7127 call_offset = offset();
7128 }
7129 membar(Assembler::StoreStore);
7130
7131 bind(skip);
7132 return call_offset;
7133 }
7134
7135 // Move a value between registers/stack slots and update the reg_state
7136 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
7137 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
7138 if (reg_state[to->value()] == reg_written) {
7139 return true; // Already written
7140 }
7141
7142 if (from != to && bt != T_VOID) {
7143 if (reg_state[to->value()] == reg_readonly) {
7144 return false; // Not yet writable
7145 }
7146 if (from->is_reg()) {
7147 if (to->is_reg()) {
7148 if (from->is_Register() && to->is_Register()) {
7149 mov(to->as_Register(), from->as_Register());
7150 } else if (from->is_FloatRegister() && to->is_FloatRegister()) {
7151 fmovd(to->as_FloatRegister(), from->as_FloatRegister());
7152 } else {
7153 ShouldNotReachHere();
7154 }
7155 } else {
7156 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
7157 Address to_addr = Address(sp, st_off);
7158 if (from->is_FloatRegister()) {
7159 if (bt == T_DOUBLE) {
7160 strd(from->as_FloatRegister(), to_addr);
7161 } else {
7162 assert(bt == T_FLOAT, "must be float");
7163 strs(from->as_FloatRegister(), to_addr);
7164 }
7165 } else {
7166 str(from->as_Register(), to_addr);
7167 }
7168 }
7169 } else {
7170 Address from_addr = Address(sp, from->reg2stack() * VMRegImpl::stack_slot_size);
7171 if (to->is_reg()) {
7172 if (to->is_FloatRegister()) {
7173 if (bt == T_DOUBLE) {
7174 ldrd(to->as_FloatRegister(), from_addr);
7175 } else {
7176 assert(bt == T_FLOAT, "must be float");
7177 ldrs(to->as_FloatRegister(), from_addr);
7178 }
7179 } else {
7180 ldr(to->as_Register(), from_addr);
7181 }
7182 } else {
7183 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
7184 ldr(rscratch1, from_addr);
7185 str(rscratch1, Address(sp, st_off));
7186 }
7187 }
7188 }
7189
7190 // Update register states
7191 reg_state[from->value()] = reg_writable;
7192 reg_state[to->value()] = reg_written;
7193 return true;
7194 }
7195
7196 // Calculate the extra stack space required for packing or unpacking inline
7197 // args and adjust the stack pointer
7198 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
7199 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
7200 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
7201 assert(sp_inc > 0, "sanity");
7202
7203 // Save a copy of the FP and LR here for deoptimization patching and frame walking
7204 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
7205
7206 // Adjust the stack pointer. This will be repaired on return by MacroAssembler::remove_frame
7207 if (sp_inc < (1 << 9)) {
7208 sub(sp, sp, sp_inc); // Fits in an immediate
7209 } else {
7210 mov(rscratch1, sp_inc);
7211 sub(sp, sp, rscratch1);
7212 }
7213
7214 return sp_inc + 2 * wordSize; // Account for the FP/LR space
7215 }
7216
7217 // Read all fields from an inline type oop and store the values in registers/stack slots
7218 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
7219 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
7220 RegState reg_state[]) {
7221 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
7222 assert(from->is_valid(), "source must be valid");
7223 bool progress = false;
7224 #ifdef ASSERT
7225 const int start_offset = offset();
7226 #endif
7227
7228 Label L_null, L_notNull;
7229 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
7230 Register tmp1 = r10;
7231 Register tmp2 = r11;
7232
7233 #ifdef ASSERT
7234 RegSet clobbered_gp_regs = MacroAssembler::call_clobbered_gp_registers();
7235 assert(clobbered_gp_regs.contains(tmp1), "tmp1 must be saved explicitly if it's not a clobber");
7236 assert(clobbered_gp_regs.contains(tmp2), "tmp2 must be saved explicitly if it's not a clobber");
7237 assert(clobbered_gp_regs.contains(r14), "r14 must be saved explicitly if it's not a clobber");
7238 #endif
7239
7240 Register fromReg = noreg;
7241 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, true);
7242 bool done = true;
7243 bool mark_done = true;
7244 VMReg toReg;
7245 BasicType bt;
7246 // Check if argument requires a null check
7247 bool null_check = false;
7248 VMReg nullCheckReg;
7249 while (stream.next(nullCheckReg, bt)) {
7250 if (sig->at(stream.sig_index())._offset == -1) {
7251 null_check = true;
7252 break;
7253 }
7254 }
7255 stream.reset(sig_index, to_index);
7256 while (stream.next(toReg, bt)) {
7257 assert(toReg->is_valid(), "destination must be valid");
7258 int idx = (int)toReg->value();
7259 if (reg_state[idx] == reg_readonly) {
7260 if (idx != from->value()) {
7261 mark_done = false;
7262 }
7263 done = false;
7264 continue;
7265 } else if (reg_state[idx] == reg_written) {
7266 continue;
7267 }
7268 assert(reg_state[idx] == reg_writable, "must be writable");
7269 reg_state[idx] = reg_written;
7270 progress = true;
7271
7272 if (fromReg == noreg) {
7273 if (from->is_reg()) {
7274 fromReg = from->as_Register();
7275 } else {
7276 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size;
7277 ldr(tmp1, Address(sp, st_off));
7278 fromReg = tmp1;
7279 }
7280 if (null_check) {
7281 // Nullable inline type argument, emit null check
7282 cbz(fromReg, L_null);
7283 }
7284 }
7285 int off = sig->at(stream.sig_index())._offset;
7286 if (off == -1) {
7287 assert(null_check, "Missing null check at");
7288 if (toReg->is_stack()) {
7289 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7290 mov(tmp2, 1);
7291 str(tmp2, Address(sp, st_off));
7292 } else {
7293 mov(toReg->as_Register(), 1);
7294 }
7295 continue;
7296 }
7297 if (sig->at(stream.sig_index())._vt_oop) {
7298 if (toReg->is_stack()) {
7299 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7300 str(fromReg, Address(sp, st_off));
7301 } else {
7302 mov(toReg->as_Register(), fromReg);
7303 }
7304 continue;
7305 }
7306 assert(off > 0, "offset in object should be positive");
7307 Address fromAddr = Address(fromReg, off);
7308 if (!toReg->is_FloatRegister()) {
7309 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
7310 if (is_reference_type(bt)) {
7311 load_heap_oop(dst, fromAddr, rscratch1, rscratch2);
7312 } else {
7313 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
7314 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
7315 }
7316 if (toReg->is_stack()) {
7317 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7318 str(dst, Address(sp, st_off));
7319 }
7320 } else if (bt == T_DOUBLE) {
7321 ldrd(toReg->as_FloatRegister(), fromAddr);
7322 } else {
7323 assert(bt == T_FLOAT, "must be float");
7324 ldrs(toReg->as_FloatRegister(), fromAddr);
7325 }
7326 }
7327 if (progress && null_check) {
7328 if (done) {
7329 b(L_notNull);
7330 bind(L_null);
7331 // Set null marker to zero to signal that the argument is null.
7332 // Also set all fields to zero since the runtime requires a canonical
7333 // representation of a flat null.
7334 stream.reset(sig_index, to_index);
7335 while (stream.next(toReg, bt)) {
7336 if (toReg->is_stack()) {
7337 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7338 str(zr, Address(sp, st_off));
7339 } else if (toReg->is_FloatRegister()) {
7340 mov(toReg->as_FloatRegister(), T2S, 0);
7341 } else {
7342 mov(toReg->as_Register(), zr);
7343 }
7344 }
7345 bind(L_notNull);
7346 } else {
7347 bind(L_null);
7348 }
7349 }
7350
7351 sig_index = stream.sig_index();
7352 to_index = stream.regs_index();
7353
7354 if (mark_done && reg_state[from->value()] != reg_written) {
7355 // This is okay because no one else will write to that slot
7356 reg_state[from->value()] = reg_writable;
7357 }
7358 from_index--;
7359 assert(progress || (start_offset == offset()), "should not emit code");
7360 return done;
7361 }
7362
7363 // Pack fields back into an inline type oop
7364 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
7365 VMRegPair* from, int from_count, int& from_index, VMReg to,
7366 RegState reg_state[], Register val_array) {
7367 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
7368 assert(to->is_valid(), "destination must be valid");
7369
7370 if (reg_state[to->value()] == reg_written) {
7371 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7372 return true; // Already written
7373 }
7374
7375 // The GC barrier expanded by store_heap_oop below may call into the
7376 // runtime so use callee-saved registers for any values that need to be
7377 // preserved. The GC barrier assembler should take care of saving the
7378 // Java argument registers.
7379 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
7380 Register val_obj_tmp = r21;
7381 Register from_reg_tmp = r22;
7382 Register tmp1 = r14;
7383 Register tmp2 = r13;
7384 Register tmp3 = r12;
7385 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
7386
7387 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
7388
7389 if (reg_state[to->value()] == reg_readonly) {
7390 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
7391 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7392 return false; // Not yet writable
7393 }
7394 val_obj = val_obj_tmp;
7395 }
7396
7397 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
7398 VMReg fromReg;
7399 BasicType bt;
7400 Label L_null;
7401 while (stream.next(fromReg, bt)) {
7402 assert(fromReg->is_valid(), "source must be valid");
7403 reg_state[fromReg->value()] = reg_writable;
7404
7405 int off = sig->at(stream.sig_index())._offset;
7406 if (off == -1) {
7407 // Nullable inline type argument, emit null check
7408 Label L_notNull;
7409 if (fromReg->is_stack()) {
7410 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7411 ldrb(tmp2, Address(sp, ld_off));
7412 cbnz(tmp2, L_notNull);
7413 } else {
7414 cbnz(fromReg->as_Register(), L_notNull);
7415 }
7416 mov(val_obj, 0);
7417 b(L_null);
7418 bind(L_notNull);
7419 continue;
7420 }
7421 if (sig->at(stream.sig_index())._vt_oop) {
7422 if (fromReg->is_stack()) {
7423 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7424 ldr(val_obj, Address(sp, ld_off));
7425 } else {
7426 mov(val_obj, fromReg->as_Register());
7427 }
7428 cbnz(val_obj, L_null);
7429 // get the buffer from the just allocated pool of buffers
7430 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
7431 load_heap_oop(val_obj, Address(val_array, index), rscratch1, rscratch2);
7432 continue;
7433 }
7434
7435 assert(off > 0, "offset in object should be positive");
7436 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
7437
7438 // Pack the scalarized field into the value object.
7439 Address dst(val_obj, off);
7440 if (!fromReg->is_FloatRegister()) {
7441 Register src;
7442 if (fromReg->is_stack()) {
7443 src = from_reg_tmp;
7444 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7445 load_sized_value(src, Address(sp, ld_off), size_in_bytes, /* is_signed */ false);
7446 } else {
7447 src = fromReg->as_Register();
7448 }
7449 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
7450 if (is_reference_type(bt)) {
7451 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep val_obj valid.
7452 mov(tmp3, val_obj);
7453 Address dst_with_tmp3(tmp3, off);
7454 store_heap_oop(dst_with_tmp3, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
7455 } else {
7456 store_sized_value(dst, src, size_in_bytes);
7457 }
7458 } else if (bt == T_DOUBLE) {
7459 strd(fromReg->as_FloatRegister(), dst);
7460 } else {
7461 assert(bt == T_FLOAT, "must be float");
7462 strs(fromReg->as_FloatRegister(), dst);
7463 }
7464 }
7465 bind(L_null);
7466 sig_index = stream.sig_index();
7467 from_index = stream.regs_index();
7468
7469 assert(reg_state[to->value()] == reg_writable, "must have already been read");
7470 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
7471 assert(success, "to register must be writable");
7472 return true;
7473 }
7474
7475 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
7476 return (reg->is_FloatRegister()) ? v8->as_VMReg() : r14->as_VMReg();
7477 }
7478
7479 void MacroAssembler::cache_wb(Address line) {
7480 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
7481 assert(line.index() == noreg, "index should be noreg");
7482 assert(line.offset() == 0, "offset should be 0");
7483 // would like to assert this
7484 // assert(line._ext.shift == 0, "shift should be zero");
7485 if (VM_Version::supports_dcpop()) {
7486 // writeback using clear virtual address to point of persistence
7487 dc(Assembler::CVAP, line.base());
7488 } else {
7489 // no need to generate anything as Unsafe.writebackMemory should
7490 // never invoke this stub
7491 }
7492 }
7493
7494 void MacroAssembler::cache_wbsync(bool is_pre) {
7495 // we only need a barrier post sync
7496 if (!is_pre) {
7497 membar(Assembler::AnyAny);
7498 }
7499 }
7500
7501 void MacroAssembler::verify_sve_vector_length(Register tmp) {
7502 if (!UseSVE || VM_Version::get_max_supported_sve_vector_length() == FloatRegister::sve_vl_min) {
7503 return;
7504 }
7505 // Make sure that native code does not change SVE vector length.
7506 Label verify_ok;
7507 movw(tmp, zr);
7508 sve_inc(tmp, B);
7509 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length());
7510 br(EQ, verify_ok);
7511 stop("Error: SVE vector length has changed since jvm startup");
7512 bind(verify_ok);
7513 }
7514
7515 void MacroAssembler::verify_ptrue() {
7516 Label verify_ok;
7517 if (!UseSVE) {
7518 return;
7519 }
7520 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
7521 sve_dec(rscratch1, B);
7522 cbz(rscratch1, verify_ok);
7523 stop("Error: the preserved predicate register (p7) elements are not all true");
7524 bind(verify_ok);
7525 }
7526
7527 void MacroAssembler::safepoint_isb() {
7528 isb();
7529 #ifndef PRODUCT
7530 if (VerifyCrossModifyFence) {
7531 // Clear the thread state.
7532 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
7533 }
7534 #endif
7535 }
7536
7537 #ifndef PRODUCT
7538 void MacroAssembler::verify_cross_modify_fence_not_required() {
7539 if (VerifyCrossModifyFence) {
7540 // Check if thread needs a cross modify fence.
7541 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
7542 Label fence_not_required;
7543 cbz(rscratch1, fence_not_required);
7544 // If it does then fail.
7545 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure)));
7546 mov(c_rarg0, rthread);
7547 blr(rscratch1);
7548 bind(fence_not_required);
7549 }
7550 }
7551 #endif
7552
7553 void MacroAssembler::spin_wait() {
7554 block_comment("spin_wait {");
7555 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
7556 switch (VM_Version::spin_wait_desc().inst()) {
7557 case SpinWait::NOP:
7558 nop();
7559 break;
7560 case SpinWait::ISB:
7561 isb();
7562 break;
7563 case SpinWait::YIELD:
7564 yield();
7565 break;
7566 case SpinWait::SB:
7567 assert(VM_Version::supports_sb(), "current CPU does not support SB instruction");
7568 sb();
7569 break;
7570 case SpinWait::WFET:
7571 spin_wait_wfet(VM_Version::spin_wait_desc().delay());
7572 break;
7573 default:
7574 ShouldNotReachHere();
7575 }
7576 }
7577 block_comment("}");
7578 }
7579
7580 void MacroAssembler::spin_wait_wfet(int delay_ns) {
7581 // The sequence assumes CNTFRQ_EL0 is fixed to 1GHz. The assumption is valid
7582 // starting from Armv8.6, according to the "D12.1.2 The system counter" of the
7583 // Arm Architecture Reference Manual for A-profile architecture version M.a.a.
7584 // This is sufficient because FEAT_WFXT is introduced from Armv8.6.
7585 Register target = rscratch1;
7586 Register current = rscratch2;
7587 get_cntvctss_el0(current);
7588 add(target, current, delay_ns);
7589
7590 Label L_wait_loop;
7591 bind(L_wait_loop);
7592
7593 wfet(target);
7594 get_cntvctss_el0(current);
7595
7596 cmp(current, target);
7597 br(LT, L_wait_loop);
7598
7599 sb();
7600 }
7601
7602 // Stack frame creation/removal
7603
7604 void MacroAssembler::enter(bool strip_ret_addr) {
7605 if (strip_ret_addr) {
7606 // Addresses can only be signed once. If there are multiple nested frames being created
7607 // in the same function, then the return address needs stripping first.
7608 strip_return_address();
7609 }
7610 protect_return_address();
7611 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
7612 mov(rfp, sp);
7613 }
7614
7615 void MacroAssembler::leave() {
7616 mov(sp, rfp);
7617 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
7618 authenticate_return_address();
7619 }
7620
7621 // ROP Protection
7622 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/
7623 // destroying stack frames or whenever directly loading/storing the LR to memory.
7624 // If ROP protection is not set then these functions are no-ops.
7625 // For more details on PAC see pauth_aarch64.hpp.
7626
7627 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory.
7628 // Uses value zero as the modifier.
7629 //
7630 void MacroAssembler::protect_return_address() {
7631 if (VM_Version::use_rop_protection()) {
7632 check_return_address();
7633 paciaz();
7634 }
7635 }
7636
7637 // Sign the return value in the given register. Use before updating the LR in the existing stack
7638 // frame for the current function.
7639 // Uses value zero as the modifier.
7640 //
7641 void MacroAssembler::protect_return_address(Register return_reg) {
7642 if (VM_Version::use_rop_protection()) {
7643 check_return_address(return_reg);
7644 paciza(return_reg);
7645 }
7646 }
7647
7648 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory.
7649 // Uses value zero as the modifier.
7650 //
7651 void MacroAssembler::authenticate_return_address() {
7652 if (VM_Version::use_rop_protection()) {
7653 autiaz();
7654 check_return_address();
7655 }
7656 }
7657
7658 // Authenticate the return value in the given register. Use before updating the LR in the existing
7659 // stack frame for the current function.
7660 // Uses value zero as the modifier.
7661 //
7662 void MacroAssembler::authenticate_return_address(Register return_reg) {
7663 if (VM_Version::use_rop_protection()) {
7664 autiza(return_reg);
7665 check_return_address(return_reg);
7666 }
7667 }
7668
7669 // Strip any PAC data from LR without performing any authentication. Use with caution - only if
7670 // there is no guaranteed way of authenticating the LR.
7671 //
7672 void MacroAssembler::strip_return_address() {
7673 if (VM_Version::use_rop_protection()) {
7674 xpaclri();
7675 }
7676 }
7677
7678 #ifndef PRODUCT
7679 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only
7680 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point
7681 // it is difficult to debug back to the callee function.
7682 // This function simply loads from the address in the given register.
7683 // Use directly after authentication to catch authentication failures.
7684 // Also use before signing to check that the pointer is valid and hasn't already been signed.
7685 //
7686 void MacroAssembler::check_return_address(Register return_reg) {
7687 if (VM_Version::use_rop_protection()) {
7688 ldr(zr, Address(return_reg));
7689 }
7690 }
7691 #endif
7692
7693 // The java_calling_convention describes stack locations as ideal slots on
7694 // a frame with no abi restrictions. Since we must observe abi restrictions
7695 // (like the placement of the register window) the slots must be biased by
7696 // the following value.
7697 static int reg2offset_in(VMReg r) {
7698 // Account for saved rfp and lr
7699 // This should really be in_preserve_stack_slots
7700 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
7701 }
7702
7703 static int reg2offset_out(VMReg r) {
7704 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
7705 }
7706
7707 // On 64bit we will store integer like items to the stack as
7708 // 64bits items (AArch64 ABI) even though java would only store
7709 // 32bits for a parameter. On 32bit it will simply be 32bits
7710 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
7711 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
7712 if (src.first()->is_stack()) {
7713 if (dst.first()->is_stack()) {
7714 // stack to stack
7715 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7716 str(tmp, Address(sp, reg2offset_out(dst.first())));
7717 } else {
7718 // stack to reg
7719 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
7720 }
7721 } else if (dst.first()->is_stack()) {
7722 // reg to stack
7723 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
7724 } else {
7725 if (dst.first() != src.first()) {
7726 sxtw(dst.first()->as_Register(), src.first()->as_Register());
7727 }
7728 }
7729 }
7730
7731 // An oop arg. Must pass a handle not the oop itself
7732 void MacroAssembler::object_move(
7733 OopMap* map,
7734 int oop_handle_offset,
7735 int framesize_in_slots,
7736 VMRegPair src,
7737 VMRegPair dst,
7738 bool is_receiver,
7739 int* receiver_offset) {
7740
7741 // must pass a handle. First figure out the location we use as a handle
7742
7743 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register();
7744
7745 // See if oop is null if it is we need no handle
7746
7747 if (src.first()->is_stack()) {
7748
7749 // Oop is already on the stack as an argument
7750 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
7751 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
7752 if (is_receiver) {
7753 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
7754 }
7755
7756 ldr(rscratch1, Address(rfp, reg2offset_in(src.first())));
7757 lea(rHandle, Address(rfp, reg2offset_in(src.first())));
7758 // conditionally move a null
7759 cmp(rscratch1, zr);
7760 csel(rHandle, zr, rHandle, Assembler::EQ);
7761 } else {
7762
7763 // Oop is in an a register we must store it to the space we reserve
7764 // on the stack for oop_handles and pass a handle if oop is non-null
7765
7766 const Register rOop = src.first()->as_Register();
7767 int oop_slot;
7768 if (rOop == j_rarg0)
7769 oop_slot = 0;
7770 else if (rOop == j_rarg1)
7771 oop_slot = 1;
7772 else if (rOop == j_rarg2)
7773 oop_slot = 2;
7774 else if (rOop == j_rarg3)
7775 oop_slot = 3;
7776 else if (rOop == j_rarg4)
7777 oop_slot = 4;
7778 else if (rOop == j_rarg5)
7779 oop_slot = 5;
7780 else if (rOop == j_rarg6)
7781 oop_slot = 6;
7782 else {
7783 assert(rOop == j_rarg7, "wrong register");
7784 oop_slot = 7;
7785 }
7786
7787 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
7788 int offset = oop_slot*VMRegImpl::stack_slot_size;
7789
7790 map->set_oop(VMRegImpl::stack2reg(oop_slot));
7791 // Store oop in handle area, may be null
7792 str(rOop, Address(sp, offset));
7793 if (is_receiver) {
7794 *receiver_offset = offset;
7795 }
7796
7797 cmp(rOop, zr);
7798 lea(rHandle, Address(sp, offset));
7799 // conditionally move a null
7800 csel(rHandle, zr, rHandle, Assembler::EQ);
7801 }
7802
7803 // If arg is on the stack then place it otherwise it is already in correct reg.
7804 if (dst.first()->is_stack()) {
7805 str(rHandle, Address(sp, reg2offset_out(dst.first())));
7806 }
7807 }
7808
7809 // A float arg may have to do float reg int reg conversion
7810 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
7811 if (src.first()->is_stack()) {
7812 if (dst.first()->is_stack()) {
7813 ldrw(tmp, Address(rfp, reg2offset_in(src.first())));
7814 strw(tmp, Address(sp, reg2offset_out(dst.first())));
7815 } else {
7816 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7817 }
7818 } else if (src.first() != dst.first()) {
7819 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7820 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7821 else
7822 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7823 }
7824 }
7825
7826 // A long move
7827 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
7828 if (src.first()->is_stack()) {
7829 if (dst.first()->is_stack()) {
7830 // stack to stack
7831 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7832 str(tmp, Address(sp, reg2offset_out(dst.first())));
7833 } else {
7834 // stack to reg
7835 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
7836 }
7837 } else if (dst.first()->is_stack()) {
7838 // reg to stack
7839 // Do we really have to sign extend???
7840 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
7841 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
7842 } else {
7843 if (dst.first() != src.first()) {
7844 mov(dst.first()->as_Register(), src.first()->as_Register());
7845 }
7846 }
7847 }
7848
7849
7850 // A double move
7851 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
7852 if (src.first()->is_stack()) {
7853 if (dst.first()->is_stack()) {
7854 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7855 str(tmp, Address(sp, reg2offset_out(dst.first())));
7856 } else {
7857 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7858 }
7859 } else if (src.first() != dst.first()) {
7860 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7861 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7862 else
7863 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7864 }
7865 }
7866
7867 // Implements fast-locking.
7868 //
7869 // - obj: the object to be locked
7870 // - t1, t2, t3: temporary registers, will be destroyed
7871 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding).
7872 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow) {
7873 assert_different_registers(basic_lock, obj, t1, t2, t3, rscratch1);
7874
7875 Label push;
7876 const Register top = t1;
7877 const Register mark = t2;
7878 const Register t = t3;
7879
7880 // Preload the markWord. It is important that this is the first
7881 // instruction emitted as it is part of C1's null check semantics.
7882 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7883
7884 if (UseObjectMonitorTable) {
7885 // Clear cache in case fast locking succeeds or we need to take the slow-path.
7886 str(zr, Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))));
7887 }
7888
7889 if (DiagnoseSyncOnValueBasedClasses != 0) {
7890 load_klass(t1, obj, rscratch1);
7891 ldrb(t1, Address(t1, Klass::misc_flags_offset()));
7892 tst(t1, KlassFlags::_misc_is_value_based_class);
7893 br(Assembler::NE, slow);
7894 }
7895
7896 // Check if the lock-stack is full.
7897 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7898 cmpw(top, (unsigned)LockStack::end_offset());
7899 br(Assembler::GE, slow);
7900
7901 // Check for recursion.
7902 subw(t, top, oopSize);
7903 ldr(t, Address(rthread, t));
7904 cmp(obj, t);
7905 br(Assembler::EQ, push);
7906
7907 // Check header for monitor (0b10).
7908 tst(mark, markWord::monitor_value);
7909 br(Assembler::NE, slow);
7910
7911 // Try to lock. Transition lock bits 0b01 => 0b00
7912 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7913 orr(mark, mark, markWord::unlocked_value);
7914 // Mask inline_type bit such that we go to the slow path if object is an inline type
7915 andr(mark, mark, ~((int) markWord::inline_type_bit_in_place));
7916
7917 eor(t, mark, markWord::unlocked_value);
7918 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword, memory_order_acquire);
7919 br(Assembler::NE, slow);
7920
7921 bind(push);
7922 // After successful lock, push object on lock-stack.
7923 str(obj, Address(rthread, top));
7924 addw(top, top, oopSize);
7925 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7926 }
7927
7928 // Implements fast-unlocking.
7929 //
7930 // - obj: the object to be unlocked
7931 // - t1, t2, t3: temporary registers
7932 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
7933 void MacroAssembler::fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
7934 // cmpxchg clobbers rscratch1.
7935 assert_different_registers(obj, t1, t2, t3, rscratch1);
7936
7937 #ifdef ASSERT
7938 {
7939 // Check for lock-stack underflow.
7940 Label stack_ok;
7941 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
7942 cmpw(t1, (unsigned)LockStack::start_offset());
7943 br(Assembler::GE, stack_ok);
7944 STOP("Lock-stack underflow");
7945 bind(stack_ok);
7946 }
7947 #endif
7948
7949 Label unlocked, push_and_slow;
7950 const Register top = t1;
7951 const Register mark = t2;
7952 const Register t = t3;
7953
7954 // Check if obj is top of lock-stack.
7955 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7956 subw(top, top, oopSize);
7957 ldr(t, Address(rthread, top));
7958 cmp(obj, t);
7959 br(Assembler::NE, slow);
7960
7961 // Pop lock-stack.
7962 DEBUG_ONLY(str(zr, Address(rthread, top));)
7963 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7964
7965 // Check if recursive.
7966 subw(t, top, oopSize);
7967 ldr(t, Address(rthread, t));
7968 cmp(obj, t);
7969 br(Assembler::EQ, unlocked);
7970
7971 // Not recursive. Check header for monitor (0b10).
7972 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7973 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow);
7974
7975 #ifdef ASSERT
7976 // Check header not unlocked (0b01).
7977 Label not_unlocked;
7978 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked);
7979 stop("fast_unlock already unlocked");
7980 bind(not_unlocked);
7981 #endif
7982
7983 // Try to unlock. Transition lock bits 0b00 => 0b01
7984 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7985 orr(t, mark, markWord::unlocked_value);
7986 cmpxchg(obj, mark, t, Assembler::xword, memory_order_release);
7987 br(Assembler::EQ, unlocked);
7988
7989 bind(push_and_slow);
7990 // Restore lock-stack and handle the unlock in runtime.
7991 DEBUG_ONLY(str(obj, Address(rthread, top));)
7992 addw(top, top, oopSize);
7993 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7994 b(slow);
7995
7996 bind(unlocked);
7997 }
7998
7999 // Rotate using USHR and SLI instructions (or copy, if rotate count is zero)
8000 void MacroAssembler::neon_vector_rotate(FloatRegister dst, SIMD_Arrangement T,
8001 FloatRegister src, int shift_amount) {
8002 assert(src != dst, "did not expect src and dst to be the same register");
8003
8004 int esize = BitsPerByte << (T / 2);
8005 int lshift = shift_amount & (esize - 1);
8006
8007 if (lshift == 0) {
8008 // T & 1 == 0 => 64-bit arrangements, else 128-bit arrangements
8009 orr(dst, (T & 1) == 0 ? T8B : T16B, src, src);
8010 } else {
8011 ushr(dst, T, src, esize - lshift);
8012 sli(dst, T, src, lshift);
8013 }
8014 }
8015
8016 void MacroAssembler::try_to_replace_prev_vector_copy_with_movprfx(FloatRegister dst) {
8017 if (code_section()->is_empty()) {
8018 return;
8019 }
8020
8021 address prev = pc() - NativeInstruction::instruction_size;
8022 uint32_t insn = nativeInstruction_at(prev)->encoding();
8023 if (!NativeInstruction::is_neon_vector_mov_alias(insn) &&
8024 !NativeInstruction::is_sve_vector_mov_alias(insn)) {
8025 return;
8026 }
8027
8028 // The destructive instruction must reuse the mov alias destination.
8029 uint32_t rd = Instruction_aarch64::extract(insn, 4, 0);
8030 if (rd != (uint32_t)dst->encoding()) {
8031 return;
8032 }
8033
8034 uint32_t rn = Instruction_aarch64::extract(insn, 9, 5);
8035 Instruction_aarch64::patch(prev, 31, 0,
8036 NativeInstruction::encode_sve_movprfx(rd, rn));
8037 }