1 /* 2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "ci/ciEnv.hpp" 29 #include "ci/ciInlineKlass.hpp" 30 #include "code/compiledIC.hpp" 31 #include "compiler/compileTask.hpp" 32 #include "compiler/disassembler.hpp" 33 #include "compiler/oopMap.hpp" 34 #include "gc/shared/barrierSet.hpp" 35 #include "gc/shared/barrierSetAssembler.hpp" 36 #include "gc/shared/cardTableBarrierSet.hpp" 37 #include "gc/shared/cardTable.hpp" 38 #include "gc/shared/collectedHeap.hpp" 39 #include "gc/shared/tlab_globals.hpp" 40 #include "interpreter/bytecodeHistogram.hpp" 41 #include "interpreter/interpreter.hpp" 42 #include "interpreter/interpreterRuntime.hpp" 43 #include "jvm.h" 44 #include "memory/resourceArea.hpp" 45 #include "memory/universe.hpp" 46 #include "nativeInst_aarch64.hpp" 47 #include "oops/accessDecorators.hpp" 48 #include "oops/compressedKlass.inline.hpp" 49 #include "oops/compressedOops.inline.hpp" 50 #include "oops/klass.inline.hpp" 51 #include "oops/resolvedFieldEntry.hpp" 52 #include "runtime/arguments.hpp" 53 #include "runtime/continuation.hpp" 54 #include "runtime/globals.hpp" 55 #include "runtime/icache.hpp" 56 #include "runtime/interfaceSupport.inline.hpp" 57 #include "runtime/javaThread.hpp" 58 #include "runtime/jniHandles.inline.hpp" 59 #include "runtime/sharedRuntime.hpp" 60 #include "runtime/signature_cc.hpp" 61 #include "runtime/stubRoutines.hpp" 62 #include "utilities/globalDefinitions.hpp" 63 #include "utilities/powerOfTwo.hpp" 64 #include "vmreg_aarch64.inline.hpp" 65 #ifdef COMPILER1 66 #include "c1/c1_LIRAssembler.hpp" 67 #endif 68 #ifdef COMPILER2 69 #include "oops/oop.hpp" 70 #include "opto/compile.hpp" 71 #include "opto/node.hpp" 72 #include "opto/output.hpp" 73 #endif 74 75 #include <sys/types.h> 76 77 #ifdef PRODUCT 78 #define BLOCK_COMMENT(str) /* nothing */ 79 #else 80 #define BLOCK_COMMENT(str) block_comment(str) 81 #endif 82 #define STOP(str) stop(str); 83 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 84 85 #ifdef ASSERT 86 extern "C" void disnm(intptr_t p); 87 #endif 88 // Target-dependent relocation processing 89 // 90 // Instruction sequences whose target may need to be retrieved or 91 // patched are distinguished by their leading instruction, sorting 92 // them into three main instruction groups and related subgroups. 93 // 94 // 1) Branch, Exception and System (insn count = 1) 95 // 1a) Unconditional branch (immediate): 96 // b/bl imm19 97 // 1b) Compare & branch (immediate): 98 // cbz/cbnz Rt imm19 99 // 1c) Test & branch (immediate): 100 // tbz/tbnz Rt imm14 101 // 1d) Conditional branch (immediate): 102 // b.cond imm19 103 // 104 // 2) Loads and Stores (insn count = 1) 105 // 2a) Load register literal: 106 // ldr Rt imm19 107 // 108 // 3) Data Processing Immediate (insn count = 2 or 3) 109 // 3a) PC-rel. addressing 110 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12 111 // adr/adrp Rx imm21; add Ry Rx #imm12 112 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page] 113 // adr/adrp Rx imm21 114 // adr/adrp Rx imm21; movk Rx #imm16<<32 115 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page 116 // The latter form can only happen when the target is an 117 // ExternalAddress, and (by definition) ExternalAddresses don't 118 // move. Because of that property, there is never any need to 119 // patch the last of the three instructions. However, 120 // MacroAssembler::target_addr_for_insn takes all three 121 // instructions into account and returns the correct address. 122 // 3b) Move wide (immediate) 123 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32; 124 // 125 // A switch on a subset of the instruction's bits provides an 126 // efficient dispatch to these subcases. 127 // 128 // insn[28:26] -> main group ('x' == don't care) 129 // 00x -> UNALLOCATED 130 // 100 -> Data Processing Immediate 131 // 101 -> Branch, Exception and System 132 // x1x -> Loads and Stores 133 // 134 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care). 135 // n.b. in some cases extra bits need to be checked to verify the 136 // instruction is as expected 137 // 138 // 1) ... xx101x Branch, Exception and System 139 // 1a) 00___x Unconditional branch (immediate) 140 // 1b) 01___0 Compare & branch (immediate) 141 // 1c) 01___1 Test & branch (immediate) 142 // 1d) 10___0 Conditional branch (immediate) 143 // other Should not happen 144 // 145 // 2) ... xxx1x0 Loads and Stores 146 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0) 147 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0) 148 // strictly should be 64 bit non-FP/SIMD i.e. 149 // 0101_000 (i.e. requires insn[31:24] == 01011000) 150 // 151 // 3) ... xx100x Data Processing Immediate 152 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0) 153 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01) 154 // strictly should be 64 bit movz #imm16<<0 155 // 110___10100 (i.e. requires insn[31:21] == 11010010100) 156 // 157 158 static uint32_t insn_at(address insn_addr, int n) { 159 return ((uint32_t*)insn_addr)[n]; 160 } 161 162 template<typename T> 163 class RelocActions : public AllStatic { 164 165 public: 166 167 static int ALWAYSINLINE run(address insn_addr, address &target) { 168 int instructions = 1; 169 uint32_t insn = insn_at(insn_addr, 0); 170 171 uint32_t dispatch = Instruction_aarch64::extract(insn, 30, 25); 172 switch(dispatch) { 173 case 0b001010: 174 case 0b001011: { 175 instructions = T::unconditionalBranch(insn_addr, target); 176 break; 177 } 178 case 0b101010: // Conditional branch (immediate) 179 case 0b011010: { // Compare & branch (immediate) 180 instructions = T::conditionalBranch(insn_addr, target); 181 break; 182 } 183 case 0b011011: { 184 instructions = T::testAndBranch(insn_addr, target); 185 break; 186 } 187 case 0b001100: 188 case 0b001110: 189 case 0b011100: 190 case 0b011110: 191 case 0b101100: 192 case 0b101110: 193 case 0b111100: 194 case 0b111110: { 195 // load/store 196 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) { 197 // Load register (literal) 198 instructions = T::loadStore(insn_addr, target); 199 break; 200 } else { 201 // nothing to do 202 assert(target == nullptr, "did not expect to relocate target for polling page load"); 203 } 204 break; 205 } 206 case 0b001000: 207 case 0b011000: 208 case 0b101000: 209 case 0b111000: { 210 // adr/adrp 211 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be"); 212 int shift = Instruction_aarch64::extract(insn, 31, 31); 213 if (shift) { 214 uint32_t insn2 = insn_at(insn_addr, 1); 215 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 216 Instruction_aarch64::extract(insn, 4, 0) == 217 Instruction_aarch64::extract(insn2, 9, 5)) { 218 instructions = T::adrp(insn_addr, target, T::adrpMem); 219 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 220 Instruction_aarch64::extract(insn, 4, 0) == 221 Instruction_aarch64::extract(insn2, 4, 0)) { 222 instructions = T::adrp(insn_addr, target, T::adrpAdd); 223 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && 224 Instruction_aarch64::extract(insn, 4, 0) == 225 Instruction_aarch64::extract(insn2, 4, 0)) { 226 instructions = T::adrp(insn_addr, target, T::adrpMovk); 227 } else { 228 ShouldNotReachHere(); 229 } 230 } else { 231 instructions = T::adr(insn_addr, target); 232 } 233 break; 234 } 235 case 0b001001: 236 case 0b011001: 237 case 0b101001: 238 case 0b111001: { 239 instructions = T::immediate(insn_addr, target); 240 break; 241 } 242 default: { 243 ShouldNotReachHere(); 244 } 245 } 246 247 T::verify(insn_addr, target); 248 return instructions * NativeInstruction::instruction_size; 249 } 250 }; 251 252 class Patcher : public AllStatic { 253 public: 254 static int unconditionalBranch(address insn_addr, address &target) { 255 intptr_t offset = (target - insn_addr) >> 2; 256 Instruction_aarch64::spatch(insn_addr, 25, 0, offset); 257 return 1; 258 } 259 static int conditionalBranch(address insn_addr, address &target) { 260 intptr_t offset = (target - insn_addr) >> 2; 261 Instruction_aarch64::spatch(insn_addr, 23, 5, offset); 262 return 1; 263 } 264 static int testAndBranch(address insn_addr, address &target) { 265 intptr_t offset = (target - insn_addr) >> 2; 266 Instruction_aarch64::spatch(insn_addr, 18, 5, offset); 267 return 1; 268 } 269 static int loadStore(address insn_addr, address &target) { 270 intptr_t offset = (target - insn_addr) >> 2; 271 Instruction_aarch64::spatch(insn_addr, 23, 5, offset); 272 return 1; 273 } 274 static int adr(address insn_addr, address &target) { 275 #ifdef ASSERT 276 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be"); 277 #endif 278 // PC-rel. addressing 279 ptrdiff_t offset = target - insn_addr; 280 int offset_lo = offset & 3; 281 offset >>= 2; 282 Instruction_aarch64::spatch(insn_addr, 23, 5, offset); 283 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo); 284 return 1; 285 } 286 template<typename U> 287 static int adrp(address insn_addr, address &target, U inner) { 288 int instructions = 1; 289 #ifdef ASSERT 290 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be"); 291 #endif 292 ptrdiff_t offset = target - insn_addr; 293 instructions = 2; 294 precond(inner != nullptr); 295 // Give the inner reloc a chance to modify the target. 296 address adjusted_target = target; 297 instructions = inner(insn_addr, adjusted_target); 298 uintptr_t pc_page = (uintptr_t)insn_addr >> 12; 299 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12; 300 offset = adr_page - pc_page; 301 int offset_lo = offset & 3; 302 offset >>= 2; 303 Instruction_aarch64::spatch(insn_addr, 23, 5, offset); 304 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo); 305 return instructions; 306 } 307 static int adrpMem(address insn_addr, address &target) { 308 uintptr_t dest = (uintptr_t)target; 309 int offset_lo = dest & 0xfff; 310 uint32_t insn2 = insn_at(insn_addr, 1); 311 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30); 312 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size); 313 guarantee(((dest >> size) << size) == dest, "misaligned target"); 314 return 2; 315 } 316 static int adrpAdd(address insn_addr, address &target) { 317 uintptr_t dest = (uintptr_t)target; 318 int offset_lo = dest & 0xfff; 319 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo); 320 return 2; 321 } 322 static int adrpMovk(address insn_addr, address &target) { 323 uintptr_t dest = uintptr_t(target); 324 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32); 325 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL); 326 target = address(dest); 327 return 2; 328 } 329 static int immediate(address insn_addr, address &target) { 330 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010100, "must be"); 331 uint64_t dest = (uint64_t)target; 332 // Move wide constant 333 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); 334 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch"); 335 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff); 336 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff); 337 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff); 338 return 3; 339 } 340 static void verify(address insn_addr, address &target) { 341 #ifdef ASSERT 342 address address_is = MacroAssembler::target_addr_for_insn(insn_addr); 343 if (!(address_is == target)) { 344 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target); 345 disnm((intptr_t)insn_addr); 346 assert(address_is == target, "should be"); 347 } 348 #endif 349 } 350 }; 351 352 // If insn1 and insn2 use the same register to form an address, either 353 // by an offsetted LDR or a simple ADD, return the offset. If the 354 // second instruction is an LDR, the offset may be scaled. 355 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) { 356 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 357 Instruction_aarch64::extract(insn1, 4, 0) == 358 Instruction_aarch64::extract(insn2, 9, 5)) { 359 // Load/store register (unsigned immediate) 360 byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 361 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30); 362 byte_offset <<= size; 363 return true; 364 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 365 Instruction_aarch64::extract(insn1, 4, 0) == 366 Instruction_aarch64::extract(insn2, 4, 0)) { 367 // add (immediate) 368 byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 369 return true; 370 } 371 return false; 372 } 373 374 class AArch64Decoder : public AllStatic { 375 public: 376 377 static int loadStore(address insn_addr, address &target) { 378 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5); 379 target = insn_addr + (offset << 2); 380 return 1; 381 } 382 static int unconditionalBranch(address insn_addr, address &target) { 383 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 25, 0); 384 target = insn_addr + (offset << 2); 385 return 1; 386 } 387 static int conditionalBranch(address insn_addr, address &target) { 388 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5); 389 target = address(((uint64_t)insn_addr + (offset << 2))); 390 return 1; 391 } 392 static int testAndBranch(address insn_addr, address &target) { 393 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 18, 5); 394 target = address(((uint64_t)insn_addr + (offset << 2))); 395 return 1; 396 } 397 static int adr(address insn_addr, address &target) { 398 // PC-rel. addressing 399 uint32_t insn = insn_at(insn_addr, 0); 400 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29); 401 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2; 402 target = address((uint64_t)insn_addr + offset); 403 return 1; 404 } 405 template<typename U> 406 static int adrp(address insn_addr, address &target, U inner) { 407 uint32_t insn = insn_at(insn_addr, 0); 408 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be"); 409 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29); 410 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2; 411 int shift = 12; 412 offset <<= shift; 413 uint64_t target_page = ((uint64_t)insn_addr) + offset; 414 target_page &= ((uint64_t)-1) << shift; 415 target = address(target_page); 416 precond(inner != nullptr); 417 inner(insn_addr, target); 418 return 2; 419 } 420 static int adrpMem(address insn_addr, address &target) { 421 uint32_t insn2 = insn_at(insn_addr, 1); 422 // Load/store register (unsigned immediate) 423 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 424 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30); 425 byte_offset <<= size; 426 target += byte_offset; 427 return 2; 428 } 429 static int adrpAdd(address insn_addr, address &target) { 430 uint32_t insn2 = insn_at(insn_addr, 1); 431 // add (immediate) 432 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 433 target += byte_offset; 434 return 2; 435 } 436 static int adrpMovk(address insn_addr, address &target) { 437 uint32_t insn2 = insn_at(insn_addr, 1); 438 uint64_t dest = uint64_t(target); 439 dest = (dest & 0xffff0000ffffffff) | 440 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32); 441 target = address(dest); 442 443 // We know the destination 4k page. Maybe we have a third 444 // instruction. 445 uint32_t insn = insn_at(insn_addr, 0); 446 uint32_t insn3 = insn_at(insn_addr, 2); 447 ptrdiff_t byte_offset; 448 if (offset_for(insn, insn3, byte_offset)) { 449 target += byte_offset; 450 return 3; 451 } else { 452 return 2; 453 } 454 } 455 static int immediate(address insn_addr, address &target) { 456 uint32_t *insns = (uint32_t *)insn_addr; 457 assert(Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010100, "must be"); 458 // Move wide constant: movz, movk, movk. See movptr(). 459 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch"); 460 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch"); 461 target = address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5)) 462 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16) 463 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32)); 464 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); 465 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch"); 466 return 3; 467 } 468 static void verify(address insn_addr, address &target) { 469 } 470 }; 471 472 address MacroAssembler::target_addr_for_insn(address insn_addr) { 473 address target; 474 RelocActions<AArch64Decoder>::run(insn_addr, target); 475 return target; 476 } 477 478 // Patch any kind of instruction; there may be several instructions. 479 // Return the total length (in bytes) of the instructions. 480 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) { 481 MACOS_AARCH64_ONLY(os::thread_wx_enable_write()); 482 return RelocActions<Patcher>::run(insn_addr, target); 483 } 484 485 int MacroAssembler::patch_oop(address insn_addr, address o) { 486 int instructions; 487 unsigned insn = *(unsigned*)insn_addr; 488 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); 489 490 MACOS_AARCH64_ONLY(os::thread_wx_enable_write()); 491 492 // OOPs are either narrow (32 bits) or wide (48 bits). We encode 493 // narrow OOPs by setting the upper 16 bits in the first 494 // instruction. 495 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) { 496 // Move narrow OOP 497 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o)); 498 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16); 499 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff); 500 instructions = 2; 501 } else { 502 // Move wide OOP 503 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch"); 504 uintptr_t dest = (uintptr_t)o; 505 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff); 506 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff); 507 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff); 508 instructions = 3; 509 } 510 return instructions * NativeInstruction::instruction_size; 511 } 512 513 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) { 514 // Metadata pointers are either narrow (32 bits) or wide (48 bits). 515 // We encode narrow ones by setting the upper 16 bits in the first 516 // instruction. 517 NativeInstruction *insn = nativeInstruction_at(insn_addr); 518 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 && 519 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); 520 521 MACOS_AARCH64_ONLY(os::thread_wx_enable_write()); 522 523 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16); 524 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff); 525 return 2 * NativeInstruction::instruction_size; 526 } 527 528 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp) { 529 ldr(tmp, Address(rthread, JavaThread::polling_word_offset())); 530 if (at_return) { 531 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore, 532 // we may safely use the sp instead to perform the stack watermark check. 533 cmp(in_nmethod ? sp : rfp, tmp); 534 br(Assembler::HI, slow_path); 535 } else { 536 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path); 537 } 538 } 539 540 void MacroAssembler::rt_call(address dest, Register tmp) { 541 CodeBlob *cb = CodeCache::find_blob(dest); 542 if (cb) { 543 far_call(RuntimeAddress(dest)); 544 } else { 545 lea(tmp, RuntimeAddress(dest)); 546 blr(tmp); 547 } 548 } 549 550 void MacroAssembler::push_cont_fastpath(Register java_thread) { 551 if (!Continuations::enabled()) return; 552 Label done; 553 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset())); 554 cmp(sp, rscratch1); 555 br(Assembler::LS, done); 556 mov(rscratch1, sp); // we can't use sp as the source in str 557 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset())); 558 bind(done); 559 } 560 561 void MacroAssembler::pop_cont_fastpath(Register java_thread) { 562 if (!Continuations::enabled()) return; 563 Label done; 564 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset())); 565 cmp(sp, rscratch1); 566 br(Assembler::LO, done); 567 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset())); 568 bind(done); 569 } 570 571 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { 572 // we must set sp to zero to clear frame 573 str(zr, Address(rthread, JavaThread::last_Java_sp_offset())); 574 575 // must clear fp, so that compiled frames are not confused; it is 576 // possible that we need it only for debugging 577 if (clear_fp) { 578 str(zr, Address(rthread, JavaThread::last_Java_fp_offset())); 579 } 580 581 // Always clear the pc because it could have been set by make_walkable() 582 str(zr, Address(rthread, JavaThread::last_Java_pc_offset())); 583 } 584 585 // Calls to C land 586 // 587 // When entering C land, the rfp, & resp of the last Java frame have to be recorded 588 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 589 // has to be reset to 0. This is required to allow proper stack traversal. 590 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 591 Register last_java_fp, 592 Register last_java_pc, 593 Register scratch) { 594 595 if (last_java_pc->is_valid()) { 596 str(last_java_pc, Address(rthread, 597 JavaThread::frame_anchor_offset() 598 + JavaFrameAnchor::last_Java_pc_offset())); 599 } 600 601 // determine last_java_sp register 602 if (last_java_sp == sp) { 603 mov(scratch, sp); 604 last_java_sp = scratch; 605 } else if (!last_java_sp->is_valid()) { 606 last_java_sp = esp; 607 } 608 609 // last_java_fp is optional 610 if (last_java_fp->is_valid()) { 611 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset())); 612 } 613 614 // We must set sp last. 615 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset())); 616 } 617 618 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 619 Register last_java_fp, 620 address last_java_pc, 621 Register scratch) { 622 assert(last_java_pc != nullptr, "must provide a valid PC"); 623 624 adr(scratch, last_java_pc); 625 str(scratch, Address(rthread, 626 JavaThread::frame_anchor_offset() 627 + JavaFrameAnchor::last_Java_pc_offset())); 628 629 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch); 630 } 631 632 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 633 Register last_java_fp, 634 Label &L, 635 Register scratch) { 636 if (L.is_bound()) { 637 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch); 638 } else { 639 InstructionMark im(this); 640 L.add_patch_at(code(), locator()); 641 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch); 642 } 643 } 644 645 static inline bool target_needs_far_branch(address addr) { 646 if (AOTCodeCache::is_on_for_dump()) { 647 return true; 648 } 649 // codecache size <= 128M 650 if (!MacroAssembler::far_branches()) { 651 return false; 652 } 653 // codecache size > 240M 654 if (MacroAssembler::codestub_branch_needs_far_jump()) { 655 return true; 656 } 657 // codecache size: 128M..240M 658 return !CodeCache::is_non_nmethod(addr); 659 } 660 661 void MacroAssembler::far_call(Address entry, Register tmp) { 662 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 663 assert(CodeCache::find_blob(entry.target()) != nullptr, 664 "destination of far call not found in code cache"); 665 assert(entry.rspec().type() == relocInfo::external_word_type 666 || entry.rspec().type() == relocInfo::runtime_call_type 667 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type"); 668 if (target_needs_far_branch(entry.target())) { 669 uint64_t offset; 670 // We can use ADRP here because we know that the total size of 671 // the code cache cannot exceed 2Gb (ADRP limit is 4GB). 672 adrp(tmp, entry, offset); 673 add(tmp, tmp, offset); 674 blr(tmp); 675 } else { 676 bl(entry); 677 } 678 } 679 680 int MacroAssembler::far_jump(Address entry, Register tmp) { 681 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 682 assert(CodeCache::find_blob(entry.target()) != nullptr, 683 "destination of far call not found in code cache"); 684 assert(entry.rspec().type() == relocInfo::external_word_type 685 || entry.rspec().type() == relocInfo::runtime_call_type 686 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type"); 687 address start = pc(); 688 if (target_needs_far_branch(entry.target())) { 689 uint64_t offset; 690 // We can use ADRP here because we know that the total size of 691 // the code cache cannot exceed 2Gb (ADRP limit is 4GB). 692 adrp(tmp, entry, offset); 693 add(tmp, tmp, offset); 694 br(tmp); 695 } else { 696 b(entry); 697 } 698 return pc() - start; 699 } 700 701 void MacroAssembler::reserved_stack_check() { 702 // testing if reserved zone needs to be enabled 703 Label no_reserved_zone_enabling; 704 705 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset())); 706 cmp(sp, rscratch1); 707 br(Assembler::LO, no_reserved_zone_enabling); 708 709 enter(); // LR and FP are live. 710 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone))); 711 mov(c_rarg0, rthread); 712 blr(rscratch1); 713 leave(); 714 715 // We have already removed our own frame. 716 // throw_delayed_StackOverflowError will think that it's been 717 // called by our caller. 718 lea(rscratch1, RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry())); 719 br(rscratch1); 720 should_not_reach_here(); 721 722 bind(no_reserved_zone_enabling); 723 } 724 725 static void pass_arg0(MacroAssembler* masm, Register arg) { 726 if (c_rarg0 != arg ) { 727 masm->mov(c_rarg0, arg); 728 } 729 } 730 731 static void pass_arg1(MacroAssembler* masm, Register arg) { 732 if (c_rarg1 != arg ) { 733 masm->mov(c_rarg1, arg); 734 } 735 } 736 737 static void pass_arg2(MacroAssembler* masm, Register arg) { 738 if (c_rarg2 != arg ) { 739 masm->mov(c_rarg2, arg); 740 } 741 } 742 743 static void pass_arg3(MacroAssembler* masm, Register arg) { 744 if (c_rarg3 != arg ) { 745 masm->mov(c_rarg3, arg); 746 } 747 } 748 749 void MacroAssembler::call_VM_base(Register oop_result, 750 Register java_thread, 751 Register last_java_sp, 752 Label* return_pc, 753 address entry_point, 754 int number_of_arguments, 755 bool check_exceptions) { 756 // determine java_thread register 757 if (!java_thread->is_valid()) { 758 java_thread = rthread; 759 } 760 761 // determine last_java_sp register 762 if (!last_java_sp->is_valid()) { 763 last_java_sp = esp; 764 } 765 766 // debugging support 767 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 768 assert(java_thread == rthread, "unexpected register"); 769 #ifdef ASSERT 770 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 771 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?"); 772 #endif // ASSERT 773 774 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 775 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 776 777 // push java thread (becomes first argument of C function) 778 779 mov(c_rarg0, java_thread); 780 781 // set last Java frame before call 782 assert(last_java_sp != rfp, "can't use rfp"); 783 784 Label l; 785 set_last_Java_frame(last_java_sp, rfp, return_pc != nullptr ? *return_pc : l, rscratch1); 786 787 // do the call, remove parameters 788 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l); 789 790 // lr could be poisoned with PAC signature during throw_pending_exception 791 // if it was tail-call optimized by compiler, since lr is not callee-saved 792 // reload it with proper value 793 adr(lr, l); 794 795 // reset last Java frame 796 // Only interpreter should have to clear fp 797 reset_last_Java_frame(true); 798 799 // C++ interp handles this in the interpreter 800 check_and_handle_popframe(java_thread); 801 check_and_handle_earlyret(java_thread); 802 803 if (check_exceptions) { 804 // check for pending exceptions (java_thread is set upon return) 805 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset()))); 806 Label ok; 807 cbz(rscratch1, ok); 808 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry())); 809 br(rscratch1); 810 bind(ok); 811 } 812 813 // get oop result if there is one and reset the value in the thread 814 if (oop_result->is_valid()) { 815 get_vm_result_oop(oop_result, java_thread); 816 } 817 } 818 819 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 820 call_VM_base(oop_result, noreg, noreg, nullptr, entry_point, number_of_arguments, check_exceptions); 821 } 822 823 // Check the entry target is always reachable from any branch. 824 static bool is_always_within_branch_range(Address entry) { 825 if (AOTCodeCache::is_on_for_dump()) { 826 return false; 827 } 828 const address target = entry.target(); 829 830 if (!CodeCache::contains(target)) { 831 // We always use trampolines for callees outside CodeCache. 832 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target"); 833 return false; 834 } 835 836 if (!MacroAssembler::far_branches()) { 837 return true; 838 } 839 840 if (entry.rspec().type() == relocInfo::runtime_call_type) { 841 // Runtime calls are calls of a non-compiled method (stubs, adapters). 842 // Non-compiled methods stay forever in CodeCache. 843 // We check whether the longest possible branch is within the branch range. 844 assert(CodeCache::find_blob(target) != nullptr && 845 !CodeCache::find_blob(target)->is_nmethod(), 846 "runtime call of compiled method"); 847 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size; 848 const address left_longest_branch_start = CodeCache::low_bound(); 849 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) && 850 Assembler::reachable_from_branch_at(right_longest_branch_start, target); 851 return is_reachable; 852 } 853 854 return false; 855 } 856 857 // Maybe emit a call via a trampoline. If the code cache is small 858 // trampolines won't be emitted. 859 address MacroAssembler::trampoline_call(Address entry) { 860 assert(entry.rspec().type() == relocInfo::runtime_call_type 861 || entry.rspec().type() == relocInfo::opt_virtual_call_type 862 || entry.rspec().type() == relocInfo::static_call_type 863 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type"); 864 865 address target = entry.target(); 866 867 if (!is_always_within_branch_range(entry)) { 868 if (!in_scratch_emit_size()) { 869 // We don't want to emit a trampoline if C2 is generating dummy 870 // code during its branch shortening phase. 871 if (entry.rspec().type() == relocInfo::runtime_call_type) { 872 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs"); 873 code()->share_trampoline_for(entry.target(), offset()); 874 } else { 875 address stub = emit_trampoline_stub(offset(), target); 876 if (stub == nullptr) { 877 postcond(pc() == badAddress); 878 return nullptr; // CodeCache is full 879 } 880 } 881 } 882 target = pc(); 883 } 884 885 address call_pc = pc(); 886 relocate(entry.rspec()); 887 bl(target); 888 889 postcond(pc() != badAddress); 890 return call_pc; 891 } 892 893 // Emit a trampoline stub for a call to a target which is too far away. 894 // 895 // code sequences: 896 // 897 // call-site: 898 // branch-and-link to <destination> or <trampoline stub> 899 // 900 // Related trampoline stub for this call site in the stub section: 901 // load the call target from the constant pool 902 // branch (LR still points to the call site above) 903 904 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset, 905 address dest) { 906 // Max stub size: alignment nop, TrampolineStub. 907 address stub = start_a_stub(max_trampoline_stub_size()); 908 if (stub == nullptr) { 909 return nullptr; // CodeBuffer::expand failed 910 } 911 912 // Create a trampoline stub relocation which relates this trampoline stub 913 // with the call instruction at insts_call_instruction_offset in the 914 // instructions code-section. 915 align(wordSize); 916 relocate(trampoline_stub_Relocation::spec(code()->insts()->start() 917 + insts_call_instruction_offset)); 918 const int stub_start_offset = offset(); 919 920 // Now, create the trampoline stub's code: 921 // - load the call 922 // - call 923 Label target; 924 ldr(rscratch1, target); 925 br(rscratch1); 926 bind(target); 927 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset, 928 "should be"); 929 emit_int64((int64_t)dest); 930 931 const address stub_start_addr = addr_at(stub_start_offset); 932 933 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); 934 935 end_a_stub(); 936 return stub_start_addr; 937 } 938 939 int MacroAssembler::max_trampoline_stub_size() { 940 // Max stub size: alignment nop, TrampolineStub. 941 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size; 942 } 943 944 void MacroAssembler::emit_static_call_stub() { 945 // CompiledDirectCall::set_to_interpreted knows the 946 // exact layout of this stub. 947 948 isb(); 949 mov_metadata(rmethod, nullptr); 950 951 // Jump to the entry point of the c2i stub. 952 if (codestub_branch_needs_far_jump()) { 953 movptr(rscratch1, 0); 954 br(rscratch1); 955 } else { 956 b(pc()); 957 } 958 } 959 960 int MacroAssembler::static_call_stub_size() { 961 if (!codestub_branch_needs_far_jump()) { 962 // isb; movk; movz; movz; b 963 return 5 * NativeInstruction::instruction_size; 964 } 965 // isb; movk; movz; movz; movk; movz; movz; br 966 return 8 * NativeInstruction::instruction_size; 967 } 968 969 void MacroAssembler::c2bool(Register x) { 970 // implements x == 0 ? 0 : 1 971 // note: must only look at least-significant byte of x 972 // since C-style booleans are stored in one byte 973 // only! (was bug) 974 tst(x, 0xff); 975 cset(x, Assembler::NE); 976 } 977 978 address MacroAssembler::ic_call(address entry, jint method_index) { 979 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 980 movptr(rscratch2, (intptr_t)Universe::non_oop_word()); 981 return trampoline_call(Address(entry, rh)); 982 } 983 984 int MacroAssembler::ic_check_size() { 985 int extra_instructions = UseCompactObjectHeaders ? 1 : 0; 986 if (target_needs_far_branch(CAST_FROM_FN_PTR(address, SharedRuntime::get_ic_miss_stub()))) { 987 return NativeInstruction::instruction_size * (7 + extra_instructions); 988 } else { 989 return NativeInstruction::instruction_size * (5 + extra_instructions); 990 } 991 } 992 993 int MacroAssembler::ic_check(int end_alignment) { 994 Register receiver = j_rarg0; 995 Register data = rscratch2; 996 Register tmp1 = rscratch1; 997 Register tmp2 = r10; 998 999 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed 1000 // before the inline cache check, so we don't have to execute any nop instructions when dispatching 1001 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align 1002 // before the inline cache check here, and not after 1003 align(end_alignment, offset() + ic_check_size()); 1004 1005 int uep_offset = offset(); 1006 1007 if (UseCompactObjectHeaders) { 1008 load_narrow_klass_compact(tmp1, receiver); 1009 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset())); 1010 cmpw(tmp1, tmp2); 1011 } else if (UseCompressedClassPointers) { 1012 ldrw(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes())); 1013 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset())); 1014 cmpw(tmp1, tmp2); 1015 } else { 1016 ldr(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes())); 1017 ldr(tmp2, Address(data, CompiledICData::speculated_klass_offset())); 1018 cmp(tmp1, tmp2); 1019 } 1020 1021 Label dont; 1022 br(Assembler::EQ, dont); 1023 far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 1024 bind(dont); 1025 assert((offset() % end_alignment) == 0, "Misaligned verified entry point"); 1026 1027 return uep_offset; 1028 } 1029 1030 // Implementation of call_VM versions 1031 1032 void MacroAssembler::call_VM(Register oop_result, 1033 address entry_point, 1034 bool check_exceptions) { 1035 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 1036 } 1037 1038 void MacroAssembler::call_VM(Register oop_result, 1039 address entry_point, 1040 Register arg_1, 1041 bool check_exceptions) { 1042 pass_arg1(this, arg_1); 1043 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 1044 } 1045 1046 void MacroAssembler::call_VM(Register oop_result, 1047 address entry_point, 1048 Register arg_1, 1049 Register arg_2, 1050 bool check_exceptions) { 1051 assert_different_registers(arg_1, c_rarg2); 1052 pass_arg2(this, arg_2); 1053 pass_arg1(this, arg_1); 1054 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 1055 } 1056 1057 void MacroAssembler::call_VM(Register oop_result, 1058 address entry_point, 1059 Register arg_1, 1060 Register arg_2, 1061 Register arg_3, 1062 bool check_exceptions) { 1063 assert_different_registers(arg_1, c_rarg2, c_rarg3); 1064 assert_different_registers(arg_2, c_rarg3); 1065 pass_arg3(this, arg_3); 1066 1067 pass_arg2(this, arg_2); 1068 1069 pass_arg1(this, arg_1); 1070 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 1071 } 1072 1073 void MacroAssembler::call_VM(Register oop_result, 1074 Register last_java_sp, 1075 address entry_point, 1076 int number_of_arguments, 1077 bool check_exceptions) { 1078 call_VM_base(oop_result, rthread, last_java_sp, nullptr, entry_point, number_of_arguments, check_exceptions); 1079 } 1080 1081 void MacroAssembler::call_VM(Register oop_result, 1082 Register last_java_sp, 1083 address entry_point, 1084 Register arg_1, 1085 bool check_exceptions) { 1086 pass_arg1(this, arg_1); 1087 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 1088 } 1089 1090 void MacroAssembler::call_VM(Register oop_result, 1091 Register last_java_sp, 1092 address entry_point, 1093 Register arg_1, 1094 Register arg_2, 1095 bool check_exceptions) { 1096 1097 assert_different_registers(arg_1, c_rarg2); 1098 pass_arg2(this, arg_2); 1099 pass_arg1(this, arg_1); 1100 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 1101 } 1102 1103 void MacroAssembler::call_VM(Register oop_result, 1104 Register last_java_sp, 1105 address entry_point, 1106 Register arg_1, 1107 Register arg_2, 1108 Register arg_3, 1109 bool check_exceptions) { 1110 assert_different_registers(arg_1, c_rarg2, c_rarg3); 1111 assert_different_registers(arg_2, c_rarg3); 1112 pass_arg3(this, arg_3); 1113 pass_arg2(this, arg_2); 1114 pass_arg1(this, arg_1); 1115 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 1116 } 1117 1118 1119 void MacroAssembler::get_vm_result_oop(Register oop_result, Register java_thread) { 1120 ldr(oop_result, Address(java_thread, JavaThread::vm_result_oop_offset())); 1121 str(zr, Address(java_thread, JavaThread::vm_result_oop_offset())); 1122 verify_oop_msg(oop_result, "broken oop in call_VM_base"); 1123 } 1124 1125 void MacroAssembler::get_vm_result_metadata(Register metadata_result, Register java_thread) { 1126 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_metadata_offset())); 1127 str(zr, Address(java_thread, JavaThread::vm_result_metadata_offset())); 1128 } 1129 1130 void MacroAssembler::align(int modulus) { 1131 align(modulus, offset()); 1132 } 1133 1134 // Ensure that the code at target bytes offset from the current offset() is aligned 1135 // according to modulus. 1136 void MacroAssembler::align(int modulus, int target) { 1137 int delta = target - offset(); 1138 while ((offset() + delta) % modulus != 0) nop(); 1139 } 1140 1141 void MacroAssembler::post_call_nop() { 1142 if (!Continuations::enabled()) { 1143 return; 1144 } 1145 InstructionMark im(this); 1146 relocate(post_call_nop_Relocation::spec()); 1147 InlineSkippedInstructionsCounter skipCounter(this); 1148 nop(); 1149 movk(zr, 0); 1150 movk(zr, 0); 1151 } 1152 1153 // these are no-ops overridden by InterpreterMacroAssembler 1154 1155 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { } 1156 1157 void MacroAssembler::check_and_handle_popframe(Register java_thread) { } 1158 1159 // Look up the method for a megamorphic invokeinterface call. 1160 // The target method is determined by <intf_klass, itable_index>. 1161 // The receiver klass is in recv_klass. 1162 // On success, the result will be in method_result, and execution falls through. 1163 // On failure, execution transfers to the given label. 1164 void MacroAssembler::lookup_interface_method(Register recv_klass, 1165 Register intf_klass, 1166 RegisterOrConstant itable_index, 1167 Register method_result, 1168 Register scan_temp, 1169 Label& L_no_such_interface, 1170 bool return_method) { 1171 assert_different_registers(recv_klass, intf_klass, scan_temp); 1172 assert_different_registers(method_result, intf_klass, scan_temp); 1173 assert(recv_klass != method_result || !return_method, 1174 "recv_klass can be destroyed when method isn't needed"); 1175 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 1176 "caller must use same register for non-constant itable index as for method"); 1177 1178 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 1179 int vtable_base = in_bytes(Klass::vtable_start_offset()); 1180 int itentry_off = in_bytes(itableMethodEntry::method_offset()); 1181 int scan_step = itableOffsetEntry::size() * wordSize; 1182 int vte_size = vtableEntry::size_in_bytes(); 1183 assert(vte_size == wordSize, "else adjust times_vte_scale"); 1184 1185 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 1186 1187 // Could store the aligned, prescaled offset in the klass. 1188 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 1189 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3))); 1190 add(scan_temp, scan_temp, vtable_base); 1191 1192 if (return_method) { 1193 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 1194 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 1195 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 1196 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3))); 1197 if (itentry_off) 1198 add(recv_klass, recv_klass, itentry_off); 1199 } 1200 1201 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) { 1202 // if (scan->interface() == intf) { 1203 // result = (klass + scan->offset() + itable_index); 1204 // } 1205 // } 1206 Label search, found_method; 1207 1208 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset())); 1209 cmp(intf_klass, method_result); 1210 br(Assembler::EQ, found_method); 1211 bind(search); 1212 // Check that the previous entry is non-null. A null entry means that 1213 // the receiver class doesn't implement the interface, and wasn't the 1214 // same as when the caller was compiled. 1215 cbz(method_result, L_no_such_interface); 1216 if (itableOffsetEntry::interface_offset() != 0) { 1217 add(scan_temp, scan_temp, scan_step); 1218 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset())); 1219 } else { 1220 ldr(method_result, Address(pre(scan_temp, scan_step))); 1221 } 1222 cmp(intf_klass, method_result); 1223 br(Assembler::NE, search); 1224 1225 bind(found_method); 1226 1227 // Got a hit. 1228 if (return_method) { 1229 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset())); 1230 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0))); 1231 } 1232 } 1233 1234 // Look up the method for a megamorphic invokeinterface call in a single pass over itable: 1235 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData 1236 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index 1237 // The target method is determined by <holder_klass, itable_index>. 1238 // The receiver klass is in recv_klass. 1239 // On success, the result will be in method_result, and execution falls through. 1240 // On failure, execution transfers to the given label. 1241 void MacroAssembler::lookup_interface_method_stub(Register recv_klass, 1242 Register holder_klass, 1243 Register resolved_klass, 1244 Register method_result, 1245 Register temp_itbl_klass, 1246 Register scan_temp, 1247 int itable_index, 1248 Label& L_no_such_interface) { 1249 // 'method_result' is only used as output register at the very end of this method. 1250 // Until then we can reuse it as 'holder_offset'. 1251 Register holder_offset = method_result; 1252 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset); 1253 1254 int vtable_start_offset = in_bytes(Klass::vtable_start_offset()); 1255 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize; 1256 int ioffset = in_bytes(itableOffsetEntry::interface_offset()); 1257 int ooffset = in_bytes(itableOffsetEntry::offset_offset()); 1258 1259 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found; 1260 1261 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 1262 add(recv_klass, recv_klass, vtable_start_offset + ioffset); 1263 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len; 1264 // temp_itbl_klass = itable[0]._interface; 1265 int vtblEntrySize = vtableEntry::size_in_bytes(); 1266 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3"); 1267 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize)))); 1268 mov(holder_offset, zr); 1269 // scan_temp = &(itable[0]._interface) 1270 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize)))); 1271 1272 // Initial checks: 1273 // - if (holder_klass != resolved_klass), go to "scan for resolved" 1274 // - if (itable[0] == holder_klass), shortcut to "holder found" 1275 // - if (itable[0] == 0), no such interface 1276 cmp(resolved_klass, holder_klass); 1277 br(Assembler::NE, L_loop_search_resolved_entry); 1278 cmp(holder_klass, temp_itbl_klass); 1279 br(Assembler::EQ, L_holder_found); 1280 cbz(temp_itbl_klass, L_no_such_interface); 1281 1282 // Loop: Look for holder_klass record in itable 1283 // do { 1284 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size); 1285 // if (temp_itbl_klass == holder_klass) { 1286 // goto L_holder_found; // Found! 1287 // } 1288 // } while (temp_itbl_klass != 0); 1289 // goto L_no_such_interface // Not found. 1290 Label L_search_holder; 1291 bind(L_search_holder); 1292 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size))); 1293 cmp(holder_klass, temp_itbl_klass); 1294 br(Assembler::EQ, L_holder_found); 1295 cbnz(temp_itbl_klass, L_search_holder); 1296 1297 b(L_no_such_interface); 1298 1299 // Loop: Look for resolved_class record in itable 1300 // while (true) { 1301 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size); 1302 // if (temp_itbl_klass == 0) { 1303 // goto L_no_such_interface; 1304 // } 1305 // if (temp_itbl_klass == resolved_klass) { 1306 // goto L_resolved_found; // Found! 1307 // } 1308 // if (temp_itbl_klass == holder_klass) { 1309 // holder_offset = scan_temp; 1310 // } 1311 // } 1312 // 1313 Label L_loop_search_resolved; 1314 bind(L_loop_search_resolved); 1315 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size))); 1316 bind(L_loop_search_resolved_entry); 1317 cbz(temp_itbl_klass, L_no_such_interface); 1318 cmp(resolved_klass, temp_itbl_klass); 1319 br(Assembler::EQ, L_resolved_found); 1320 cmp(holder_klass, temp_itbl_klass); 1321 br(Assembler::NE, L_loop_search_resolved); 1322 mov(holder_offset, scan_temp); 1323 b(L_loop_search_resolved); 1324 1325 // See if we already have a holder klass. If not, go and scan for it. 1326 bind(L_resolved_found); 1327 cbz(holder_offset, L_search_holder); 1328 mov(scan_temp, holder_offset); 1329 1330 // Finally, scan_temp contains holder_klass vtable offset 1331 bind(L_holder_found); 1332 ldrw(method_result, Address(scan_temp, ooffset - ioffset)); 1333 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset()) 1334 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass 1335 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0))); 1336 } 1337 1338 // virtual method calling 1339 void MacroAssembler::lookup_virtual_method(Register recv_klass, 1340 RegisterOrConstant vtable_index, 1341 Register method_result) { 1342 assert(vtableEntry::size() * wordSize == 8, 1343 "adjust the scaling in the code below"); 1344 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset()); 1345 1346 if (vtable_index.is_register()) { 1347 lea(method_result, Address(recv_klass, 1348 vtable_index.as_register(), 1349 Address::lsl(LogBytesPerWord))); 1350 ldr(method_result, Address(method_result, vtable_offset_in_bytes)); 1351 } else { 1352 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize; 1353 ldr(method_result, 1354 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0)); 1355 } 1356 } 1357 1358 void MacroAssembler::check_klass_subtype(Register sub_klass, 1359 Register super_klass, 1360 Register temp_reg, 1361 Label& L_success) { 1362 Label L_failure; 1363 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr); 1364 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr); 1365 bind(L_failure); 1366 } 1367 1368 1369 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 1370 Register super_klass, 1371 Register temp_reg, 1372 Label* L_success, 1373 Label* L_failure, 1374 Label* L_slow_path, 1375 Register super_check_offset) { 1376 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset); 1377 bool must_load_sco = ! super_check_offset->is_valid(); 1378 if (must_load_sco) { 1379 assert(temp_reg != noreg, "supply either a temp or a register offset"); 1380 } 1381 1382 Label L_fallthrough; 1383 int label_nulls = 0; 1384 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; } 1385 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; } 1386 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; } 1387 assert(label_nulls <= 1, "at most one null in the batch"); 1388 1389 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 1390 Address super_check_offset_addr(super_klass, sco_offset); 1391 1392 // Hacked jmp, which may only be used just before L_fallthrough. 1393 #define final_jmp(label) \ 1394 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 1395 else b(label) /*omit semi*/ 1396 1397 // If the pointers are equal, we are done (e.g., String[] elements). 1398 // This self-check enables sharing of secondary supertype arrays among 1399 // non-primary types such as array-of-interface. Otherwise, each such 1400 // type would need its own customized SSA. 1401 // We move this check to the front of the fast path because many 1402 // type checks are in fact trivially successful in this manner, 1403 // so we get a nicely predicted branch right at the start of the check. 1404 cmp(sub_klass, super_klass); 1405 br(Assembler::EQ, *L_success); 1406 1407 // Check the supertype display: 1408 if (must_load_sco) { 1409 ldrw(temp_reg, super_check_offset_addr); 1410 super_check_offset = temp_reg; 1411 } 1412 1413 Address super_check_addr(sub_klass, super_check_offset); 1414 ldr(rscratch1, super_check_addr); 1415 cmp(super_klass, rscratch1); // load displayed supertype 1416 br(Assembler::EQ, *L_success); 1417 1418 // This check has worked decisively for primary supers. 1419 // Secondary supers are sought in the super_cache ('super_cache_addr'). 1420 // (Secondary supers are interfaces and very deeply nested subtypes.) 1421 // This works in the same check above because of a tricky aliasing 1422 // between the super_cache and the primary super display elements. 1423 // (The 'super_check_addr' can address either, as the case requires.) 1424 // Note that the cache is updated below if it does not help us find 1425 // what we need immediately. 1426 // So if it was a primary super, we can just fail immediately. 1427 // Otherwise, it's the slow path for us (no success at this point). 1428 1429 sub(rscratch1, super_check_offset, in_bytes(Klass::secondary_super_cache_offset())); 1430 if (L_failure == &L_fallthrough) { 1431 cbz(rscratch1, *L_slow_path); 1432 } else { 1433 cbnz(rscratch1, *L_failure); 1434 final_jmp(*L_slow_path); 1435 } 1436 1437 bind(L_fallthrough); 1438 1439 #undef final_jmp 1440 } 1441 1442 // These two are taken from x86, but they look generally useful 1443 1444 // scans count pointer sized words at [addr] for occurrence of value, 1445 // generic 1446 void MacroAssembler::repne_scan(Register addr, Register value, Register count, 1447 Register scratch) { 1448 Label Lloop, Lexit; 1449 cbz(count, Lexit); 1450 bind(Lloop); 1451 ldr(scratch, post(addr, wordSize)); 1452 cmp(value, scratch); 1453 br(EQ, Lexit); 1454 sub(count, count, 1); 1455 cbnz(count, Lloop); 1456 bind(Lexit); 1457 } 1458 1459 // scans count 4 byte words at [addr] for occurrence of value, 1460 // generic 1461 void MacroAssembler::repne_scanw(Register addr, Register value, Register count, 1462 Register scratch) { 1463 Label Lloop, Lexit; 1464 cbz(count, Lexit); 1465 bind(Lloop); 1466 ldrw(scratch, post(addr, wordSize)); 1467 cmpw(value, scratch); 1468 br(EQ, Lexit); 1469 sub(count, count, 1); 1470 cbnz(count, Lloop); 1471 bind(Lexit); 1472 } 1473 1474 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass, 1475 Register super_klass, 1476 Register temp_reg, 1477 Register temp2_reg, 1478 Label* L_success, 1479 Label* L_failure, 1480 bool set_cond_codes) { 1481 // NB! Callers may assume that, when temp2_reg is a valid register, 1482 // this code sets it to a nonzero value. 1483 1484 assert_different_registers(sub_klass, super_klass, temp_reg); 1485 if (temp2_reg != noreg) 1486 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1); 1487 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 1488 1489 Label L_fallthrough; 1490 int label_nulls = 0; 1491 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; } 1492 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; } 1493 assert(label_nulls <= 1, "at most one null in the batch"); 1494 1495 // a couple of useful fields in sub_klass: 1496 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 1497 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 1498 Address secondary_supers_addr(sub_klass, ss_offset); 1499 Address super_cache_addr( sub_klass, sc_offset); 1500 1501 BLOCK_COMMENT("check_klass_subtype_slow_path"); 1502 1503 // Do a linear scan of the secondary super-klass chain. 1504 // This code is rarely used, so simplicity is a virtue here. 1505 // The repne_scan instruction uses fixed registers, which we must spill. 1506 // Don't worry too much about pre-existing connections with the input regs. 1507 1508 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super) 1509 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter) 1510 1511 RegSet pushed_registers; 1512 if (!IS_A_TEMP(r2)) pushed_registers += r2; 1513 if (!IS_A_TEMP(r5)) pushed_registers += r5; 1514 1515 if (super_klass != r0) { 1516 if (!IS_A_TEMP(r0)) pushed_registers += r0; 1517 } 1518 1519 push(pushed_registers, sp); 1520 1521 // Get super_klass value into r0 (even if it was in r5 or r2). 1522 if (super_klass != r0) { 1523 mov(r0, super_klass); 1524 } 1525 1526 #ifndef PRODUCT 1527 incrementw(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr)); 1528 #endif //PRODUCT 1529 1530 // We will consult the secondary-super array. 1531 ldr(r5, secondary_supers_addr); 1532 // Load the array length. 1533 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes())); 1534 // Skip to start of data. 1535 add(r5, r5, Array<Klass*>::base_offset_in_bytes()); 1536 1537 cmp(sp, zr); // Clear Z flag; SP is never zero 1538 // Scan R2 words at [R5] for an occurrence of R0. 1539 // Set NZ/Z based on last compare. 1540 repne_scan(r5, r0, r2, rscratch1); 1541 1542 // Unspill the temp. registers: 1543 pop(pushed_registers, sp); 1544 1545 br(Assembler::NE, *L_failure); 1546 1547 // Success. Cache the super we found and proceed in triumph. 1548 1549 if (UseSecondarySupersCache) { 1550 str(super_klass, super_cache_addr); 1551 } 1552 1553 if (L_success != &L_fallthrough) { 1554 b(*L_success); 1555 } 1556 1557 #undef IS_A_TEMP 1558 1559 bind(L_fallthrough); 1560 } 1561 1562 // If Register r is invalid, remove a new register from 1563 // available_regs, and add new register to regs_to_push. 1564 Register MacroAssembler::allocate_if_noreg(Register r, 1565 RegSetIterator<Register> &available_regs, 1566 RegSet ®s_to_push) { 1567 if (!r->is_valid()) { 1568 r = *available_regs++; 1569 regs_to_push += r; 1570 } 1571 return r; 1572 } 1573 1574 // check_klass_subtype_slow_path_table() looks for super_klass in the 1575 // hash table belonging to super_klass, branching to L_success or 1576 // L_failure as appropriate. This is essentially a shim which 1577 // allocates registers as necessary then calls 1578 // lookup_secondary_supers_table() to do the work. Any of the temp 1579 // regs may be noreg, in which case this logic will chooses some 1580 // registers push and pop them from the stack. 1581 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass, 1582 Register super_klass, 1583 Register temp_reg, 1584 Register temp2_reg, 1585 Register temp3_reg, 1586 Register result_reg, 1587 FloatRegister vtemp, 1588 Label* L_success, 1589 Label* L_failure, 1590 bool set_cond_codes) { 1591 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg); 1592 1593 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1); 1594 1595 Label L_fallthrough; 1596 int label_nulls = 0; 1597 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; } 1598 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; } 1599 assert(label_nulls <= 1, "at most one null in the batch"); 1600 1601 BLOCK_COMMENT("check_klass_subtype_slow_path"); 1602 1603 RegSetIterator<Register> available_regs 1604 = (RegSet::range(r0, r15) - temps - sub_klass - super_klass).begin(); 1605 1606 RegSet pushed_regs; 1607 1608 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs); 1609 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs); 1610 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs); 1611 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs); 1612 1613 push(pushed_regs, sp); 1614 1615 lookup_secondary_supers_table_var(sub_klass, 1616 super_klass, 1617 temp_reg, temp2_reg, temp3_reg, vtemp, result_reg, 1618 nullptr); 1619 cmp(result_reg, zr); 1620 1621 // Unspill the temp. registers: 1622 pop(pushed_regs, sp); 1623 1624 // NB! Callers may assume that, when set_cond_codes is true, this 1625 // code sets temp2_reg to a nonzero value. 1626 if (set_cond_codes) { 1627 mov(temp2_reg, 1); 1628 } 1629 1630 br(Assembler::NE, *L_failure); 1631 1632 if (L_success != &L_fallthrough) { 1633 b(*L_success); 1634 } 1635 1636 bind(L_fallthrough); 1637 } 1638 1639 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 1640 Register super_klass, 1641 Register temp_reg, 1642 Register temp2_reg, 1643 Label* L_success, 1644 Label* L_failure, 1645 bool set_cond_codes) { 1646 if (UseSecondarySupersTable) { 1647 check_klass_subtype_slow_path_table 1648 (sub_klass, super_klass, temp_reg, temp2_reg, /*temp3*/noreg, /*result*/noreg, 1649 /*vtemp*/fnoreg, 1650 L_success, L_failure, set_cond_codes); 1651 } else { 1652 check_klass_subtype_slow_path_linear 1653 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes); 1654 } 1655 } 1656 1657 1658 // Ensure that the inline code and the stub are using the same registers. 1659 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \ 1660 do { \ 1661 assert(r_super_klass == r0 && \ 1662 r_array_base == r1 && \ 1663 r_array_length == r2 && \ 1664 (r_array_index == r3 || r_array_index == noreg) && \ 1665 (r_sub_klass == r4 || r_sub_klass == noreg) && \ 1666 (r_bitmap == rscratch2 || r_bitmap == noreg) && \ 1667 (result == r5 || result == noreg), "registers must match aarch64.ad"); \ 1668 } while(0) 1669 1670 bool MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass, 1671 Register r_super_klass, 1672 Register temp1, 1673 Register temp2, 1674 Register temp3, 1675 FloatRegister vtemp, 1676 Register result, 1677 u1 super_klass_slot, 1678 bool stub_is_near) { 1679 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2); 1680 1681 Label L_fallthrough; 1682 1683 BLOCK_COMMENT("lookup_secondary_supers_table {"); 1684 1685 const Register 1686 r_array_base = temp1, // r1 1687 r_array_length = temp2, // r2 1688 r_array_index = temp3, // r3 1689 r_bitmap = rscratch2; 1690 1691 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS; 1692 1693 u1 bit = super_klass_slot; 1694 1695 // Make sure that result is nonzero if the TBZ below misses. 1696 mov(result, 1); 1697 1698 // We're going to need the bitmap in a vector reg and in a core reg, 1699 // so load both now. 1700 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset())); 1701 if (bit != 0) { 1702 ldrd(vtemp, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset())); 1703 } 1704 // First check the bitmap to see if super_klass might be present. If 1705 // the bit is zero, we are certain that super_klass is not one of 1706 // the secondary supers. 1707 tbz(r_bitmap, bit, L_fallthrough); 1708 1709 // Get the first array index that can contain super_klass into r_array_index. 1710 if (bit != 0) { 1711 shld(vtemp, vtemp, Klass::SECONDARY_SUPERS_TABLE_MASK - bit); 1712 cnt(vtemp, T8B, vtemp); 1713 addv(vtemp, T8B, vtemp); 1714 fmovd(r_array_index, vtemp); 1715 } else { 1716 mov(r_array_index, (u1)1); 1717 } 1718 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word. 1719 1720 // We will consult the secondary-super array. 1721 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset()))); 1722 1723 // The value i in r_array_index is >= 1, so even though r_array_base 1724 // points to the length, we don't need to adjust it to point to the 1725 // data. 1726 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code"); 1727 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code"); 1728 1729 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord))); 1730 eor(result, result, r_super_klass); 1731 cbz(result, L_fallthrough); // Found a match 1732 1733 // Is there another entry to check? Consult the bitmap. 1734 tbz(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK, L_fallthrough); 1735 1736 // Linear probe. 1737 if (bit != 0) { 1738 ror(r_bitmap, r_bitmap, bit); 1739 } 1740 1741 // The slot we just inspected is at secondary_supers[r_array_index - 1]. 1742 // The next slot to be inspected, by the stub we're about to call, 1743 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap 1744 // have been checked. 1745 Address stub = RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()); 1746 if (stub_is_near) { 1747 bl(stub); 1748 } else { 1749 address call = trampoline_call(stub); 1750 if (call == nullptr) { 1751 return false; // trampoline allocation failed 1752 } 1753 } 1754 1755 BLOCK_COMMENT("} lookup_secondary_supers_table"); 1756 1757 bind(L_fallthrough); 1758 1759 if (VerifySecondarySupers) { 1760 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0 1761 temp1, temp2, result); // r1, r2, r5 1762 } 1763 return true; 1764 } 1765 1766 // At runtime, return 0 in result if r_super_klass is a superclass of 1767 // r_sub_klass, otherwise return nonzero. Use this version of 1768 // lookup_secondary_supers_table() if you don't know ahead of time 1769 // which superclass will be searched for. Used by interpreter and 1770 // runtime stubs. It is larger and has somewhat greater latency than 1771 // the version above, which takes a constant super_klass_slot. 1772 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass, 1773 Register r_super_klass, 1774 Register temp1, 1775 Register temp2, 1776 Register temp3, 1777 FloatRegister vtemp, 1778 Register result, 1779 Label *L_success) { 1780 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2); 1781 1782 Label L_fallthrough; 1783 1784 BLOCK_COMMENT("lookup_secondary_supers_table {"); 1785 1786 const Register 1787 r_array_index = temp3, 1788 slot = rscratch1, 1789 r_bitmap = rscratch2; 1790 1791 ldrb(slot, Address(r_super_klass, Klass::hash_slot_offset())); 1792 1793 // Make sure that result is nonzero if the test below misses. 1794 mov(result, 1); 1795 1796 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset())); 1797 1798 // First check the bitmap to see if super_klass might be present. If 1799 // the bit is zero, we are certain that super_klass is not one of 1800 // the secondary supers. 1801 1802 // This next instruction is equivalent to: 1803 // mov(tmp_reg, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); 1804 // sub(temp2, tmp_reg, slot); 1805 eor(temp2, slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); 1806 lslv(temp2, r_bitmap, temp2); 1807 tbz(temp2, Klass::SECONDARY_SUPERS_TABLE_SIZE - 1, L_fallthrough); 1808 1809 bool must_save_v0 = (vtemp == fnoreg); 1810 if (must_save_v0) { 1811 // temp1 and result are free, so use them to preserve vtemp 1812 vtemp = v0; 1813 mov(temp1, vtemp, D, 0); 1814 mov(result, vtemp, D, 1); 1815 } 1816 1817 // Get the first array index that can contain super_klass into r_array_index. 1818 mov(vtemp, D, 0, temp2); 1819 cnt(vtemp, T8B, vtemp); 1820 addv(vtemp, T8B, vtemp); 1821 mov(r_array_index, vtemp, D, 0); 1822 1823 if (must_save_v0) { 1824 mov(vtemp, D, 0, temp1 ); 1825 mov(vtemp, D, 1, result); 1826 } 1827 1828 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word. 1829 1830 const Register 1831 r_array_base = temp1, 1832 r_array_length = temp2; 1833 1834 // The value i in r_array_index is >= 1, so even though r_array_base 1835 // points to the length, we don't need to adjust it to point to the 1836 // data. 1837 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code"); 1838 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code"); 1839 1840 // We will consult the secondary-super array. 1841 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset()))); 1842 1843 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord))); 1844 eor(result, result, r_super_klass); 1845 cbz(result, L_success ? *L_success : L_fallthrough); // Found a match 1846 1847 // Is there another entry to check? Consult the bitmap. 1848 rorv(r_bitmap, r_bitmap, slot); 1849 // rol(r_bitmap, r_bitmap, 1); 1850 tbz(r_bitmap, 1, L_fallthrough); 1851 1852 // The slot we just inspected is at secondary_supers[r_array_index - 1]. 1853 // The next slot to be inspected, by the logic we're about to call, 1854 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap 1855 // have been checked. 1856 lookup_secondary_supers_table_slow_path(r_super_klass, r_array_base, r_array_index, 1857 r_bitmap, r_array_length, result, /*is_stub*/false); 1858 1859 BLOCK_COMMENT("} lookup_secondary_supers_table"); 1860 1861 bind(L_fallthrough); 1862 1863 if (VerifySecondarySupers) { 1864 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0 1865 temp1, temp2, result); // r1, r2, r5 1866 } 1867 1868 if (L_success) { 1869 cbz(result, *L_success); 1870 } 1871 } 1872 1873 // Called by code generated by check_klass_subtype_slow_path 1874 // above. This is called when there is a collision in the hashed 1875 // lookup in the secondary supers array. 1876 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass, 1877 Register r_array_base, 1878 Register r_array_index, 1879 Register r_bitmap, 1880 Register temp1, 1881 Register result, 1882 bool is_stub) { 1883 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, result, rscratch1); 1884 1885 const Register 1886 r_array_length = temp1, 1887 r_sub_klass = noreg; // unused 1888 1889 if (is_stub) { 1890 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS; 1891 } 1892 1893 Label L_fallthrough, L_huge; 1894 1895 // Load the array length. 1896 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes())); 1897 // And adjust the array base to point to the data. 1898 // NB! Effectively increments current slot index by 1. 1899 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, ""); 1900 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes()); 1901 1902 // The bitmap is full to bursting. 1903 // Implicit invariant: BITMAP_FULL implies (length > 0) 1904 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), ""); 1905 cmpw(r_array_length, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 2)); 1906 br(GT, L_huge); 1907 1908 // NB! Our caller has checked bits 0 and 1 in the bitmap. The 1909 // current slot (at secondary_supers[r_array_index]) has not yet 1910 // been inspected, and r_array_index may be out of bounds if we 1911 // wrapped around the end of the array. 1912 1913 { // This is conventional linear probing, but instead of terminating 1914 // when a null entry is found in the table, we maintain a bitmap 1915 // in which a 0 indicates missing entries. 1916 // As long as the bitmap is not completely full, 1917 // array_length == popcount(bitmap). The array_length check above 1918 // guarantees there are 0s in the bitmap, so the loop eventually 1919 // terminates. 1920 Label L_loop; 1921 bind(L_loop); 1922 1923 // Check for wraparound. 1924 cmp(r_array_index, r_array_length); 1925 csel(r_array_index, zr, r_array_index, GE); 1926 1927 ldr(rscratch1, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord))); 1928 eor(result, rscratch1, r_super_klass); 1929 cbz(result, L_fallthrough); 1930 1931 tbz(r_bitmap, 2, L_fallthrough); // look-ahead check (Bit 2); result is non-zero 1932 1933 ror(r_bitmap, r_bitmap, 1); 1934 add(r_array_index, r_array_index, 1); 1935 b(L_loop); 1936 } 1937 1938 { // Degenerate case: more than 64 secondary supers. 1939 // FIXME: We could do something smarter here, maybe a vectorized 1940 // comparison or a binary search, but is that worth any added 1941 // complexity? 1942 bind(L_huge); 1943 cmp(sp, zr); // Clear Z flag; SP is never zero 1944 repne_scan(r_array_base, r_super_klass, r_array_length, rscratch1); 1945 cset(result, NE); // result == 0 iff we got a match. 1946 } 1947 1948 bind(L_fallthrough); 1949 } 1950 1951 // Make sure that the hashed lookup and a linear scan agree. 1952 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass, 1953 Register r_super_klass, 1954 Register temp1, 1955 Register temp2, 1956 Register result) { 1957 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, result, rscratch1); 1958 1959 const Register 1960 r_array_base = temp1, 1961 r_array_length = temp2; 1962 1963 BLOCK_COMMENT("verify_secondary_supers_table {"); 1964 1965 // We will consult the secondary-super array. 1966 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset()))); 1967 1968 // Load the array length. 1969 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes())); 1970 // And adjust the array base to point to the data. 1971 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes()); 1972 1973 cmp(sp, zr); // Clear Z flag; SP is never zero 1974 // Scan R2 words at [R5] for an occurrence of R0. 1975 // Set NZ/Z based on last compare. 1976 repne_scan(/*addr*/r_array_base, /*value*/r_super_klass, /*count*/r_array_length, rscratch2); 1977 // rscratch1 == 0 iff we got a match. 1978 cset(rscratch1, NE); 1979 1980 Label passed; 1981 cmp(result, zr); 1982 cset(result, NE); // normalize result to 0/1 for comparison 1983 1984 cmp(rscratch1, result); 1985 br(EQ, passed); 1986 { 1987 mov(r0, r_super_klass); // r0 <- r0 1988 mov(r1, r_sub_klass); // r1 <- r4 1989 mov(r2, /*expected*/rscratch1); // r2 <- r8 1990 mov(r3, result); // r3 <- r5 1991 mov(r4, (address)("mismatch")); // r4 <- const 1992 rt_call(CAST_FROM_FN_PTR(address, Klass::on_secondary_supers_verification_failure), rscratch2); 1993 should_not_reach_here(); 1994 } 1995 bind(passed); 1996 1997 BLOCK_COMMENT("} verify_secondary_supers_table"); 1998 } 1999 2000 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) { 2001 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required"); 2002 assert_different_registers(klass, rthread, scratch); 2003 2004 Label L_fallthrough, L_tmp; 2005 if (L_fast_path == nullptr) { 2006 L_fast_path = &L_fallthrough; 2007 } else if (L_slow_path == nullptr) { 2008 L_slow_path = &L_fallthrough; 2009 } 2010 // Fast path check: class is fully initialized 2011 lea(scratch, Address(klass, InstanceKlass::init_state_offset())); 2012 ldarb(scratch, scratch); 2013 cmp(scratch, InstanceKlass::fully_initialized); 2014 br(Assembler::EQ, *L_fast_path); 2015 2016 // Fast path check: current thread is initializer thread 2017 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset())); 2018 cmp(rthread, scratch); 2019 2020 if (L_slow_path == &L_fallthrough) { 2021 br(Assembler::EQ, *L_fast_path); 2022 bind(*L_slow_path); 2023 } else if (L_fast_path == &L_fallthrough) { 2024 br(Assembler::NE, *L_slow_path); 2025 bind(*L_fast_path); 2026 } else { 2027 Unimplemented(); 2028 } 2029 } 2030 2031 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) { 2032 if (!VerifyOops || VerifyAdapterSharing) { 2033 // Below address of the code string confuses VerifyAdapterSharing 2034 // because it may differ between otherwise equivalent adapters. 2035 return; 2036 } 2037 2038 // Pass register number to verify_oop_subroutine 2039 const char* b = nullptr; 2040 { 2041 ResourceMark rm; 2042 stringStream ss; 2043 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line); 2044 b = code_string(ss.as_string()); 2045 } 2046 BLOCK_COMMENT("verify_oop {"); 2047 2048 strip_return_address(); // This might happen within a stack frame. 2049 protect_return_address(); 2050 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 2051 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 2052 2053 mov(r0, reg); 2054 movptr(rscratch1, (uintptr_t)(address)b); 2055 2056 // call indirectly to solve generation ordering problem 2057 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address())); 2058 ldr(rscratch2, Address(rscratch2)); 2059 blr(rscratch2); 2060 2061 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 2062 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 2063 authenticate_return_address(); 2064 2065 BLOCK_COMMENT("} verify_oop"); 2066 } 2067 2068 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) { 2069 if (!VerifyOops || VerifyAdapterSharing) { 2070 // Below address of the code string confuses VerifyAdapterSharing 2071 // because it may differ between otherwise equivalent adapters. 2072 return; 2073 } 2074 2075 const char* b = nullptr; 2076 { 2077 ResourceMark rm; 2078 stringStream ss; 2079 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line); 2080 b = code_string(ss.as_string()); 2081 } 2082 BLOCK_COMMENT("verify_oop_addr {"); 2083 2084 strip_return_address(); // This might happen within a stack frame. 2085 protect_return_address(); 2086 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 2087 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 2088 2089 // addr may contain sp so we will have to adjust it based on the 2090 // pushes that we just did. 2091 if (addr.uses(sp)) { 2092 lea(r0, addr); 2093 ldr(r0, Address(r0, 4 * wordSize)); 2094 } else { 2095 ldr(r0, addr); 2096 } 2097 movptr(rscratch1, (uintptr_t)(address)b); 2098 2099 // call indirectly to solve generation ordering problem 2100 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address())); 2101 ldr(rscratch2, Address(rscratch2)); 2102 blr(rscratch2); 2103 2104 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 2105 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 2106 authenticate_return_address(); 2107 2108 BLOCK_COMMENT("} verify_oop_addr"); 2109 } 2110 2111 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 2112 int extra_slot_offset) { 2113 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 2114 int stackElementSize = Interpreter::stackElementSize; 2115 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 2116 #ifdef ASSERT 2117 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 2118 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 2119 #endif 2120 if (arg_slot.is_constant()) { 2121 return Address(esp, arg_slot.as_constant() * stackElementSize 2122 + offset); 2123 } else { 2124 add(rscratch1, esp, arg_slot.as_register(), 2125 ext::uxtx, exact_log2(stackElementSize)); 2126 return Address(rscratch1, offset); 2127 } 2128 } 2129 2130 // Handle the receiver type profile update given the "recv" klass. 2131 // 2132 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset". 2133 // If there are no matching or claimable receiver entries in RD, updates 2134 // the polymorphic counter. 2135 // 2136 // This code expected to run by either the interpreter or JIT-ed code, without 2137 // extra synchronization. For safety, receiver cells are claimed atomically, which 2138 // avoids grossly misrepresenting the profiles under concurrent updates. For speed, 2139 // counter updates are not atomic. 2140 // 2141 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) { 2142 assert_different_registers(recv, mdp, rscratch1, rscratch2); 2143 2144 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0)); 2145 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit())); 2146 int poly_count_offset = in_bytes(CounterData::count_offset()); 2147 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset; 2148 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset; 2149 2150 // Adjust for MDP offsets. 2151 base_receiver_offset += mdp_offset; 2152 end_receiver_offset += mdp_offset; 2153 poly_count_offset += mdp_offset; 2154 2155 #ifdef ASSERT 2156 // We are about to walk the MDO slots without asking for offsets. 2157 // Check that our math hits all the right spots. 2158 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) { 2159 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c)); 2160 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c)); 2161 int offset = base_receiver_offset + receiver_step*c; 2162 int count_offset = offset + receiver_to_count_step; 2163 assert(offset == real_recv_offset, "receiver slot math"); 2164 assert(count_offset == real_count_offset, "receiver count math"); 2165 } 2166 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset()); 2167 assert(poly_count_offset == real_poly_count_offset, "poly counter math"); 2168 #endif 2169 2170 // Corner case: no profile table. Increment poly counter and exit. 2171 if (ReceiverTypeData::row_limit() == 0) { 2172 increment(Address(mdp, poly_count_offset), DataLayout::counter_increment); 2173 return; 2174 } 2175 2176 Register offset = rscratch2; 2177 2178 Label L_loop_search_receiver, L_loop_search_empty; 2179 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update; 2180 2181 // The code here recognizes three major cases: 2182 // A. Fastest: receiver found in the table 2183 // B. Fast: no receiver in the table, and the table is full 2184 // C. Slow: no receiver in the table, free slots in the table 2185 // 2186 // The case A performance is most important, as perfectly-behaved code would end up 2187 // there, especially with larger TypeProfileWidth. The case B performance is 2188 // important as well, this is where bulk of code would land for normally megamorphic 2189 // cases. The case C performance is not essential, its job is to deal with installation 2190 // races, we optimize for code density instead. Case C needs to make sure that receiver 2191 // rows are only claimed once. This makes sure we never overwrite a row for another 2192 // receiver and never duplicate the receivers in the list, making profile type-accurate. 2193 // 2194 // It is very tempting to handle these cases in a single loop, and claim the first slot 2195 // without checking the rest of the table. But, profiling code should tolerate free slots 2196 // in the table, as class unloading can clear them. After such cleanup, the receiver 2197 // we need might be _after_ the free slot. Therefore, we need to let at least full scan 2198 // to complete, before trying to install new slots. Splitting the code in several tight 2199 // loops also helpfully optimizes for cases A and B. 2200 // 2201 // This code is effectively: 2202 // 2203 // restart: 2204 // // Fastest: receiver is already installed 2205 // for (i = 0; i < receiver_count(); i++) { 2206 // if (receiver(i) == recv) goto found_recv(i); 2207 // } 2208 // 2209 // // Fast: no receiver, but profile is full 2210 // for (i = 0; i < receiver_count(); i++) { 2211 // if (receiver(i) == null) goto found_null(i); 2212 // } 2213 // goto polymorphic 2214 // 2215 // // Slow: try to install receiver 2216 // found_null(i): 2217 // CAS(&receiver(i), null, recv); 2218 // goto restart 2219 // 2220 // polymorphic: 2221 // count++; 2222 // return 2223 // 2224 // found_recv(i): 2225 // *receiver_count(i)++ 2226 // 2227 2228 bind(L_restart); 2229 2230 // Fastest: receiver is already installed 2231 mov(offset, base_receiver_offset); 2232 bind(L_loop_search_receiver); 2233 ldr(rscratch1, Address(mdp, offset)); 2234 cmp(rscratch1, recv); 2235 br(Assembler::EQ, L_found_recv); 2236 add(offset, offset, receiver_step); 2237 sub(rscratch1, offset, end_receiver_offset); 2238 cbnz(rscratch1, L_loop_search_receiver); 2239 2240 // Fast: no receiver, but profile is full 2241 mov(offset, base_receiver_offset); 2242 bind(L_loop_search_empty); 2243 ldr(rscratch1, Address(mdp, offset)); 2244 cbz(rscratch1, L_found_empty); 2245 add(offset, offset, receiver_step); 2246 sub(rscratch1, offset, end_receiver_offset); 2247 cbnz(rscratch1, L_loop_search_empty); 2248 b(L_polymorphic); 2249 2250 // Slow: try to install receiver 2251 bind(L_found_empty); 2252 2253 // Atomically swing receiver slot: null -> recv. 2254 // 2255 // The update uses CAS, which clobbers rscratch1. Therefore, rscratch2 2256 // is used to hold the destination address. This is safe because the 2257 // offset is no longer needed after the address is computed. 2258 2259 lea(rscratch2, Address(mdp, offset)); 2260 cmpxchg(/*addr*/ rscratch2, /*expected*/ zr, /*new*/ recv, Assembler::xword, 2261 /*acquire*/ false, /*release*/ false, /*weak*/ true, noreg); 2262 2263 // CAS success means the slot now has the receiver we want. CAS failure means 2264 // something had claimed the slot concurrently: it can be the same receiver we want, 2265 // or something else. Since this is a slow path, we can optimize for code density, 2266 // and just restart the search from the beginning. 2267 b(L_restart); 2268 2269 // Counter updates: 2270 2271 // Increment polymorphic counter instead of receiver slot. 2272 bind(L_polymorphic); 2273 mov(offset, poly_count_offset); 2274 b(L_count_update); 2275 2276 // Found a receiver, convert its slot offset to corresponding count offset. 2277 bind(L_found_recv); 2278 add(offset, offset, receiver_to_count_step); 2279 2280 bind(L_count_update); 2281 increment(Address(mdp, offset), DataLayout::counter_increment); 2282 } 2283 2284 2285 void MacroAssembler::call_VM_leaf_base(address entry_point, 2286 int number_of_arguments, 2287 Label *retaddr) { 2288 Label E, L; 2289 2290 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize))); 2291 2292 mov(rscratch1, RuntimeAddress(entry_point)); 2293 blr(rscratch1); 2294 if (retaddr) 2295 bind(*retaddr); 2296 2297 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize))); 2298 } 2299 2300 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 2301 call_VM_leaf_base(entry_point, number_of_arguments); 2302 } 2303 2304 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 2305 pass_arg0(this, arg_0); 2306 call_VM_leaf_base(entry_point, 1); 2307 } 2308 2309 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2310 assert_different_registers(arg_1, c_rarg0); 2311 pass_arg0(this, arg_0); 2312 pass_arg1(this, arg_1); 2313 call_VM_leaf_base(entry_point, 2); 2314 } 2315 2316 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, 2317 Register arg_1, Register arg_2) { 2318 assert_different_registers(arg_1, c_rarg0); 2319 assert_different_registers(arg_2, c_rarg0, c_rarg1); 2320 pass_arg0(this, arg_0); 2321 pass_arg1(this, arg_1); 2322 pass_arg2(this, arg_2); 2323 call_VM_leaf_base(entry_point, 3); 2324 } 2325 2326 void MacroAssembler::super_call_VM_leaf(address entry_point) { 2327 MacroAssembler::call_VM_leaf_base(entry_point, 1); 2328 } 2329 2330 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 2331 pass_arg0(this, arg_0); 2332 MacroAssembler::call_VM_leaf_base(entry_point, 1); 2333 } 2334 2335 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2336 2337 assert_different_registers(arg_0, c_rarg1); 2338 pass_arg1(this, arg_1); 2339 pass_arg0(this, arg_0); 2340 MacroAssembler::call_VM_leaf_base(entry_point, 2); 2341 } 2342 2343 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2344 assert_different_registers(arg_0, c_rarg1, c_rarg2); 2345 assert_different_registers(arg_1, c_rarg2); 2346 pass_arg2(this, arg_2); 2347 pass_arg1(this, arg_1); 2348 pass_arg0(this, arg_0); 2349 MacroAssembler::call_VM_leaf_base(entry_point, 3); 2350 } 2351 2352 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 2353 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3); 2354 assert_different_registers(arg_1, c_rarg2, c_rarg3); 2355 assert_different_registers(arg_2, c_rarg3); 2356 pass_arg3(this, arg_3); 2357 pass_arg2(this, arg_2); 2358 pass_arg1(this, arg_1); 2359 pass_arg0(this, arg_0); 2360 MacroAssembler::call_VM_leaf_base(entry_point, 4); 2361 } 2362 2363 void MacroAssembler::null_check(Register reg, int offset) { 2364 if (needs_explicit_null_check(offset)) { 2365 // provoke OS null exception if reg is null by 2366 // accessing M[reg] w/o changing any registers 2367 // NOTE: this is plenty to provoke a segv 2368 ldr(zr, Address(reg)); 2369 } else { 2370 // nothing to do, (later) access of M[reg + offset] 2371 // will provoke OS null exception if reg is null 2372 } 2373 } 2374 2375 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) { 2376 assert_different_registers(markword, rscratch2); 2377 mov(rscratch2, markWord::inline_type_mask_in_place); 2378 andr(markword, markword, rscratch2); 2379 mov(rscratch2, markWord::inline_type_pattern); 2380 cmp(markword, rscratch2); 2381 br(Assembler::EQ, is_inline_type); 2382 } 2383 2384 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null) { 2385 assert_different_registers(tmp, rscratch1); 2386 if (can_be_null) { 2387 cbz(object, not_inline_type); 2388 } 2389 const int is_inline_type_mask = markWord::inline_type_pattern; 2390 ldr(tmp, Address(object, oopDesc::mark_offset_in_bytes())); 2391 mov(rscratch1, is_inline_type_mask); 2392 andr(tmp, tmp, rscratch1); 2393 cmp(tmp, rscratch1); 2394 br(Assembler::NE, not_inline_type); 2395 } 2396 2397 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) { 2398 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86 2399 tbnz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, is_null_free_inline_type); 2400 } 2401 2402 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) { 2403 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86 2404 tbz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, not_null_free_inline_type); 2405 } 2406 2407 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) { 2408 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86 2409 tbnz(flags, ResolvedFieldEntry::is_flat_shift, is_flat); 2410 } 2411 2412 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) { 2413 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86 2414 tbnz(flags, ResolvedFieldEntry::has_null_marker_shift, has_null_marker); 2415 } 2416 2417 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) { 2418 Label test_mark_word; 2419 // load mark word 2420 ldr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes())); 2421 // check displaced 2422 tst(temp_reg, markWord::unlocked_value); 2423 br(Assembler::NE, test_mark_word); 2424 // slow path use klass prototype 2425 load_prototype_header(temp_reg, oop); 2426 2427 bind(test_mark_word); 2428 andr(temp_reg, temp_reg, test_bit); 2429 if (jmp_set) { 2430 cbnz(temp_reg, jmp_label); 2431 } else { 2432 cbz(temp_reg, jmp_label); 2433 } 2434 } 2435 2436 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array) { 2437 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array); 2438 } 2439 2440 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg, 2441 Label&is_non_flat_array) { 2442 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array); 2443 } 2444 2445 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array) { 2446 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array); 2447 } 2448 2449 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) { 2450 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array); 2451 } 2452 2453 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) { 2454 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace); 2455 br(Assembler::NE, is_flat_array); 2456 } 2457 2458 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) { 2459 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace); 2460 br(Assembler::EQ, is_non_flat_array); 2461 } 2462 2463 // MacroAssembler protected routines needed to implement 2464 // public methods 2465 2466 void MacroAssembler::mov(Register r, Address dest) { 2467 code_section()->relocate(pc(), dest.rspec()); 2468 uint64_t imm64 = (uint64_t)dest.target(); 2469 movptr(r, imm64); 2470 } 2471 2472 // Move a constant pointer into r. In AArch64 mode the virtual 2473 // address space is 48 bits in size, so we only need three 2474 // instructions to create a patchable instruction sequence that can 2475 // reach anywhere. 2476 void MacroAssembler::movptr(Register r, uintptr_t imm64) { 2477 #ifndef PRODUCT 2478 { 2479 char buffer[64]; 2480 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64); 2481 block_comment(buffer); 2482 } 2483 #endif 2484 assert(imm64 < (1ull << 48), "48-bit overflow in address constant"); 2485 movz(r, imm64 & 0xffff); 2486 imm64 >>= 16; 2487 movk(r, imm64 & 0xffff, 16); 2488 imm64 >>= 16; 2489 movk(r, imm64 & 0xffff, 32); 2490 } 2491 2492 // Macro to mov replicated immediate to vector register. 2493 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is, 2494 // the upper 56/48/32 bits must be zeros for B/H/S type. 2495 // Vd will get the following values for different arrangements in T 2496 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh 2497 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh 2498 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh 2499 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh 2500 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh 2501 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh 2502 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh 2503 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh 2504 // Clobbers rscratch1 2505 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) { 2506 assert(T != T1Q, "unsupported"); 2507 if (T == T1D || T == T2D) { 2508 int imm = operand_valid_for_movi_immediate(imm64, T); 2509 if (-1 != imm) { 2510 movi(Vd, T, imm); 2511 } else { 2512 mov(rscratch1, imm64); 2513 dup(Vd, T, rscratch1); 2514 } 2515 return; 2516 } 2517 2518 #ifdef ASSERT 2519 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)"); 2520 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)"); 2521 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)"); 2522 #endif 2523 int shift = operand_valid_for_movi_immediate(imm64, T); 2524 uint32_t imm32 = imm64 & 0xffffffffULL; 2525 if (shift >= 0) { 2526 movi(Vd, T, (imm32 >> shift) & 0xff, shift); 2527 } else { 2528 movw(rscratch1, imm32); 2529 dup(Vd, T, rscratch1); 2530 } 2531 } 2532 2533 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64) 2534 { 2535 #ifndef PRODUCT 2536 { 2537 char buffer[64]; 2538 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, imm64); 2539 block_comment(buffer); 2540 } 2541 #endif 2542 if (operand_valid_for_logical_immediate(false, imm64)) { 2543 orr(dst, zr, imm64); 2544 } else { 2545 // we can use a combination of MOVZ or MOVN with 2546 // MOVK to build up the constant 2547 uint64_t imm_h[4]; 2548 int zero_count = 0; 2549 int neg_count = 0; 2550 int i; 2551 for (i = 0; i < 4; i++) { 2552 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL); 2553 if (imm_h[i] == 0) { 2554 zero_count++; 2555 } else if (imm_h[i] == 0xffffL) { 2556 neg_count++; 2557 } 2558 } 2559 if (zero_count == 4) { 2560 // one MOVZ will do 2561 movz(dst, 0); 2562 } else if (neg_count == 4) { 2563 // one MOVN will do 2564 movn(dst, 0); 2565 } else if (zero_count == 3) { 2566 for (i = 0; i < 4; i++) { 2567 if (imm_h[i] != 0L) { 2568 movz(dst, (uint32_t)imm_h[i], (i << 4)); 2569 break; 2570 } 2571 } 2572 } else if (neg_count == 3) { 2573 // one MOVN will do 2574 for (int i = 0; i < 4; i++) { 2575 if (imm_h[i] != 0xffffL) { 2576 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4)); 2577 break; 2578 } 2579 } 2580 } else if (zero_count == 2) { 2581 // one MOVZ and one MOVK will do 2582 for (i = 0; i < 3; i++) { 2583 if (imm_h[i] != 0L) { 2584 movz(dst, (uint32_t)imm_h[i], (i << 4)); 2585 i++; 2586 break; 2587 } 2588 } 2589 for (;i < 4; i++) { 2590 if (imm_h[i] != 0L) { 2591 movk(dst, (uint32_t)imm_h[i], (i << 4)); 2592 } 2593 } 2594 } else if (neg_count == 2) { 2595 // one MOVN and one MOVK will do 2596 for (i = 0; i < 4; i++) { 2597 if (imm_h[i] != 0xffffL) { 2598 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4)); 2599 i++; 2600 break; 2601 } 2602 } 2603 for (;i < 4; i++) { 2604 if (imm_h[i] != 0xffffL) { 2605 movk(dst, (uint32_t)imm_h[i], (i << 4)); 2606 } 2607 } 2608 } else if (zero_count == 1) { 2609 // one MOVZ and two MOVKs will do 2610 for (i = 0; i < 4; i++) { 2611 if (imm_h[i] != 0L) { 2612 movz(dst, (uint32_t)imm_h[i], (i << 4)); 2613 i++; 2614 break; 2615 } 2616 } 2617 for (;i < 4; i++) { 2618 if (imm_h[i] != 0x0L) { 2619 movk(dst, (uint32_t)imm_h[i], (i << 4)); 2620 } 2621 } 2622 } else if (neg_count == 1) { 2623 // one MOVN and two MOVKs will do 2624 for (i = 0; i < 4; i++) { 2625 if (imm_h[i] != 0xffffL) { 2626 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4)); 2627 i++; 2628 break; 2629 } 2630 } 2631 for (;i < 4; i++) { 2632 if (imm_h[i] != 0xffffL) { 2633 movk(dst, (uint32_t)imm_h[i], (i << 4)); 2634 } 2635 } 2636 } else { 2637 // use a MOVZ and 3 MOVKs (makes it easier to debug) 2638 movz(dst, (uint32_t)imm_h[0], 0); 2639 for (i = 1; i < 4; i++) { 2640 movk(dst, (uint32_t)imm_h[i], (i << 4)); 2641 } 2642 } 2643 } 2644 } 2645 2646 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32) 2647 { 2648 #ifndef PRODUCT 2649 { 2650 char buffer[64]; 2651 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX32, imm32); 2652 block_comment(buffer); 2653 } 2654 #endif 2655 if (operand_valid_for_logical_immediate(true, imm32)) { 2656 orrw(dst, zr, imm32); 2657 } else { 2658 // we can use MOVZ, MOVN or two calls to MOVK to build up the 2659 // constant 2660 uint32_t imm_h[2]; 2661 imm_h[0] = imm32 & 0xffff; 2662 imm_h[1] = ((imm32 >> 16) & 0xffff); 2663 if (imm_h[0] == 0) { 2664 movzw(dst, imm_h[1], 16); 2665 } else if (imm_h[0] == 0xffff) { 2666 movnw(dst, imm_h[1] ^ 0xffff, 16); 2667 } else if (imm_h[1] == 0) { 2668 movzw(dst, imm_h[0], 0); 2669 } else if (imm_h[1] == 0xffff) { 2670 movnw(dst, imm_h[0] ^ 0xffff, 0); 2671 } else { 2672 // use a MOVZ and MOVK (makes it easier to debug) 2673 movzw(dst, imm_h[0], 0); 2674 movkw(dst, imm_h[1], 16); 2675 } 2676 } 2677 } 2678 2679 // Form an address from base + offset in Rd. Rd may or may 2680 // not actually be used: you must use the Address that is returned. 2681 // It is up to you to ensure that the shift provided matches the size 2682 // of your data. 2683 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) { 2684 if (Address::offset_ok_for_immed(byte_offset, shift)) 2685 // It fits; no need for any heroics 2686 return Address(base, byte_offset); 2687 2688 // Don't do anything clever with negative or misaligned offsets 2689 unsigned mask = (1 << shift) - 1; 2690 if (byte_offset < 0 || byte_offset & mask) { 2691 mov(Rd, byte_offset); 2692 add(Rd, base, Rd); 2693 return Address(Rd); 2694 } 2695 2696 // See if we can do this with two 12-bit offsets 2697 { 2698 uint64_t word_offset = byte_offset >> shift; 2699 uint64_t masked_offset = word_offset & 0xfff000; 2700 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0) 2701 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) { 2702 add(Rd, base, masked_offset << shift); 2703 word_offset -= masked_offset; 2704 return Address(Rd, word_offset << shift); 2705 } 2706 } 2707 2708 // Do it the hard way 2709 mov(Rd, byte_offset); 2710 add(Rd, base, Rd); 2711 return Address(Rd); 2712 } 2713 2714 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb, 2715 bool want_remainder, Register scratch) 2716 { 2717 // Full implementation of Java idiv and irem. The function 2718 // returns the (pc) offset of the div instruction - may be needed 2719 // for implicit exceptions. 2720 // 2721 // constraint : ra/rb =/= scratch 2722 // normal case 2723 // 2724 // input : ra: dividend 2725 // rb: divisor 2726 // 2727 // result: either 2728 // quotient (= ra idiv rb) 2729 // remainder (= ra irem rb) 2730 2731 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 2732 2733 int idivl_offset = offset(); 2734 if (! want_remainder) { 2735 sdivw(result, ra, rb); 2736 } else { 2737 sdivw(scratch, ra, rb); 2738 Assembler::msubw(result, scratch, rb, ra); 2739 } 2740 2741 return idivl_offset; 2742 } 2743 2744 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb, 2745 bool want_remainder, Register scratch) 2746 { 2747 // Full implementation of Java ldiv and lrem. The function 2748 // returns the (pc) offset of the div instruction - may be needed 2749 // for implicit exceptions. 2750 // 2751 // constraint : ra/rb =/= scratch 2752 // normal case 2753 // 2754 // input : ra: dividend 2755 // rb: divisor 2756 // 2757 // result: either 2758 // quotient (= ra idiv rb) 2759 // remainder (= ra irem rb) 2760 2761 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 2762 2763 int idivq_offset = offset(); 2764 if (! want_remainder) { 2765 sdiv(result, ra, rb); 2766 } else { 2767 sdiv(scratch, ra, rb); 2768 Assembler::msub(result, scratch, rb, ra); 2769 } 2770 2771 return idivq_offset; 2772 } 2773 2774 void MacroAssembler::membar(Membar_mask_bits order_constraint) { 2775 address prev = pc() - NativeMembar::instruction_size; 2776 address last = code()->last_insn(); 2777 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) { 2778 NativeMembar *bar = NativeMembar_at(prev); 2779 if (AlwaysMergeDMB) { 2780 bar->set_kind(bar->get_kind() | order_constraint); 2781 BLOCK_COMMENT("merged membar(always)"); 2782 return; 2783 } 2784 // Don't promote DMB ST|DMB LD to DMB (a full barrier) because 2785 // doing so would introduce a StoreLoad which the caller did not 2786 // intend 2787 if (bar->get_kind() == order_constraint 2788 || bar->get_kind() == AnyAny 2789 || order_constraint == AnyAny) { 2790 // We are merging two memory barrier instructions. On AArch64 we 2791 // can do this simply by ORing them together. 2792 bar->set_kind(bar->get_kind() | order_constraint); 2793 BLOCK_COMMENT("merged membar"); 2794 return; 2795 } else { 2796 // A special case like "DMB ST;DMB LD;DMB ST", the last DMB can be skipped 2797 // We need check the last 2 instructions 2798 address prev2 = prev - NativeMembar::instruction_size; 2799 if (last != code()->last_label() && nativeInstruction_at(prev2)->is_Membar()) { 2800 NativeMembar *bar2 = NativeMembar_at(prev2); 2801 assert(bar2->get_kind() == order_constraint, "it should be merged before"); 2802 BLOCK_COMMENT("merged membar(elided)"); 2803 return; 2804 } 2805 } 2806 } 2807 code()->set_last_insn(pc()); 2808 dmb(Assembler::barrier(order_constraint)); 2809 } 2810 2811 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) { 2812 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) { 2813 merge_ldst(rt, adr, size_in_bytes, is_store); 2814 code()->clear_last_insn(); 2815 return true; 2816 } else { 2817 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported."); 2818 const uint64_t mask = size_in_bytes - 1; 2819 if (adr.getMode() == Address::base_plus_offset && 2820 (adr.offset() & mask) == 0) { // only supports base_plus_offset. 2821 code()->set_last_insn(pc()); 2822 } 2823 return false; 2824 } 2825 } 2826 2827 void MacroAssembler::ldr(Register Rx, const Address &adr) { 2828 // We always try to merge two adjacent loads into one ldp. 2829 if (!try_merge_ldst(Rx, adr, 8, false)) { 2830 Assembler::ldr(Rx, adr); 2831 } 2832 } 2833 2834 void MacroAssembler::ldrw(Register Rw, const Address &adr) { 2835 // We always try to merge two adjacent loads into one ldp. 2836 if (!try_merge_ldst(Rw, adr, 4, false)) { 2837 Assembler::ldrw(Rw, adr); 2838 } 2839 } 2840 2841 void MacroAssembler::str(Register Rx, const Address &adr) { 2842 // We always try to merge two adjacent stores into one stp. 2843 if (!try_merge_ldst(Rx, adr, 8, true)) { 2844 Assembler::str(Rx, adr); 2845 } 2846 } 2847 2848 void MacroAssembler::strw(Register Rw, const Address &adr) { 2849 // We always try to merge two adjacent stores into one stp. 2850 if (!try_merge_ldst(Rw, adr, 4, true)) { 2851 Assembler::strw(Rw, adr); 2852 } 2853 } 2854 2855 // MacroAssembler routines found actually to be needed 2856 2857 void MacroAssembler::push(Register src) 2858 { 2859 str(src, Address(pre(esp, -1 * wordSize))); 2860 } 2861 2862 void MacroAssembler::pop(Register dst) 2863 { 2864 ldr(dst, Address(post(esp, 1 * wordSize))); 2865 } 2866 2867 // Note: load_unsigned_short used to be called load_unsigned_word. 2868 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 2869 int off = offset(); 2870 ldrh(dst, src); 2871 return off; 2872 } 2873 2874 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 2875 int off = offset(); 2876 ldrb(dst, src); 2877 return off; 2878 } 2879 2880 int MacroAssembler::load_signed_short(Register dst, Address src) { 2881 int off = offset(); 2882 ldrsh(dst, src); 2883 return off; 2884 } 2885 2886 int MacroAssembler::load_signed_byte(Register dst, Address src) { 2887 int off = offset(); 2888 ldrsb(dst, src); 2889 return off; 2890 } 2891 2892 int MacroAssembler::load_signed_short32(Register dst, Address src) { 2893 int off = offset(); 2894 ldrshw(dst, src); 2895 return off; 2896 } 2897 2898 int MacroAssembler::load_signed_byte32(Register dst, Address src) { 2899 int off = offset(); 2900 ldrsbw(dst, src); 2901 return off; 2902 } 2903 2904 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) { 2905 switch (size_in_bytes) { 2906 case 8: ldr(dst, src); break; 2907 case 4: ldrw(dst, src); break; 2908 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 2909 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 2910 default: ShouldNotReachHere(); 2911 } 2912 } 2913 2914 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) { 2915 switch (size_in_bytes) { 2916 case 8: str(src, dst); break; 2917 case 4: strw(src, dst); break; 2918 case 2: strh(src, dst); break; 2919 case 1: strb(src, dst); break; 2920 default: ShouldNotReachHere(); 2921 } 2922 } 2923 2924 void MacroAssembler::decrementw(Register reg, int value) 2925 { 2926 if (value < 0) { incrementw(reg, -value); return; } 2927 if (value == 0) { return; } 2928 if (value < (1 << 12)) { subw(reg, reg, value); return; } 2929 /* else */ { 2930 guarantee(reg != rscratch2, "invalid dst for register decrement"); 2931 movw(rscratch2, (unsigned)value); 2932 subw(reg, reg, rscratch2); 2933 } 2934 } 2935 2936 void MacroAssembler::decrement(Register reg, int value) 2937 { 2938 if (value < 0) { increment(reg, -value); return; } 2939 if (value == 0) { return; } 2940 if (value < (1 << 12)) { sub(reg, reg, value); return; } 2941 /* else */ { 2942 assert(reg != rscratch2, "invalid dst for register decrement"); 2943 mov(rscratch2, (uint64_t)value); 2944 sub(reg, reg, rscratch2); 2945 } 2946 } 2947 2948 void MacroAssembler::decrementw(Address dst, int value) 2949 { 2950 assert(!dst.uses(rscratch1), "invalid dst for address decrement"); 2951 if (dst.getMode() == Address::literal) { 2952 assert(abs(value) < (1 << 12), "invalid value and address mode combination"); 2953 lea(rscratch2, dst); 2954 dst = Address(rscratch2); 2955 } 2956 ldrw(rscratch1, dst); 2957 decrementw(rscratch1, value); 2958 strw(rscratch1, dst); 2959 } 2960 2961 void MacroAssembler::decrement(Address dst, int value) 2962 { 2963 assert(!dst.uses(rscratch1), "invalid address for decrement"); 2964 if (dst.getMode() == Address::literal) { 2965 assert(abs(value) < (1 << 12), "invalid value and address mode combination"); 2966 lea(rscratch2, dst); 2967 dst = Address(rscratch2); 2968 } 2969 ldr(rscratch1, dst); 2970 decrement(rscratch1, value); 2971 str(rscratch1, dst); 2972 } 2973 2974 void MacroAssembler::incrementw(Register reg, int value) 2975 { 2976 if (value < 0) { decrementw(reg, -value); return; } 2977 if (value == 0) { return; } 2978 if (value < (1 << 12)) { addw(reg, reg, value); return; } 2979 /* else */ { 2980 assert(reg != rscratch2, "invalid dst for register increment"); 2981 movw(rscratch2, (unsigned)value); 2982 addw(reg, reg, rscratch2); 2983 } 2984 } 2985 2986 void MacroAssembler::increment(Register reg, int value) 2987 { 2988 if (value < 0) { decrement(reg, -value); return; } 2989 if (value == 0) { return; } 2990 if (value < (1 << 12)) { add(reg, reg, value); return; } 2991 /* else */ { 2992 assert(reg != rscratch2, "invalid dst for register increment"); 2993 movw(rscratch2, (unsigned)value); 2994 add(reg, reg, rscratch2); 2995 } 2996 } 2997 2998 void MacroAssembler::incrementw(Address dst, int value) 2999 { 3000 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 3001 if (dst.getMode() == Address::literal) { 3002 assert(abs(value) < (1 << 12), "invalid value and address mode combination"); 3003 lea(rscratch2, dst); 3004 dst = Address(rscratch2); 3005 } 3006 ldrw(rscratch1, dst); 3007 incrementw(rscratch1, value); 3008 strw(rscratch1, dst); 3009 } 3010 3011 void MacroAssembler::increment(Address dst, int value) 3012 { 3013 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 3014 if (dst.getMode() == Address::literal) { 3015 assert(abs(value) < (1 << 12), "invalid value and address mode combination"); 3016 lea(rscratch2, dst); 3017 dst = Address(rscratch2); 3018 } 3019 ldr(rscratch1, dst); 3020 increment(rscratch1, value); 3021 str(rscratch1, dst); 3022 } 3023 3024 // Push lots of registers in the bit set supplied. Don't push sp. 3025 // Return the number of words pushed 3026 int MacroAssembler::push(unsigned int bitset, Register stack) { 3027 int words_pushed = 0; 3028 3029 // Scan bitset to accumulate register pairs 3030 unsigned char regs[32]; 3031 int count = 0; 3032 for (int reg = 0; reg <= 30; reg++) { 3033 if (1 & bitset) 3034 regs[count++] = reg; 3035 bitset >>= 1; 3036 } 3037 regs[count++] = zr->raw_encoding(); 3038 count &= ~1; // Only push an even number of regs 3039 3040 if (count) { 3041 stp(as_Register(regs[0]), as_Register(regs[1]), 3042 Address(pre(stack, -count * wordSize))); 3043 words_pushed += 2; 3044 } 3045 for (int i = 2; i < count; i += 2) { 3046 stp(as_Register(regs[i]), as_Register(regs[i+1]), 3047 Address(stack, i * wordSize)); 3048 words_pushed += 2; 3049 } 3050 3051 assert(words_pushed == count, "oops, pushed != count"); 3052 3053 return count; 3054 } 3055 3056 int MacroAssembler::pop(unsigned int bitset, Register stack) { 3057 int words_pushed = 0; 3058 3059 // Scan bitset to accumulate register pairs 3060 unsigned char regs[32]; 3061 int count = 0; 3062 for (int reg = 0; reg <= 30; reg++) { 3063 if (1 & bitset) 3064 regs[count++] = reg; 3065 bitset >>= 1; 3066 } 3067 regs[count++] = zr->raw_encoding(); 3068 count &= ~1; 3069 3070 for (int i = 2; i < count; i += 2) { 3071 ldp(as_Register(regs[i]), as_Register(regs[i+1]), 3072 Address(stack, i * wordSize)); 3073 words_pushed += 2; 3074 } 3075 if (count) { 3076 ldp(as_Register(regs[0]), as_Register(regs[1]), 3077 Address(post(stack, count * wordSize))); 3078 words_pushed += 2; 3079 } 3080 3081 assert(words_pushed == count, "oops, pushed != count"); 3082 3083 return count; 3084 } 3085 3086 // Push lots of registers in the bit set supplied. Don't push sp. 3087 // Return the number of dwords pushed 3088 int MacroAssembler::push_fp(unsigned int bitset, Register stack, FpPushPopMode mode) { 3089 int words_pushed = 0; 3090 bool use_sve = false; 3091 int sve_vector_size_in_bytes = 0; 3092 3093 #ifdef COMPILER2 3094 use_sve = Matcher::supports_scalable_vector(); 3095 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE); 3096 #endif 3097 3098 // Scan bitset to accumulate register pairs 3099 unsigned char regs[32]; 3100 int count = 0; 3101 for (int reg = 0; reg <= 31; reg++) { 3102 if (1 & bitset) 3103 regs[count++] = reg; 3104 bitset >>= 1; 3105 } 3106 3107 if (count == 0) { 3108 return 0; 3109 } 3110 3111 if (mode == PushPopFull) { 3112 if (use_sve && sve_vector_size_in_bytes > 16) { 3113 mode = PushPopSVE; 3114 } else { 3115 mode = PushPopNeon; 3116 } 3117 } 3118 3119 #ifndef PRODUCT 3120 { 3121 char buffer[48]; 3122 if (mode == PushPopSVE) { 3123 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d SVE registers", count); 3124 } else if (mode == PushPopNeon) { 3125 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d Neon registers", count); 3126 } else { 3127 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d fp registers", count); 3128 } 3129 block_comment(buffer); 3130 } 3131 #endif 3132 3133 if (mode == PushPopSVE) { 3134 sub(stack, stack, sve_vector_size_in_bytes * count); 3135 for (int i = 0; i < count; i++) { 3136 sve_str(as_FloatRegister(regs[i]), Address(stack, i)); 3137 } 3138 return count * sve_vector_size_in_bytes / 8; 3139 } 3140 3141 if (mode == PushPopNeon) { 3142 if (count == 1) { 3143 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2))); 3144 return 2; 3145 } 3146 3147 bool odd = (count & 1) == 1; 3148 int push_slots = count + (odd ? 1 : 0); 3149 3150 // Always pushing full 128 bit registers. 3151 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2))); 3152 words_pushed += 2; 3153 3154 for (int i = 2; i + 1 < count; i += 2) { 3155 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2)); 3156 words_pushed += 2; 3157 } 3158 3159 if (odd) { 3160 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2)); 3161 words_pushed++; 3162 } 3163 3164 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count); 3165 return count * 2; 3166 } 3167 3168 if (mode == PushPopFp) { 3169 bool odd = (count & 1) == 1; 3170 int push_slots = count + (odd ? 1 : 0); 3171 3172 if (count == 1) { 3173 // Stack pointer must be 16 bytes aligned 3174 strd(as_FloatRegister(regs[0]), Address(pre(stack, -push_slots * wordSize))); 3175 return 1; 3176 } 3177 3178 stpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize))); 3179 words_pushed += 2; 3180 3181 for (int i = 2; i + 1 < count; i += 2) { 3182 stpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize)); 3183 words_pushed += 2; 3184 } 3185 3186 if (odd) { 3187 // Stack pointer must be 16 bytes aligned 3188 strd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize)); 3189 words_pushed++; 3190 } 3191 3192 assert(words_pushed == count, "oops, pushed != count"); 3193 3194 return count; 3195 } 3196 3197 return 0; 3198 } 3199 3200 // Return the number of dwords popped 3201 int MacroAssembler::pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode) { 3202 int words_pushed = 0; 3203 bool use_sve = false; 3204 int sve_vector_size_in_bytes = 0; 3205 3206 #ifdef COMPILER2 3207 use_sve = Matcher::supports_scalable_vector(); 3208 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE); 3209 #endif 3210 // Scan bitset to accumulate register pairs 3211 unsigned char regs[32]; 3212 int count = 0; 3213 for (int reg = 0; reg <= 31; reg++) { 3214 if (1 & bitset) 3215 regs[count++] = reg; 3216 bitset >>= 1; 3217 } 3218 3219 if (count == 0) { 3220 return 0; 3221 } 3222 3223 if (mode == PushPopFull) { 3224 if (use_sve && sve_vector_size_in_bytes > 16) { 3225 mode = PushPopSVE; 3226 } else { 3227 mode = PushPopNeon; 3228 } 3229 } 3230 3231 #ifndef PRODUCT 3232 { 3233 char buffer[48]; 3234 if (mode == PushPopSVE) { 3235 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d SVE registers", count); 3236 } else if (mode == PushPopNeon) { 3237 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d Neon registers", count); 3238 } else { 3239 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d fp registers", count); 3240 } 3241 block_comment(buffer); 3242 } 3243 #endif 3244 3245 if (mode == PushPopSVE) { 3246 for (int i = count - 1; i >= 0; i--) { 3247 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i)); 3248 } 3249 add(stack, stack, sve_vector_size_in_bytes * count); 3250 return count * sve_vector_size_in_bytes / 8; 3251 } 3252 3253 if (mode == PushPopNeon) { 3254 if (count == 1) { 3255 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2))); 3256 return 2; 3257 } 3258 3259 bool odd = (count & 1) == 1; 3260 int push_slots = count + (odd ? 1 : 0); 3261 3262 if (odd) { 3263 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2)); 3264 words_pushed++; 3265 } 3266 3267 for (int i = 2; i + 1 < count; i += 2) { 3268 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2)); 3269 words_pushed += 2; 3270 } 3271 3272 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2))); 3273 words_pushed += 2; 3274 3275 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count); 3276 3277 return count * 2; 3278 } 3279 3280 if (mode == PushPopFp) { 3281 bool odd = (count & 1) == 1; 3282 int push_slots = count + (odd ? 1 : 0); 3283 3284 if (count == 1) { 3285 ldrd(as_FloatRegister(regs[0]), Address(post(stack, push_slots * wordSize))); 3286 return 1; 3287 } 3288 3289 if (odd) { 3290 ldrd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize)); 3291 words_pushed++; 3292 } 3293 3294 for (int i = 2; i + 1 < count; i += 2) { 3295 ldpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize)); 3296 words_pushed += 2; 3297 } 3298 3299 ldpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize))); 3300 words_pushed += 2; 3301 3302 assert(words_pushed == count, "oops, pushed != count"); 3303 3304 return count; 3305 } 3306 3307 return 0; 3308 } 3309 3310 // Return the number of dwords pushed 3311 int MacroAssembler::push_p(unsigned int bitset, Register stack) { 3312 bool use_sve = false; 3313 int sve_predicate_size_in_slots = 0; 3314 3315 #ifdef COMPILER2 3316 use_sve = Matcher::supports_scalable_vector(); 3317 if (use_sve) { 3318 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots(); 3319 } 3320 #endif 3321 3322 if (!use_sve) { 3323 return 0; 3324 } 3325 3326 unsigned char regs[PRegister::number_of_registers]; 3327 int count = 0; 3328 for (int reg = 0; reg < PRegister::number_of_registers; reg++) { 3329 if (1 & bitset) 3330 regs[count++] = reg; 3331 bitset >>= 1; 3332 } 3333 3334 if (count == 0) { 3335 return 0; 3336 } 3337 3338 int total_push_bytes = align_up(sve_predicate_size_in_slots * 3339 VMRegImpl::stack_slot_size * count, 16); 3340 sub(stack, stack, total_push_bytes); 3341 for (int i = 0; i < count; i++) { 3342 sve_str(as_PRegister(regs[i]), Address(stack, i)); 3343 } 3344 return total_push_bytes / 8; 3345 } 3346 3347 // Return the number of dwords popped 3348 int MacroAssembler::pop_p(unsigned int bitset, Register stack) { 3349 bool use_sve = false; 3350 int sve_predicate_size_in_slots = 0; 3351 3352 #ifdef COMPILER2 3353 use_sve = Matcher::supports_scalable_vector(); 3354 if (use_sve) { 3355 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots(); 3356 } 3357 #endif 3358 3359 if (!use_sve) { 3360 return 0; 3361 } 3362 3363 unsigned char regs[PRegister::number_of_registers]; 3364 int count = 0; 3365 for (int reg = 0; reg < PRegister::number_of_registers; reg++) { 3366 if (1 & bitset) 3367 regs[count++] = reg; 3368 bitset >>= 1; 3369 } 3370 3371 if (count == 0) { 3372 return 0; 3373 } 3374 3375 int total_pop_bytes = align_up(sve_predicate_size_in_slots * 3376 VMRegImpl::stack_slot_size * count, 16); 3377 for (int i = count - 1; i >= 0; i--) { 3378 sve_ldr(as_PRegister(regs[i]), Address(stack, i)); 3379 } 3380 add(stack, stack, total_pop_bytes); 3381 return total_pop_bytes / 8; 3382 } 3383 3384 #ifdef ASSERT 3385 void MacroAssembler::verify_heapbase(const char* msg) { 3386 #if 0 3387 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed"); 3388 assert (Universe::heap() != nullptr, "java heap should be initialized"); 3389 if (!UseCompressedOops || Universe::ptr_base() == nullptr) { 3390 // rheapbase is allocated as general register 3391 return; 3392 } 3393 if (CheckCompressedOops) { 3394 Label ok; 3395 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1 3396 cmpptr(rheapbase, ExternalAddress(CompressedOops::base_addr())); 3397 br(Assembler::EQ, ok); 3398 stop(msg); 3399 bind(ok); 3400 pop(1 << rscratch1->encoding(), sp); 3401 } 3402 #endif 3403 } 3404 #endif 3405 3406 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) { 3407 assert_different_registers(value, tmp1, tmp2); 3408 Label done, tagged, weak_tagged; 3409 3410 cbz(value, done); // Use null as-is. 3411 tst(value, JNIHandles::tag_mask); // Test for tag. 3412 br(Assembler::NE, tagged); 3413 3414 // Resolve local handle 3415 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2); 3416 verify_oop(value); 3417 b(done); 3418 3419 bind(tagged); 3420 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1); 3421 tbnz(value, 0, weak_tagged); // Test for weak tag. 3422 3423 // Resolve global handle 3424 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2); 3425 verify_oop(value); 3426 b(done); 3427 3428 bind(weak_tagged); 3429 // Resolve jweak. 3430 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, 3431 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2); 3432 verify_oop(value); 3433 3434 bind(done); 3435 } 3436 3437 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) { 3438 assert_different_registers(value, tmp1, tmp2); 3439 Label done; 3440 3441 cbz(value, done); // Use null as-is. 3442 3443 #ifdef ASSERT 3444 { 3445 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10); 3446 Label valid_global_tag; 3447 tbnz(value, 1, valid_global_tag); // Test for global tag 3448 stop("non global jobject using resolve_global_jobject"); 3449 bind(valid_global_tag); 3450 } 3451 #endif 3452 3453 // Resolve global handle 3454 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2); 3455 verify_oop(value); 3456 3457 bind(done); 3458 } 3459 3460 void MacroAssembler::stop(const char* msg) { 3461 // Skip AOT caching C strings in scratch buffer. 3462 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg); 3463 BLOCK_COMMENT(str); 3464 // load msg into r0 so we can access it from the signal handler 3465 // ExternalAddress enables saving and restoring via the code cache 3466 lea(c_rarg0, ExternalAddress((address) str)); 3467 dcps1(0xdeae); 3468 } 3469 3470 void MacroAssembler::unimplemented(const char* what) { 3471 const char* buf = nullptr; 3472 { 3473 ResourceMark rm; 3474 stringStream ss; 3475 ss.print("unimplemented: %s", what); 3476 buf = code_string(ss.as_string()); 3477 } 3478 stop(buf); 3479 } 3480 3481 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) { 3482 #ifdef ASSERT 3483 Label OK; 3484 br(cc, OK); 3485 stop(msg); 3486 bind(OK); 3487 #endif 3488 } 3489 3490 // If a constant does not fit in an immediate field, generate some 3491 // number of MOV instructions and then perform the operation. 3492 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm, 3493 add_sub_imm_insn insn1, 3494 add_sub_reg_insn insn2, 3495 bool is32) { 3496 assert(Rd != zr, "Rd = zr and not setting flags?"); 3497 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm); 3498 if (fits) { 3499 (this->*insn1)(Rd, Rn, imm); 3500 } else { 3501 if (g_uabs(imm) < (1 << 24)) { 3502 (this->*insn1)(Rd, Rn, imm & -(1 << 12)); 3503 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1)); 3504 } else { 3505 assert_different_registers(Rd, Rn); 3506 mov(Rd, imm); 3507 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 3508 } 3509 } 3510 } 3511 3512 // Separate vsn which sets the flags. Optimisations are more restricted 3513 // because we must set the flags correctly. 3514 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm, 3515 add_sub_imm_insn insn1, 3516 add_sub_reg_insn insn2, 3517 bool is32) { 3518 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm); 3519 if (fits) { 3520 (this->*insn1)(Rd, Rn, imm); 3521 } else { 3522 assert_different_registers(Rd, Rn); 3523 assert(Rd != zr, "overflow in immediate operand"); 3524 mov(Rd, imm); 3525 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 3526 } 3527 } 3528 3529 3530 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) { 3531 if (increment.is_register()) { 3532 add(Rd, Rn, increment.as_register()); 3533 } else { 3534 add(Rd, Rn, increment.as_constant()); 3535 } 3536 } 3537 3538 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) { 3539 if (increment.is_register()) { 3540 addw(Rd, Rn, increment.as_register()); 3541 } else { 3542 addw(Rd, Rn, increment.as_constant()); 3543 } 3544 } 3545 3546 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) { 3547 if (decrement.is_register()) { 3548 sub(Rd, Rn, decrement.as_register()); 3549 } else { 3550 sub(Rd, Rn, decrement.as_constant()); 3551 } 3552 } 3553 3554 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) { 3555 if (decrement.is_register()) { 3556 subw(Rd, Rn, decrement.as_register()); 3557 } else { 3558 subw(Rd, Rn, decrement.as_constant()); 3559 } 3560 } 3561 3562 void MacroAssembler::reinit_heapbase() 3563 { 3564 if (UseCompressedOops) { 3565 if (Universe::is_fully_initialized()) { 3566 mov(rheapbase, CompressedOops::base()); 3567 } else { 3568 lea(rheapbase, ExternalAddress(CompressedOops::base_addr())); 3569 ldr(rheapbase, Address(rheapbase)); 3570 } 3571 } 3572 } 3573 3574 // A generic CAS; success or failure is in the EQ flag. A weak CAS 3575 // doesn't retry and may fail spuriously. If the oldval is wanted, 3576 // Pass a register for the result, otherwise pass noreg. 3577 3578 // Clobbers rscratch1 3579 void MacroAssembler::cmpxchg(Register addr, Register expected, 3580 Register new_val, 3581 enum operand_size size, 3582 bool acquire, bool release, 3583 bool weak, 3584 Register result) { 3585 if (result == noreg) result = rscratch1; 3586 BLOCK_COMMENT("cmpxchg {"); 3587 if (UseLSE) { 3588 mov(result, expected); 3589 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true); 3590 compare_eq(result, expected, size); 3591 #ifdef ASSERT 3592 // Poison rscratch1 which is written on !UseLSE branch 3593 mov(rscratch1, 0x1f1f1f1f1f1f1f1f); 3594 #endif 3595 } else { 3596 Label retry_load, done; 3597 prfm(Address(addr), PSTL1STRM); 3598 bind(retry_load); 3599 load_exclusive(result, addr, size, acquire); 3600 compare_eq(result, expected, size); 3601 br(Assembler::NE, done); 3602 store_exclusive(rscratch1, new_val, addr, size, release); 3603 if (weak) { 3604 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller. 3605 } else { 3606 cbnzw(rscratch1, retry_load); 3607 } 3608 bind(done); 3609 } 3610 BLOCK_COMMENT("} cmpxchg"); 3611 } 3612 3613 // A generic comparison. Only compares for equality, clobbers rscratch1. 3614 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) { 3615 if (size == xword) { 3616 cmp(rm, rn); 3617 } else if (size == word) { 3618 cmpw(rm, rn); 3619 } else if (size == halfword) { 3620 eorw(rscratch1, rm, rn); 3621 ands(zr, rscratch1, 0xffff); 3622 } else if (size == byte) { 3623 eorw(rscratch1, rm, rn); 3624 ands(zr, rscratch1, 0xff); 3625 } else { 3626 ShouldNotReachHere(); 3627 } 3628 } 3629 3630 3631 static bool different(Register a, RegisterOrConstant b, Register c) { 3632 if (b.is_constant()) 3633 return a != c; 3634 else 3635 return a != b.as_register() && a != c && b.as_register() != c; 3636 } 3637 3638 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \ 3639 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \ 3640 if (UseLSE) { \ 3641 prev = prev->is_valid() ? prev : zr; \ 3642 if (incr.is_register()) { \ 3643 AOP(sz, incr.as_register(), prev, addr); \ 3644 } else { \ 3645 mov(rscratch2, incr.as_constant()); \ 3646 AOP(sz, rscratch2, prev, addr); \ 3647 } \ 3648 return; \ 3649 } \ 3650 Register result = rscratch2; \ 3651 if (prev->is_valid()) \ 3652 result = different(prev, incr, addr) ? prev : rscratch2; \ 3653 \ 3654 Label retry_load; \ 3655 prfm(Address(addr), PSTL1STRM); \ 3656 bind(retry_load); \ 3657 LDXR(result, addr); \ 3658 OP(rscratch1, result, incr); \ 3659 STXR(rscratch2, rscratch1, addr); \ 3660 cbnzw(rscratch2, retry_load); \ 3661 if (prev->is_valid() && prev != result) { \ 3662 IOP(prev, rscratch1, incr); \ 3663 } \ 3664 } 3665 3666 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword) 3667 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word) 3668 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword) 3669 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word) 3670 3671 #undef ATOMIC_OP 3672 3673 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \ 3674 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \ 3675 if (UseLSE) { \ 3676 prev = prev->is_valid() ? prev : zr; \ 3677 AOP(sz, newv, prev, addr); \ 3678 return; \ 3679 } \ 3680 Register result = rscratch2; \ 3681 if (prev->is_valid()) \ 3682 result = different(prev, newv, addr) ? prev : rscratch2; \ 3683 \ 3684 Label retry_load; \ 3685 prfm(Address(addr), PSTL1STRM); \ 3686 bind(retry_load); \ 3687 LDXR(result, addr); \ 3688 STXR(rscratch1, newv, addr); \ 3689 cbnzw(rscratch1, retry_load); \ 3690 if (prev->is_valid() && prev != result) \ 3691 mov(prev, result); \ 3692 } 3693 3694 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword) 3695 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word) 3696 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword) 3697 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word) 3698 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword) 3699 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word) 3700 3701 #undef ATOMIC_XCHG 3702 3703 #ifndef PRODUCT 3704 extern "C" void findpc(intptr_t x); 3705 #endif 3706 3707 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) 3708 { 3709 // In order to get locks to work, we need to fake a in_VM state 3710 if (ShowMessageBoxOnError) { 3711 JavaThread* thread = JavaThread::current(); 3712 thread->set_thread_state(_thread_in_vm); 3713 #ifndef PRODUCT 3714 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 3715 ttyLocker ttyl; 3716 BytecodeCounter::print(); 3717 } 3718 #endif 3719 if (os::message_box(msg, "Execution stopped, print registers?")) { 3720 ttyLocker ttyl; 3721 tty->print_cr(" pc = 0x%016" PRIx64, pc); 3722 #ifndef PRODUCT 3723 tty->cr(); 3724 findpc(pc); 3725 tty->cr(); 3726 #endif 3727 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]); 3728 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]); 3729 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]); 3730 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]); 3731 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]); 3732 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]); 3733 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]); 3734 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]); 3735 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]); 3736 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]); 3737 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]); 3738 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]); 3739 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]); 3740 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]); 3741 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]); 3742 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]); 3743 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]); 3744 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]); 3745 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]); 3746 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]); 3747 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]); 3748 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]); 3749 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]); 3750 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]); 3751 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]); 3752 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]); 3753 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]); 3754 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]); 3755 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]); 3756 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]); 3757 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]); 3758 BREAKPOINT; 3759 } 3760 } 3761 fatal("DEBUG MESSAGE: %s", msg); 3762 } 3763 3764 RegSet MacroAssembler::call_clobbered_gp_registers() { 3765 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2); 3766 #ifndef R18_RESERVED 3767 regs += r18_tls; 3768 #endif 3769 return regs; 3770 } 3771 3772 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) { 3773 int step = 4 * wordSize; 3774 push(call_clobbered_gp_registers() - exclude, sp); 3775 sub(sp, sp, step); 3776 mov(rscratch1, -step); 3777 // Push v0-v7, v16-v31. 3778 for (int i = 31; i>= 4; i -= 4) { 3779 if (i <= v7->encoding() || i >= v16->encoding()) 3780 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1), 3781 as_FloatRegister(i), T1D, Address(post(sp, rscratch1))); 3782 } 3783 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2), 3784 as_FloatRegister(3), T1D, Address(sp)); 3785 } 3786 3787 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) { 3788 for (int i = 0; i < 32; i += 4) { 3789 if (i <= v7->encoding() || i >= v16->encoding()) 3790 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2), 3791 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize))); 3792 } 3793 3794 reinitialize_ptrue(); 3795 3796 pop(call_clobbered_gp_registers() - exclude, sp); 3797 } 3798 3799 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve, 3800 int sve_vector_size_in_bytes, int total_predicate_in_bytes) { 3801 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp 3802 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) { 3803 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers); 3804 for (int i = 0; i < FloatRegister::number_of_registers; i++) { 3805 sve_str(as_FloatRegister(i), Address(sp, i)); 3806 } 3807 } else { 3808 int step = (save_vectors ? 8 : 4) * wordSize; 3809 mov(rscratch1, -step); 3810 sub(sp, sp, step); 3811 for (int i = 28; i >= 4; i -= 4) { 3812 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2), 3813 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1))); 3814 } 3815 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp); 3816 } 3817 if (save_vectors && use_sve && total_predicate_in_bytes > 0) { 3818 sub(sp, sp, total_predicate_in_bytes); 3819 for (int i = 0; i < PRegister::number_of_registers; i++) { 3820 sve_str(as_PRegister(i), Address(sp, i)); 3821 } 3822 } 3823 } 3824 3825 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve, 3826 int sve_vector_size_in_bytes, int total_predicate_in_bytes) { 3827 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) { 3828 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) { 3829 sve_ldr(as_PRegister(i), Address(sp, i)); 3830 } 3831 add(sp, sp, total_predicate_in_bytes); 3832 } 3833 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) { 3834 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) { 3835 sve_ldr(as_FloatRegister(i), Address(sp, i)); 3836 } 3837 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers); 3838 } else { 3839 int step = (restore_vectors ? 8 : 4) * wordSize; 3840 for (int i = 0; i <= 28; i += 4) 3841 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2), 3842 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step))); 3843 } 3844 3845 // We may use predicate registers and rely on ptrue with SVE, 3846 // regardless of wide vector (> 8 bytes) used or not. 3847 if (use_sve) { 3848 reinitialize_ptrue(); 3849 } 3850 3851 // integer registers except lr & sp 3852 pop(RegSet::range(r0, r17), sp); 3853 #ifdef R18_RESERVED 3854 ldp(zr, r19, Address(post(sp, 2 * wordSize))); 3855 pop(RegSet::range(r20, r29), sp); 3856 #else 3857 pop(RegSet::range(r18_tls, r29), sp); 3858 #endif 3859 } 3860 3861 /** 3862 * Helpers for multiply_to_len(). 3863 */ 3864 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 3865 Register src1, Register src2) { 3866 adds(dest_lo, dest_lo, src1); 3867 adc(dest_hi, dest_hi, zr); 3868 adds(dest_lo, dest_lo, src2); 3869 adc(final_dest_hi, dest_hi, zr); 3870 } 3871 3872 // Generate an address from (r + r1 extend offset). "size" is the 3873 // size of the operand. The result may be in rscratch2. 3874 Address MacroAssembler::offsetted_address(Register r, Register r1, 3875 Address::extend ext, int offset, int size) { 3876 if (offset || (ext.shift() % size != 0)) { 3877 lea(rscratch2, Address(r, r1, ext)); 3878 return Address(rscratch2, offset); 3879 } else { 3880 return Address(r, r1, ext); 3881 } 3882 } 3883 3884 Address MacroAssembler::spill_address(int size, int offset, Register tmp) 3885 { 3886 assert(offset >= 0, "spill to negative address?"); 3887 // Offset reachable ? 3888 // Not aligned - 9 bits signed offset 3889 // Aligned - 12 bits unsigned offset shifted 3890 Register base = sp; 3891 if ((offset & (size-1)) && offset >= (1<<8)) { 3892 add(tmp, base, offset & ((1<<12)-1)); 3893 base = tmp; 3894 offset &= -1u<<12; 3895 } 3896 3897 if (offset >= (1<<12) * size) { 3898 add(tmp, base, offset & (((1<<12)-1)<<12)); 3899 base = tmp; 3900 offset &= ~(((1<<12)-1)<<12); 3901 } 3902 3903 return Address(base, offset); 3904 } 3905 3906 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) { 3907 assert(offset >= 0, "spill to negative address?"); 3908 3909 Register base = sp; 3910 3911 // An immediate offset in the range 0 to 255 which is multiplied 3912 // by the current vector or predicate register size in bytes. 3913 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) { 3914 return Address(base, offset / sve_reg_size_in_bytes); 3915 } 3916 3917 add(tmp, base, offset); 3918 return Address(tmp); 3919 } 3920 3921 // Checks whether offset is aligned. 3922 // Returns true if it is, else false. 3923 bool MacroAssembler::merge_alignment_check(Register base, 3924 size_t size, 3925 int64_t cur_offset, 3926 int64_t prev_offset) const { 3927 if (AvoidUnalignedAccesses) { 3928 if (base == sp) { 3929 // Checks whether low offset if aligned to pair of registers. 3930 int64_t pair_mask = size * 2 - 1; 3931 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset; 3932 return (offset & pair_mask) == 0; 3933 } else { // If base is not sp, we can't guarantee the access is aligned. 3934 return false; 3935 } 3936 } else { 3937 int64_t mask = size - 1; 3938 // Load/store pair instruction only supports element size aligned offset. 3939 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0; 3940 } 3941 } 3942 3943 // Checks whether current and previous loads/stores can be merged. 3944 // Returns true if it can be merged, else false. 3945 bool MacroAssembler::ldst_can_merge(Register rt, 3946 const Address &adr, 3947 size_t cur_size_in_bytes, 3948 bool is_store) const { 3949 address prev = pc() - NativeInstruction::instruction_size; 3950 address last = code()->last_insn(); 3951 3952 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) { 3953 return false; 3954 } 3955 3956 if (adr.getMode() != Address::base_plus_offset || prev != last) { 3957 return false; 3958 } 3959 3960 NativeLdSt* prev_ldst = NativeLdSt_at(prev); 3961 size_t prev_size_in_bytes = prev_ldst->size_in_bytes(); 3962 3963 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging."); 3964 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging."); 3965 3966 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) { 3967 return false; 3968 } 3969 3970 int64_t max_offset = 63 * prev_size_in_bytes; 3971 int64_t min_offset = -64 * prev_size_in_bytes; 3972 3973 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged."); 3974 3975 // Only same base can be merged. 3976 if (adr.base() != prev_ldst->base()) { 3977 return false; 3978 } 3979 3980 int64_t cur_offset = adr.offset(); 3981 int64_t prev_offset = prev_ldst->offset(); 3982 size_t diff = abs(cur_offset - prev_offset); 3983 if (diff != prev_size_in_bytes) { 3984 return false; 3985 } 3986 3987 // Following cases can not be merged: 3988 // ldr x2, [x2, #8] 3989 // ldr x3, [x2, #16] 3990 // or: 3991 // ldr x2, [x3, #8] 3992 // ldr x2, [x3, #16] 3993 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL. 3994 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) { 3995 return false; 3996 } 3997 3998 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset; 3999 // Offset range must be in ldp/stp instruction's range. 4000 if (low_offset > max_offset || low_offset < min_offset) { 4001 return false; 4002 } 4003 4004 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) { 4005 return true; 4006 } 4007 4008 return false; 4009 } 4010 4011 // Merge current load/store with previous load/store into ldp/stp. 4012 void MacroAssembler::merge_ldst(Register rt, 4013 const Address &adr, 4014 size_t cur_size_in_bytes, 4015 bool is_store) { 4016 4017 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged."); 4018 4019 Register rt_low, rt_high; 4020 address prev = pc() - NativeInstruction::instruction_size; 4021 NativeLdSt* prev_ldst = NativeLdSt_at(prev); 4022 4023 int64_t offset; 4024 4025 if (adr.offset() < prev_ldst->offset()) { 4026 offset = adr.offset(); 4027 rt_low = rt; 4028 rt_high = prev_ldst->target(); 4029 } else { 4030 offset = prev_ldst->offset(); 4031 rt_low = prev_ldst->target(); 4032 rt_high = rt; 4033 } 4034 4035 Address adr_p = Address(prev_ldst->base(), offset); 4036 // Overwrite previous generated binary. 4037 code_section()->set_end(prev); 4038 4039 const size_t sz = prev_ldst->size_in_bytes(); 4040 assert(sz == 8 || sz == 4, "only supports 64/32bit merging."); 4041 if (!is_store) { 4042 BLOCK_COMMENT("merged ldr pair"); 4043 if (sz == 8) { 4044 ldp(rt_low, rt_high, adr_p); 4045 } else { 4046 ldpw(rt_low, rt_high, adr_p); 4047 } 4048 } else { 4049 BLOCK_COMMENT("merged str pair"); 4050 if (sz == 8) { 4051 stp(rt_low, rt_high, adr_p); 4052 } else { 4053 stpw(rt_low, rt_high, adr_p); 4054 } 4055 } 4056 } 4057 4058 /** 4059 * Multiply 64 bit by 64 bit first loop. 4060 */ 4061 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 4062 Register y, Register y_idx, Register z, 4063 Register carry, Register product, 4064 Register idx, Register kdx) { 4065 // 4066 // jlong carry, x[], y[], z[]; 4067 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 4068 // huge_128 product = y[idx] * x[xstart] + carry; 4069 // z[kdx] = (jlong)product; 4070 // carry = (jlong)(product >>> 64); 4071 // } 4072 // z[xstart] = carry; 4073 // 4074 4075 Label L_first_loop, L_first_loop_exit; 4076 Label L_one_x, L_one_y, L_multiply; 4077 4078 subsw(xstart, xstart, 1); 4079 br(Assembler::MI, L_one_x); 4080 4081 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt))); 4082 ldr(x_xstart, Address(rscratch1)); 4083 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian 4084 4085 bind(L_first_loop); 4086 subsw(idx, idx, 1); 4087 br(Assembler::MI, L_first_loop_exit); 4088 subsw(idx, idx, 1); 4089 br(Assembler::MI, L_one_y); 4090 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 4091 ldr(y_idx, Address(rscratch1)); 4092 ror(y_idx, y_idx, 32); // convert big-endian to little-endian 4093 bind(L_multiply); 4094 4095 // AArch64 has a multiply-accumulate instruction that we can't use 4096 // here because it has no way to process carries, so we have to use 4097 // separate add and adc instructions. Bah. 4098 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product 4099 mul(product, x_xstart, y_idx); 4100 adds(product, product, carry); 4101 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product 4102 4103 subw(kdx, kdx, 2); 4104 ror(product, product, 32); // back to big-endian 4105 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong)); 4106 4107 b(L_first_loop); 4108 4109 bind(L_one_y); 4110 ldrw(y_idx, Address(y, 0)); 4111 b(L_multiply); 4112 4113 bind(L_one_x); 4114 ldrw(x_xstart, Address(x, 0)); 4115 b(L_first_loop); 4116 4117 bind(L_first_loop_exit); 4118 } 4119 4120 /** 4121 * Multiply 128 bit by 128. Unrolled inner loop. 4122 * 4123 */ 4124 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z, 4125 Register carry, Register carry2, 4126 Register idx, Register jdx, 4127 Register yz_idx1, Register yz_idx2, 4128 Register tmp, Register tmp3, Register tmp4, 4129 Register tmp6, Register product_hi) { 4130 4131 // jlong carry, x[], y[], z[]; 4132 // int kdx = ystart+1; 4133 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 4134 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry; 4135 // jlong carry2 = (jlong)(tmp3 >>> 64); 4136 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2; 4137 // carry = (jlong)(tmp4 >>> 64); 4138 // z[kdx+idx+1] = (jlong)tmp3; 4139 // z[kdx+idx] = (jlong)tmp4; 4140 // } 4141 // idx += 2; 4142 // if (idx > 0) { 4143 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry; 4144 // z[kdx+idx] = (jlong)yz_idx1; 4145 // carry = (jlong)(yz_idx1 >>> 64); 4146 // } 4147 // 4148 4149 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 4150 4151 lsrw(jdx, idx, 2); 4152 4153 bind(L_third_loop); 4154 4155 subsw(jdx, jdx, 1); 4156 br(Assembler::MI, L_third_loop_exit); 4157 subw(idx, idx, 4); 4158 4159 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 4160 4161 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0)); 4162 4163 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt))); 4164 4165 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 4166 ror(yz_idx2, yz_idx2, 32); 4167 4168 ldp(rscratch2, rscratch1, Address(tmp6, 0)); 4169 4170 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 4171 umulh(tmp4, product_hi, yz_idx1); 4172 4173 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian 4174 ror(rscratch2, rscratch2, 32); 4175 4176 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp 4177 umulh(carry2, product_hi, yz_idx2); 4178 4179 // propagate sum of both multiplications into carry:tmp4:tmp3 4180 adds(tmp3, tmp3, carry); 4181 adc(tmp4, tmp4, zr); 4182 adds(tmp3, tmp3, rscratch1); 4183 adcs(tmp4, tmp4, tmp); 4184 adc(carry, carry2, zr); 4185 adds(tmp4, tmp4, rscratch2); 4186 adc(carry, carry, zr); 4187 4188 ror(tmp3, tmp3, 32); // convert little-endian to big-endian 4189 ror(tmp4, tmp4, 32); 4190 stp(tmp4, tmp3, Address(tmp6, 0)); 4191 4192 b(L_third_loop); 4193 bind (L_third_loop_exit); 4194 4195 andw (idx, idx, 0x3); 4196 cbz(idx, L_post_third_loop_done); 4197 4198 Label L_check_1; 4199 subsw(idx, idx, 2); 4200 br(Assembler::MI, L_check_1); 4201 4202 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 4203 ldr(yz_idx1, Address(rscratch1, 0)); 4204 ror(yz_idx1, yz_idx1, 32); 4205 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 4206 umulh(tmp4, product_hi, yz_idx1); 4207 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt))); 4208 ldr(yz_idx2, Address(rscratch1, 0)); 4209 ror(yz_idx2, yz_idx2, 32); 4210 4211 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2); 4212 4213 ror(tmp3, tmp3, 32); 4214 str(tmp3, Address(rscratch1, 0)); 4215 4216 bind (L_check_1); 4217 4218 andw (idx, idx, 0x1); 4219 subsw(idx, idx, 1); 4220 br(Assembler::MI, L_post_third_loop_done); 4221 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt))); 4222 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3 4223 umulh(carry2, tmp4, product_hi); 4224 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt))); 4225 4226 add2_with_carry(carry2, tmp3, tmp4, carry); 4227 4228 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt))); 4229 extr(carry, carry2, tmp3, 32); 4230 4231 bind(L_post_third_loop_done); 4232 } 4233 4234 /** 4235 * Code for BigInteger::multiplyToLen() intrinsic. 4236 * 4237 * r0: x 4238 * r1: xlen 4239 * r2: y 4240 * r3: ylen 4241 * r4: z 4242 * r5: tmp0 4243 * r10: tmp1 4244 * r11: tmp2 4245 * r12: tmp3 4246 * r13: tmp4 4247 * r14: tmp5 4248 * r15: tmp6 4249 * r16: tmp7 4250 * 4251 */ 4252 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, 4253 Register z, Register tmp0, 4254 Register tmp1, Register tmp2, Register tmp3, Register tmp4, 4255 Register tmp5, Register tmp6, Register product_hi) { 4256 4257 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, product_hi); 4258 4259 const Register idx = tmp1; 4260 const Register kdx = tmp2; 4261 const Register xstart = tmp3; 4262 4263 const Register y_idx = tmp4; 4264 const Register carry = tmp5; 4265 const Register product = xlen; 4266 const Register x_xstart = tmp0; 4267 4268 // First Loop. 4269 // 4270 // final static long LONG_MASK = 0xffffffffL; 4271 // int xstart = xlen - 1; 4272 // int ystart = ylen - 1; 4273 // long carry = 0; 4274 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 4275 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 4276 // z[kdx] = (int)product; 4277 // carry = product >>> 32; 4278 // } 4279 // z[xstart] = (int)carry; 4280 // 4281 4282 movw(idx, ylen); // idx = ylen; 4283 addw(kdx, xlen, ylen); // kdx = xlen+ylen; 4284 mov(carry, zr); // carry = 0; 4285 4286 Label L_done; 4287 4288 movw(xstart, xlen); 4289 subsw(xstart, xstart, 1); 4290 br(Assembler::MI, L_done); 4291 4292 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 4293 4294 Label L_second_loop; 4295 cbzw(kdx, L_second_loop); 4296 4297 Label L_carry; 4298 subw(kdx, kdx, 1); 4299 cbzw(kdx, L_carry); 4300 4301 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 4302 lsr(carry, carry, 32); 4303 subw(kdx, kdx, 1); 4304 4305 bind(L_carry); 4306 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 4307 4308 // Second and third (nested) loops. 4309 // 4310 // for (int i = xstart-1; i >= 0; i--) { // Second loop 4311 // carry = 0; 4312 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 4313 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 4314 // (z[k] & LONG_MASK) + carry; 4315 // z[k] = (int)product; 4316 // carry = product >>> 32; 4317 // } 4318 // z[i] = (int)carry; 4319 // } 4320 // 4321 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi 4322 4323 const Register jdx = tmp1; 4324 4325 bind(L_second_loop); 4326 mov(carry, zr); // carry = 0; 4327 movw(jdx, ylen); // j = ystart+1 4328 4329 subsw(xstart, xstart, 1); // i = xstart-1; 4330 br(Assembler::MI, L_done); 4331 4332 str(z, Address(pre(sp, -4 * wordSize))); 4333 4334 Label L_last_x; 4335 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j 4336 subsw(xstart, xstart, 1); // i = xstart-1; 4337 br(Assembler::MI, L_last_x); 4338 4339 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt))); 4340 ldr(product_hi, Address(rscratch1)); 4341 ror(product_hi, product_hi, 32); // convert big-endian to little-endian 4342 4343 Label L_third_loop_prologue; 4344 bind(L_third_loop_prologue); 4345 4346 str(ylen, Address(sp, wordSize)); 4347 stp(x, xstart, Address(sp, 2 * wordSize)); 4348 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product, 4349 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi); 4350 ldp(z, ylen, Address(post(sp, 2 * wordSize))); 4351 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen 4352 4353 addw(tmp3, xlen, 1); 4354 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 4355 subsw(tmp3, tmp3, 1); 4356 br(Assembler::MI, L_done); 4357 4358 lsr(carry, carry, 32); 4359 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 4360 b(L_second_loop); 4361 4362 // Next infrequent code is moved outside loops. 4363 bind(L_last_x); 4364 ldrw(product_hi, Address(x, 0)); 4365 b(L_third_loop_prologue); 4366 4367 bind(L_done); 4368 } 4369 4370 // Code for BigInteger::mulAdd intrinsic 4371 // out = r0 4372 // in = r1 4373 // offset = r2 (already out.length-offset) 4374 // len = r3 4375 // k = r4 4376 // 4377 // pseudo code from java implementation: 4378 // carry = 0; 4379 // offset = out.length-offset - 1; 4380 // for (int j=len-1; j >= 0; j--) { 4381 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry; 4382 // out[offset--] = (int)product; 4383 // carry = product >>> 32; 4384 // } 4385 // return (int)carry; 4386 void MacroAssembler::mul_add(Register out, Register in, Register offset, 4387 Register len, Register k) { 4388 Label LOOP, END; 4389 // pre-loop 4390 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches 4391 csel(out, zr, out, Assembler::EQ); 4392 br(Assembler::EQ, END); 4393 add(in, in, len, LSL, 2); // in[j+1] address 4394 add(offset, out, offset, LSL, 2); // out[offset + 1] address 4395 mov(out, zr); // used to keep carry now 4396 BIND(LOOP); 4397 ldrw(rscratch1, Address(pre(in, -4))); 4398 madd(rscratch1, rscratch1, k, out); 4399 ldrw(rscratch2, Address(pre(offset, -4))); 4400 add(rscratch1, rscratch1, rscratch2); 4401 strw(rscratch1, Address(offset)); 4402 lsr(out, rscratch1, 32); 4403 subs(len, len, 1); 4404 br(Assembler::NE, LOOP); 4405 BIND(END); 4406 } 4407 4408 /** 4409 * Emits code to update CRC-32 with a byte value according to constants in table 4410 * 4411 * @param [in,out]crc Register containing the crc. 4412 * @param [in]val Register containing the byte to fold into the CRC. 4413 * @param [in]table Register containing the table of crc constants. 4414 * 4415 * uint32_t crc; 4416 * val = crc_table[(val ^ crc) & 0xFF]; 4417 * crc = val ^ (crc >> 8); 4418 * 4419 */ 4420 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 4421 eor(val, val, crc); 4422 andr(val, val, 0xff); 4423 ldrw(val, Address(table, val, Address::lsl(2))); 4424 eor(crc, val, crc, Assembler::LSR, 8); 4425 } 4426 4427 /** 4428 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3 4429 * 4430 * @param [in,out]crc Register containing the crc. 4431 * @param [in]v Register containing the 32-bit to fold into the CRC. 4432 * @param [in]table0 Register containing table 0 of crc constants. 4433 * @param [in]table1 Register containing table 1 of crc constants. 4434 * @param [in]table2 Register containing table 2 of crc constants. 4435 * @param [in]table3 Register containing table 3 of crc constants. 4436 * 4437 * uint32_t crc; 4438 * v = crc ^ v 4439 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24] 4440 * 4441 */ 4442 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp, 4443 Register table0, Register table1, Register table2, Register table3, 4444 bool upper) { 4445 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0); 4446 uxtb(tmp, v); 4447 ldrw(crc, Address(table3, tmp, Address::lsl(2))); 4448 ubfx(tmp, v, 8, 8); 4449 ldrw(tmp, Address(table2, tmp, Address::lsl(2))); 4450 eor(crc, crc, tmp); 4451 ubfx(tmp, v, 16, 8); 4452 ldrw(tmp, Address(table1, tmp, Address::lsl(2))); 4453 eor(crc, crc, tmp); 4454 ubfx(tmp, v, 24, 8); 4455 ldrw(tmp, Address(table0, tmp, Address::lsl(2))); 4456 eor(crc, crc, tmp); 4457 } 4458 4459 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf, 4460 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) { 4461 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit; 4462 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2); 4463 4464 subs(tmp0, len, 384); 4465 mvnw(crc, crc); 4466 br(Assembler::GE, CRC_by128_pre); 4467 BIND(CRC_less128); 4468 subs(len, len, 32); 4469 br(Assembler::GE, CRC_by32_loop); 4470 BIND(CRC_less32); 4471 adds(len, len, 32 - 4); 4472 br(Assembler::GE, CRC_by4_loop); 4473 adds(len, len, 4); 4474 br(Assembler::GT, CRC_by1_loop); 4475 b(L_exit); 4476 4477 BIND(CRC_by32_loop); 4478 ldp(tmp0, tmp1, Address(buf)); 4479 crc32x(crc, crc, tmp0); 4480 ldp(tmp2, tmp3, Address(buf, 16)); 4481 crc32x(crc, crc, tmp1); 4482 add(buf, buf, 32); 4483 crc32x(crc, crc, tmp2); 4484 subs(len, len, 32); 4485 crc32x(crc, crc, tmp3); 4486 br(Assembler::GE, CRC_by32_loop); 4487 cmn(len, (u1)32); 4488 br(Assembler::NE, CRC_less32); 4489 b(L_exit); 4490 4491 BIND(CRC_by4_loop); 4492 ldrw(tmp0, Address(post(buf, 4))); 4493 subs(len, len, 4); 4494 crc32w(crc, crc, tmp0); 4495 br(Assembler::GE, CRC_by4_loop); 4496 adds(len, len, 4); 4497 br(Assembler::LE, L_exit); 4498 BIND(CRC_by1_loop); 4499 ldrb(tmp0, Address(post(buf, 1))); 4500 subs(len, len, 1); 4501 crc32b(crc, crc, tmp0); 4502 br(Assembler::GT, CRC_by1_loop); 4503 b(L_exit); 4504 4505 BIND(CRC_by128_pre); 4506 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2, 4507 4*256*sizeof(juint) + 8*sizeof(juint)); 4508 mov(crc, 0); 4509 crc32x(crc, crc, tmp0); 4510 crc32x(crc, crc, tmp1); 4511 4512 cbnz(len, CRC_less128); 4513 4514 BIND(L_exit); 4515 mvnw(crc, crc); 4516 } 4517 4518 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf, 4519 Register len, Register tmp0, Register tmp1, Register tmp2, 4520 Register tmp3) { 4521 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit; 4522 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3); 4523 4524 mvnw(crc, crc); 4525 4526 subs(len, len, 128); 4527 br(Assembler::GE, CRC_by64_pre); 4528 BIND(CRC_less64); 4529 adds(len, len, 128-32); 4530 br(Assembler::GE, CRC_by32_loop); 4531 BIND(CRC_less32); 4532 adds(len, len, 32-4); 4533 br(Assembler::GE, CRC_by4_loop); 4534 adds(len, len, 4); 4535 br(Assembler::GT, CRC_by1_loop); 4536 b(L_exit); 4537 4538 BIND(CRC_by32_loop); 4539 ldp(tmp0, tmp1, Address(post(buf, 16))); 4540 subs(len, len, 32); 4541 crc32x(crc, crc, tmp0); 4542 ldr(tmp2, Address(post(buf, 8))); 4543 crc32x(crc, crc, tmp1); 4544 ldr(tmp3, Address(post(buf, 8))); 4545 crc32x(crc, crc, tmp2); 4546 crc32x(crc, crc, tmp3); 4547 br(Assembler::GE, CRC_by32_loop); 4548 cmn(len, (u1)32); 4549 br(Assembler::NE, CRC_less32); 4550 b(L_exit); 4551 4552 BIND(CRC_by4_loop); 4553 ldrw(tmp0, Address(post(buf, 4))); 4554 subs(len, len, 4); 4555 crc32w(crc, crc, tmp0); 4556 br(Assembler::GE, CRC_by4_loop); 4557 adds(len, len, 4); 4558 br(Assembler::LE, L_exit); 4559 BIND(CRC_by1_loop); 4560 ldrb(tmp0, Address(post(buf, 1))); 4561 subs(len, len, 1); 4562 crc32b(crc, crc, tmp0); 4563 br(Assembler::GT, CRC_by1_loop); 4564 b(L_exit); 4565 4566 BIND(CRC_by64_pre); 4567 sub(buf, buf, 8); 4568 ldp(tmp0, tmp1, Address(buf, 8)); 4569 crc32x(crc, crc, tmp0); 4570 ldr(tmp2, Address(buf, 24)); 4571 crc32x(crc, crc, tmp1); 4572 ldr(tmp3, Address(buf, 32)); 4573 crc32x(crc, crc, tmp2); 4574 ldr(tmp0, Address(buf, 40)); 4575 crc32x(crc, crc, tmp3); 4576 ldr(tmp1, Address(buf, 48)); 4577 crc32x(crc, crc, tmp0); 4578 ldr(tmp2, Address(buf, 56)); 4579 crc32x(crc, crc, tmp1); 4580 ldr(tmp3, Address(pre(buf, 64))); 4581 4582 b(CRC_by64_loop); 4583 4584 align(CodeEntryAlignment); 4585 BIND(CRC_by64_loop); 4586 subs(len, len, 64); 4587 crc32x(crc, crc, tmp2); 4588 ldr(tmp0, Address(buf, 8)); 4589 crc32x(crc, crc, tmp3); 4590 ldr(tmp1, Address(buf, 16)); 4591 crc32x(crc, crc, tmp0); 4592 ldr(tmp2, Address(buf, 24)); 4593 crc32x(crc, crc, tmp1); 4594 ldr(tmp3, Address(buf, 32)); 4595 crc32x(crc, crc, tmp2); 4596 ldr(tmp0, Address(buf, 40)); 4597 crc32x(crc, crc, tmp3); 4598 ldr(tmp1, Address(buf, 48)); 4599 crc32x(crc, crc, tmp0); 4600 ldr(tmp2, Address(buf, 56)); 4601 crc32x(crc, crc, tmp1); 4602 ldr(tmp3, Address(pre(buf, 64))); 4603 br(Assembler::GE, CRC_by64_loop); 4604 4605 // post-loop 4606 crc32x(crc, crc, tmp2); 4607 crc32x(crc, crc, tmp3); 4608 4609 sub(len, len, 64); 4610 add(buf, buf, 8); 4611 cmn(len, (u1)128); 4612 br(Assembler::NE, CRC_less64); 4613 BIND(L_exit); 4614 mvnw(crc, crc); 4615 } 4616 4617 /** 4618 * @param crc register containing existing CRC (32-bit) 4619 * @param buf register pointing to input byte buffer (byte*) 4620 * @param len register containing number of bytes 4621 * @param table register that will contain address of CRC table 4622 * @param tmp scratch register 4623 */ 4624 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, 4625 Register table0, Register table1, Register table2, Register table3, 4626 Register tmp, Register tmp2, Register tmp3) { 4627 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit; 4628 4629 if (UseCryptoPmullForCRC32) { 4630 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3); 4631 return; 4632 } 4633 4634 if (UseCRC32) { 4635 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3); 4636 return; 4637 } 4638 4639 mvnw(crc, crc); 4640 4641 { 4642 uint64_t offset; 4643 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset); 4644 add(table0, table0, offset); 4645 } 4646 add(table1, table0, 1*256*sizeof(juint)); 4647 add(table2, table0, 2*256*sizeof(juint)); 4648 add(table3, table0, 3*256*sizeof(juint)); 4649 4650 { // Neon code start 4651 cmp(len, (u1)64); 4652 br(Assembler::LT, L_by16); 4653 eor(v16, T16B, v16, v16); 4654 4655 Label L_fold; 4656 4657 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants 4658 4659 ld1(v0, v1, T2D, post(buf, 32)); 4660 ld1r(v4, T2D, post(tmp, 8)); 4661 ld1r(v5, T2D, post(tmp, 8)); 4662 ld1r(v6, T2D, post(tmp, 8)); 4663 ld1r(v7, T2D, post(tmp, 8)); 4664 mov(v16, S, 0, crc); 4665 4666 eor(v0, T16B, v0, v16); 4667 sub(len, len, 64); 4668 4669 BIND(L_fold); 4670 pmull(v22, T8H, v0, v5, T8B); 4671 pmull(v20, T8H, v0, v7, T8B); 4672 pmull(v23, T8H, v0, v4, T8B); 4673 pmull(v21, T8H, v0, v6, T8B); 4674 4675 pmull2(v18, T8H, v0, v5, T16B); 4676 pmull2(v16, T8H, v0, v7, T16B); 4677 pmull2(v19, T8H, v0, v4, T16B); 4678 pmull2(v17, T8H, v0, v6, T16B); 4679 4680 uzp1(v24, T8H, v20, v22); 4681 uzp2(v25, T8H, v20, v22); 4682 eor(v20, T16B, v24, v25); 4683 4684 uzp1(v26, T8H, v16, v18); 4685 uzp2(v27, T8H, v16, v18); 4686 eor(v16, T16B, v26, v27); 4687 4688 ushll2(v22, T4S, v20, T8H, 8); 4689 ushll(v20, T4S, v20, T4H, 8); 4690 4691 ushll2(v18, T4S, v16, T8H, 8); 4692 ushll(v16, T4S, v16, T4H, 8); 4693 4694 eor(v22, T16B, v23, v22); 4695 eor(v18, T16B, v19, v18); 4696 eor(v20, T16B, v21, v20); 4697 eor(v16, T16B, v17, v16); 4698 4699 uzp1(v17, T2D, v16, v20); 4700 uzp2(v21, T2D, v16, v20); 4701 eor(v17, T16B, v17, v21); 4702 4703 ushll2(v20, T2D, v17, T4S, 16); 4704 ushll(v16, T2D, v17, T2S, 16); 4705 4706 eor(v20, T16B, v20, v22); 4707 eor(v16, T16B, v16, v18); 4708 4709 uzp1(v17, T2D, v20, v16); 4710 uzp2(v21, T2D, v20, v16); 4711 eor(v28, T16B, v17, v21); 4712 4713 pmull(v22, T8H, v1, v5, T8B); 4714 pmull(v20, T8H, v1, v7, T8B); 4715 pmull(v23, T8H, v1, v4, T8B); 4716 pmull(v21, T8H, v1, v6, T8B); 4717 4718 pmull2(v18, T8H, v1, v5, T16B); 4719 pmull2(v16, T8H, v1, v7, T16B); 4720 pmull2(v19, T8H, v1, v4, T16B); 4721 pmull2(v17, T8H, v1, v6, T16B); 4722 4723 ld1(v0, v1, T2D, post(buf, 32)); 4724 4725 uzp1(v24, T8H, v20, v22); 4726 uzp2(v25, T8H, v20, v22); 4727 eor(v20, T16B, v24, v25); 4728 4729 uzp1(v26, T8H, v16, v18); 4730 uzp2(v27, T8H, v16, v18); 4731 eor(v16, T16B, v26, v27); 4732 4733 ushll2(v22, T4S, v20, T8H, 8); 4734 ushll(v20, T4S, v20, T4H, 8); 4735 4736 ushll2(v18, T4S, v16, T8H, 8); 4737 ushll(v16, T4S, v16, T4H, 8); 4738 4739 eor(v22, T16B, v23, v22); 4740 eor(v18, T16B, v19, v18); 4741 eor(v20, T16B, v21, v20); 4742 eor(v16, T16B, v17, v16); 4743 4744 uzp1(v17, T2D, v16, v20); 4745 uzp2(v21, T2D, v16, v20); 4746 eor(v16, T16B, v17, v21); 4747 4748 ushll2(v20, T2D, v16, T4S, 16); 4749 ushll(v16, T2D, v16, T2S, 16); 4750 4751 eor(v20, T16B, v22, v20); 4752 eor(v16, T16B, v16, v18); 4753 4754 uzp1(v17, T2D, v20, v16); 4755 uzp2(v21, T2D, v20, v16); 4756 eor(v20, T16B, v17, v21); 4757 4758 shl(v16, T2D, v28, 1); 4759 shl(v17, T2D, v20, 1); 4760 4761 eor(v0, T16B, v0, v16); 4762 eor(v1, T16B, v1, v17); 4763 4764 subs(len, len, 32); 4765 br(Assembler::GE, L_fold); 4766 4767 mov(crc, 0); 4768 mov(tmp, v0, D, 0); 4769 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 4770 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 4771 mov(tmp, v0, D, 1); 4772 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 4773 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 4774 mov(tmp, v1, D, 0); 4775 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 4776 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 4777 mov(tmp, v1, D, 1); 4778 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 4779 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 4780 4781 add(len, len, 32); 4782 } // Neon code end 4783 4784 BIND(L_by16); 4785 subs(len, len, 16); 4786 br(Assembler::GE, L_by16_loop); 4787 adds(len, len, 16-4); 4788 br(Assembler::GE, L_by4_loop); 4789 adds(len, len, 4); 4790 br(Assembler::GT, L_by1_loop); 4791 b(L_exit); 4792 4793 BIND(L_by4_loop); 4794 ldrw(tmp, Address(post(buf, 4))); 4795 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3); 4796 subs(len, len, 4); 4797 br(Assembler::GE, L_by4_loop); 4798 adds(len, len, 4); 4799 br(Assembler::LE, L_exit); 4800 BIND(L_by1_loop); 4801 subs(len, len, 1); 4802 ldrb(tmp, Address(post(buf, 1))); 4803 update_byte_crc32(crc, tmp, table0); 4804 br(Assembler::GT, L_by1_loop); 4805 b(L_exit); 4806 4807 align(CodeEntryAlignment); 4808 BIND(L_by16_loop); 4809 subs(len, len, 16); 4810 ldp(tmp, tmp3, Address(post(buf, 16))); 4811 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 4812 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 4813 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false); 4814 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true); 4815 br(Assembler::GE, L_by16_loop); 4816 adds(len, len, 16-4); 4817 br(Assembler::GE, L_by4_loop); 4818 adds(len, len, 4); 4819 br(Assembler::GT, L_by1_loop); 4820 BIND(L_exit); 4821 mvnw(crc, crc); 4822 } 4823 4824 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf, 4825 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) { 4826 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit; 4827 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2); 4828 4829 subs(tmp0, len, 384); 4830 br(Assembler::GE, CRC_by128_pre); 4831 BIND(CRC_less128); 4832 subs(len, len, 32); 4833 br(Assembler::GE, CRC_by32_loop); 4834 BIND(CRC_less32); 4835 adds(len, len, 32 - 4); 4836 br(Assembler::GE, CRC_by4_loop); 4837 adds(len, len, 4); 4838 br(Assembler::GT, CRC_by1_loop); 4839 b(L_exit); 4840 4841 BIND(CRC_by32_loop); 4842 ldp(tmp0, tmp1, Address(buf)); 4843 crc32cx(crc, crc, tmp0); 4844 ldr(tmp2, Address(buf, 16)); 4845 crc32cx(crc, crc, tmp1); 4846 ldr(tmp3, Address(buf, 24)); 4847 crc32cx(crc, crc, tmp2); 4848 add(buf, buf, 32); 4849 subs(len, len, 32); 4850 crc32cx(crc, crc, tmp3); 4851 br(Assembler::GE, CRC_by32_loop); 4852 cmn(len, (u1)32); 4853 br(Assembler::NE, CRC_less32); 4854 b(L_exit); 4855 4856 BIND(CRC_by4_loop); 4857 ldrw(tmp0, Address(post(buf, 4))); 4858 subs(len, len, 4); 4859 crc32cw(crc, crc, tmp0); 4860 br(Assembler::GE, CRC_by4_loop); 4861 adds(len, len, 4); 4862 br(Assembler::LE, L_exit); 4863 BIND(CRC_by1_loop); 4864 ldrb(tmp0, Address(post(buf, 1))); 4865 subs(len, len, 1); 4866 crc32cb(crc, crc, tmp0); 4867 br(Assembler::GT, CRC_by1_loop); 4868 b(L_exit); 4869 4870 BIND(CRC_by128_pre); 4871 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2, 4872 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50); 4873 mov(crc, 0); 4874 crc32cx(crc, crc, tmp0); 4875 crc32cx(crc, crc, tmp1); 4876 4877 cbnz(len, CRC_less128); 4878 4879 BIND(L_exit); 4880 } 4881 4882 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf, 4883 Register len, Register tmp0, Register tmp1, Register tmp2, 4884 Register tmp3) { 4885 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit; 4886 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3); 4887 4888 subs(len, len, 128); 4889 br(Assembler::GE, CRC_by64_pre); 4890 BIND(CRC_less64); 4891 adds(len, len, 128-32); 4892 br(Assembler::GE, CRC_by32_loop); 4893 BIND(CRC_less32); 4894 adds(len, len, 32-4); 4895 br(Assembler::GE, CRC_by4_loop); 4896 adds(len, len, 4); 4897 br(Assembler::GT, CRC_by1_loop); 4898 b(L_exit); 4899 4900 BIND(CRC_by32_loop); 4901 ldp(tmp0, tmp1, Address(post(buf, 16))); 4902 subs(len, len, 32); 4903 crc32cx(crc, crc, tmp0); 4904 ldr(tmp2, Address(post(buf, 8))); 4905 crc32cx(crc, crc, tmp1); 4906 ldr(tmp3, Address(post(buf, 8))); 4907 crc32cx(crc, crc, tmp2); 4908 crc32cx(crc, crc, tmp3); 4909 br(Assembler::GE, CRC_by32_loop); 4910 cmn(len, (u1)32); 4911 br(Assembler::NE, CRC_less32); 4912 b(L_exit); 4913 4914 BIND(CRC_by4_loop); 4915 ldrw(tmp0, Address(post(buf, 4))); 4916 subs(len, len, 4); 4917 crc32cw(crc, crc, tmp0); 4918 br(Assembler::GE, CRC_by4_loop); 4919 adds(len, len, 4); 4920 br(Assembler::LE, L_exit); 4921 BIND(CRC_by1_loop); 4922 ldrb(tmp0, Address(post(buf, 1))); 4923 subs(len, len, 1); 4924 crc32cb(crc, crc, tmp0); 4925 br(Assembler::GT, CRC_by1_loop); 4926 b(L_exit); 4927 4928 BIND(CRC_by64_pre); 4929 sub(buf, buf, 8); 4930 ldp(tmp0, tmp1, Address(buf, 8)); 4931 crc32cx(crc, crc, tmp0); 4932 ldr(tmp2, Address(buf, 24)); 4933 crc32cx(crc, crc, tmp1); 4934 ldr(tmp3, Address(buf, 32)); 4935 crc32cx(crc, crc, tmp2); 4936 ldr(tmp0, Address(buf, 40)); 4937 crc32cx(crc, crc, tmp3); 4938 ldr(tmp1, Address(buf, 48)); 4939 crc32cx(crc, crc, tmp0); 4940 ldr(tmp2, Address(buf, 56)); 4941 crc32cx(crc, crc, tmp1); 4942 ldr(tmp3, Address(pre(buf, 64))); 4943 4944 b(CRC_by64_loop); 4945 4946 align(CodeEntryAlignment); 4947 BIND(CRC_by64_loop); 4948 subs(len, len, 64); 4949 crc32cx(crc, crc, tmp2); 4950 ldr(tmp0, Address(buf, 8)); 4951 crc32cx(crc, crc, tmp3); 4952 ldr(tmp1, Address(buf, 16)); 4953 crc32cx(crc, crc, tmp0); 4954 ldr(tmp2, Address(buf, 24)); 4955 crc32cx(crc, crc, tmp1); 4956 ldr(tmp3, Address(buf, 32)); 4957 crc32cx(crc, crc, tmp2); 4958 ldr(tmp0, Address(buf, 40)); 4959 crc32cx(crc, crc, tmp3); 4960 ldr(tmp1, Address(buf, 48)); 4961 crc32cx(crc, crc, tmp0); 4962 ldr(tmp2, Address(buf, 56)); 4963 crc32cx(crc, crc, tmp1); 4964 ldr(tmp3, Address(pre(buf, 64))); 4965 br(Assembler::GE, CRC_by64_loop); 4966 4967 // post-loop 4968 crc32cx(crc, crc, tmp2); 4969 crc32cx(crc, crc, tmp3); 4970 4971 sub(len, len, 64); 4972 add(buf, buf, 8); 4973 cmn(len, (u1)128); 4974 br(Assembler::NE, CRC_less64); 4975 BIND(L_exit); 4976 } 4977 4978 /** 4979 * @param crc register containing existing CRC (32-bit) 4980 * @param buf register pointing to input byte buffer (byte*) 4981 * @param len register containing number of bytes 4982 * @param table register that will contain address of CRC table 4983 * @param tmp scratch register 4984 */ 4985 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len, 4986 Register table0, Register table1, Register table2, Register table3, 4987 Register tmp, Register tmp2, Register tmp3) { 4988 if (UseCryptoPmullForCRC32) { 4989 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3); 4990 } else { 4991 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3); 4992 } 4993 } 4994 4995 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf, 4996 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) { 4997 Label CRC_by128_loop; 4998 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2); 4999 5000 sub(len, len, 256); 5001 Register table = tmp0; 5002 { 5003 uint64_t offset; 5004 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset); 5005 add(table, table, offset); 5006 } 5007 add(table, table, table_offset); 5008 5009 // Registers v0..v7 are used as data registers. 5010 // Registers v16..v31 are used as tmp registers. 5011 sub(buf, buf, 0x10); 5012 ldrq(v0, Address(buf, 0x10)); 5013 ldrq(v1, Address(buf, 0x20)); 5014 ldrq(v2, Address(buf, 0x30)); 5015 ldrq(v3, Address(buf, 0x40)); 5016 ldrq(v4, Address(buf, 0x50)); 5017 ldrq(v5, Address(buf, 0x60)); 5018 ldrq(v6, Address(buf, 0x70)); 5019 ldrq(v7, Address(pre(buf, 0x80))); 5020 5021 movi(v31, T4S, 0); 5022 mov(v31, S, 0, crc); 5023 eor(v0, T16B, v0, v31); 5024 5025 // Register v16 contains constants from the crc table. 5026 ldrq(v16, Address(table)); 5027 b(CRC_by128_loop); 5028 5029 align(OptoLoopAlignment); 5030 BIND(CRC_by128_loop); 5031 pmull (v17, T1Q, v0, v16, T1D); 5032 pmull2(v18, T1Q, v0, v16, T2D); 5033 ldrq(v0, Address(buf, 0x10)); 5034 eor3(v0, T16B, v17, v18, v0); 5035 5036 pmull (v19, T1Q, v1, v16, T1D); 5037 pmull2(v20, T1Q, v1, v16, T2D); 5038 ldrq(v1, Address(buf, 0x20)); 5039 eor3(v1, T16B, v19, v20, v1); 5040 5041 pmull (v21, T1Q, v2, v16, T1D); 5042 pmull2(v22, T1Q, v2, v16, T2D); 5043 ldrq(v2, Address(buf, 0x30)); 5044 eor3(v2, T16B, v21, v22, v2); 5045 5046 pmull (v23, T1Q, v3, v16, T1D); 5047 pmull2(v24, T1Q, v3, v16, T2D); 5048 ldrq(v3, Address(buf, 0x40)); 5049 eor3(v3, T16B, v23, v24, v3); 5050 5051 pmull (v25, T1Q, v4, v16, T1D); 5052 pmull2(v26, T1Q, v4, v16, T2D); 5053 ldrq(v4, Address(buf, 0x50)); 5054 eor3(v4, T16B, v25, v26, v4); 5055 5056 pmull (v27, T1Q, v5, v16, T1D); 5057 pmull2(v28, T1Q, v5, v16, T2D); 5058 ldrq(v5, Address(buf, 0x60)); 5059 eor3(v5, T16B, v27, v28, v5); 5060 5061 pmull (v29, T1Q, v6, v16, T1D); 5062 pmull2(v30, T1Q, v6, v16, T2D); 5063 ldrq(v6, Address(buf, 0x70)); 5064 eor3(v6, T16B, v29, v30, v6); 5065 5066 // Reuse registers v23, v24. 5067 // Using them won't block the first instruction of the next iteration. 5068 pmull (v23, T1Q, v7, v16, T1D); 5069 pmull2(v24, T1Q, v7, v16, T2D); 5070 ldrq(v7, Address(pre(buf, 0x80))); 5071 eor3(v7, T16B, v23, v24, v7); 5072 5073 subs(len, len, 0x80); 5074 br(Assembler::GE, CRC_by128_loop); 5075 5076 // fold into 512 bits 5077 // Use v31 for constants because v16 can be still in use. 5078 ldrq(v31, Address(table, 0x10)); 5079 5080 pmull (v17, T1Q, v0, v31, T1D); 5081 pmull2(v18, T1Q, v0, v31, T2D); 5082 eor3(v0, T16B, v17, v18, v4); 5083 5084 pmull (v19, T1Q, v1, v31, T1D); 5085 pmull2(v20, T1Q, v1, v31, T2D); 5086 eor3(v1, T16B, v19, v20, v5); 5087 5088 pmull (v21, T1Q, v2, v31, T1D); 5089 pmull2(v22, T1Q, v2, v31, T2D); 5090 eor3(v2, T16B, v21, v22, v6); 5091 5092 pmull (v23, T1Q, v3, v31, T1D); 5093 pmull2(v24, T1Q, v3, v31, T2D); 5094 eor3(v3, T16B, v23, v24, v7); 5095 5096 // fold into 128 bits 5097 // Use v17 for constants because v31 can be still in use. 5098 ldrq(v17, Address(table, 0x20)); 5099 pmull (v25, T1Q, v0, v17, T1D); 5100 pmull2(v26, T1Q, v0, v17, T2D); 5101 eor3(v3, T16B, v3, v25, v26); 5102 5103 // Use v18 for constants because v17 can be still in use. 5104 ldrq(v18, Address(table, 0x30)); 5105 pmull (v27, T1Q, v1, v18, T1D); 5106 pmull2(v28, T1Q, v1, v18, T2D); 5107 eor3(v3, T16B, v3, v27, v28); 5108 5109 // Use v19 for constants because v18 can be still in use. 5110 ldrq(v19, Address(table, 0x40)); 5111 pmull (v29, T1Q, v2, v19, T1D); 5112 pmull2(v30, T1Q, v2, v19, T2D); 5113 eor3(v0, T16B, v3, v29, v30); 5114 5115 add(len, len, 0x80); 5116 add(buf, buf, 0x10); 5117 5118 mov(tmp0, v0, D, 0); 5119 mov(tmp1, v0, D, 1); 5120 } 5121 5122 void MacroAssembler::addptr(const Address &dst, int32_t src) { 5123 Address adr; 5124 switch(dst.getMode()) { 5125 case Address::base_plus_offset: 5126 // This is the expected mode, although we allow all the other 5127 // forms below. 5128 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord); 5129 break; 5130 default: 5131 lea(rscratch2, dst); 5132 adr = Address(rscratch2); 5133 break; 5134 } 5135 ldr(rscratch1, adr); 5136 add(rscratch1, rscratch1, src); 5137 str(rscratch1, adr); 5138 } 5139 5140 void MacroAssembler::cmpptr(Register src1, Address src2) { 5141 uint64_t offset; 5142 adrp(rscratch1, src2, offset); 5143 ldr(rscratch1, Address(rscratch1, offset)); 5144 cmp(src1, rscratch1); 5145 } 5146 5147 void MacroAssembler::cmpoop(Register obj1, Register obj2) { 5148 cmp(obj1, obj2); 5149 } 5150 5151 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) { 5152 load_method_holder(rresult, rmethod); 5153 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset())); 5154 } 5155 5156 void MacroAssembler::load_method_holder(Register holder, Register method) { 5157 ldr(holder, Address(method, Method::const_offset())); // ConstMethod* 5158 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool* 5159 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass* 5160 } 5161 5162 void MacroAssembler::load_metadata(Register dst, Register src) { 5163 if (UseCompactObjectHeaders) { 5164 load_narrow_klass_compact(dst, src); 5165 } else if (UseCompressedClassPointers) { 5166 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes())); 5167 } else { 5168 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 5169 } 5170 } 5171 5172 // Loads the obj's Klass* into dst. 5173 // Preserves all registers (incl src, rscratch1 and rscratch2). 5174 // Input: 5175 // src - the oop we want to load the klass from. 5176 // dst - output narrow klass. 5177 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) { 5178 assert(UseCompactObjectHeaders, "expects UseCompactObjectHeaders"); 5179 ldr(dst, Address(src, oopDesc::mark_offset_in_bytes())); 5180 lsr(dst, dst, markWord::klass_shift); 5181 } 5182 5183 void MacroAssembler::load_klass(Register dst, Register src) { 5184 if (UseCompactObjectHeaders) { 5185 load_narrow_klass_compact(dst, src); 5186 decode_klass_not_null(dst); 5187 } else if (UseCompressedClassPointers) { 5188 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes())); 5189 decode_klass_not_null(dst); 5190 } else { 5191 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 5192 } 5193 } 5194 5195 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) { 5196 if (RestoreMXCSROnJNICalls) { 5197 Label OK; 5198 get_fpcr(tmp1); 5199 mov(tmp2, tmp1); 5200 // Set FPCR to the state we need. We do want Round to Nearest. We 5201 // don't want non-IEEE rounding modes or floating-point traps. 5202 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode 5203 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12) 5204 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ 5205 eor(tmp2, tmp1, tmp2); 5206 cbz(tmp2, OK); // Only reset FPCR if it's wrong 5207 set_fpcr(tmp1); 5208 bind(OK); 5209 } 5210 } 5211 5212 // ((OopHandle)result).resolve(); 5213 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) { 5214 // OopHandle::resolve is an indirection. 5215 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2); 5216 } 5217 5218 // ((WeakHandle)result).resolve(); 5219 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) { 5220 assert_different_registers(result, tmp1, tmp2); 5221 Label resolved; 5222 5223 // A null weak handle resolves to null. 5224 cbz(result, resolved); 5225 5226 // Only 64 bit platforms support GCs that require a tmp register 5227 // WeakHandle::resolve is an indirection like jweak. 5228 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, 5229 result, Address(result), tmp1, tmp2); 5230 bind(resolved); 5231 } 5232 5233 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) { 5234 const int mirror_offset = in_bytes(Klass::java_mirror_offset()); 5235 ldr(dst, Address(rmethod, Method::const_offset())); 5236 ldr(dst, Address(dst, ConstMethod::constants_offset())); 5237 ldr(dst, Address(dst, ConstantPool::pool_holder_offset())); 5238 ldr(dst, Address(dst, mirror_offset)); 5239 resolve_oop_handle(dst, tmp1, tmp2); 5240 } 5241 5242 void MacroAssembler::cmp_klass(Register obj, Register klass, Register tmp) { 5243 assert_different_registers(obj, klass, tmp); 5244 if (UseCompressedClassPointers) { 5245 if (UseCompactObjectHeaders) { 5246 load_narrow_klass_compact(tmp, obj); 5247 } else { 5248 ldrw(tmp, Address(obj, oopDesc::klass_offset_in_bytes())); 5249 } 5250 if (CompressedKlassPointers::base() == nullptr) { 5251 cmp(klass, tmp, LSL, CompressedKlassPointers::shift()); 5252 return; 5253 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0 5254 && CompressedKlassPointers::shift() == 0) { 5255 // Only the bottom 32 bits matter 5256 cmpw(klass, tmp); 5257 return; 5258 } 5259 decode_klass_not_null(tmp); 5260 } else { 5261 ldr(tmp, Address(obj, oopDesc::klass_offset_in_bytes())); 5262 } 5263 cmp(klass, tmp); 5264 } 5265 5266 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) { 5267 if (UseCompactObjectHeaders) { 5268 load_narrow_klass_compact(tmp1, obj1); 5269 load_narrow_klass_compact(tmp2, obj2); 5270 cmpw(tmp1, tmp2); 5271 } else if (UseCompressedClassPointers) { 5272 ldrw(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes())); 5273 ldrw(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes())); 5274 cmpw(tmp1, tmp2); 5275 } else { 5276 ldr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes())); 5277 ldr(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes())); 5278 cmp(tmp1, tmp2); 5279 } 5280 } 5281 5282 void MacroAssembler::load_prototype_header(Register dst, Register src) { 5283 load_klass(dst, src); 5284 ldr(dst, Address(dst, Klass::prototype_header_offset())); 5285 } 5286 5287 void MacroAssembler::store_klass(Register dst, Register src) { 5288 // FIXME: Should this be a store release? concurrent gcs assumes 5289 // klass length is valid if klass field is not null. 5290 assert(!UseCompactObjectHeaders, "not with compact headers"); 5291 if (UseCompressedClassPointers) { 5292 encode_klass_not_null(src); 5293 strw(src, Address(dst, oopDesc::klass_offset_in_bytes())); 5294 } else { 5295 str(src, Address(dst, oopDesc::klass_offset_in_bytes())); 5296 } 5297 } 5298 5299 void MacroAssembler::store_klass_gap(Register dst, Register src) { 5300 assert(!UseCompactObjectHeaders, "not with compact headers"); 5301 if (UseCompressedClassPointers) { 5302 // Store to klass gap in destination 5303 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes())); 5304 } 5305 } 5306 5307 // Algorithm must match CompressedOops::encode. 5308 void MacroAssembler::encode_heap_oop(Register d, Register s) { 5309 #ifdef ASSERT 5310 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 5311 #endif 5312 verify_oop_msg(s, "broken oop in encode_heap_oop"); 5313 if (CompressedOops::base() == nullptr) { 5314 if (CompressedOops::shift() != 0) { 5315 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 5316 lsr(d, s, LogMinObjAlignmentInBytes); 5317 } else { 5318 mov(d, s); 5319 } 5320 } else { 5321 subs(d, s, rheapbase); 5322 csel(d, d, zr, Assembler::HS); 5323 lsr(d, d, LogMinObjAlignmentInBytes); 5324 5325 /* Old algorithm: is this any worse? 5326 Label nonnull; 5327 cbnz(r, nonnull); 5328 sub(r, r, rheapbase); 5329 bind(nonnull); 5330 lsr(r, r, LogMinObjAlignmentInBytes); 5331 */ 5332 } 5333 } 5334 5335 void MacroAssembler::encode_heap_oop_not_null(Register r) { 5336 #ifdef ASSERT 5337 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 5338 if (CheckCompressedOops) { 5339 Label ok; 5340 cbnz(r, ok); 5341 stop("null oop passed to encode_heap_oop_not_null"); 5342 bind(ok); 5343 } 5344 #endif 5345 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null"); 5346 if (CompressedOops::base() != nullptr) { 5347 sub(r, r, rheapbase); 5348 } 5349 if (CompressedOops::shift() != 0) { 5350 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 5351 lsr(r, r, LogMinObjAlignmentInBytes); 5352 } 5353 } 5354 5355 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 5356 #ifdef ASSERT 5357 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 5358 if (CheckCompressedOops) { 5359 Label ok; 5360 cbnz(src, ok); 5361 stop("null oop passed to encode_heap_oop_not_null2"); 5362 bind(ok); 5363 } 5364 #endif 5365 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2"); 5366 5367 Register data = src; 5368 if (CompressedOops::base() != nullptr) { 5369 sub(dst, src, rheapbase); 5370 data = dst; 5371 } 5372 if (CompressedOops::shift() != 0) { 5373 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 5374 lsr(dst, data, LogMinObjAlignmentInBytes); 5375 data = dst; 5376 } 5377 if (data == src) 5378 mov(dst, src); 5379 } 5380 5381 void MacroAssembler::decode_heap_oop(Register d, Register s) { 5382 #ifdef ASSERT 5383 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 5384 #endif 5385 if (CompressedOops::base() == nullptr) { 5386 if (CompressedOops::shift() != 0) { 5387 lsl(d, s, CompressedOops::shift()); 5388 } else if (d != s) { 5389 mov(d, s); 5390 } 5391 } else { 5392 Label done; 5393 if (d != s) 5394 mov(d, s); 5395 cbz(s, done); 5396 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes); 5397 bind(done); 5398 } 5399 verify_oop_msg(d, "broken oop in decode_heap_oop"); 5400 } 5401 5402 void MacroAssembler::decode_heap_oop_not_null(Register r) { 5403 assert (UseCompressedOops, "should only be used for compressed headers"); 5404 assert (Universe::heap() != nullptr, "java heap should be initialized"); 5405 // Cannot assert, unverified entry point counts instructions (see .ad file) 5406 // vtableStubs also counts instructions in pd_code_size_limit. 5407 // Also do not verify_oop as this is called by verify_oop. 5408 if (CompressedOops::shift() != 0) { 5409 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 5410 if (CompressedOops::base() != nullptr) { 5411 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes); 5412 } else { 5413 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes); 5414 } 5415 } else { 5416 assert (CompressedOops::base() == nullptr, "sanity"); 5417 } 5418 } 5419 5420 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 5421 assert (UseCompressedOops, "should only be used for compressed headers"); 5422 assert (Universe::heap() != nullptr, "java heap should be initialized"); 5423 // Cannot assert, unverified entry point counts instructions (see .ad file) 5424 // vtableStubs also counts instructions in pd_code_size_limit. 5425 // Also do not verify_oop as this is called by verify_oop. 5426 if (CompressedOops::shift() != 0) { 5427 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 5428 if (CompressedOops::base() != nullptr) { 5429 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes); 5430 } else { 5431 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes); 5432 } 5433 } else { 5434 assert (CompressedOops::base() == nullptr, "sanity"); 5435 if (dst != src) { 5436 mov(dst, src); 5437 } 5438 } 5439 } 5440 5441 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone); 5442 5443 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() { 5444 assert(Metaspace::initialized(), "metaspace not initialized yet"); 5445 assert(_klass_decode_mode != KlassDecodeNone, "should be initialized"); 5446 return _klass_decode_mode; 5447 } 5448 5449 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode(address base, int shift, const size_t range) { 5450 assert(UseCompressedClassPointers, "not using compressed class pointers"); 5451 5452 // KlassDecodeMode shouldn't be set already. 5453 assert(_klass_decode_mode == KlassDecodeNone, "set once"); 5454 5455 if (base == nullptr) { 5456 return KlassDecodeZero; 5457 } 5458 5459 if (operand_valid_for_logical_immediate( 5460 /*is32*/false, (uint64_t)base)) { 5461 const uint64_t range_mask = right_n_bits(log2i_ceil(range)); 5462 if (((uint64_t)base & range_mask) == 0) { 5463 return KlassDecodeXor; 5464 } 5465 } 5466 5467 const uint64_t shifted_base = 5468 (uint64_t)base >> shift; 5469 if ((shifted_base & 0xffff0000ffffffff) == 0) { 5470 return KlassDecodeMovk; 5471 } 5472 5473 // No valid encoding. 5474 return KlassDecodeNone; 5475 } 5476 5477 // Check if one of the above decoding modes will work for given base, shift and range. 5478 bool MacroAssembler::check_klass_decode_mode(address base, int shift, const size_t range) { 5479 return klass_decode_mode(base, shift, range) != KlassDecodeNone; 5480 } 5481 5482 bool MacroAssembler::set_klass_decode_mode(address base, int shift, const size_t range) { 5483 _klass_decode_mode = klass_decode_mode(base, shift, range); 5484 return _klass_decode_mode != KlassDecodeNone; 5485 } 5486 5487 static Register pick_different_tmp(Register dst, Register src) { 5488 auto tmps = RegSet::of(r0, r1, r2) - RegSet::of(src, dst); 5489 return *tmps.begin(); 5490 } 5491 5492 void MacroAssembler::encode_klass_not_null_for_aot(Register dst, Register src) { 5493 // we have to load the klass base from the AOT constants area but 5494 // not the shift because it is not allowed to change 5495 int shift = CompressedKlassPointers::shift(); 5496 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!"); 5497 if (dst != src) { 5498 // we can load the base into dst, subtract it formthe src and shift down 5499 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr())); 5500 ldr(dst, dst); 5501 sub(dst, src, dst); 5502 lsr(dst, dst, shift); 5503 } else { 5504 // we need an extra register in order to load the coop base 5505 Register tmp = pick_different_tmp(dst, src); 5506 RegSet regs = RegSet::of(tmp); 5507 push(regs, sp); 5508 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr())); 5509 ldr(tmp, tmp); 5510 sub(dst, src, tmp); 5511 lsr(dst, dst, shift); 5512 pop(regs, sp); 5513 } 5514 } 5515 5516 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 5517 if (AOTCodeCache::is_on_for_dump()) { 5518 encode_klass_not_null_for_aot(dst, src); 5519 return; 5520 } 5521 5522 switch (klass_decode_mode()) { 5523 case KlassDecodeZero: 5524 if (CompressedKlassPointers::shift() != 0) { 5525 lsr(dst, src, CompressedKlassPointers::shift()); 5526 } else { 5527 if (dst != src) mov(dst, src); 5528 } 5529 break; 5530 5531 case KlassDecodeXor: 5532 if (CompressedKlassPointers::shift() != 0) { 5533 eor(dst, src, (uint64_t)CompressedKlassPointers::base()); 5534 lsr(dst, dst, CompressedKlassPointers::shift()); 5535 } else { 5536 eor(dst, src, (uint64_t)CompressedKlassPointers::base()); 5537 } 5538 break; 5539 5540 case KlassDecodeMovk: 5541 if (CompressedKlassPointers::shift() != 0) { 5542 ubfx(dst, src, CompressedKlassPointers::shift(), 32); 5543 } else { 5544 movw(dst, src); 5545 } 5546 break; 5547 5548 case KlassDecodeNone: 5549 ShouldNotReachHere(); 5550 break; 5551 } 5552 } 5553 5554 void MacroAssembler::encode_klass_not_null(Register r) { 5555 encode_klass_not_null(r, r); 5556 } 5557 5558 void MacroAssembler::decode_klass_not_null_for_aot(Register dst, Register src) { 5559 // we have to load the klass base from the AOT constants area but 5560 // not the shift because it is not allowed to change 5561 int shift = CompressedKlassPointers::shift(); 5562 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!"); 5563 if (dst != src) { 5564 // we can load the base into dst then add the offset with a suitable shift 5565 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr())); 5566 ldr(dst, dst); 5567 add(dst, dst, src, LSL, shift); 5568 } else { 5569 // we need an extra register in order to load the coop base 5570 Register tmp = pick_different_tmp(dst, src); 5571 RegSet regs = RegSet::of(tmp); 5572 push(regs, sp); 5573 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr())); 5574 ldr(tmp, tmp); 5575 add(dst, tmp, src, LSL, shift); 5576 pop(regs, sp); 5577 } 5578 } 5579 5580 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 5581 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5582 5583 if (AOTCodeCache::is_on_for_dump()) { 5584 decode_klass_not_null_for_aot(dst, src); 5585 return; 5586 } 5587 5588 switch (klass_decode_mode()) { 5589 case KlassDecodeZero: 5590 if (CompressedKlassPointers::shift() != 0) { 5591 lsl(dst, src, CompressedKlassPointers::shift()); 5592 } else { 5593 if (dst != src) mov(dst, src); 5594 } 5595 break; 5596 5597 case KlassDecodeXor: 5598 if (CompressedKlassPointers::shift() != 0) { 5599 lsl(dst, src, CompressedKlassPointers::shift()); 5600 eor(dst, dst, (uint64_t)CompressedKlassPointers::base()); 5601 } else { 5602 eor(dst, src, (uint64_t)CompressedKlassPointers::base()); 5603 } 5604 break; 5605 5606 case KlassDecodeMovk: { 5607 const uint64_t shifted_base = 5608 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift(); 5609 5610 if (dst != src) movw(dst, src); 5611 movk(dst, shifted_base >> 32, 32); 5612 5613 if (CompressedKlassPointers::shift() != 0) { 5614 lsl(dst, dst, CompressedKlassPointers::shift()); 5615 } 5616 5617 break; 5618 } 5619 5620 case KlassDecodeNone: 5621 ShouldNotReachHere(); 5622 break; 5623 } 5624 } 5625 5626 void MacroAssembler::decode_klass_not_null(Register r) { 5627 decode_klass_not_null(r, r); 5628 } 5629 5630 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 5631 #ifdef ASSERT 5632 { 5633 ThreadInVMfromUnknown tiv; 5634 assert (UseCompressedOops, "should only be used for compressed oops"); 5635 assert (Universe::heap() != nullptr, "java heap should be initialized"); 5636 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder"); 5637 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop"); 5638 } 5639 #endif 5640 int oop_index = oop_recorder()->find_index(obj); 5641 InstructionMark im(this); 5642 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5643 code_section()->relocate(inst_mark(), rspec); 5644 movz(dst, 0xDEAD, 16); 5645 movk(dst, 0xBEEF); 5646 } 5647 5648 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 5649 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5650 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder"); 5651 int index = oop_recorder()->find_index(k); 5652 5653 InstructionMark im(this); 5654 RelocationHolder rspec = metadata_Relocation::spec(index); 5655 code_section()->relocate(inst_mark(), rspec); 5656 narrowKlass nk = CompressedKlassPointers::encode(k); 5657 movz(dst, (nk >> 16), 16); 5658 movk(dst, nk & 0xffff); 5659 } 5660 5661 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, 5662 Register dst, Address src, 5663 Register tmp1, Register tmp2) { 5664 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); 5665 decorators = AccessInternal::decorator_fixup(decorators, type); 5666 bool as_raw = (decorators & AS_RAW) != 0; 5667 if (as_raw) { 5668 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2); 5669 } else { 5670 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2); 5671 } 5672 } 5673 5674 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, 5675 Address dst, Register val, 5676 Register tmp1, Register tmp2, Register tmp3) { 5677 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); 5678 decorators = AccessInternal::decorator_fixup(decorators, type); 5679 bool as_raw = (decorators & AS_RAW) != 0; 5680 if (as_raw) { 5681 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3); 5682 } else { 5683 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3); 5684 } 5685 } 5686 5687 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst, 5688 Register inline_layout_info) { 5689 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 5690 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info); 5691 } 5692 5693 void MacroAssembler::payload_offset(Register inline_klass, Register offset) { 5694 ldr(offset, Address(inline_klass, InlineKlass::adr_members_offset())); 5695 ldrw(offset, Address(offset, InlineKlass::payload_offset_offset())); 5696 } 5697 5698 void MacroAssembler::payload_address(Register oop, Register data, Register inline_klass) { 5699 // ((address) (void*) o) + vk->payload_offset(); 5700 Register offset = (data == oop) ? rscratch1 : data; 5701 payload_offset(inline_klass, offset); 5702 if (data == oop) { 5703 add(data, data, offset); 5704 } else { 5705 lea(data, Address(oop, offset)); 5706 } 5707 } 5708 5709 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass, 5710 Register index, Register data) { 5711 assert_different_registers(array, array_klass, index); 5712 assert_different_registers(rscratch1, array, index); 5713 5714 // array->base() + (index << Klass::layout_helper_log2_element_size(lh)); 5715 ldrw(rscratch1, Address(array_klass, Klass::layout_helper_offset())); 5716 5717 // Klass::layout_helper_log2_element_size(lh) 5718 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask; 5719 lsr(rscratch1, rscratch1, Klass::_lh_log2_element_size_shift); 5720 andr(rscratch1, rscratch1, Klass::_lh_log2_element_size_mask); 5721 lslv(index, index, rscratch1); 5722 5723 add(data, array, index); 5724 add(data, data, arrayOopDesc::base_offset_in_bytes(T_FLAT_ELEMENT)); 5725 } 5726 5727 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, 5728 Register tmp2, DecoratorSet decorators) { 5729 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2); 5730 } 5731 5732 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, 5733 Register tmp2, DecoratorSet decorators) { 5734 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2); 5735 } 5736 5737 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1, 5738 Register tmp2, Register tmp3, DecoratorSet decorators) { 5739 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3); 5740 } 5741 5742 // Used for storing nulls. 5743 void MacroAssembler::store_heap_oop_null(Address dst) { 5744 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg); 5745 } 5746 5747 Address MacroAssembler::allocate_metadata_address(Metadata* obj) { 5748 assert(oop_recorder() != nullptr, "this assembler needs a Recorder"); 5749 int index = oop_recorder()->allocate_metadata_index(obj); 5750 RelocationHolder rspec = metadata_Relocation::spec(index); 5751 return Address((address)obj, rspec); 5752 } 5753 5754 // Move an oop into a register. 5755 void MacroAssembler::movoop(Register dst, jobject obj) { 5756 int oop_index; 5757 if (obj == nullptr) { 5758 oop_index = oop_recorder()->allocate_oop_index(obj); 5759 } else { 5760 #ifdef ASSERT 5761 { 5762 ThreadInVMfromUnknown tiv; 5763 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop"); 5764 } 5765 #endif 5766 oop_index = oop_recorder()->find_index(obj); 5767 } 5768 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5769 5770 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) { 5771 mov(dst, Address((address)obj, rspec)); 5772 } else { 5773 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address 5774 ldr(dst, Address(dummy, rspec)); 5775 } 5776 } 5777 5778 // Move a metadata address into a register. 5779 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 5780 int oop_index; 5781 if (obj == nullptr) { 5782 oop_index = oop_recorder()->allocate_metadata_index(obj); 5783 } else { 5784 oop_index = oop_recorder()->find_index(obj); 5785 } 5786 RelocationHolder rspec = metadata_Relocation::spec(oop_index); 5787 mov(dst, Address((address)obj, rspec)); 5788 } 5789 5790 Address MacroAssembler::constant_oop_address(jobject obj) { 5791 #ifdef ASSERT 5792 { 5793 ThreadInVMfromUnknown tiv; 5794 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder"); 5795 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop"); 5796 } 5797 #endif 5798 int oop_index = oop_recorder()->find_index(obj); 5799 return Address((address)obj, oop_Relocation::spec(oop_index)); 5800 } 5801 5802 // Object / value buffer allocation... 5803 void MacroAssembler::allocate_instance(Register klass, Register new_obj, 5804 Register t1, Register t2, 5805 bool clear_fields, Label& alloc_failed) 5806 { 5807 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop; 5808 Register layout_size = t1; 5809 assert(new_obj == r0, "needs to be r0"); 5810 assert_different_registers(klass, new_obj, t1, t2); 5811 5812 // get instance_size in InstanceKlass (scaled to a count of bytes) 5813 ldrw(layout_size, Address(klass, Klass::layout_helper_offset())); 5814 // test to see if it is malformed in some way 5815 tst(layout_size, Klass::_lh_instance_slow_path_bit); 5816 br(Assembler::NE, slow_case_no_pop); 5817 5818 // Allocate the instance: 5819 // If TLAB is enabled: 5820 // Try to allocate in the TLAB. 5821 // If fails, go to the slow path. 5822 // Initialize the allocation. 5823 // Exit. 5824 // 5825 // Go to slow path. 5826 5827 if (UseTLAB) { 5828 push(klass); 5829 tlab_allocate(new_obj, layout_size, 0, klass, t2, slow_case); 5830 if (ZeroTLAB || (!clear_fields)) { 5831 // the fields have been already cleared 5832 b(initialize_header); 5833 } else { 5834 // initialize both the header and fields 5835 b(initialize_object); 5836 } 5837 5838 if (clear_fields) { 5839 // The object is initialized before the header. If the object size is 5840 // zero, go directly to the header initialization. 5841 bind(initialize_object); 5842 int header_size = oopDesc::header_size() * HeapWordSize; 5843 assert(is_aligned(header_size, BytesPerLong), "oop header size must be 8-byte-aligned"); 5844 subs(layout_size, layout_size, header_size); 5845 br(Assembler::EQ, initialize_header); 5846 5847 // Initialize topmost object field, divide size by 8, check if odd and 5848 // test if zero. 5849 5850 #ifdef ASSERT 5851 // make sure instance_size was multiple of 8 5852 Label L; 5853 tst(layout_size, 7); 5854 br(Assembler::EQ, L); 5855 stop("object size is not multiple of 8 - adjust this code"); 5856 bind(L); 5857 // must be > 0, no extra check needed here 5858 #endif 5859 5860 lsr(layout_size, layout_size, LogBytesPerLong); 5861 5862 // initialize remaining object fields: instance_size was a multiple of 8 5863 { 5864 Label loop; 5865 Register base = t2; 5866 5867 bind(loop); 5868 add(rscratch1, new_obj, layout_size, Assembler::LSL, LogBytesPerLong); 5869 str(zr, Address(rscratch1, header_size - 1*oopSize)); 5870 subs(layout_size, layout_size, 1); 5871 br(Assembler::NE, loop); 5872 } 5873 } // clear_fields 5874 5875 // initialize object header only. 5876 bind(initialize_header); 5877 pop(klass); 5878 Register mark_word = t2; 5879 if (UseCompactObjectHeaders || Arguments::is_valhalla_enabled()) { 5880 ldr(mark_word, Address(klass, Klass::prototype_header_offset())); 5881 str(mark_word, Address(new_obj, oopDesc::mark_offset_in_bytes())); 5882 } else { 5883 mov(mark_word, (intptr_t)markWord::prototype().value()); 5884 str(mark_word, Address(new_obj, oopDesc::mark_offset_in_bytes())); 5885 } 5886 if (!UseCompactObjectHeaders) { 5887 store_klass_gap(new_obj, zr); // zero klass gap for compressed oops 5888 mov(t2, klass); // preserve klass 5889 store_klass(new_obj, t2); // src klass reg is potentially compressed 5890 } 5891 b(done); 5892 } 5893 5894 if (UseTLAB) { 5895 bind(slow_case); 5896 pop(klass); 5897 } 5898 bind(slow_case_no_pop); 5899 b(alloc_failed); 5900 5901 bind(done); 5902 } 5903 5904 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 5905 void MacroAssembler::tlab_allocate(Register obj, 5906 Register var_size_in_bytes, 5907 int con_size_in_bytes, 5908 Register t1, 5909 Register t2, 5910 Label& slow_case) { 5911 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); 5912 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case); 5913 } 5914 5915 void MacroAssembler::verify_tlab() { 5916 #ifdef ASSERT 5917 if (UseTLAB && VerifyOops) { 5918 Label next, ok; 5919 5920 stp(rscratch2, rscratch1, Address(pre(sp, -16))); 5921 5922 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 5923 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 5924 cmp(rscratch2, rscratch1); 5925 br(Assembler::HS, next); 5926 STOP("assert(top >= start)"); 5927 should_not_reach_here(); 5928 5929 bind(next); 5930 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 5931 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 5932 cmp(rscratch2, rscratch1); 5933 br(Assembler::HS, ok); 5934 STOP("assert(top <= end)"); 5935 should_not_reach_here(); 5936 5937 bind(ok); 5938 ldp(rscratch2, rscratch1, Address(post(sp, 16))); 5939 } 5940 #endif 5941 } 5942 5943 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) { 5944 assert_different_registers(holder_klass, index, layout_info); 5945 InlineLayoutInfo array[2]; 5946 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements 5947 if (is_power_of_2(size)) { 5948 lsl(index, index, log2i_exact(size)); // Scale index by power of 2 5949 } else { 5950 mov(layout_info, size); 5951 mul(index, index, layout_info); // Scale the index to be the entry index * array_element_size 5952 } 5953 ldr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset())); 5954 add(layout_info, layout_info, Array<InlineLayoutInfo>::base_offset_in_bytes()); 5955 lea(layout_info, Address(layout_info, index)); 5956 } 5957 5958 // Writes to stack successive pages until offset reached to check for 5959 // stack overflow + shadow pages. This clobbers tmp. 5960 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 5961 assert_different_registers(tmp, size, rscratch1); 5962 mov(tmp, sp); 5963 // Bang stack for total size given plus shadow page size. 5964 // Bang one page at a time because large size can bang beyond yellow and 5965 // red zones. 5966 Label loop; 5967 mov(rscratch1, (int)os::vm_page_size()); 5968 bind(loop); 5969 lea(tmp, Address(tmp, -(int)os::vm_page_size())); 5970 subsw(size, size, rscratch1); 5971 str(size, Address(tmp)); 5972 br(Assembler::GT, loop); 5973 5974 // Bang down shadow pages too. 5975 // At this point, (tmp-0) is the last address touched, so don't 5976 // touch it again. (It was touched as (tmp-pagesize) but then tmp 5977 // was post-decremented.) Skip this address by starting at i=1, and 5978 // touch a few more pages below. N.B. It is important to touch all 5979 // the way down to and including i=StackShadowPages. 5980 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) { 5981 // this could be any sized move but this is can be a debugging crumb 5982 // so the bigger the better. 5983 lea(tmp, Address(tmp, -(int)os::vm_page_size())); 5984 str(size, Address(tmp)); 5985 } 5986 } 5987 5988 // Move the address of the polling page into dest. 5989 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) { 5990 ldr(dest, Address(rthread, JavaThread::polling_page_offset())); 5991 } 5992 5993 // Read the polling page. The address of the polling page must 5994 // already be in r. 5995 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) { 5996 address mark; 5997 { 5998 InstructionMark im(this); 5999 code_section()->relocate(inst_mark(), rtype); 6000 ldrw(zr, Address(r, 0)); 6001 mark = inst_mark(); 6002 } 6003 verify_cross_modify_fence_not_required(); 6004 return mark; 6005 } 6006 6007 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) { 6008 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12; 6009 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12; 6010 uint64_t dest_page = (uint64_t)dest.target() >> 12; 6011 int64_t offset_low = dest_page - low_page; 6012 int64_t offset_high = dest_page - high_page; 6013 6014 assert(is_valid_AArch64_address(dest.target()), "bad address"); 6015 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address"); 6016 6017 InstructionMark im(this); 6018 code_section()->relocate(inst_mark(), dest.rspec()); 6019 // 8143067: Ensure that the adrp can reach the dest from anywhere within 6020 // the code cache so that if it is relocated we know it will still reach 6021 if (offset_high >= -(1<<20) && offset_low < (1<<20)) { 6022 _adrp(reg1, dest.target()); 6023 } else { 6024 uint64_t target = (uint64_t)dest.target(); 6025 uint64_t adrp_target 6026 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL); 6027 6028 _adrp(reg1, (address)adrp_target); 6029 movk(reg1, target >> 32, 32); 6030 } 6031 byte_offset = (uint64_t)dest.target() & 0xfff; 6032 } 6033 6034 void MacroAssembler::load_byte_map_base(Register reg) { 6035 CardTableBarrierSet* ctbs = CardTableBarrierSet::barrier_set(); 6036 6037 // Strictly speaking the card table base isn't an address at all, and it might 6038 // even be negative. It is thus materialised as a constant. 6039 mov(reg, (uint64_t)ctbs->card_table_base_const()); 6040 } 6041 6042 #ifdef ASSERT 6043 void MacroAssembler::build_frame(int framesize) { 6044 build_frame(framesize, false); 6045 } 6046 #endif 6047 6048 void MacroAssembler::build_frame(int framesize DEBUG_ONLY(COMMA bool zap_rfp_lr_spills)) { 6049 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR"); 6050 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment"); 6051 protect_return_address(); 6052 if (framesize < ((1 << 9) + 2 * wordSize)) { 6053 sub(sp, sp, framesize); 6054 if (DEBUG_ONLY(zap_rfp_lr_spills ||) false) { 6055 mov_immediate64(rscratch1, ((uint64_t)badRegWordVal) << 32 | (uint64_t)badRegWordVal); 6056 stp(rscratch1, rscratch1, Address(sp, framesize - 2 * wordSize)); 6057 } else { 6058 stp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 6059 } 6060 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize); 6061 } else { 6062 if (DEBUG_ONLY(zap_rfp_lr_spills ||) false) { 6063 mov_immediate64(rscratch1, ((uint64_t)badRegWordVal) << 32 | (uint64_t)badRegWordVal); 6064 stp(rscratch1, rscratch1, Address(pre(sp, -2 * wordSize))); 6065 } else { 6066 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 6067 } 6068 if (PreserveFramePointer) mov(rfp, sp); 6069 if (framesize < ((1 << 12) + 2 * wordSize)) 6070 sub(sp, sp, framesize - 2 * wordSize); 6071 else { 6072 mov(rscratch1, framesize - 2 * wordSize); 6073 sub(sp, sp, rscratch1); 6074 } 6075 } 6076 verify_cross_modify_fence_not_required(); 6077 } 6078 6079 void MacroAssembler::remove_frame(int framesize) { 6080 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR"); 6081 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment"); 6082 if (framesize < ((1 << 9) + 2 * wordSize)) { 6083 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 6084 add(sp, sp, framesize); 6085 } else { 6086 if (framesize < ((1 << 12) + 2 * wordSize)) 6087 add(sp, sp, framesize - 2 * wordSize); 6088 else { 6089 mov(rscratch1, framesize - 2 * wordSize); 6090 add(sp, sp, rscratch1); 6091 } 6092 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 6093 } 6094 authenticate_return_address(); 6095 } 6096 6097 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) { 6098 if (needs_stack_repair) { 6099 // The method has a scalarized entry point (where fields of value object arguments 6100 // are passed through registers and stack), and a non-scalarized entry point (where 6101 // value object arguments are given as oops). The non-scalarized entry point will 6102 // first load each field of value object arguments and store them in registers and on 6103 // the stack in a way compatible with the scalarized entry point. To do so, some extra 6104 // stack space might be reserved (if argument registers are not enough). On leaving the 6105 // method, this space must be freed. 6106 // 6107 // In case we used the non-scalarized entry point the stack looks like this: 6108 // 6109 // | Arguments from caller | 6110 // |---------------------------| <-- caller's SP 6111 // | Saved LR #1 | 6112 // | Saved FP #1 | 6113 // |---------------------------| 6114 // | Extension space for | 6115 // | inline arg (un)packing | 6116 // |---------------------------| <-- start of this method's frame 6117 // | Saved LR #2 | 6118 // | Saved FP #2 | 6119 // |---------------------------| <-- FP (with -XX:+PreserveFramePointer) 6120 // | sp_inc | 6121 // | method locals | 6122 // |---------------------------| <-- SP 6123 // 6124 // There are two copies of FP and LR on the stack. They will be identical at 6125 // first, but that can change. 6126 // If the caller has been deoptimized, LR #1 will be patched to point at the 6127 // deopt blob, and LR #2 will still point into the old method. 6128 // If the saved FP (x29) was not used as the frame pointer, but to store an 6129 // oop, the GC will be aware only of FP #1 as the spilled location of x29 and 6130 // will fix only this one. Overall, FP/LR #2 are not reliable and are simply 6131 // needed to add space between the extension space and the locals, as there 6132 // would be between the real arguments and the locals if we don't need to 6133 // do unpacking (from the scalarized entry point). 6134 // 6135 // When restoring, one must then load FP #1 into x29, and LR #1 into x30, 6136 // while keeping in mind that from the scalarized entry point, there will be 6137 // only one copy of each. Indeed, in the case we used the scalarized calling 6138 // convention, the stack looks like this: 6139 // 6140 // | Arguments from caller | 6141 // |---------------------------| <-- caller's SP / start of this method's frame 6142 // | Saved LR | 6143 // | Saved FP | 6144 // |---------------------------| <-- FP (with -XX:+PreserveFramePointer) 6145 // | sp_inc | 6146 // | method locals | 6147 // |---------------------------| <-- SP 6148 // 6149 // The sp_inc stack slot holds the total size of the frame including the 6150 // extension space minus two words for the saved FP and LR. That is how to 6151 // find FP/LR #1. This size is expressed in bytes. Be careful when using it 6152 // from C++ in pointer arithmetic; you might need to divide it by wordSize. 6153 // 6154 // One can find sp_inc since the start the method's frame is SP + initial_framesize. 6155 6156 int sp_inc_offset = initial_framesize - 3 * wordSize; // Immediately below saved LR and FP 6157 6158 ldr(rscratch1, Address(sp, sp_inc_offset)); 6159 add(sp, sp, rscratch1); 6160 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 6161 } else { 6162 remove_frame(initial_framesize); 6163 } 6164 } 6165 6166 void MacroAssembler::save_stack_increment(int sp_inc, int frame_size) { 6167 int real_frame_size = frame_size + sp_inc; 6168 assert(sp_inc == 0 || sp_inc > 2*wordSize, "invalid sp_inc value"); 6169 assert(real_frame_size >= 2*wordSize, "frame size must include FP/LR space"); 6170 assert((real_frame_size & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 6171 6172 int sp_inc_offset = frame_size - 3 * wordSize; // Immediately below saved LR and FP 6173 6174 // Subtract two words for the saved FP and LR as these will be popped 6175 // separately. See remove_frame above. 6176 mov(rscratch1, real_frame_size - 2*wordSize); 6177 str(rscratch1, Address(sp, sp_inc_offset)); 6178 } 6179 6180 // This method counts leading positive bytes (highest bit not set) in provided byte array 6181 address MacroAssembler::count_positives(Register ary1, Register len, Register result) { 6182 // Simple and most common case of aligned small array which is not at the 6183 // end of memory page is placed here. All other cases are in stub. 6184 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE; 6185 const uint64_t UPPER_BIT_MASK=0x8080808080808080; 6186 assert_different_registers(ary1, len, result); 6187 6188 mov(result, len); 6189 cmpw(len, 0); 6190 br(LE, DONE); 6191 cmpw(len, 4 * wordSize); 6192 br(GE, STUB_LONG); // size > 32 then go to stub 6193 6194 int shift = 64 - exact_log2(os::vm_page_size()); 6195 lsl(rscratch1, ary1, shift); 6196 mov(rscratch2, (size_t)(4 * wordSize) << shift); 6197 adds(rscratch2, rscratch1, rscratch2); // At end of page? 6198 br(CS, STUB); // at the end of page then go to stub 6199 subs(len, len, wordSize); 6200 br(LT, END); 6201 6202 BIND(LOOP); 6203 ldr(rscratch1, Address(post(ary1, wordSize))); 6204 tst(rscratch1, UPPER_BIT_MASK); 6205 br(NE, SET_RESULT); 6206 subs(len, len, wordSize); 6207 br(GE, LOOP); 6208 cmpw(len, -wordSize); 6209 br(EQ, DONE); 6210 6211 BIND(END); 6212 ldr(rscratch1, Address(ary1)); 6213 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes 6214 lslv(rscratch1, rscratch1, rscratch2); 6215 tst(rscratch1, UPPER_BIT_MASK); 6216 br(NE, SET_RESULT); 6217 b(DONE); 6218 6219 BIND(STUB); 6220 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives()); 6221 assert(count_pos.target() != nullptr, "count_positives stub has not been generated"); 6222 address tpc1 = trampoline_call(count_pos); 6223 if (tpc1 == nullptr) { 6224 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE)); 6225 postcond(pc() == badAddress); 6226 return nullptr; 6227 } 6228 b(DONE); 6229 6230 BIND(STUB_LONG); 6231 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long()); 6232 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated"); 6233 address tpc2 = trampoline_call(count_pos_long); 6234 if (tpc2 == nullptr) { 6235 DEBUG_ONLY(reset_labels(SET_RESULT, DONE)); 6236 postcond(pc() == badAddress); 6237 return nullptr; 6238 } 6239 b(DONE); 6240 6241 BIND(SET_RESULT); 6242 6243 add(len, len, wordSize); 6244 sub(result, result, len); 6245 6246 BIND(DONE); 6247 postcond(pc() != badAddress); 6248 return pc(); 6249 } 6250 6251 // Clobbers: rscratch1, rscratch2, rflags 6252 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals) 6253 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3, 6254 Register tmp4, Register tmp5, Register result, 6255 Register cnt1, int elem_size) { 6256 Label DONE, SAME; 6257 Register tmp1 = rscratch1; 6258 Register tmp2 = rscratch2; 6259 int elem_per_word = wordSize/elem_size; 6260 int log_elem_size = exact_log2(elem_size); 6261 int klass_offset = arrayOopDesc::klass_offset_in_bytes(); 6262 int length_offset = arrayOopDesc::length_offset_in_bytes(); 6263 int base_offset 6264 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE); 6265 // When the length offset is not aligned to 8 bytes, 6266 // then we align it down. This is valid because the new 6267 // offset will always be the klass which is the same 6268 // for type arrays. 6269 int start_offset = align_down(length_offset, BytesPerWord); 6270 int extra_length = base_offset - start_offset; 6271 assert(start_offset == length_offset || start_offset == klass_offset, 6272 "start offset must be 8-byte-aligned or be the klass offset"); 6273 assert(base_offset != start_offset, "must include the length field"); 6274 extra_length = extra_length / elem_size; // We count in elements, not bytes. 6275 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16); 6276 6277 assert(elem_size == 1 || elem_size == 2, "must be char or byte"); 6278 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2); 6279 6280 #ifndef PRODUCT 6281 { 6282 const char kind = (elem_size == 2) ? 'U' : 'L'; 6283 char comment[64]; 6284 os::snprintf_checked(comment, sizeof comment, "array_equals%c{", kind); 6285 BLOCK_COMMENT(comment); 6286 } 6287 #endif 6288 6289 // if (a1 == a2) 6290 // return true; 6291 cmpoop(a1, a2); // May have read barriers for a1 and a2. 6292 br(EQ, SAME); 6293 6294 if (UseSimpleArrayEquals) { 6295 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL; 6296 // if (a1 == nullptr || a2 == nullptr) 6297 // return false; 6298 // a1 & a2 == 0 means (some-pointer is null) or 6299 // (very-rare-or-even-probably-impossible-pointer-values) 6300 // so, we can save one branch in most cases 6301 tst(a1, a2); 6302 mov(result, false); 6303 br(EQ, A_MIGHT_BE_NULL); 6304 // if (a1.length != a2.length) 6305 // return false; 6306 bind(A_IS_NOT_NULL); 6307 ldrw(cnt1, Address(a1, length_offset)); 6308 ldrw(tmp5, Address(a2, length_offset)); 6309 cmp(cnt1, tmp5); 6310 br(NE, DONE); // If lengths differ, return false 6311 // Increase loop counter by diff between base- and actual start-offset. 6312 addw(cnt1, cnt1, extra_length); 6313 lea(a1, Address(a1, start_offset)); 6314 lea(a2, Address(a2, start_offset)); 6315 // Check for short strings, i.e. smaller than wordSize. 6316 subs(cnt1, cnt1, elem_per_word); 6317 br(Assembler::LT, SHORT); 6318 // Main 8 byte comparison loop. 6319 bind(NEXT_WORD); { 6320 ldr(tmp1, Address(post(a1, wordSize))); 6321 ldr(tmp2, Address(post(a2, wordSize))); 6322 subs(cnt1, cnt1, elem_per_word); 6323 eor(tmp5, tmp1, tmp2); 6324 cbnz(tmp5, DONE); 6325 } br(GT, NEXT_WORD); 6326 // Last longword. In the case where length == 4 we compare the 6327 // same longword twice, but that's still faster than another 6328 // conditional branch. 6329 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when 6330 // length == 4. 6331 if (log_elem_size > 0) 6332 lsl(cnt1, cnt1, log_elem_size); 6333 ldr(tmp3, Address(a1, cnt1)); 6334 ldr(tmp4, Address(a2, cnt1)); 6335 eor(tmp5, tmp3, tmp4); 6336 cbnz(tmp5, DONE); 6337 b(SAME); 6338 bind(A_MIGHT_BE_NULL); 6339 // in case both a1 and a2 are not-null, proceed with loads 6340 cbz(a1, DONE); 6341 cbz(a2, DONE); 6342 b(A_IS_NOT_NULL); 6343 bind(SHORT); 6344 6345 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left. 6346 { 6347 ldrw(tmp1, Address(post(a1, 4))); 6348 ldrw(tmp2, Address(post(a2, 4))); 6349 eorw(tmp5, tmp1, tmp2); 6350 cbnzw(tmp5, DONE); 6351 } 6352 bind(TAIL03); 6353 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left. 6354 { 6355 ldrh(tmp3, Address(post(a1, 2))); 6356 ldrh(tmp4, Address(post(a2, 2))); 6357 eorw(tmp5, tmp3, tmp4); 6358 cbnzw(tmp5, DONE); 6359 } 6360 bind(TAIL01); 6361 if (elem_size == 1) { // Only needed when comparing byte arrays. 6362 tbz(cnt1, 0, SAME); // 0-1 bytes left. 6363 { 6364 ldrb(tmp1, a1); 6365 ldrb(tmp2, a2); 6366 eorw(tmp5, tmp1, tmp2); 6367 cbnzw(tmp5, DONE); 6368 } 6369 } 6370 } else { 6371 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB, 6372 CSET_EQ, LAST_CHECK; 6373 mov(result, false); 6374 cbz(a1, DONE); 6375 ldrw(cnt1, Address(a1, length_offset)); 6376 cbz(a2, DONE); 6377 ldrw(tmp5, Address(a2, length_offset)); 6378 cmp(cnt1, tmp5); 6379 br(NE, DONE); // If lengths differ, return false 6380 // Increase loop counter by diff between base- and actual start-offset. 6381 addw(cnt1, cnt1, extra_length); 6382 6383 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's 6384 // faster to perform another branch before comparing a1 and a2 6385 cmp(cnt1, (u1)elem_per_word); 6386 br(LE, SHORT); // short or same 6387 ldr(tmp3, Address(pre(a1, start_offset))); 6388 subs(zr, cnt1, stubBytesThreshold); 6389 br(GE, STUB); 6390 ldr(tmp4, Address(pre(a2, start_offset))); 6391 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size); 6392 6393 // Main 16 byte comparison loop with 2 exits 6394 bind(NEXT_DWORD); { 6395 ldr(tmp1, Address(pre(a1, wordSize))); 6396 ldr(tmp2, Address(pre(a2, wordSize))); 6397 subs(cnt1, cnt1, 2 * elem_per_word); 6398 br(LE, TAIL); 6399 eor(tmp4, tmp3, tmp4); 6400 cbnz(tmp4, DONE); 6401 ldr(tmp3, Address(pre(a1, wordSize))); 6402 ldr(tmp4, Address(pre(a2, wordSize))); 6403 cmp(cnt1, (u1)elem_per_word); 6404 br(LE, TAIL2); 6405 cmp(tmp1, tmp2); 6406 } br(EQ, NEXT_DWORD); 6407 b(DONE); 6408 6409 bind(TAIL); 6410 eor(tmp4, tmp3, tmp4); 6411 eor(tmp2, tmp1, tmp2); 6412 lslv(tmp2, tmp2, tmp5); 6413 orr(tmp5, tmp4, tmp2); 6414 cmp(tmp5, zr); 6415 b(CSET_EQ); 6416 6417 bind(TAIL2); 6418 eor(tmp2, tmp1, tmp2); 6419 cbnz(tmp2, DONE); 6420 b(LAST_CHECK); 6421 6422 bind(STUB); 6423 ldr(tmp4, Address(pre(a2, start_offset))); 6424 if (elem_size == 2) { // convert to byte counter 6425 lsl(cnt1, cnt1, 1); 6426 } 6427 eor(tmp5, tmp3, tmp4); 6428 cbnz(tmp5, DONE); 6429 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals()); 6430 assert(stub.target() != nullptr, "array_equals_long stub has not been generated"); 6431 address tpc = trampoline_call(stub); 6432 if (tpc == nullptr) { 6433 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE)); 6434 postcond(pc() == badAddress); 6435 return nullptr; 6436 } 6437 b(DONE); 6438 6439 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2) 6440 // so, if a2 == null => return false(0), else return true, so we can return a2 6441 mov(result, a2); 6442 b(DONE); 6443 bind(SHORT); 6444 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size); 6445 ldr(tmp3, Address(a1, start_offset)); 6446 ldr(tmp4, Address(a2, start_offset)); 6447 bind(LAST_CHECK); 6448 eor(tmp4, tmp3, tmp4); 6449 lslv(tmp5, tmp4, tmp5); 6450 cmp(tmp5, zr); 6451 bind(CSET_EQ); 6452 cset(result, EQ); 6453 b(DONE); 6454 } 6455 6456 bind(SAME); 6457 mov(result, true); 6458 // That's it. 6459 bind(DONE); 6460 6461 BLOCK_COMMENT("} array_equals"); 6462 postcond(pc() != badAddress); 6463 return pc(); 6464 } 6465 6466 // Compare Strings 6467 6468 // For Strings we're passed the address of the first characters in a1 6469 // and a2 and the length in cnt1. 6470 // There are two implementations. For arrays >= 8 bytes, all 6471 // comparisons (including the final one, which may overlap) are 6472 // performed 8 bytes at a time. For strings < 8 bytes, we compare a 6473 // halfword, then a short, and then a byte. 6474 6475 void MacroAssembler::string_equals(Register a1, Register a2, 6476 Register result, Register cnt1) 6477 { 6478 Label SAME, DONE, SHORT, NEXT_WORD; 6479 Register tmp1 = rscratch1; 6480 Register tmp2 = rscratch2; 6481 6482 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2); 6483 6484 #ifndef PRODUCT 6485 { 6486 char comment[64]; 6487 os::snprintf_checked(comment, sizeof comment, "{string_equalsL"); 6488 BLOCK_COMMENT(comment); 6489 } 6490 #endif 6491 6492 mov(result, false); 6493 6494 // Check for short strings, i.e. smaller than wordSize. 6495 subs(cnt1, cnt1, wordSize); 6496 br(Assembler::LT, SHORT); 6497 // Main 8 byte comparison loop. 6498 bind(NEXT_WORD); { 6499 ldr(tmp1, Address(post(a1, wordSize))); 6500 ldr(tmp2, Address(post(a2, wordSize))); 6501 subs(cnt1, cnt1, wordSize); 6502 eor(tmp1, tmp1, tmp2); 6503 cbnz(tmp1, DONE); 6504 } br(GT, NEXT_WORD); 6505 // Last longword. In the case where length == 4 we compare the 6506 // same longword twice, but that's still faster than another 6507 // conditional branch. 6508 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when 6509 // length == 4. 6510 ldr(tmp1, Address(a1, cnt1)); 6511 ldr(tmp2, Address(a2, cnt1)); 6512 eor(tmp2, tmp1, tmp2); 6513 cbnz(tmp2, DONE); 6514 b(SAME); 6515 6516 bind(SHORT); 6517 Label TAIL03, TAIL01; 6518 6519 tbz(cnt1, 2, TAIL03); // 0-7 bytes left. 6520 { 6521 ldrw(tmp1, Address(post(a1, 4))); 6522 ldrw(tmp2, Address(post(a2, 4))); 6523 eorw(tmp1, tmp1, tmp2); 6524 cbnzw(tmp1, DONE); 6525 } 6526 bind(TAIL03); 6527 tbz(cnt1, 1, TAIL01); // 0-3 bytes left. 6528 { 6529 ldrh(tmp1, Address(post(a1, 2))); 6530 ldrh(tmp2, Address(post(a2, 2))); 6531 eorw(tmp1, tmp1, tmp2); 6532 cbnzw(tmp1, DONE); 6533 } 6534 bind(TAIL01); 6535 tbz(cnt1, 0, SAME); // 0-1 bytes left. 6536 { 6537 ldrb(tmp1, a1); 6538 ldrb(tmp2, a2); 6539 eorw(tmp1, tmp1, tmp2); 6540 cbnzw(tmp1, DONE); 6541 } 6542 // Arrays are equal. 6543 bind(SAME); 6544 mov(result, true); 6545 6546 // That's it. 6547 bind(DONE); 6548 BLOCK_COMMENT("} string_equals"); 6549 } 6550 6551 6552 // The size of the blocks erased by the zero_blocks stub. We must 6553 // handle anything smaller than this ourselves in zero_words(). 6554 const int MacroAssembler::zero_words_block_size = 8; 6555 6556 // zero_words() is used by C2 ClearArray patterns and by 6557 // C1_MacroAssembler. It is as small as possible, handling small word 6558 // counts locally and delegating anything larger to the zero_blocks 6559 // stub. It is expanded many times in compiled code, so it is 6560 // important to keep it short. 6561 6562 // ptr: Address of a buffer to be zeroed. 6563 // cnt: Count in HeapWords. 6564 // 6565 // ptr, cnt, rscratch1, and rscratch2 are clobbered. 6566 address MacroAssembler::zero_words(Register ptr, Register cnt) 6567 { 6568 assert(is_power_of_2(zero_words_block_size), "adjust this"); 6569 6570 BLOCK_COMMENT("zero_words {"); 6571 assert(ptr == r10 && cnt == r11, "mismatch in register usage"); 6572 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks()); 6573 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated"); 6574 6575 subs(rscratch1, cnt, zero_words_block_size); 6576 Label around; 6577 br(LO, around); 6578 { 6579 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks()); 6580 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated"); 6581 // Make sure this is a C2 compilation. C1 allocates space only for 6582 // trampoline stubs generated by Call LIR ops, and in any case it 6583 // makes sense for a C1 compilation task to proceed as quickly as 6584 // possible. 6585 CompileTask* task; 6586 if (StubRoutines::aarch64::complete() 6587 && Thread::current()->is_Compiler_thread() 6588 && (task = ciEnv::current()->task()) 6589 && is_c2_compile(task->comp_level())) { 6590 address tpc = trampoline_call(zero_blocks); 6591 if (tpc == nullptr) { 6592 DEBUG_ONLY(reset_labels(around)); 6593 return nullptr; 6594 } 6595 } else { 6596 far_call(zero_blocks); 6597 } 6598 } 6599 bind(around); 6600 6601 // We have a few words left to do. zero_blocks has adjusted r10 and r11 6602 // for us. 6603 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) { 6604 Label l; 6605 tbz(cnt, exact_log2(i), l); 6606 for (int j = 0; j < i; j += 2) { 6607 stp(zr, zr, post(ptr, 2 * BytesPerWord)); 6608 } 6609 bind(l); 6610 } 6611 { 6612 Label l; 6613 tbz(cnt, 0, l); 6614 str(zr, Address(ptr)); 6615 bind(l); 6616 } 6617 6618 BLOCK_COMMENT("} zero_words"); 6619 return pc(); 6620 } 6621 6622 // base: Address of a buffer to be zeroed, 8 bytes aligned. 6623 // cnt: Immediate count in HeapWords. 6624 // 6625 // r10, r11, rscratch1, and rscratch2 are clobbered. 6626 address MacroAssembler::zero_words(Register base, uint64_t cnt) 6627 { 6628 assert(wordSize <= BlockZeroingLowLimit, 6629 "increase BlockZeroingLowLimit"); 6630 address result = nullptr; 6631 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) { 6632 #ifndef PRODUCT 6633 { 6634 char buf[64]; 6635 os::snprintf_checked(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt); 6636 BLOCK_COMMENT(buf); 6637 } 6638 #endif 6639 if (cnt >= 16) { 6640 uint64_t loops = cnt/16; 6641 if (loops > 1) { 6642 mov(rscratch2, loops - 1); 6643 } 6644 { 6645 Label loop; 6646 bind(loop); 6647 for (int i = 0; i < 16; i += 2) { 6648 stp(zr, zr, Address(base, i * BytesPerWord)); 6649 } 6650 add(base, base, 16 * BytesPerWord); 6651 if (loops > 1) { 6652 subs(rscratch2, rscratch2, 1); 6653 br(GE, loop); 6654 } 6655 } 6656 } 6657 cnt %= 16; 6658 int i = cnt & 1; // store any odd word to start 6659 if (i) str(zr, Address(base)); 6660 for (; i < (int)cnt; i += 2) { 6661 stp(zr, zr, Address(base, i * wordSize)); 6662 } 6663 BLOCK_COMMENT("} zero_words"); 6664 result = pc(); 6665 } else { 6666 mov(r10, base); mov(r11, cnt); 6667 result = zero_words(r10, r11); 6668 } 6669 return result; 6670 } 6671 6672 // Zero blocks of memory by using DC ZVA. 6673 // 6674 // Aligns the base address first sufficiently for DC ZVA, then uses 6675 // DC ZVA repeatedly for every full block. cnt is the size to be 6676 // zeroed in HeapWords. Returns the count of words left to be zeroed 6677 // in cnt. 6678 // 6679 // NOTE: This is intended to be used in the zero_blocks() stub. If 6680 // you want to use it elsewhere, note that cnt must be >= 2*zva_length. 6681 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) { 6682 Register tmp = rscratch1; 6683 Register tmp2 = rscratch2; 6684 int zva_length = VM_Version::zva_length(); 6685 Label initial_table_end, loop_zva; 6686 Label fini; 6687 6688 // Base must be 16 byte aligned. If not just return and let caller handle it 6689 tst(base, 0x0f); 6690 br(Assembler::NE, fini); 6691 // Align base with ZVA length. 6692 neg(tmp, base); 6693 andr(tmp, tmp, zva_length - 1); 6694 6695 // tmp: the number of bytes to be filled to align the base with ZVA length. 6696 add(base, base, tmp); 6697 sub(cnt, cnt, tmp, Assembler::ASR, 3); 6698 adr(tmp2, initial_table_end); 6699 sub(tmp2, tmp2, tmp, Assembler::LSR, 2); 6700 br(tmp2); 6701 6702 for (int i = -zva_length + 16; i < 0; i += 16) 6703 stp(zr, zr, Address(base, i)); 6704 bind(initial_table_end); 6705 6706 sub(cnt, cnt, zva_length >> 3); 6707 bind(loop_zva); 6708 dc(Assembler::ZVA, base); 6709 subs(cnt, cnt, zva_length >> 3); 6710 add(base, base, zva_length); 6711 br(Assembler::GE, loop_zva); 6712 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA 6713 bind(fini); 6714 } 6715 6716 // base: Address of a buffer to be filled, 8 bytes aligned. 6717 // cnt: Count in 8-byte unit. 6718 // value: Value to be filled with. 6719 // base will point to the end of the buffer after filling. 6720 void MacroAssembler::fill_words(Register base, Register cnt, Register value) 6721 { 6722 // Algorithm: 6723 // 6724 // if (cnt == 0) { 6725 // return; 6726 // } 6727 // if ((p & 8) != 0) { 6728 // *p++ = v; 6729 // } 6730 // 6731 // scratch1 = cnt & 14; 6732 // cnt -= scratch1; 6733 // p += scratch1; 6734 // switch (scratch1 / 2) { 6735 // do { 6736 // cnt -= 16; 6737 // p[-16] = v; 6738 // p[-15] = v; 6739 // case 7: 6740 // p[-14] = v; 6741 // p[-13] = v; 6742 // case 6: 6743 // p[-12] = v; 6744 // p[-11] = v; 6745 // // ... 6746 // case 1: 6747 // p[-2] = v; 6748 // p[-1] = v; 6749 // case 0: 6750 // p += 16; 6751 // } while (cnt); 6752 // } 6753 // if ((cnt & 1) == 1) { 6754 // *p++ = v; 6755 // } 6756 6757 assert_different_registers(base, cnt, value, rscratch1, rscratch2); 6758 6759 Label fini, skip, entry, loop; 6760 const int unroll = 8; // Number of stp instructions we'll unroll 6761 6762 cbz(cnt, fini); 6763 tbz(base, 3, skip); 6764 str(value, Address(post(base, 8))); 6765 sub(cnt, cnt, 1); 6766 bind(skip); 6767 6768 andr(rscratch1, cnt, (unroll-1) * 2); 6769 sub(cnt, cnt, rscratch1); 6770 add(base, base, rscratch1, Assembler::LSL, 3); 6771 adr(rscratch2, entry); 6772 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1); 6773 br(rscratch2); 6774 6775 bind(loop); 6776 add(base, base, unroll * 16); 6777 for (int i = -unroll; i < 0; i++) 6778 stp(value, value, Address(base, i * 16)); 6779 bind(entry); 6780 subs(cnt, cnt, unroll * 2); 6781 br(Assembler::GE, loop); 6782 6783 tbz(cnt, 0, fini); 6784 str(value, Address(post(base, 8))); 6785 bind(fini); 6786 } 6787 6788 // Intrinsic for 6789 // 6790 // - sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len) 6791 // Encodes char[] to byte[] in ISO-8859-1 6792 // 6793 // - java.lang.StringCoding#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len) 6794 // Encodes byte[] (containing UTF-16) to byte[] in ISO-8859-1 6795 // 6796 // - java.lang.StringCoding#encodeAsciiArray0(char[] sa, int sp, byte[] da, int dp, int len) 6797 // Encodes char[] to byte[] in ASCII 6798 // 6799 // This version always returns the number of characters copied, and does not 6800 // clobber the 'len' register. A successful copy will complete with the post- 6801 // condition: 'res' == 'len', while an unsuccessful copy will exit with the 6802 // post-condition: 0 <= 'res' < 'len'. 6803 // 6804 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to 6805 // degrade performance (on Ampere Altra - Neoverse N1), to an extent 6806 // beyond the acceptable, even though the footprint would be smaller. 6807 // Using 'umaxv' in the ASCII-case comes with a small penalty but does 6808 // avoid additional bloat. 6809 // 6810 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags 6811 void MacroAssembler::encode_iso_array(Register src, Register dst, 6812 Register len, Register res, bool ascii, 6813 FloatRegister vtmp0, FloatRegister vtmp1, 6814 FloatRegister vtmp2, FloatRegister vtmp3, 6815 FloatRegister vtmp4, FloatRegister vtmp5) 6816 { 6817 Register cnt = res; 6818 Register max = rscratch1; 6819 Register chk = rscratch2; 6820 6821 prfm(Address(src), PLDL1STRM); 6822 movw(cnt, len); 6823 6824 #define ASCII(insn) do { if (ascii) { insn; } } while (0) 6825 6826 Label LOOP_32, DONE_32, FAIL_32; 6827 6828 BIND(LOOP_32); 6829 { 6830 cmpw(cnt, 32); 6831 br(LT, DONE_32); 6832 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64))); 6833 // Extract lower bytes. 6834 FloatRegister vlo0 = vtmp4; 6835 FloatRegister vlo1 = vtmp5; 6836 uzp1(vlo0, T16B, vtmp0, vtmp1); 6837 uzp1(vlo1, T16B, vtmp2, vtmp3); 6838 // Merge bits... 6839 orr(vtmp0, T16B, vtmp0, vtmp1); 6840 orr(vtmp2, T16B, vtmp2, vtmp3); 6841 // Extract merged upper bytes. 6842 FloatRegister vhix = vtmp0; 6843 uzp2(vhix, T16B, vtmp0, vtmp2); 6844 // ISO-check on hi-parts (all zero). 6845 // ASCII-check on lo-parts (no sign). 6846 FloatRegister vlox = vtmp1; // Merge lower bytes. 6847 ASCII(orr(vlox, T16B, vlo0, vlo1)); 6848 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox)); 6849 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox)); 6850 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0)); 6851 ASCII(orr(chk, chk, max)); 6852 cbnz(chk, FAIL_32); 6853 subw(cnt, cnt, 32); 6854 st1(vlo0, vlo1, T16B, Address(post(dst, 32))); 6855 b(LOOP_32); 6856 } 6857 BIND(FAIL_32); 6858 sub(src, src, 64); 6859 BIND(DONE_32); 6860 6861 Label LOOP_8, SKIP_8; 6862 6863 BIND(LOOP_8); 6864 { 6865 cmpw(cnt, 8); 6866 br(LT, SKIP_8); 6867 FloatRegister vhi = vtmp0; 6868 FloatRegister vlo = vtmp1; 6869 ld1(vtmp3, T8H, src); 6870 uzp1(vlo, T16B, vtmp3, vtmp3); 6871 uzp2(vhi, T16B, vtmp3, vtmp3); 6872 // ISO-check on hi-parts (all zero). 6873 // ASCII-check on lo-parts (no sign). 6874 ASCII(cm(LT, vtmp2, T16B, vlo)); 6875 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2)); 6876 ASCII(umov(max, vtmp2, B, 0)); 6877 ASCII(orr(chk, chk, max)); 6878 cbnz(chk, SKIP_8); 6879 6880 strd(vlo, Address(post(dst, 8))); 6881 subw(cnt, cnt, 8); 6882 add(src, src, 16); 6883 b(LOOP_8); 6884 } 6885 BIND(SKIP_8); 6886 6887 #undef ASCII 6888 6889 Label LOOP, DONE; 6890 6891 cbz(cnt, DONE); 6892 BIND(LOOP); 6893 { 6894 Register chr = rscratch1; 6895 ldrh(chr, Address(post(src, 2))); 6896 tst(chr, ascii ? 0xff80 : 0xff00); 6897 br(NE, DONE); 6898 strb(chr, Address(post(dst, 1))); 6899 subs(cnt, cnt, 1); 6900 br(GT, LOOP); 6901 } 6902 BIND(DONE); 6903 // Return index where we stopped. 6904 subw(res, len, cnt); 6905 } 6906 6907 // Inflate byte[] array to char[]. 6908 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6 6909 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 6910 FloatRegister vtmp1, FloatRegister vtmp2, 6911 FloatRegister vtmp3, Register tmp4) { 6912 Label big, done, after_init, to_stub; 6913 6914 assert_different_registers(src, dst, len, tmp4, rscratch1); 6915 6916 fmovd(vtmp1, 0.0); 6917 lsrw(tmp4, len, 3); 6918 bind(after_init); 6919 cbnzw(tmp4, big); 6920 // Short string: less than 8 bytes. 6921 { 6922 Label loop, tiny; 6923 6924 cmpw(len, 4); 6925 br(LT, tiny); 6926 // Use SIMD to do 4 bytes. 6927 ldrs(vtmp2, post(src, 4)); 6928 zip1(vtmp3, T8B, vtmp2, vtmp1); 6929 subw(len, len, 4); 6930 strd(vtmp3, post(dst, 8)); 6931 6932 cbzw(len, done); 6933 6934 // Do the remaining bytes by steam. 6935 bind(loop); 6936 ldrb(tmp4, post(src, 1)); 6937 strh(tmp4, post(dst, 2)); 6938 subw(len, len, 1); 6939 6940 bind(tiny); 6941 cbnz(len, loop); 6942 6943 b(done); 6944 } 6945 6946 if (SoftwarePrefetchHintDistance >= 0) { 6947 bind(to_stub); 6948 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate()); 6949 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated"); 6950 address tpc = trampoline_call(stub); 6951 if (tpc == nullptr) { 6952 DEBUG_ONLY(reset_labels(big, done)); 6953 postcond(pc() == badAddress); 6954 return nullptr; 6955 } 6956 b(after_init); 6957 } 6958 6959 // Unpack the bytes 8 at a time. 6960 bind(big); 6961 { 6962 Label loop, around, loop_last, loop_start; 6963 6964 if (SoftwarePrefetchHintDistance >= 0) { 6965 const int large_loop_threshold = (64 + 16)/8; 6966 ldrd(vtmp2, post(src, 8)); 6967 andw(len, len, 7); 6968 cmp(tmp4, (u1)large_loop_threshold); 6969 br(GE, to_stub); 6970 b(loop_start); 6971 6972 bind(loop); 6973 ldrd(vtmp2, post(src, 8)); 6974 bind(loop_start); 6975 subs(tmp4, tmp4, 1); 6976 br(EQ, loop_last); 6977 zip1(vtmp2, T16B, vtmp2, vtmp1); 6978 ldrd(vtmp3, post(src, 8)); 6979 st1(vtmp2, T8H, post(dst, 16)); 6980 subs(tmp4, tmp4, 1); 6981 zip1(vtmp3, T16B, vtmp3, vtmp1); 6982 st1(vtmp3, T8H, post(dst, 16)); 6983 br(NE, loop); 6984 b(around); 6985 bind(loop_last); 6986 zip1(vtmp2, T16B, vtmp2, vtmp1); 6987 st1(vtmp2, T8H, post(dst, 16)); 6988 bind(around); 6989 cbz(len, done); 6990 } else { 6991 andw(len, len, 7); 6992 bind(loop); 6993 ldrd(vtmp2, post(src, 8)); 6994 sub(tmp4, tmp4, 1); 6995 zip1(vtmp3, T16B, vtmp2, vtmp1); 6996 st1(vtmp3, T8H, post(dst, 16)); 6997 cbnz(tmp4, loop); 6998 } 6999 } 7000 7001 // Do the tail of up to 8 bytes. 7002 add(src, src, len); 7003 ldrd(vtmp3, Address(src, -8)); 7004 add(dst, dst, len, ext::uxtw, 1); 7005 zip1(vtmp3, T16B, vtmp3, vtmp1); 7006 strq(vtmp3, Address(dst, -16)); 7007 7008 bind(done); 7009 postcond(pc() != badAddress); 7010 return pc(); 7011 } 7012 7013 // Compress char[] array to byte[]. 7014 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) 7015 // Return the array length if every element in array can be encoded, 7016 // otherwise, the index of first non-latin1 (> 0xff) character. 7017 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 7018 Register res, 7019 FloatRegister tmp0, FloatRegister tmp1, 7020 FloatRegister tmp2, FloatRegister tmp3, 7021 FloatRegister tmp4, FloatRegister tmp5) { 7022 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5); 7023 } 7024 7025 // java.math.round(double a) 7026 // Returns the closest long to the argument, with ties rounding to 7027 // positive infinity. This requires some fiddling for corner 7028 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5). 7029 void MacroAssembler::java_round_double(Register dst, FloatRegister src, 7030 FloatRegister ftmp) { 7031 Label DONE; 7032 BLOCK_COMMENT("java_round_double: { "); 7033 fmovd(rscratch1, src); 7034 // Use RoundToNearestTiesAway unless src small and -ve. 7035 fcvtasd(dst, src); 7036 // Test if src >= 0 || abs(src) >= 0x1.0p52 7037 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit 7038 mov(rscratch2, julong_cast(0x1.0p52)); 7039 cmp(rscratch1, rscratch2); 7040 br(HS, DONE); { 7041 // src < 0 && abs(src) < 0x1.0p52 7042 // src may have a fractional part, so add 0.5 7043 fmovd(ftmp, 0.5); 7044 faddd(ftmp, src, ftmp); 7045 // Convert double to jlong, use RoundTowardsNegative 7046 fcvtmsd(dst, ftmp); 7047 } 7048 bind(DONE); 7049 BLOCK_COMMENT("} java_round_double"); 7050 } 7051 7052 void MacroAssembler::java_round_float(Register dst, FloatRegister src, 7053 FloatRegister ftmp) { 7054 Label DONE; 7055 BLOCK_COMMENT("java_round_float: { "); 7056 fmovs(rscratch1, src); 7057 // Use RoundToNearestTiesAway unless src small and -ve. 7058 fcvtassw(dst, src); 7059 // Test if src >= 0 || abs(src) >= 0x1.0p23 7060 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit 7061 mov(rscratch2, jint_cast(0x1.0p23f)); 7062 cmp(rscratch1, rscratch2); 7063 br(HS, DONE); { 7064 // src < 0 && |src| < 0x1.0p23 7065 // src may have a fractional part, so add 0.5 7066 fmovs(ftmp, 0.5f); 7067 fadds(ftmp, src, ftmp); 7068 // Convert float to jint, use RoundTowardsNegative 7069 fcvtmssw(dst, ftmp); 7070 } 7071 bind(DONE); 7072 BLOCK_COMMENT("} java_round_float"); 7073 } 7074 7075 // get_thread() can be called anywhere inside generated code so we 7076 // need to save whatever non-callee save context might get clobbered 7077 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed, 7078 // the call setup code. 7079 // 7080 // On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags. 7081 // On other systems, the helper is a usual C function. 7082 // 7083 void MacroAssembler::get_thread(Register dst) { 7084 RegSet saved_regs = 7085 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst) 7086 NOT_LINUX (RegSet::range(r0, r17) + lr - dst); 7087 7088 protect_return_address(); 7089 push(saved_regs, sp); 7090 7091 mov(lr, ExternalAddress(CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper))); 7092 blr(lr); 7093 if (dst != c_rarg0) { 7094 mov(dst, c_rarg0); 7095 } 7096 7097 pop(saved_regs, sp); 7098 authenticate_return_address(); 7099 } 7100 7101 #ifdef COMPILER2 7102 // C2 compiled method's prolog code 7103 // Moved here from aarch64.ad to support Valhalla code below 7104 void MacroAssembler::verified_entry(Compile* C, int sp_inc) { 7105 if (C->clinit_barrier_on_entry()) { 7106 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started"); 7107 7108 Label L_skip_barrier; 7109 7110 mov_metadata(rscratch2, C->method()->holder()->constant_encoding()); 7111 clinit_barrier(rscratch2, rscratch1, &L_skip_barrier); 7112 far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); 7113 bind(L_skip_barrier); 7114 } 7115 7116 if (C->max_vector_size() > 0) { 7117 reinitialize_ptrue(); 7118 } 7119 7120 int bangsize = C->output()->bang_size_in_bytes(); 7121 if (C->output()->need_stack_bang(bangsize)) 7122 generate_stack_overflow_check(bangsize); 7123 7124 // n.b. frame size includes space for return pc and rfp 7125 const long framesize = C->output()->frame_size_in_bytes(); 7126 build_frame(framesize DEBUG_ONLY(COMMA sp_inc != 0)); 7127 7128 if (C->needs_stack_repair()) { 7129 save_stack_increment(sp_inc, framesize); 7130 } 7131 7132 if (VerifyStackAtCalls) { 7133 Unimplemented(); 7134 } 7135 } 7136 #endif // COMPILER2 7137 7138 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) { 7139 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields"); 7140 // An inline type might be returned. If fields are in registers we 7141 // need to allocate an inline type instance and initialize it with 7142 // the value of the fields. 7143 Label skip; 7144 // We only need a new buffered inline type if a new one is not returned 7145 tbz(r0, 0, skip); 7146 int call_offset = -1; 7147 7148 // Be careful not to clobber r1-7 which hold returned fields 7149 // Also do not use callee-saved registers as these may be live in the interpreter 7150 Register tmp1 = r13, tmp2 = r14, klass = r15, r0_preserved = r12; 7151 7152 // The following code is similar to allocate_instance but has some slight differences, 7153 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after 7154 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these. 7155 Label slow_case; 7156 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space 7157 mov(r0_preserved, r0); // save r0 for slow_case since *_allocate may corrupt it when allocation failed 7158 7159 if (vk != nullptr) { 7160 // Called from C1, where the return type is statically known. 7161 movptr(klass, (intptr_t)vk->get_InlineKlass()); 7162 jint lh = vk->layout_helper(); 7163 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved"); 7164 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) { 7165 tlab_allocate(r0, noreg, lh, tmp1, tmp2, slow_case); 7166 } else { 7167 b(slow_case); 7168 } 7169 } else { 7170 // Call from interpreter. R0 contains ((the InlineKlass* of the return type) | 0x01) 7171 andr(klass, r0, -2); 7172 if (UseTLAB) { 7173 ldrw(tmp2, Address(klass, Klass::layout_helper_offset())); 7174 tst(tmp2, Klass::_lh_instance_slow_path_bit); 7175 br(Assembler::NE, slow_case); 7176 tlab_allocate(r0, tmp2, 0, tmp1, tmp2, slow_case); 7177 } else { 7178 b(slow_case); 7179 } 7180 } 7181 if (UseTLAB) { 7182 // 2. Initialize buffered inline instance header 7183 Register buffer_obj = r0; 7184 if (UseCompactObjectHeaders) { 7185 ldr(rscratch1, Address(klass, Klass::prototype_header_offset())); 7186 str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes())); 7187 } else { 7188 mov(rscratch1, (intptr_t)markWord::inline_type_prototype().value()); 7189 str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes())); 7190 store_klass_gap(buffer_obj, zr); 7191 if (vk == nullptr) { 7192 // store_klass corrupts klass, so save it for later use (interpreter case only). 7193 mov(tmp1, klass); 7194 } 7195 store_klass(buffer_obj, klass); 7196 klass = tmp1; 7197 } 7198 // 3. Initialize its fields with an inline class specific handler 7199 if (vk != nullptr) { 7200 far_call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint. 7201 } else { 7202 ldr(tmp1, Address(klass, InlineKlass::adr_members_offset())); 7203 ldr(tmp1, Address(tmp1, InlineKlass::pack_handler_offset())); 7204 blr(tmp1); 7205 } 7206 7207 membar(Assembler::StoreStore); 7208 b(skip); 7209 } else { 7210 // Must have already branched to slow_case above. 7211 DEBUG_ONLY(should_not_reach_here()); 7212 } 7213 bind(slow_case); 7214 // We failed to allocate a new inline type, fall back to a runtime 7215 // call. Some oop field may be live in some registers but we can't 7216 // tell. That runtime call will take care of preserving them 7217 // across a GC if there's one. 7218 mov(r0, r0_preserved); 7219 7220 if (from_interpreter) { 7221 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf()); 7222 } else { 7223 far_call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf())); 7224 call_offset = offset(); 7225 } 7226 membar(Assembler::StoreStore); 7227 7228 bind(skip); 7229 return call_offset; 7230 } 7231 7232 // Move a value between registers/stack slots and update the reg_state 7233 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) { 7234 assert(from->is_valid() && to->is_valid(), "source and destination must be valid"); 7235 if (reg_state[to->value()] == reg_written) { 7236 return true; // Already written 7237 } 7238 7239 if (from != to && bt != T_VOID) { 7240 if (reg_state[to->value()] == reg_readonly) { 7241 return false; // Not yet writable 7242 } 7243 if (from->is_reg()) { 7244 if (to->is_reg()) { 7245 if (from->is_Register() && to->is_Register()) { 7246 mov(to->as_Register(), from->as_Register()); 7247 } else if (from->is_FloatRegister() && to->is_FloatRegister()) { 7248 fmovd(to->as_FloatRegister(), from->as_FloatRegister()); 7249 } else { 7250 ShouldNotReachHere(); 7251 } 7252 } else { 7253 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size; 7254 Address to_addr = Address(sp, st_off); 7255 if (from->is_FloatRegister()) { 7256 if (bt == T_DOUBLE) { 7257 strd(from->as_FloatRegister(), to_addr); 7258 } else { 7259 assert(bt == T_FLOAT, "must be float"); 7260 strs(from->as_FloatRegister(), to_addr); 7261 } 7262 } else { 7263 str(from->as_Register(), to_addr); 7264 } 7265 } 7266 } else { 7267 Address from_addr = Address(sp, from->reg2stack() * VMRegImpl::stack_slot_size); 7268 if (to->is_reg()) { 7269 if (to->is_FloatRegister()) { 7270 if (bt == T_DOUBLE) { 7271 ldrd(to->as_FloatRegister(), from_addr); 7272 } else { 7273 assert(bt == T_FLOAT, "must be float"); 7274 ldrs(to->as_FloatRegister(), from_addr); 7275 } 7276 } else { 7277 ldr(to->as_Register(), from_addr); 7278 } 7279 } else { 7280 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size; 7281 ldr(rscratch1, from_addr); 7282 str(rscratch1, Address(sp, st_off)); 7283 } 7284 } 7285 } 7286 7287 // Update register states 7288 reg_state[from->value()] = reg_writable; 7289 reg_state[to->value()] = reg_written; 7290 return true; 7291 } 7292 7293 // Calculate the extra stack space required for packing or unpacking inline 7294 // args and adjust the stack pointer 7295 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) { 7296 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size; 7297 sp_inc = align_up(sp_inc, StackAlignmentInBytes); 7298 assert(sp_inc > 0, "sanity"); 7299 7300 // Save a copy of the FP and LR here for deoptimization patching and frame walking 7301 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 7302 7303 // Adjust the stack pointer. This will be repaired on return by MacroAssembler::remove_frame 7304 if (sp_inc < (1 << 9)) { 7305 sub(sp, sp, sp_inc); // Fits in an immediate 7306 } else { 7307 mov(rscratch1, sp_inc); 7308 sub(sp, sp, rscratch1); 7309 } 7310 7311 return sp_inc + 2 * wordSize; // Account for the FP/LR space 7312 } 7313 7314 // Read all fields from an inline type oop and store the values in registers/stack slots 7315 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, 7316 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index, 7317 RegState reg_state[]) { 7318 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter"); 7319 assert(from->is_valid(), "source must be valid"); 7320 bool progress = false; 7321 #ifdef ASSERT 7322 const int start_offset = offset(); 7323 #endif 7324 7325 Label L_null, L_notNull; 7326 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for) 7327 Register tmp1 = r10; 7328 Register tmp2 = r11; 7329 7330 #ifndef ASSERT 7331 RegSet clobbered_gp_regs = MacroAssembler::call_clobbered_gp_registers(); 7332 assert(clobbered_gp_regs.contains(tmp1), "tmp1 must be saved explicitly if it's not a clobber"); 7333 assert(clobbered_gp_regs.contains(tmp2), "tmp2 must be saved explicitly if it's not a clobber"); 7334 assert(clobbered_gp_regs.contains(r14), "r14 must be saved explicitly if it's not a clobber"); 7335 #endif 7336 7337 Register fromReg = noreg; 7338 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, true); 7339 bool done = true; 7340 bool mark_done = true; 7341 VMReg toReg; 7342 BasicType bt; 7343 // Check if argument requires a null check 7344 bool null_check = false; 7345 VMReg nullCheckReg; 7346 while (stream.next(nullCheckReg, bt)) { 7347 if (sig->at(stream.sig_index())._offset == -1) { 7348 null_check = true; 7349 break; 7350 } 7351 } 7352 stream.reset(sig_index, to_index); 7353 while (stream.next(toReg, bt)) { 7354 assert(toReg->is_valid(), "destination must be valid"); 7355 int idx = (int)toReg->value(); 7356 if (reg_state[idx] == reg_readonly) { 7357 if (idx != from->value()) { 7358 mark_done = false; 7359 } 7360 done = false; 7361 continue; 7362 } else if (reg_state[idx] == reg_written) { 7363 continue; 7364 } 7365 assert(reg_state[idx] == reg_writable, "must be writable"); 7366 reg_state[idx] = reg_written; 7367 progress = true; 7368 7369 if (fromReg == noreg) { 7370 if (from->is_reg()) { 7371 fromReg = from->as_Register(); 7372 } else { 7373 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size; 7374 ldr(tmp1, Address(sp, st_off)); 7375 fromReg = tmp1; 7376 } 7377 if (null_check) { 7378 // Nullable inline type argument, emit null check 7379 cbz(fromReg, L_null); 7380 } 7381 } 7382 int off = sig->at(stream.sig_index())._offset; 7383 if (off == -1) { 7384 assert(null_check, "Missing null check at"); 7385 if (toReg->is_stack()) { 7386 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size; 7387 mov(tmp2, 1); 7388 str(tmp2, Address(sp, st_off)); 7389 } else { 7390 mov(toReg->as_Register(), 1); 7391 } 7392 continue; 7393 } 7394 assert(off > 0, "offset in object should be positive"); 7395 Address fromAddr = Address(fromReg, off); 7396 if (!toReg->is_FloatRegister()) { 7397 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register(); 7398 if (is_reference_type(bt)) { 7399 load_heap_oop(dst, fromAddr, rscratch1, rscratch2); 7400 } else { 7401 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN); 7402 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed); 7403 } 7404 if (toReg->is_stack()) { 7405 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size; 7406 str(dst, Address(sp, st_off)); 7407 } 7408 } else if (bt == T_DOUBLE) { 7409 ldrd(toReg->as_FloatRegister(), fromAddr); 7410 } else { 7411 assert(bt == T_FLOAT, "must be float"); 7412 ldrs(toReg->as_FloatRegister(), fromAddr); 7413 } 7414 } 7415 if (progress && null_check) { 7416 if (done) { 7417 b(L_notNull); 7418 bind(L_null); 7419 // Set null marker to zero to signal that the argument is null. 7420 // Also set all fields to zero since the runtime requires a canonical 7421 // representation of a flat null. 7422 stream.reset(sig_index, to_index); 7423 while (stream.next(toReg, bt)) { 7424 if (toReg->is_stack()) { 7425 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size; 7426 str(zr, Address(sp, st_off)); 7427 } else if (toReg->is_FloatRegister()) { 7428 mov(toReg->as_FloatRegister(), T2S, 0); 7429 } else { 7430 mov(toReg->as_Register(), zr); 7431 } 7432 } 7433 bind(L_notNull); 7434 } else { 7435 bind(L_null); 7436 } 7437 } 7438 7439 sig_index = stream.sig_index(); 7440 to_index = stream.regs_index(); 7441 7442 if (mark_done && reg_state[from->value()] != reg_written) { 7443 // This is okay because no one else will write to that slot 7444 reg_state[from->value()] = reg_writable; 7445 } 7446 from_index--; 7447 assert(progress || (start_offset == offset()), "should not emit code"); 7448 return done; 7449 } 7450 7451 // Pack fields back into an inline type oop 7452 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index, 7453 VMRegPair* from, int from_count, int& from_index, VMReg to, 7454 RegState reg_state[], Register val_array) { 7455 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter"); 7456 assert(to->is_valid(), "destination must be valid"); 7457 7458 if (reg_state[to->value()] == reg_written) { 7459 skip_unpacked_fields(sig, sig_index, from, from_count, from_index); 7460 return true; // Already written 7461 } 7462 7463 // The GC barrier expanded by store_heap_oop below may call into the 7464 // runtime so use callee-saved registers for any values that need to be 7465 // preserved. The GC barrier assembler should take care of saving the 7466 // Java argument registers. 7467 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value? 7468 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for). 7469 Register val_obj_tmp = r21; 7470 Register from_reg_tmp = r22; 7471 Register tmp1 = r14; 7472 Register tmp2 = r13; 7473 Register tmp3 = r12; 7474 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register(); 7475 7476 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array); 7477 7478 if (reg_state[to->value()] == reg_readonly) { 7479 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) { 7480 skip_unpacked_fields(sig, sig_index, from, from_count, from_index); 7481 return false; // Not yet writable 7482 } 7483 val_obj = val_obj_tmp; 7484 } 7485 7486 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT); 7487 load_heap_oop(val_obj, Address(val_array, index), tmp1, tmp2); 7488 7489 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index); 7490 VMReg fromReg; 7491 BasicType bt; 7492 Label L_null; 7493 while (stream.next(fromReg, bt)) { 7494 assert(fromReg->is_valid(), "source must be valid"); 7495 reg_state[fromReg->value()] = reg_writable; 7496 7497 int off = sig->at(stream.sig_index())._offset; 7498 if (off == -1) { 7499 // Nullable inline type argument, emit null check 7500 Label L_notNull; 7501 if (fromReg->is_stack()) { 7502 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size; 7503 ldrb(tmp2, Address(sp, ld_off)); 7504 cbnz(tmp2, L_notNull); 7505 } else { 7506 cbnz(fromReg->as_Register(), L_notNull); 7507 } 7508 mov(val_obj, 0); 7509 b(L_null); 7510 bind(L_notNull); 7511 continue; 7512 } 7513 7514 assert(off > 0, "offset in object should be positive"); 7515 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize; 7516 7517 // Pack the scalarized field into the value object. 7518 Address dst(val_obj, off); 7519 if (!fromReg->is_FloatRegister()) { 7520 Register src; 7521 if (fromReg->is_stack()) { 7522 src = from_reg_tmp; 7523 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size; 7524 load_sized_value(src, Address(sp, ld_off), size_in_bytes, /* is_signed */ false); 7525 } else { 7526 src = fromReg->as_Register(); 7527 } 7528 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array); 7529 if (is_reference_type(bt)) { 7530 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep val_obj valid. 7531 mov(tmp3, val_obj); 7532 Address dst_with_tmp3(tmp3, off); 7533 store_heap_oop(dst_with_tmp3, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED); 7534 } else { 7535 store_sized_value(dst, src, size_in_bytes); 7536 } 7537 } else if (bt == T_DOUBLE) { 7538 strd(fromReg->as_FloatRegister(), dst); 7539 } else { 7540 assert(bt == T_FLOAT, "must be float"); 7541 strs(fromReg->as_FloatRegister(), dst); 7542 } 7543 } 7544 bind(L_null); 7545 sig_index = stream.sig_index(); 7546 from_index = stream.regs_index(); 7547 7548 assert(reg_state[to->value()] == reg_writable, "must have already been read"); 7549 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state); 7550 assert(success, "to register must be writeable"); 7551 return true; 7552 } 7553 7554 VMReg MacroAssembler::spill_reg_for(VMReg reg) { 7555 return (reg->is_FloatRegister()) ? v8->as_VMReg() : r14->as_VMReg(); 7556 } 7557 7558 void MacroAssembler::cache_wb(Address line) { 7559 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset"); 7560 assert(line.index() == noreg, "index should be noreg"); 7561 assert(line.offset() == 0, "offset should be 0"); 7562 // would like to assert this 7563 // assert(line._ext.shift == 0, "shift should be zero"); 7564 if (VM_Version::supports_dcpop()) { 7565 // writeback using clear virtual address to point of persistence 7566 dc(Assembler::CVAP, line.base()); 7567 } else { 7568 // no need to generate anything as Unsafe.writebackMemory should 7569 // never invoke this stub 7570 } 7571 } 7572 7573 void MacroAssembler::cache_wbsync(bool is_pre) { 7574 // we only need a barrier post sync 7575 if (!is_pre) { 7576 membar(Assembler::AnyAny); 7577 } 7578 } 7579 7580 void MacroAssembler::verify_sve_vector_length(Register tmp) { 7581 if (!UseSVE || VM_Version::get_max_supported_sve_vector_length() == FloatRegister::sve_vl_min) { 7582 return; 7583 } 7584 // Make sure that native code does not change SVE vector length. 7585 Label verify_ok; 7586 movw(tmp, zr); 7587 sve_inc(tmp, B); 7588 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length()); 7589 br(EQ, verify_ok); 7590 stop("Error: SVE vector length has changed since jvm startup"); 7591 bind(verify_ok); 7592 } 7593 7594 void MacroAssembler::verify_ptrue() { 7595 Label verify_ok; 7596 if (!UseSVE) { 7597 return; 7598 } 7599 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count. 7600 sve_dec(rscratch1, B); 7601 cbz(rscratch1, verify_ok); 7602 stop("Error: the preserved predicate register (p7) elements are not all true"); 7603 bind(verify_ok); 7604 } 7605 7606 void MacroAssembler::safepoint_isb() { 7607 isb(); 7608 #ifndef PRODUCT 7609 if (VerifyCrossModifyFence) { 7610 // Clear the thread state. 7611 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset()))); 7612 } 7613 #endif 7614 } 7615 7616 #ifndef PRODUCT 7617 void MacroAssembler::verify_cross_modify_fence_not_required() { 7618 if (VerifyCrossModifyFence) { 7619 // Check if thread needs a cross modify fence. 7620 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset()))); 7621 Label fence_not_required; 7622 cbz(rscratch1, fence_not_required); 7623 // If it does then fail. 7624 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure))); 7625 mov(c_rarg0, rthread); 7626 blr(rscratch1); 7627 bind(fence_not_required); 7628 } 7629 } 7630 #endif 7631 7632 void MacroAssembler::spin_wait() { 7633 block_comment("spin_wait {"); 7634 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) { 7635 switch (VM_Version::spin_wait_desc().inst()) { 7636 case SpinWait::NOP: 7637 nop(); 7638 break; 7639 case SpinWait::ISB: 7640 isb(); 7641 break; 7642 case SpinWait::YIELD: 7643 yield(); 7644 break; 7645 case SpinWait::SB: 7646 assert(VM_Version::supports_sb(), "current CPU does not support SB instruction"); 7647 sb(); 7648 break; 7649 default: 7650 ShouldNotReachHere(); 7651 } 7652 } 7653 block_comment("}"); 7654 } 7655 7656 // Stack frame creation/removal 7657 7658 void MacroAssembler::enter(bool strip_ret_addr) { 7659 if (strip_ret_addr) { 7660 // Addresses can only be signed once. If there are multiple nested frames being created 7661 // in the same function, then the return address needs stripping first. 7662 strip_return_address(); 7663 } 7664 protect_return_address(); 7665 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 7666 mov(rfp, sp); 7667 } 7668 7669 void MacroAssembler::leave() { 7670 mov(sp, rfp); 7671 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 7672 authenticate_return_address(); 7673 } 7674 7675 // ROP Protection 7676 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/ 7677 // destroying stack frames or whenever directly loading/storing the LR to memory. 7678 // If ROP protection is not set then these functions are no-ops. 7679 // For more details on PAC see pauth_aarch64.hpp. 7680 7681 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory. 7682 // Uses value zero as the modifier. 7683 // 7684 void MacroAssembler::protect_return_address() { 7685 if (VM_Version::use_rop_protection()) { 7686 check_return_address(); 7687 paciaz(); 7688 } 7689 } 7690 7691 // Sign the return value in the given register. Use before updating the LR in the existing stack 7692 // frame for the current function. 7693 // Uses value zero as the modifier. 7694 // 7695 void MacroAssembler::protect_return_address(Register return_reg) { 7696 if (VM_Version::use_rop_protection()) { 7697 check_return_address(return_reg); 7698 paciza(return_reg); 7699 } 7700 } 7701 7702 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory. 7703 // Uses value zero as the modifier. 7704 // 7705 void MacroAssembler::authenticate_return_address() { 7706 if (VM_Version::use_rop_protection()) { 7707 autiaz(); 7708 check_return_address(); 7709 } 7710 } 7711 7712 // Authenticate the return value in the given register. Use before updating the LR in the existing 7713 // stack frame for the current function. 7714 // Uses value zero as the modifier. 7715 // 7716 void MacroAssembler::authenticate_return_address(Register return_reg) { 7717 if (VM_Version::use_rop_protection()) { 7718 autiza(return_reg); 7719 check_return_address(return_reg); 7720 } 7721 } 7722 7723 // Strip any PAC data from LR without performing any authentication. Use with caution - only if 7724 // there is no guaranteed way of authenticating the LR. 7725 // 7726 void MacroAssembler::strip_return_address() { 7727 if (VM_Version::use_rop_protection()) { 7728 xpaclri(); 7729 } 7730 } 7731 7732 #ifndef PRODUCT 7733 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only 7734 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point 7735 // it is difficult to debug back to the callee function. 7736 // This function simply loads from the address in the given register. 7737 // Use directly after authentication to catch authentication failures. 7738 // Also use before signing to check that the pointer is valid and hasn't already been signed. 7739 // 7740 void MacroAssembler::check_return_address(Register return_reg) { 7741 if (VM_Version::use_rop_protection()) { 7742 ldr(zr, Address(return_reg)); 7743 } 7744 } 7745 #endif 7746 7747 // The java_calling_convention describes stack locations as ideal slots on 7748 // a frame with no abi restrictions. Since we must observe abi restrictions 7749 // (like the placement of the register window) the slots must be biased by 7750 // the following value. 7751 static int reg2offset_in(VMReg r) { 7752 // Account for saved rfp and lr 7753 // This should really be in_preserve_stack_slots 7754 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size; 7755 } 7756 7757 static int reg2offset_out(VMReg r) { 7758 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; 7759 } 7760 7761 // On 64bit we will store integer like items to the stack as 7762 // 64bits items (AArch64 ABI) even though java would only store 7763 // 32bits for a parameter. On 32bit it will simply be 32bits 7764 // So this routine will do 32->32 on 32bit and 32->64 on 64bit 7765 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) { 7766 if (src.first()->is_stack()) { 7767 if (dst.first()->is_stack()) { 7768 // stack to stack 7769 ldr(tmp, Address(rfp, reg2offset_in(src.first()))); 7770 str(tmp, Address(sp, reg2offset_out(dst.first()))); 7771 } else { 7772 // stack to reg 7773 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first()))); 7774 } 7775 } else if (dst.first()->is_stack()) { 7776 // reg to stack 7777 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first()))); 7778 } else { 7779 if (dst.first() != src.first()) { 7780 sxtw(dst.first()->as_Register(), src.first()->as_Register()); 7781 } 7782 } 7783 } 7784 7785 // An oop arg. Must pass a handle not the oop itself 7786 void MacroAssembler::object_move( 7787 OopMap* map, 7788 int oop_handle_offset, 7789 int framesize_in_slots, 7790 VMRegPair src, 7791 VMRegPair dst, 7792 bool is_receiver, 7793 int* receiver_offset) { 7794 7795 // must pass a handle. First figure out the location we use as a handle 7796 7797 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register(); 7798 7799 // See if oop is null if it is we need no handle 7800 7801 if (src.first()->is_stack()) { 7802 7803 // Oop is already on the stack as an argument 7804 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); 7805 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); 7806 if (is_receiver) { 7807 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; 7808 } 7809 7810 ldr(rscratch1, Address(rfp, reg2offset_in(src.first()))); 7811 lea(rHandle, Address(rfp, reg2offset_in(src.first()))); 7812 // conditionally move a null 7813 cmp(rscratch1, zr); 7814 csel(rHandle, zr, rHandle, Assembler::EQ); 7815 } else { 7816 7817 // Oop is in an a register we must store it to the space we reserve 7818 // on the stack for oop_handles and pass a handle if oop is non-null 7819 7820 const Register rOop = src.first()->as_Register(); 7821 int oop_slot; 7822 if (rOop == j_rarg0) 7823 oop_slot = 0; 7824 else if (rOop == j_rarg1) 7825 oop_slot = 1; 7826 else if (rOop == j_rarg2) 7827 oop_slot = 2; 7828 else if (rOop == j_rarg3) 7829 oop_slot = 3; 7830 else if (rOop == j_rarg4) 7831 oop_slot = 4; 7832 else if (rOop == j_rarg5) 7833 oop_slot = 5; 7834 else if (rOop == j_rarg6) 7835 oop_slot = 6; 7836 else { 7837 assert(rOop == j_rarg7, "wrong register"); 7838 oop_slot = 7; 7839 } 7840 7841 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset; 7842 int offset = oop_slot*VMRegImpl::stack_slot_size; 7843 7844 map->set_oop(VMRegImpl::stack2reg(oop_slot)); 7845 // Store oop in handle area, may be null 7846 str(rOop, Address(sp, offset)); 7847 if (is_receiver) { 7848 *receiver_offset = offset; 7849 } 7850 7851 cmp(rOop, zr); 7852 lea(rHandle, Address(sp, offset)); 7853 // conditionally move a null 7854 csel(rHandle, zr, rHandle, Assembler::EQ); 7855 } 7856 7857 // If arg is on the stack then place it otherwise it is already in correct reg. 7858 if (dst.first()->is_stack()) { 7859 str(rHandle, Address(sp, reg2offset_out(dst.first()))); 7860 } 7861 } 7862 7863 // A float arg may have to do float reg int reg conversion 7864 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) { 7865 if (src.first()->is_stack()) { 7866 if (dst.first()->is_stack()) { 7867 ldrw(tmp, Address(rfp, reg2offset_in(src.first()))); 7868 strw(tmp, Address(sp, reg2offset_out(dst.first()))); 7869 } else { 7870 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first()))); 7871 } 7872 } else if (src.first() != dst.first()) { 7873 if (src.is_single_phys_reg() && dst.is_single_phys_reg()) 7874 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister()); 7875 else 7876 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first()))); 7877 } 7878 } 7879 7880 // A long move 7881 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) { 7882 if (src.first()->is_stack()) { 7883 if (dst.first()->is_stack()) { 7884 // stack to stack 7885 ldr(tmp, Address(rfp, reg2offset_in(src.first()))); 7886 str(tmp, Address(sp, reg2offset_out(dst.first()))); 7887 } else { 7888 // stack to reg 7889 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first()))); 7890 } 7891 } else if (dst.first()->is_stack()) { 7892 // reg to stack 7893 // Do we really have to sign extend??? 7894 // __ movslq(src.first()->as_Register(), src.first()->as_Register()); 7895 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first()))); 7896 } else { 7897 if (dst.first() != src.first()) { 7898 mov(dst.first()->as_Register(), src.first()->as_Register()); 7899 } 7900 } 7901 } 7902 7903 7904 // A double move 7905 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) { 7906 if (src.first()->is_stack()) { 7907 if (dst.first()->is_stack()) { 7908 ldr(tmp, Address(rfp, reg2offset_in(src.first()))); 7909 str(tmp, Address(sp, reg2offset_out(dst.first()))); 7910 } else { 7911 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first()))); 7912 } 7913 } else if (src.first() != dst.first()) { 7914 if (src.is_single_phys_reg() && dst.is_single_phys_reg()) 7915 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister()); 7916 else 7917 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first()))); 7918 } 7919 } 7920 7921 // Implements fast-locking. 7922 // 7923 // - obj: the object to be locked 7924 // - t1, t2, t3: temporary registers, will be destroyed 7925 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding). 7926 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow) { 7927 assert_different_registers(basic_lock, obj, t1, t2, t3, rscratch1); 7928 7929 Label push; 7930 const Register top = t1; 7931 const Register mark = t2; 7932 const Register t = t3; 7933 7934 // Preload the markWord. It is important that this is the first 7935 // instruction emitted as it is part of C1's null check semantics. 7936 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes())); 7937 7938 if (UseObjectMonitorTable) { 7939 // Clear cache in case fast locking succeeds or we need to take the slow-path. 7940 str(zr, Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes())))); 7941 } 7942 7943 if (DiagnoseSyncOnValueBasedClasses != 0) { 7944 load_klass(t1, obj); 7945 ldrb(t1, Address(t1, Klass::misc_flags_offset())); 7946 tst(t1, KlassFlags::_misc_is_value_based_class); 7947 br(Assembler::NE, slow); 7948 } 7949 7950 // Check if the lock-stack is full. 7951 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset())); 7952 cmpw(top, (unsigned)LockStack::end_offset()); 7953 br(Assembler::GE, slow); 7954 7955 // Check for recursion. 7956 subw(t, top, oopSize); 7957 ldr(t, Address(rthread, t)); 7958 cmp(obj, t); 7959 br(Assembler::EQ, push); 7960 7961 // Check header for monitor (0b10). 7962 tst(mark, markWord::monitor_value); 7963 br(Assembler::NE, slow); 7964 7965 // Try to lock. Transition lock bits 0b01 => 0b00 7966 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea"); 7967 orr(mark, mark, markWord::unlocked_value); 7968 // Mask inline_type bit such that we go to the slow path if object is an inline type 7969 andr(mark, mark, ~((int) markWord::inline_type_bit_in_place)); 7970 7971 eor(t, mark, markWord::unlocked_value); 7972 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword, 7973 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg); 7974 br(Assembler::NE, slow); 7975 7976 bind(push); 7977 // After successful lock, push object on lock-stack. 7978 str(obj, Address(rthread, top)); 7979 addw(top, top, oopSize); 7980 strw(top, Address(rthread, JavaThread::lock_stack_top_offset())); 7981 } 7982 7983 // Implements fast-unlocking. 7984 // 7985 // - obj: the object to be unlocked 7986 // - t1, t2, t3: temporary registers 7987 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding). 7988 void MacroAssembler::fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) { 7989 // cmpxchg clobbers rscratch1. 7990 assert_different_registers(obj, t1, t2, t3, rscratch1); 7991 7992 #ifdef ASSERT 7993 { 7994 // Check for lock-stack underflow. 7995 Label stack_ok; 7996 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset())); 7997 cmpw(t1, (unsigned)LockStack::start_offset()); 7998 br(Assembler::GE, stack_ok); 7999 STOP("Lock-stack underflow"); 8000 bind(stack_ok); 8001 } 8002 #endif 8003 8004 Label unlocked, push_and_slow; 8005 const Register top = t1; 8006 const Register mark = t2; 8007 const Register t = t3; 8008 8009 // Check if obj is top of lock-stack. 8010 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset())); 8011 subw(top, top, oopSize); 8012 ldr(t, Address(rthread, top)); 8013 cmp(obj, t); 8014 br(Assembler::NE, slow); 8015 8016 // Pop lock-stack. 8017 DEBUG_ONLY(str(zr, Address(rthread, top));) 8018 strw(top, Address(rthread, JavaThread::lock_stack_top_offset())); 8019 8020 // Check if recursive. 8021 subw(t, top, oopSize); 8022 ldr(t, Address(rthread, t)); 8023 cmp(obj, t); 8024 br(Assembler::EQ, unlocked); 8025 8026 // Not recursive. Check header for monitor (0b10). 8027 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes())); 8028 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow); 8029 8030 #ifdef ASSERT 8031 // Check header not unlocked (0b01). 8032 Label not_unlocked; 8033 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked); 8034 stop("fast_unlock already unlocked"); 8035 bind(not_unlocked); 8036 #endif 8037 8038 // Try to unlock. Transition lock bits 0b00 => 0b01 8039 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea"); 8040 orr(t, mark, markWord::unlocked_value); 8041 cmpxchg(obj, mark, t, Assembler::xword, 8042 /*acquire*/ false, /*release*/ true, /*weak*/ false, noreg); 8043 br(Assembler::EQ, unlocked); 8044 8045 bind(push_and_slow); 8046 // Restore lock-stack and handle the unlock in runtime. 8047 DEBUG_ONLY(str(obj, Address(rthread, top));) 8048 addw(top, top, oopSize); 8049 strw(top, Address(rthread, JavaThread::lock_stack_top_offset())); 8050 b(slow); 8051 8052 bind(unlocked); 8053 } --- EOF ---