1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/atomicAccess.hpp"
36 #include "runtime/vm_version.hpp"
37 #include "utilities/globalDefinitions.hpp"
38 #include "utilities/powerOfTwo.hpp"
39
40 class OopMap;
41
42 // MacroAssembler extends Assembler by frequently used macros.
43 //
44 // Instructions for which a 'better' code sequence exists depending
45 // on arguments should also go in here.
46
47 class MacroAssembler: public Assembler {
48 friend class LIR_Assembler;
49
50 public:
51 using Assembler::mov;
52 using Assembler::movi;
53
54 protected:
55
56 // Support for VM calls
57 //
58 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
59 // may customize this version by overriding it for its purposes (e.g., to save/restore
60 // additional registers when doing a VM call).
61 virtual void call_VM_leaf_base(
62 address entry_point, // the entry point
63 int number_of_arguments, // the number of arguments to pop after the call
64 Label *retaddr = nullptr
65 );
66
67 virtual void call_VM_leaf_base(
68 address entry_point, // the entry point
69 int number_of_arguments, // the number of arguments to pop after the call
70 Label &retaddr) {
71 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
72 }
73
74 // This is the base routine called by the different versions of call_VM. The interpreter
75 // may customize this version by overriding it for its purposes (e.g., to save/restore
76 // additional registers when doing a VM call).
77 //
78 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
79 // returns the register which contains the thread upon return. If a thread register has been
80 // specified, the return value will correspond to that register. If no last_java_sp is specified
81 // (noreg) than rsp will be used instead.
82 virtual void call_VM_base( // returns the register containing the thread upon return
83 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
84 Register java_thread, // the thread if computed before ; use noreg otherwise
85 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
86 Label* return_pc, // to set up last_Java_frame; use nullptr otherwise
87 address entry_point, // the entry point
88 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
89 bool check_exceptions // whether to check for pending exceptions after return
90 );
91
92 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
93
94 enum KlassDecodeMode {
95 KlassDecodeNone,
96 KlassDecodeZero,
97 KlassDecodeXor,
98 KlassDecodeMovk
99 };
100
101 // Calculate decoding mode based on given parameters, used for checking then ultimately setting.
102 static KlassDecodeMode klass_decode_mode(address base, int shift, const size_t range);
103
104 private:
105 static KlassDecodeMode _klass_decode_mode;
106
107 // Returns above setting with asserts
108 static KlassDecodeMode klass_decode_mode();
109
110 public:
111 // Checks the decode mode and returns false if not compatible with preferred decoding mode.
112 static bool check_klass_decode_mode(address base, int shift, const size_t range);
113
114 // Sets the decode mode and returns false if cannot be set.
115 static bool set_klass_decode_mode(address base, int shift, const size_t range);
116
117 public:
118 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
119
120 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
121 // The implementation is only non-empty for the InterpreterMacroAssembler,
122 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
123 virtual void check_and_handle_popframe(Register java_thread);
124 virtual void check_and_handle_earlyret(Register java_thread);
125
126 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp = rscratch1);
127 void rt_call(address dest, Register tmp = rscratch1);
128
129 // Load Effective Address
130 void lea(Register r, const Address &a) {
131 InstructionMark im(this);
132 a.lea(this, r);
133 }
134
135 // Whether materializing the given address for a LDR/STR requires an
136 // additional lea instruction.
137 static bool legitimize_address_requires_lea(const Address &a, int size) {
138 return a.getMode() == Address::base_plus_offset &&
139 !Address::offset_ok_for_immed(a.offset(), exact_log2(size));
140 }
141
142 /* Sometimes we get misaligned loads and stores, usually from Unsafe
143 accesses, and these can exceed the offset range. */
144 Address legitimize_address(const Address &a, int size, Register scratch) {
145 if (legitimize_address_requires_lea(a, size)) {
146 block_comment("legitimize_address {");
147 lea(scratch, a);
148 block_comment("} legitimize_address");
149 return Address(scratch);
150 }
151 return a;
152 }
153
154 void addmw(Address a, Register incr, Register scratch) {
155 ldrw(scratch, a);
156 addw(scratch, scratch, incr);
157 strw(scratch, a);
158 }
159
160 // Add constant to memory word
161 void addmw(Address a, int imm, Register scratch) {
162 ldrw(scratch, a);
163 if (imm > 0)
164 addw(scratch, scratch, (unsigned)imm);
165 else
166 subw(scratch, scratch, (unsigned)-imm);
167 strw(scratch, a);
168 }
169
170 void bind(Label& L) {
171 Assembler::bind(L);
172 code()->clear_last_merge_candidate();
173 code()->set_last_label(pc());
174 }
175
176 void membar(Membar_mask_bits order_constraint);
177
178 using Assembler::ldr;
179 using Assembler::str;
180 using Assembler::ldrw;
181 using Assembler::strw;
182
183 void ldr(Register Rx, const Address &adr);
184 void ldrw(Register Rw, const Address &adr);
185 void str(Register Rx, const Address &adr);
186 void strw(Register Rx, const Address &adr);
187
188 // Frame creation and destruction shared between JITs.
189 void build_frame(int framesize);
190 void remove_frame(int framesize);
191
192 virtual void _call_Unimplemented(address call_site) {
193 mov(rscratch2, call_site);
194 }
195
196 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
197 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
198 // https://reviews.llvm.org/D3311
199
200 #ifdef _WIN64
201 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
202 #else
203 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
204 #endif
205
206 // aliases defined in AARCH64 spec
207
208 template<class T>
209 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
210
211 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
212 inline void cmp(Register Rd, unsigned imm) = delete;
213
214 template<class T>
215 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
216
217 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
218 inline void cmn(Register Rd, unsigned imm) = delete;
219
220 void cset(Register Rd, Assembler::Condition cond) {
221 csinc(Rd, zr, zr, ~cond);
222 }
223 void csetw(Register Rd, Assembler::Condition cond) {
224 csincw(Rd, zr, zr, ~cond);
225 }
226
227 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
228 csneg(Rd, Rn, Rn, ~cond);
229 }
230 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
231 csnegw(Rd, Rn, Rn, ~cond);
232 }
233
234 inline void movw(Register Rd, Register Rn) {
235 if (Rd == sp || Rn == sp) {
236 Assembler::addw(Rd, Rn, 0U);
237 } else {
238 orrw(Rd, zr, Rn);
239 }
240 }
241 inline void mov(Register Rd, Register Rn) {
242 assert(Rd != r31_sp && Rn != r31_sp, "should be");
243 if (Rd == Rn) {
244 } else if (Rd == sp || Rn == sp) {
245 Assembler::add(Rd, Rn, 0U);
246 } else {
247 orr(Rd, zr, Rn);
248 }
249 }
250
251 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
252 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
253
254 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
255 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
256
257 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
258 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
259
260 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
261 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
262 }
263 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
264 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
265 }
266
267 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
268 bfmw(Rd, Rn, lsb, (lsb + width - 1));
269 }
270 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
271 bfm(Rd, Rn, lsb , (lsb + width - 1));
272 }
273
274 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
275 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
276 }
277 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
278 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
279 }
280
281 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
282 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
283 }
284 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
285 sbfm(Rd, Rn, lsb , (lsb + width - 1));
286 }
287
288 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
289 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
290 }
291 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
292 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
293 }
294
295 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
296 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
297 }
298 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
299 ubfm(Rd, Rn, lsb , (lsb + width - 1));
300 }
301
302 inline void asrw(Register Rd, Register Rn, unsigned imm) {
303 sbfmw(Rd, Rn, imm, 31);
304 }
305
306 inline void asr(Register Rd, Register Rn, unsigned imm) {
307 sbfm(Rd, Rn, imm, 63);
308 }
309
310 inline void lslw(Register Rd, Register Rn, unsigned imm) {
311 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
312 }
313
314 inline void lsl(Register Rd, Register Rn, unsigned imm) {
315 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
316 }
317
318 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
319 ubfmw(Rd, Rn, imm, 31);
320 }
321
322 inline void lsr(Register Rd, Register Rn, unsigned imm) {
323 ubfm(Rd, Rn, imm, 63);
324 }
325
326 inline void rorw(Register Rd, Register Rn, unsigned imm) {
327 extrw(Rd, Rn, Rn, imm);
328 }
329
330 inline void ror(Register Rd, Register Rn, unsigned imm) {
331 extr(Rd, Rn, Rn, imm);
332 }
333
334 inline void rolw(Register Rd, Register Rn, unsigned imm) {
335 extrw(Rd, Rn, Rn, (32 - imm));
336 }
337
338 inline void rol(Register Rd, Register Rn, unsigned imm) {
339 extr(Rd, Rn, Rn, (64 - imm));
340 }
341
342 using Assembler::rax1;
343 using Assembler::eor3;
344
345 inline void rax1(Register Rd, Register Rn, Register Rm) {
346 eor(Rd, Rn, Rm, ROR, 63); // Rd = Rn ^ rol(Rm, 1)
347 }
348
349 inline void eor3(Register Rd, Register Rn, Register Rm, Register Rk) {
350 assert(Rd != Rn, "Use tmp register");
351 eor(Rd, Rm, Rk);
352 eor(Rd, Rd, Rn);
353 }
354
355 inline void sxtbw(Register Rd, Register Rn) {
356 sbfmw(Rd, Rn, 0, 7);
357 }
358 inline void sxthw(Register Rd, Register Rn) {
359 sbfmw(Rd, Rn, 0, 15);
360 }
361 inline void sxtb(Register Rd, Register Rn) {
362 sbfm(Rd, Rn, 0, 7);
363 }
364 inline void sxth(Register Rd, Register Rn) {
365 sbfm(Rd, Rn, 0, 15);
366 }
367 inline void sxtw(Register Rd, Register Rn) {
368 sbfm(Rd, Rn, 0, 31);
369 }
370
371 inline void uxtbw(Register Rd, Register Rn) {
372 ubfmw(Rd, Rn, 0, 7);
373 }
374 inline void uxthw(Register Rd, Register Rn) {
375 ubfmw(Rd, Rn, 0, 15);
376 }
377 inline void uxtb(Register Rd, Register Rn) {
378 ubfm(Rd, Rn, 0, 7);
379 }
380 inline void uxth(Register Rd, Register Rn) {
381 ubfm(Rd, Rn, 0, 15);
382 }
383 inline void uxtw(Register Rd, Register Rn) {
384 ubfm(Rd, Rn, 0, 31);
385 }
386
387 inline void cmnw(Register Rn, Register Rm) {
388 addsw(zr, Rn, Rm);
389 }
390 inline void cmn(Register Rn, Register Rm) {
391 adds(zr, Rn, Rm);
392 }
393
394 inline void cmpw(Register Rn, Register Rm) {
395 subsw(zr, Rn, Rm);
396 }
397 inline void cmp(Register Rn, Register Rm) {
398 subs(zr, Rn, Rm);
399 }
400
401 inline void negw(Register Rd, Register Rn) {
402 subw(Rd, zr, Rn);
403 }
404
405 inline void neg(Register Rd, Register Rn) {
406 sub(Rd, zr, Rn);
407 }
408
409 inline void negsw(Register Rd, Register Rn) {
410 subsw(Rd, zr, Rn);
411 }
412
413 inline void negs(Register Rd, Register Rn) {
414 subs(Rd, zr, Rn);
415 }
416
417 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
418 addsw(zr, Rn, Rm, kind, shift);
419 }
420 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
421 adds(zr, Rn, Rm, kind, shift);
422 }
423
424 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
425 subsw(zr, Rn, Rm, kind, shift);
426 }
427 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
428 subs(zr, Rn, Rm, kind, shift);
429 }
430
431 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
432 subw(Rd, zr, Rn, kind, shift);
433 }
434
435 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
436 sub(Rd, zr, Rn, kind, shift);
437 }
438
439 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
440 subsw(Rd, zr, Rn, kind, shift);
441 }
442
443 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
444 subs(Rd, zr, Rn, kind, shift);
445 }
446
447 inline void mnegw(Register Rd, Register Rn, Register Rm) {
448 msubw(Rd, Rn, Rm, zr);
449 }
450 inline void mneg(Register Rd, Register Rn, Register Rm) {
451 msub(Rd, Rn, Rm, zr);
452 }
453
454 inline void mulw(Register Rd, Register Rn, Register Rm) {
455 maddw(Rd, Rn, Rm, zr);
456 }
457 inline void mul(Register Rd, Register Rn, Register Rm) {
458 madd(Rd, Rn, Rm, zr);
459 }
460
461 inline void smnegl(Register Rd, Register Rn, Register Rm) {
462 smsubl(Rd, Rn, Rm, zr);
463 }
464 inline void smull(Register Rd, Register Rn, Register Rm) {
465 smaddl(Rd, Rn, Rm, zr);
466 }
467
468 inline void umnegl(Register Rd, Register Rn, Register Rm) {
469 umsubl(Rd, Rn, Rm, zr);
470 }
471 inline void umull(Register Rd, Register Rn, Register Rm) {
472 umaddl(Rd, Rn, Rm, zr);
473 }
474
475 #define WRAP(INSN) \
476 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
477 if (VM_Version::supports_a53mac() && Ra != zr) \
478 nop(); \
479 Assembler::INSN(Rd, Rn, Rm, Ra); \
480 }
481
482 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
483 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
484 #undef WRAP
485
486 using Assembler::andw, Assembler::andr;
487 void andw(Register Rd, Register Rn, uint64_t imm) {
488 if (operand_valid_for_logical_immediate(/*is32*/true, imm)) {
489 Assembler::andw(Rd, Rn, imm);
490 } else {
491 assert(Rd != Rn, "must be");
492 movw(Rd, imm);
493 andw(Rd, Rn, Rd);
494 }
495 }
496 void andr(Register Rd, Register Rn, uint64_t imm) {
497 if (operand_valid_for_logical_immediate(/*is32*/false, imm)) {
498 Assembler::andr(Rd, Rn, imm);
499 } else {
500 assert(Rd != Rn, "must be");
501 mov(Rd, imm);
502 andr(Rd, Rn, Rd);
503 }
504 }
505
506 // macro assembly operations needed for aarch64
507
508 public:
509
510 enum FpPushPopMode {
511 PushPopFull,
512 PushPopSVE,
513 PushPopNeon,
514 PushPopFp
515 };
516
517 // first two private routines for loading 32 bit or 64 bit constants
518 private:
519
520 void mov_immediate64(Register dst, uint64_t imm64);
521 void mov_immediate32(Register dst, uint32_t imm32);
522
523 void mov(Register dst, Address a);
524
525 public:
526
527 int push(RegSet regset, Register stack);
528 int pop(RegSet regset, Register stack);
529
530 int push_fp(FloatRegSet regset, Register stack, FpPushPopMode mode = PushPopFull);
531 int pop_fp(FloatRegSet regset, Register stack, FpPushPopMode mode = PushPopFull);
532
533 static RegSet call_clobbered_gp_registers();
534
535 int push_p(PRegSet regset, Register stack);
536 int pop_p(PRegSet regset, Register stack);
537
538 // Push and pop everything that might be clobbered by a native
539 // runtime call except rscratch1 and rscratch2. (They are always
540 // scratch, so we don't have to protect them.) Only save the lower
541 // 64 bits of each vector register. Additional registers can be excluded
542 // in a passed RegSet.
543 void push_call_clobbered_registers_except(RegSet exclude);
544 void pop_call_clobbered_registers_except(RegSet exclude);
545
546 void push_call_clobbered_registers() {
547 push_call_clobbered_registers_except(RegSet());
548 }
549 void pop_call_clobbered_registers() {
550 pop_call_clobbered_registers_except(RegSet());
551 }
552
553
554 // now mov instructions for loading absolute addresses and 32 or
555 // 64 bit integers
556
557 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
558
559 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
560 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
561
562 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
563
564 void mov(Register dst, RegisterOrConstant src) {
565 if (src.is_register())
566 mov(dst, src.as_register());
567 else
568 mov(dst, src.as_constant());
569 }
570
571 void movptr(Register r, uintptr_t imm64);
572
573 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
574
575 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
576 orr(Vd, T, Vn, Vn);
577 }
578
579 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
580 fcvtsh(tmp, src);
581 smov(dst, tmp, H, 0);
582 }
583
584 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
585 mov(tmp, H, 0, src);
586 fcvths(dst, tmp);
587 }
588
589 // Generalized Test Bit And Branch, including a "far" variety which
590 // spans more than 32KiB.
591 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
592 assert(cond == EQ || cond == NE, "must be");
593
594 if (isfar)
595 cond = ~cond;
596
597 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
598 if (cond == Assembler::EQ)
599 branch = &Assembler::tbz;
600 else
601 branch = &Assembler::tbnz;
602
603 if (isfar) {
604 Label L;
605 (this->*branch)(Rt, bitpos, L);
606 b(dest);
607 bind(L);
608 } else {
609 (this->*branch)(Rt, bitpos, dest);
610 }
611 }
612
613 // macro instructions for accessing and updating floating point
614 // status register
615 //
616 // FPSR : op1 == 011
617 // CRn == 0100
618 // CRm == 0100
619 // op2 == 001
620
621 inline void get_fpsr(Register reg)
622 {
623 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
624 }
625
626 inline void set_fpsr(Register reg)
627 {
628 msr(0b011, 0b0100, 0b0100, 0b001, reg);
629 }
630
631 inline void clear_fpsr()
632 {
633 msr(0b011, 0b0100, 0b0100, 0b001, zr);
634 }
635
636 // FPCR : op1 == 011
637 // CRn == 0100
638 // CRm == 0100
639 // op2 == 000
640
641 inline void get_fpcr(Register reg) {
642 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
643 }
644
645 inline void set_fpcr(Register reg) {
646 msr(0b011, 0b0100, 0b0100, 0b000, reg);
647 }
648
649 // DCZID_EL0: op1 == 011
650 // CRn == 0000
651 // CRm == 0000
652 // op2 == 111
653 inline void get_dczid_el0(Register reg)
654 {
655 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
656 }
657
658 // CTR_EL0: op1 == 011
659 // CRn == 0000
660 // CRm == 0000
661 // op2 == 001
662 inline void get_ctr_el0(Register reg)
663 {
664 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
665 }
666
667 inline void get_nzcv(Register reg) {
668 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
669 }
670
671 inline void set_nzcv(Register reg) {
672 msr(0b011, 0b0100, 0b0010, 0b000, reg);
673 }
674
675 // CNTVCTSS_EL0: op1 == 011
676 // CRn == 1110
677 // CRm == 0000
678 // op2 == 110
679 inline void get_cntvctss_el0(Register reg) {
680 mrs(0b011, 0b1110, 0b0000, 0b110, reg);
681 }
682
683 // idiv variant which deals with MINLONG as dividend and -1 as divisor
684 int corrected_idivl(Register result, Register ra, Register rb,
685 bool want_remainder, Register tmp = rscratch1);
686 int corrected_idivq(Register result, Register ra, Register rb,
687 bool want_remainder, Register tmp = rscratch1);
688
689 // Support for null-checks
690 //
691 // Generates code that causes a null OS exception if the content of reg is null.
692 // If the accessed location is M[reg + offset] and the offset is known, provide the
693 // offset. No explicit code generation is needed if the offset is within a certain
694 // range (0 <= offset <= page_size).
695
696 virtual void null_check(Register reg, int offset = -1);
697 static bool needs_explicit_null_check(intptr_t offset);
698 static bool uses_implicit_null_check(void* address);
699
700 static address target_addr_for_insn(address insn_addr);
701
702 // Required platform-specific helpers for Label::patch_instructions.
703 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
704 static int pd_patch_instruction_size(address branch, address target);
705 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
706 pd_patch_instruction_size(branch, target);
707 }
708 static address pd_call_destination(address branch) {
709 return target_addr_for_insn(branch);
710 }
711 #ifndef PRODUCT
712 static void pd_print_patched_instruction(address branch);
713 #endif
714
715 static int patch_oop(address insn_addr, address o);
716
717 // Return whether code is emitted to a scratch blob.
718 virtual bool in_scratch_emit_size() {
719 return false;
720 }
721 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
722 static int max_trampoline_stub_size();
723 void emit_static_call_stub();
724 static int static_call_stub_size();
725
726 // The following 4 methods return the offset of the appropriate move instruction
727
728 // Support for fast byte/short loading with zero extension (depending on particular CPU)
729 int load_unsigned_byte(Register dst, Address src);
730 int load_unsigned_short(Register dst, Address src);
731
732 // Support for fast byte/short loading with sign extension (depending on particular CPU)
733 int load_signed_byte(Register dst, Address src);
734 int load_signed_short(Register dst, Address src);
735
736 int load_signed_byte32(Register dst, Address src);
737 int load_signed_short32(Register dst, Address src);
738
739 // Support for sign-extension (hi:lo = extend_sign(lo))
740 void extend_sign(Register hi, Register lo);
741
742 // Clean up a subword typed value to the representation in compliance with JVMS ยง2.3
743 void narrow_subword_type(Register reg, BasicType bt);
744
745 // Load and store values by size and signed-ness
746 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
747 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
748
749 // Support for inc/dec with optimal instruction selection depending on value
750
751 // x86_64 aliases an unqualified register/address increment and
752 // decrement to call incrementq and decrementq but also supports
753 // explicitly sized calls to incrementq/decrementq or
754 // incrementl/decrementl
755
756 // for aarch64 the proper convention would be to use
757 // increment/decrement for 64 bit operations and
758 // incrementw/decrementw for 32 bit operations. so when porting
759 // x86_64 code we can leave calls to increment/decrement as is,
760 // replace incrementq/decrementq with increment/decrement and
761 // replace incrementl/decrementl with incrementw/decrementw.
762
763 // n.b. increment/decrement calls with an Address destination will
764 // need to use a scratch register to load the value to be
765 // incremented. increment/decrement calls which add or subtract a
766 // constant value greater than 2^24 will need to use a 2nd scratch
767 // register to hold the constant. so, a register increment/decrement
768 // may trash rscratch2 and an address increment/decrement trash
769 // rscratch and rscratch2
770
771 void decrementw(Address dst, int value = 1);
772 void decrementw(Register reg, int value = 1);
773
774 void decrement(Register reg, int value = 1);
775 void decrement(Address dst, int value = 1);
776
777 void incrementw(Address dst, int value = 1, Register result = rscratch1);
778 void incrementw(Register reg, int value = 1);
779
780 void increment(Register reg, int value = 1);
781 void increment(Address dst, int value = 1, Register result = rscratch1);
782
783
784 // Alignment
785 void align(int modulus);
786 void align(int modulus, int target);
787
788 // nop
789 void post_call_nop();
790
791 // Stack frame creation/removal
792 void enter(bool strip_ret_addr = false);
793 void leave();
794
795 // ROP Protection
796 void protect_return_address();
797 void protect_return_address(Register return_reg);
798 void authenticate_return_address();
799 void authenticate_return_address(Register return_reg);
800 void strip_return_address();
801 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
802
803 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
804 // The pointer will be loaded into the thread register.
805 void get_thread(Register thread);
806
807 // support for argument shuffling
808 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
809 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
810 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
811 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
812 void object_move(
813 OopMap* map,
814 int oop_handle_offset,
815 int framesize_in_slots,
816 VMRegPair src,
817 VMRegPair dst,
818 bool is_receiver,
819 int* receiver_offset);
820
821
822 // Support for VM calls
823 //
824 // It is imperative that all calls into the VM are handled via the call_VM macros.
825 // They make sure that the stack linkage is setup correctly. call_VM's correspond
826 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
827
828
829 void call_VM(Register oop_result,
830 address entry_point,
831 bool check_exceptions = true);
832 void call_VM(Register oop_result,
833 address entry_point,
834 Register arg_1,
835 bool check_exceptions = true);
836 void call_VM(Register oop_result,
837 address entry_point,
838 Register arg_1, Register arg_2,
839 bool check_exceptions = true);
840 void call_VM(Register oop_result,
841 address entry_point,
842 Register arg_1, Register arg_2, Register arg_3,
843 bool check_exceptions = true);
844
845 // Overloadings with last_Java_sp
846 void call_VM(Register oop_result,
847 Register last_java_sp,
848 address entry_point,
849 int number_of_arguments = 0,
850 bool check_exceptions = true);
851 void call_VM(Register oop_result,
852 Register last_java_sp,
853 address entry_point,
854 Register arg_1, bool
855 check_exceptions = true);
856 void call_VM(Register oop_result,
857 Register last_java_sp,
858 address entry_point,
859 Register arg_1, Register arg_2,
860 bool check_exceptions = true);
861 void call_VM(Register oop_result,
862 Register last_java_sp,
863 address entry_point,
864 Register arg_1, Register arg_2, Register arg_3,
865 bool check_exceptions = true);
866
867 void get_vm_result_oop(Register oop_result, Register thread);
868 void get_vm_result_metadata(Register metadata_result, Register thread);
869
870 // These always tightly bind to MacroAssembler::call_VM_base
871 // bypassing the virtual implementation
872 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
873 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
874 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
875 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
876 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
877
878 void call_VM_leaf(address entry_point,
879 int number_of_arguments = 0);
880 void call_VM_leaf(address entry_point,
881 Register arg_1);
882 void call_VM_leaf(address entry_point,
883 Register arg_1, Register arg_2);
884 void call_VM_leaf(address entry_point,
885 Register arg_1, Register arg_2, Register arg_3);
886
887 // These always tightly bind to MacroAssembler::call_VM_leaf_base
888 // bypassing the virtual implementation
889 void super_call_VM_leaf(address entry_point);
890 void super_call_VM_leaf(address entry_point, Register arg_1);
891 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
892 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
893 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
894
895 // last Java Frame (fills frame anchor)
896 void set_last_Java_frame(Register last_java_sp,
897 Register last_java_fp,
898 address last_java_pc,
899 Register scratch);
900
901 void set_last_Java_frame(Register last_java_sp,
902 Register last_java_fp,
903 Label &last_java_pc,
904 Register scratch);
905
906 void set_last_Java_frame(Register last_java_sp,
907 Register last_java_fp,
908 Register last_java_pc,
909 Register scratch);
910
911 void reset_last_Java_frame(Register thread);
912
913 // thread in the default location (rthread)
914 void reset_last_Java_frame(bool clear_fp);
915
916 void resolve_jobject(Register value, Register tmp1, Register tmp2);
917 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
918
919 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
920 void c2bool(Register x);
921
922 void load_method_holder_cld(Register rresult, Register rmethod);
923 void load_method_holder(Register holder, Register method);
924
925 // oop manipulations
926 void load_narrow_klass_compact(Register dst, Register src);
927 void load_klass(Register dst, Register src);
928 void store_klass(Register dst, Register src);
929 void cmp_klass(Register obj, Register klass, Register tmp);
930 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
931
932 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
933 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
934 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
935
936 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
937 Register tmp1, Register tmp2);
938
939 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
940 Register tmp1, Register tmp2, Register tmp3);
941
942 void load_heap_oop(Register dst, Address src, Register tmp1,
943 Register tmp2, DecoratorSet decorators = 0);
944
945 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
946 Register tmp2, DecoratorSet decorators = 0);
947 void store_heap_oop(Address dst, Register val, Register tmp1,
948 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
949
950 // currently unimplemented
951 // Used for storing null. All other oop constants should be
952 // stored using routines that take a jobject.
953 void store_heap_oop_null(Address dst);
954
955 void store_klass_gap(Register dst, Register src);
956
957 // This dummy is to prevent a call to store_heap_oop from
958 // converting a zero (like null) into a Register by giving
959 // the compiler two choices it can't resolve
960
961 void store_heap_oop(Address dst, void* dummy);
962
963 void encode_heap_oop(Register d, Register s);
964 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
965 void decode_heap_oop(Register d, Register s);
966 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
967 void encode_heap_oop_not_null(Register r);
968 void decode_heap_oop_not_null(Register r);
969 void encode_heap_oop_not_null(Register dst, Register src);
970 void decode_heap_oop_not_null(Register dst, Register src);
971
972 void set_narrow_oop(Register dst, jobject obj);
973
974 void decode_klass_not_null_for_aot(Register dst, Register src);
975 void encode_klass_not_null_for_aot(Register dst, Register src);
976 void encode_klass_not_null(Register r);
977 void decode_klass_not_null(Register r);
978 void encode_klass_not_null(Register dst, Register src);
979 void decode_klass_not_null(Register dst, Register src);
980
981 void set_narrow_klass(Register dst, Klass* k);
982
983 // if heap base register is used - reinit it with the correct value
984 void reinit_heapbase();
985
986 DEBUG_ONLY(void verify_heapbase(const char* msg);)
987
988 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
989 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
990 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
991 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
992
993 void push_cont_fastpath(Register java_thread = rthread);
994 void pop_cont_fastpath(Register java_thread = rthread);
995
996 // Round up to a power of two
997 void round_to(Register reg, int modulus);
998
999 // java.lang.Math::round intrinsics
1000 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1001 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1002
1003 // allocation
1004 void tlab_allocate(
1005 Register obj, // result: pointer to object after successful allocation
1006 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1007 int con_size_in_bytes, // object size in bytes if known at compile time
1008 Register t1, // temp register
1009 Register t2, // temp register
1010 Label& slow_case // continuation point if fast allocation fails
1011 );
1012 void verify_tlab();
1013
1014 // interface method calling
1015 void lookup_interface_method(Register recv_klass,
1016 Register intf_klass,
1017 RegisterOrConstant itable_index,
1018 Register method_result,
1019 Register scan_temp,
1020 Label& no_such_interface,
1021 bool return_method = true);
1022
1023 void lookup_interface_method_stub(Register recv_klass,
1024 Register holder_klass,
1025 Register resolved_klass,
1026 Register method_result,
1027 Register temp_reg,
1028 Register temp_reg2,
1029 int itable_index,
1030 Label& L_no_such_interface);
1031
1032 // virtual method calling
1033 // n.b. x86 allows RegisterOrConstant for vtable_index
1034 void lookup_virtual_method(Register recv_klass,
1035 RegisterOrConstant vtable_index,
1036 Register method_result);
1037
1038 // Test sub_klass against super_klass, with fast and slow paths.
1039
1040 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1041 // One of the three labels can be null, meaning take the fall-through.
1042 // If super_check_offset is -1, the value is loaded up from super_klass.
1043 // No registers are killed, except temp_reg.
1044 void check_klass_subtype_fast_path(Register sub_klass,
1045 Register super_klass,
1046 Register temp_reg,
1047 Label* L_success,
1048 Label* L_failure,
1049 Label* L_slow_path,
1050 Register super_check_offset = noreg);
1051
1052 // The rest of the type check; must be wired to a corresponding fast path.
1053 // It does not repeat the fast path logic, so don't use it standalone.
1054 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1055 // Updates the sub's secondary super cache as necessary.
1056 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1057 void check_klass_subtype_slow_path(Register sub_klass,
1058 Register super_klass,
1059 Register temp_reg,
1060 Register temp2_reg,
1061 Label* L_success,
1062 Label* L_failure,
1063 bool set_cond_codes = false);
1064
1065 void check_klass_subtype_slow_path_linear(Register sub_klass,
1066 Register super_klass,
1067 Register temp_reg,
1068 Register temp2_reg,
1069 Label* L_success,
1070 Label* L_failure,
1071 bool set_cond_codes = false);
1072
1073 void check_klass_subtype_slow_path_table(Register sub_klass,
1074 Register super_klass,
1075 Register temp_reg,
1076 Register temp2_reg,
1077 Register temp3_reg,
1078 Register result_reg,
1079 FloatRegister vtemp_reg,
1080 Label* L_success,
1081 Label* L_failure,
1082 bool set_cond_codes = false);
1083
1084 // If r is valid, return r.
1085 // If r is invalid, remove a register r2 from available_regs, add r2
1086 // to regs_to_push, then return r2.
1087 Register allocate_if_noreg(const Register r,
1088 RegSetIterator<Register> &available_regs,
1089 RegSet ®s_to_push);
1090
1091 // Secondary subtype checking
1092 void lookup_secondary_supers_table_var(Register sub_klass,
1093 Register r_super_klass,
1094 Register temp1,
1095 Register temp2,
1096 Register temp3,
1097 FloatRegister vtemp,
1098 Register result,
1099 Label *L_success);
1100
1101
1102 // As above, but with a constant super_klass.
1103 // The result is in Register result, not the condition codes.
1104 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1105 Register r_super_klass,
1106 Register temp1,
1107 Register temp2,
1108 Register temp3,
1109 FloatRegister vtemp,
1110 Register result,
1111 u1 super_klass_slot,
1112 bool stub_is_near = false);
1113
1114 void verify_secondary_supers_table(Register r_sub_klass,
1115 Register r_super_klass,
1116 Register temp1,
1117 Register temp2,
1118 Register result);
1119
1120 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1121 Register r_array_base,
1122 Register r_array_index,
1123 Register r_bitmap,
1124 Register temp1,
1125 Register result,
1126 bool is_stub = true);
1127
1128 // Simplified, combined version, good for typical uses.
1129 // Falls through on failure.
1130 void check_klass_subtype(Register sub_klass,
1131 Register super_klass,
1132 Register temp_reg,
1133 Label& L_success);
1134
1135 void clinit_barrier(Register klass,
1136 Register thread,
1137 Label* L_fast_path = nullptr,
1138 Label* L_slow_path = nullptr);
1139
1140 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1141
1142 void profile_receiver_type(Register recv, Register mdp, int mdp_offset);
1143
1144 void verify_sve_vector_length(Register tmp = rscratch1);
1145 void reinitialize_ptrue() {
1146 if (UseSVE > 0) {
1147 sve_ptrue(ptrue, B);
1148 }
1149 }
1150 void verify_ptrue();
1151
1152 // Debugging
1153
1154 // only if +VerifyOops
1155 void _verify_oop(Register reg, const char* s, const char* file, int line);
1156 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1157
1158 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1159 if (VerifyOops) {
1160 _verify_oop(reg, s, file, line);
1161 }
1162 }
1163 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1164 if (VerifyOops) {
1165 _verify_oop_addr(reg, s, file, line);
1166 }
1167 }
1168
1169 // TODO: verify method and klass metadata (compare against vptr?)
1170 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1171 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1172
1173 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1174 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1175 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1176 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1177 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1178
1179 // Restore cpu control state after JNI call
1180 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1181
1182 // prints msg, dumps registers and stops execution
1183 void stop(const char* msg);
1184
1185 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1186
1187 void untested() { stop("untested"); }
1188
1189 void unimplemented(const char* what = "");
1190
1191 void should_not_reach_here() { stop("should not reach here"); }
1192
1193 void _assert_asm(Condition cc, const char* msg);
1194 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1195 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1196
1197 // Stack overflow checking
1198 void bang_stack_with_offset(int offset) {
1199 // stack grows down, caller passes positive offset
1200 assert(offset > 0, "must bang with negative offset");
1201 sub(rscratch2, sp, offset);
1202 str(zr, Address(rscratch2));
1203 }
1204
1205 // Writes to stack successive pages until offset reached to check for
1206 // stack overflow + shadow pages. Also, clobbers tmp
1207 void bang_stack_size(Register size, Register tmp);
1208
1209 // Check for reserved stack access in method being exited (for JIT)
1210 void reserved_stack_check();
1211
1212 // Arithmetics
1213
1214 // Clobber: rscratch1, rscratch2
1215 void addptr(const Address &dst, int32_t src);
1216
1217 // Clobber: rscratch1
1218 void cmpptr(Register src1, Address src2);
1219
1220 void cmpoop(Register obj1, Register obj2);
1221
1222 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1223 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1224 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1225 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1226
1227 void atomic_xchg(Register prev, Register newv, Register addr);
1228 void atomic_xchgw(Register prev, Register newv, Register addr);
1229 void atomic_xchgl(Register prev, Register newv, Register addr);
1230 void atomic_xchglw(Register prev, Register newv, Register addr);
1231 void atomic_xchgal(Register prev, Register newv, Register addr);
1232 void atomic_xchgalw(Register prev, Register newv, Register addr);
1233
1234 void orptr(Address adr, RegisterOrConstant src) {
1235 ldr(rscratch1, adr);
1236 if (src.is_register())
1237 orr(rscratch1, rscratch1, src.as_register());
1238 else
1239 orr(rscratch1, rscratch1, src.as_constant());
1240 str(rscratch1, adr);
1241 }
1242
1243 private:
1244 // A generic CAS; success or failure is in the EQ flag.
1245 // Clobbers rscratch1
1246 void cmpxchg(Register addr, Register expected, Register new_val,
1247 enum operand_size size, enum atomic_memory_order order,
1248 bool weak, Register result);
1249
1250 public:
1251 void cmpxchg(Register addr, Register expected, Register new_val,
1252 enum operand_size size, enum atomic_memory_order order,
1253 Register result = noreg) {
1254 cmpxchg(addr, expected, new_val, size, order, /* weak */ false, result);
1255 }
1256
1257 void cmpxchg_weak(Register addr, Register expected, Register new_val,
1258 enum operand_size size, enum atomic_memory_order order,
1259 Register result = noreg) {
1260 cmpxchg(addr, expected, new_val, size, order, /* weak */ true, result);
1261 }
1262
1263 #ifdef ASSERT
1264 // Template short-hand support to clean-up after a failed call to trampoline
1265 // call generation (see trampoline_call() below), when a set of Labels must
1266 // be reset (before returning).
1267 template<typename Label, typename... More>
1268 void reset_labels(Label &lbl, More&... more) {
1269 lbl.reset(); reset_labels(more...);
1270 }
1271 template<typename Label>
1272 void reset_labels(Label &lbl) {
1273 lbl.reset();
1274 }
1275 #endif
1276
1277 private:
1278 void compare_eq(Register rn, Register rm, enum operand_size size);
1279
1280 public:
1281 // AArch64 OpenJDK uses four different types of calls:
1282 // - direct call: bl pc_relative_offset
1283 // This is the shortest and the fastest, but the offset has the range:
1284 // +/-128MB for the release build, +/-2MB for the debug build.
1285 //
1286 // - far call: adrp reg, pc_relative_offset; add; bl reg
1287 // This is longer than a direct call. The offset has
1288 // the range +/-4GB. As the code cache size is limited to 4GB,
1289 // far calls can reach anywhere in the code cache. If a jump is
1290 // needed rather than a call, a far jump 'b reg' can be used instead.
1291 // All instructions are embedded at a call site.
1292 //
1293 // - trampoline call:
1294 // This is only available in C1/C2-generated code (nmethod). It is a combination
1295 // of a direct call, which is used if the destination of a call is in range,
1296 // and a register-indirect call. It has the advantages of reaching anywhere in
1297 // the AArch64 address space and being patchable at runtime when the generated
1298 // code is being executed by other threads.
1299 //
1300 // [Main code section]
1301 // bl trampoline
1302 // [Stub code section]
1303 // trampoline:
1304 // ldr reg, pc + 8
1305 // br reg
1306 // <64-bit destination address>
1307 //
1308 // If the destination is in range when the generated code is moved to the code
1309 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1310 // is not used.
1311 // The optimization does not remove the trampoline from the stub section.
1312 // This is necessary because the trampoline may well be redirected later when
1313 // code is patched, and the new destination may not be reachable by a simple BR
1314 // instruction.
1315 //
1316 // - indirect call: move reg, address; blr reg
1317 // This too can reach anywhere in the address space, but it cannot be
1318 // patched while code is running, so it must only be modified at a safepoint.
1319 // This form of call is most suitable for targets at fixed addresses, which
1320 // will never be patched.
1321 //
1322 // The patching we do conforms to the "Concurrent modification and
1323 // execution of instructions" section of the Arm Architectural
1324 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1325 // or SVC instructions to be modified while another thread is
1326 // executing them.
1327 //
1328 // To patch a trampoline call when the BL can't reach, we first modify
1329 // the 64-bit destination address in the trampoline, then modify the
1330 // BL to point to the trampoline, then flush the instruction cache to
1331 // broadcast the change to all executing threads. See
1332 // NativeCall::set_destination_mt_safe for the details.
1333 //
1334 // There is a benign race in that the other thread might observe the
1335 // modified BL before it observes the modified 64-bit destination
1336 // address. That does not matter because the destination method has been
1337 // invalidated, so there will be a trap at its start.
1338 // For this to work, the destination address in the trampoline is
1339 // always updated, even if we're not using the trampoline.
1340
1341 // Emit a direct call if the entry address will always be in range,
1342 // otherwise a trampoline call.
1343 // Supported entry.rspec():
1344 // - relocInfo::runtime_call_type
1345 // - relocInfo::opt_virtual_call_type
1346 // - relocInfo::static_call_type
1347 // - relocInfo::virtual_call_type
1348 //
1349 // Return: the call PC or null if CodeCache is full.
1350 // Clobbers: rscratch1
1351 address trampoline_call(Address entry);
1352
1353 static bool far_branches() {
1354 return ReservedCodeCacheSize > branch_range;
1355 }
1356
1357 // Check if branches to the non nmethod section require a far jump
1358 static bool codestub_branch_needs_far_jump() {
1359 if (AOTCodeCache::is_on_for_dump()) {
1360 // To calculate far_codestub_branch_size correctly.
1361 return true;
1362 }
1363 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1364 }
1365
1366 // Emit a direct call/jump if the entry address will always be in range,
1367 // otherwise a far call/jump.
1368 // The address must be inside the code cache.
1369 // Supported entry.rspec():
1370 // - relocInfo::external_word_type
1371 // - relocInfo::runtime_call_type
1372 // - relocInfo::none
1373 // In the case of a far call/jump, the entry address is put in the tmp register.
1374 // The tmp register is invalidated.
1375 //
1376 // Far_jump returns the amount of the emitted code.
1377 void far_call(Address entry, Register tmp = rscratch1);
1378 int far_jump(Address entry, Register tmp = rscratch1);
1379
1380 static int far_codestub_branch_size() {
1381 if (codestub_branch_needs_far_jump()) {
1382 return 3 * 4; // adrp, add, br
1383 } else {
1384 return 4;
1385 }
1386 }
1387
1388 // Emit the CompiledIC call idiom
1389 address ic_call(address entry, jint method_index = 0);
1390 static int ic_check_size();
1391 int ic_check(int end_alignment);
1392
1393 public:
1394
1395 // Data
1396
1397 void mov_metadata(Register dst, Metadata* obj);
1398 Address allocate_metadata_address(Metadata* obj);
1399 Address constant_oop_address(jobject obj);
1400
1401 void movoop(Register dst, jobject obj);
1402
1403 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1404 void kernel_crc32(Register crc, Register buf, Register len,
1405 Register table0, Register table1, Register table2, Register table3,
1406 Register tmp, Register tmp2, Register tmp3);
1407 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1408 void kernel_crc32c(Register crc, Register buf, Register len,
1409 Register table0, Register table1, Register table2, Register table3,
1410 Register tmp, Register tmp2, Register tmp3);
1411
1412 // Stack push and pop individual 64 bit registers
1413 void push(Register src);
1414 void pop(Register dst);
1415
1416 void repne_scan(Register addr, Register value, Register count,
1417 Register scratch);
1418 void repne_scanw(Register addr, Register value, Register count,
1419 Register scratch);
1420
1421 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1422 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1423
1424 // If a constant does not fit in an immediate field, generate some
1425 // number of MOV instructions and then perform the operation
1426 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1427 add_sub_imm_insn insn1,
1428 add_sub_reg_insn insn2, bool is32);
1429 // Separate vsn which sets the flags
1430 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1431 add_sub_imm_insn insn1,
1432 add_sub_reg_insn insn2, bool is32);
1433
1434 #define WRAP(INSN, is32) \
1435 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1436 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1437 } \
1438 \
1439 void INSN(Register Rd, Register Rn, Register Rm, \
1440 enum shift_kind kind, unsigned shift = 0) { \
1441 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1442 } \
1443 \
1444 void INSN(Register Rd, Register Rn, Register Rm) { \
1445 Assembler::INSN(Rd, Rn, Rm); \
1446 } \
1447 \
1448 void INSN(Register Rd, Register Rn, Register Rm, \
1449 ext::operation option, int amount = 0) { \
1450 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1451 }
1452
1453 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1454
1455 #undef WRAP
1456 #define WRAP(INSN, is32) \
1457 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1458 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1459 } \
1460 \
1461 void INSN(Register Rd, Register Rn, Register Rm, \
1462 enum shift_kind kind, unsigned shift = 0) { \
1463 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1464 } \
1465 \
1466 void INSN(Register Rd, Register Rn, Register Rm) { \
1467 Assembler::INSN(Rd, Rn, Rm); \
1468 } \
1469 \
1470 void INSN(Register Rd, Register Rn, Register Rm, \
1471 ext::operation option, int amount = 0) { \
1472 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1473 }
1474
1475 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1476
1477 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1478 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1479 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1480 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1481
1482 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1483
1484 void tableswitch(Register index, jint lowbound, jint highbound,
1485 Label &jumptable, Label &jumptable_end, int stride = 1) {
1486 adr(rscratch1, jumptable);
1487 subsw(rscratch2, index, lowbound);
1488 subsw(zr, rscratch2, highbound - lowbound);
1489 br(Assembler::HS, jumptable_end);
1490 add(rscratch1, rscratch1, rscratch2,
1491 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1492 br(rscratch1);
1493 }
1494
1495 // Form an address from base + offset in Rd. Rd may or may not
1496 // actually be used: you must use the Address that is returned. It
1497 // is up to you to ensure that the shift provided matches the size
1498 // of your data.
1499 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1500
1501 // Return true iff an address is within the 48-bit AArch64 address
1502 // space.
1503 bool is_valid_AArch64_address(address a) {
1504 return ((uint64_t)a >> 48) == 0;
1505 }
1506
1507 // Load the base of the cardtable byte map into reg.
1508 void load_byte_map_base(Register reg);
1509
1510 // Load a constant address in the AOT Runtime Constants area
1511 void load_aotrc_address(Register reg, address a);
1512
1513 // Prolog generator routines to support switch between x86 code and
1514 // generated ARM code
1515
1516 // routine to generate an x86 prolog for a stub function which
1517 // bootstraps into the generated ARM code which directly follows the
1518 // stub
1519 //
1520
1521 public:
1522
1523 address read_polling_page(Register r, relocInfo::relocType rtype);
1524 void get_polling_page(Register dest, relocInfo::relocType rtype);
1525
1526 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1527 void update_byte_crc32(Register crc, Register val, Register table);
1528 void update_word_crc32(Register crc, Register v, Register tmp,
1529 Register table0, Register table1, Register table2, Register table3,
1530 bool upper = false);
1531
1532 address count_positives(Register ary1, Register len, Register result);
1533
1534 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1535 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1536
1537 // Ensure that the inline code and the stub use the same registers.
1538 #define ARRAYS_HASHCODE_REGISTERS \
1539 do { \
1540 assert(result == r0 && \
1541 ary == r1 && \
1542 cnt == r2 && \
1543 vdata0 == v3 && \
1544 vdata1 == v2 && \
1545 vdata2 == v1 && \
1546 vdata3 == v0 && \
1547 vmul0 == v4 && \
1548 vmul1 == v5 && \
1549 vmul2 == v6 && \
1550 vmul3 == v7 && \
1551 vpow == v12 && \
1552 vpowm == v13, "registers must match aarch64.ad"); \
1553 } while (0)
1554
1555 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1556
1557 void fill_words(Register base, Register cnt, Register value);
1558 address zero_words(Register base, uint64_t cnt);
1559 address zero_words(Register ptr, Register cnt);
1560 void zero_dcache_blocks(Register base, Register cnt);
1561
1562 static const int zero_words_block_size;
1563
1564 address byte_array_inflate(Register src, Register dst, Register len,
1565 FloatRegister vtmp1, FloatRegister vtmp2,
1566 FloatRegister vtmp3, Register tmp4);
1567
1568 void char_array_compress(Register src, Register dst, Register len,
1569 Register res,
1570 FloatRegister vtmp0, FloatRegister vtmp1,
1571 FloatRegister vtmp2, FloatRegister vtmp3,
1572 FloatRegister vtmp4, FloatRegister vtmp5);
1573
1574 void encode_iso_array(Register src, Register dst,
1575 Register len, Register res, bool ascii,
1576 FloatRegister vtmp0, FloatRegister vtmp1,
1577 FloatRegister vtmp2, FloatRegister vtmp3,
1578 FloatRegister vtmp4, FloatRegister vtmp5);
1579
1580 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1581 address pio2, address dsin_coef, address dcos_coef);
1582 private:
1583 // begin trigonometric functions support block
1584 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1585 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1586 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1587 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1588 // end trigonometric functions support block
1589 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1590 Register src1, Register src2);
1591 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1592 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1593 }
1594 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1595 Register y, Register y_idx, Register z,
1596 Register carry, Register product,
1597 Register idx, Register kdx);
1598 void multiply_128_x_128_loop(Register y, Register z,
1599 Register carry, Register carry2,
1600 Register idx, Register jdx,
1601 Register yz_idx1, Register yz_idx2,
1602 Register tmp, Register tmp3, Register tmp4,
1603 Register tmp7, Register product_hi);
1604 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1605 Register len, Register tmp0, Register tmp1, Register tmp2,
1606 Register tmp3);
1607 void kernel_crc32_using_crc32(Register crc, Register buf,
1608 Register len, Register tmp0, Register tmp1, Register tmp2,
1609 Register tmp3);
1610 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1611 Register len, Register tmp0, Register tmp1, Register tmp2,
1612 Register tmp3);
1613 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1614 Register len, Register tmp0, Register tmp1, Register tmp2,
1615 Register tmp3);
1616 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1617 Register len, Register tmp0, Register tmp1, Register tmp2,
1618 size_t table_offset);
1619
1620 void ghash_modmul (FloatRegister result,
1621 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1622 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1623 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1624 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1625 public:
1626 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1627 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1628 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1629 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1630 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1631 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1632 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1633 void ghash_multiply_wide(int index,
1634 FloatRegister result_lo, FloatRegister result_hi,
1635 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1636 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1637 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1638 FloatRegister p, FloatRegister z, FloatRegister t1);
1639 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1640 FloatRegister p, FloatRegister z, FloatRegister t1);
1641 void ghash_processBlocks_wide(Label& p, Register state, Register subkeyH,
1642 Register data, Register blocks, int unrolls);
1643
1644
1645 void aesenc_loadkeys(Register key, Register keylen);
1646 void aesecb_encrypt(Register from, Register to, Register keylen,
1647 FloatRegister data = v0, int unrolls = 1);
1648 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1649 void aes_round(FloatRegister input, FloatRegister subkey);
1650
1651 // ChaCha20 functions support block
1652 void cc20_qr_add4(FloatRegister (&addFirst)[4],
1653 FloatRegister (&addSecond)[4]);
1654 void cc20_qr_xor4(FloatRegister (&firstElem)[4],
1655 FloatRegister (&secondElem)[4], FloatRegister (&result)[4]);
1656 void cc20_qr_lrot4(FloatRegister (&sourceReg)[4],
1657 FloatRegister (&destReg)[4], int bits, FloatRegister table);
1658 void cc20_set_qr_registers(FloatRegister (&vectorSet)[4],
1659 const FloatRegister (&stateVectors)[16], int idx1, int idx2,
1660 int idx3, int idx4);
1661
1662 // Rotate using ORR (for identity) or USHR + SLI.
1663 void neon_vector_rotate(FloatRegister dst, SIMD_Arrangement T,
1664 FloatRegister src, int shift_amount);
1665
1666 // Place an ISB after code may have been modified due to a safepoint.
1667 void safepoint_isb();
1668
1669 private:
1670 // Return the effective address r + (r1 << ext) + offset.
1671 // Uses rscratch2.
1672 Address offsetted_address(Register r, Register r1, Address::extend ext,
1673 int offset, int size);
1674
1675 private:
1676 // Returns an address on the stack which is reachable with a ldr/str of size
1677 // Uses rscratch2 if the address is not directly reachable
1678 Address spill_address(int size, int offset, Register tmp=rscratch2);
1679 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1680
1681 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1682
1683 // Check whether two loads/stores can be merged into ldp/stp.
1684 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1685
1686 // Merge current load/store with previous load/store into ldp/stp.
1687 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1688
1689 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1690 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1691
1692 public:
1693 void spill(Register Rx, bool is64, int offset) {
1694 if (is64) {
1695 str(Rx, spill_address(8, offset));
1696 } else {
1697 strw(Rx, spill_address(4, offset));
1698 }
1699 }
1700 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1701 str(Vx, T, spill_address(1 << (int)T, offset));
1702 }
1703
1704 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1705 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1706 }
1707 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1708 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1709 }
1710
1711 void unspill(Register Rx, bool is64, int offset) {
1712 if (is64) {
1713 ldr(Rx, spill_address(8, offset));
1714 } else {
1715 ldrw(Rx, spill_address(4, offset));
1716 }
1717 }
1718 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1719 ldr(Vx, T, spill_address(1 << (int)T, offset));
1720 }
1721
1722 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1723 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1724 }
1725 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1726 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1727 }
1728
1729 void spill_copy128(int src_offset, int dst_offset,
1730 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1731 if (src_offset < 512 && (src_offset & 7) == 0 &&
1732 dst_offset < 512 && (dst_offset & 7) == 0) {
1733 ldp(tmp1, tmp2, Address(sp, src_offset));
1734 stp(tmp1, tmp2, Address(sp, dst_offset));
1735 } else {
1736 unspill(tmp1, true, src_offset);
1737 spill(tmp1, true, dst_offset);
1738 unspill(tmp1, true, src_offset+8);
1739 spill(tmp1, true, dst_offset+8);
1740 }
1741 }
1742 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1743 int sve_vec_reg_size_in_bytes) {
1744 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1745 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1746 spill_copy128(src_offset, dst_offset);
1747 src_offset += 16;
1748 dst_offset += 16;
1749 }
1750 }
1751 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1752 int sve_predicate_reg_size_in_bytes) {
1753 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1754 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1755 reinitialize_ptrue();
1756 }
1757 void cache_wb(Address line);
1758 void cache_wbsync(bool is_pre);
1759
1760 // Code for java.lang.Thread::onSpinWait() intrinsic.
1761 void spin_wait();
1762 void spin_wait_wfet(int delay_ns);
1763
1764 void fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1765 void fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1766
1767 private:
1768 // Check the current thread doesn't need a cross modify fence.
1769 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1770 void try_to_replace_prev_vector_copy_with_movprfx(FloatRegister dst);
1771
1772 public:
1773 void maybe_movprfx(FloatRegister dst, FloatRegister src) {
1774 if (dst != src) {
1775 sve_movprfx(dst, src);
1776 }
1777 }
1778
1779 // Wrappers for SVE explicit destructive instructions, overriding the
1780 // same-signature Assembler entry points to enable movprfx fusion optimization.
1781 //
1782 // Implicit destructive instructions (e.g. predicated unary ops like sve_abs/
1783 // sve_neg/sve_not, whose ISA encoding allows Zd != Zn but whose use as a Java
1784 // Vector API masked operation requires pass-through of the first source) are
1785 // not covered here. For those, the .ad file is responsible for emitting
1786 // movprfx explicitly via maybe_movprfx() before the destructive op.
1787 #define SVE_DESTRUCTIVE_BINARY_INS(NAME) \
1788 using Assembler::NAME; \
1789 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, \
1790 FloatRegister Zm) { \
1791 if (Zd != Zm) { \
1792 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1793 } \
1794 Assembler::NAME(Zd, T, Pg, Zm); \
1795 }
1796
1797 #define SVE_DESTRUCTIVE_BINARY_5(I1, I2, I3, I4, I5) \
1798 SVE_DESTRUCTIVE_BINARY_INS(I1); SVE_DESTRUCTIVE_BINARY_INS(I2); \
1799 SVE_DESTRUCTIVE_BINARY_INS(I3); SVE_DESTRUCTIVE_BINARY_INS(I4); \
1800 SVE_DESTRUCTIVE_BINARY_INS(I5);
1801
1802 SVE_DESTRUCTIVE_BINARY_5(sve_add, sve_and, sve_asr, sve_bic, sve_eor)
1803 SVE_DESTRUCTIVE_BINARY_5(sve_fabd, sve_fadd, sve_fdiv, sve_fmax, sve_fmin)
1804 SVE_DESTRUCTIVE_BINARY_5(sve_fmul, sve_fsub, sve_lsl, sve_lsr, sve_mul)
1805 SVE_DESTRUCTIVE_BINARY_5(sve_orr, sve_smax, sve_smin, sve_sqadd, sve_sqsub)
1806 SVE_DESTRUCTIVE_BINARY_5(sve_sub, sve_uqadd, sve_uqsub, sve_umax, sve_umin)
1807
1808 #undef SVE_DESTRUCTIVE_BINARY_INS
1809 #undef SVE_DESTRUCTIVE_BINARY_5
1810
1811 #define SVE_DESTRUCTIVE_SHIFT_IMM_INS(NAME) \
1812 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, int shift) { \
1813 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1814 Assembler::NAME(Zd, T, Pg, shift); \
1815 }
1816
1817 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_asr);
1818 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_lsl);
1819 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_lsr);
1820
1821 #undef SVE_DESTRUCTIVE_SHIFT_IMM_INS
1822
1823 #define SVE_DESTRUCTIVE_UNPRED_IMM_INS(NAME, IMM_TYPE) \
1824 void NAME(FloatRegister Zd, SIMD_RegVariant T, IMM_TYPE imm) { \
1825 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1826 Assembler::NAME(Zd, T, imm); \
1827 }
1828
1829 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_add, unsigned);
1830 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_sub, unsigned);
1831 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_and, uint64_t);
1832 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_eor, uint64_t);
1833 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_orr, uint64_t);
1834
1835 #undef SVE_DESTRUCTIVE_UNPRED_IMM_INS
1836
1837 #define SVE_DESTRUCTIVE_TERNARY_INS(NAME) \
1838 using Assembler::NAME; \
1839 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, \
1840 FloatRegister Zn, FloatRegister Zm) { \
1841 if (Zd != Zn && Zd != Zm) { \
1842 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1843 } \
1844 Assembler::NAME(Zd, T, Pg, Zn, Zm); \
1845 }
1846
1847 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmad);
1848 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmla);
1849 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmls);
1850 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmsb);
1851 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmad);
1852 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmla);
1853 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmls);
1854 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmsb);
1855 SVE_DESTRUCTIVE_TERNARY_INS(sve_mla);
1856 SVE_DESTRUCTIVE_TERNARY_INS(sve_mls);
1857
1858 #undef SVE_DESTRUCTIVE_TERNARY_INS
1859
1860 #define SVE_DESTRUCTIVE_TERNARY_UNPRED_INS(NAME) \
1861 using Assembler::NAME; \
1862 void NAME(FloatRegister Zd, FloatRegister Zm, FloatRegister Zk) { \
1863 if (Zd != Zm && Zd != Zk) { \
1864 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1865 } \
1866 Assembler::NAME(Zd, Zm, Zk); \
1867 }
1868
1869 SVE_DESTRUCTIVE_TERNARY_UNPRED_INS(sve_bsl);
1870 SVE_DESTRUCTIVE_TERNARY_UNPRED_INS(sve_eor3);
1871
1872 #undef SVE_DESTRUCTIVE_TERNARY_UNPRED_INS
1873 };
1874
1875 #ifdef ASSERT
1876 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1877 #endif
1878
1879 struct tableswitch {
1880 Register _reg;
1881 int _insn_index; jint _first_key; jint _last_key;
1882 Label _after;
1883 Label _branches;
1884 };
1885
1886 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP