1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/globalDefinitions.hpp"
37 #include "utilities/powerOfTwo.hpp"
38
39 class OopMap;
40
41 // MacroAssembler extends Assembler by frequently used macros.
42 //
43 // Instructions for which a 'better' code sequence exists depending
44 // on arguments should also go in here.
45
46 class MacroAssembler: public Assembler {
47 friend class LIR_Assembler;
48
49 public:
50 using Assembler::mov;
51 using Assembler::movi;
52
53 protected:
54
55 // Support for VM calls
56 //
57 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 virtual void call_VM_leaf_base(
61 address entry_point, // the entry point
62 int number_of_arguments, // the number of arguments to pop after the call
63 Label *retaddr = nullptr
64 );
65
66 virtual void call_VM_leaf_base(
67 address entry_point, // the entry point
68 int number_of_arguments, // the number of arguments to pop after the call
69 Label &retaddr) {
70 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
71 }
72
73 // This is the base routine called by the different versions of call_VM. The interpreter
74 // may customize this version by overriding it for its purposes (e.g., to save/restore
75 // additional registers when doing a VM call).
76 //
77 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
78 // returns the register which contains the thread upon return. If a thread register has been
79 // specified, the return value will correspond to that register. If no last_java_sp is specified
80 // (noreg) than rsp will be used instead.
81 virtual void call_VM_base( // returns the register containing the thread upon return
82 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
83 Register java_thread, // the thread if computed before ; use noreg otherwise
84 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
85 Label* return_pc, // to set up last_Java_frame; use nullptr otherwise
86 address entry_point, // the entry point
87 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
88 bool check_exceptions // whether to check for pending exceptions after return
89 );
90
91 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
92
93 enum KlassDecodeMode {
94 KlassDecodeNone,
95 KlassDecodeZero,
96 KlassDecodeXor,
97 KlassDecodeMovk
98 };
99
100 // Calculate decoding mode based on given parameters, used for checking then ultimately setting.
101 static KlassDecodeMode klass_decode_mode(address base, int shift, const size_t range);
102
103 private:
104 static KlassDecodeMode _klass_decode_mode;
105
106 // Returns above setting with asserts
107 static KlassDecodeMode klass_decode_mode();
108
109 public:
110 // Checks the decode mode and returns false if not compatible with preferred decoding mode.
111 static bool check_klass_decode_mode(address base, int shift, const size_t range);
112
113 // Sets the decode mode and returns false if cannot be set.
114 static bool set_klass_decode_mode(address base, int shift, const size_t range);
115
116 public:
117 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
118
119 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
120 // The implementation is only non-empty for the InterpreterMacroAssembler,
121 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
122 virtual void check_and_handle_popframe(Register java_thread);
123 virtual void check_and_handle_earlyret(Register java_thread);
124
125 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp = rscratch1);
126 void rt_call(address dest, Register tmp = rscratch1);
127
128 // Load Effective Address
129 void lea(Register r, const Address &a) {
130 InstructionMark im(this);
131 a.lea(this, r);
132 }
133
134 // Whether materializing the given address for a LDR/STR requires an
135 // additional lea instruction.
136 static bool legitimize_address_requires_lea(const Address &a, int size) {
137 return a.getMode() == Address::base_plus_offset &&
138 !Address::offset_ok_for_immed(a.offset(), exact_log2(size));
139 }
140
141 /* Sometimes we get misaligned loads and stores, usually from Unsafe
142 accesses, and these can exceed the offset range. */
143 Address legitimize_address(const Address &a, int size, Register scratch) {
144 if (legitimize_address_requires_lea(a, size)) {
145 block_comment("legitimize_address {");
146 lea(scratch, a);
147 block_comment("} legitimize_address");
148 return Address(scratch);
149 }
150 return a;
151 }
152
153 void addmw(Address a, Register incr, Register scratch) {
154 ldrw(scratch, a);
155 addw(scratch, scratch, incr);
156 strw(scratch, a);
157 }
158
159 // Add constant to memory word
160 void addmw(Address a, int imm, Register scratch) {
161 ldrw(scratch, a);
162 if (imm > 0)
163 addw(scratch, scratch, (unsigned)imm);
164 else
165 subw(scratch, scratch, (unsigned)-imm);
166 strw(scratch, a);
167 }
168
169 void bind(Label& L) {
170 Assembler::bind(L);
171 code()->clear_last_merge_candidate();
172 code()->set_last_label(pc());
173 }
174
175 void membar(Membar_mask_bits order_constraint);
176
177 using Assembler::ldr;
178 using Assembler::str;
179 using Assembler::ldrw;
180 using Assembler::strw;
181
182 void ldr(Register Rx, const Address &adr);
183 void ldrw(Register Rw, const Address &adr);
184 void str(Register Rx, const Address &adr);
185 void strw(Register Rx, const Address &adr);
186
187 // Frame creation and destruction shared between JITs.
188 void build_frame(int framesize);
189 void remove_frame(int framesize);
190
191 virtual void _call_Unimplemented(address call_site) {
192 mov(rscratch2, call_site);
193 }
194
195 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
196 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
197 // https://reviews.llvm.org/D3311
198
199 #ifdef _WIN64
200 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
201 #else
202 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
203 #endif
204
205 // aliases defined in AARCH64 spec
206
207 template<class T>
208 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
209
210 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
211 inline void cmp(Register Rd, unsigned imm) = delete;
212
213 template<class T>
214 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
215
216 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
217 inline void cmn(Register Rd, unsigned imm) = delete;
218
219 void cset(Register Rd, Assembler::Condition cond) {
220 csinc(Rd, zr, zr, ~cond);
221 }
222 void csetw(Register Rd, Assembler::Condition cond) {
223 csincw(Rd, zr, zr, ~cond);
224 }
225
226 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
227 csneg(Rd, Rn, Rn, ~cond);
228 }
229 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
230 csnegw(Rd, Rn, Rn, ~cond);
231 }
232
233 inline void movw(Register Rd, Register Rn) {
234 if (Rd == sp || Rn == sp) {
235 Assembler::addw(Rd, Rn, 0U);
236 } else {
237 orrw(Rd, zr, Rn);
238 }
239 }
240 inline void mov(Register Rd, Register Rn) {
241 assert(Rd != r31_sp && Rn != r31_sp, "should be");
242 if (Rd == Rn) {
243 } else if (Rd == sp || Rn == sp) {
244 Assembler::add(Rd, Rn, 0U);
245 } else {
246 orr(Rd, zr, Rn);
247 }
248 }
249
250 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
251 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
252
253 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
254 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
255
256 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
257 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
258
259 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
260 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
261 }
262 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
263 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
264 }
265
266 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
267 bfmw(Rd, Rn, lsb, (lsb + width - 1));
268 }
269 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
270 bfm(Rd, Rn, lsb , (lsb + width - 1));
271 }
272
273 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
274 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
275 }
276 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
277 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
278 }
279
280 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
281 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
282 }
283 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
284 sbfm(Rd, Rn, lsb , (lsb + width - 1));
285 }
286
287 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
288 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
289 }
290 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
291 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
292 }
293
294 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
295 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
296 }
297 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
298 ubfm(Rd, Rn, lsb , (lsb + width - 1));
299 }
300
301 inline void asrw(Register Rd, Register Rn, unsigned imm) {
302 sbfmw(Rd, Rn, imm, 31);
303 }
304
305 inline void asr(Register Rd, Register Rn, unsigned imm) {
306 sbfm(Rd, Rn, imm, 63);
307 }
308
309 inline void lslw(Register Rd, Register Rn, unsigned imm) {
310 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
311 }
312
313 inline void lsl(Register Rd, Register Rn, unsigned imm) {
314 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
315 }
316
317 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
318 ubfmw(Rd, Rn, imm, 31);
319 }
320
321 inline void lsr(Register Rd, Register Rn, unsigned imm) {
322 ubfm(Rd, Rn, imm, 63);
323 }
324
325 inline void rorw(Register Rd, Register Rn, unsigned imm) {
326 extrw(Rd, Rn, Rn, imm);
327 }
328
329 inline void ror(Register Rd, Register Rn, unsigned imm) {
330 extr(Rd, Rn, Rn, imm);
331 }
332
333 inline void rolw(Register Rd, Register Rn, unsigned imm) {
334 extrw(Rd, Rn, Rn, (32 - imm));
335 }
336
337 inline void rol(Register Rd, Register Rn, unsigned imm) {
338 extr(Rd, Rn, Rn, (64 - imm));
339 }
340
341 using Assembler::rax1;
342 using Assembler::eor3;
343
344 inline void rax1(Register Rd, Register Rn, Register Rm) {
345 eor(Rd, Rn, Rm, ROR, 63); // Rd = Rn ^ rol(Rm, 1)
346 }
347
348 inline void eor3(Register Rd, Register Rn, Register Rm, Register Rk) {
349 assert(Rd != Rn, "Use tmp register");
350 eor(Rd, Rm, Rk);
351 eor(Rd, Rd, Rn);
352 }
353
354 inline void sxtbw(Register Rd, Register Rn) {
355 sbfmw(Rd, Rn, 0, 7);
356 }
357 inline void sxthw(Register Rd, Register Rn) {
358 sbfmw(Rd, Rn, 0, 15);
359 }
360 inline void sxtb(Register Rd, Register Rn) {
361 sbfm(Rd, Rn, 0, 7);
362 }
363 inline void sxth(Register Rd, Register Rn) {
364 sbfm(Rd, Rn, 0, 15);
365 }
366 inline void sxtw(Register Rd, Register Rn) {
367 sbfm(Rd, Rn, 0, 31);
368 }
369
370 inline void uxtbw(Register Rd, Register Rn) {
371 ubfmw(Rd, Rn, 0, 7);
372 }
373 inline void uxthw(Register Rd, Register Rn) {
374 ubfmw(Rd, Rn, 0, 15);
375 }
376 inline void uxtb(Register Rd, Register Rn) {
377 ubfm(Rd, Rn, 0, 7);
378 }
379 inline void uxth(Register Rd, Register Rn) {
380 ubfm(Rd, Rn, 0, 15);
381 }
382 inline void uxtw(Register Rd, Register Rn) {
383 ubfm(Rd, Rn, 0, 31);
384 }
385
386 inline void cmnw(Register Rn, Register Rm) {
387 addsw(zr, Rn, Rm);
388 }
389 inline void cmn(Register Rn, Register Rm) {
390 adds(zr, Rn, Rm);
391 }
392
393 inline void cmpw(Register Rn, Register Rm) {
394 subsw(zr, Rn, Rm);
395 }
396 inline void cmp(Register Rn, Register Rm) {
397 subs(zr, Rn, Rm);
398 }
399
400 inline void negw(Register Rd, Register Rn) {
401 subw(Rd, zr, Rn);
402 }
403
404 inline void neg(Register Rd, Register Rn) {
405 sub(Rd, zr, Rn);
406 }
407
408 inline void negsw(Register Rd, Register Rn) {
409 subsw(Rd, zr, Rn);
410 }
411
412 inline void negs(Register Rd, Register Rn) {
413 subs(Rd, zr, Rn);
414 }
415
416 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
417 addsw(zr, Rn, Rm, kind, shift);
418 }
419 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
420 adds(zr, Rn, Rm, kind, shift);
421 }
422
423 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
424 subsw(zr, Rn, Rm, kind, shift);
425 }
426 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
427 subs(zr, Rn, Rm, kind, shift);
428 }
429
430 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
431 subw(Rd, zr, Rn, kind, shift);
432 }
433
434 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
435 sub(Rd, zr, Rn, kind, shift);
436 }
437
438 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
439 subsw(Rd, zr, Rn, kind, shift);
440 }
441
442 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
443 subs(Rd, zr, Rn, kind, shift);
444 }
445
446 inline void mnegw(Register Rd, Register Rn, Register Rm) {
447 msubw(Rd, Rn, Rm, zr);
448 }
449 inline void mneg(Register Rd, Register Rn, Register Rm) {
450 msub(Rd, Rn, Rm, zr);
451 }
452
453 inline void mulw(Register Rd, Register Rn, Register Rm) {
454 maddw(Rd, Rn, Rm, zr);
455 }
456 inline void mul(Register Rd, Register Rn, Register Rm) {
457 madd(Rd, Rn, Rm, zr);
458 }
459
460 inline void smnegl(Register Rd, Register Rn, Register Rm) {
461 smsubl(Rd, Rn, Rm, zr);
462 }
463 inline void smull(Register Rd, Register Rn, Register Rm) {
464 smaddl(Rd, Rn, Rm, zr);
465 }
466
467 inline void umnegl(Register Rd, Register Rn, Register Rm) {
468 umsubl(Rd, Rn, Rm, zr);
469 }
470 inline void umull(Register Rd, Register Rn, Register Rm) {
471 umaddl(Rd, Rn, Rm, zr);
472 }
473
474 #define WRAP(INSN) \
475 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
476 if (VM_Version::supports_a53mac() && Ra != zr) \
477 nop(); \
478 Assembler::INSN(Rd, Rn, Rm, Ra); \
479 }
480
481 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
482 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
483 #undef WRAP
484
485
486 // macro assembly operations needed for aarch64
487
488 public:
489
490 enum FpPushPopMode {
491 PushPopFull,
492 PushPopSVE,
493 PushPopNeon,
494 PushPopFp
495 };
496
497 // first two private routines for loading 32 bit or 64 bit constants
498 private:
499
500 void mov_immediate64(Register dst, uint64_t imm64);
501 void mov_immediate32(Register dst, uint32_t imm32);
502
503 void mov(Register dst, Address a);
504
505 public:
506
507 int push(RegSet regset, Register stack);
508 int pop(RegSet regset, Register stack);
509
510 int push_fp(FloatRegSet regset, Register stack, FpPushPopMode mode = PushPopFull);
511 int pop_fp(FloatRegSet regset, Register stack, FpPushPopMode mode = PushPopFull);
512
513 static RegSet call_clobbered_gp_registers();
514
515 int push_p(PRegSet regset, Register stack);
516 int pop_p(PRegSet regset, Register stack);
517
518 // Push and pop everything that might be clobbered by a native
519 // runtime call except rscratch1 and rscratch2. (They are always
520 // scratch, so we don't have to protect them.) Only save the lower
521 // 64 bits of each vector register. Additional registers can be excluded
522 // in a passed RegSet.
523 void push_call_clobbered_registers_except(RegSet exclude);
524 void pop_call_clobbered_registers_except(RegSet exclude);
525
526 void push_call_clobbered_registers() {
527 push_call_clobbered_registers_except(RegSet());
528 }
529 void pop_call_clobbered_registers() {
530 pop_call_clobbered_registers_except(RegSet());
531 }
532
533
534 // now mov instructions for loading absolute addresses and 32 or
535 // 64 bit integers
536
537 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
538
539 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
540 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
541
542 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
543
544 void mov(Register dst, RegisterOrConstant src) {
545 if (src.is_register())
546 mov(dst, src.as_register());
547 else
548 mov(dst, src.as_constant());
549 }
550
551 void movptr(Register r, uintptr_t imm64);
552
553 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
554
555 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
556 orr(Vd, T, Vn, Vn);
557 }
558
559 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
560 fcvtsh(tmp, src);
561 smov(dst, tmp, H, 0);
562 }
563
564 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
565 mov(tmp, H, 0, src);
566 fcvths(dst, tmp);
567 }
568
569 // Generalized Test Bit And Branch, including a "far" variety which
570 // spans more than 32KiB.
571 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
572 assert(cond == EQ || cond == NE, "must be");
573
574 if (isfar)
575 cond = ~cond;
576
577 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
578 if (cond == Assembler::EQ)
579 branch = &Assembler::tbz;
580 else
581 branch = &Assembler::tbnz;
582
583 if (isfar) {
584 Label L;
585 (this->*branch)(Rt, bitpos, L);
586 b(dest);
587 bind(L);
588 } else {
589 (this->*branch)(Rt, bitpos, dest);
590 }
591 }
592
593 // macro instructions for accessing and updating floating point
594 // status register
595 //
596 // FPSR : op1 == 011
597 // CRn == 0100
598 // CRm == 0100
599 // op2 == 001
600
601 inline void get_fpsr(Register reg)
602 {
603 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
604 }
605
606 inline void set_fpsr(Register reg)
607 {
608 msr(0b011, 0b0100, 0b0100, 0b001, reg);
609 }
610
611 inline void clear_fpsr()
612 {
613 msr(0b011, 0b0100, 0b0100, 0b001, zr);
614 }
615
616 // FPCR : op1 == 011
617 // CRn == 0100
618 // CRm == 0100
619 // op2 == 000
620
621 inline void get_fpcr(Register reg) {
622 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
623 }
624
625 inline void set_fpcr(Register reg) {
626 msr(0b011, 0b0100, 0b0100, 0b000, reg);
627 }
628
629 // DCZID_EL0: op1 == 011
630 // CRn == 0000
631 // CRm == 0000
632 // op2 == 111
633 inline void get_dczid_el0(Register reg)
634 {
635 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
636 }
637
638 // CTR_EL0: op1 == 011
639 // CRn == 0000
640 // CRm == 0000
641 // op2 == 001
642 inline void get_ctr_el0(Register reg)
643 {
644 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
645 }
646
647 inline void get_nzcv(Register reg) {
648 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
649 }
650
651 inline void set_nzcv(Register reg) {
652 msr(0b011, 0b0100, 0b0010, 0b000, reg);
653 }
654
655 // CNTVCTSS_EL0: op1 == 011
656 // CRn == 1110
657 // CRm == 0000
658 // op2 == 110
659 inline void get_cntvctss_el0(Register reg) {
660 mrs(0b011, 0b1110, 0b0000, 0b110, reg);
661 }
662
663 // idiv variant which deals with MINLONG as dividend and -1 as divisor
664 int corrected_idivl(Register result, Register ra, Register rb,
665 bool want_remainder, Register tmp = rscratch1);
666 int corrected_idivq(Register result, Register ra, Register rb,
667 bool want_remainder, Register tmp = rscratch1);
668
669 // Support for null-checks
670 //
671 // Generates code that causes a null OS exception if the content of reg is null.
672 // If the accessed location is M[reg + offset] and the offset is known, provide the
673 // offset. No explicit code generation is needed if the offset is within a certain
674 // range (0 <= offset <= page_size).
675
676 virtual void null_check(Register reg, int offset = -1);
677 static bool needs_explicit_null_check(intptr_t offset);
678 static bool uses_implicit_null_check(void* address);
679
680 static address target_addr_for_insn(address insn_addr);
681
682 // Required platform-specific helpers for Label::patch_instructions.
683 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
684 static int pd_patch_instruction_size(address branch, address target);
685 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
686 pd_patch_instruction_size(branch, target);
687 }
688 static address pd_call_destination(address branch) {
689 return target_addr_for_insn(branch);
690 }
691 #ifndef PRODUCT
692 static void pd_print_patched_instruction(address branch);
693 #endif
694
695 static int patch_oop(address insn_addr, address o);
696
697 // Return whether code is emitted to a scratch blob.
698 virtual bool in_scratch_emit_size() {
699 return false;
700 }
701 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
702 static int max_trampoline_stub_size();
703 void emit_static_call_stub();
704 static int static_call_stub_size();
705
706 // The following 4 methods return the offset of the appropriate move instruction
707
708 // Support for fast byte/short loading with zero extension (depending on particular CPU)
709 int load_unsigned_byte(Register dst, Address src);
710 int load_unsigned_short(Register dst, Address src);
711
712 // Support for fast byte/short loading with sign extension (depending on particular CPU)
713 int load_signed_byte(Register dst, Address src);
714 int load_signed_short(Register dst, Address src);
715
716 int load_signed_byte32(Register dst, Address src);
717 int load_signed_short32(Register dst, Address src);
718
719 // Support for sign-extension (hi:lo = extend_sign(lo))
720 void extend_sign(Register hi, Register lo);
721
722 // Clean up a subword typed value to the representation in compliance with JVMS ยง2.3
723 void narrow_subword_type(Register reg, BasicType bt);
724
725 // Load and store values by size and signed-ness
726 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
727 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
728
729 // Support for inc/dec with optimal instruction selection depending on value
730
731 // x86_64 aliases an unqualified register/address increment and
732 // decrement to call incrementq and decrementq but also supports
733 // explicitly sized calls to incrementq/decrementq or
734 // incrementl/decrementl
735
736 // for aarch64 the proper convention would be to use
737 // increment/decrement for 64 bit operations and
738 // incrementw/decrementw for 32 bit operations. so when porting
739 // x86_64 code we can leave calls to increment/decrement as is,
740 // replace incrementq/decrementq with increment/decrement and
741 // replace incrementl/decrementl with incrementw/decrementw.
742
743 // n.b. increment/decrement calls with an Address destination will
744 // need to use a scratch register to load the value to be
745 // incremented. increment/decrement calls which add or subtract a
746 // constant value greater than 2^12 will need to use a 2nd scratch
747 // register to hold the constant. so, a register increment/decrement
748 // may trash rscratch2 and an address increment/decrement trash
749 // rscratch and rscratch2
750
751 void decrementw(Address dst, int value = 1);
752 void decrementw(Register reg, int value = 1);
753
754 void decrement(Register reg, int value = 1);
755 void decrement(Address dst, int value = 1);
756
757 void incrementw(Address dst, int value = 1);
758 void incrementw(Register reg, int value = 1);
759
760 void increment(Register reg, int value = 1);
761 void increment(Address dst, int value = 1);
762
763
764 // Alignment
765 void align(int modulus);
766 void align(int modulus, int target);
767
768 // nop
769 void post_call_nop();
770
771 // Stack frame creation/removal
772 void enter(bool strip_ret_addr = false);
773 void leave();
774
775 // ROP Protection
776 void protect_return_address();
777 void protect_return_address(Register return_reg);
778 void authenticate_return_address();
779 void authenticate_return_address(Register return_reg);
780 void strip_return_address();
781 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
782
783 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
784 // The pointer will be loaded into the thread register.
785 void get_thread(Register thread);
786
787 // support for argument shuffling
788 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
789 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
790 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
791 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
792 void object_move(
793 OopMap* map,
794 int oop_handle_offset,
795 int framesize_in_slots,
796 VMRegPair src,
797 VMRegPair dst,
798 bool is_receiver,
799 int* receiver_offset);
800
801
802 // Support for VM calls
803 //
804 // It is imperative that all calls into the VM are handled via the call_VM macros.
805 // They make sure that the stack linkage is setup correctly. call_VM's correspond
806 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
807
808
809 void call_VM(Register oop_result,
810 address entry_point,
811 bool check_exceptions = true);
812 void call_VM(Register oop_result,
813 address entry_point,
814 Register arg_1,
815 bool check_exceptions = true);
816 void call_VM(Register oop_result,
817 address entry_point,
818 Register arg_1, Register arg_2,
819 bool check_exceptions = true);
820 void call_VM(Register oop_result,
821 address entry_point,
822 Register arg_1, Register arg_2, Register arg_3,
823 bool check_exceptions = true);
824
825 // Overloadings with last_Java_sp
826 void call_VM(Register oop_result,
827 Register last_java_sp,
828 address entry_point,
829 int number_of_arguments = 0,
830 bool check_exceptions = true);
831 void call_VM(Register oop_result,
832 Register last_java_sp,
833 address entry_point,
834 Register arg_1, bool
835 check_exceptions = true);
836 void call_VM(Register oop_result,
837 Register last_java_sp,
838 address entry_point,
839 Register arg_1, Register arg_2,
840 bool check_exceptions = true);
841 void call_VM(Register oop_result,
842 Register last_java_sp,
843 address entry_point,
844 Register arg_1, Register arg_2, Register arg_3,
845 bool check_exceptions = true);
846
847 void get_vm_result_oop(Register oop_result, Register thread);
848 void get_vm_result_metadata(Register metadata_result, Register thread);
849
850 // These always tightly bind to MacroAssembler::call_VM_base
851 // bypassing the virtual implementation
852 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
853 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
854 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
855 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
856 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
857
858 void call_VM_leaf(address entry_point,
859 int number_of_arguments = 0);
860 void call_VM_leaf(address entry_point,
861 Register arg_1);
862 void call_VM_leaf(address entry_point,
863 Register arg_1, Register arg_2);
864 void call_VM_leaf(address entry_point,
865 Register arg_1, Register arg_2, Register arg_3);
866
867 // These always tightly bind to MacroAssembler::call_VM_leaf_base
868 // bypassing the virtual implementation
869 void super_call_VM_leaf(address entry_point);
870 void super_call_VM_leaf(address entry_point, Register arg_1);
871 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
872 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
873 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
874
875 // last Java Frame (fills frame anchor)
876 void set_last_Java_frame(Register last_java_sp,
877 Register last_java_fp,
878 address last_java_pc,
879 Register scratch);
880
881 void set_last_Java_frame(Register last_java_sp,
882 Register last_java_fp,
883 Label &last_java_pc,
884 Register scratch);
885
886 void set_last_Java_frame(Register last_java_sp,
887 Register last_java_fp,
888 Register last_java_pc,
889 Register scratch);
890
891 void reset_last_Java_frame(Register thread);
892
893 // thread in the default location (rthread)
894 void reset_last_Java_frame(bool clear_fp);
895
896 void resolve_jobject(Register value, Register tmp1, Register tmp2);
897 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
898
899 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
900 void c2bool(Register x);
901
902 void load_method_holder_cld(Register rresult, Register rmethod);
903 void load_method_holder(Register holder, Register method);
904
905 // oop manipulations
906 void load_narrow_klass_compact(Register dst, Register src);
907 void load_klass(Register dst, Register src);
908 void store_klass(Register dst, Register src);
909 void cmp_klass(Register obj, Register klass, Register tmp);
910 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
911
912 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
913 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
914 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
915
916 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
917 Register tmp1, Register tmp2);
918
919 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
920 Register tmp1, Register tmp2, Register tmp3);
921
922 void load_heap_oop(Register dst, Address src, Register tmp1,
923 Register tmp2, DecoratorSet decorators = 0);
924
925 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
926 Register tmp2, DecoratorSet decorators = 0);
927 void store_heap_oop(Address dst, Register val, Register tmp1,
928 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
929
930 // currently unimplemented
931 // Used for storing null. All other oop constants should be
932 // stored using routines that take a jobject.
933 void store_heap_oop_null(Address dst);
934
935 void store_klass_gap(Register dst, Register src);
936
937 // This dummy is to prevent a call to store_heap_oop from
938 // converting a zero (like null) into a Register by giving
939 // the compiler two choices it can't resolve
940
941 void store_heap_oop(Address dst, void* dummy);
942
943 void encode_heap_oop(Register d, Register s);
944 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
945 void decode_heap_oop(Register d, Register s);
946 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
947 void encode_heap_oop_not_null(Register r);
948 void decode_heap_oop_not_null(Register r);
949 void encode_heap_oop_not_null(Register dst, Register src);
950 void decode_heap_oop_not_null(Register dst, Register src);
951
952 void set_narrow_oop(Register dst, jobject obj);
953
954 void decode_klass_not_null_for_aot(Register dst, Register src);
955 void encode_klass_not_null_for_aot(Register dst, Register src);
956 void encode_klass_not_null(Register r);
957 void decode_klass_not_null(Register r);
958 void encode_klass_not_null(Register dst, Register src);
959 void decode_klass_not_null(Register dst, Register src);
960
961 void set_narrow_klass(Register dst, Klass* k);
962
963 // if heap base register is used - reinit it with the correct value
964 void reinit_heapbase();
965
966 DEBUG_ONLY(void verify_heapbase(const char* msg);)
967
968 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
969 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
970 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
971 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
972
973 void push_cont_fastpath(Register java_thread = rthread);
974 void pop_cont_fastpath(Register java_thread = rthread);
975
976 // Round up to a power of two
977 void round_to(Register reg, int modulus);
978
979 // java.lang.Math::round intrinsics
980 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
981 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
982
983 // allocation
984 void tlab_allocate(
985 Register obj, // result: pointer to object after successful allocation
986 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
987 int con_size_in_bytes, // object size in bytes if known at compile time
988 Register t1, // temp register
989 Register t2, // temp register
990 Label& slow_case // continuation point if fast allocation fails
991 );
992 void verify_tlab();
993
994 // interface method calling
995 void lookup_interface_method(Register recv_klass,
996 Register intf_klass,
997 RegisterOrConstant itable_index,
998 Register method_result,
999 Register scan_temp,
1000 Label& no_such_interface,
1001 bool return_method = true);
1002
1003 void lookup_interface_method_stub(Register recv_klass,
1004 Register holder_klass,
1005 Register resolved_klass,
1006 Register method_result,
1007 Register temp_reg,
1008 Register temp_reg2,
1009 int itable_index,
1010 Label& L_no_such_interface);
1011
1012 // virtual method calling
1013 // n.b. x86 allows RegisterOrConstant for vtable_index
1014 void lookup_virtual_method(Register recv_klass,
1015 RegisterOrConstant vtable_index,
1016 Register method_result);
1017
1018 // Test sub_klass against super_klass, with fast and slow paths.
1019
1020 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1021 // One of the three labels can be null, meaning take the fall-through.
1022 // If super_check_offset is -1, the value is loaded up from super_klass.
1023 // No registers are killed, except temp_reg.
1024 void check_klass_subtype_fast_path(Register sub_klass,
1025 Register super_klass,
1026 Register temp_reg,
1027 Label* L_success,
1028 Label* L_failure,
1029 Label* L_slow_path,
1030 Register super_check_offset = noreg);
1031
1032 // The rest of the type check; must be wired to a corresponding fast path.
1033 // It does not repeat the fast path logic, so don't use it standalone.
1034 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1035 // Updates the sub's secondary super cache as necessary.
1036 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1037 void check_klass_subtype_slow_path(Register sub_klass,
1038 Register super_klass,
1039 Register temp_reg,
1040 Register temp2_reg,
1041 Label* L_success,
1042 Label* L_failure,
1043 bool set_cond_codes = false);
1044
1045 void check_klass_subtype_slow_path_linear(Register sub_klass,
1046 Register super_klass,
1047 Register temp_reg,
1048 Register temp2_reg,
1049 Label* L_success,
1050 Label* L_failure,
1051 bool set_cond_codes = false);
1052
1053 void check_klass_subtype_slow_path_table(Register sub_klass,
1054 Register super_klass,
1055 Register temp_reg,
1056 Register temp2_reg,
1057 Register temp3_reg,
1058 Register result_reg,
1059 FloatRegister vtemp_reg,
1060 Label* L_success,
1061 Label* L_failure,
1062 bool set_cond_codes = false);
1063
1064 // If r is valid, return r.
1065 // If r is invalid, remove a register r2 from available_regs, add r2
1066 // to regs_to_push, then return r2.
1067 Register allocate_if_noreg(const Register r,
1068 RegSetIterator<Register> &available_regs,
1069 RegSet ®s_to_push);
1070
1071 // Secondary subtype checking
1072 void lookup_secondary_supers_table_var(Register sub_klass,
1073 Register r_super_klass,
1074 Register temp1,
1075 Register temp2,
1076 Register temp3,
1077 FloatRegister vtemp,
1078 Register result,
1079 Label *L_success);
1080
1081
1082 // As above, but with a constant super_klass.
1083 // The result is in Register result, not the condition codes.
1084 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1085 Register r_super_klass,
1086 Register temp1,
1087 Register temp2,
1088 Register temp3,
1089 FloatRegister vtemp,
1090 Register result,
1091 u1 super_klass_slot,
1092 bool stub_is_near = false);
1093
1094 void verify_secondary_supers_table(Register r_sub_klass,
1095 Register r_super_klass,
1096 Register temp1,
1097 Register temp2,
1098 Register result);
1099
1100 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1101 Register r_array_base,
1102 Register r_array_index,
1103 Register r_bitmap,
1104 Register temp1,
1105 Register result,
1106 bool is_stub = true);
1107
1108 // Simplified, combined version, good for typical uses.
1109 // Falls through on failure.
1110 void check_klass_subtype(Register sub_klass,
1111 Register super_klass,
1112 Register temp_reg,
1113 Label& L_success);
1114
1115 void clinit_barrier(Register klass,
1116 Register thread,
1117 Label* L_fast_path = nullptr,
1118 Label* L_slow_path = nullptr);
1119
1120 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1121
1122 void profile_receiver_type(Register recv, Register mdp, int mdp_offset);
1123
1124 void verify_sve_vector_length(Register tmp = rscratch1);
1125 void reinitialize_ptrue() {
1126 if (UseSVE > 0) {
1127 sve_ptrue(ptrue, B);
1128 }
1129 }
1130 void verify_ptrue();
1131
1132 // Debugging
1133
1134 // only if +VerifyOops
1135 void _verify_oop(Register reg, const char* s, const char* file, int line);
1136 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1137
1138 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1139 if (VerifyOops) {
1140 _verify_oop(reg, s, file, line);
1141 }
1142 }
1143 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1144 if (VerifyOops) {
1145 _verify_oop_addr(reg, s, file, line);
1146 }
1147 }
1148
1149 // TODO: verify method and klass metadata (compare against vptr?)
1150 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1151 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1152
1153 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1154 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1155 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1156 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1157 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1158
1159 // Restore cpu control state after JNI call
1160 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1161
1162 // prints msg, dumps registers and stops execution
1163 void stop(const char* msg);
1164
1165 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1166
1167 void untested() { stop("untested"); }
1168
1169 void unimplemented(const char* what = "");
1170
1171 void should_not_reach_here() { stop("should not reach here"); }
1172
1173 void _assert_asm(Condition cc, const char* msg);
1174 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1175 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1176
1177 // Stack overflow checking
1178 void bang_stack_with_offset(int offset) {
1179 // stack grows down, caller passes positive offset
1180 assert(offset > 0, "must bang with negative offset");
1181 sub(rscratch2, sp, offset);
1182 str(zr, Address(rscratch2));
1183 }
1184
1185 // Writes to stack successive pages until offset reached to check for
1186 // stack overflow + shadow pages. Also, clobbers tmp
1187 void bang_stack_size(Register size, Register tmp);
1188
1189 // Check for reserved stack access in method being exited (for JIT)
1190 void reserved_stack_check();
1191
1192 // Arithmetics
1193
1194 // Clobber: rscratch1, rscratch2
1195 void addptr(const Address &dst, int32_t src);
1196
1197 // Clobber: rscratch1
1198 void cmpptr(Register src1, Address src2);
1199
1200 void cmpoop(Register obj1, Register obj2);
1201
1202 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1203 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1204 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1205 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1206
1207 void atomic_xchg(Register prev, Register newv, Register addr);
1208 void atomic_xchgw(Register prev, Register newv, Register addr);
1209 void atomic_xchgl(Register prev, Register newv, Register addr);
1210 void atomic_xchglw(Register prev, Register newv, Register addr);
1211 void atomic_xchgal(Register prev, Register newv, Register addr);
1212 void atomic_xchgalw(Register prev, Register newv, Register addr);
1213
1214 void orptr(Address adr, RegisterOrConstant src) {
1215 ldr(rscratch1, adr);
1216 if (src.is_register())
1217 orr(rscratch1, rscratch1, src.as_register());
1218 else
1219 orr(rscratch1, rscratch1, src.as_constant());
1220 str(rscratch1, adr);
1221 }
1222
1223 // A generic CAS; success or failure is in the EQ flag.
1224 // Clobbers rscratch1
1225 void cmpxchg(Register addr, Register expected, Register new_val,
1226 enum operand_size size,
1227 bool acquire, bool release, bool weak,
1228 Register result);
1229
1230 #ifdef ASSERT
1231 // Template short-hand support to clean-up after a failed call to trampoline
1232 // call generation (see trampoline_call() below), when a set of Labels must
1233 // be reset (before returning).
1234 template<typename Label, typename... More>
1235 void reset_labels(Label &lbl, More&... more) {
1236 lbl.reset(); reset_labels(more...);
1237 }
1238 template<typename Label>
1239 void reset_labels(Label &lbl) {
1240 lbl.reset();
1241 }
1242 #endif
1243
1244 private:
1245 void compare_eq(Register rn, Register rm, enum operand_size size);
1246
1247 public:
1248 // AArch64 OpenJDK uses four different types of calls:
1249 // - direct call: bl pc_relative_offset
1250 // This is the shortest and the fastest, but the offset has the range:
1251 // +/-128MB for the release build, +/-2MB for the debug build.
1252 //
1253 // - far call: adrp reg, pc_relative_offset; add; bl reg
1254 // This is longer than a direct call. The offset has
1255 // the range +/-4GB. As the code cache size is limited to 4GB,
1256 // far calls can reach anywhere in the code cache. If a jump is
1257 // needed rather than a call, a far jump 'b reg' can be used instead.
1258 // All instructions are embedded at a call site.
1259 //
1260 // - trampoline call:
1261 // This is only available in C1/C2-generated code (nmethod). It is a combination
1262 // of a direct call, which is used if the destination of a call is in range,
1263 // and a register-indirect call. It has the advantages of reaching anywhere in
1264 // the AArch64 address space and being patchable at runtime when the generated
1265 // code is being executed by other threads.
1266 //
1267 // [Main code section]
1268 // bl trampoline
1269 // [Stub code section]
1270 // trampoline:
1271 // ldr reg, pc + 8
1272 // br reg
1273 // <64-bit destination address>
1274 //
1275 // If the destination is in range when the generated code is moved to the code
1276 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1277 // is not used.
1278 // The optimization does not remove the trampoline from the stub section.
1279 // This is necessary because the trampoline may well be redirected later when
1280 // code is patched, and the new destination may not be reachable by a simple BR
1281 // instruction.
1282 //
1283 // - indirect call: move reg, address; blr reg
1284 // This too can reach anywhere in the address space, but it cannot be
1285 // patched while code is running, so it must only be modified at a safepoint.
1286 // This form of call is most suitable for targets at fixed addresses, which
1287 // will never be patched.
1288 //
1289 // The patching we do conforms to the "Concurrent modification and
1290 // execution of instructions" section of the Arm Architectural
1291 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1292 // or SVC instructions to be modified while another thread is
1293 // executing them.
1294 //
1295 // To patch a trampoline call when the BL can't reach, we first modify
1296 // the 64-bit destination address in the trampoline, then modify the
1297 // BL to point to the trampoline, then flush the instruction cache to
1298 // broadcast the change to all executing threads. See
1299 // NativeCall::set_destination_mt_safe for the details.
1300 //
1301 // There is a benign race in that the other thread might observe the
1302 // modified BL before it observes the modified 64-bit destination
1303 // address. That does not matter because the destination method has been
1304 // invalidated, so there will be a trap at its start.
1305 // For this to work, the destination address in the trampoline is
1306 // always updated, even if we're not using the trampoline.
1307
1308 // Emit a direct call if the entry address will always be in range,
1309 // otherwise a trampoline call.
1310 // Supported entry.rspec():
1311 // - relocInfo::runtime_call_type
1312 // - relocInfo::opt_virtual_call_type
1313 // - relocInfo::static_call_type
1314 // - relocInfo::virtual_call_type
1315 //
1316 // Return: the call PC or null if CodeCache is full.
1317 // Clobbers: rscratch1
1318 address trampoline_call(Address entry);
1319
1320 static bool far_branches() {
1321 return ReservedCodeCacheSize > branch_range;
1322 }
1323
1324 // Check if branches to the non nmethod section require a far jump
1325 static bool codestub_branch_needs_far_jump() {
1326 if (AOTCodeCache::is_on_for_dump()) {
1327 // To calculate far_codestub_branch_size correctly.
1328 return true;
1329 }
1330 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1331 }
1332
1333 // Emit a direct call/jump if the entry address will always be in range,
1334 // otherwise a far call/jump.
1335 // The address must be inside the code cache.
1336 // Supported entry.rspec():
1337 // - relocInfo::external_word_type
1338 // - relocInfo::runtime_call_type
1339 // - relocInfo::none
1340 // In the case of a far call/jump, the entry address is put in the tmp register.
1341 // The tmp register is invalidated.
1342 //
1343 // Far_jump returns the amount of the emitted code.
1344 void far_call(Address entry, Register tmp = rscratch1);
1345 int far_jump(Address entry, Register tmp = rscratch1);
1346
1347 static int far_codestub_branch_size() {
1348 if (codestub_branch_needs_far_jump()) {
1349 return 3 * 4; // adrp, add, br
1350 } else {
1351 return 4;
1352 }
1353 }
1354
1355 // Emit the CompiledIC call idiom
1356 address ic_call(address entry, jint method_index = 0);
1357 static int ic_check_size();
1358 int ic_check(int end_alignment);
1359
1360 public:
1361
1362 // Data
1363
1364 void mov_metadata(Register dst, Metadata* obj);
1365 Address allocate_metadata_address(Metadata* obj);
1366 Address constant_oop_address(jobject obj);
1367
1368 void movoop(Register dst, jobject obj);
1369
1370 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1371 void kernel_crc32(Register crc, Register buf, Register len,
1372 Register table0, Register table1, Register table2, Register table3,
1373 Register tmp, Register tmp2, Register tmp3);
1374 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1375 void kernel_crc32c(Register crc, Register buf, Register len,
1376 Register table0, Register table1, Register table2, Register table3,
1377 Register tmp, Register tmp2, Register tmp3);
1378
1379 // Stack push and pop individual 64 bit registers
1380 void push(Register src);
1381 void pop(Register dst);
1382
1383 void repne_scan(Register addr, Register value, Register count,
1384 Register scratch);
1385 void repne_scanw(Register addr, Register value, Register count,
1386 Register scratch);
1387
1388 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1389 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1390
1391 // If a constant does not fit in an immediate field, generate some
1392 // number of MOV instructions and then perform the operation
1393 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1394 add_sub_imm_insn insn1,
1395 add_sub_reg_insn insn2, bool is32);
1396 // Separate vsn which sets the flags
1397 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1398 add_sub_imm_insn insn1,
1399 add_sub_reg_insn insn2, bool is32);
1400
1401 #define WRAP(INSN, is32) \
1402 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1403 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1404 } \
1405 \
1406 void INSN(Register Rd, Register Rn, Register Rm, \
1407 enum shift_kind kind, unsigned shift = 0) { \
1408 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1409 } \
1410 \
1411 void INSN(Register Rd, Register Rn, Register Rm) { \
1412 Assembler::INSN(Rd, Rn, Rm); \
1413 } \
1414 \
1415 void INSN(Register Rd, Register Rn, Register Rm, \
1416 ext::operation option, int amount = 0) { \
1417 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1418 }
1419
1420 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1421
1422 #undef WRAP
1423 #define WRAP(INSN, is32) \
1424 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1425 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1426 } \
1427 \
1428 void INSN(Register Rd, Register Rn, Register Rm, \
1429 enum shift_kind kind, unsigned shift = 0) { \
1430 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1431 } \
1432 \
1433 void INSN(Register Rd, Register Rn, Register Rm) { \
1434 Assembler::INSN(Rd, Rn, Rm); \
1435 } \
1436 \
1437 void INSN(Register Rd, Register Rn, Register Rm, \
1438 ext::operation option, int amount = 0) { \
1439 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1440 }
1441
1442 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1443
1444 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1445 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1446 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1447 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1448
1449 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1450
1451 void tableswitch(Register index, jint lowbound, jint highbound,
1452 Label &jumptable, Label &jumptable_end, int stride = 1) {
1453 adr(rscratch1, jumptable);
1454 subsw(rscratch2, index, lowbound);
1455 subsw(zr, rscratch2, highbound - lowbound);
1456 br(Assembler::HS, jumptable_end);
1457 add(rscratch1, rscratch1, rscratch2,
1458 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1459 br(rscratch1);
1460 }
1461
1462 // Form an address from base + offset in Rd. Rd may or may not
1463 // actually be used: you must use the Address that is returned. It
1464 // is up to you to ensure that the shift provided matches the size
1465 // of your data.
1466 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1467
1468 // Return true iff an address is within the 48-bit AArch64 address
1469 // space.
1470 bool is_valid_AArch64_address(address a) {
1471 return ((uint64_t)a >> 48) == 0;
1472 }
1473
1474 // Load the base of the cardtable byte map into reg.
1475 void load_byte_map_base(Register reg);
1476
1477 // Load a constant address in the AOT Runtime Constants area
1478 void load_aotrc_address(Register reg, address a);
1479
1480 // Prolog generator routines to support switch between x86 code and
1481 // generated ARM code
1482
1483 // routine to generate an x86 prolog for a stub function which
1484 // bootstraps into the generated ARM code which directly follows the
1485 // stub
1486 //
1487
1488 public:
1489
1490 address read_polling_page(Register r, relocInfo::relocType rtype);
1491 void get_polling_page(Register dest, relocInfo::relocType rtype);
1492
1493 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1494 void update_byte_crc32(Register crc, Register val, Register table);
1495 void update_word_crc32(Register crc, Register v, Register tmp,
1496 Register table0, Register table1, Register table2, Register table3,
1497 bool upper = false);
1498
1499 address count_positives(Register ary1, Register len, Register result);
1500
1501 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1502 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1503
1504 // Ensure that the inline code and the stub use the same registers.
1505 #define ARRAYS_HASHCODE_REGISTERS \
1506 do { \
1507 assert(result == r0 && \
1508 ary == r1 && \
1509 cnt == r2 && \
1510 vdata0 == v3 && \
1511 vdata1 == v2 && \
1512 vdata2 == v1 && \
1513 vdata3 == v0 && \
1514 vmul0 == v4 && \
1515 vmul1 == v5 && \
1516 vmul2 == v6 && \
1517 vmul3 == v7 && \
1518 vpow == v12 && \
1519 vpowm == v13, "registers must match aarch64.ad"); \
1520 } while (0)
1521
1522 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1523
1524 void fill_words(Register base, Register cnt, Register value);
1525 address zero_words(Register base, uint64_t cnt);
1526 address zero_words(Register ptr, Register cnt);
1527 void zero_dcache_blocks(Register base, Register cnt);
1528
1529 static const int zero_words_block_size;
1530
1531 address byte_array_inflate(Register src, Register dst, Register len,
1532 FloatRegister vtmp1, FloatRegister vtmp2,
1533 FloatRegister vtmp3, Register tmp4);
1534
1535 void char_array_compress(Register src, Register dst, Register len,
1536 Register res,
1537 FloatRegister vtmp0, FloatRegister vtmp1,
1538 FloatRegister vtmp2, FloatRegister vtmp3,
1539 FloatRegister vtmp4, FloatRegister vtmp5);
1540
1541 void encode_iso_array(Register src, Register dst,
1542 Register len, Register res, bool ascii,
1543 FloatRegister vtmp0, FloatRegister vtmp1,
1544 FloatRegister vtmp2, FloatRegister vtmp3,
1545 FloatRegister vtmp4, FloatRegister vtmp5);
1546
1547 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1548 address pio2, address dsin_coef, address dcos_coef);
1549 private:
1550 // begin trigonometric functions support block
1551 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1552 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1553 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1554 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1555 // end trigonometric functions support block
1556 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1557 Register src1, Register src2);
1558 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1559 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1560 }
1561 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1562 Register y, Register y_idx, Register z,
1563 Register carry, Register product,
1564 Register idx, Register kdx);
1565 void multiply_128_x_128_loop(Register y, Register z,
1566 Register carry, Register carry2,
1567 Register idx, Register jdx,
1568 Register yz_idx1, Register yz_idx2,
1569 Register tmp, Register tmp3, Register tmp4,
1570 Register tmp7, Register product_hi);
1571 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1572 Register len, Register tmp0, Register tmp1, Register tmp2,
1573 Register tmp3);
1574 void kernel_crc32_using_crc32(Register crc, Register buf,
1575 Register len, Register tmp0, Register tmp1, Register tmp2,
1576 Register tmp3);
1577 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1578 Register len, Register tmp0, Register tmp1, Register tmp2,
1579 Register tmp3);
1580 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1581 Register len, Register tmp0, Register tmp1, Register tmp2,
1582 Register tmp3);
1583 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1584 Register len, Register tmp0, Register tmp1, Register tmp2,
1585 size_t table_offset);
1586
1587 void ghash_modmul (FloatRegister result,
1588 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1589 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1590 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1591 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1592 public:
1593 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1594 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1595 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1596 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1597 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1598 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1599 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1600 void ghash_multiply_wide(int index,
1601 FloatRegister result_lo, FloatRegister result_hi,
1602 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1603 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1604 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1605 FloatRegister p, FloatRegister z, FloatRegister t1);
1606 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1607 FloatRegister p, FloatRegister z, FloatRegister t1);
1608 void ghash_processBlocks_wide(Label& p, Register state, Register subkeyH,
1609 Register data, Register blocks, int unrolls);
1610
1611
1612 void aesenc_loadkeys(Register key, Register keylen);
1613 void aesecb_encrypt(Register from, Register to, Register keylen,
1614 FloatRegister data = v0, int unrolls = 1);
1615 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1616 void aes_round(FloatRegister input, FloatRegister subkey);
1617
1618 // ChaCha20 functions support block
1619 void cc20_qr_add4(FloatRegister (&addFirst)[4],
1620 FloatRegister (&addSecond)[4]);
1621 void cc20_qr_xor4(FloatRegister (&firstElem)[4],
1622 FloatRegister (&secondElem)[4], FloatRegister (&result)[4]);
1623 void cc20_qr_lrot4(FloatRegister (&sourceReg)[4],
1624 FloatRegister (&destReg)[4], int bits, FloatRegister table);
1625 void cc20_set_qr_registers(FloatRegister (&vectorSet)[4],
1626 const FloatRegister (&stateVectors)[16], int idx1, int idx2,
1627 int idx3, int idx4);
1628
1629 // Rotate using ORR (for identity) or USHR + SLI.
1630 void neon_vector_rotate(FloatRegister dst, SIMD_Arrangement T,
1631 FloatRegister src, int shift_amount);
1632
1633 // Place an ISB after code may have been modified due to a safepoint.
1634 void safepoint_isb();
1635
1636 private:
1637 // Return the effective address r + (r1 << ext) + offset.
1638 // Uses rscratch2.
1639 Address offsetted_address(Register r, Register r1, Address::extend ext,
1640 int offset, int size);
1641
1642 private:
1643 // Returns an address on the stack which is reachable with a ldr/str of size
1644 // Uses rscratch2 if the address is not directly reachable
1645 Address spill_address(int size, int offset, Register tmp=rscratch2);
1646 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1647
1648 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1649
1650 // Check whether two loads/stores can be merged into ldp/stp.
1651 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1652
1653 // Merge current load/store with previous load/store into ldp/stp.
1654 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1655
1656 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1657 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1658
1659 public:
1660 void spill(Register Rx, bool is64, int offset) {
1661 if (is64) {
1662 str(Rx, spill_address(8, offset));
1663 } else {
1664 strw(Rx, spill_address(4, offset));
1665 }
1666 }
1667 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1668 str(Vx, T, spill_address(1 << (int)T, offset));
1669 }
1670
1671 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1672 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1673 }
1674 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1675 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1676 }
1677
1678 void unspill(Register Rx, bool is64, int offset) {
1679 if (is64) {
1680 ldr(Rx, spill_address(8, offset));
1681 } else {
1682 ldrw(Rx, spill_address(4, offset));
1683 }
1684 }
1685 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1686 ldr(Vx, T, spill_address(1 << (int)T, offset));
1687 }
1688
1689 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1690 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1691 }
1692 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1693 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1694 }
1695
1696 void spill_copy128(int src_offset, int dst_offset,
1697 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1698 if (src_offset < 512 && (src_offset & 7) == 0 &&
1699 dst_offset < 512 && (dst_offset & 7) == 0) {
1700 ldp(tmp1, tmp2, Address(sp, src_offset));
1701 stp(tmp1, tmp2, Address(sp, dst_offset));
1702 } else {
1703 unspill(tmp1, true, src_offset);
1704 spill(tmp1, true, dst_offset);
1705 unspill(tmp1, true, src_offset+8);
1706 spill(tmp1, true, dst_offset+8);
1707 }
1708 }
1709 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1710 int sve_vec_reg_size_in_bytes) {
1711 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1712 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1713 spill_copy128(src_offset, dst_offset);
1714 src_offset += 16;
1715 dst_offset += 16;
1716 }
1717 }
1718 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1719 int sve_predicate_reg_size_in_bytes) {
1720 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1721 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1722 reinitialize_ptrue();
1723 }
1724 void cache_wb(Address line);
1725 void cache_wbsync(bool is_pre);
1726
1727 // Code for java.lang.Thread::onSpinWait() intrinsic.
1728 void spin_wait();
1729 void spin_wait_wfet(int delay_ns);
1730
1731 void fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1732 void fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1733
1734 private:
1735 // Check the current thread doesn't need a cross modify fence.
1736 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1737 void try_to_replace_prev_vector_copy_with_movprfx(FloatRegister dst);
1738
1739 public:
1740 void maybe_movprfx(FloatRegister dst, FloatRegister src) {
1741 if (dst != src) {
1742 sve_movprfx(dst, src);
1743 }
1744 }
1745
1746 // Wrappers for SVE explicit destructive instructions, overriding the
1747 // same-signature Assembler entry points to enable movprfx fusion optimization.
1748 //
1749 // Implicit destructive instructions (e.g. predicated unary ops like sve_abs/
1750 // sve_neg/sve_not, whose ISA encoding allows Zd != Zn but whose use as a Java
1751 // Vector API masked operation requires pass-through of the first source) are
1752 // not covered here. For those, the .ad file is responsible for emitting
1753 // movprfx explicitly via maybe_movprfx() before the destructive op.
1754 #define SVE_DESTRUCTIVE_BINARY_INS(NAME) \
1755 using Assembler::NAME; \
1756 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, \
1757 FloatRegister Zm) { \
1758 if (Zd != Zm) { \
1759 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1760 } \
1761 Assembler::NAME(Zd, T, Pg, Zm); \
1762 }
1763
1764 #define SVE_DESTRUCTIVE_BINARY_5(I1, I2, I3, I4, I5) \
1765 SVE_DESTRUCTIVE_BINARY_INS(I1); SVE_DESTRUCTIVE_BINARY_INS(I2); \
1766 SVE_DESTRUCTIVE_BINARY_INS(I3); SVE_DESTRUCTIVE_BINARY_INS(I4); \
1767 SVE_DESTRUCTIVE_BINARY_INS(I5);
1768
1769 SVE_DESTRUCTIVE_BINARY_5(sve_add, sve_and, sve_asr, sve_bic, sve_eor)
1770 SVE_DESTRUCTIVE_BINARY_5(sve_fabd, sve_fadd, sve_fdiv, sve_fmax, sve_fmin)
1771 SVE_DESTRUCTIVE_BINARY_5(sve_fmul, sve_fsub, sve_lsl, sve_lsr, sve_mul)
1772 SVE_DESTRUCTIVE_BINARY_5(sve_orr, sve_smax, sve_smin, sve_sqadd, sve_sqsub)
1773 SVE_DESTRUCTIVE_BINARY_5(sve_sub, sve_uqadd, sve_uqsub, sve_umax, sve_umin)
1774
1775 #undef SVE_DESTRUCTIVE_BINARY_INS
1776 #undef SVE_DESTRUCTIVE_BINARY_5
1777
1778 #define SVE_DESTRUCTIVE_SHIFT_IMM_INS(NAME) \
1779 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, int shift) { \
1780 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1781 Assembler::NAME(Zd, T, Pg, shift); \
1782 }
1783
1784 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_asr);
1785 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_lsl);
1786 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_lsr);
1787
1788 #undef SVE_DESTRUCTIVE_SHIFT_IMM_INS
1789
1790 #define SVE_DESTRUCTIVE_UNPRED_IMM_INS(NAME, IMM_TYPE) \
1791 void NAME(FloatRegister Zd, SIMD_RegVariant T, IMM_TYPE imm) { \
1792 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1793 Assembler::NAME(Zd, T, imm); \
1794 }
1795
1796 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_add, unsigned);
1797 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_sub, unsigned);
1798 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_and, uint64_t);
1799 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_eor, uint64_t);
1800 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_orr, uint64_t);
1801
1802 #undef SVE_DESTRUCTIVE_UNPRED_IMM_INS
1803
1804 #define SVE_DESTRUCTIVE_TERNARY_INS(NAME) \
1805 using Assembler::NAME; \
1806 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, \
1807 FloatRegister Zn, FloatRegister Zm) { \
1808 if (Zd != Zn && Zd != Zm) { \
1809 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1810 } \
1811 Assembler::NAME(Zd, T, Pg, Zn, Zm); \
1812 }
1813
1814 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmad);
1815 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmla);
1816 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmls);
1817 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmsb);
1818 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmad);
1819 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmla);
1820 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmls);
1821 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmsb);
1822 SVE_DESTRUCTIVE_TERNARY_INS(sve_mla);
1823 SVE_DESTRUCTIVE_TERNARY_INS(sve_mls);
1824
1825 #undef SVE_DESTRUCTIVE_TERNARY_INS
1826
1827 using Assembler::sve_eor3;
1828 void sve_eor3(FloatRegister Zd, FloatRegister Zm, FloatRegister Zk) {
1829 if (Zd != Zm && Zd != Zk) {
1830 try_to_replace_prev_vector_copy_with_movprfx(Zd);
1831 }
1832 Assembler::sve_eor3(Zd, Zm, Zk);
1833 }
1834 };
1835
1836 #ifdef ASSERT
1837 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1838 #endif
1839
1840 struct tableswitch {
1841 Register _reg;
1842 int _insn_index; jint _first_key; jint _last_key;
1843 Label _after;
1844 Label _branches;
1845 };
1846
1847 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP