1 /*
   2  * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "metaprogramming/enableIf.hpp"
  31 #include "oops/compressedOops.hpp"
  32 #include "runtime/vm_version.hpp"
  33 #include "utilities/macros.hpp"
  34 #include "utilities/powerOfTwo.hpp"
  35 #include "runtime/signature.hpp"
  36 
  37 
  38 class ciInlineKlass;
  39 
  40 // MacroAssembler extends Assembler by frequently used macros.
  41 //
  42 // Instructions for which a 'better' code sequence exists depending
  43 // on arguments should also go in here.
  44 
  45 class MacroAssembler: public Assembler {
  46   friend class LIR_Assembler;
  47 
  48  public:
  49   using Assembler::mov;
  50   using Assembler::movi;
  51 
  52  protected:
  53 
  54   // Support for VM calls
  55   //
  56   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  57   // may customize this version by overriding it for its purposes (e.g., to save/restore
  58   // additional registers when doing a VM call).
  59   virtual void call_VM_leaf_base(
  60     address entry_point,               // the entry point
  61     int     number_of_arguments,        // the number of arguments to pop after the call
  62     Label *retaddr = NULL
  63   );
  64 
  65   virtual void call_VM_leaf_base(
  66     address entry_point,               // the entry point
  67     int     number_of_arguments,        // the number of arguments to pop after the call
  68     Label &retaddr) {
  69     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  70   }
  71 
  72   // This is the base routine called by the different versions of call_VM. The interpreter
  73   // may customize this version by overriding it for its purposes (e.g., to save/restore
  74   // additional registers when doing a VM call).
  75   //
  76   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  77   // returns the register which contains the thread upon return. If a thread register has been
  78   // specified, the return value will correspond to that register. If no last_java_sp is specified
  79   // (noreg) than rsp will be used instead.
  80   virtual void call_VM_base(           // returns the register containing the thread upon return
  81     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  82     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  83     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  84     address  entry_point,              // the entry point
  85     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  86     bool     check_exceptions          // whether to check for pending exceptions after return
  87   );
  88 
  89   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  90 
  91   enum KlassDecodeMode {
  92     KlassDecodeNone,
  93     KlassDecodeZero,
  94     KlassDecodeXor,
  95     KlassDecodeMovk
  96   };
  97 
  98   KlassDecodeMode klass_decode_mode();
  99 
 100  private:
 101   static KlassDecodeMode _klass_decode_mode;
 102 
 103  public:
 104   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
 105 
 106  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 107  // The implementation is only non-empty for the InterpreterMacroAssembler,
 108  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 109  virtual void check_and_handle_popframe(Register java_thread);
 110  virtual void check_and_handle_earlyret(Register java_thread);
 111 
 112   void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod);
 113 
 114   // Helper functions for statistics gathering.
 115   // Unconditional atomic increment.
 116   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 117   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 118     lea(tmp1, counter_addr);
 119     atomic_incw(tmp1, tmp2, tmp3);
 120   }
 121   // Load Effective Address
 122   void lea(Register r, const Address &a) {
 123     InstructionMark im(this);
 124     code_section()->relocate(inst_mark(), a.rspec());
 125     a.lea(this, r);
 126   }
 127 
 128   /* Sometimes we get misaligned loads and stores, usually from Unsafe
 129      accesses, and these can exceed the offset range. */
 130   Address legitimize_address(const Address &a, int size, Register scratch) {
 131     if (a.getMode() == Address::base_plus_offset) {
 132       if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
 133         block_comment("legitimize_address {");
 134         lea(scratch, a);
 135         block_comment("} legitimize_address");
 136         return Address(scratch);
 137       }
 138     }
 139     return a;
 140   }
 141 
 142   void addmw(Address a, Register incr, Register scratch) {
 143     ldrw(scratch, a);
 144     addw(scratch, scratch, incr);
 145     strw(scratch, a);
 146   }
 147 
 148   // Add constant to memory word
 149   void addmw(Address a, int imm, Register scratch) {
 150     ldrw(scratch, a);
 151     if (imm > 0)
 152       addw(scratch, scratch, (unsigned)imm);
 153     else
 154       subw(scratch, scratch, (unsigned)-imm);
 155     strw(scratch, a);
 156   }
 157 
 158   void bind(Label& L) {
 159     Assembler::bind(L);
 160     code()->clear_last_insn();
 161   }
 162 
 163   void membar(Membar_mask_bits order_constraint);
 164 
 165   using Assembler::ldr;
 166   using Assembler::str;
 167   using Assembler::ldrw;
 168   using Assembler::strw;
 169 
 170   void ldr(Register Rx, const Address &adr);
 171   void ldrw(Register Rw, const Address &adr);
 172   void str(Register Rx, const Address &adr);
 173   void strw(Register Rx, const Address &adr);
 174 
 175   // Frame creation and destruction shared between JITs.
 176   void build_frame(int framesize);
 177   void remove_frame(int framesize);
 178 
 179   virtual void _call_Unimplemented(address call_site) {
 180     mov(rscratch2, call_site);
 181   }
 182 
 183 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
 184 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
 185 // https://reviews.llvm.org/D3311
 186 
 187 #ifdef _WIN64
 188 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
 189 #else
 190 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 191 #endif
 192 
 193   // aliases defined in AARCH64 spec
 194 
 195   template<class T>
 196   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 197 
 198   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 199   inline void cmp(Register Rd, unsigned imm) = delete;
 200 
 201   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 202   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 203 
 204   void cset(Register Rd, Assembler::Condition cond) {
 205     csinc(Rd, zr, zr, ~cond);
 206   }
 207   void csetw(Register Rd, Assembler::Condition cond) {
 208     csincw(Rd, zr, zr, ~cond);
 209   }
 210 
 211   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 212     csneg(Rd, Rn, Rn, ~cond);
 213   }
 214   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 215     csnegw(Rd, Rn, Rn, ~cond);
 216   }
 217 
 218   inline void movw(Register Rd, Register Rn) {
 219     if (Rd == sp || Rn == sp) {
 220       addw(Rd, Rn, 0U);
 221     } else {
 222       orrw(Rd, zr, Rn);
 223     }
 224   }
 225   inline void mov(Register Rd, Register Rn) {
 226     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 227     if (Rd == Rn) {
 228     } else if (Rd == sp || Rn == sp) {
 229       add(Rd, Rn, 0U);
 230     } else {
 231       orr(Rd, zr, Rn);
 232     }
 233   }
 234 
 235   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 236   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 237 
 238   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 239   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 240 
 241   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 242   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 243 
 244   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 245     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 246   }
 247   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 248     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 249   }
 250 
 251   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 252     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 253   }
 254   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 255     bfm(Rd, Rn, lsb , (lsb + width - 1));
 256   }
 257 
 258   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 259     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 260   }
 261   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 262     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 263   }
 264 
 265   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 266     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 267   }
 268   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 269     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 270   }
 271 
 272   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 273     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 274   }
 275   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 276     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 277   }
 278 
 279   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 280     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 281   }
 282   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 283     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 284   }
 285 
 286   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 287     sbfmw(Rd, Rn, imm, 31);
 288   }
 289 
 290   inline void asr(Register Rd, Register Rn, unsigned imm) {
 291     sbfm(Rd, Rn, imm, 63);
 292   }
 293 
 294   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 295     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 296   }
 297 
 298   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 299     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 300   }
 301 
 302   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 303     ubfmw(Rd, Rn, imm, 31);
 304   }
 305 
 306   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 307     ubfm(Rd, Rn, imm, 63);
 308   }
 309 
 310   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 311     extrw(Rd, Rn, Rn, imm);
 312   }
 313 
 314   inline void ror(Register Rd, Register Rn, unsigned imm) {
 315     extr(Rd, Rn, Rn, imm);
 316   }
 317 
 318   inline void sxtbw(Register Rd, Register Rn) {
 319     sbfmw(Rd, Rn, 0, 7);
 320   }
 321   inline void sxthw(Register Rd, Register Rn) {
 322     sbfmw(Rd, Rn, 0, 15);
 323   }
 324   inline void sxtb(Register Rd, Register Rn) {
 325     sbfm(Rd, Rn, 0, 7);
 326   }
 327   inline void sxth(Register Rd, Register Rn) {
 328     sbfm(Rd, Rn, 0, 15);
 329   }
 330   inline void sxtw(Register Rd, Register Rn) {
 331     sbfm(Rd, Rn, 0, 31);
 332   }
 333 
 334   inline void uxtbw(Register Rd, Register Rn) {
 335     ubfmw(Rd, Rn, 0, 7);
 336   }
 337   inline void uxthw(Register Rd, Register Rn) {
 338     ubfmw(Rd, Rn, 0, 15);
 339   }
 340   inline void uxtb(Register Rd, Register Rn) {
 341     ubfm(Rd, Rn, 0, 7);
 342   }
 343   inline void uxth(Register Rd, Register Rn) {
 344     ubfm(Rd, Rn, 0, 15);
 345   }
 346   inline void uxtw(Register Rd, Register Rn) {
 347     ubfm(Rd, Rn, 0, 31);
 348   }
 349 
 350   inline void cmnw(Register Rn, Register Rm) {
 351     addsw(zr, Rn, Rm);
 352   }
 353   inline void cmn(Register Rn, Register Rm) {
 354     adds(zr, Rn, Rm);
 355   }
 356 
 357   inline void cmpw(Register Rn, Register Rm) {
 358     subsw(zr, Rn, Rm);
 359   }
 360   inline void cmp(Register Rn, Register Rm) {
 361     subs(zr, Rn, Rm);
 362   }
 363 
 364   inline void negw(Register Rd, Register Rn) {
 365     subw(Rd, zr, Rn);
 366   }
 367 
 368   inline void neg(Register Rd, Register Rn) {
 369     sub(Rd, zr, Rn);
 370   }
 371 
 372   inline void negsw(Register Rd, Register Rn) {
 373     subsw(Rd, zr, Rn);
 374   }
 375 
 376   inline void negs(Register Rd, Register Rn) {
 377     subs(Rd, zr, Rn);
 378   }
 379 
 380   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 381     addsw(zr, Rn, Rm, kind, shift);
 382   }
 383   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 384     adds(zr, Rn, Rm, kind, shift);
 385   }
 386 
 387   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 388     subsw(zr, Rn, Rm, kind, shift);
 389   }
 390   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 391     subs(zr, Rn, Rm, kind, shift);
 392   }
 393 
 394   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 395     subw(Rd, zr, Rn, kind, shift);
 396   }
 397 
 398   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 399     sub(Rd, zr, Rn, kind, shift);
 400   }
 401 
 402   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 403     subsw(Rd, zr, Rn, kind, shift);
 404   }
 405 
 406   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 407     subs(Rd, zr, Rn, kind, shift);
 408   }
 409 
 410   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 411     msubw(Rd, Rn, Rm, zr);
 412   }
 413   inline void mneg(Register Rd, Register Rn, Register Rm) {
 414     msub(Rd, Rn, Rm, zr);
 415   }
 416 
 417   inline void mulw(Register Rd, Register Rn, Register Rm) {
 418     maddw(Rd, Rn, Rm, zr);
 419   }
 420   inline void mul(Register Rd, Register Rn, Register Rm) {
 421     madd(Rd, Rn, Rm, zr);
 422   }
 423 
 424   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 425     smsubl(Rd, Rn, Rm, zr);
 426   }
 427   inline void smull(Register Rd, Register Rn, Register Rm) {
 428     smaddl(Rd, Rn, Rm, zr);
 429   }
 430 
 431   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 432     umsubl(Rd, Rn, Rm, zr);
 433   }
 434   inline void umull(Register Rd, Register Rn, Register Rm) {
 435     umaddl(Rd, Rn, Rm, zr);
 436   }
 437 
 438 #define WRAP(INSN)                                                            \
 439   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 440     if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr)        \
 441       nop();                                                                  \
 442     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 443   }
 444 
 445   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 446   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 447 #undef WRAP
 448 
 449 
 450   // macro assembly operations needed for aarch64
 451 
 452   // first two private routines for loading 32 bit or 64 bit constants
 453 private:
 454 
 455   void mov_immediate64(Register dst, uint64_t imm64);
 456   void mov_immediate32(Register dst, uint32_t imm32);
 457 
 458   int push(unsigned int bitset, Register stack);
 459   int pop(unsigned int bitset, Register stack);
 460 
 461   int push_fp(unsigned int bitset, Register stack);
 462   int pop_fp(unsigned int bitset, Register stack);
 463 
 464   int push_p(unsigned int bitset, Register stack);
 465   int pop_p(unsigned int bitset, Register stack);
 466 
 467   void mov(Register dst, Address a);
 468 
 469 public:
 470   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 471   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 472 
 473   void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
 474   void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
 475 
 476   static RegSet call_clobbered_gp_registers();
 477 
 478   void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
 479   void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
 480 
 481   // Push and pop everything that might be clobbered by a native
 482   // runtime call except rscratch1 and rscratch2.  (They are always
 483   // scratch, so we don't have to protect them.)  Only save the lower
 484   // 64 bits of each vector register. Additonal registers can be excluded
 485   // in a passed RegSet.
 486   void push_call_clobbered_registers_except(RegSet exclude);
 487   void pop_call_clobbered_registers_except(RegSet exclude);
 488 
 489   void push_call_clobbered_registers() {
 490     push_call_clobbered_registers_except(RegSet());
 491   }
 492   void pop_call_clobbered_registers() {
 493     pop_call_clobbered_registers_except(RegSet());
 494   }
 495 
 496 
 497   // now mov instructions for loading absolute addresses and 32 or
 498   // 64 bit integers
 499 
 500   inline void mov(Register dst, address addr)             { mov_immediate64(dst, (uint64_t)addr); }
 501 
 502   template<typename T, ENABLE_IF(std::is_integral<T>::value)>
 503   inline void mov(Register dst, T o)                      { mov_immediate64(dst, (uint64_t)o); }
 504 
 505   inline void movw(Register dst, uint32_t imm32)          { mov_immediate32(dst, imm32); }
 506 
 507   void mov(Register dst, RegisterOrConstant src) {
 508     if (src.is_register())
 509       mov(dst, src.as_register());
 510     else
 511       mov(dst, src.as_constant());
 512   }
 513 
 514   void movptr(Register r, uintptr_t imm64);
 515 
 516   void mov(FloatRegister Vd, SIMD_Arrangement T, uint32_t imm32);
 517 
 518   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 519     orr(Vd, T, Vn, Vn);
 520   }
 521 
 522 
 523 public:
 524 
 525   // Generalized Test Bit And Branch, including a "far" variety which
 526   // spans more than 32KiB.
 527   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
 528     assert(cond == EQ || cond == NE, "must be");
 529 
 530     if (isfar)
 531       cond = ~cond;
 532 
 533     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 534     if (cond == Assembler::EQ)
 535       branch = &Assembler::tbz;
 536     else
 537       branch = &Assembler::tbnz;
 538 
 539     if (isfar) {
 540       Label L;
 541       (this->*branch)(Rt, bitpos, L);
 542       b(dest);
 543       bind(L);
 544     } else {
 545       (this->*branch)(Rt, bitpos, dest);
 546     }
 547   }
 548 
 549   // macro instructions for accessing and updating floating point
 550   // status register
 551   //
 552   // FPSR : op1 == 011
 553   //        CRn == 0100
 554   //        CRm == 0100
 555   //        op2 == 001
 556 
 557   inline void get_fpsr(Register reg)
 558   {
 559     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 560   }
 561 
 562   inline void set_fpsr(Register reg)
 563   {
 564     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 565   }
 566 
 567   inline void clear_fpsr()
 568   {
 569     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 570   }
 571 
 572   // DCZID_EL0: op1 == 011
 573   //            CRn == 0000
 574   //            CRm == 0000
 575   //            op2 == 111
 576   inline void get_dczid_el0(Register reg)
 577   {
 578     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 579   }
 580 
 581   // CTR_EL0:   op1 == 011
 582   //            CRn == 0000
 583   //            CRm == 0000
 584   //            op2 == 001
 585   inline void get_ctr_el0(Register reg)
 586   {
 587     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 588   }
 589 
 590   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 591   int corrected_idivl(Register result, Register ra, Register rb,
 592                       bool want_remainder, Register tmp = rscratch1);
 593   int corrected_idivq(Register result, Register ra, Register rb,
 594                       bool want_remainder, Register tmp = rscratch1);
 595 
 596   // Support for NULL-checks
 597   //
 598   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 599   // If the accessed location is M[reg + offset] and the offset is known, provide the
 600   // offset. No explicit code generation is needed if the offset is within a certain
 601   // range (0 <= offset <= page_size).
 602 
 603   virtual void null_check(Register reg, int offset = -1);
 604   static bool needs_explicit_null_check(intptr_t offset);
 605   static bool uses_implicit_null_check(void* address);
 606 
 607   // markWord tests, kills markWord reg
 608   void test_markword_is_inline_type(Register markword, Label& is_inline_type);
 609 
 610   // inlineKlass queries, kills temp_reg
 611   void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type);
 612   void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type);
 613   void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type);
 614 
 615   // Get the default value oop for the given InlineKlass
 616   void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj);
 617   // The empty value oop, for the given InlineKlass ("empty" as in no instance fields)
 618   // get_default_value_oop with extra assertion for empty inline klass
 619   void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj);
 620 
 621   void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
 622   void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
 623   void test_field_is_inlined(Register flags, Register temp_reg, Label& is_flattened);
 624 
 625   // Check oops for special arrays, i.e. flattened and/or null-free
 626   void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
 627   void test_flattened_array_oop(Register klass, Register temp_reg, Label& is_flattened_array);
 628   void test_non_flattened_array_oop(Register oop, Register temp_reg, Label&is_non_flattened_array);
 629   void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
 630   void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
 631 
 632   // Check array klass layout helper for flatten or null-free arrays...
 633   void test_flattened_array_layout(Register lh, Label& is_flattened_array);
 634   void test_non_flattened_array_layout(Register lh, Label& is_non_flattened_array);
 635   void test_null_free_array_layout(Register lh, Label& is_null_free_array);
 636   void test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array);
 637 
 638   static address target_addr_for_insn(address insn_addr, unsigned insn);
 639   static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
 640   static address target_addr_for_insn(address insn_addr) {
 641     unsigned insn = *(unsigned*)insn_addr;
 642     return target_addr_for_insn(insn_addr, insn);
 643   }
 644   static address target_addr_for_insn_or_null(address insn_addr) {
 645     unsigned insn = *(unsigned*)insn_addr;
 646     return target_addr_for_insn_or_null(insn_addr, insn);
 647   }
 648 
 649   // Required platform-specific helpers for Label::patch_instructions.
 650   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 651   static int pd_patch_instruction_size(address branch, address target);
 652   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 653     pd_patch_instruction_size(branch, target);
 654   }
 655   static address pd_call_destination(address branch) {
 656     return target_addr_for_insn(branch);
 657   }
 658 #ifndef PRODUCT
 659   static void pd_print_patched_instruction(address branch);
 660 #endif
 661 
 662   static int patch_oop(address insn_addr, address o);
 663   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 664 
 665   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 666   void emit_static_call_stub();
 667 
 668   // The following 4 methods return the offset of the appropriate move instruction
 669 
 670   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 671   int load_unsigned_byte(Register dst, Address src);
 672   int load_unsigned_short(Register dst, Address src);
 673 
 674   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 675   int load_signed_byte(Register dst, Address src);
 676   int load_signed_short(Register dst, Address src);
 677 
 678   int load_signed_byte32(Register dst, Address src);
 679   int load_signed_short32(Register dst, Address src);
 680 
 681   // Support for sign-extension (hi:lo = extend_sign(lo))
 682   void extend_sign(Register hi, Register lo);
 683 
 684   // Load and store values by size and signed-ness
 685   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 686   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 687 
 688   // Support for inc/dec with optimal instruction selection depending on value
 689 
 690   // x86_64 aliases an unqualified register/address increment and
 691   // decrement to call incrementq and decrementq but also supports
 692   // explicitly sized calls to incrementq/decrementq or
 693   // incrementl/decrementl
 694 
 695   // for aarch64 the proper convention would be to use
 696   // increment/decrement for 64 bit operatons and
 697   // incrementw/decrementw for 32 bit operations. so when porting
 698   // x86_64 code we can leave calls to increment/decrement as is,
 699   // replace incrementq/decrementq with increment/decrement and
 700   // replace incrementl/decrementl with incrementw/decrementw.
 701 
 702   // n.b. increment/decrement calls with an Address destination will
 703   // need to use a scratch register to load the value to be
 704   // incremented. increment/decrement calls which add or subtract a
 705   // constant value greater than 2^12 will need to use a 2nd scratch
 706   // register to hold the constant. so, a register increment/decrement
 707   // may trash rscratch2 and an address increment/decrement trash
 708   // rscratch and rscratch2
 709 
 710   void decrementw(Address dst, int value = 1);
 711   void decrementw(Register reg, int value = 1);
 712 
 713   void decrement(Register reg, int value = 1);
 714   void decrement(Address dst, int value = 1);
 715 
 716   void incrementw(Address dst, int value = 1);
 717   void incrementw(Register reg, int value = 1);
 718 
 719   void increment(Register reg, int value = 1);
 720   void increment(Address dst, int value = 1);
 721 
 722 
 723   // Alignment
 724   void align(int modulus);
 725 
 726   // Stack frame creation/removal
 727   void enter(bool strip_ret_addr = false);
 728   void leave();
 729 
 730   // ROP Protection
 731   void protect_return_address();
 732   void protect_return_address(Register return_reg, Register temp_reg);
 733   void authenticate_return_address(Register return_reg = lr);
 734   void authenticate_return_address(Register return_reg, Register temp_reg);
 735   void strip_return_address();
 736   void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
 737 
 738   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 739   // The pointer will be loaded into the thread register.
 740   void get_thread(Register thread);
 741 
 742 
 743   // Support for VM calls
 744   //
 745   // It is imperative that all calls into the VM are handled via the call_VM macros.
 746   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 747   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 748 
 749 
 750   void call_VM(Register oop_result,
 751                address entry_point,
 752                bool check_exceptions = true);
 753   void call_VM(Register oop_result,
 754                address entry_point,
 755                Register arg_1,
 756                bool check_exceptions = true);
 757   void call_VM(Register oop_result,
 758                address entry_point,
 759                Register arg_1, Register arg_2,
 760                bool check_exceptions = true);
 761   void call_VM(Register oop_result,
 762                address entry_point,
 763                Register arg_1, Register arg_2, Register arg_3,
 764                bool check_exceptions = true);
 765 
 766   // Overloadings with last_Java_sp
 767   void call_VM(Register oop_result,
 768                Register last_java_sp,
 769                address entry_point,
 770                int number_of_arguments = 0,
 771                bool check_exceptions = true);
 772   void call_VM(Register oop_result,
 773                Register last_java_sp,
 774                address entry_point,
 775                Register arg_1, bool
 776                check_exceptions = true);
 777   void call_VM(Register oop_result,
 778                Register last_java_sp,
 779                address entry_point,
 780                Register arg_1, Register arg_2,
 781                bool check_exceptions = true);
 782   void call_VM(Register oop_result,
 783                Register last_java_sp,
 784                address entry_point,
 785                Register arg_1, Register arg_2, Register arg_3,
 786                bool check_exceptions = true);
 787 
 788   void get_vm_result  (Register oop_result, Register thread);
 789   void get_vm_result_2(Register metadata_result, Register thread);
 790 
 791   // These always tightly bind to MacroAssembler::call_VM_base
 792   // bypassing the virtual implementation
 793   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 794   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 795   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 796   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 797   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 798 
 799   void call_VM_leaf(address entry_point,
 800                     int number_of_arguments = 0);
 801   void call_VM_leaf(address entry_point,
 802                     Register arg_1);
 803   void call_VM_leaf(address entry_point,
 804                     Register arg_1, Register arg_2);
 805   void call_VM_leaf(address entry_point,
 806                     Register arg_1, Register arg_2, Register arg_3);
 807 
 808   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 809   // bypassing the virtual implementation
 810   void super_call_VM_leaf(address entry_point);
 811   void super_call_VM_leaf(address entry_point, Register arg_1);
 812   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 813   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 814   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 815 
 816   // last Java Frame (fills frame anchor)
 817   void set_last_Java_frame(Register last_java_sp,
 818                            Register last_java_fp,
 819                            address last_java_pc,
 820                            Register scratch);
 821 
 822   void set_last_Java_frame(Register last_java_sp,
 823                            Register last_java_fp,
 824                            Label &last_java_pc,
 825                            Register scratch);
 826 
 827   void set_last_Java_frame(Register last_java_sp,
 828                            Register last_java_fp,
 829                            Register last_java_pc,
 830                            Register scratch);
 831 
 832   void reset_last_Java_frame(Register thread);
 833 
 834   // thread in the default location (rthread)
 835   void reset_last_Java_frame(bool clear_fp);
 836 
 837   // Stores
 838   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 839   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 840 
 841   void resolve_jobject(Register value, Register thread, Register tmp);
 842 
 843   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 844   void c2bool(Register x);
 845 
 846   void load_method_holder_cld(Register rresult, Register rmethod);
 847   void load_method_holder(Register holder, Register method);
 848 
 849   // oop manipulations
 850   void load_metadata(Register dst, Register src);
 851 
 852   void load_klass(Register dst, Register src);
 853   void store_klass(Register dst, Register src);
 854   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 855 
 856   void resolve_weak_handle(Register result, Register tmp);
 857   void resolve_oop_handle(Register result, Register tmp = r5);
 858   void load_mirror(Register dst, Register method, Register tmp = r5);
 859 
 860   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 861                       Register tmp1, Register tmp_thread);
 862 
 863   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 864                        Register tmp1, Register tmp_thread, Register tmp3 = noreg);
 865 
 866   void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register inline_klass);
 867 
 868   // inline type data payload offsets...
 869   void first_field_offset(Register inline_klass, Register offset);
 870   void data_for_oop(Register oop, Register data, Register inline_klass);
 871   // get data payload ptr a flat value array at index, kills rcx and index
 872   void data_for_value_array_index(Register array, Register array_klass,
 873                                   Register index, Register data);
 874 
 875   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 876                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 877 
 878   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 879                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 880   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 881                       Register tmp_thread = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
 882 
 883   // currently unimplemented
 884   // Used for storing NULL. All other oop constants should be
 885   // stored using routines that take a jobject.
 886   void store_heap_oop_null(Address dst);
 887 
 888   void load_prototype_header(Register dst, Register src);
 889 
 890   void store_klass_gap(Register dst, Register src);
 891 
 892   // This dummy is to prevent a call to store_heap_oop from
 893   // converting a zero (like NULL) into a Register by giving
 894   // the compiler two choices it can't resolve
 895 
 896   void store_heap_oop(Address dst, void* dummy);
 897 
 898   void encode_heap_oop(Register d, Register s);
 899   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 900   void decode_heap_oop(Register d, Register s);
 901   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 902   void encode_heap_oop_not_null(Register r);
 903   void decode_heap_oop_not_null(Register r);
 904   void encode_heap_oop_not_null(Register dst, Register src);
 905   void decode_heap_oop_not_null(Register dst, Register src);
 906 
 907   void set_narrow_oop(Register dst, jobject obj);
 908 
 909   void encode_klass_not_null(Register r);
 910   void decode_klass_not_null(Register r);
 911   void encode_klass_not_null(Register dst, Register src);
 912   void decode_klass_not_null(Register dst, Register src);
 913 
 914   void set_narrow_klass(Register dst, Klass* k);
 915 
 916   // if heap base register is used - reinit it with the correct value
 917   void reinit_heapbase();
 918 
 919   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 920 
 921   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 922                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 923   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 924                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 925 
 926   // Round up to a power of two
 927   void round_to(Register reg, int modulus);
 928 
 929   // allocation
 930 
 931   // Object / value buffer allocation...
 932   // Allocate instance of klass, assumes klass initialized by caller
 933   // new_obj prefers to be rax
 934   // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
 935   void allocate_instance(Register klass, Register new_obj,
 936                          Register t1, Register t2,
 937                          bool clear_fields, Label& alloc_failed);
 938 
 939   void eden_allocate(
 940     Register obj,                      // result: pointer to object after successful allocation
 941     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 942     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 943     Register t1,                       // temp register
 944     Label&   slow_case                 // continuation point if fast allocation fails
 945   );
 946   void tlab_allocate(
 947     Register obj,                      // result: pointer to object after successful allocation
 948     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 949     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 950     Register t1,                       // temp register
 951     Register t2,                       // temp register
 952     Label&   slow_case                 // continuation point if fast allocation fails
 953   );
 954   void verify_tlab();
 955 
 956   // For field "index" within "klass", return inline_klass ...
 957   void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
 958 
 959   // interface method calling
 960   void lookup_interface_method(Register recv_klass,
 961                                Register intf_klass,
 962                                RegisterOrConstant itable_index,
 963                                Register method_result,
 964                                Register scan_temp,
 965                                Label& no_such_interface,
 966                    bool return_method = true);
 967 
 968   // virtual method calling
 969   // n.b. x86 allows RegisterOrConstant for vtable_index
 970   void lookup_virtual_method(Register recv_klass,
 971                              RegisterOrConstant vtable_index,
 972                              Register method_result);
 973 
 974   // Test sub_klass against super_klass, with fast and slow paths.
 975 
 976   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 977   // One of the three labels can be NULL, meaning take the fall-through.
 978   // If super_check_offset is -1, the value is loaded up from super_klass.
 979   // No registers are killed, except temp_reg.
 980   void check_klass_subtype_fast_path(Register sub_klass,
 981                                      Register super_klass,
 982                                      Register temp_reg,
 983                                      Label* L_success,
 984                                      Label* L_failure,
 985                                      Label* L_slow_path,
 986                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 987 
 988   // The rest of the type check; must be wired to a corresponding fast path.
 989   // It does not repeat the fast path logic, so don't use it standalone.
 990   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 991   // Updates the sub's secondary super cache as necessary.
 992   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 993   void check_klass_subtype_slow_path(Register sub_klass,
 994                                      Register super_klass,
 995                                      Register temp_reg,
 996                                      Register temp2_reg,
 997                                      Label* L_success,
 998                                      Label* L_failure,
 999                                      bool set_cond_codes = false);
1000 
1001   // Simplified, combined version, good for typical uses.
1002   // Falls through on failure.
1003   void check_klass_subtype(Register sub_klass,
1004                            Register super_klass,
1005                            Register temp_reg,
1006                            Label& L_success);
1007 
1008   void clinit_barrier(Register klass,
1009                       Register thread,
1010                       Label* L_fast_path = NULL,
1011                       Label* L_slow_path = NULL);
1012 
1013   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1014 
1015   void verify_sve_vector_length();
1016   void reinitialize_ptrue() {
1017     if (UseSVE > 0) {
1018       sve_ptrue(ptrue, B);
1019     }
1020   }
1021   void verify_ptrue();
1022 
1023   // Debugging
1024 
1025   // only if +VerifyOops
1026   void verify_oop(Register reg, const char* s = "broken oop");
1027   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1028 
1029 // TODO: verify method and klass metadata (compare against vptr?)
1030   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1031   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1032 
1033 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1034 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1035 
1036   // only if +VerifyFPU
1037   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1038 
1039   // prints msg, dumps registers and stops execution
1040   void stop(const char* msg);
1041 
1042   static void debug64(char* msg, int64_t pc, int64_t regs[]);
1043 
1044   void untested()                                { stop("untested"); }
1045 
1046   void unimplemented(const char* what = "");
1047 
1048   void should_not_reach_here()                   { stop("should not reach here"); }
1049 
1050   // Stack overflow checking
1051   void bang_stack_with_offset(int offset) {
1052     // stack grows down, caller passes positive offset
1053     assert(offset > 0, "must bang with negative offset");
1054     sub(rscratch2, sp, offset);
1055     str(zr, Address(rscratch2));
1056   }
1057 
1058   // Writes to stack successive pages until offset reached to check for
1059   // stack overflow + shadow pages.  Also, clobbers tmp
1060   void bang_stack_size(Register size, Register tmp);
1061 
1062   // Check for reserved stack access in method being exited (for JIT)
1063   void reserved_stack_check();
1064 
1065   // Arithmetics
1066 
1067   void addptr(const Address &dst, int32_t src);
1068   void cmpptr(Register src1, Address src2);
1069 
1070   void cmpoop(Register obj1, Register obj2);
1071 
1072   // Various forms of CAS
1073 
1074   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1075                           Label &suceed, Label *fail);
1076   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1077                   Label &suceed, Label *fail);
1078 
1079   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1080                   Label &suceed, Label *fail);
1081 
1082   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1083   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1084   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1085   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1086 
1087   void atomic_xchg(Register prev, Register newv, Register addr);
1088   void atomic_xchgw(Register prev, Register newv, Register addr);
1089   void atomic_xchgl(Register prev, Register newv, Register addr);
1090   void atomic_xchglw(Register prev, Register newv, Register addr);
1091   void atomic_xchgal(Register prev, Register newv, Register addr);
1092   void atomic_xchgalw(Register prev, Register newv, Register addr);
1093 
1094   void orptr(Address adr, RegisterOrConstant src) {
1095     ldr(rscratch1, adr);
1096     if (src.is_register())
1097       orr(rscratch1, rscratch1, src.as_register());
1098     else
1099       orr(rscratch1, rscratch1, src.as_constant());
1100     str(rscratch1, adr);
1101   }
1102 
1103   // A generic CAS; success or failure is in the EQ flag.
1104   // Clobbers rscratch1
1105   void cmpxchg(Register addr, Register expected, Register new_val,
1106                enum operand_size size,
1107                bool acquire, bool release, bool weak,
1108                Register result);
1109 
1110 private:
1111   void compare_eq(Register rn, Register rm, enum operand_size size);
1112 
1113 #ifdef ASSERT
1114   // Template short-hand support to clean-up after a failed call to trampoline
1115   // call generation (see trampoline_call() below),  when a set of Labels must
1116   // be reset (before returning).
1117   template<typename Label, typename... More>
1118   void reset_labels(Label &lbl, More&... more) {
1119     lbl.reset(); reset_labels(more...);
1120   }
1121   template<typename Label>
1122   void reset_labels(Label &lbl) {
1123     lbl.reset();
1124   }
1125 #endif
1126 
1127 public:
1128   // Calls
1129 
1130   address trampoline_call(Address entry, CodeBuffer* cbuf = NULL);
1131 
1132   static bool far_branches() {
1133     return ReservedCodeCacheSize > branch_range;
1134   }
1135 
1136   // Jumps that can reach anywhere in the code cache.
1137   // Trashes tmp.
1138   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1139   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1140 
1141   static int far_branch_size() {
1142     if (far_branches()) {
1143       return 3 * 4;  // adrp, add, br
1144     } else {
1145       return 4;
1146     }
1147   }
1148 
1149   // Emit the CompiledIC call idiom
1150   address ic_call(address entry, jint method_index = 0);
1151 
1152 public:
1153 
1154   // Data
1155 
1156   void mov_metadata(Register dst, Metadata* obj);
1157   Address allocate_metadata_address(Metadata* obj);
1158   Address constant_oop_address(jobject obj);
1159 
1160   void movoop(Register dst, jobject obj, bool immediate = false);
1161 
1162   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1163   void kernel_crc32(Register crc, Register buf, Register len,
1164         Register table0, Register table1, Register table2, Register table3,
1165         Register tmp, Register tmp2, Register tmp3);
1166   // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1167   void kernel_crc32c(Register crc, Register buf, Register len,
1168         Register table0, Register table1, Register table2, Register table3,
1169         Register tmp, Register tmp2, Register tmp3);
1170 
1171   // Stack push and pop individual 64 bit registers
1172   void push(Register src);
1173   void pop(Register dst);
1174 
1175   void repne_scan(Register addr, Register value, Register count,
1176                   Register scratch);
1177   void repne_scanw(Register addr, Register value, Register count,
1178                    Register scratch);
1179 
1180   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1181   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1182 
1183   // If a constant does not fit in an immediate field, generate some
1184   // number of MOV instructions and then perform the operation
1185   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1186                              add_sub_imm_insn insn1,
1187                              add_sub_reg_insn insn2);
1188   // Seperate vsn which sets the flags
1189   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1190                              add_sub_imm_insn insn1,
1191                              add_sub_reg_insn insn2);
1192 
1193 #define WRAP(INSN)                                                      \
1194   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1195     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1196   }                                                                     \
1197                                                                         \
1198   void INSN(Register Rd, Register Rn, Register Rm,                      \
1199              enum shift_kind kind, unsigned shift = 0) {                \
1200     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1201   }                                                                     \
1202                                                                         \
1203   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1204     Assembler::INSN(Rd, Rn, Rm);                                        \
1205   }                                                                     \
1206                                                                         \
1207   void INSN(Register Rd, Register Rn, Register Rm,                      \
1208            ext::operation option, int amount = 0) {                     \
1209     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1210   }
1211 
1212   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1213 
1214 #undef WRAP
1215 #define WRAP(INSN)                                                      \
1216   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1217     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1218   }                                                                     \
1219                                                                         \
1220   void INSN(Register Rd, Register Rn, Register Rm,                      \
1221              enum shift_kind kind, unsigned shift = 0) {                \
1222     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1223   }                                                                     \
1224                                                                         \
1225   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1226     Assembler::INSN(Rd, Rn, Rm);                                        \
1227   }                                                                     \
1228                                                                         \
1229   void INSN(Register Rd, Register Rn, Register Rm,                      \
1230            ext::operation option, int amount = 0) {                     \
1231     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1232   }
1233 
1234   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1235 
1236   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1237   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1238   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1239   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1240 
1241   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1242 
1243   void verified_entry(Compile* C, int sp_inc);
1244 
1245   // Inline type specific methods
1246   #include "asm/macroAssembler_common.hpp"
1247 
1248   int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1249   bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1250   bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1251                             VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1252                             RegState reg_state[]);
1253   bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1254                           VMRegPair* from, int from_count, int& from_index, VMReg to,
1255                           RegState reg_state[], Register val_array);
1256   int extend_stack_for_inline_args(int args_on_stack);
1257   void remove_frame(int initial_framesize, bool needs_stack_repair);
1258   VMReg spill_reg_for(VMReg reg);
1259   void save_stack_increment(int sp_inc, int frame_size);
1260 
1261   void tableswitch(Register index, jint lowbound, jint highbound,
1262                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1263     adr(rscratch1, jumptable);
1264     subsw(rscratch2, index, lowbound);
1265     subsw(zr, rscratch2, highbound - lowbound);
1266     br(Assembler::HS, jumptable_end);
1267     add(rscratch1, rscratch1, rscratch2,
1268         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1269     br(rscratch1);
1270   }
1271 
1272   // Form an address from base + offset in Rd.  Rd may or may not
1273   // actually be used: you must use the Address that is returned.  It
1274   // is up to you to ensure that the shift provided matches the size
1275   // of your data.
1276   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1277 
1278   // Return true iff an address is within the 48-bit AArch64 address
1279   // space.
1280   bool is_valid_AArch64_address(address a) {
1281     return ((uint64_t)a >> 48) == 0;
1282   }
1283 
1284   // Load the base of the cardtable byte map into reg.
1285   void load_byte_map_base(Register reg);
1286 
1287   // Prolog generator routines to support switch between x86 code and
1288   // generated ARM code
1289 
1290   // routine to generate an x86 prolog for a stub function which
1291   // bootstraps into the generated ARM code which directly follows the
1292   // stub
1293   //
1294 
1295   public:
1296 
1297   void ldr_constant(Register dest, const Address &const_addr) {
1298     if (NearCpool) {
1299       ldr(dest, const_addr);
1300     } else {
1301       uint64_t offset;
1302       adrp(dest, InternalAddress(const_addr.target()), offset);
1303       ldr(dest, Address(dest, offset));
1304     }
1305   }
1306 
1307   address read_polling_page(Register r, relocInfo::relocType rtype);
1308   void get_polling_page(Register dest, relocInfo::relocType rtype);
1309 
1310   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1311   void update_byte_crc32(Register crc, Register val, Register table);
1312   void update_word_crc32(Register crc, Register v, Register tmp,
1313         Register table0, Register table1, Register table2, Register table3,
1314         bool upper = false);
1315 
1316   address count_positives(Register ary1, Register len, Register result);
1317 
1318   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1319                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1320 
1321   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1322                      int elem_size);
1323 
1324   void fill_words(Register base, Register cnt, Register value);
1325   void fill_words(Register base, uint64_t cnt, Register value);
1326 
1327   void zero_words(Register base, uint64_t cnt);
1328   address zero_words(Register ptr, Register cnt);
1329   void zero_dcache_blocks(Register base, Register cnt);
1330 
1331   static const int zero_words_block_size;
1332 
1333   address byte_array_inflate(Register src, Register dst, Register len,
1334                              FloatRegister vtmp1, FloatRegister vtmp2,
1335                              FloatRegister vtmp3, Register tmp4);
1336 
1337   void char_array_compress(Register src, Register dst, Register len,
1338                            Register res,
1339                            FloatRegister vtmp0, FloatRegister vtmp1,
1340                            FloatRegister vtmp2, FloatRegister vtmp3);
1341 
1342   void encode_iso_array(Register src, Register dst,
1343                         Register len, Register res, bool ascii,
1344                         FloatRegister vtmp0, FloatRegister vtmp1,
1345                         FloatRegister vtmp2, FloatRegister vtmp3);
1346 
1347   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1348                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1349                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1350                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1351                 Register tmp3, Register tmp4, Register tmp5);
1352   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1353       address pio2, address dsin_coef, address dcos_coef);
1354  private:
1355   // begin trigonometric functions support block
1356   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1357   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1358   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1359   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1360   // end trigonometric functions support block
1361   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1362                        Register src1, Register src2);
1363   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1364     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1365   }
1366   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1367                              Register y, Register y_idx, Register z,
1368                              Register carry, Register product,
1369                              Register idx, Register kdx);
1370   void multiply_128_x_128_loop(Register y, Register z,
1371                                Register carry, Register carry2,
1372                                Register idx, Register jdx,
1373                                Register yz_idx1, Register yz_idx2,
1374                                Register tmp, Register tmp3, Register tmp4,
1375                                Register tmp7, Register product_hi);
1376   void kernel_crc32_using_crc32(Register crc, Register buf,
1377         Register len, Register tmp0, Register tmp1, Register tmp2,
1378         Register tmp3);
1379   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1380         Register len, Register tmp0, Register tmp1, Register tmp2,
1381         Register tmp3);
1382 
1383   void ghash_modmul (FloatRegister result,
1384                      FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1385                      FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1386                      FloatRegister t1, FloatRegister t2, FloatRegister t3);
1387   void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1388 public:
1389   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1390                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1391                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1392   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1393   void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1394                       FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1395                       FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1396   void ghash_multiply_wide(int index,
1397                            FloatRegister result_lo, FloatRegister result_hi,
1398                            FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1399                            FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1400   void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1401                     FloatRegister p, FloatRegister z, FloatRegister t1);
1402   void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1403                     FloatRegister p, FloatRegister z, FloatRegister t1);
1404   void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1405                                 Register data, Register blocks, int unrolls);
1406 
1407 
1408   void aesenc_loadkeys(Register key, Register keylen);
1409   void aesecb_encrypt(Register from, Register to, Register keylen,
1410                       FloatRegister data = v0, int unrolls = 1);
1411   void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1412   void aes_round(FloatRegister input, FloatRegister subkey);
1413 
1414   // Place an ISB after code may have been modified due to a safepoint.
1415   void safepoint_isb();
1416 
1417 private:
1418   // Return the effective address r + (r1 << ext) + offset.
1419   // Uses rscratch2.
1420   Address offsetted_address(Register r, Register r1, Address::extend ext,
1421                             int offset, int size);
1422 
1423 private:
1424   // Returns an address on the stack which is reachable with a ldr/str of size
1425   // Uses rscratch2 if the address is not directly reachable
1426   Address spill_address(int size, int offset, Register tmp=rscratch2);
1427   Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1428 
1429   bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1430 
1431   // Check whether two loads/stores can be merged into ldp/stp.
1432   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1433 
1434   // Merge current load/store with previous load/store into ldp/stp.
1435   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1436 
1437   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1438   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1439 
1440 public:
1441   void spill(Register Rx, bool is64, int offset) {
1442     if (is64) {
1443       str(Rx, spill_address(8, offset));
1444     } else {
1445       strw(Rx, spill_address(4, offset));
1446     }
1447   }
1448   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1449     str(Vx, T, spill_address(1 << (int)T, offset));
1450   }
1451 
1452   void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1453     sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1454   }
1455   void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1456     sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1457   }
1458 
1459   void unspill(Register Rx, bool is64, int offset) {
1460     if (is64) {
1461       ldr(Rx, spill_address(8, offset));
1462     } else {
1463       ldrw(Rx, spill_address(4, offset));
1464     }
1465   }
1466   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1467     ldr(Vx, T, spill_address(1 << (int)T, offset));
1468   }
1469 
1470   void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1471     sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1472   }
1473   void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1474     sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1475   }
1476 
1477   void spill_copy128(int src_offset, int dst_offset,
1478                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1479     if (src_offset < 512 && (src_offset & 7) == 0 &&
1480         dst_offset < 512 && (dst_offset & 7) == 0) {
1481       ldp(tmp1, tmp2, Address(sp, src_offset));
1482       stp(tmp1, tmp2, Address(sp, dst_offset));
1483     } else {
1484       unspill(tmp1, true, src_offset);
1485       spill(tmp1, true, dst_offset);
1486       unspill(tmp1, true, src_offset+8);
1487       spill(tmp1, true, dst_offset+8);
1488     }
1489   }
1490   void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1491                                             int sve_vec_reg_size_in_bytes) {
1492     assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1493     for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1494       spill_copy128(src_offset, dst_offset);
1495       src_offset += 16;
1496       dst_offset += 16;
1497     }
1498   }
1499   void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1500                                                int sve_predicate_reg_size_in_bytes) {
1501     sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1502     sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1503     reinitialize_ptrue();
1504   }
1505   void cache_wb(Address line);
1506   void cache_wbsync(bool is_pre);
1507 
1508   // Code for java.lang.Thread::onSpinWait() intrinsic.
1509   void spin_wait();
1510 
1511 private:
1512   // Check the current thread doesn't need a cross modify fence.
1513   void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1514 
1515 };
1516 
1517 #ifdef ASSERT
1518 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1519 #endif
1520 
1521 /**
1522  * class SkipIfEqual:
1523  *
1524  * Instantiating this class will result in assembly code being output that will
1525  * jump around any code emitted between the creation of the instance and it's
1526  * automatic destruction at the end of a scope block, depending on the value of
1527  * the flag passed to the constructor, which will be checked at run-time.
1528  */
1529 class SkipIfEqual {
1530  private:
1531   MacroAssembler* _masm;
1532   Label _label;
1533 
1534  public:
1535    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1536    ~SkipIfEqual();
1537 };
1538 
1539 struct tableswitch {
1540   Register _reg;
1541   int _insn_index; jint _first_key; jint _last_key;
1542   Label _after;
1543   Label _branches;
1544 };
1545 
1546 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP