1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/atomicAccess.hpp"
36 #include "runtime/vm_version.hpp"
37 #include "utilities/globalDefinitions.hpp"
38 #include "utilities/macros.hpp"
39 #include "utilities/powerOfTwo.hpp"
40 #include "runtime/signature.hpp"
41
42
43 class ciInlineKlass;
44
45 class OopMap;
46 struct GtestFriendToMacroAssembler;
47
48 // MacroAssembler extends Assembler by frequently used macros.
49 //
50 // Instructions for which a 'better' code sequence exists depending
51 // on arguments should also go in here.
52
53 class MacroAssembler: public Assembler {
54 friend class LIR_Assembler;
55 friend struct GtestFriendToMacroAssembler;
56
57 public:
58 using Assembler::mov;
59 using Assembler::movi;
60
61 protected:
62
63 // Support for VM calls
64 //
65 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
66 // may customize this version by overriding it for its purposes (e.g., to save/restore
67 // additional registers when doing a VM call).
68 virtual void call_VM_leaf_base(
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments to pop after the call
71 Label *retaddr = nullptr
72 );
73
74 virtual void call_VM_leaf_base(
75 address entry_point, // the entry point
76 int number_of_arguments, // the number of arguments to pop after the call
77 Label &retaddr) {
78 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
79 }
80
81 // This is the base routine called by the different versions of call_VM. The interpreter
82 // may customize this version by overriding it for its purposes (e.g., to save/restore
83 // additional registers when doing a VM call).
84 //
85 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
86 // returns the register which contains the thread upon return. If a thread register has been
87 // specified, the return value will correspond to that register. If no last_java_sp is specified
88 // (noreg) than rsp will be used instead.
89 virtual void call_VM_base( // returns the register containing the thread upon return
90 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
91 Register java_thread, // the thread if computed before ; use noreg otherwise
92 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
93 Label* return_pc, // to set up last_Java_frame; use nullptr otherwise
94 address entry_point, // the entry point
95 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
96 bool check_exceptions // whether to check for pending exceptions after return
97 );
98
99 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
100
101 private:
102
103 enum KlassDecodeMode {
104 KlassDecodeNone,
105 KlassDecodeZero,
106 KlassDecodeXor,
107 KlassDecodeMovk,
108 KlassDecodeFallback
109 };
110
111 static KlassDecodeMode _klass_decode_mode;
112
113 // Returns above setting with asserts
114 static KlassDecodeMode klass_decode_mode();
115
116 // Calculate decoding mode based on given parameters, used for checking then ultimately setting.
117 static KlassDecodeMode klass_decode_mode(address base, int shift, const size_t range);
118
119 void emit_encode_klass_not_null(Register dst, Register src, Register tmp,
120 address base, int shift, KlassDecodeMode decode_mode);
121 void emit_decode_klass_not_null(Register dst, Register src, Register tmp,
122 address base, int shift, KlassDecodeMode decode_mode);
123 public:
124 // Determines the decode mode best suited for the given encoding parameters.
125 static void initialize_klass_decode_mode(address base, int shift, const size_t range);
126
127 public:
128 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
129
130 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
131 // The implementation is only non-empty for the InterpreterMacroAssembler,
132 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
133 virtual void check_and_handle_popframe(Register java_thread);
134 virtual void check_and_handle_earlyret(Register java_thread);
135
136 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp = rscratch1);
137 void rt_call(address dest, Register tmp = rscratch1);
138
139 // Load Effective Address
140 void lea(Register r, const Address &a) {
141 InstructionMark im(this);
142 a.lea(this, r);
143 }
144
145 // Whether materializing the given address for a LDR/STR requires an
146 // additional lea instruction.
147 static bool legitimize_address_requires_lea(const Address &a, int size) {
148 return a.getMode() == Address::base_plus_offset &&
149 !Address::offset_ok_for_immed(a.offset(), exact_log2(size));
150 }
151
152 /* Sometimes we get misaligned loads and stores, usually from Unsafe
153 accesses, and these can exceed the offset range. */
154 Address legitimize_address(const Address &a, int size, Register scratch) {
155 if (legitimize_address_requires_lea(a, size)) {
156 block_comment("legitimize_address {");
157 lea(scratch, a);
158 block_comment("} legitimize_address");
159 return Address(scratch);
160 }
161 return a;
162 }
163
164 void addmw(Address a, Register incr, Register scratch) {
165 ldrw(scratch, a);
166 addw(scratch, scratch, incr);
167 strw(scratch, a);
168 }
169
170 // Add constant to memory word
171 void addmw(Address a, int imm, Register scratch) {
172 ldrw(scratch, a);
173 if (imm > 0)
174 addw(scratch, scratch, (unsigned)imm);
175 else
176 subw(scratch, scratch, (unsigned)-imm);
177 strw(scratch, a);
178 }
179
180 void bind(Label& L) {
181 Assembler::bind(L);
182 code()->clear_last_merge_candidate();
183 code()->set_last_label(pc());
184 }
185
186 void membar(Membar_mask_bits order_constraint);
187
188 using Assembler::ldr;
189 using Assembler::str;
190 using Assembler::ldrw;
191 using Assembler::strw;
192
193 void ldr(Register Rx, const Address &adr);
194 void ldrw(Register Rw, const Address &adr);
195 void str(Register Rx, const Address &adr);
196 void strw(Register Rx, const Address &adr);
197
198 // Frame creation and destruction shared between JITs.
199 DEBUG_ONLY(void build_frame(int framesize);)
200 void build_frame(int framesize DEBUG_ONLY(COMMA bool zap_rfp_lr_spills));
201 void remove_frame(int framesize);
202
203 virtual void _call_Unimplemented(address call_site) {
204 mov(rscratch2, call_site);
205 }
206
207 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
208 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
209 // https://reviews.llvm.org/D3311
210
211 #ifdef _WIN64
212 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
213 #else
214 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
215 #endif
216
217 // aliases defined in AARCH64 spec
218
219 template<class T>
220 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
221
222 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
223 inline void cmp(Register Rd, unsigned imm) = delete;
224
225 template<class T>
226 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
227
228 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
229 inline void cmn(Register Rd, unsigned imm) = delete;
230
231 void cset(Register Rd, Assembler::Condition cond) {
232 csinc(Rd, zr, zr, ~cond);
233 }
234 void csetw(Register Rd, Assembler::Condition cond) {
235 csincw(Rd, zr, zr, ~cond);
236 }
237
238 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
239 csneg(Rd, Rn, Rn, ~cond);
240 }
241 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
242 csnegw(Rd, Rn, Rn, ~cond);
243 }
244
245 inline void movw(Register Rd, Register Rn) {
246 if (Rd == sp || Rn == sp) {
247 Assembler::addw(Rd, Rn, 0U);
248 } else {
249 orrw(Rd, zr, Rn);
250 }
251 }
252 inline void mov(Register Rd, Register Rn) {
253 assert(Rd != r31_sp && Rn != r31_sp, "should be");
254 if (Rd == Rn) {
255 } else if (Rd == sp || Rn == sp) {
256 Assembler::add(Rd, Rn, 0U);
257 } else {
258 orr(Rd, zr, Rn);
259 }
260 }
261
262 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
263 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
264
265 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
266 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
267
268 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
269 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
270
271 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
272 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
273 }
274 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
275 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
276 }
277
278 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
279 bfmw(Rd, Rn, lsb, (lsb + width - 1));
280 }
281 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
282 bfm(Rd, Rn, lsb , (lsb + width - 1));
283 }
284
285 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
286 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
287 }
288 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
289 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
290 }
291
292 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
293 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
294 }
295 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
296 sbfm(Rd, Rn, lsb , (lsb + width - 1));
297 }
298
299 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
300 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
301 }
302 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
303 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
304 }
305
306 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
307 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
308 }
309 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
310 ubfm(Rd, Rn, lsb , (lsb + width - 1));
311 }
312
313 inline void asrw(Register Rd, Register Rn, unsigned imm) {
314 sbfmw(Rd, Rn, imm, 31);
315 }
316
317 inline void asr(Register Rd, Register Rn, unsigned imm) {
318 sbfm(Rd, Rn, imm, 63);
319 }
320
321 inline void lslw(Register Rd, Register Rn, unsigned imm) {
322 if (imm > 0 || Rd != Rn) {
323 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
324 }
325 }
326
327 inline void lsl(Register Rd, Register Rn, unsigned imm) {
328 if (imm > 0 || Rd != Rn) {
329 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
330 }
331 }
332
333 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
334 if (imm > 0 || Rd != Rn) {
335 ubfmw(Rd, Rn, imm, 31);
336 }
337 }
338
339 inline void lsr(Register Rd, Register Rn, unsigned imm) {
340 if (imm > 0 || Rd != Rn) {
341 ubfm(Rd, Rn, imm, 63);
342 }
343 }
344
345 inline void rorw(Register Rd, Register Rn, unsigned imm) {
346 extrw(Rd, Rn, Rn, imm);
347 }
348
349 inline void ror(Register Rd, Register Rn, unsigned imm) {
350 extr(Rd, Rn, Rn, imm);
351 }
352
353 inline void rolw(Register Rd, Register Rn, unsigned imm) {
354 extrw(Rd, Rn, Rn, (32 - imm));
355 }
356
357 inline void rol(Register Rd, Register Rn, unsigned imm) {
358 extr(Rd, Rn, Rn, (64 - imm));
359 }
360
361 using Assembler::rax1;
362 using Assembler::eor3;
363
364 inline void rax1(Register Rd, Register Rn, Register Rm) {
365 eor(Rd, Rn, Rm, ROR, 63); // Rd = Rn ^ rol(Rm, 1)
366 }
367
368 inline void eor3(Register Rd, Register Rn, Register Rm, Register Rk) {
369 assert(Rd != Rn, "Use tmp register");
370 eor(Rd, Rm, Rk);
371 eor(Rd, Rd, Rn);
372 }
373
374 inline void sxtbw(Register Rd, Register Rn) {
375 sbfmw(Rd, Rn, 0, 7);
376 }
377 inline void sxthw(Register Rd, Register Rn) {
378 sbfmw(Rd, Rn, 0, 15);
379 }
380 inline void sxtb(Register Rd, Register Rn) {
381 sbfm(Rd, Rn, 0, 7);
382 }
383 inline void sxth(Register Rd, Register Rn) {
384 sbfm(Rd, Rn, 0, 15);
385 }
386 inline void sxtw(Register Rd, Register Rn) {
387 sbfm(Rd, Rn, 0, 31);
388 }
389
390 inline void uxtbw(Register Rd, Register Rn) {
391 ubfmw(Rd, Rn, 0, 7);
392 }
393 inline void uxthw(Register Rd, Register Rn) {
394 ubfmw(Rd, Rn, 0, 15);
395 }
396 inline void uxtb(Register Rd, Register Rn) {
397 ubfm(Rd, Rn, 0, 7);
398 }
399 inline void uxth(Register Rd, Register Rn) {
400 ubfm(Rd, Rn, 0, 15);
401 }
402 inline void uxtw(Register Rd, Register Rn) {
403 ubfm(Rd, Rn, 0, 31);
404 }
405
406 inline void cmnw(Register Rn, Register Rm) {
407 addsw(zr, Rn, Rm);
408 }
409 inline void cmn(Register Rn, Register Rm) {
410 adds(zr, Rn, Rm);
411 }
412
413 inline void cmpw(Register Rn, Register Rm) {
414 subsw(zr, Rn, Rm);
415 }
416 inline void cmp(Register Rn, Register Rm) {
417 subs(zr, Rn, Rm);
418 }
419
420 inline void negw(Register Rd, Register Rn) {
421 subw(Rd, zr, Rn);
422 }
423
424 inline void neg(Register Rd, Register Rn) {
425 sub(Rd, zr, Rn);
426 }
427
428 inline void negsw(Register Rd, Register Rn) {
429 subsw(Rd, zr, Rn);
430 }
431
432 inline void negs(Register Rd, Register Rn) {
433 subs(Rd, zr, Rn);
434 }
435
436 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
437 addsw(zr, Rn, Rm, kind, shift);
438 }
439 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
440 adds(zr, Rn, Rm, kind, shift);
441 }
442
443 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
444 subsw(zr, Rn, Rm, kind, shift);
445 }
446 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
447 subs(zr, Rn, Rm, kind, shift);
448 }
449
450 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
451 subw(Rd, zr, Rn, kind, shift);
452 }
453
454 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
455 sub(Rd, zr, Rn, kind, shift);
456 }
457
458 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
459 subsw(Rd, zr, Rn, kind, shift);
460 }
461
462 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
463 subs(Rd, zr, Rn, kind, shift);
464 }
465
466 inline void mnegw(Register Rd, Register Rn, Register Rm) {
467 msubw(Rd, Rn, Rm, zr);
468 }
469 inline void mneg(Register Rd, Register Rn, Register Rm) {
470 msub(Rd, Rn, Rm, zr);
471 }
472
473 inline void mulw(Register Rd, Register Rn, Register Rm) {
474 maddw(Rd, Rn, Rm, zr);
475 }
476 inline void mul(Register Rd, Register Rn, Register Rm) {
477 madd(Rd, Rn, Rm, zr);
478 }
479
480 inline void smnegl(Register Rd, Register Rn, Register Rm) {
481 smsubl(Rd, Rn, Rm, zr);
482 }
483 inline void smull(Register Rd, Register Rn, Register Rm) {
484 smaddl(Rd, Rn, Rm, zr);
485 }
486
487 inline void umnegl(Register Rd, Register Rn, Register Rm) {
488 umsubl(Rd, Rn, Rm, zr);
489 }
490 inline void umull(Register Rd, Register Rn, Register Rm) {
491 umaddl(Rd, Rn, Rm, zr);
492 }
493
494 #define WRAP(INSN) \
495 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
496 if (VM_Version::supports_a53mac() && Ra != zr) \
497 nop(); \
498 Assembler::INSN(Rd, Rn, Rm, Ra); \
499 }
500
501 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
502 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
503 #undef WRAP
504
505 using Assembler::andw, Assembler::andr;
506 void andw(Register Rd, Register Rn, uint64_t imm) {
507 if (operand_valid_for_logical_immediate(/*is32*/true, imm)) {
508 Assembler::andw(Rd, Rn, imm);
509 } else {
510 assert(Rd != Rn, "must be");
511 movw(Rd, imm);
512 andw(Rd, Rn, Rd);
513 }
514 }
515 void andr(Register Rd, Register Rn, uint64_t imm) {
516 if (operand_valid_for_logical_immediate(/*is32*/false, imm)) {
517 Assembler::andr(Rd, Rn, imm);
518 } else {
519 assert(Rd != Rn, "must be");
520 mov(Rd, imm);
521 andr(Rd, Rn, Rd);
522 }
523 }
524
525 // macro assembly operations needed for aarch64
526
527 public:
528
529 enum FpPushPopMode {
530 PushPopFull,
531 PushPopSVE,
532 PushPopNeon,
533 PushPopFp
534 };
535
536 // first two private routines for loading 32 bit or 64 bit constants
537 private:
538
539 void mov_immediate64(Register dst, uint64_t imm64);
540 void mov_immediate32(Register dst, uint32_t imm32);
541
542 void mov(Register dst, Address a);
543
544 public:
545
546 int push(RegSet regset, Register stack);
547 int pop(RegSet regset, Register stack);
548
549 int push_fp(FloatRegSet regset, Register stack, FpPushPopMode mode = PushPopFull);
550 int pop_fp(FloatRegSet regset, Register stack, FpPushPopMode mode = PushPopFull);
551
552 static RegSet call_clobbered_gp_registers();
553
554 int push_p(PRegSet regset, Register stack);
555 int pop_p(PRegSet regset, Register stack);
556
557 // Push and pop everything that might be clobbered by a native
558 // runtime call except rscratch1 and rscratch2. (They are always
559 // scratch, so we don't have to protect them.) Only save the lower
560 // 64 bits of each vector register. Additional registers can be excluded
561 // in a passed RegSet.
562 void push_call_clobbered_registers_except(RegSet exclude);
563 void pop_call_clobbered_registers_except(RegSet exclude);
564
565 void push_call_clobbered_registers() {
566 push_call_clobbered_registers_except(RegSet());
567 }
568 void pop_call_clobbered_registers() {
569 pop_call_clobbered_registers_except(RegSet());
570 }
571
572
573 // now mov instructions for loading absolute addresses and 32 or
574 // 64 bit integers
575
576 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
577
578 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
579 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
580
581 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
582
583 void mov(Register dst, RegisterOrConstant src) {
584 if (src.is_register())
585 mov(dst, src.as_register());
586 else
587 mov(dst, src.as_constant());
588 }
589
590 void movptr(Register r, uintptr_t imm64);
591
592 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
593
594 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
595 orr(Vd, T, Vn, Vn);
596 }
597
598 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
599 fcvtsh(tmp, src);
600 smov(dst, tmp, H, 0);
601 }
602
603 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
604 mov(tmp, H, 0, src);
605 fcvths(dst, tmp);
606 }
607
608 // Generalized Test Bit And Branch, including a "far" variety which
609 // spans more than 32KiB.
610 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
611 assert(cond == EQ || cond == NE, "must be");
612
613 if (isfar)
614 cond = ~cond;
615
616 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
617 if (cond == Assembler::EQ)
618 branch = &Assembler::tbz;
619 else
620 branch = &Assembler::tbnz;
621
622 if (isfar) {
623 Label L;
624 (this->*branch)(Rt, bitpos, L);
625 b(dest);
626 bind(L);
627 } else {
628 (this->*branch)(Rt, bitpos, dest);
629 }
630 }
631
632 // macro instructions for accessing and updating floating point
633 // status register
634 //
635 // FPSR : op1 == 011
636 // CRn == 0100
637 // CRm == 0100
638 // op2 == 001
639
640 inline void get_fpsr(Register reg)
641 {
642 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
643 }
644
645 inline void set_fpsr(Register reg)
646 {
647 msr(0b011, 0b0100, 0b0100, 0b001, reg);
648 }
649
650 inline void clear_fpsr()
651 {
652 msr(0b011, 0b0100, 0b0100, 0b001, zr);
653 }
654
655 // FPCR : op1 == 011
656 // CRn == 0100
657 // CRm == 0100
658 // op2 == 000
659
660 inline void get_fpcr(Register reg) {
661 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
662 }
663
664 inline void set_fpcr(Register reg) {
665 msr(0b011, 0b0100, 0b0100, 0b000, reg);
666 }
667
668 // DCZID_EL0: op1 == 011
669 // CRn == 0000
670 // CRm == 0000
671 // op2 == 111
672 inline void get_dczid_el0(Register reg)
673 {
674 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
675 }
676
677 // CTR_EL0: op1 == 011
678 // CRn == 0000
679 // CRm == 0000
680 // op2 == 001
681 inline void get_ctr_el0(Register reg)
682 {
683 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
684 }
685
686 inline void get_nzcv(Register reg) {
687 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
688 }
689
690 inline void set_nzcv(Register reg) {
691 msr(0b011, 0b0100, 0b0010, 0b000, reg);
692 }
693
694 // CNTVCTSS_EL0: op1 == 011
695 // CRn == 1110
696 // CRm == 0000
697 // op2 == 110
698 inline void get_cntvctss_el0(Register reg) {
699 mrs(0b011, 0b1110, 0b0000, 0b110, reg);
700 }
701
702 // idiv variant which deals with MINLONG as dividend and -1 as divisor
703 int corrected_idivl(Register result, Register ra, Register rb,
704 bool want_remainder, Register tmp = rscratch1);
705 int corrected_idivq(Register result, Register ra, Register rb,
706 bool want_remainder, Register tmp = rscratch1);
707
708 // Support for null-checks
709 //
710 // Generates code that causes a null OS exception if the content of reg is null.
711 // If the accessed location is M[reg + offset] and the offset is known, provide the
712 // offset. No explicit code generation is needed if the offset is within a certain
713 // range (0 <= offset <= page_size).
714
715 virtual void null_check(Register reg, int offset = -1);
716 static bool needs_explicit_null_check(intptr_t offset);
717 static bool uses_implicit_null_check(void* address);
718
719 // markWord tests, kills markWord reg
720 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
721
722 // inlineKlass queries, kills temp_reg
723 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
724
725 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
726 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
727 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
728
729 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
730 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
731 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
732 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
733 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
734 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
735
736 // Check array klass layout helper for flat or null-free arrays...
737 void test_flat_array_layout(Register lh, Label& is_flat_array);
738
739 static address target_addr_for_insn(address insn_addr);
740
741 // Required platform-specific helpers for Label::patch_instructions.
742 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
743 static int pd_patch_instruction_size(address branch, address target);
744 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
745 pd_patch_instruction_size(branch, target);
746 }
747 static address pd_call_destination(address branch) {
748 return target_addr_for_insn(branch);
749 }
750 #ifndef PRODUCT
751 static void pd_print_patched_instruction(address branch);
752 #endif
753
754 static int patch_oop(address insn_addr, address o);
755
756 // Return whether code is emitted to a scratch blob.
757 virtual bool in_scratch_emit_size() {
758 return false;
759 }
760 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
761 static int max_trampoline_stub_size();
762 void emit_static_call_stub();
763 static int static_call_stub_size();
764
765 // The following 4 methods return the offset of the appropriate move instruction
766
767 // Support for fast byte/short loading with zero extension (depending on particular CPU)
768 int load_unsigned_byte(Register dst, Address src);
769 int load_unsigned_short(Register dst, Address src);
770
771 // Support for fast byte/short loading with sign extension (depending on particular CPU)
772 int load_signed_byte(Register dst, Address src);
773 int load_signed_short(Register dst, Address src);
774
775 int load_signed_byte32(Register dst, Address src);
776 int load_signed_short32(Register dst, Address src);
777
778 // Support for sign-extension (hi:lo = extend_sign(lo))
779 void extend_sign(Register hi, Register lo);
780
781 // Clean up a subword typed value to the representation in compliance with JVMS ยง2.3
782 void narrow_subword_type(Register reg, BasicType bt);
783
784 // Load and store values by size and signed-ness
785 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
786 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
787
788 // Support for inc/dec with optimal instruction selection depending on value
789
790 // x86_64 aliases an unqualified register/address increment and
791 // decrement to call incrementq and decrementq but also supports
792 // explicitly sized calls to incrementq/decrementq or
793 // incrementl/decrementl
794
795 // for aarch64 the proper convention would be to use
796 // increment/decrement for 64 bit operations and
797 // incrementw/decrementw for 32 bit operations. so when porting
798 // x86_64 code we can leave calls to increment/decrement as is,
799 // replace incrementq/decrementq with increment/decrement and
800 // replace incrementl/decrementl with incrementw/decrementw.
801
802 // n.b. increment/decrement calls with an Address destination will
803 // need to use a scratch register to load the value to be
804 // incremented. increment/decrement calls which add or subtract a
805 // constant value greater than 2^24 will need to use a 2nd scratch
806 // register to hold the constant. so, a register increment/decrement
807 // may trash rscratch2 and an address increment/decrement trash
808 // rscratch and rscratch2
809
810 void decrementw(Address dst, int value = 1);
811 void decrementw(Register reg, int value = 1);
812
813 void decrement(Register reg, int value = 1);
814 void decrement(Address dst, int value = 1);
815
816 void incrementw(Address dst, int value = 1, Register result = rscratch1);
817 void incrementw(Register reg, int value = 1);
818
819 void increment(Register reg, int value = 1);
820 void increment(Address dst, int value = 1, Register result = rscratch1);
821
822
823 // Alignment
824 void align(int modulus);
825 void align(int modulus, int target);
826
827 // nop
828 void post_call_nop();
829
830 // Stack frame creation/removal
831 void enter(bool strip_ret_addr = false);
832 void leave();
833
834 // ROP Protection
835 void protect_return_address();
836 void protect_return_address(Register return_reg);
837 void authenticate_return_address();
838 void authenticate_return_address(Register return_reg);
839 void strip_return_address();
840 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
841
842 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
843 // The pointer will be loaded into the thread register.
844 void get_thread(Register thread);
845
846 // support for argument shuffling
847 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
848 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
849 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
850 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
851 void object_move(
852 OopMap* map,
853 int oop_handle_offset,
854 int framesize_in_slots,
855 VMRegPair src,
856 VMRegPair dst,
857 bool is_receiver,
858 int* receiver_offset);
859
860
861 // Support for VM calls
862 //
863 // It is imperative that all calls into the VM are handled via the call_VM macros.
864 // They make sure that the stack linkage is setup correctly. call_VM's correspond
865 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
866
867
868 void call_VM(Register oop_result,
869 address entry_point,
870 bool check_exceptions = true);
871 void call_VM(Register oop_result,
872 address entry_point,
873 Register arg_1,
874 bool check_exceptions = true);
875 void call_VM(Register oop_result,
876 address entry_point,
877 Register arg_1, Register arg_2,
878 bool check_exceptions = true);
879 void call_VM(Register oop_result,
880 address entry_point,
881 Register arg_1, Register arg_2, Register arg_3,
882 bool check_exceptions = true);
883
884 // Overloadings with last_Java_sp
885 void call_VM(Register oop_result,
886 Register last_java_sp,
887 address entry_point,
888 int number_of_arguments = 0,
889 bool check_exceptions = true);
890 void call_VM(Register oop_result,
891 Register last_java_sp,
892 address entry_point,
893 Register arg_1, bool
894 check_exceptions = true);
895 void call_VM(Register oop_result,
896 Register last_java_sp,
897 address entry_point,
898 Register arg_1, Register arg_2,
899 bool check_exceptions = true);
900 void call_VM(Register oop_result,
901 Register last_java_sp,
902 address entry_point,
903 Register arg_1, Register arg_2, Register arg_3,
904 bool check_exceptions = true);
905
906 void get_vm_result_oop(Register oop_result, Register thread);
907 void get_vm_result_metadata(Register metadata_result, Register thread);
908
909 // These always tightly bind to MacroAssembler::call_VM_base
910 // bypassing the virtual implementation
911 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
912 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
913 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
914 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
915 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
916
917 void call_VM_leaf(address entry_point,
918 int number_of_arguments = 0);
919 void call_VM_leaf(address entry_point,
920 Register arg_1);
921 void call_VM_leaf(address entry_point,
922 Register arg_1, Register arg_2);
923 void call_VM_leaf(address entry_point,
924 Register arg_1, Register arg_2, Register arg_3);
925
926 // These always tightly bind to MacroAssembler::call_VM_leaf_base
927 // bypassing the virtual implementation
928 void super_call_VM_leaf(address entry_point);
929 void super_call_VM_leaf(address entry_point, Register arg_1);
930 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
931 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
932 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
933
934 // last Java Frame (fills frame anchor)
935 void set_last_Java_frame(Register last_java_sp,
936 Register last_java_fp,
937 address last_java_pc,
938 Register scratch);
939
940 void set_last_Java_frame(Register last_java_sp,
941 Register last_java_fp,
942 Label &last_java_pc,
943 Register scratch);
944
945 void set_last_Java_frame(Register last_java_sp,
946 Register last_java_fp,
947 Register last_java_pc,
948 Register scratch);
949
950 void reset_last_Java_frame(Register thread);
951
952 // thread in the default location (rthread)
953 void reset_last_Java_frame(bool clear_fp);
954
955 void resolve_jobject(Register value, Register tmp1, Register tmp2);
956 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
957
958 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
959 void c2bool(Register x);
960
961 void load_method_holder_cld(Register rresult, Register rmethod);
962 void load_method_holder(Register holder, Register method);
963
964 // oop manipulations
965 void load_metadata(Register dst, Register src);
966
967 void load_narrow_klass_compact(Register dst, Register src);
968 void load_narrow_klass(Register dst, Register src);
969 void load_klass(Register dst, Register src, Register tmp);
970 void store_klass(Register dst, Register src, Register tmp);
971 void cmp_klass(Register obj, Register klass, Register tmp, Register tmp2);
972 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
973
974 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
975 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
976 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
977
978 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
979 Register tmp1, Register tmp2);
980
981 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
982 Register tmp1, Register tmp2, Register tmp3);
983
984 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
985
986 // inline type data payload offsets...
987 void payload_offset(Register inline_klass, Register offset);
988 void payload_address(Register oop, Register data, Register inline_klass);
989
990 void load_heap_oop(Register dst, Address src, Register tmp1,
991 Register tmp2, DecoratorSet decorators = 0);
992
993 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
994 Register tmp2, DecoratorSet decorators = 0);
995 void store_heap_oop(Address dst, Register val, Register tmp1,
996 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
997
998 // currently unimplemented
999 // Used for storing null. All other oop constants should be
1000 // stored using routines that take a jobject.
1001 void store_heap_oop_null(Address dst);
1002
1003 void load_prototype_header(Register dst, Register src);
1004
1005 void store_klass_gap(Register dst, Register src);
1006
1007 // This dummy is to prevent a call to store_heap_oop from
1008 // converting a zero (like null) into a Register by giving
1009 // the compiler two choices it can't resolve
1010
1011 void store_heap_oop(Address dst, void* dummy);
1012
1013 void encode_heap_oop(Register d, Register s);
1014 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
1015 void decode_heap_oop(Register d, Register s);
1016 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
1017 void encode_heap_oop_not_null(Register r);
1018 void decode_heap_oop_not_null(Register r);
1019 void encode_heap_oop_not_null(Register dst, Register src);
1020 void decode_heap_oop_not_null(Register dst, Register src);
1021
1022 void set_narrow_oop(Register dst, jobject obj);
1023
1024 void encode_klass_not_null(Register dst, Register src, Register tmp);
1025 void decode_klass_not_null(Register dst, Register src, Register tmp);
1026
1027 void set_narrow_klass(Register dst, Klass* k);
1028
1029 // if heap base register is used - reinit it with the correct value
1030 void reinit_heapbase();
1031
1032 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1033
1034 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
1035 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1036 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
1037 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1038
1039 void push_cont_fastpath(Register java_thread = rthread);
1040 void pop_cont_fastpath(Register java_thread = rthread);
1041
1042 // Round up to a power of two
1043 void round_to(Register reg, int modulus);
1044
1045 // java.lang.Math::round intrinsics
1046 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1047 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1048
1049 // allocation
1050
1051 void tlab_allocate(
1052 Register obj, // result: pointer to object after successful allocation
1053 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1054 int con_size_in_bytes, // object size in bytes if known at compile time
1055 Register t1, // temp register
1056 Register t2, // temp register
1057 Label& slow_case // continuation point if fast allocation fails
1058 );
1059 void verify_tlab();
1060
1061 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
1062
1063 // interface method calling
1064 void lookup_interface_method(Register recv_klass,
1065 Register intf_klass,
1066 RegisterOrConstant itable_index,
1067 Register method_result,
1068 Register scan_temp,
1069 Label& no_such_interface,
1070 bool return_method = true);
1071
1072 void lookup_interface_method_stub(Register recv_klass,
1073 Register holder_klass,
1074 Register resolved_klass,
1075 Register method_result,
1076 Register temp_reg,
1077 Register temp_reg2,
1078 int itable_index,
1079 Label& L_no_such_interface);
1080
1081 // virtual method calling
1082 // n.b. x86 allows RegisterOrConstant for vtable_index
1083 void lookup_virtual_method(Register recv_klass,
1084 RegisterOrConstant vtable_index,
1085 Register method_result);
1086
1087 // Test sub_klass against super_klass, with fast and slow paths.
1088
1089 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1090 // One of the three labels can be null, meaning take the fall-through.
1091 // If super_check_offset is -1, the value is loaded up from super_klass.
1092 // No registers are killed, except temp_reg.
1093 void check_klass_subtype_fast_path(Register sub_klass,
1094 Register super_klass,
1095 Register temp_reg,
1096 Label* L_success,
1097 Label* L_failure,
1098 Label* L_slow_path,
1099 Register super_check_offset = noreg);
1100
1101 // The rest of the type check; must be wired to a corresponding fast path.
1102 // It does not repeat the fast path logic, so don't use it standalone.
1103 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1104 // Updates the sub's secondary super cache as necessary.
1105 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1106 void check_klass_subtype_slow_path(Register sub_klass,
1107 Register super_klass,
1108 Register temp_reg,
1109 Register temp2_reg,
1110 Label* L_success,
1111 Label* L_failure,
1112 bool set_cond_codes = false);
1113
1114 void check_klass_subtype_slow_path_linear(Register sub_klass,
1115 Register super_klass,
1116 Register temp_reg,
1117 Register temp2_reg,
1118 Label* L_success,
1119 Label* L_failure,
1120 bool set_cond_codes = false);
1121
1122 void check_klass_subtype_slow_path_table(Register sub_klass,
1123 Register super_klass,
1124 Register temp_reg,
1125 Register temp2_reg,
1126 Register temp3_reg,
1127 Register result_reg,
1128 FloatRegister vtemp_reg,
1129 Label* L_success,
1130 Label* L_failure,
1131 bool set_cond_codes = false);
1132
1133 // If r is valid, return r.
1134 // If r is invalid, remove a register r2 from available_regs, add r2
1135 // to regs_to_push, then return r2.
1136 Register allocate_if_noreg(const Register r,
1137 RegSetIterator<Register> &available_regs,
1138 RegSet ®s_to_push);
1139
1140 // Secondary subtype checking
1141 void lookup_secondary_supers_table_var(Register sub_klass,
1142 Register r_super_klass,
1143 Register temp1,
1144 Register temp2,
1145 Register temp3,
1146 FloatRegister vtemp,
1147 Register result,
1148 Label *L_success);
1149
1150
1151 // As above, but with a constant super_klass.
1152 // The result is in Register result, not the condition codes.
1153 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1154 Register r_super_klass,
1155 Register temp1,
1156 Register temp2,
1157 Register temp3,
1158 FloatRegister vtemp,
1159 Register result,
1160 u1 super_klass_slot,
1161 bool stub_is_near = false);
1162
1163 void verify_secondary_supers_table(Register r_sub_klass,
1164 Register r_super_klass,
1165 Register temp1,
1166 Register temp2,
1167 Register result);
1168
1169 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1170 Register r_array_base,
1171 Register r_array_index,
1172 Register r_bitmap,
1173 Register temp1,
1174 Register result,
1175 bool is_stub = true);
1176
1177 // Simplified, combined version, good for typical uses.
1178 // Falls through on failure.
1179 void check_klass_subtype(Register sub_klass,
1180 Register super_klass,
1181 Register temp_reg,
1182 Label& L_success);
1183
1184 void clinit_barrier(Register klass,
1185 Register thread,
1186 Label* L_fast_path = nullptr,
1187 Label* L_slow_path = nullptr);
1188
1189 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1190
1191 void profile_receiver_type(Register recv, Register mdp, int mdp_offset);
1192
1193 void verify_sve_vector_length(Register tmp = rscratch1);
1194 void reinitialize_ptrue() {
1195 if (UseSVE > 0) {
1196 sve_ptrue(ptrue, B);
1197 }
1198 }
1199 void verify_ptrue();
1200
1201 // Debugging
1202
1203 // only if +VerifyOops
1204 void _verify_oop(Register reg, const char* s, const char* file, int line);
1205 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1206
1207 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1208 if (VerifyOops) {
1209 _verify_oop(reg, s, file, line);
1210 }
1211 }
1212 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1213 if (VerifyOops) {
1214 _verify_oop_addr(reg, s, file, line);
1215 }
1216 }
1217
1218 // TODO: verify method and klass metadata (compare against vptr?)
1219 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1220 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1221
1222 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1223 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1224 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1225 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1226 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1227
1228 // Restore cpu control state after JNI call
1229 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1230
1231 // prints msg, dumps registers and stops execution
1232 void stop(const char* msg);
1233
1234 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1235
1236 void untested() { stop("untested"); }
1237
1238 void unimplemented(const char* what = "");
1239
1240 void should_not_reach_here() { stop("should not reach here"); }
1241
1242 void _assert_asm(Condition cc, const char* msg);
1243 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1244 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1245
1246 // Stack overflow checking
1247 void bang_stack_with_offset(int offset) {
1248 // stack grows down, caller passes positive offset
1249 assert(offset > 0, "must bang with negative offset");
1250 sub(rscratch2, sp, offset);
1251 str(zr, Address(rscratch2));
1252 }
1253
1254 // Writes to stack successive pages until offset reached to check for
1255 // stack overflow + shadow pages. Also, clobbers tmp
1256 void bang_stack_size(Register size, Register tmp);
1257
1258 // Check for reserved stack access in method being exited (for JIT)
1259 void reserved_stack_check();
1260
1261 // Arithmetics
1262
1263 // Clobber: rscratch1, rscratch2
1264 void addptr(const Address &dst, int32_t src);
1265
1266 // Clobber: rscratch1
1267 void cmpptr(Register src1, Address src2);
1268
1269 void cmpoop(Register obj1, Register obj2);
1270
1271 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1272 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1273 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1274 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1275
1276 void atomic_xchg(Register prev, Register newv, Register addr);
1277 void atomic_xchgw(Register prev, Register newv, Register addr);
1278 void atomic_xchgl(Register prev, Register newv, Register addr);
1279 void atomic_xchglw(Register prev, Register newv, Register addr);
1280 void atomic_xchgal(Register prev, Register newv, Register addr);
1281 void atomic_xchgalw(Register prev, Register newv, Register addr);
1282
1283 void orptr(Address adr, RegisterOrConstant src) {
1284 ldr(rscratch1, adr);
1285 if (src.is_register())
1286 orr(rscratch1, rscratch1, src.as_register());
1287 else
1288 orr(rscratch1, rscratch1, src.as_constant());
1289 str(rscratch1, adr);
1290 }
1291
1292 private:
1293 // A generic CAS; success or failure is in the EQ flag.
1294 // Clobbers rscratch1
1295 void cmpxchg(Register addr, Register expected, Register new_val,
1296 enum operand_size size, enum atomic_memory_order order,
1297 bool weak, Register result);
1298
1299 public:
1300 void cmpxchg(Register addr, Register expected, Register new_val,
1301 enum operand_size size, enum atomic_memory_order order,
1302 Register result = noreg) {
1303 cmpxchg(addr, expected, new_val, size, order, /* weak */ false, result);
1304 }
1305
1306 void cmpxchg_weak(Register addr, Register expected, Register new_val,
1307 enum operand_size size, enum atomic_memory_order order,
1308 Register result = noreg) {
1309 cmpxchg(addr, expected, new_val, size, order, /* weak */ true, result);
1310 }
1311
1312 #ifdef ASSERT
1313 // Template short-hand support to clean-up after a failed call to trampoline
1314 // call generation (see trampoline_call() below), when a set of Labels must
1315 // be reset (before returning).
1316 template<typename Label, typename... More>
1317 void reset_labels(Label &lbl, More&... more) {
1318 lbl.reset(); reset_labels(more...);
1319 }
1320 template<typename Label>
1321 void reset_labels(Label &lbl) {
1322 lbl.reset();
1323 }
1324 #endif
1325
1326 private:
1327 void compare_eq(Register rn, Register rm, enum operand_size size);
1328
1329 public:
1330 // AArch64 OpenJDK uses four different types of calls:
1331 // - direct call: bl pc_relative_offset
1332 // This is the shortest and the fastest, but the offset has the range:
1333 // +/-128MB for the release build, +/-2MB for the debug build.
1334 //
1335 // - far call: adrp reg, pc_relative_offset; add; bl reg
1336 // This is longer than a direct call. The offset has
1337 // the range +/-4GB. As the code cache size is limited to 4GB,
1338 // far calls can reach anywhere in the code cache. If a jump is
1339 // needed rather than a call, a far jump 'b reg' can be used instead.
1340 // All instructions are embedded at a call site.
1341 //
1342 // - trampoline call:
1343 // This is only available in C1/C2-generated code (nmethod). It is a combination
1344 // of a direct call, which is used if the destination of a call is in range,
1345 // and a register-indirect call. It has the advantages of reaching anywhere in
1346 // the AArch64 address space and being patchable at runtime when the generated
1347 // code is being executed by other threads.
1348 //
1349 // [Main code section]
1350 // bl trampoline
1351 // [Stub code section]
1352 // trampoline:
1353 // ldr reg, pc + 8
1354 // br reg
1355 // <64-bit destination address>
1356 //
1357 // If the destination is in range when the generated code is moved to the code
1358 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1359 // is not used.
1360 // The optimization does not remove the trampoline from the stub section.
1361 // This is necessary because the trampoline may well be redirected later when
1362 // code is patched, and the new destination may not be reachable by a simple BR
1363 // instruction.
1364 //
1365 // - indirect call: move reg, address; blr reg
1366 // This too can reach anywhere in the address space, but it cannot be
1367 // patched while code is running, so it must only be modified at a safepoint.
1368 // This form of call is most suitable for targets at fixed addresses, which
1369 // will never be patched.
1370 //
1371 // The patching we do conforms to the "Concurrent modification and
1372 // execution of instructions" section of the Arm Architectural
1373 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1374 // or SVC instructions to be modified while another thread is
1375 // executing them.
1376 //
1377 // To patch a trampoline call when the BL can't reach, we first modify
1378 // the 64-bit destination address in the trampoline, then modify the
1379 // BL to point to the trampoline, then flush the instruction cache to
1380 // broadcast the change to all executing threads. See
1381 // NativeCall::set_destination_mt_safe for the details.
1382 //
1383 // There is a benign race in that the other thread might observe the
1384 // modified BL before it observes the modified 64-bit destination
1385 // address. That does not matter because the destination method has been
1386 // invalidated, so there will be a trap at its start.
1387 // For this to work, the destination address in the trampoline is
1388 // always updated, even if we're not using the trampoline.
1389
1390 // Emit a direct call if the entry address will always be in range,
1391 // otherwise a trampoline call.
1392 // Supported entry.rspec():
1393 // - relocInfo::runtime_call_type
1394 // - relocInfo::opt_virtual_call_type
1395 // - relocInfo::static_call_type
1396 // - relocInfo::virtual_call_type
1397 //
1398 // Return: the call PC or null if CodeCache is full.
1399 // Clobbers: rscratch1
1400 address trampoline_call(Address entry);
1401
1402 static bool far_branches() {
1403 return ReservedCodeCacheSize > branch_range;
1404 }
1405 // Check if the static call stub branch needs a far jump.
1406 static bool codestub_branch_needs_far_jump() {
1407 if (AOTCodeCache::is_on_for_dump()) {
1408 // To calculate static_call_stub_size correctly.
1409 return true;
1410 }
1411 return far_branches();
1412 }
1413 // Check if a branch to the given address needs a far jump.
1414 static bool target_needs_far_branch(address addr);
1415
1416 // Emit a direct call/jump if the entry address will always be in range,
1417 // otherwise a far call/jump.
1418 // The address must be inside the code cache.
1419 // Supported entry.rspec():
1420 // - relocInfo::external_word_type
1421 // - relocInfo::runtime_call_type
1422 // - relocInfo::none
1423 // In the case of a far call/jump, the entry address is put in the tmp register.
1424 // The tmp register is invalidated.
1425 //
1426 void far_call(Address entry, Register tmp = rscratch1);
1427 // Far_jump returns the amount of the emitted code.
1428 int far_jump(Address entry, Register tmp = rscratch1);
1429
1430 // Emit the CompiledIC call idiom
1431 address ic_call(address entry, jint method_index = 0);
1432 static int ic_check_size();
1433 int ic_check(int end_alignment);
1434
1435 public:
1436
1437 // Data
1438
1439 void mov_metadata(Register dst, Metadata* obj);
1440 Address allocate_metadata_address(Metadata* obj);
1441 Address constant_oop_address(jobject obj);
1442
1443 void movoop(Register dst, jobject obj);
1444
1445 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1446 void kernel_crc32(Register crc, Register buf, Register len,
1447 Register table0, Register table1, Register table2, Register table3,
1448 Register tmp, Register tmp2, Register tmp3);
1449 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1450 void kernel_crc32c(Register crc, Register buf, Register len,
1451 Register table0, Register table1, Register table2, Register table3,
1452 Register tmp, Register tmp2, Register tmp3);
1453
1454 // Stack push and pop individual 64 bit registers
1455 void push(Register src);
1456 void pop(Register dst);
1457
1458 void repne_scan(Register addr, Register value, Register count,
1459 Register scratch);
1460 void repne_scanw(Register addr, Register value, Register count,
1461 Register scratch);
1462
1463 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1464 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1465
1466 // If a constant does not fit in an immediate field, generate some
1467 // number of MOV instructions and then perform the operation
1468 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1469 add_sub_imm_insn insn1,
1470 add_sub_reg_insn insn2, bool is32);
1471 // Separate vsn which sets the flags
1472 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1473 add_sub_imm_insn insn1,
1474 add_sub_reg_insn insn2, bool is32);
1475
1476 #define WRAP(INSN, is32) \
1477 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1478 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1479 } \
1480 \
1481 void INSN(Register Rd, Register Rn, Register Rm, \
1482 enum shift_kind kind, unsigned shift = 0) { \
1483 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1484 } \
1485 \
1486 void INSN(Register Rd, Register Rn, Register Rm) { \
1487 Assembler::INSN(Rd, Rn, Rm); \
1488 } \
1489 \
1490 void INSN(Register Rd, Register Rn, Register Rm, \
1491 ext::operation option, int amount = 0) { \
1492 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1493 }
1494
1495 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1496
1497 #undef WRAP
1498 #define WRAP(INSN, is32) \
1499 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1500 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1501 } \
1502 \
1503 void INSN(Register Rd, Register Rn, Register Rm, \
1504 enum shift_kind kind, unsigned shift = 0) { \
1505 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1506 } \
1507 \
1508 void INSN(Register Rd, Register Rn, Register Rm) { \
1509 Assembler::INSN(Rd, Rn, Rm); \
1510 } \
1511 \
1512 void INSN(Register Rd, Register Rn, Register Rm, \
1513 ext::operation option, int amount = 0) { \
1514 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1515 }
1516
1517 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1518
1519 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1520 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1521 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1522 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1523
1524 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1525
1526 void verified_entry(Compile* C, int sp_inc);
1527
1528 // Inline type specific methods
1529 #include "asm/macroAssembler_common.hpp"
1530
1531 void save_stack_increment(int sp_inc, int frame_size);
1532
1533 void tableswitch(Register index, jint lowbound, jint highbound,
1534 Label &jumptable, Label &jumptable_end, int stride = 1) {
1535 adr(rscratch1, jumptable);
1536 subsw(rscratch2, index, lowbound);
1537 subsw(zr, rscratch2, highbound - lowbound);
1538 br(Assembler::HS, jumptable_end);
1539 add(rscratch1, rscratch1, rscratch2,
1540 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1541 br(rscratch1);
1542 }
1543
1544 // Form an address from base + offset in Rd. Rd may or may not
1545 // actually be used: you must use the Address that is returned. It
1546 // is up to you to ensure that the shift provided matches the size
1547 // of your data.
1548 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1549
1550 // Return true iff an address is within the 48-bit AArch64 address
1551 // space.
1552 bool is_valid_AArch64_address(address a) {
1553 return ((uint64_t)a >> 48) == 0;
1554 }
1555
1556 // Load the base of the cardtable byte map into reg.
1557 void load_byte_map_base(Register reg);
1558
1559 // Load a constant address in the AOT Runtime Constants area
1560 void load_aotrc_address(Register reg, address a);
1561
1562 // Prolog generator routines to support switch between x86 code and
1563 // generated ARM code
1564
1565 // routine to generate an x86 prolog for a stub function which
1566 // bootstraps into the generated ARM code which directly follows the
1567 // stub
1568 //
1569
1570 public:
1571
1572 address read_polling_page(Register r, relocInfo::relocType rtype);
1573 void get_polling_page(Register dest, relocInfo::relocType rtype);
1574
1575 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1576 void update_byte_crc32(Register crc, Register val, Register table);
1577 void update_word_crc32(Register crc, Register v, Register tmp,
1578 Register table0, Register table1, Register table2, Register table3,
1579 bool upper = false);
1580
1581 address count_positives(Register ary1, Register len, Register result);
1582
1583 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1584 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1585
1586 // Ensure that the inline code and the stub use the same registers.
1587 #define ARRAYS_HASHCODE_REGISTERS \
1588 do { \
1589 assert(result == r0 && \
1590 ary == r1 && \
1591 cnt == r2 && \
1592 vdata0 == v3 && \
1593 vdata1 == v2 && \
1594 vdata2 == v1 && \
1595 vdata3 == v0 && \
1596 vmul0 == v4 && \
1597 vmul1 == v5 && \
1598 vmul2 == v6 && \
1599 vmul3 == v7 && \
1600 vpow == v12 && \
1601 vpowm == v13, "registers must match aarch64.ad"); \
1602 } while (0)
1603
1604 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1605
1606 void fill_words(Register base, Register cnt, Register value);
1607 void fill_words(Register base, uint64_t cnt, Register value);
1608
1609 address zero_words(Register base, uint64_t cnt);
1610 address zero_words(Register ptr, Register cnt);
1611 void zero_dcache_blocks(Register base, Register cnt);
1612
1613 static const int zero_words_block_size;
1614
1615 address byte_array_inflate(Register src, Register dst, Register len,
1616 FloatRegister vtmp1, FloatRegister vtmp2,
1617 FloatRegister vtmp3, Register tmp4);
1618
1619 void char_array_compress(Register src, Register dst, Register len,
1620 Register res,
1621 FloatRegister vtmp0, FloatRegister vtmp1,
1622 FloatRegister vtmp2, FloatRegister vtmp3,
1623 FloatRegister vtmp4, FloatRegister vtmp5);
1624
1625 void encode_iso_array(Register src, Register dst,
1626 Register len, Register res, bool ascii,
1627 FloatRegister vtmp0, FloatRegister vtmp1,
1628 FloatRegister vtmp2, FloatRegister vtmp3,
1629 FloatRegister vtmp4, FloatRegister vtmp5);
1630
1631 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1632 address pio2, address dsin_coef, address dcos_coef);
1633 private:
1634 // begin trigonometric functions support block
1635 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1636 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1637 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1638 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1639 // end trigonometric functions support block
1640 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1641 Register src1, Register src2);
1642 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1643 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1644 }
1645 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1646 Register y, Register y_idx, Register z,
1647 Register carry, Register product,
1648 Register idx, Register kdx);
1649 void multiply_128_x_128_loop(Register y, Register z,
1650 Register carry, Register carry2,
1651 Register idx, Register jdx,
1652 Register yz_idx1, Register yz_idx2,
1653 Register tmp, Register tmp3, Register tmp4,
1654 Register tmp7, Register product_hi);
1655 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1656 Register len, Register tmp0, Register tmp1, Register tmp2,
1657 Register tmp3);
1658 void kernel_crc32_using_crc32(Register crc, Register buf,
1659 Register len, Register tmp0, Register tmp1, Register tmp2,
1660 Register tmp3);
1661 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1662 Register len, Register tmp0, Register tmp1, Register tmp2,
1663 Register tmp3);
1664 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1665 Register len, Register tmp0, Register tmp1, Register tmp2,
1666 Register tmp3);
1667 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1668 Register len, Register tmp0, Register tmp1, Register tmp2,
1669 size_t table_offset);
1670
1671 void ghash_modmul (FloatRegister result,
1672 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1673 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1674 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1675 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1676 public:
1677 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1678 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1679 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1680 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1681 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1682 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1683 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1684 void ghash_multiply_wide(int index,
1685 FloatRegister result_lo, FloatRegister result_hi,
1686 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1687 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1688 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1689 FloatRegister p, FloatRegister z, FloatRegister t1);
1690 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1691 FloatRegister p, FloatRegister z, FloatRegister t1);
1692 void ghash_processBlocks_wide(Label& p, Register state, Register subkeyH,
1693 Register data, Register blocks, int unrolls);
1694
1695
1696 void aesenc_loadkeys(Register key, Register keylen);
1697 void aesecb_encrypt(Register from, Register to, Register keylen,
1698 FloatRegister data = v0, int unrolls = 1);
1699 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1700 void aes_round(FloatRegister input, FloatRegister subkey);
1701
1702 // ChaCha20 functions support block
1703 void cc20_qr_add4(FloatRegister (&addFirst)[4],
1704 FloatRegister (&addSecond)[4]);
1705 void cc20_qr_xor4(FloatRegister (&firstElem)[4],
1706 FloatRegister (&secondElem)[4], FloatRegister (&result)[4]);
1707 void cc20_qr_lrot4(FloatRegister (&sourceReg)[4],
1708 FloatRegister (&destReg)[4], int bits, FloatRegister table);
1709 void cc20_set_qr_registers(FloatRegister (&vectorSet)[4],
1710 const FloatRegister (&stateVectors)[16], int idx1, int idx2,
1711 int idx3, int idx4);
1712
1713 // Rotate using ORR (for identity) or USHR + SLI.
1714 void neon_vector_rotate(FloatRegister dst, SIMD_Arrangement T,
1715 FloatRegister src, int shift_amount);
1716
1717 // Place an ISB after code may have been modified due to a safepoint.
1718 void safepoint_isb();
1719
1720 private:
1721 // Return the effective address r + (r1 << ext) + offset.
1722 // Uses rscratch2.
1723 Address offsetted_address(Register r, Register r1, Address::extend ext,
1724 int offset, int size);
1725
1726 private:
1727 // Returns an address on the stack which is reachable with a ldr/str of size
1728 // Uses rscratch2 if the address is not directly reachable
1729 Address spill_address(int size, int offset, Register tmp=rscratch2);
1730 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1731
1732 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1733
1734 // Check whether two loads/stores can be merged into ldp/stp.
1735 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1736
1737 // Merge current load/store with previous load/store into ldp/stp.
1738 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1739
1740 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1741 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1742
1743 public:
1744 void spill(Register Rx, bool is64, int offset) {
1745 if (is64) {
1746 str(Rx, spill_address(8, offset));
1747 } else {
1748 strw(Rx, spill_address(4, offset));
1749 }
1750 }
1751 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1752 str(Vx, T, spill_address(1 << (int)T, offset));
1753 }
1754
1755 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1756 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1757 }
1758 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1759 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1760 }
1761
1762 void unspill(Register Rx, bool is64, int offset) {
1763 if (is64) {
1764 ldr(Rx, spill_address(8, offset));
1765 } else {
1766 ldrw(Rx, spill_address(4, offset));
1767 }
1768 }
1769 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1770 ldr(Vx, T, spill_address(1 << (int)T, offset));
1771 }
1772
1773 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1774 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1775 }
1776 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1777 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1778 }
1779
1780 void spill_copy128(int src_offset, int dst_offset,
1781 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1782 if (src_offset < 512 && (src_offset & 7) == 0 &&
1783 dst_offset < 512 && (dst_offset & 7) == 0) {
1784 ldp(tmp1, tmp2, Address(sp, src_offset));
1785 stp(tmp1, tmp2, Address(sp, dst_offset));
1786 } else {
1787 unspill(tmp1, true, src_offset);
1788 spill(tmp1, true, dst_offset);
1789 unspill(tmp1, true, src_offset+8);
1790 spill(tmp1, true, dst_offset+8);
1791 }
1792 }
1793 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1794 int sve_vec_reg_size_in_bytes) {
1795 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1796 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1797 spill_copy128(src_offset, dst_offset);
1798 src_offset += 16;
1799 dst_offset += 16;
1800 }
1801 }
1802 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1803 int sve_predicate_reg_size_in_bytes) {
1804 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1805 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1806 reinitialize_ptrue();
1807 }
1808 void cache_wb(Address line);
1809 void cache_wbsync(bool is_pre);
1810
1811 // Code for java.lang.Thread::onSpinWait() intrinsic.
1812 void spin_wait();
1813 void spin_wait_wfet(int delay_ns);
1814
1815 void fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1816 void fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1817
1818 private:
1819 // Check the current thread doesn't need a cross modify fence.
1820 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1821 void try_to_replace_prev_vector_copy_with_movprfx(FloatRegister dst);
1822
1823 public:
1824 void maybe_movprfx(FloatRegister dst, FloatRegister src) {
1825 if (dst != src) {
1826 sve_movprfx(dst, src);
1827 }
1828 }
1829
1830 // Wrappers for SVE explicit destructive instructions, overriding the
1831 // same-signature Assembler entry points to enable movprfx fusion optimization.
1832 //
1833 // Implicit destructive instructions (e.g. predicated unary ops like sve_abs/
1834 // sve_neg/sve_not, whose ISA encoding allows Zd != Zn but whose use as a Java
1835 // Vector API masked operation requires pass-through of the first source) are
1836 // not covered here. For those, the .ad file is responsible for emitting
1837 // movprfx explicitly via maybe_movprfx() before the destructive op.
1838 #define SVE_DESTRUCTIVE_BINARY_INS(NAME) \
1839 using Assembler::NAME; \
1840 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, \
1841 FloatRegister Zm) { \
1842 if (Zd != Zm) { \
1843 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1844 } \
1845 Assembler::NAME(Zd, T, Pg, Zm); \
1846 }
1847
1848 #define SVE_DESTRUCTIVE_BINARY_5(I1, I2, I3, I4, I5) \
1849 SVE_DESTRUCTIVE_BINARY_INS(I1); SVE_DESTRUCTIVE_BINARY_INS(I2); \
1850 SVE_DESTRUCTIVE_BINARY_INS(I3); SVE_DESTRUCTIVE_BINARY_INS(I4); \
1851 SVE_DESTRUCTIVE_BINARY_INS(I5);
1852
1853 SVE_DESTRUCTIVE_BINARY_5(sve_add, sve_and, sve_asr, sve_bic, sve_eor)
1854 SVE_DESTRUCTIVE_BINARY_5(sve_fabd, sve_fadd, sve_fdiv, sve_fmax, sve_fmin)
1855 SVE_DESTRUCTIVE_BINARY_5(sve_fmul, sve_fsub, sve_lsl, sve_lsr, sve_mul)
1856 SVE_DESTRUCTIVE_BINARY_5(sve_orr, sve_smax, sve_smin, sve_sqadd, sve_sqsub)
1857 SVE_DESTRUCTIVE_BINARY_5(sve_sub, sve_uqadd, sve_uqsub, sve_umax, sve_umin)
1858 SVE_DESTRUCTIVE_BINARY_INS(sve_sdiv);
1859 SVE_DESTRUCTIVE_BINARY_INS(sve_udiv);
1860
1861 #undef SVE_DESTRUCTIVE_BINARY_INS
1862 #undef SVE_DESTRUCTIVE_BINARY_5
1863
1864 #define SVE_DESTRUCTIVE_SHIFT_IMM_INS(NAME) \
1865 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, int shift) { \
1866 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1867 Assembler::NAME(Zd, T, Pg, shift); \
1868 }
1869
1870 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_asr);
1871 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_lsl);
1872 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_lsr);
1873
1874 #undef SVE_DESTRUCTIVE_SHIFT_IMM_INS
1875
1876 #define SVE_DESTRUCTIVE_UNPRED_IMM_INS(NAME, IMM_TYPE) \
1877 void NAME(FloatRegister Zd, SIMD_RegVariant T, IMM_TYPE imm) { \
1878 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1879 Assembler::NAME(Zd, T, imm); \
1880 }
1881
1882 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_add, unsigned);
1883 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_sub, unsigned);
1884 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_and, uint64_t);
1885 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_eor, uint64_t);
1886 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_orr, uint64_t);
1887
1888 #undef SVE_DESTRUCTIVE_UNPRED_IMM_INS
1889
1890 #define SVE_DESTRUCTIVE_TERNARY_INS(NAME) \
1891 using Assembler::NAME; \
1892 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, \
1893 FloatRegister Zn, FloatRegister Zm) { \
1894 if (Zd != Zn && Zd != Zm) { \
1895 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1896 } \
1897 Assembler::NAME(Zd, T, Pg, Zn, Zm); \
1898 }
1899
1900 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmad);
1901 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmla);
1902 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmls);
1903 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmsb);
1904 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmad);
1905 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmla);
1906 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmls);
1907 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmsb);
1908 SVE_DESTRUCTIVE_TERNARY_INS(sve_mla);
1909 SVE_DESTRUCTIVE_TERNARY_INS(sve_mls);
1910
1911 #undef SVE_DESTRUCTIVE_TERNARY_INS
1912
1913 #define SVE_DESTRUCTIVE_TERNARY_UNPRED_INS(NAME) \
1914 using Assembler::NAME; \
1915 void NAME(FloatRegister Zd, FloatRegister Zm, FloatRegister Zk) { \
1916 if (Zd != Zm && Zd != Zk) { \
1917 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1918 } \
1919 Assembler::NAME(Zd, Zm, Zk); \
1920 }
1921
1922 SVE_DESTRUCTIVE_TERNARY_UNPRED_INS(sve_bsl);
1923 SVE_DESTRUCTIVE_TERNARY_UNPRED_INS(sve_eor3);
1924
1925 #undef SVE_DESTRUCTIVE_TERNARY_UNPRED_INS
1926 };
1927
1928 #ifdef ASSERT
1929 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1930 #endif
1931
1932 struct tableswitch {
1933 Register _reg;
1934 int _insn_index; jint _first_key; jint _last_key;
1935 Label _after;
1936 Label _branches;
1937 };
1938
1939 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP