1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.hpp"
  30 #include "oops/compressedOops.hpp"
  31 #include "utilities/macros.hpp"
  32 #include "runtime/signature.hpp"
  33 
  34 
  35 class ciValueKlass;
  36 
  37 // MacroAssembler extends Assembler by frequently used macros.
  38 //
  39 // Instructions for which a 'better' code sequence exists depending
  40 // on arguments should also go in here.
  41 
  42 class MacroAssembler: public Assembler {
  43   friend class LIR_Assembler;
  44 
  45  public:
  46   using Assembler::mov;
  47   using Assembler::movi;
  48 
  49  protected:
  50 
  51   // Support for VM calls
  52   //
  53   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  54   // may customize this version by overriding it for its purposes (e.g., to save/restore
  55   // additional registers when doing a VM call).
  56   virtual void call_VM_leaf_base(
  57     address entry_point,               // the entry point
  58     int     number_of_arguments,        // the number of arguments to pop after the call
  59     Label *retaddr = NULL
  60   );
  61 
  62   virtual void call_VM_leaf_base(
  63     address entry_point,               // the entry point
  64     int     number_of_arguments,        // the number of arguments to pop after the call
  65     Label &retaddr) {
  66     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  67   }
  68 
  69   // This is the base routine called by the different versions of call_VM. The interpreter
  70   // may customize this version by overriding it for its purposes (e.g., to save/restore
  71   // additional registers when doing a VM call).
  72   //
  73   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  74   // returns the register which contains the thread upon return. If a thread register has been
  75   // specified, the return value will correspond to that register. If no last_java_sp is specified
  76   // (noreg) than rsp will be used instead.
  77   virtual void call_VM_base(           // returns the register containing the thread upon return
  78     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  79     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  80     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  81     address  entry_point,              // the entry point
  82     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  83     bool     check_exceptions          // whether to check for pending exceptions after return
  84   );
  85 
  86   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  87 
  88   // True if an XOR can be used to expand narrow klass references.
  89   bool use_XOR_for_compressed_class_base;
  90 
  91  public:
  92   MacroAssembler(CodeBuffer* code) : Assembler(code) {
  93     use_XOR_for_compressed_class_base
  94       = operand_valid_for_logical_immediate
  95            (/*is32*/false, (uint64_t)CompressedKlassPointers::base())
  96          && ((uint64_t)CompressedKlassPointers::base()
  97              > (1UL << log2_intptr(CompressedKlassPointers::range())));
  98   }
  99 
 100  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 101  // The implementation is only non-empty for the InterpreterMacroAssembler,
 102  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 103  virtual void check_and_handle_popframe(Register java_thread);
 104  virtual void check_and_handle_earlyret(Register java_thread);
 105 
 106   void safepoint_poll(Label& slow_path);
 107   void safepoint_poll_acquire(Label& slow_path);
 108 
 109   // Biased locking support
 110   // lock_reg and obj_reg must be loaded up with the appropriate values.
 111   // swap_reg is killed.
 112   // tmp_reg must be supplied and must not be rscratch1 or rscratch2
 113   // Optional slow case is for implementations (interpreter and C1) which branch to
 114   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 115   // Returns offset of first potentially-faulting instruction for null
 116   // check info (currently consumed only by C1). If
 117   // swap_reg_contains_mark is true then returns -1 as it is assumed
 118   // the calling code has already passed any potential faults.
 119   int biased_locking_enter(Register lock_reg, Register obj_reg,
 120                            Register swap_reg, Register tmp_reg,
 121                            bool swap_reg_contains_mark,
 122                            Label& done, Label* slow_case = NULL,
 123                            BiasedLockingCounters* counters = NULL);
 124   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 125 
 126 
 127   // Helper functions for statistics gathering.
 128   // Unconditional atomic increment.
 129   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 130   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 131     lea(tmp1, counter_addr);
 132     atomic_incw(tmp1, tmp2, tmp3);
 133   }
 134   // Load Effective Address
 135   void lea(Register r, const Address &a) {
 136     InstructionMark im(this);
 137     code_section()->relocate(inst_mark(), a.rspec());
 138     a.lea(this, r);
 139   }
 140 
 141   void addmw(Address a, Register incr, Register scratch) {
 142     ldrw(scratch, a);
 143     addw(scratch, scratch, incr);
 144     strw(scratch, a);
 145   }
 146 
 147   // Add constant to memory word
 148   void addmw(Address a, int imm, Register scratch) {
 149     ldrw(scratch, a);
 150     if (imm > 0)
 151       addw(scratch, scratch, (unsigned)imm);
 152     else
 153       subw(scratch, scratch, (unsigned)-imm);
 154     strw(scratch, a);
 155   }
 156 
 157   void bind(Label& L) {
 158     Assembler::bind(L);
 159     code()->clear_last_insn();
 160   }
 161 
 162   void membar(Membar_mask_bits order_constraint);
 163 
 164   using Assembler::ldr;
 165   using Assembler::str;
 166 
 167   void ldr(Register Rx, const Address &adr);
 168   void ldrw(Register Rw, const Address &adr);
 169   void str(Register Rx, const Address &adr);
 170   void strw(Register Rx, const Address &adr);
 171 
 172   // Frame creation and destruction shared between JITs.
 173   void build_frame(int framesize);
 174   void remove_frame(int framesize);
 175 
 176   virtual void _call_Unimplemented(address call_site) {
 177     mov(rscratch2, call_site);
 178     haltsim();
 179   }
 180 
 181 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 182 
 183   virtual void notify(int type);
 184 
 185   // aliases defined in AARCH64 spec
 186 
 187   template<class T>
 188   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 189 
 190   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 191   inline void cmp(Register Rd, unsigned imm) __attribute__ ((deprecated));
 192 
 193   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 194   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 195 
 196   void cset(Register Rd, Assembler::Condition cond) {
 197     csinc(Rd, zr, zr, ~cond);
 198   }
 199   void csetw(Register Rd, Assembler::Condition cond) {
 200     csincw(Rd, zr, zr, ~cond);
 201   }
 202 
 203   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 204     csneg(Rd, Rn, Rn, ~cond);
 205   }
 206   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 207     csnegw(Rd, Rn, Rn, ~cond);
 208   }
 209 
 210   inline void movw(Register Rd, Register Rn) {
 211     if (Rd == sp || Rn == sp) {
 212       addw(Rd, Rn, 0U);
 213     } else {
 214       orrw(Rd, zr, Rn);
 215     }
 216   }
 217   inline void mov(Register Rd, Register Rn) {
 218     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 219     if (Rd == Rn) {
 220     } else if (Rd == sp || Rn == sp) {
 221       add(Rd, Rn, 0U);
 222     } else {
 223       orr(Rd, zr, Rn);
 224     }
 225   }
 226 
 227   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 228   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 229 
 230   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 231   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 232 
 233   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 234   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 235 
 236   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 237     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 238   }
 239   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 240     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 241   }
 242 
 243   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 244     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 245   }
 246   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 247     bfm(Rd, Rn, lsb , (lsb + width - 1));
 248   }
 249 
 250   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 251     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 252   }
 253   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 254     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 255   }
 256 
 257   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 258     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 259   }
 260   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 261     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 262   }
 263 
 264   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 265     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 266   }
 267   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 268     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 269   }
 270 
 271   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 272     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 273   }
 274   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 275     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 276   }
 277 
 278   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 279     sbfmw(Rd, Rn, imm, 31);
 280   }
 281 
 282   inline void asr(Register Rd, Register Rn, unsigned imm) {
 283     sbfm(Rd, Rn, imm, 63);
 284   }
 285 
 286   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 287     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 288   }
 289 
 290   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 291     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 292   }
 293 
 294   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 295     ubfmw(Rd, Rn, imm, 31);
 296   }
 297 
 298   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 299     ubfm(Rd, Rn, imm, 63);
 300   }
 301 
 302   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 303     extrw(Rd, Rn, Rn, imm);
 304   }
 305 
 306   inline void ror(Register Rd, Register Rn, unsigned imm) {
 307     extr(Rd, Rn, Rn, imm);
 308   }
 309 
 310   inline void sxtbw(Register Rd, Register Rn) {
 311     sbfmw(Rd, Rn, 0, 7);
 312   }
 313   inline void sxthw(Register Rd, Register Rn) {
 314     sbfmw(Rd, Rn, 0, 15);
 315   }
 316   inline void sxtb(Register Rd, Register Rn) {
 317     sbfm(Rd, Rn, 0, 7);
 318   }
 319   inline void sxth(Register Rd, Register Rn) {
 320     sbfm(Rd, Rn, 0, 15);
 321   }
 322   inline void sxtw(Register Rd, Register Rn) {
 323     sbfm(Rd, Rn, 0, 31);
 324   }
 325 
 326   inline void uxtbw(Register Rd, Register Rn) {
 327     ubfmw(Rd, Rn, 0, 7);
 328   }
 329   inline void uxthw(Register Rd, Register Rn) {
 330     ubfmw(Rd, Rn, 0, 15);
 331   }
 332   inline void uxtb(Register Rd, Register Rn) {
 333     ubfm(Rd, Rn, 0, 7);
 334   }
 335   inline void uxth(Register Rd, Register Rn) {
 336     ubfm(Rd, Rn, 0, 15);
 337   }
 338   inline void uxtw(Register Rd, Register Rn) {
 339     ubfm(Rd, Rn, 0, 31);
 340   }
 341 
 342   inline void cmnw(Register Rn, Register Rm) {
 343     addsw(zr, Rn, Rm);
 344   }
 345   inline void cmn(Register Rn, Register Rm) {
 346     adds(zr, Rn, Rm);
 347   }
 348 
 349   inline void cmpw(Register Rn, Register Rm) {
 350     subsw(zr, Rn, Rm);
 351   }
 352   inline void cmp(Register Rn, Register Rm) {
 353     subs(zr, Rn, Rm);
 354   }
 355 
 356   inline void negw(Register Rd, Register Rn) {
 357     subw(Rd, zr, Rn);
 358   }
 359 
 360   inline void neg(Register Rd, Register Rn) {
 361     sub(Rd, zr, Rn);
 362   }
 363 
 364   inline void negsw(Register Rd, Register Rn) {
 365     subsw(Rd, zr, Rn);
 366   }
 367 
 368   inline void negs(Register Rd, Register Rn) {
 369     subs(Rd, zr, Rn);
 370   }
 371 
 372   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 373     addsw(zr, Rn, Rm, kind, shift);
 374   }
 375   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 376     adds(zr, Rn, Rm, kind, shift);
 377   }
 378 
 379   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 380     subsw(zr, Rn, Rm, kind, shift);
 381   }
 382   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 383     subs(zr, Rn, Rm, kind, shift);
 384   }
 385 
 386   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 387     subw(Rd, zr, Rn, kind, shift);
 388   }
 389 
 390   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 391     sub(Rd, zr, Rn, kind, shift);
 392   }
 393 
 394   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 395     subsw(Rd, zr, Rn, kind, shift);
 396   }
 397 
 398   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 399     subs(Rd, zr, Rn, kind, shift);
 400   }
 401 
 402   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 403     msubw(Rd, Rn, Rm, zr);
 404   }
 405   inline void mneg(Register Rd, Register Rn, Register Rm) {
 406     msub(Rd, Rn, Rm, zr);
 407   }
 408 
 409   inline void mulw(Register Rd, Register Rn, Register Rm) {
 410     maddw(Rd, Rn, Rm, zr);
 411   }
 412   inline void mul(Register Rd, Register Rn, Register Rm) {
 413     madd(Rd, Rn, Rm, zr);
 414   }
 415 
 416   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 417     smsubl(Rd, Rn, Rm, zr);
 418   }
 419   inline void smull(Register Rd, Register Rn, Register Rm) {
 420     smaddl(Rd, Rn, Rm, zr);
 421   }
 422 
 423   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 424     umsubl(Rd, Rn, Rm, zr);
 425   }
 426   inline void umull(Register Rd, Register Rn, Register Rm) {
 427     umaddl(Rd, Rn, Rm, zr);
 428   }
 429 
 430 #define WRAP(INSN)                                                            \
 431   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 432     if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr)        \
 433       nop();                                                                  \
 434     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 435   }
 436 
 437   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 438   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 439 #undef WRAP
 440 
 441 
 442   // macro assembly operations needed for aarch64
 443 
 444   // first two private routines for loading 32 bit or 64 bit constants
 445 private:
 446 
 447   void mov_immediate64(Register dst, u_int64_t imm64);
 448   void mov_immediate32(Register dst, u_int32_t imm32);
 449 
 450   int push(unsigned int bitset, Register stack);
 451   int pop(unsigned int bitset, Register stack);
 452 
 453   void mov(Register dst, Address a);
 454 
 455 public:
 456   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 457   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 458 
 459   // Push and pop everything that might be clobbered by a native
 460   // runtime call except rscratch1 and rscratch2.  (They are always
 461   // scratch, so we don't have to protect them.)  Only save the lower
 462   // 64 bits of each vector register.
 463   void push_call_clobbered_registers();
 464   void pop_call_clobbered_registers();
 465 
 466   // now mov instructions for loading absolute addresses and 32 or
 467   // 64 bit integers
 468 
 469   inline void mov(Register dst, address addr)
 470   {
 471     mov_immediate64(dst, (u_int64_t)addr);
 472   }
 473 
 474   inline void mov(Register dst, u_int64_t imm64)
 475   {
 476     mov_immediate64(dst, imm64);
 477   }
 478 
 479   inline void movw(Register dst, u_int32_t imm32)
 480   {
 481     mov_immediate32(dst, imm32);
 482   }
 483 
 484   inline void mov(Register dst, long l)
 485   {
 486     mov(dst, (u_int64_t)l);
 487   }
 488 
 489   inline void mov(Register dst, int i)
 490   {
 491     mov(dst, (long)i);
 492   }
 493 
 494   void mov(Register dst, RegisterOrConstant src) {
 495     if (src.is_register())
 496       mov(dst, src.as_register());
 497     else
 498       mov(dst, src.as_constant());
 499   }
 500 
 501   void movptr(Register r, uintptr_t imm64);
 502 
 503   void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
 504 
 505   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 506     orr(Vd, T, Vn, Vn);
 507   }
 508 
 509 public:
 510 
 511   // Generalized Test Bit And Branch, including a "far" variety which
 512   // spans more than 32KiB.
 513   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
 514     assert(cond == EQ || cond == NE, "must be");
 515 
 516     if (far)
 517       cond = ~cond;
 518 
 519     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 520     if (cond == Assembler::EQ)
 521       branch = &Assembler::tbz;
 522     else
 523       branch = &Assembler::tbnz;
 524 
 525     if (far) {
 526       Label L;
 527       (this->*branch)(Rt, bitpos, L);
 528       b(dest);
 529       bind(L);
 530     } else {
 531       (this->*branch)(Rt, bitpos, dest);
 532     }
 533   }
 534 
 535   // macro instructions for accessing and updating floating point
 536   // status register
 537   //
 538   // FPSR : op1 == 011
 539   //        CRn == 0100
 540   //        CRm == 0100
 541   //        op2 == 001
 542 
 543   inline void get_fpsr(Register reg)
 544   {
 545     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 546   }
 547 
 548   inline void set_fpsr(Register reg)
 549   {
 550     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 551   }
 552 
 553   inline void clear_fpsr()
 554   {
 555     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 556   }
 557 
 558   // DCZID_EL0: op1 == 011
 559   //            CRn == 0000
 560   //            CRm == 0000
 561   //            op2 == 111
 562   inline void get_dczid_el0(Register reg)
 563   {
 564     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 565   }
 566 
 567   // CTR_EL0:   op1 == 011
 568   //            CRn == 0000
 569   //            CRm == 0000
 570   //            op2 == 001
 571   inline void get_ctr_el0(Register reg)
 572   {
 573     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 574   }
 575 
 576   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 577   int corrected_idivl(Register result, Register ra, Register rb,
 578                       bool want_remainder, Register tmp = rscratch1);
 579   int corrected_idivq(Register result, Register ra, Register rb,
 580                       bool want_remainder, Register tmp = rscratch1);
 581 
 582   // Support for NULL-checks
 583   //
 584   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 585   // If the accessed location is M[reg + offset] and the offset is known, provide the
 586   // offset. No explicit code generation is needed if the offset is within a certain
 587   // range (0 <= offset <= page_size).
 588 
 589   virtual void null_check(Register reg, int offset = -1);
 590   static bool needs_explicit_null_check(intptr_t offset);
 591   static bool uses_implicit_null_check(void* address);
 592 
 593   void test_klass_is_value(Register klass, Register temp_reg, Label& is_value);
 594 
 595   void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable);
 596   void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable);
 597   void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened);
 598 
 599   // Check klass/oops is flat value type array (oop->_klass->_layout_helper & vt_bit)
 600   void test_flattened_array_oop(Register klass, Register temp_reg, Label& is_flattened_array);
 601   void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
 602 
 603   static address target_addr_for_insn(address insn_addr, unsigned insn);
 604   static address target_addr_for_insn(address insn_addr) {
 605     unsigned insn = *(unsigned*)insn_addr;
 606     return target_addr_for_insn(insn_addr, insn);
 607   }
 608 
 609   // Required platform-specific helpers for Label::patch_instructions.
 610   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 611   static int pd_patch_instruction_size(address branch, address target);
 612   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 613     pd_patch_instruction_size(branch, target);
 614   }
 615   static address pd_call_destination(address branch) {
 616     return target_addr_for_insn(branch);
 617   }
 618 #ifndef PRODUCT
 619   static void pd_print_patched_instruction(address branch);
 620 #endif
 621 
 622   static int patch_oop(address insn_addr, address o);
 623   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 624 
 625   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 626   void emit_static_call_stub();
 627 
 628   // The following 4 methods return the offset of the appropriate move instruction
 629 
 630   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 631   int load_unsigned_byte(Register dst, Address src);
 632   int load_unsigned_short(Register dst, Address src);
 633 
 634   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 635   int load_signed_byte(Register dst, Address src);
 636   int load_signed_short(Register dst, Address src);
 637 
 638   int load_signed_byte32(Register dst, Address src);
 639   int load_signed_short32(Register dst, Address src);
 640 
 641   // Support for sign-extension (hi:lo = extend_sign(lo))
 642   void extend_sign(Register hi, Register lo);
 643 
 644   // Load and store values by size and signed-ness
 645   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 646   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 647 
 648   // Support for inc/dec with optimal instruction selection depending on value
 649 
 650   // x86_64 aliases an unqualified register/address increment and
 651   // decrement to call incrementq and decrementq but also supports
 652   // explicitly sized calls to incrementq/decrementq or
 653   // incrementl/decrementl
 654 
 655   // for aarch64 the proper convention would be to use
 656   // increment/decrement for 64 bit operatons and
 657   // incrementw/decrementw for 32 bit operations. so when porting
 658   // x86_64 code we can leave calls to increment/decrement as is,
 659   // replace incrementq/decrementq with increment/decrement and
 660   // replace incrementl/decrementl with incrementw/decrementw.
 661 
 662   // n.b. increment/decrement calls with an Address destination will
 663   // need to use a scratch register to load the value to be
 664   // incremented. increment/decrement calls which add or subtract a
 665   // constant value greater than 2^12 will need to use a 2nd scratch
 666   // register to hold the constant. so, a register increment/decrement
 667   // may trash rscratch2 and an address increment/decrement trash
 668   // rscratch and rscratch2
 669 
 670   void decrementw(Address dst, int value = 1);
 671   void decrementw(Register reg, int value = 1);
 672 
 673   void decrement(Register reg, int value = 1);
 674   void decrement(Address dst, int value = 1);
 675 
 676   void incrementw(Address dst, int value = 1);
 677   void incrementw(Register reg, int value = 1);
 678 
 679   void increment(Register reg, int value = 1);
 680   void increment(Address dst, int value = 1);
 681 
 682 
 683   // Alignment
 684   void align(int modulus);
 685 
 686   // Stack frame creation/removal
 687   void enter()
 688   {
 689     stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
 690     mov(rfp, sp);
 691   }
 692   void leave()
 693   {
 694     mov(sp, rfp);
 695     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
 696   }
 697 
 698   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 699   // The pointer will be loaded into the thread register.
 700   void get_thread(Register thread);
 701 
 702 
 703   // Support for VM calls
 704   //
 705   // It is imperative that all calls into the VM are handled via the call_VM macros.
 706   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 707   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 708 
 709 
 710   void call_VM(Register oop_result,
 711                address entry_point,
 712                bool check_exceptions = true);
 713   void call_VM(Register oop_result,
 714                address entry_point,
 715                Register arg_1,
 716                bool check_exceptions = true);
 717   void call_VM(Register oop_result,
 718                address entry_point,
 719                Register arg_1, Register arg_2,
 720                bool check_exceptions = true);
 721   void call_VM(Register oop_result,
 722                address entry_point,
 723                Register arg_1, Register arg_2, Register arg_3,
 724                bool check_exceptions = true);
 725 
 726   // Overloadings with last_Java_sp
 727   void call_VM(Register oop_result,
 728                Register last_java_sp,
 729                address entry_point,
 730                int number_of_arguments = 0,
 731                bool check_exceptions = true);
 732   void call_VM(Register oop_result,
 733                Register last_java_sp,
 734                address entry_point,
 735                Register arg_1, bool
 736                check_exceptions = true);
 737   void call_VM(Register oop_result,
 738                Register last_java_sp,
 739                address entry_point,
 740                Register arg_1, Register arg_2,
 741                bool check_exceptions = true);
 742   void call_VM(Register oop_result,
 743                Register last_java_sp,
 744                address entry_point,
 745                Register arg_1, Register arg_2, Register arg_3,
 746                bool check_exceptions = true);
 747 
 748   void get_vm_result  (Register oop_result, Register thread);
 749   void get_vm_result_2(Register metadata_result, Register thread);
 750 
 751   // These always tightly bind to MacroAssembler::call_VM_base
 752   // bypassing the virtual implementation
 753   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 754   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 755   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 756   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 757   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 758 
 759   void call_VM_leaf(address entry_point,
 760                     int number_of_arguments = 0);
 761   void call_VM_leaf(address entry_point,
 762                     Register arg_1);
 763   void call_VM_leaf(address entry_point,
 764                     Register arg_1, Register arg_2);
 765   void call_VM_leaf(address entry_point,
 766                     Register arg_1, Register arg_2, Register arg_3);
 767 
 768   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 769   // bypassing the virtual implementation
 770   void super_call_VM_leaf(address entry_point);
 771   void super_call_VM_leaf(address entry_point, Register arg_1);
 772   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 773   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 774   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 775 
 776   // last Java Frame (fills frame anchor)
 777   void set_last_Java_frame(Register last_java_sp,
 778                            Register last_java_fp,
 779                            address last_java_pc,
 780                            Register scratch);
 781 
 782   void set_last_Java_frame(Register last_java_sp,
 783                            Register last_java_fp,
 784                            Label &last_java_pc,
 785                            Register scratch);
 786 
 787   void set_last_Java_frame(Register last_java_sp,
 788                            Register last_java_fp,
 789                            Register last_java_pc,
 790                            Register scratch);
 791 
 792   void reset_last_Java_frame(Register thread);
 793 
 794   // thread in the default location (rthread)
 795   void reset_last_Java_frame(bool clear_fp);
 796 
 797   // Stores
 798   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 799   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 800 
 801   void resolve_jobject(Register value, Register thread, Register tmp);
 802 
 803   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 804   void c2bool(Register x);
 805 
 806   // oop manipulations
 807   void load_metadata(Register dst, Register src);
 808   void load_storage_props(Register dst, Register src);
 809 
 810   void load_klass(Register dst, Register src);
 811   void store_klass(Register dst, Register src);
 812   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 813 
 814   void resolve_oop_handle(Register result, Register tmp = r5);
 815   void load_mirror(Register dst, Register method, Register tmp = r5);
 816 
 817   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 818                       Register tmp1, Register tmp_thread);
 819 
 820   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 821                        Register tmp1, Register tmp_thread, Register tmp3 = noreg);
 822 
 823   // Resolves obj for access. Result is placed in the same register.
 824   // All other registers are preserved.
 825   void resolve(DecoratorSet decorators, Register obj);
 826 
 827   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 828                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 829 
 830   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 831                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 832   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 833                       Register tmp_thread = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
 834 
 835   // currently unimplemented
 836   // Used for storing NULL. All other oop constants should be
 837   // stored using routines that take a jobject.
 838   void store_heap_oop_null(Address dst);
 839 
 840   void load_prototype_header(Register dst, Register src);
 841 
 842   void store_klass_gap(Register dst, Register src);
 843 
 844   // This dummy is to prevent a call to store_heap_oop from
 845   // converting a zero (like NULL) into a Register by giving
 846   // the compiler two choices it can't resolve
 847 
 848   void store_heap_oop(Address dst, void* dummy);
 849 
 850   void encode_heap_oop(Register d, Register s);
 851   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 852   void decode_heap_oop(Register d, Register s);
 853   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 854   void encode_heap_oop_not_null(Register r);
 855   void decode_heap_oop_not_null(Register r);
 856   void encode_heap_oop_not_null(Register dst, Register src);
 857   void decode_heap_oop_not_null(Register dst, Register src);
 858 
 859   void set_narrow_oop(Register dst, jobject obj);
 860 
 861   void encode_klass_not_null(Register r);
 862   void decode_klass_not_null(Register r);
 863   void encode_klass_not_null(Register dst, Register src);
 864   void decode_klass_not_null(Register dst, Register src);
 865 
 866   void set_narrow_klass(Register dst, Klass* k);
 867 
 868   // if heap base register is used - reinit it with the correct value
 869   void reinit_heapbase();
 870 
 871   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 872 
 873   void push_CPU_state(bool save_vectors = false);
 874   void pop_CPU_state(bool restore_vectors = false) ;
 875 
 876   // Round up to a power of two
 877   void round_to(Register reg, int modulus);
 878 
 879   // allocation
 880   void eden_allocate(
 881     Register obj,                      // result: pointer to object after successful allocation
 882     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 883     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 884     Register t1,                       // temp register
 885     Label&   slow_case                 // continuation point if fast allocation fails
 886   );
 887   void tlab_allocate(
 888     Register obj,                      // result: pointer to object after successful allocation
 889     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 890     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 891     Register t1,                       // temp register
 892     Register t2,                       // temp register
 893     Label&   slow_case                 // continuation point if fast allocation fails
 894   );
 895   void zero_memory(Register addr, Register len, Register t1);
 896   void verify_tlab();
 897 
 898   // interface method calling
 899   void lookup_interface_method(Register recv_klass,
 900                                Register intf_klass,
 901                                RegisterOrConstant itable_index,
 902                                Register method_result,
 903                                Register scan_temp,
 904                                Label& no_such_interface,
 905                    bool return_method = true);
 906 
 907   // virtual method calling
 908   // n.b. x86 allows RegisterOrConstant for vtable_index
 909   void lookup_virtual_method(Register recv_klass,
 910                              RegisterOrConstant vtable_index,
 911                              Register method_result);
 912 
 913   // Test sub_klass against super_klass, with fast and slow paths.
 914 
 915   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 916   // One of the three labels can be NULL, meaning take the fall-through.
 917   // If super_check_offset is -1, the value is loaded up from super_klass.
 918   // No registers are killed, except temp_reg.
 919   void check_klass_subtype_fast_path(Register sub_klass,
 920                                      Register super_klass,
 921                                      Register temp_reg,
 922                                      Label* L_success,
 923                                      Label* L_failure,
 924                                      Label* L_slow_path,
 925                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 926 
 927   // The rest of the type check; must be wired to a corresponding fast path.
 928   // It does not repeat the fast path logic, so don't use it standalone.
 929   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 930   // Updates the sub's secondary super cache as necessary.
 931   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 932   void check_klass_subtype_slow_path(Register sub_klass,
 933                                      Register super_klass,
 934                                      Register temp_reg,
 935                                      Register temp2_reg,
 936                                      Label* L_success,
 937                                      Label* L_failure,
 938                                      bool set_cond_codes = false);
 939 
 940   // Simplified, combined version, good for typical uses.
 941   // Falls through on failure.
 942   void check_klass_subtype(Register sub_klass,
 943                            Register super_klass,
 944                            Register temp_reg,
 945                            Label& L_success);
 946 
 947   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 948 
 949 
 950   // Debugging
 951 
 952   // only if +VerifyOops
 953   void verify_oop(Register reg, const char* s = "broken oop");
 954   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 955 
 956 // TODO: verify method and klass metadata (compare against vptr?)
 957   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 958   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 959 
 960 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 961 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 962 
 963   // only if +VerifyFPU
 964   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 965 
 966   // prints msg, dumps registers and stops execution
 967   void stop(const char* msg);
 968 
 969   // prints msg and continues
 970   void warn(const char* msg);
 971 
 972   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 973 
 974   void untested()                                { stop("untested"); }
 975 
 976   void unimplemented(const char* what = "");
 977 
 978   void should_not_reach_here()                   { stop("should not reach here"); }
 979 
 980   // Stack overflow checking
 981   void bang_stack_with_offset(int offset) {
 982     // stack grows down, caller passes positive offset
 983     assert(offset > 0, "must bang with negative offset");
 984     sub(rscratch2, sp, offset);
 985     str(zr, Address(rscratch2));
 986   }
 987 
 988   // Writes to stack successive pages until offset reached to check for
 989   // stack overflow + shadow pages.  Also, clobbers tmp
 990   void bang_stack_size(Register size, Register tmp);
 991 
 992   // Check for reserved stack access in method being exited (for JIT)
 993   void reserved_stack_check();
 994 
 995   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 996                                                 Register tmp,
 997                                                 int offset);
 998 
 999   // Arithmetics
1000 
1001   void addptr(const Address &dst, int32_t src);
1002   void cmpptr(Register src1, Address src2);
1003 
1004   void cmpoop(Register obj1, Register obj2);
1005 
1006   // Various forms of CAS
1007 
1008   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1009                           Label &suceed, Label *fail);
1010   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1011                   Label &suceed, Label *fail);
1012 
1013   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1014                   Label &suceed, Label *fail);
1015 
1016   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1017   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1018   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1019   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1020 
1021   void atomic_xchg(Register prev, Register newv, Register addr);
1022   void atomic_xchgw(Register prev, Register newv, Register addr);
1023   void atomic_xchgal(Register prev, Register newv, Register addr);
1024   void atomic_xchgalw(Register prev, Register newv, Register addr);
1025 
1026   void orptr(Address adr, RegisterOrConstant src) {
1027     ldr(rscratch1, adr);
1028     if (src.is_register())
1029       orr(rscratch1, rscratch1, src.as_register());
1030     else
1031       orr(rscratch1, rscratch1, src.as_constant());
1032     str(rscratch1, adr);
1033   }
1034 
1035   // A generic CAS; success or failure is in the EQ flag.
1036   // Clobbers rscratch1
1037   void cmpxchg(Register addr, Register expected, Register new_val,
1038                enum operand_size size,
1039                bool acquire, bool release, bool weak,
1040                Register result);
1041 private:
1042   void compare_eq(Register rn, Register rm, enum operand_size size);
1043 
1044 public:
1045   // Calls
1046 
1047   address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1048 
1049   static bool far_branches() {
1050     return ReservedCodeCacheSize > branch_range || UseAOT;
1051   }
1052 
1053   // Jumps that can reach anywhere in the code cache.
1054   // Trashes tmp.
1055   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1056   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1057 
1058   static int far_branch_size() {
1059     if (far_branches()) {
1060       return 3 * 4;  // adrp, add, br
1061     } else {
1062       return 4;
1063     }
1064   }
1065 
1066   // Emit the CompiledIC call idiom
1067   address ic_call(address entry, jint method_index = 0);
1068 
1069 public:
1070 
1071   // Data
1072 
1073   void mov_metadata(Register dst, Metadata* obj);
1074   Address allocate_metadata_address(Metadata* obj);
1075   Address constant_oop_address(jobject obj);
1076 
1077   void movoop(Register dst, jobject obj, bool immediate = false);
1078 
1079   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1080   void kernel_crc32(Register crc, Register buf, Register len,
1081         Register table0, Register table1, Register table2, Register table3,
1082         Register tmp, Register tmp2, Register tmp3);
1083   // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1084   void kernel_crc32c(Register crc, Register buf, Register len,
1085         Register table0, Register table1, Register table2, Register table3,
1086         Register tmp, Register tmp2, Register tmp3);
1087 
1088   // Stack push and pop individual 64 bit registers
1089   void push(Register src);
1090   void pop(Register dst);
1091 
1092   // push all registers onto the stack
1093   void pusha();
1094   void popa();
1095 
1096   void repne_scan(Register addr, Register value, Register count,
1097                   Register scratch);
1098   void repne_scanw(Register addr, Register value, Register count,
1099                    Register scratch);
1100 
1101   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1102   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1103 
1104   // If a constant does not fit in an immediate field, generate some
1105   // number of MOV instructions and then perform the operation
1106   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1107                              add_sub_imm_insn insn1,
1108                              add_sub_reg_insn insn2);
1109   // Seperate vsn which sets the flags
1110   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1111                              add_sub_imm_insn insn1,
1112                              add_sub_reg_insn insn2);
1113 
1114 #define WRAP(INSN)                                                      \
1115   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1116     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1117   }                                                                     \
1118                                                                         \
1119   void INSN(Register Rd, Register Rn, Register Rm,                      \
1120              enum shift_kind kind, unsigned shift = 0) {                \
1121     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1122   }                                                                     \
1123                                                                         \
1124   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1125     Assembler::INSN(Rd, Rn, Rm);                                        \
1126   }                                                                     \
1127                                                                         \
1128   void INSN(Register Rd, Register Rn, Register Rm,                      \
1129            ext::operation option, int amount = 0) {                     \
1130     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1131   }
1132 
1133   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1134 
1135 #undef WRAP
1136 #define WRAP(INSN)                                                      \
1137   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1138     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1139   }                                                                     \
1140                                                                         \
1141   void INSN(Register Rd, Register Rn, Register Rm,                      \
1142              enum shift_kind kind, unsigned shift = 0) {                \
1143     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1144   }                                                                     \
1145                                                                         \
1146   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1147     Assembler::INSN(Rd, Rn, Rm);                                        \
1148   }                                                                     \
1149                                                                         \
1150   void INSN(Register Rd, Register Rn, Register Rm,                      \
1151            ext::operation option, int amount = 0) {                     \
1152     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1153   }
1154 
1155   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1156 
1157   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1158   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1159   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1160   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1161 
1162   void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1163 
1164 
1165   enum RegState {
1166      reg_readonly,
1167      reg_writable,
1168      reg_written
1169   };
1170 
1171   void verified_entry(Compile* C, int sp_inc);
1172 
1173   int store_value_type_fields_to_buf(ciValueKlass* vk, bool from_interpreter = true);
1174 
1175 // Unpack all value type arguments passed as oops 
1176   void unpack_value_args(Compile* C, bool receiver_only);
1177   bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[], int ret_off, int extra_stack_offset);
1178   bool unpack_value_helper(const GrowableArray<SigEntry>* sig, int& sig_index, VMReg from, VMRegPair* regs_to, int& to_index,
1179                            RegState reg_state[], int ret_off, int extra_stack_offset);
1180   bool pack_value_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1181                          VMReg to, VMRegPair* regs_from, int regs_from_count, int& from_index, RegState reg_state[],
1182                          int ret_off, int extra_stack_offset);
1183   void restore_stack(Compile* C);
1184 
1185   int shuffle_value_args(bool is_packing, bool receiver_only, int extra_stack_offset,
1186                          BasicType* sig_bt, const GrowableArray<SigEntry>* sig_cc,
1187                          int args_passed, int args_on_stack, VMRegPair* regs,
1188                          int args_passed_to, int args_on_stack_to, VMRegPair* regs_to);
1189   bool shuffle_value_args_spill(bool is_packing,  const GrowableArray<SigEntry>* sig_cc, int sig_cc_index,
1190                                 VMRegPair* regs_from, int from_index, int regs_from_count,
1191                                 RegState* reg_state, int sp_inc, int extra_stack_offset);
1192   VMReg spill_reg_for(VMReg reg);
1193 
1194 
1195   void tableswitch(Register index, jint lowbound, jint highbound,
1196                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1197     adr(rscratch1, jumptable);
1198     subsw(rscratch2, index, lowbound);
1199     subsw(zr, rscratch2, highbound - lowbound);
1200     br(Assembler::HS, jumptable_end);
1201     add(rscratch1, rscratch1, rscratch2,
1202         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1203     br(rscratch1);
1204   }
1205 
1206   // Form an address from base + offset in Rd.  Rd may or may not
1207   // actually be used: you must use the Address that is returned.  It
1208   // is up to you to ensure that the shift provided matches the size
1209   // of your data.
1210   Address form_address(Register Rd, Register base, long byte_offset, int shift);
1211 
1212   // Return true iff an address is within the 48-bit AArch64 address
1213   // space.
1214   bool is_valid_AArch64_address(address a) {
1215     return ((uint64_t)a >> 48) == 0;
1216   }
1217 
1218   // Load the base of the cardtable byte map into reg.
1219   void load_byte_map_base(Register reg);
1220 
1221   // Prolog generator routines to support switch between x86 code and
1222   // generated ARM code
1223 
1224   // routine to generate an x86 prolog for a stub function which
1225   // bootstraps into the generated ARM code which directly follows the
1226   // stub
1227   //
1228 
1229   public:
1230   // enum used for aarch64--x86 linkage to define return type of x86 function
1231   enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1232 
1233 #ifdef BUILTIN_SIM
1234   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1235 #else
1236   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1237 #endif
1238 
1239   // special version of call_VM_leaf_base needed for aarch64 simulator
1240   // where we need to specify both the gp and fp arg counts and the
1241   // return type so that the linkage routine from aarch64 to x86 and
1242   // back knows which aarch64 registers to copy to x86 registers and
1243   // which x86 result register to copy back to an aarch64 register
1244 
1245   void call_VM_leaf_base1(
1246     address  entry_point,             // the entry point
1247     int      number_of_gp_arguments,  // the number of gp reg arguments to pass
1248     int      number_of_fp_arguments,  // the number of fp reg arguments to pass
1249     ret_type type,                    // the return type for the call
1250     Label*   retaddr = NULL
1251   );
1252 
1253   void ldr_constant(Register dest, const Address &const_addr) {
1254     if (NearCpool) {
1255       ldr(dest, const_addr);
1256     } else {
1257       unsigned long offset;
1258       adrp(dest, InternalAddress(const_addr.target()), offset);
1259       ldr(dest, Address(dest, offset));
1260     }
1261   }
1262 
1263   address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1264   address read_polling_page(Register r, relocInfo::relocType rtype);
1265   void get_polling_page(Register dest, address page, relocInfo::relocType rtype);
1266 
1267   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1268   void update_byte_crc32(Register crc, Register val, Register table);
1269   void update_word_crc32(Register crc, Register v, Register tmp,
1270         Register table0, Register table1, Register table2, Register table3,
1271         bool upper = false);
1272 
1273   void string_compare(Register str1, Register str2,
1274                       Register cnt1, Register cnt2, Register result,
1275                       Register tmp1, Register tmp2, FloatRegister vtmp1,
1276                       FloatRegister vtmp2, FloatRegister vtmp3, int ae);
1277 
1278   void has_negatives(Register ary1, Register len, Register result);
1279 
1280   void arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1281                      Register tmp1, Register tmp2, Register tmp3, int elem_size);
1282 
1283   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1284                      int elem_size);
1285 
1286   void fill_words(Register base, Register cnt, Register value);
1287   void fill_words(Register base, u_int64_t cnt, Register value);
1288 
1289   void zero_words(Register base, u_int64_t cnt);
1290   void zero_words(Register ptr, Register cnt);
1291   void zero_dcache_blocks(Register base, Register cnt);
1292 
1293   static const int zero_words_block_size;
1294 
1295   void byte_array_inflate(Register src, Register dst, Register len,
1296                           FloatRegister vtmp1, FloatRegister vtmp2,
1297                           FloatRegister vtmp3, Register tmp4);
1298 
1299   void char_array_compress(Register src, Register dst, Register len,
1300                            FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1301                            FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1302                            Register result);
1303 
1304   void encode_iso_array(Register src, Register dst,
1305                         Register len, Register result,
1306                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1307                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1308   void string_indexof(Register str1, Register str2,
1309                       Register cnt1, Register cnt2,
1310                       Register tmp1, Register tmp2,
1311                       Register tmp3, Register tmp4,
1312                       Register tmp5, Register tmp6,
1313                       int int_cnt1, Register result, int ae);
1314   void string_indexof_char(Register str1, Register cnt1,
1315                            Register ch, Register result,
1316                            Register tmp1, Register tmp2, Register tmp3);
1317   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1318                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1319                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1320                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1321                 Register tmp3, Register tmp4, Register tmp5);
1322   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1323       address pio2, address dsin_coef, address dcos_coef);
1324  private:
1325   // begin trigonometric functions support block
1326   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1327   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1328   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1329   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1330   // end trigonometric functions support block
1331   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1332                        Register src1, Register src2);
1333   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1334     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1335   }
1336   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1337                              Register y, Register y_idx, Register z,
1338                              Register carry, Register product,
1339                              Register idx, Register kdx);
1340   void multiply_128_x_128_loop(Register y, Register z,
1341                                Register carry, Register carry2,
1342                                Register idx, Register jdx,
1343                                Register yz_idx1, Register yz_idx2,
1344                                Register tmp, Register tmp3, Register tmp4,
1345                                Register tmp7, Register product_hi);
1346   void kernel_crc32_using_crc32(Register crc, Register buf,
1347         Register len, Register tmp0, Register tmp1, Register tmp2,
1348         Register tmp3);
1349   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1350         Register len, Register tmp0, Register tmp1, Register tmp2,
1351         Register tmp3);
1352 public:
1353   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1354                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1355                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1356   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1357   // ISB may be needed because of a safepoint
1358   void maybe_isb() { isb(); }
1359 
1360 private:
1361   // Return the effective address r + (r1 << ext) + offset.
1362   // Uses rscratch2.
1363   Address offsetted_address(Register r, Register r1, Address::extend ext,
1364                             int offset, int size);
1365 
1366 private:
1367   // Returns an address on the stack which is reachable with a ldr/str of size
1368   // Uses rscratch2 if the address is not directly reachable
1369   Address spill_address(int size, int offset, Register tmp=rscratch2);
1370 
1371   bool merge_alignment_check(Register base, size_t size, long cur_offset, long prev_offset) const;
1372 
1373   // Check whether two loads/stores can be merged into ldp/stp.
1374   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1375 
1376   // Merge current load/store with previous load/store into ldp/stp.
1377   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1378 
1379   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1380   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1381 
1382 public:
1383   void spill(Register Rx, bool is64, int offset) {
1384     if (is64) {
1385       str(Rx, spill_address(8, offset));
1386     } else {
1387       strw(Rx, spill_address(4, offset));
1388     }
1389   }
1390   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1391     str(Vx, T, spill_address(1 << (int)T, offset));
1392   }
1393   void unspill(Register Rx, bool is64, int offset) {
1394     if (is64) {
1395       ldr(Rx, spill_address(8, offset));
1396     } else {
1397       ldrw(Rx, spill_address(4, offset));
1398     }
1399   }
1400   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1401     ldr(Vx, T, spill_address(1 << (int)T, offset));
1402   }
1403   void spill_copy128(int src_offset, int dst_offset,
1404                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1405     if (src_offset < 512 && (src_offset & 7) == 0 &&
1406         dst_offset < 512 && (dst_offset & 7) == 0) {
1407       ldp(tmp1, tmp2, Address(sp, src_offset));
1408       stp(tmp1, tmp2, Address(sp, dst_offset));
1409     } else {
1410       unspill(tmp1, true, src_offset);
1411       spill(tmp1, true, dst_offset);
1412       unspill(tmp1, true, src_offset+8);
1413       spill(tmp1, true, dst_offset+8);
1414     }
1415   }
1416 
1417   #include "asm/macroAssembler_common.hpp"
1418 
1419 };
1420 
1421 #ifdef ASSERT
1422 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1423 #endif
1424 
1425 /**
1426  * class SkipIfEqual:
1427  *
1428  * Instantiating this class will result in assembly code being output that will
1429  * jump around any code emitted between the creation of the instance and it's
1430  * automatic destruction at the end of a scope block, depending on the value of
1431  * the flag passed to the constructor, which will be checked at run-time.
1432  */
1433 class SkipIfEqual {
1434  private:
1435   MacroAssembler* _masm;
1436   Label _label;
1437 
1438  public:
1439    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1440    ~SkipIfEqual();
1441 };
1442 
1443 struct tableswitch {
1444   Register _reg;
1445   int _insn_index; jint _first_key; jint _last_key;
1446   Label _after;
1447   Label _branches;
1448 };
1449 
1450 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP