1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/globalDefinitions.hpp"
37 #include "utilities/macros.hpp"
38 #include "utilities/powerOfTwo.hpp"
39 #include "runtime/signature.hpp"
40
41
42 class ciInlineKlass;
43
44 class OopMap;
45
46 // MacroAssembler extends Assembler by frequently used macros.
47 //
48 // Instructions for which a 'better' code sequence exists depending
49 // on arguments should also go in here.
50
51 class MacroAssembler: public Assembler {
52 friend class LIR_Assembler;
53
54 public:
55 using Assembler::mov;
56 using Assembler::movi;
57
58 protected:
59
60 // Support for VM calls
61 //
62 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
63 // may customize this version by overriding it for its purposes (e.g., to save/restore
64 // additional registers when doing a VM call).
65 virtual void call_VM_leaf_base(
66 address entry_point, // the entry point
67 int number_of_arguments, // the number of arguments to pop after the call
68 Label *retaddr = nullptr
69 );
70
71 virtual void call_VM_leaf_base(
72 address entry_point, // the entry point
73 int number_of_arguments, // the number of arguments to pop after the call
74 Label &retaddr) {
75 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
76 }
77
78 // This is the base routine called by the different versions of call_VM. The interpreter
79 // may customize this version by overriding it for its purposes (e.g., to save/restore
80 // additional registers when doing a VM call).
81 //
82 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
83 // returns the register which contains the thread upon return. If a thread register has been
84 // specified, the return value will correspond to that register. If no last_java_sp is specified
85 // (noreg) than rsp will be used instead.
86 virtual void call_VM_base( // returns the register containing the thread upon return
87 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
88 Register java_thread, // the thread if computed before ; use noreg otherwise
89 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
90 Label* return_pc, // to set up last_Java_frame; use nullptr otherwise
91 address entry_point, // the entry point
92 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
93 bool check_exceptions // whether to check for pending exceptions after return
94 );
95
96 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
97
98 enum KlassDecodeMode {
99 KlassDecodeNone,
100 KlassDecodeZero,
101 KlassDecodeXor,
102 KlassDecodeMovk
103 };
104
105 // Calculate decoding mode based on given parameters, used for checking then ultimately setting.
106 static KlassDecodeMode klass_decode_mode(address base, int shift, const size_t range);
107
108 private:
109 static KlassDecodeMode _klass_decode_mode;
110
111 // Returns above setting with asserts
112 static KlassDecodeMode klass_decode_mode();
113
114 public:
115 // Checks the decode mode and returns false if not compatible with preferred decoding mode.
116 static bool check_klass_decode_mode(address base, int shift, const size_t range);
117
118 // Sets the decode mode and returns false if cannot be set.
119 static bool set_klass_decode_mode(address base, int shift, const size_t range);
120
121 public:
122 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
123
124 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
125 // The implementation is only non-empty for the InterpreterMacroAssembler,
126 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
127 virtual void check_and_handle_popframe(Register java_thread);
128 virtual void check_and_handle_earlyret(Register java_thread);
129
130 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp = rscratch1);
131 void rt_call(address dest, Register tmp = rscratch1);
132
133 // Load Effective Address
134 void lea(Register r, const Address &a) {
135 InstructionMark im(this);
136 a.lea(this, r);
137 }
138
139 // Whether materializing the given address for a LDR/STR requires an
140 // additional lea instruction.
141 static bool legitimize_address_requires_lea(const Address &a, int size) {
142 return a.getMode() == Address::base_plus_offset &&
143 !Address::offset_ok_for_immed(a.offset(), exact_log2(size));
144 }
145
146 /* Sometimes we get misaligned loads and stores, usually from Unsafe
147 accesses, and these can exceed the offset range. */
148 Address legitimize_address(const Address &a, int size, Register scratch) {
149 if (legitimize_address_requires_lea(a, size)) {
150 block_comment("legitimize_address {");
151 lea(scratch, a);
152 block_comment("} legitimize_address");
153 return Address(scratch);
154 }
155 return a;
156 }
157
158 void addmw(Address a, Register incr, Register scratch) {
159 ldrw(scratch, a);
160 addw(scratch, scratch, incr);
161 strw(scratch, a);
162 }
163
164 // Add constant to memory word
165 void addmw(Address a, int imm, Register scratch) {
166 ldrw(scratch, a);
167 if (imm > 0)
168 addw(scratch, scratch, (unsigned)imm);
169 else
170 subw(scratch, scratch, (unsigned)-imm);
171 strw(scratch, a);
172 }
173
174 void bind(Label& L) {
175 Assembler::bind(L);
176 code()->clear_last_insn();
177 code()->set_last_label(pc());
178 }
179
180 void membar(Membar_mask_bits order_constraint);
181
182 using Assembler::ldr;
183 using Assembler::str;
184 using Assembler::ldrw;
185 using Assembler::strw;
186
187 void ldr(Register Rx, const Address &adr);
188 void ldrw(Register Rw, const Address &adr);
189 void str(Register Rx, const Address &adr);
190 void strw(Register Rx, const Address &adr);
191
192 // Frame creation and destruction shared between JITs.
193 DEBUG_ONLY(void build_frame(int framesize);)
194 void build_frame(int framesize DEBUG_ONLY(COMMA bool zap_rfp_lr_spills));
195 void remove_frame(int framesize);
196
197 virtual void _call_Unimplemented(address call_site) {
198 mov(rscratch2, call_site);
199 }
200
201 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
202 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
203 // https://reviews.llvm.org/D3311
204
205 #ifdef _WIN64
206 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
207 #else
208 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
209 #endif
210
211 // aliases defined in AARCH64 spec
212
213 template<class T>
214 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
215
216 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
217 inline void cmp(Register Rd, unsigned imm) = delete;
218
219 template<class T>
220 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
221
222 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
223 inline void cmn(Register Rd, unsigned imm) = delete;
224
225 void cset(Register Rd, Assembler::Condition cond) {
226 csinc(Rd, zr, zr, ~cond);
227 }
228 void csetw(Register Rd, Assembler::Condition cond) {
229 csincw(Rd, zr, zr, ~cond);
230 }
231
232 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
233 csneg(Rd, Rn, Rn, ~cond);
234 }
235 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
236 csnegw(Rd, Rn, Rn, ~cond);
237 }
238
239 inline void movw(Register Rd, Register Rn) {
240 if (Rd == sp || Rn == sp) {
241 Assembler::addw(Rd, Rn, 0U);
242 } else {
243 orrw(Rd, zr, Rn);
244 }
245 }
246 inline void mov(Register Rd, Register Rn) {
247 assert(Rd != r31_sp && Rn != r31_sp, "should be");
248 if (Rd == Rn) {
249 } else if (Rd == sp || Rn == sp) {
250 Assembler::add(Rd, Rn, 0U);
251 } else {
252 orr(Rd, zr, Rn);
253 }
254 }
255
256 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
257 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
258
259 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
260 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
261
262 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
263 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
264
265 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
266 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
267 }
268 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
269 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
270 }
271
272 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
273 bfmw(Rd, Rn, lsb, (lsb + width - 1));
274 }
275 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
276 bfm(Rd, Rn, lsb , (lsb + width - 1));
277 }
278
279 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
280 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
281 }
282 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
283 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
284 }
285
286 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
287 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
288 }
289 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
290 sbfm(Rd, Rn, lsb , (lsb + width - 1));
291 }
292
293 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
294 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
295 }
296 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
297 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
298 }
299
300 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
301 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
302 }
303 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
304 ubfm(Rd, Rn, lsb , (lsb + width - 1));
305 }
306
307 inline void asrw(Register Rd, Register Rn, unsigned imm) {
308 sbfmw(Rd, Rn, imm, 31);
309 }
310
311 inline void asr(Register Rd, Register Rn, unsigned imm) {
312 sbfm(Rd, Rn, imm, 63);
313 }
314
315 inline void lslw(Register Rd, Register Rn, unsigned imm) {
316 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
317 }
318
319 inline void lsl(Register Rd, Register Rn, unsigned imm) {
320 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
321 }
322
323 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
324 ubfmw(Rd, Rn, imm, 31);
325 }
326
327 inline void lsr(Register Rd, Register Rn, unsigned imm) {
328 ubfm(Rd, Rn, imm, 63);
329 }
330
331 inline void rorw(Register Rd, Register Rn, unsigned imm) {
332 extrw(Rd, Rn, Rn, imm);
333 }
334
335 inline void ror(Register Rd, Register Rn, unsigned imm) {
336 extr(Rd, Rn, Rn, imm);
337 }
338
339 inline void rolw(Register Rd, Register Rn, unsigned imm) {
340 extrw(Rd, Rn, Rn, (32 - imm));
341 }
342
343 inline void rol(Register Rd, Register Rn, unsigned imm) {
344 extr(Rd, Rn, Rn, (64 - imm));
345 }
346
347 using Assembler::rax1;
348 using Assembler::eor3;
349
350 inline void rax1(Register Rd, Register Rn, Register Rm) {
351 eor(Rd, Rn, Rm, ROR, 63); // Rd = Rn ^ rol(Rm, 1)
352 }
353
354 inline void eor3(Register Rd, Register Rn, Register Rm, Register Rk) {
355 assert(Rd != Rn, "Use tmp register");
356 eor(Rd, Rm, Rk);
357 eor(Rd, Rd, Rn);
358 }
359
360 inline void sxtbw(Register Rd, Register Rn) {
361 sbfmw(Rd, Rn, 0, 7);
362 }
363 inline void sxthw(Register Rd, Register Rn) {
364 sbfmw(Rd, Rn, 0, 15);
365 }
366 inline void sxtb(Register Rd, Register Rn) {
367 sbfm(Rd, Rn, 0, 7);
368 }
369 inline void sxth(Register Rd, Register Rn) {
370 sbfm(Rd, Rn, 0, 15);
371 }
372 inline void sxtw(Register Rd, Register Rn) {
373 sbfm(Rd, Rn, 0, 31);
374 }
375
376 inline void uxtbw(Register Rd, Register Rn) {
377 ubfmw(Rd, Rn, 0, 7);
378 }
379 inline void uxthw(Register Rd, Register Rn) {
380 ubfmw(Rd, Rn, 0, 15);
381 }
382 inline void uxtb(Register Rd, Register Rn) {
383 ubfm(Rd, Rn, 0, 7);
384 }
385 inline void uxth(Register Rd, Register Rn) {
386 ubfm(Rd, Rn, 0, 15);
387 }
388 inline void uxtw(Register Rd, Register Rn) {
389 ubfm(Rd, Rn, 0, 31);
390 }
391
392 inline void cmnw(Register Rn, Register Rm) {
393 addsw(zr, Rn, Rm);
394 }
395 inline void cmn(Register Rn, Register Rm) {
396 adds(zr, Rn, Rm);
397 }
398
399 inline void cmpw(Register Rn, Register Rm) {
400 subsw(zr, Rn, Rm);
401 }
402 inline void cmp(Register Rn, Register Rm) {
403 subs(zr, Rn, Rm);
404 }
405
406 inline void negw(Register Rd, Register Rn) {
407 subw(Rd, zr, Rn);
408 }
409
410 inline void neg(Register Rd, Register Rn) {
411 sub(Rd, zr, Rn);
412 }
413
414 inline void negsw(Register Rd, Register Rn) {
415 subsw(Rd, zr, Rn);
416 }
417
418 inline void negs(Register Rd, Register Rn) {
419 subs(Rd, zr, Rn);
420 }
421
422 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
423 addsw(zr, Rn, Rm, kind, shift);
424 }
425 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
426 adds(zr, Rn, Rm, kind, shift);
427 }
428
429 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
430 subsw(zr, Rn, Rm, kind, shift);
431 }
432 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
433 subs(zr, Rn, Rm, kind, shift);
434 }
435
436 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
437 subw(Rd, zr, Rn, kind, shift);
438 }
439
440 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
441 sub(Rd, zr, Rn, kind, shift);
442 }
443
444 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
445 subsw(Rd, zr, Rn, kind, shift);
446 }
447
448 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
449 subs(Rd, zr, Rn, kind, shift);
450 }
451
452 inline void mnegw(Register Rd, Register Rn, Register Rm) {
453 msubw(Rd, Rn, Rm, zr);
454 }
455 inline void mneg(Register Rd, Register Rn, Register Rm) {
456 msub(Rd, Rn, Rm, zr);
457 }
458
459 inline void mulw(Register Rd, Register Rn, Register Rm) {
460 maddw(Rd, Rn, Rm, zr);
461 }
462 inline void mul(Register Rd, Register Rn, Register Rm) {
463 madd(Rd, Rn, Rm, zr);
464 }
465
466 inline void smnegl(Register Rd, Register Rn, Register Rm) {
467 smsubl(Rd, Rn, Rm, zr);
468 }
469 inline void smull(Register Rd, Register Rn, Register Rm) {
470 smaddl(Rd, Rn, Rm, zr);
471 }
472
473 inline void umnegl(Register Rd, Register Rn, Register Rm) {
474 umsubl(Rd, Rn, Rm, zr);
475 }
476 inline void umull(Register Rd, Register Rn, Register Rm) {
477 umaddl(Rd, Rn, Rm, zr);
478 }
479
480 #define WRAP(INSN) \
481 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
482 if (VM_Version::supports_a53mac() && Ra != zr) \
483 nop(); \
484 Assembler::INSN(Rd, Rn, Rm, Ra); \
485 }
486
487 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
488 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
489 #undef WRAP
490
491
492 // macro assembly operations needed for aarch64
493
494 public:
495
496 enum FpPushPopMode {
497 PushPopFull,
498 PushPopSVE,
499 PushPopNeon,
500 PushPopFp
501 };
502
503 // first two private routines for loading 32 bit or 64 bit constants
504 private:
505
506 void mov_immediate64(Register dst, uint64_t imm64);
507 void mov_immediate32(Register dst, uint32_t imm32);
508
509 void mov(Register dst, Address a);
510
511 public:
512
513 int push(RegSet regset, Register stack);
514 int pop(RegSet regset, Register stack);
515
516 int push_fp(FloatRegSet regset, Register stack, FpPushPopMode mode = PushPopFull);
517 int pop_fp(FloatRegSet regset, Register stack, FpPushPopMode mode = PushPopFull);
518
519 static RegSet call_clobbered_gp_registers();
520
521 int push_p(PRegSet regset, Register stack);
522 int pop_p(PRegSet regset, Register stack);
523
524 // Push and pop everything that might be clobbered by a native
525 // runtime call except rscratch1 and rscratch2. (They are always
526 // scratch, so we don't have to protect them.) Only save the lower
527 // 64 bits of each vector register. Additional registers can be excluded
528 // in a passed RegSet.
529 void push_call_clobbered_registers_except(RegSet exclude);
530 void pop_call_clobbered_registers_except(RegSet exclude);
531
532 void push_call_clobbered_registers() {
533 push_call_clobbered_registers_except(RegSet());
534 }
535 void pop_call_clobbered_registers() {
536 pop_call_clobbered_registers_except(RegSet());
537 }
538
539
540 // now mov instructions for loading absolute addresses and 32 or
541 // 64 bit integers
542
543 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
544
545 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
546 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
547
548 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
549
550 void mov(Register dst, RegisterOrConstant src) {
551 if (src.is_register())
552 mov(dst, src.as_register());
553 else
554 mov(dst, src.as_constant());
555 }
556
557 void movptr(Register r, uintptr_t imm64);
558
559 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
560
561 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
562 orr(Vd, T, Vn, Vn);
563 }
564
565 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
566 fcvtsh(tmp, src);
567 smov(dst, tmp, H, 0);
568 }
569
570 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
571 mov(tmp, H, 0, src);
572 fcvths(dst, tmp);
573 }
574
575 // Generalized Test Bit And Branch, including a "far" variety which
576 // spans more than 32KiB.
577 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
578 assert(cond == EQ || cond == NE, "must be");
579
580 if (isfar)
581 cond = ~cond;
582
583 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
584 if (cond == Assembler::EQ)
585 branch = &Assembler::tbz;
586 else
587 branch = &Assembler::tbnz;
588
589 if (isfar) {
590 Label L;
591 (this->*branch)(Rt, bitpos, L);
592 b(dest);
593 bind(L);
594 } else {
595 (this->*branch)(Rt, bitpos, dest);
596 }
597 }
598
599 // macro instructions for accessing and updating floating point
600 // status register
601 //
602 // FPSR : op1 == 011
603 // CRn == 0100
604 // CRm == 0100
605 // op2 == 001
606
607 inline void get_fpsr(Register reg)
608 {
609 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
610 }
611
612 inline void set_fpsr(Register reg)
613 {
614 msr(0b011, 0b0100, 0b0100, 0b001, reg);
615 }
616
617 inline void clear_fpsr()
618 {
619 msr(0b011, 0b0100, 0b0100, 0b001, zr);
620 }
621
622 // FPCR : op1 == 011
623 // CRn == 0100
624 // CRm == 0100
625 // op2 == 000
626
627 inline void get_fpcr(Register reg) {
628 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
629 }
630
631 inline void set_fpcr(Register reg) {
632 msr(0b011, 0b0100, 0b0100, 0b000, reg);
633 }
634
635 // DCZID_EL0: op1 == 011
636 // CRn == 0000
637 // CRm == 0000
638 // op2 == 111
639 inline void get_dczid_el0(Register reg)
640 {
641 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
642 }
643
644 // CTR_EL0: op1 == 011
645 // CRn == 0000
646 // CRm == 0000
647 // op2 == 001
648 inline void get_ctr_el0(Register reg)
649 {
650 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
651 }
652
653 inline void get_nzcv(Register reg) {
654 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
655 }
656
657 inline void set_nzcv(Register reg) {
658 msr(0b011, 0b0100, 0b0010, 0b000, reg);
659 }
660
661 // CNTVCTSS_EL0: op1 == 011
662 // CRn == 1110
663 // CRm == 0000
664 // op2 == 110
665 inline void get_cntvctss_el0(Register reg) {
666 mrs(0b011, 0b1110, 0b0000, 0b110, reg);
667 }
668
669 // idiv variant which deals with MINLONG as dividend and -1 as divisor
670 int corrected_idivl(Register result, Register ra, Register rb,
671 bool want_remainder, Register tmp = rscratch1);
672 int corrected_idivq(Register result, Register ra, Register rb,
673 bool want_remainder, Register tmp = rscratch1);
674
675 // Support for null-checks
676 //
677 // Generates code that causes a null OS exception if the content of reg is null.
678 // If the accessed location is M[reg + offset] and the offset is known, provide the
679 // offset. No explicit code generation is needed if the offset is within a certain
680 // range (0 <= offset <= page_size).
681
682 virtual void null_check(Register reg, int offset = -1);
683 static bool needs_explicit_null_check(intptr_t offset);
684 static bool uses_implicit_null_check(void* address);
685
686 // markWord tests, kills markWord reg
687 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
688
689 // inlineKlass queries, kills temp_reg
690 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
691
692 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
693 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
694 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
695 void test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker);
696
697 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
698 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
699 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
700 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
701 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
702 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
703
704 // Check array klass layout helper for flat or null-free arrays...
705 void test_flat_array_layout(Register lh, Label& is_flat_array);
706 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array);
707
708 static address target_addr_for_insn(address insn_addr);
709
710 // Required platform-specific helpers for Label::patch_instructions.
711 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
712 static int pd_patch_instruction_size(address branch, address target);
713 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
714 pd_patch_instruction_size(branch, target);
715 }
716 static address pd_call_destination(address branch) {
717 return target_addr_for_insn(branch);
718 }
719 #ifndef PRODUCT
720 static void pd_print_patched_instruction(address branch);
721 #endif
722
723 static int patch_oop(address insn_addr, address o);
724 static int patch_narrow_klass(address insn_addr, narrowKlass n);
725
726 // Return whether code is emitted to a scratch blob.
727 virtual bool in_scratch_emit_size() {
728 return false;
729 }
730 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
731 static int max_trampoline_stub_size();
732 void emit_static_call_stub();
733 static int static_call_stub_size();
734
735 // The following 4 methods return the offset of the appropriate move instruction
736
737 // Support for fast byte/short loading with zero extension (depending on particular CPU)
738 int load_unsigned_byte(Register dst, Address src);
739 int load_unsigned_short(Register dst, Address src);
740
741 // Support for fast byte/short loading with sign extension (depending on particular CPU)
742 int load_signed_byte(Register dst, Address src);
743 int load_signed_short(Register dst, Address src);
744
745 int load_signed_byte32(Register dst, Address src);
746 int load_signed_short32(Register dst, Address src);
747
748 // Support for sign-extension (hi:lo = extend_sign(lo))
749 void extend_sign(Register hi, Register lo);
750
751 // Clean up a subword typed value to the representation in compliance with JVMS ยง2.3
752 void narrow_subword_type(Register reg, BasicType bt);
753
754 // Load and store values by size and signed-ness
755 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
756 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
757
758 // Support for inc/dec with optimal instruction selection depending on value
759
760 // x86_64 aliases an unqualified register/address increment and
761 // decrement to call incrementq and decrementq but also supports
762 // explicitly sized calls to incrementq/decrementq or
763 // incrementl/decrementl
764
765 // for aarch64 the proper convention would be to use
766 // increment/decrement for 64 bit operations and
767 // incrementw/decrementw for 32 bit operations. so when porting
768 // x86_64 code we can leave calls to increment/decrement as is,
769 // replace incrementq/decrementq with increment/decrement and
770 // replace incrementl/decrementl with incrementw/decrementw.
771
772 // n.b. increment/decrement calls with an Address destination will
773 // need to use a scratch register to load the value to be
774 // incremented. increment/decrement calls which add or subtract a
775 // constant value greater than 2^12 will need to use a 2nd scratch
776 // register to hold the constant. so, a register increment/decrement
777 // may trash rscratch2 and an address increment/decrement trash
778 // rscratch and rscratch2
779
780 void decrementw(Address dst, int value = 1);
781 void decrementw(Register reg, int value = 1);
782
783 void decrement(Register reg, int value = 1);
784 void decrement(Address dst, int value = 1);
785
786 void incrementw(Address dst, int value = 1);
787 void incrementw(Register reg, int value = 1);
788
789 void increment(Register reg, int value = 1);
790 void increment(Address dst, int value = 1);
791
792
793 // Alignment
794 void align(int modulus);
795 void align(int modulus, int target);
796
797 // nop
798 void post_call_nop();
799
800 // Stack frame creation/removal
801 void enter(bool strip_ret_addr = false);
802 void leave();
803
804 // ROP Protection
805 void protect_return_address();
806 void protect_return_address(Register return_reg);
807 void authenticate_return_address();
808 void authenticate_return_address(Register return_reg);
809 void strip_return_address();
810 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
811
812 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
813 // The pointer will be loaded into the thread register.
814 void get_thread(Register thread);
815
816 // support for argument shuffling
817 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
818 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
819 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
820 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
821 void object_move(
822 OopMap* map,
823 int oop_handle_offset,
824 int framesize_in_slots,
825 VMRegPair src,
826 VMRegPair dst,
827 bool is_receiver,
828 int* receiver_offset);
829
830
831 // Support for VM calls
832 //
833 // It is imperative that all calls into the VM are handled via the call_VM macros.
834 // They make sure that the stack linkage is setup correctly. call_VM's correspond
835 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
836
837
838 void call_VM(Register oop_result,
839 address entry_point,
840 bool check_exceptions = true);
841 void call_VM(Register oop_result,
842 address entry_point,
843 Register arg_1,
844 bool check_exceptions = true);
845 void call_VM(Register oop_result,
846 address entry_point,
847 Register arg_1, Register arg_2,
848 bool check_exceptions = true);
849 void call_VM(Register oop_result,
850 address entry_point,
851 Register arg_1, Register arg_2, Register arg_3,
852 bool check_exceptions = true);
853
854 // Overloadings with last_Java_sp
855 void call_VM(Register oop_result,
856 Register last_java_sp,
857 address entry_point,
858 int number_of_arguments = 0,
859 bool check_exceptions = true);
860 void call_VM(Register oop_result,
861 Register last_java_sp,
862 address entry_point,
863 Register arg_1, bool
864 check_exceptions = true);
865 void call_VM(Register oop_result,
866 Register last_java_sp,
867 address entry_point,
868 Register arg_1, Register arg_2,
869 bool check_exceptions = true);
870 void call_VM(Register oop_result,
871 Register last_java_sp,
872 address entry_point,
873 Register arg_1, Register arg_2, Register arg_3,
874 bool check_exceptions = true);
875
876 void get_vm_result_oop(Register oop_result, Register thread);
877 void get_vm_result_metadata(Register metadata_result, Register thread);
878
879 // These always tightly bind to MacroAssembler::call_VM_base
880 // bypassing the virtual implementation
881 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
882 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
883 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
884 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
885 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
886
887 void call_VM_leaf(address entry_point,
888 int number_of_arguments = 0);
889 void call_VM_leaf(address entry_point,
890 Register arg_1);
891 void call_VM_leaf(address entry_point,
892 Register arg_1, Register arg_2);
893 void call_VM_leaf(address entry_point,
894 Register arg_1, Register arg_2, Register arg_3);
895
896 // These always tightly bind to MacroAssembler::call_VM_leaf_base
897 // bypassing the virtual implementation
898 void super_call_VM_leaf(address entry_point);
899 void super_call_VM_leaf(address entry_point, Register arg_1);
900 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
901 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
902 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
903
904 // last Java Frame (fills frame anchor)
905 void set_last_Java_frame(Register last_java_sp,
906 Register last_java_fp,
907 address last_java_pc,
908 Register scratch);
909
910 void set_last_Java_frame(Register last_java_sp,
911 Register last_java_fp,
912 Label &last_java_pc,
913 Register scratch);
914
915 void set_last_Java_frame(Register last_java_sp,
916 Register last_java_fp,
917 Register last_java_pc,
918 Register scratch);
919
920 void reset_last_Java_frame(Register thread);
921
922 // thread in the default location (rthread)
923 void reset_last_Java_frame(bool clear_fp);
924
925 void resolve_jobject(Register value, Register tmp1, Register tmp2);
926 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
927
928 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
929 void c2bool(Register x);
930
931 void load_method_holder_cld(Register rresult, Register rmethod);
932 void load_method_holder(Register holder, Register method);
933
934 // oop manipulations
935 void load_metadata(Register dst, Register src);
936
937 void load_narrow_klass_compact(Register dst, Register src);
938 void load_klass(Register dst, Register src);
939 void store_klass(Register dst, Register src);
940 void cmp_klass(Register obj, Register klass, Register tmp);
941 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
942
943 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
944 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
945 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
946
947 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
948 Register tmp1, Register tmp2);
949
950 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
951 Register tmp1, Register tmp2, Register tmp3);
952
953 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
954
955 // inline type data payload offsets...
956 void payload_offset(Register inline_klass, Register offset);
957 void payload_address(Register oop, Register data, Register inline_klass);
958 // get data payload ptr a flat value array at index, kills rcx and index
959 void data_for_value_array_index(Register array, Register array_klass,
960 Register index, Register data);
961
962 void load_heap_oop(Register dst, Address src, Register tmp1,
963 Register tmp2, DecoratorSet decorators = 0);
964
965 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
966 Register tmp2, DecoratorSet decorators = 0);
967 void store_heap_oop(Address dst, Register val, Register tmp1,
968 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
969
970 // currently unimplemented
971 // Used for storing null. All other oop constants should be
972 // stored using routines that take a jobject.
973 void store_heap_oop_null(Address dst);
974
975 void load_prototype_header(Register dst, Register src);
976
977 void store_klass_gap(Register dst, Register src);
978
979 // This dummy is to prevent a call to store_heap_oop from
980 // converting a zero (like null) into a Register by giving
981 // the compiler two choices it can't resolve
982
983 void store_heap_oop(Address dst, void* dummy);
984
985 void encode_heap_oop(Register d, Register s);
986 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
987 void decode_heap_oop(Register d, Register s);
988 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
989 void encode_heap_oop_not_null(Register r);
990 void decode_heap_oop_not_null(Register r);
991 void encode_heap_oop_not_null(Register dst, Register src);
992 void decode_heap_oop_not_null(Register dst, Register src);
993
994 void set_narrow_oop(Register dst, jobject obj);
995
996 void decode_klass_not_null_for_aot(Register dst, Register src);
997 void encode_klass_not_null_for_aot(Register dst, Register src);
998 void encode_klass_not_null(Register r);
999 void decode_klass_not_null(Register r);
1000 void encode_klass_not_null(Register dst, Register src);
1001 void decode_klass_not_null(Register dst, Register src);
1002
1003 void set_narrow_klass(Register dst, Klass* k);
1004
1005 // if heap base register is used - reinit it with the correct value
1006 void reinit_heapbase();
1007
1008 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1009
1010 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
1011 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1012 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
1013 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1014
1015 void push_cont_fastpath(Register java_thread = rthread);
1016 void pop_cont_fastpath(Register java_thread = rthread);
1017
1018 // Round up to a power of two
1019 void round_to(Register reg, int modulus);
1020
1021 // java.lang.Math::round intrinsics
1022 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1023 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1024
1025 // allocation
1026
1027 void tlab_allocate(
1028 Register obj, // result: pointer to object after successful allocation
1029 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1030 int con_size_in_bytes, // object size in bytes if known at compile time
1031 Register t1, // temp register
1032 Register t2, // temp register
1033 Label& slow_case // continuation point if fast allocation fails
1034 );
1035 void verify_tlab();
1036
1037 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
1038
1039 // interface method calling
1040 void lookup_interface_method(Register recv_klass,
1041 Register intf_klass,
1042 RegisterOrConstant itable_index,
1043 Register method_result,
1044 Register scan_temp,
1045 Label& no_such_interface,
1046 bool return_method = true);
1047
1048 void lookup_interface_method_stub(Register recv_klass,
1049 Register holder_klass,
1050 Register resolved_klass,
1051 Register method_result,
1052 Register temp_reg,
1053 Register temp_reg2,
1054 int itable_index,
1055 Label& L_no_such_interface);
1056
1057 // virtual method calling
1058 // n.b. x86 allows RegisterOrConstant for vtable_index
1059 void lookup_virtual_method(Register recv_klass,
1060 RegisterOrConstant vtable_index,
1061 Register method_result);
1062
1063 // Test sub_klass against super_klass, with fast and slow paths.
1064
1065 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1066 // One of the three labels can be null, meaning take the fall-through.
1067 // If super_check_offset is -1, the value is loaded up from super_klass.
1068 // No registers are killed, except temp_reg.
1069 void check_klass_subtype_fast_path(Register sub_klass,
1070 Register super_klass,
1071 Register temp_reg,
1072 Label* L_success,
1073 Label* L_failure,
1074 Label* L_slow_path,
1075 Register super_check_offset = noreg);
1076
1077 // The rest of the type check; must be wired to a corresponding fast path.
1078 // It does not repeat the fast path logic, so don't use it standalone.
1079 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1080 // Updates the sub's secondary super cache as necessary.
1081 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1082 void check_klass_subtype_slow_path(Register sub_klass,
1083 Register super_klass,
1084 Register temp_reg,
1085 Register temp2_reg,
1086 Label* L_success,
1087 Label* L_failure,
1088 bool set_cond_codes = false);
1089
1090 void check_klass_subtype_slow_path_linear(Register sub_klass,
1091 Register super_klass,
1092 Register temp_reg,
1093 Register temp2_reg,
1094 Label* L_success,
1095 Label* L_failure,
1096 bool set_cond_codes = false);
1097
1098 void check_klass_subtype_slow_path_table(Register sub_klass,
1099 Register super_klass,
1100 Register temp_reg,
1101 Register temp2_reg,
1102 Register temp3_reg,
1103 Register result_reg,
1104 FloatRegister vtemp_reg,
1105 Label* L_success,
1106 Label* L_failure,
1107 bool set_cond_codes = false);
1108
1109 // If r is valid, return r.
1110 // If r is invalid, remove a register r2 from available_regs, add r2
1111 // to regs_to_push, then return r2.
1112 Register allocate_if_noreg(const Register r,
1113 RegSetIterator<Register> &available_regs,
1114 RegSet ®s_to_push);
1115
1116 // Secondary subtype checking
1117 void lookup_secondary_supers_table_var(Register sub_klass,
1118 Register r_super_klass,
1119 Register temp1,
1120 Register temp2,
1121 Register temp3,
1122 FloatRegister vtemp,
1123 Register result,
1124 Label *L_success);
1125
1126
1127 // As above, but with a constant super_klass.
1128 // The result is in Register result, not the condition codes.
1129 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1130 Register r_super_klass,
1131 Register temp1,
1132 Register temp2,
1133 Register temp3,
1134 FloatRegister vtemp,
1135 Register result,
1136 u1 super_klass_slot,
1137 bool stub_is_near = false);
1138
1139 void verify_secondary_supers_table(Register r_sub_klass,
1140 Register r_super_klass,
1141 Register temp1,
1142 Register temp2,
1143 Register result);
1144
1145 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1146 Register r_array_base,
1147 Register r_array_index,
1148 Register r_bitmap,
1149 Register temp1,
1150 Register result,
1151 bool is_stub = true);
1152
1153 // Simplified, combined version, good for typical uses.
1154 // Falls through on failure.
1155 void check_klass_subtype(Register sub_klass,
1156 Register super_klass,
1157 Register temp_reg,
1158 Label& L_success);
1159
1160 void clinit_barrier(Register klass,
1161 Register thread,
1162 Label* L_fast_path = nullptr,
1163 Label* L_slow_path = nullptr);
1164
1165 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1166
1167 void profile_receiver_type(Register recv, Register mdp, int mdp_offset);
1168
1169 void verify_sve_vector_length(Register tmp = rscratch1);
1170 void reinitialize_ptrue() {
1171 if (UseSVE > 0) {
1172 sve_ptrue(ptrue, B);
1173 }
1174 }
1175 void verify_ptrue();
1176
1177 // Debugging
1178
1179 // only if +VerifyOops
1180 void _verify_oop(Register reg, const char* s, const char* file, int line);
1181 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1182
1183 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1184 if (VerifyOops) {
1185 _verify_oop(reg, s, file, line);
1186 }
1187 }
1188 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1189 if (VerifyOops) {
1190 _verify_oop_addr(reg, s, file, line);
1191 }
1192 }
1193
1194 // TODO: verify method and klass metadata (compare against vptr?)
1195 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1196 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1197
1198 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1199 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1200 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1201 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1202 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1203
1204 // Restore cpu control state after JNI call
1205 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1206
1207 // prints msg, dumps registers and stops execution
1208 void stop(const char* msg);
1209
1210 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1211
1212 void untested() { stop("untested"); }
1213
1214 void unimplemented(const char* what = "");
1215
1216 void should_not_reach_here() { stop("should not reach here"); }
1217
1218 void _assert_asm(Condition cc, const char* msg);
1219 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1220 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1221
1222 // Stack overflow checking
1223 void bang_stack_with_offset(int offset) {
1224 // stack grows down, caller passes positive offset
1225 assert(offset > 0, "must bang with negative offset");
1226 sub(rscratch2, sp, offset);
1227 str(zr, Address(rscratch2));
1228 }
1229
1230 // Writes to stack successive pages until offset reached to check for
1231 // stack overflow + shadow pages. Also, clobbers tmp
1232 void bang_stack_size(Register size, Register tmp);
1233
1234 // Check for reserved stack access in method being exited (for JIT)
1235 void reserved_stack_check();
1236
1237 // Arithmetics
1238
1239 // Clobber: rscratch1, rscratch2
1240 void addptr(const Address &dst, int32_t src);
1241
1242 // Clobber: rscratch1
1243 void cmpptr(Register src1, Address src2);
1244
1245 void cmpoop(Register obj1, Register obj2);
1246
1247 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1248 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1249 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1250 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1251
1252 void atomic_xchg(Register prev, Register newv, Register addr);
1253 void atomic_xchgw(Register prev, Register newv, Register addr);
1254 void atomic_xchgl(Register prev, Register newv, Register addr);
1255 void atomic_xchglw(Register prev, Register newv, Register addr);
1256 void atomic_xchgal(Register prev, Register newv, Register addr);
1257 void atomic_xchgalw(Register prev, Register newv, Register addr);
1258
1259 void orptr(Address adr, RegisterOrConstant src) {
1260 ldr(rscratch1, adr);
1261 if (src.is_register())
1262 orr(rscratch1, rscratch1, src.as_register());
1263 else
1264 orr(rscratch1, rscratch1, src.as_constant());
1265 str(rscratch1, adr);
1266 }
1267
1268 // A generic CAS; success or failure is in the EQ flag.
1269 // Clobbers rscratch1
1270 void cmpxchg(Register addr, Register expected, Register new_val,
1271 enum operand_size size,
1272 bool acquire, bool release, bool weak,
1273 Register result);
1274
1275 #ifdef ASSERT
1276 // Template short-hand support to clean-up after a failed call to trampoline
1277 // call generation (see trampoline_call() below), when a set of Labels must
1278 // be reset (before returning).
1279 template<typename Label, typename... More>
1280 void reset_labels(Label &lbl, More&... more) {
1281 lbl.reset(); reset_labels(more...);
1282 }
1283 template<typename Label>
1284 void reset_labels(Label &lbl) {
1285 lbl.reset();
1286 }
1287 #endif
1288
1289 private:
1290 void compare_eq(Register rn, Register rm, enum operand_size size);
1291
1292 public:
1293 // AArch64 OpenJDK uses four different types of calls:
1294 // - direct call: bl pc_relative_offset
1295 // This is the shortest and the fastest, but the offset has the range:
1296 // +/-128MB for the release build, +/-2MB for the debug build.
1297 //
1298 // - far call: adrp reg, pc_relative_offset; add; bl reg
1299 // This is longer than a direct call. The offset has
1300 // the range +/-4GB. As the code cache size is limited to 4GB,
1301 // far calls can reach anywhere in the code cache. If a jump is
1302 // needed rather than a call, a far jump 'b reg' can be used instead.
1303 // All instructions are embedded at a call site.
1304 //
1305 // - trampoline call:
1306 // This is only available in C1/C2-generated code (nmethod). It is a combination
1307 // of a direct call, which is used if the destination of a call is in range,
1308 // and a register-indirect call. It has the advantages of reaching anywhere in
1309 // the AArch64 address space and being patchable at runtime when the generated
1310 // code is being executed by other threads.
1311 //
1312 // [Main code section]
1313 // bl trampoline
1314 // [Stub code section]
1315 // trampoline:
1316 // ldr reg, pc + 8
1317 // br reg
1318 // <64-bit destination address>
1319 //
1320 // If the destination is in range when the generated code is moved to the code
1321 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1322 // is not used.
1323 // The optimization does not remove the trampoline from the stub section.
1324 // This is necessary because the trampoline may well be redirected later when
1325 // code is patched, and the new destination may not be reachable by a simple BR
1326 // instruction.
1327 //
1328 // - indirect call: move reg, address; blr reg
1329 // This too can reach anywhere in the address space, but it cannot be
1330 // patched while code is running, so it must only be modified at a safepoint.
1331 // This form of call is most suitable for targets at fixed addresses, which
1332 // will never be patched.
1333 //
1334 // The patching we do conforms to the "Concurrent modification and
1335 // execution of instructions" section of the Arm Architectural
1336 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1337 // or SVC instructions to be modified while another thread is
1338 // executing them.
1339 //
1340 // To patch a trampoline call when the BL can't reach, we first modify
1341 // the 64-bit destination address in the trampoline, then modify the
1342 // BL to point to the trampoline, then flush the instruction cache to
1343 // broadcast the change to all executing threads. See
1344 // NativeCall::set_destination_mt_safe for the details.
1345 //
1346 // There is a benign race in that the other thread might observe the
1347 // modified BL before it observes the modified 64-bit destination
1348 // address. That does not matter because the destination method has been
1349 // invalidated, so there will be a trap at its start.
1350 // For this to work, the destination address in the trampoline is
1351 // always updated, even if we're not using the trampoline.
1352
1353 // Emit a direct call if the entry address will always be in range,
1354 // otherwise a trampoline call.
1355 // Supported entry.rspec():
1356 // - relocInfo::runtime_call_type
1357 // - relocInfo::opt_virtual_call_type
1358 // - relocInfo::static_call_type
1359 // - relocInfo::virtual_call_type
1360 //
1361 // Return: the call PC or null if CodeCache is full.
1362 // Clobbers: rscratch1
1363 address trampoline_call(Address entry);
1364
1365 static bool far_branches() {
1366 return ReservedCodeCacheSize > branch_range;
1367 }
1368
1369 // Check if branches to the non nmethod section require a far jump
1370 static bool codestub_branch_needs_far_jump() {
1371 if (AOTCodeCache::is_on_for_dump()) {
1372 // To calculate far_codestub_branch_size correctly.
1373 return true;
1374 }
1375 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1376 }
1377
1378 // Emit a direct call/jump if the entry address will always be in range,
1379 // otherwise a far call/jump.
1380 // The address must be inside the code cache.
1381 // Supported entry.rspec():
1382 // - relocInfo::external_word_type
1383 // - relocInfo::runtime_call_type
1384 // - relocInfo::none
1385 // In the case of a far call/jump, the entry address is put in the tmp register.
1386 // The tmp register is invalidated.
1387 //
1388 // Far_jump returns the amount of the emitted code.
1389 void far_call(Address entry, Register tmp = rscratch1);
1390 int far_jump(Address entry, Register tmp = rscratch1);
1391
1392 static int far_codestub_branch_size() {
1393 if (codestub_branch_needs_far_jump()) {
1394 return 3 * 4; // adrp, add, br
1395 } else {
1396 return 4;
1397 }
1398 }
1399
1400 // Emit the CompiledIC call idiom
1401 address ic_call(address entry, jint method_index = 0);
1402 static int ic_check_size();
1403 int ic_check(int end_alignment);
1404
1405 public:
1406
1407 // Data
1408
1409 void mov_metadata(Register dst, Metadata* obj);
1410 Address allocate_metadata_address(Metadata* obj);
1411 Address constant_oop_address(jobject obj);
1412
1413 void movoop(Register dst, jobject obj);
1414
1415 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1416 void kernel_crc32(Register crc, Register buf, Register len,
1417 Register table0, Register table1, Register table2, Register table3,
1418 Register tmp, Register tmp2, Register tmp3);
1419 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1420 void kernel_crc32c(Register crc, Register buf, Register len,
1421 Register table0, Register table1, Register table2, Register table3,
1422 Register tmp, Register tmp2, Register tmp3);
1423
1424 // Stack push and pop individual 64 bit registers
1425 void push(Register src);
1426 void pop(Register dst);
1427
1428 void repne_scan(Register addr, Register value, Register count,
1429 Register scratch);
1430 void repne_scanw(Register addr, Register value, Register count,
1431 Register scratch);
1432
1433 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1434 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1435
1436 // If a constant does not fit in an immediate field, generate some
1437 // number of MOV instructions and then perform the operation
1438 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1439 add_sub_imm_insn insn1,
1440 add_sub_reg_insn insn2, bool is32);
1441 // Separate vsn which sets the flags
1442 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1443 add_sub_imm_insn insn1,
1444 add_sub_reg_insn insn2, bool is32);
1445
1446 #define WRAP(INSN, is32) \
1447 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1448 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1449 } \
1450 \
1451 void INSN(Register Rd, Register Rn, Register Rm, \
1452 enum shift_kind kind, unsigned shift = 0) { \
1453 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1454 } \
1455 \
1456 void INSN(Register Rd, Register Rn, Register Rm) { \
1457 Assembler::INSN(Rd, Rn, Rm); \
1458 } \
1459 \
1460 void INSN(Register Rd, Register Rn, Register Rm, \
1461 ext::operation option, int amount = 0) { \
1462 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1463 }
1464
1465 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1466
1467 #undef WRAP
1468 #define WRAP(INSN, is32) \
1469 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1470 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1471 } \
1472 \
1473 void INSN(Register Rd, Register Rn, Register Rm, \
1474 enum shift_kind kind, unsigned shift = 0) { \
1475 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1476 } \
1477 \
1478 void INSN(Register Rd, Register Rn, Register Rm) { \
1479 Assembler::INSN(Rd, Rn, Rm); \
1480 } \
1481 \
1482 void INSN(Register Rd, Register Rn, Register Rm, \
1483 ext::operation option, int amount = 0) { \
1484 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1485 }
1486
1487 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1488
1489 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1490 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1491 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1492 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1493
1494 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1495
1496 void verified_entry(Compile* C, int sp_inc);
1497
1498 // Inline type specific methods
1499 #include "asm/macroAssembler_common.hpp"
1500
1501 void save_stack_increment(int sp_inc, int frame_size);
1502
1503 void tableswitch(Register index, jint lowbound, jint highbound,
1504 Label &jumptable, Label &jumptable_end, int stride = 1) {
1505 adr(rscratch1, jumptable);
1506 subsw(rscratch2, index, lowbound);
1507 subsw(zr, rscratch2, highbound - lowbound);
1508 br(Assembler::HS, jumptable_end);
1509 add(rscratch1, rscratch1, rscratch2,
1510 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1511 br(rscratch1);
1512 }
1513
1514 // Form an address from base + offset in Rd. Rd may or may not
1515 // actually be used: you must use the Address that is returned. It
1516 // is up to you to ensure that the shift provided matches the size
1517 // of your data.
1518 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1519
1520 // Return true iff an address is within the 48-bit AArch64 address
1521 // space.
1522 bool is_valid_AArch64_address(address a) {
1523 return ((uint64_t)a >> 48) == 0;
1524 }
1525
1526 // Load the base of the cardtable byte map into reg.
1527 void load_byte_map_base(Register reg);
1528
1529 // Load a constant address in the AOT Runtime Constants area
1530 void load_aotrc_address(Register reg, address a);
1531
1532 // Prolog generator routines to support switch between x86 code and
1533 // generated ARM code
1534
1535 // routine to generate an x86 prolog for a stub function which
1536 // bootstraps into the generated ARM code which directly follows the
1537 // stub
1538 //
1539
1540 public:
1541
1542 address read_polling_page(Register r, relocInfo::relocType rtype);
1543 void get_polling_page(Register dest, relocInfo::relocType rtype);
1544
1545 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1546 void update_byte_crc32(Register crc, Register val, Register table);
1547 void update_word_crc32(Register crc, Register v, Register tmp,
1548 Register table0, Register table1, Register table2, Register table3,
1549 bool upper = false);
1550
1551 address count_positives(Register ary1, Register len, Register result);
1552
1553 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1554 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1555
1556 // Ensure that the inline code and the stub use the same registers.
1557 #define ARRAYS_HASHCODE_REGISTERS \
1558 do { \
1559 assert(result == r0 && \
1560 ary == r1 && \
1561 cnt == r2 && \
1562 vdata0 == v3 && \
1563 vdata1 == v2 && \
1564 vdata2 == v1 && \
1565 vdata3 == v0 && \
1566 vmul0 == v4 && \
1567 vmul1 == v5 && \
1568 vmul2 == v6 && \
1569 vmul3 == v7 && \
1570 vpow == v12 && \
1571 vpowm == v13, "registers must match aarch64.ad"); \
1572 } while (0)
1573
1574 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1575
1576 void fill_words(Register base, Register cnt, Register value);
1577 void fill_words(Register base, uint64_t cnt, Register value);
1578
1579 address zero_words(Register base, uint64_t cnt);
1580 address zero_words(Register ptr, Register cnt);
1581 void zero_dcache_blocks(Register base, Register cnt);
1582
1583 static const int zero_words_block_size;
1584
1585 address byte_array_inflate(Register src, Register dst, Register len,
1586 FloatRegister vtmp1, FloatRegister vtmp2,
1587 FloatRegister vtmp3, Register tmp4);
1588
1589 void char_array_compress(Register src, Register dst, Register len,
1590 Register res,
1591 FloatRegister vtmp0, FloatRegister vtmp1,
1592 FloatRegister vtmp2, FloatRegister vtmp3,
1593 FloatRegister vtmp4, FloatRegister vtmp5);
1594
1595 void encode_iso_array(Register src, Register dst,
1596 Register len, Register res, bool ascii,
1597 FloatRegister vtmp0, FloatRegister vtmp1,
1598 FloatRegister vtmp2, FloatRegister vtmp3,
1599 FloatRegister vtmp4, FloatRegister vtmp5);
1600
1601 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1602 address pio2, address dsin_coef, address dcos_coef);
1603 private:
1604 // begin trigonometric functions support block
1605 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1606 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1607 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1608 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1609 // end trigonometric functions support block
1610 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1611 Register src1, Register src2);
1612 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1613 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1614 }
1615 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1616 Register y, Register y_idx, Register z,
1617 Register carry, Register product,
1618 Register idx, Register kdx);
1619 void multiply_128_x_128_loop(Register y, Register z,
1620 Register carry, Register carry2,
1621 Register idx, Register jdx,
1622 Register yz_idx1, Register yz_idx2,
1623 Register tmp, Register tmp3, Register tmp4,
1624 Register tmp7, Register product_hi);
1625 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1626 Register len, Register tmp0, Register tmp1, Register tmp2,
1627 Register tmp3);
1628 void kernel_crc32_using_crc32(Register crc, Register buf,
1629 Register len, Register tmp0, Register tmp1, Register tmp2,
1630 Register tmp3);
1631 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1632 Register len, Register tmp0, Register tmp1, Register tmp2,
1633 Register tmp3);
1634 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1635 Register len, Register tmp0, Register tmp1, Register tmp2,
1636 Register tmp3);
1637 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1638 Register len, Register tmp0, Register tmp1, Register tmp2,
1639 size_t table_offset);
1640
1641 void ghash_modmul (FloatRegister result,
1642 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1643 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1644 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1645 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1646 public:
1647 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1648 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1649 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1650 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1651 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1652 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1653 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1654 void ghash_multiply_wide(int index,
1655 FloatRegister result_lo, FloatRegister result_hi,
1656 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1657 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1658 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1659 FloatRegister p, FloatRegister z, FloatRegister t1);
1660 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1661 FloatRegister p, FloatRegister z, FloatRegister t1);
1662 void ghash_processBlocks_wide(Label& p, Register state, Register subkeyH,
1663 Register data, Register blocks, int unrolls);
1664
1665
1666 void aesenc_loadkeys(Register key, Register keylen);
1667 void aesecb_encrypt(Register from, Register to, Register keylen,
1668 FloatRegister data = v0, int unrolls = 1);
1669 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1670 void aes_round(FloatRegister input, FloatRegister subkey);
1671
1672 // ChaCha20 functions support block
1673 void cc20_qr_add4(FloatRegister (&addFirst)[4],
1674 FloatRegister (&addSecond)[4]);
1675 void cc20_qr_xor4(FloatRegister (&firstElem)[4],
1676 FloatRegister (&secondElem)[4], FloatRegister (&result)[4]);
1677 void cc20_qr_lrot4(FloatRegister (&sourceReg)[4],
1678 FloatRegister (&destReg)[4], int bits, FloatRegister table);
1679 void cc20_set_qr_registers(FloatRegister (&vectorSet)[4],
1680 const FloatRegister (&stateVectors)[16], int idx1, int idx2,
1681 int idx3, int idx4);
1682
1683 // Rotate using ORR (for identity) or USHR + SLI.
1684 void neon_vector_rotate(FloatRegister dst, SIMD_Arrangement T,
1685 FloatRegister src, int shift_amount);
1686
1687 // Place an ISB after code may have been modified due to a safepoint.
1688 void safepoint_isb();
1689
1690 private:
1691 // Return the effective address r + (r1 << ext) + offset.
1692 // Uses rscratch2.
1693 Address offsetted_address(Register r, Register r1, Address::extend ext,
1694 int offset, int size);
1695
1696 private:
1697 // Returns an address on the stack which is reachable with a ldr/str of size
1698 // Uses rscratch2 if the address is not directly reachable
1699 Address spill_address(int size, int offset, Register tmp=rscratch2);
1700 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1701
1702 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1703
1704 // Check whether two loads/stores can be merged into ldp/stp.
1705 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1706
1707 // Merge current load/store with previous load/store into ldp/stp.
1708 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1709
1710 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1711 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1712
1713 public:
1714 void spill(Register Rx, bool is64, int offset) {
1715 if (is64) {
1716 str(Rx, spill_address(8, offset));
1717 } else {
1718 strw(Rx, spill_address(4, offset));
1719 }
1720 }
1721 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1722 str(Vx, T, spill_address(1 << (int)T, offset));
1723 }
1724
1725 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1726 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1727 }
1728 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1729 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1730 }
1731
1732 void unspill(Register Rx, bool is64, int offset) {
1733 if (is64) {
1734 ldr(Rx, spill_address(8, offset));
1735 } else {
1736 ldrw(Rx, spill_address(4, offset));
1737 }
1738 }
1739 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1740 ldr(Vx, T, spill_address(1 << (int)T, offset));
1741 }
1742
1743 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1744 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1745 }
1746 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1747 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1748 }
1749
1750 void spill_copy128(int src_offset, int dst_offset,
1751 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1752 if (src_offset < 512 && (src_offset & 7) == 0 &&
1753 dst_offset < 512 && (dst_offset & 7) == 0) {
1754 ldp(tmp1, tmp2, Address(sp, src_offset));
1755 stp(tmp1, tmp2, Address(sp, dst_offset));
1756 } else {
1757 unspill(tmp1, true, src_offset);
1758 spill(tmp1, true, dst_offset);
1759 unspill(tmp1, true, src_offset+8);
1760 spill(tmp1, true, dst_offset+8);
1761 }
1762 }
1763 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1764 int sve_vec_reg_size_in_bytes) {
1765 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1766 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1767 spill_copy128(src_offset, dst_offset);
1768 src_offset += 16;
1769 dst_offset += 16;
1770 }
1771 }
1772 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1773 int sve_predicate_reg_size_in_bytes) {
1774 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1775 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1776 reinitialize_ptrue();
1777 }
1778 void cache_wb(Address line);
1779 void cache_wbsync(bool is_pre);
1780
1781 // Code for java.lang.Thread::onSpinWait() intrinsic.
1782 void spin_wait();
1783 void spin_wait_wfet(int delay_ns);
1784
1785 void fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1786 void fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1787
1788 private:
1789 // Check the current thread doesn't need a cross modify fence.
1790 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1791
1792 };
1793
1794 #ifdef ASSERT
1795 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1796 #endif
1797
1798 struct tableswitch {
1799 Register _reg;
1800 int _insn_index; jint _first_key; jint _last_key;
1801 Label _after;
1802 Label _branches;
1803 };
1804
1805 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP