1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/macros.hpp"
37 #include "utilities/powerOfTwo.hpp"
38 #include "runtime/signature.hpp"
39
40
41 class ciInlineKlass;
42
43 class OopMap;
44
45 // MacroAssembler extends Assembler by frequently used macros.
46 //
47 // Instructions for which a 'better' code sequence exists depending
48 // on arguments should also go in here.
49
50 class MacroAssembler: public Assembler {
51 friend class LIR_Assembler;
52
53 public:
54 using Assembler::mov;
55 using Assembler::movi;
56
57 protected:
58
59 // Support for VM calls
60 //
61 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
62 // may customize this version by overriding it for its purposes (e.g., to save/restore
63 // additional registers when doing a VM call).
64 virtual void call_VM_leaf_base(
65 address entry_point, // the entry point
66 int number_of_arguments, // the number of arguments to pop after the call
67 Label *retaddr = nullptr
68 );
69
70 virtual void call_VM_leaf_base(
71 address entry_point, // the entry point
72 int number_of_arguments, // the number of arguments to pop after the call
73 Label &retaddr) {
74 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
75 }
76
77 // This is the base routine called by the different versions of call_VM. The interpreter
78 // may customize this version by overriding it for its purposes (e.g., to save/restore
79 // additional registers when doing a VM call).
80 //
81 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
82 // returns the register which contains the thread upon return. If a thread register has been
83 // specified, the return value will correspond to that register. If no last_java_sp is specified
84 // (noreg) than rsp will be used instead.
85 virtual void call_VM_base( // returns the register containing the thread upon return
86 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
87 Register java_thread, // the thread if computed before ; use noreg otherwise
88 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
89 address entry_point, // the entry point
90 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
91 bool check_exceptions // whether to check for pending exceptions after return
92 );
93
94 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
95
96 enum KlassDecodeMode {
97 KlassDecodeNone,
98 KlassDecodeZero,
99 KlassDecodeXor,
100 KlassDecodeMovk
101 };
102
103 // Calculate decoding mode based on given parameters, used for checking then ultimately setting.
104 static KlassDecodeMode klass_decode_mode(address base, int shift, const size_t range);
105
106 private:
107 static KlassDecodeMode _klass_decode_mode;
108
109 // Returns above setting with asserts
110 static KlassDecodeMode klass_decode_mode();
111
112 public:
113 // Checks the decode mode and returns false if not compatible with preferred decoding mode.
114 static bool check_klass_decode_mode(address base, int shift, const size_t range);
115
116 // Sets the decode mode and returns false if cannot be set.
117 static bool set_klass_decode_mode(address base, int shift, const size_t range);
118
119 public:
120 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
121
122 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
123 // The implementation is only non-empty for the InterpreterMacroAssembler,
124 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
125 virtual void check_and_handle_popframe(Register java_thread);
126 virtual void check_and_handle_earlyret(Register java_thread);
127
128 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp = rscratch1);
129 void rt_call(address dest, Register tmp = rscratch1);
130
131 // Load Effective Address
132 void lea(Register r, const Address &a) {
133 InstructionMark im(this);
134 a.lea(this, r);
135 }
136
137 // Whether materializing the given address for a LDR/STR requires an
138 // additional lea instruction.
139 static bool legitimize_address_requires_lea(const Address &a, int size) {
140 return a.getMode() == Address::base_plus_offset &&
141 !Address::offset_ok_for_immed(a.offset(), exact_log2(size));
142 }
143
144 /* Sometimes we get misaligned loads and stores, usually from Unsafe
145 accesses, and these can exceed the offset range. */
146 Address legitimize_address(const Address &a, int size, Register scratch) {
147 if (legitimize_address_requires_lea(a, size)) {
148 block_comment("legitimize_address {");
149 lea(scratch, a);
150 block_comment("} legitimize_address");
151 return Address(scratch);
152 }
153 return a;
154 }
155
156 void addmw(Address a, Register incr, Register scratch) {
157 ldrw(scratch, a);
158 addw(scratch, scratch, incr);
159 strw(scratch, a);
160 }
161
162 // Add constant to memory word
163 void addmw(Address a, int imm, Register scratch) {
164 ldrw(scratch, a);
165 if (imm > 0)
166 addw(scratch, scratch, (unsigned)imm);
167 else
168 subw(scratch, scratch, (unsigned)-imm);
169 strw(scratch, a);
170 }
171
172 void bind(Label& L) {
173 Assembler::bind(L);
174 code()->clear_last_insn();
175 code()->set_last_label(pc());
176 }
177
178 void membar(Membar_mask_bits order_constraint);
179
180 using Assembler::ldr;
181 using Assembler::str;
182 using Assembler::ldrw;
183 using Assembler::strw;
184
185 void ldr(Register Rx, const Address &adr);
186 void ldrw(Register Rw, const Address &adr);
187 void str(Register Rx, const Address &adr);
188 void strw(Register Rx, const Address &adr);
189
190 // Frame creation and destruction shared between JITs.
191 void build_frame(int framesize);
192 void remove_frame(int framesize);
193
194 virtual void _call_Unimplemented(address call_site) {
195 mov(rscratch2, call_site);
196 }
197
198 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
199 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
200 // https://reviews.llvm.org/D3311
201
202 #ifdef _WIN64
203 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
204 #else
205 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
206 #endif
207
208 // aliases defined in AARCH64 spec
209
210 template<class T>
211 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
212
213 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
214 inline void cmp(Register Rd, unsigned imm) = delete;
215
216 template<class T>
217 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
218
219 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
220 inline void cmn(Register Rd, unsigned imm) = delete;
221
222 void cset(Register Rd, Assembler::Condition cond) {
223 csinc(Rd, zr, zr, ~cond);
224 }
225 void csetw(Register Rd, Assembler::Condition cond) {
226 csincw(Rd, zr, zr, ~cond);
227 }
228
229 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
230 csneg(Rd, Rn, Rn, ~cond);
231 }
232 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
233 csnegw(Rd, Rn, Rn, ~cond);
234 }
235
236 inline void movw(Register Rd, Register Rn) {
237 if (Rd == sp || Rn == sp) {
238 Assembler::addw(Rd, Rn, 0U);
239 } else {
240 orrw(Rd, zr, Rn);
241 }
242 }
243 inline void mov(Register Rd, Register Rn) {
244 assert(Rd != r31_sp && Rn != r31_sp, "should be");
245 if (Rd == Rn) {
246 } else if (Rd == sp || Rn == sp) {
247 Assembler::add(Rd, Rn, 0U);
248 } else {
249 orr(Rd, zr, Rn);
250 }
251 }
252
253 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
254 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
255
256 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
257 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
258
259 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
260 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
261
262 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
263 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
264 }
265 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
266 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
267 }
268
269 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
270 bfmw(Rd, Rn, lsb, (lsb + width - 1));
271 }
272 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
273 bfm(Rd, Rn, lsb , (lsb + width - 1));
274 }
275
276 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
277 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
278 }
279 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
280 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
281 }
282
283 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
284 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
285 }
286 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
287 sbfm(Rd, Rn, lsb , (lsb + width - 1));
288 }
289
290 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
291 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
292 }
293 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
294 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
295 }
296
297 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
298 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
299 }
300 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
301 ubfm(Rd, Rn, lsb , (lsb + width - 1));
302 }
303
304 inline void asrw(Register Rd, Register Rn, unsigned imm) {
305 sbfmw(Rd, Rn, imm, 31);
306 }
307
308 inline void asr(Register Rd, Register Rn, unsigned imm) {
309 sbfm(Rd, Rn, imm, 63);
310 }
311
312 inline void lslw(Register Rd, Register Rn, unsigned imm) {
313 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
314 }
315
316 inline void lsl(Register Rd, Register Rn, unsigned imm) {
317 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
318 }
319
320 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
321 ubfmw(Rd, Rn, imm, 31);
322 }
323
324 inline void lsr(Register Rd, Register Rn, unsigned imm) {
325 ubfm(Rd, Rn, imm, 63);
326 }
327
328 inline void rorw(Register Rd, Register Rn, unsigned imm) {
329 extrw(Rd, Rn, Rn, imm);
330 }
331
332 inline void ror(Register Rd, Register Rn, unsigned imm) {
333 extr(Rd, Rn, Rn, imm);
334 }
335
336 inline void rolw(Register Rd, Register Rn, unsigned imm) {
337 extrw(Rd, Rn, Rn, (32 - imm));
338 }
339
340 inline void rol(Register Rd, Register Rn, unsigned imm) {
341 extr(Rd, Rn, Rn, (64 - imm));
342 }
343
344 using Assembler::rax1;
345 using Assembler::eor3;
346
347 inline void rax1(Register Rd, Register Rn, Register Rm) {
348 eor(Rd, Rn, Rm, ROR, 63); // Rd = Rn ^ rol(Rm, 1)
349 }
350
351 inline void eor3(Register Rd, Register Rn, Register Rm, Register Rk) {
352 assert(Rd != Rn, "Use tmp register");
353 eor(Rd, Rm, Rk);
354 eor(Rd, Rd, Rn);
355 }
356
357 inline void sxtbw(Register Rd, Register Rn) {
358 sbfmw(Rd, Rn, 0, 7);
359 }
360 inline void sxthw(Register Rd, Register Rn) {
361 sbfmw(Rd, Rn, 0, 15);
362 }
363 inline void sxtb(Register Rd, Register Rn) {
364 sbfm(Rd, Rn, 0, 7);
365 }
366 inline void sxth(Register Rd, Register Rn) {
367 sbfm(Rd, Rn, 0, 15);
368 }
369 inline void sxtw(Register Rd, Register Rn) {
370 sbfm(Rd, Rn, 0, 31);
371 }
372
373 inline void uxtbw(Register Rd, Register Rn) {
374 ubfmw(Rd, Rn, 0, 7);
375 }
376 inline void uxthw(Register Rd, Register Rn) {
377 ubfmw(Rd, Rn, 0, 15);
378 }
379 inline void uxtb(Register Rd, Register Rn) {
380 ubfm(Rd, Rn, 0, 7);
381 }
382 inline void uxth(Register Rd, Register Rn) {
383 ubfm(Rd, Rn, 0, 15);
384 }
385 inline void uxtw(Register Rd, Register Rn) {
386 ubfm(Rd, Rn, 0, 31);
387 }
388
389 inline void cmnw(Register Rn, Register Rm) {
390 addsw(zr, Rn, Rm);
391 }
392 inline void cmn(Register Rn, Register Rm) {
393 adds(zr, Rn, Rm);
394 }
395
396 inline void cmpw(Register Rn, Register Rm) {
397 subsw(zr, Rn, Rm);
398 }
399 inline void cmp(Register Rn, Register Rm) {
400 subs(zr, Rn, Rm);
401 }
402
403 inline void negw(Register Rd, Register Rn) {
404 subw(Rd, zr, Rn);
405 }
406
407 inline void neg(Register Rd, Register Rn) {
408 sub(Rd, zr, Rn);
409 }
410
411 inline void negsw(Register Rd, Register Rn) {
412 subsw(Rd, zr, Rn);
413 }
414
415 inline void negs(Register Rd, Register Rn) {
416 subs(Rd, zr, Rn);
417 }
418
419 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
420 addsw(zr, Rn, Rm, kind, shift);
421 }
422 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
423 adds(zr, Rn, Rm, kind, shift);
424 }
425
426 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
427 subsw(zr, Rn, Rm, kind, shift);
428 }
429 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
430 subs(zr, Rn, Rm, kind, shift);
431 }
432
433 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
434 subw(Rd, zr, Rn, kind, shift);
435 }
436
437 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
438 sub(Rd, zr, Rn, kind, shift);
439 }
440
441 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
442 subsw(Rd, zr, Rn, kind, shift);
443 }
444
445 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
446 subs(Rd, zr, Rn, kind, shift);
447 }
448
449 inline void mnegw(Register Rd, Register Rn, Register Rm) {
450 msubw(Rd, Rn, Rm, zr);
451 }
452 inline void mneg(Register Rd, Register Rn, Register Rm) {
453 msub(Rd, Rn, Rm, zr);
454 }
455
456 inline void mulw(Register Rd, Register Rn, Register Rm) {
457 maddw(Rd, Rn, Rm, zr);
458 }
459 inline void mul(Register Rd, Register Rn, Register Rm) {
460 madd(Rd, Rn, Rm, zr);
461 }
462
463 inline void smnegl(Register Rd, Register Rn, Register Rm) {
464 smsubl(Rd, Rn, Rm, zr);
465 }
466 inline void smull(Register Rd, Register Rn, Register Rm) {
467 smaddl(Rd, Rn, Rm, zr);
468 }
469
470 inline void umnegl(Register Rd, Register Rn, Register Rm) {
471 umsubl(Rd, Rn, Rm, zr);
472 }
473 inline void umull(Register Rd, Register Rn, Register Rm) {
474 umaddl(Rd, Rn, Rm, zr);
475 }
476
477 #define WRAP(INSN) \
478 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
479 if (VM_Version::supports_a53mac() && Ra != zr) \
480 nop(); \
481 Assembler::INSN(Rd, Rn, Rm, Ra); \
482 }
483
484 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
485 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
486 #undef WRAP
487
488
489 // macro assembly operations needed for aarch64
490
491 public:
492
493 enum FpPushPopMode {
494 PushPopFull,
495 PushPopSVE,
496 PushPopNeon,
497 PushPopFp
498 };
499
500 // first two private routines for loading 32 bit or 64 bit constants
501 private:
502
503 void mov_immediate64(Register dst, uint64_t imm64);
504 void mov_immediate32(Register dst, uint32_t imm32);
505
506 int push(unsigned int bitset, Register stack);
507 int pop(unsigned int bitset, Register stack);
508
509 int push_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
510 int pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
511
512 int push_p(unsigned int bitset, Register stack);
513 int pop_p(unsigned int bitset, Register stack);
514
515 void mov(Register dst, Address a);
516
517 public:
518
519 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
520 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
521
522 void push_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) push_fp(regs.bits(), stack, mode); }
523 void pop_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) pop_fp(regs.bits(), stack, mode); }
524
525 static RegSet call_clobbered_gp_registers();
526
527 void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
528 void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
529
530 // Push and pop everything that might be clobbered by a native
531 // runtime call except rscratch1 and rscratch2. (They are always
532 // scratch, so we don't have to protect them.) Only save the lower
533 // 64 bits of each vector register. Additional registers can be excluded
534 // in a passed RegSet.
535 void push_call_clobbered_registers_except(RegSet exclude);
536 void pop_call_clobbered_registers_except(RegSet exclude);
537
538 void push_call_clobbered_registers() {
539 push_call_clobbered_registers_except(RegSet());
540 }
541 void pop_call_clobbered_registers() {
542 pop_call_clobbered_registers_except(RegSet());
543 }
544
545
546 // now mov instructions for loading absolute addresses and 32 or
547 // 64 bit integers
548
549 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
550
551 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
552 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
553
554 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
555
556 void mov(Register dst, RegisterOrConstant src) {
557 if (src.is_register())
558 mov(dst, src.as_register());
559 else
560 mov(dst, src.as_constant());
561 }
562
563 void movptr(Register r, uintptr_t imm64);
564
565 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
566
567 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
568 orr(Vd, T, Vn, Vn);
569 }
570
571 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
572 fcvtsh(tmp, src);
573 smov(dst, tmp, H, 0);
574 }
575
576 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
577 mov(tmp, H, 0, src);
578 fcvths(dst, tmp);
579 }
580
581 // Generalized Test Bit And Branch, including a "far" variety which
582 // spans more than 32KiB.
583 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
584 assert(cond == EQ || cond == NE, "must be");
585
586 if (isfar)
587 cond = ~cond;
588
589 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
590 if (cond == Assembler::EQ)
591 branch = &Assembler::tbz;
592 else
593 branch = &Assembler::tbnz;
594
595 if (isfar) {
596 Label L;
597 (this->*branch)(Rt, bitpos, L);
598 b(dest);
599 bind(L);
600 } else {
601 (this->*branch)(Rt, bitpos, dest);
602 }
603 }
604
605 // macro instructions for accessing and updating floating point
606 // status register
607 //
608 // FPSR : op1 == 011
609 // CRn == 0100
610 // CRm == 0100
611 // op2 == 001
612
613 inline void get_fpsr(Register reg)
614 {
615 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
616 }
617
618 inline void set_fpsr(Register reg)
619 {
620 msr(0b011, 0b0100, 0b0100, 0b001, reg);
621 }
622
623 inline void clear_fpsr()
624 {
625 msr(0b011, 0b0100, 0b0100, 0b001, zr);
626 }
627
628 // FPCR : op1 == 011
629 // CRn == 0100
630 // CRm == 0100
631 // op2 == 000
632
633 inline void get_fpcr(Register reg) {
634 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
635 }
636
637 inline void set_fpcr(Register reg) {
638 msr(0b011, 0b0100, 0b0100, 0b000, reg);
639 }
640
641 // DCZID_EL0: op1 == 011
642 // CRn == 0000
643 // CRm == 0000
644 // op2 == 111
645 inline void get_dczid_el0(Register reg)
646 {
647 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
648 }
649
650 // CTR_EL0: op1 == 011
651 // CRn == 0000
652 // CRm == 0000
653 // op2 == 001
654 inline void get_ctr_el0(Register reg)
655 {
656 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
657 }
658
659 inline void get_nzcv(Register reg) {
660 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
661 }
662
663 inline void set_nzcv(Register reg) {
664 msr(0b011, 0b0100, 0b0010, 0b000, reg);
665 }
666
667 // idiv variant which deals with MINLONG as dividend and -1 as divisor
668 int corrected_idivl(Register result, Register ra, Register rb,
669 bool want_remainder, Register tmp = rscratch1);
670 int corrected_idivq(Register result, Register ra, Register rb,
671 bool want_remainder, Register tmp = rscratch1);
672
673 // Support for null-checks
674 //
675 // Generates code that causes a null OS exception if the content of reg is null.
676 // If the accessed location is M[reg + offset] and the offset is known, provide the
677 // offset. No explicit code generation is needed if the offset is within a certain
678 // range (0 <= offset <= page_size).
679
680 virtual void null_check(Register reg, int offset = -1);
681 static bool needs_explicit_null_check(intptr_t offset);
682 static bool uses_implicit_null_check(void* address);
683
684 // markWord tests, kills markWord reg
685 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
686
687 // inlineKlass queries, kills temp_reg
688 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
689
690 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
691 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
692 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
693 void test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker);
694
695 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
696 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
697 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
698 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
699 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
700 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
701
702 // Check array klass layout helper for flat or null-free arrays...
703 void test_flat_array_layout(Register lh, Label& is_flat_array);
704 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array);
705
706 static address target_addr_for_insn(address insn_addr, unsigned insn);
707 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
708 static address target_addr_for_insn(address insn_addr) {
709 unsigned insn = *(unsigned*)insn_addr;
710 return target_addr_for_insn(insn_addr, insn);
711 }
712 static address target_addr_for_insn_or_null(address insn_addr) {
713 unsigned insn = *(unsigned*)insn_addr;
714 return target_addr_for_insn_or_null(insn_addr, insn);
715 }
716
717 // Required platform-specific helpers for Label::patch_instructions.
718 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
719 static int pd_patch_instruction_size(address branch, address target);
720 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
721 pd_patch_instruction_size(branch, target);
722 }
723 static address pd_call_destination(address branch) {
724 return target_addr_for_insn(branch);
725 }
726 #ifndef PRODUCT
727 static void pd_print_patched_instruction(address branch);
728 #endif
729
730 static int patch_oop(address insn_addr, address o);
731 static int patch_narrow_klass(address insn_addr, narrowKlass n);
732
733 // Return whether code is emitted to a scratch blob.
734 virtual bool in_scratch_emit_size() {
735 return false;
736 }
737 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
738 static int max_trampoline_stub_size();
739 void emit_static_call_stub();
740 static int static_call_stub_size();
741
742 // The following 4 methods return the offset of the appropriate move instruction
743
744 // Support for fast byte/short loading with zero extension (depending on particular CPU)
745 int load_unsigned_byte(Register dst, Address src);
746 int load_unsigned_short(Register dst, Address src);
747
748 // Support for fast byte/short loading with sign extension (depending on particular CPU)
749 int load_signed_byte(Register dst, Address src);
750 int load_signed_short(Register dst, Address src);
751
752 int load_signed_byte32(Register dst, Address src);
753 int load_signed_short32(Register dst, Address src);
754
755 // Support for sign-extension (hi:lo = extend_sign(lo))
756 void extend_sign(Register hi, Register lo);
757
758 // Load and store values by size and signed-ness
759 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
760 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
761
762 // Support for inc/dec with optimal instruction selection depending on value
763
764 // x86_64 aliases an unqualified register/address increment and
765 // decrement to call incrementq and decrementq but also supports
766 // explicitly sized calls to incrementq/decrementq or
767 // incrementl/decrementl
768
769 // for aarch64 the proper convention would be to use
770 // increment/decrement for 64 bit operations and
771 // incrementw/decrementw for 32 bit operations. so when porting
772 // x86_64 code we can leave calls to increment/decrement as is,
773 // replace incrementq/decrementq with increment/decrement and
774 // replace incrementl/decrementl with incrementw/decrementw.
775
776 // n.b. increment/decrement calls with an Address destination will
777 // need to use a scratch register to load the value to be
778 // incremented. increment/decrement calls which add or subtract a
779 // constant value greater than 2^12 will need to use a 2nd scratch
780 // register to hold the constant. so, a register increment/decrement
781 // may trash rscratch2 and an address increment/decrement trash
782 // rscratch and rscratch2
783
784 void decrementw(Address dst, int value = 1);
785 void decrementw(Register reg, int value = 1);
786
787 void decrement(Register reg, int value = 1);
788 void decrement(Address dst, int value = 1);
789
790 void incrementw(Address dst, int value = 1);
791 void incrementw(Register reg, int value = 1);
792
793 void increment(Register reg, int value = 1);
794 void increment(Address dst, int value = 1);
795
796
797 // Alignment
798 void align(int modulus);
799 void align(int modulus, int target);
800
801 // nop
802 void post_call_nop();
803
804 // Stack frame creation/removal
805 void enter(bool strip_ret_addr = false);
806 void leave();
807
808 // ROP Protection
809 void protect_return_address();
810 void protect_return_address(Register return_reg);
811 void authenticate_return_address();
812 void authenticate_return_address(Register return_reg);
813 void strip_return_address();
814 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
815
816 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
817 // The pointer will be loaded into the thread register.
818 void get_thread(Register thread);
819
820 // support for argument shuffling
821 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
822 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
823 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
824 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
825 void object_move(
826 OopMap* map,
827 int oop_handle_offset,
828 int framesize_in_slots,
829 VMRegPair src,
830 VMRegPair dst,
831 bool is_receiver,
832 int* receiver_offset);
833
834
835 // Support for VM calls
836 //
837 // It is imperative that all calls into the VM are handled via the call_VM macros.
838 // They make sure that the stack linkage is setup correctly. call_VM's correspond
839 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
840
841
842 void call_VM(Register oop_result,
843 address entry_point,
844 bool check_exceptions = true);
845 void call_VM(Register oop_result,
846 address entry_point,
847 Register arg_1,
848 bool check_exceptions = true);
849 void call_VM(Register oop_result,
850 address entry_point,
851 Register arg_1, Register arg_2,
852 bool check_exceptions = true);
853 void call_VM(Register oop_result,
854 address entry_point,
855 Register arg_1, Register arg_2, Register arg_3,
856 bool check_exceptions = true);
857
858 // Overloadings with last_Java_sp
859 void call_VM(Register oop_result,
860 Register last_java_sp,
861 address entry_point,
862 int number_of_arguments = 0,
863 bool check_exceptions = true);
864 void call_VM(Register oop_result,
865 Register last_java_sp,
866 address entry_point,
867 Register arg_1, bool
868 check_exceptions = true);
869 void call_VM(Register oop_result,
870 Register last_java_sp,
871 address entry_point,
872 Register arg_1, Register arg_2,
873 bool check_exceptions = true);
874 void call_VM(Register oop_result,
875 Register last_java_sp,
876 address entry_point,
877 Register arg_1, Register arg_2, Register arg_3,
878 bool check_exceptions = true);
879
880 void get_vm_result_oop(Register oop_result, Register thread);
881 void get_vm_result_metadata(Register metadata_result, Register thread);
882
883 // These always tightly bind to MacroAssembler::call_VM_base
884 // bypassing the virtual implementation
885 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
886 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
887 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
888 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
889 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
890
891 void call_VM_leaf(address entry_point,
892 int number_of_arguments = 0);
893 void call_VM_leaf(address entry_point,
894 Register arg_1);
895 void call_VM_leaf(address entry_point,
896 Register arg_1, Register arg_2);
897 void call_VM_leaf(address entry_point,
898 Register arg_1, Register arg_2, Register arg_3);
899
900 // These always tightly bind to MacroAssembler::call_VM_leaf_base
901 // bypassing the virtual implementation
902 void super_call_VM_leaf(address entry_point);
903 void super_call_VM_leaf(address entry_point, Register arg_1);
904 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
905 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
906 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
907
908 // last Java Frame (fills frame anchor)
909 void set_last_Java_frame(Register last_java_sp,
910 Register last_java_fp,
911 address last_java_pc,
912 Register scratch);
913
914 void set_last_Java_frame(Register last_java_sp,
915 Register last_java_fp,
916 Label &last_java_pc,
917 Register scratch);
918
919 void set_last_Java_frame(Register last_java_sp,
920 Register last_java_fp,
921 Register last_java_pc,
922 Register scratch);
923
924 void reset_last_Java_frame(Register thread);
925
926 // thread in the default location (rthread)
927 void reset_last_Java_frame(bool clear_fp);
928
929 // Stores
930 void store_check(Register obj); // store check for obj - register is destroyed afterwards
931 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
932
933 void resolve_jobject(Register value, Register tmp1, Register tmp2);
934 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
935
936 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
937 void c2bool(Register x);
938
939 void load_method_holder_cld(Register rresult, Register rmethod);
940 void load_method_holder(Register holder, Register method);
941
942 // oop manipulations
943 void load_metadata(Register dst, Register src);
944
945 void load_narrow_klass_compact(Register dst, Register src);
946 void load_klass(Register dst, Register src);
947 void store_klass(Register dst, Register src);
948 void cmp_klass(Register obj, Register klass, Register tmp);
949 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
950
951 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
952 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
953 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
954
955 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
956 Register tmp1, Register tmp2);
957
958 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
959 Register tmp1, Register tmp2, Register tmp3);
960
961 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
962
963 // inline type data payload offsets...
964 void payload_offset(Register inline_klass, Register offset);
965 void payload_address(Register oop, Register data, Register inline_klass);
966 // get data payload ptr a flat value array at index, kills rcx and index
967 void data_for_value_array_index(Register array, Register array_klass,
968 Register index, Register data);
969
970 void load_heap_oop(Register dst, Address src, Register tmp1,
971 Register tmp2, DecoratorSet decorators = 0);
972
973 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
974 Register tmp2, DecoratorSet decorators = 0);
975 void store_heap_oop(Address dst, Register val, Register tmp1,
976 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
977
978 // currently unimplemented
979 // Used for storing null. All other oop constants should be
980 // stored using routines that take a jobject.
981 void store_heap_oop_null(Address dst);
982
983 void load_prototype_header(Register dst, Register src);
984
985 void store_klass_gap(Register dst, Register src);
986
987 // This dummy is to prevent a call to store_heap_oop from
988 // converting a zero (like null) into a Register by giving
989 // the compiler two choices it can't resolve
990
991 void store_heap_oop(Address dst, void* dummy);
992
993 void encode_heap_oop(Register d, Register s);
994 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
995 void decode_heap_oop(Register d, Register s);
996 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
997 void encode_heap_oop_not_null(Register r);
998 void decode_heap_oop_not_null(Register r);
999 void encode_heap_oop_not_null(Register dst, Register src);
1000 void decode_heap_oop_not_null(Register dst, Register src);
1001
1002 void set_narrow_oop(Register dst, jobject obj);
1003
1004 void decode_klass_not_null_for_aot(Register dst, Register src);
1005 void encode_klass_not_null_for_aot(Register dst, Register src);
1006 void encode_klass_not_null(Register r);
1007 void decode_klass_not_null(Register r);
1008 void encode_klass_not_null(Register dst, Register src);
1009 void decode_klass_not_null(Register dst, Register src);
1010
1011 void set_narrow_klass(Register dst, Klass* k);
1012
1013 // if heap base register is used - reinit it with the correct value
1014 void reinit_heapbase();
1015
1016 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1017
1018 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
1019 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1020 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
1021 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1022
1023 void push_cont_fastpath(Register java_thread = rthread);
1024 void pop_cont_fastpath(Register java_thread = rthread);
1025
1026 void inc_held_monitor_count(Register tmp);
1027 void dec_held_monitor_count(Register tmp);
1028
1029 // Round up to a power of two
1030 void round_to(Register reg, int modulus);
1031
1032 // java.lang.Math::round intrinsics
1033 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1034 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1035
1036 // allocation
1037
1038 // Object / value buffer allocation...
1039 // Allocate instance of klass, assumes klass initialized by caller
1040 // new_obj prefers to be rax
1041 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
1042 void allocate_instance(Register klass, Register new_obj,
1043 Register t1, Register t2,
1044 bool clear_fields, Label& alloc_failed);
1045
1046 void tlab_allocate(
1047 Register obj, // result: pointer to object after successful allocation
1048 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1049 int con_size_in_bytes, // object size in bytes if known at compile time
1050 Register t1, // temp register
1051 Register t2, // temp register
1052 Label& slow_case // continuation point if fast allocation fails
1053 );
1054 void verify_tlab();
1055
1056 // For field "index" within "klass", return inline_klass ...
1057 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
1058 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
1059
1060
1061 // interface method calling
1062 void lookup_interface_method(Register recv_klass,
1063 Register intf_klass,
1064 RegisterOrConstant itable_index,
1065 Register method_result,
1066 Register scan_temp,
1067 Label& no_such_interface,
1068 bool return_method = true);
1069
1070 void lookup_interface_method_stub(Register recv_klass,
1071 Register holder_klass,
1072 Register resolved_klass,
1073 Register method_result,
1074 Register temp_reg,
1075 Register temp_reg2,
1076 int itable_index,
1077 Label& L_no_such_interface);
1078
1079 // virtual method calling
1080 // n.b. x86 allows RegisterOrConstant for vtable_index
1081 void lookup_virtual_method(Register recv_klass,
1082 RegisterOrConstant vtable_index,
1083 Register method_result);
1084
1085 // Test sub_klass against super_klass, with fast and slow paths.
1086
1087 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1088 // One of the three labels can be null, meaning take the fall-through.
1089 // If super_check_offset is -1, the value is loaded up from super_klass.
1090 // No registers are killed, except temp_reg.
1091 void check_klass_subtype_fast_path(Register sub_klass,
1092 Register super_klass,
1093 Register temp_reg,
1094 Label* L_success,
1095 Label* L_failure,
1096 Label* L_slow_path,
1097 Register super_check_offset = noreg);
1098
1099 // The rest of the type check; must be wired to a corresponding fast path.
1100 // It does not repeat the fast path logic, so don't use it standalone.
1101 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1102 // Updates the sub's secondary super cache as necessary.
1103 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1104 void check_klass_subtype_slow_path(Register sub_klass,
1105 Register super_klass,
1106 Register temp_reg,
1107 Register temp2_reg,
1108 Label* L_success,
1109 Label* L_failure,
1110 bool set_cond_codes = false);
1111
1112 void check_klass_subtype_slow_path_linear(Register sub_klass,
1113 Register super_klass,
1114 Register temp_reg,
1115 Register temp2_reg,
1116 Label* L_success,
1117 Label* L_failure,
1118 bool set_cond_codes = false);
1119
1120 void check_klass_subtype_slow_path_table(Register sub_klass,
1121 Register super_klass,
1122 Register temp_reg,
1123 Register temp2_reg,
1124 Register temp3_reg,
1125 Register result_reg,
1126 FloatRegister vtemp_reg,
1127 Label* L_success,
1128 Label* L_failure,
1129 bool set_cond_codes = false);
1130
1131 // If r is valid, return r.
1132 // If r is invalid, remove a register r2 from available_regs, add r2
1133 // to regs_to_push, then return r2.
1134 Register allocate_if_noreg(const Register r,
1135 RegSetIterator<Register> &available_regs,
1136 RegSet ®s_to_push);
1137
1138 // Secondary subtype checking
1139 void lookup_secondary_supers_table_var(Register sub_klass,
1140 Register r_super_klass,
1141 Register temp1,
1142 Register temp2,
1143 Register temp3,
1144 FloatRegister vtemp,
1145 Register result,
1146 Label *L_success);
1147
1148
1149 // As above, but with a constant super_klass.
1150 // The result is in Register result, not the condition codes.
1151 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1152 Register r_super_klass,
1153 Register temp1,
1154 Register temp2,
1155 Register temp3,
1156 FloatRegister vtemp,
1157 Register result,
1158 u1 super_klass_slot,
1159 bool stub_is_near = false);
1160
1161 void verify_secondary_supers_table(Register r_sub_klass,
1162 Register r_super_klass,
1163 Register temp1,
1164 Register temp2,
1165 Register result);
1166
1167 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1168 Register r_array_base,
1169 Register r_array_index,
1170 Register r_bitmap,
1171 Register temp1,
1172 Register result,
1173 bool is_stub = true);
1174
1175 // Simplified, combined version, good for typical uses.
1176 // Falls through on failure.
1177 void check_klass_subtype(Register sub_klass,
1178 Register super_klass,
1179 Register temp_reg,
1180 Label& L_success);
1181
1182 void clinit_barrier(Register klass,
1183 Register thread,
1184 Label* L_fast_path = nullptr,
1185 Label* L_slow_path = nullptr);
1186
1187 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1188
1189 void verify_sve_vector_length(Register tmp = rscratch1);
1190 void reinitialize_ptrue() {
1191 if (UseSVE > 0) {
1192 sve_ptrue(ptrue, B);
1193 }
1194 }
1195 void verify_ptrue();
1196
1197 // Debugging
1198
1199 // only if +VerifyOops
1200 void _verify_oop(Register reg, const char* s, const char* file, int line);
1201 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1202
1203 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1204 if (VerifyOops) {
1205 _verify_oop(reg, s, file, line);
1206 }
1207 }
1208 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1209 if (VerifyOops) {
1210 _verify_oop_addr(reg, s, file, line);
1211 }
1212 }
1213
1214 // TODO: verify method and klass metadata (compare against vptr?)
1215 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1216 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1217
1218 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1219 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1220 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1221 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1222 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1223
1224 // Restore cpu control state after JNI call
1225 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1226
1227 // prints msg, dumps registers and stops execution
1228 void stop(const char* msg);
1229
1230 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1231
1232 void untested() { stop("untested"); }
1233
1234 void unimplemented(const char* what = "");
1235
1236 void should_not_reach_here() { stop("should not reach here"); }
1237
1238 void _assert_asm(Condition cc, const char* msg);
1239 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1240 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1241
1242 // Stack overflow checking
1243 void bang_stack_with_offset(int offset) {
1244 // stack grows down, caller passes positive offset
1245 assert(offset > 0, "must bang with negative offset");
1246 sub(rscratch2, sp, offset);
1247 str(zr, Address(rscratch2));
1248 }
1249
1250 // Writes to stack successive pages until offset reached to check for
1251 // stack overflow + shadow pages. Also, clobbers tmp
1252 void bang_stack_size(Register size, Register tmp);
1253
1254 // Check for reserved stack access in method being exited (for JIT)
1255 void reserved_stack_check();
1256
1257 // Arithmetics
1258
1259 // Clobber: rscratch1, rscratch2
1260 void addptr(const Address &dst, int32_t src);
1261
1262 // Clobber: rscratch1
1263 void cmpptr(Register src1, Address src2);
1264
1265 void cmpoop(Register obj1, Register obj2);
1266
1267 // Various forms of CAS
1268
1269 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1270 Label &succeed, Label *fail);
1271 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1272 Label &succeed, Label *fail);
1273
1274 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1275 Label &succeed, Label *fail);
1276
1277 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1278 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1279 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1280 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1281
1282 void atomic_xchg(Register prev, Register newv, Register addr);
1283 void atomic_xchgw(Register prev, Register newv, Register addr);
1284 void atomic_xchgl(Register prev, Register newv, Register addr);
1285 void atomic_xchglw(Register prev, Register newv, Register addr);
1286 void atomic_xchgal(Register prev, Register newv, Register addr);
1287 void atomic_xchgalw(Register prev, Register newv, Register addr);
1288
1289 void orptr(Address adr, RegisterOrConstant src) {
1290 ldr(rscratch1, adr);
1291 if (src.is_register())
1292 orr(rscratch1, rscratch1, src.as_register());
1293 else
1294 orr(rscratch1, rscratch1, src.as_constant());
1295 str(rscratch1, adr);
1296 }
1297
1298 // A generic CAS; success or failure is in the EQ flag.
1299 // Clobbers rscratch1
1300 void cmpxchg(Register addr, Register expected, Register new_val,
1301 enum operand_size size,
1302 bool acquire, bool release, bool weak,
1303 Register result);
1304
1305 #ifdef ASSERT
1306 // Template short-hand support to clean-up after a failed call to trampoline
1307 // call generation (see trampoline_call() below), when a set of Labels must
1308 // be reset (before returning).
1309 template<typename Label, typename... More>
1310 void reset_labels(Label &lbl, More&... more) {
1311 lbl.reset(); reset_labels(more...);
1312 }
1313 template<typename Label>
1314 void reset_labels(Label &lbl) {
1315 lbl.reset();
1316 }
1317 #endif
1318
1319 private:
1320 void compare_eq(Register rn, Register rm, enum operand_size size);
1321
1322 public:
1323 // AArch64 OpenJDK uses four different types of calls:
1324 // - direct call: bl pc_relative_offset
1325 // This is the shortest and the fastest, but the offset has the range:
1326 // +/-128MB for the release build, +/-2MB for the debug build.
1327 //
1328 // - far call: adrp reg, pc_relative_offset; add; bl reg
1329 // This is longer than a direct call. The offset has
1330 // the range +/-4GB. As the code cache size is limited to 4GB,
1331 // far calls can reach anywhere in the code cache. If a jump is
1332 // needed rather than a call, a far jump 'b reg' can be used instead.
1333 // All instructions are embedded at a call site.
1334 //
1335 // - trampoline call:
1336 // This is only available in C1/C2-generated code (nmethod). It is a combination
1337 // of a direct call, which is used if the destination of a call is in range,
1338 // and a register-indirect call. It has the advantages of reaching anywhere in
1339 // the AArch64 address space and being patchable at runtime when the generated
1340 // code is being executed by other threads.
1341 //
1342 // [Main code section]
1343 // bl trampoline
1344 // [Stub code section]
1345 // trampoline:
1346 // ldr reg, pc + 8
1347 // br reg
1348 // <64-bit destination address>
1349 //
1350 // If the destination is in range when the generated code is moved to the code
1351 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1352 // is not used.
1353 // The optimization does not remove the trampoline from the stub section.
1354 // This is necessary because the trampoline may well be redirected later when
1355 // code is patched, and the new destination may not be reachable by a simple BR
1356 // instruction.
1357 //
1358 // - indirect call: move reg, address; blr reg
1359 // This too can reach anywhere in the address space, but it cannot be
1360 // patched while code is running, so it must only be modified at a safepoint.
1361 // This form of call is most suitable for targets at fixed addresses, which
1362 // will never be patched.
1363 //
1364 // The patching we do conforms to the "Concurrent modification and
1365 // execution of instructions" section of the Arm Architectural
1366 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1367 // or SVC instructions to be modified while another thread is
1368 // executing them.
1369 //
1370 // To patch a trampoline call when the BL can't reach, we first modify
1371 // the 64-bit destination address in the trampoline, then modify the
1372 // BL to point to the trampoline, then flush the instruction cache to
1373 // broadcast the change to all executing threads. See
1374 // NativeCall::set_destination_mt_safe for the details.
1375 //
1376 // There is a benign race in that the other thread might observe the
1377 // modified BL before it observes the modified 64-bit destination
1378 // address. That does not matter because the destination method has been
1379 // invalidated, so there will be a trap at its start.
1380 // For this to work, the destination address in the trampoline is
1381 // always updated, even if we're not using the trampoline.
1382
1383 // Emit a direct call if the entry address will always be in range,
1384 // otherwise a trampoline call.
1385 // Supported entry.rspec():
1386 // - relocInfo::runtime_call_type
1387 // - relocInfo::opt_virtual_call_type
1388 // - relocInfo::static_call_type
1389 // - relocInfo::virtual_call_type
1390 //
1391 // Return: the call PC or null if CodeCache is full.
1392 // Clobbers: rscratch1
1393 address trampoline_call(Address entry);
1394
1395 static bool far_branches() {
1396 return ReservedCodeCacheSize > branch_range;
1397 }
1398
1399 // Check if branches to the non nmethod section require a far jump
1400 static bool codestub_branch_needs_far_jump() {
1401 if (AOTCodeCache::is_on_for_dump()) {
1402 // To calculate far_codestub_branch_size correctly.
1403 return true;
1404 }
1405 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1406 }
1407
1408 // Emit a direct call/jump if the entry address will always be in range,
1409 // otherwise a far call/jump.
1410 // The address must be inside the code cache.
1411 // Supported entry.rspec():
1412 // - relocInfo::external_word_type
1413 // - relocInfo::runtime_call_type
1414 // - relocInfo::none
1415 // In the case of a far call/jump, the entry address is put in the tmp register.
1416 // The tmp register is invalidated.
1417 //
1418 // Far_jump returns the amount of the emitted code.
1419 void far_call(Address entry, Register tmp = rscratch1);
1420 int far_jump(Address entry, Register tmp = rscratch1);
1421
1422 static int far_codestub_branch_size() {
1423 if (codestub_branch_needs_far_jump()) {
1424 return 3 * 4; // adrp, add, br
1425 } else {
1426 return 4;
1427 }
1428 }
1429
1430 // Emit the CompiledIC call idiom
1431 address ic_call(address entry, jint method_index = 0);
1432 static int ic_check_size();
1433 int ic_check(int end_alignment);
1434
1435 public:
1436
1437 // Data
1438
1439 void mov_metadata(Register dst, Metadata* obj);
1440 Address allocate_metadata_address(Metadata* obj);
1441 Address constant_oop_address(jobject obj);
1442
1443 void movoop(Register dst, jobject obj);
1444
1445 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1446 void kernel_crc32(Register crc, Register buf, Register len,
1447 Register table0, Register table1, Register table2, Register table3,
1448 Register tmp, Register tmp2, Register tmp3);
1449 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1450 void kernel_crc32c(Register crc, Register buf, Register len,
1451 Register table0, Register table1, Register table2, Register table3,
1452 Register tmp, Register tmp2, Register tmp3);
1453
1454 // Stack push and pop individual 64 bit registers
1455 void push(Register src);
1456 void pop(Register dst);
1457
1458 void repne_scan(Register addr, Register value, Register count,
1459 Register scratch);
1460 void repne_scanw(Register addr, Register value, Register count,
1461 Register scratch);
1462
1463 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1464 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1465
1466 // If a constant does not fit in an immediate field, generate some
1467 // number of MOV instructions and then perform the operation
1468 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1469 add_sub_imm_insn insn1,
1470 add_sub_reg_insn insn2, bool is32);
1471 // Separate vsn which sets the flags
1472 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1473 add_sub_imm_insn insn1,
1474 add_sub_reg_insn insn2, bool is32);
1475
1476 #define WRAP(INSN, is32) \
1477 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1478 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1479 } \
1480 \
1481 void INSN(Register Rd, Register Rn, Register Rm, \
1482 enum shift_kind kind, unsigned shift = 0) { \
1483 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1484 } \
1485 \
1486 void INSN(Register Rd, Register Rn, Register Rm) { \
1487 Assembler::INSN(Rd, Rn, Rm); \
1488 } \
1489 \
1490 void INSN(Register Rd, Register Rn, Register Rm, \
1491 ext::operation option, int amount = 0) { \
1492 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1493 }
1494
1495 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1496
1497 #undef WRAP
1498 #define WRAP(INSN, is32) \
1499 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1500 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1501 } \
1502 \
1503 void INSN(Register Rd, Register Rn, Register Rm, \
1504 enum shift_kind kind, unsigned shift = 0) { \
1505 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1506 } \
1507 \
1508 void INSN(Register Rd, Register Rn, Register Rm) { \
1509 Assembler::INSN(Rd, Rn, Rm); \
1510 } \
1511 \
1512 void INSN(Register Rd, Register Rn, Register Rm, \
1513 ext::operation option, int amount = 0) { \
1514 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1515 }
1516
1517 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1518
1519 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1520 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1521 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1522 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1523
1524 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1525
1526 void verified_entry(Compile* C, int sp_inc);
1527
1528 // Inline type specific methods
1529 #include "asm/macroAssembler_common.hpp"
1530
1531 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1532 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1533 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1534 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1535 RegState reg_state[]);
1536 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1537 VMRegPair* from, int from_count, int& from_index, VMReg to,
1538 RegState reg_state[], Register val_array);
1539 int extend_stack_for_inline_args(int args_on_stack);
1540 void remove_frame(int initial_framesize, bool needs_stack_repair);
1541 VMReg spill_reg_for(VMReg reg);
1542 void save_stack_increment(int sp_inc, int frame_size);
1543
1544 void tableswitch(Register index, jint lowbound, jint highbound,
1545 Label &jumptable, Label &jumptable_end, int stride = 1) {
1546 adr(rscratch1, jumptable);
1547 subsw(rscratch2, index, lowbound);
1548 subsw(zr, rscratch2, highbound - lowbound);
1549 br(Assembler::HS, jumptable_end);
1550 add(rscratch1, rscratch1, rscratch2,
1551 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1552 br(rscratch1);
1553 }
1554
1555 // Form an address from base + offset in Rd. Rd may or may not
1556 // actually be used: you must use the Address that is returned. It
1557 // is up to you to ensure that the shift provided matches the size
1558 // of your data.
1559 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1560
1561 // Return true iff an address is within the 48-bit AArch64 address
1562 // space.
1563 bool is_valid_AArch64_address(address a) {
1564 return ((uint64_t)a >> 48) == 0;
1565 }
1566
1567 // Load the base of the cardtable byte map into reg.
1568 void load_byte_map_base(Register reg);
1569
1570 // Prolog generator routines to support switch between x86 code and
1571 // generated ARM code
1572
1573 // routine to generate an x86 prolog for a stub function which
1574 // bootstraps into the generated ARM code which directly follows the
1575 // stub
1576 //
1577
1578 public:
1579
1580 address read_polling_page(Register r, relocInfo::relocType rtype);
1581 void get_polling_page(Register dest, relocInfo::relocType rtype);
1582
1583 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1584 void update_byte_crc32(Register crc, Register val, Register table);
1585 void update_word_crc32(Register crc, Register v, Register tmp,
1586 Register table0, Register table1, Register table2, Register table3,
1587 bool upper = false);
1588
1589 address count_positives(Register ary1, Register len, Register result);
1590
1591 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1592 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1593
1594 // Ensure that the inline code and the stub use the same registers.
1595 #define ARRAYS_HASHCODE_REGISTERS \
1596 do { \
1597 assert(result == r0 && \
1598 ary == r1 && \
1599 cnt == r2 && \
1600 vdata0 == v3 && \
1601 vdata1 == v2 && \
1602 vdata2 == v1 && \
1603 vdata3 == v0 && \
1604 vmul0 == v4 && \
1605 vmul1 == v5 && \
1606 vmul2 == v6 && \
1607 vmul3 == v7 && \
1608 vpow == v12 && \
1609 vpowm == v13, "registers must match aarch64.ad"); \
1610 } while (0)
1611
1612 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1613
1614 void fill_words(Register base, Register cnt, Register value);
1615 void fill_words(Register base, uint64_t cnt, Register value);
1616
1617 address zero_words(Register base, uint64_t cnt);
1618 address zero_words(Register ptr, Register cnt);
1619 void zero_dcache_blocks(Register base, Register cnt);
1620
1621 static const int zero_words_block_size;
1622
1623 address byte_array_inflate(Register src, Register dst, Register len,
1624 FloatRegister vtmp1, FloatRegister vtmp2,
1625 FloatRegister vtmp3, Register tmp4);
1626
1627 void char_array_compress(Register src, Register dst, Register len,
1628 Register res,
1629 FloatRegister vtmp0, FloatRegister vtmp1,
1630 FloatRegister vtmp2, FloatRegister vtmp3,
1631 FloatRegister vtmp4, FloatRegister vtmp5);
1632
1633 void encode_iso_array(Register src, Register dst,
1634 Register len, Register res, bool ascii,
1635 FloatRegister vtmp0, FloatRegister vtmp1,
1636 FloatRegister vtmp2, FloatRegister vtmp3,
1637 FloatRegister vtmp4, FloatRegister vtmp5);
1638
1639 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1640 address pio2, address dsin_coef, address dcos_coef);
1641 private:
1642 // begin trigonometric functions support block
1643 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1644 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1645 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1646 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1647 // end trigonometric functions support block
1648 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1649 Register src1, Register src2);
1650 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1651 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1652 }
1653 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1654 Register y, Register y_idx, Register z,
1655 Register carry, Register product,
1656 Register idx, Register kdx);
1657 void multiply_128_x_128_loop(Register y, Register z,
1658 Register carry, Register carry2,
1659 Register idx, Register jdx,
1660 Register yz_idx1, Register yz_idx2,
1661 Register tmp, Register tmp3, Register tmp4,
1662 Register tmp7, Register product_hi);
1663 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1664 Register len, Register tmp0, Register tmp1, Register tmp2,
1665 Register tmp3);
1666 void kernel_crc32_using_crc32(Register crc, Register buf,
1667 Register len, Register tmp0, Register tmp1, Register tmp2,
1668 Register tmp3);
1669 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1670 Register len, Register tmp0, Register tmp1, Register tmp2,
1671 Register tmp3);
1672 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1673 Register len, Register tmp0, Register tmp1, Register tmp2,
1674 Register tmp3);
1675 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1676 Register len, Register tmp0, Register tmp1, Register tmp2,
1677 size_t table_offset);
1678
1679 void ghash_modmul (FloatRegister result,
1680 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1681 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1682 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1683 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1684 public:
1685 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1686 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1687 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1688 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1689 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1690 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1691 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1692 void ghash_multiply_wide(int index,
1693 FloatRegister result_lo, FloatRegister result_hi,
1694 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1695 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1696 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1697 FloatRegister p, FloatRegister z, FloatRegister t1);
1698 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1699 FloatRegister p, FloatRegister z, FloatRegister t1);
1700 void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1701 Register data, Register blocks, int unrolls);
1702
1703
1704 void aesenc_loadkeys(Register key, Register keylen);
1705 void aesecb_encrypt(Register from, Register to, Register keylen,
1706 FloatRegister data = v0, int unrolls = 1);
1707 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1708 void aes_round(FloatRegister input, FloatRegister subkey);
1709
1710 // ChaCha20 functions support block
1711 void cc20_qr_add4(FloatRegister (&addFirst)[4],
1712 FloatRegister (&addSecond)[4]);
1713 void cc20_qr_xor4(FloatRegister (&firstElem)[4],
1714 FloatRegister (&secondElem)[4], FloatRegister (&result)[4]);
1715 void cc20_qr_lrot4(FloatRegister (&sourceReg)[4],
1716 FloatRegister (&destReg)[4], int bits, FloatRegister table);
1717 void cc20_set_qr_registers(FloatRegister (&vectorSet)[4],
1718 const FloatRegister (&stateVectors)[16], int idx1, int idx2,
1719 int idx3, int idx4);
1720
1721 // Place an ISB after code may have been modified due to a safepoint.
1722 void safepoint_isb();
1723
1724 private:
1725 // Return the effective address r + (r1 << ext) + offset.
1726 // Uses rscratch2.
1727 Address offsetted_address(Register r, Register r1, Address::extend ext,
1728 int offset, int size);
1729
1730 private:
1731 // Returns an address on the stack which is reachable with a ldr/str of size
1732 // Uses rscratch2 if the address is not directly reachable
1733 Address spill_address(int size, int offset, Register tmp=rscratch2);
1734 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1735
1736 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1737
1738 // Check whether two loads/stores can be merged into ldp/stp.
1739 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1740
1741 // Merge current load/store with previous load/store into ldp/stp.
1742 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1743
1744 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1745 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1746
1747 public:
1748 void spill(Register Rx, bool is64, int offset) {
1749 if (is64) {
1750 str(Rx, spill_address(8, offset));
1751 } else {
1752 strw(Rx, spill_address(4, offset));
1753 }
1754 }
1755 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1756 str(Vx, T, spill_address(1 << (int)T, offset));
1757 }
1758
1759 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1760 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1761 }
1762 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1763 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1764 }
1765
1766 void unspill(Register Rx, bool is64, int offset) {
1767 if (is64) {
1768 ldr(Rx, spill_address(8, offset));
1769 } else {
1770 ldrw(Rx, spill_address(4, offset));
1771 }
1772 }
1773 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1774 ldr(Vx, T, spill_address(1 << (int)T, offset));
1775 }
1776
1777 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1778 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1779 }
1780 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1781 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1782 }
1783
1784 void spill_copy128(int src_offset, int dst_offset,
1785 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1786 if (src_offset < 512 && (src_offset & 7) == 0 &&
1787 dst_offset < 512 && (dst_offset & 7) == 0) {
1788 ldp(tmp1, tmp2, Address(sp, src_offset));
1789 stp(tmp1, tmp2, Address(sp, dst_offset));
1790 } else {
1791 unspill(tmp1, true, src_offset);
1792 spill(tmp1, true, dst_offset);
1793 unspill(tmp1, true, src_offset+8);
1794 spill(tmp1, true, dst_offset+8);
1795 }
1796 }
1797 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1798 int sve_vec_reg_size_in_bytes) {
1799 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1800 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1801 spill_copy128(src_offset, dst_offset);
1802 src_offset += 16;
1803 dst_offset += 16;
1804 }
1805 }
1806 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1807 int sve_predicate_reg_size_in_bytes) {
1808 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1809 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1810 reinitialize_ptrue();
1811 }
1812 void cache_wb(Address line);
1813 void cache_wbsync(bool is_pre);
1814
1815 // Code for java.lang.Thread::onSpinWait() intrinsic.
1816 void spin_wait();
1817
1818 void lightweight_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1819 void lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1820
1821 private:
1822 // Check the current thread doesn't need a cross modify fence.
1823 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1824
1825 };
1826
1827 #ifdef ASSERT
1828 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1829 #endif
1830
1831 struct tableswitch {
1832 Register _reg;
1833 int _insn_index; jint _first_key; jint _last_key;
1834 Label _after;
1835 Label _branches;
1836 };
1837
1838 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP