1 /* 2 * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP 27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP 28 29 #include "asm/assembler.inline.hpp" 30 #include "code/vmreg.hpp" 31 #include "metaprogramming/enableIf.hpp" 32 #include "oops/compressedOops.hpp" 33 #include "oops/compressedKlass.hpp" 34 #include "runtime/vm_version.hpp" 35 #include "utilities/macros.hpp" 36 #include "utilities/powerOfTwo.hpp" 37 #include "runtime/signature.hpp" 38 39 40 class ciInlineKlass; 41 42 class OopMap; 43 44 // MacroAssembler extends Assembler by frequently used macros. 45 // 46 // Instructions for which a 'better' code sequence exists depending 47 // on arguments should also go in here. 48 49 class MacroAssembler: public Assembler { 50 friend class LIR_Assembler; 51 52 public: 53 using Assembler::mov; 54 using Assembler::movi; 55 56 protected: 57 58 // Support for VM calls 59 // 60 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 61 // may customize this version by overriding it for its purposes (e.g., to save/restore 62 // additional registers when doing a VM call). 63 virtual void call_VM_leaf_base( 64 address entry_point, // the entry point 65 int number_of_arguments, // the number of arguments to pop after the call 66 Label *retaddr = nullptr 67 ); 68 69 virtual void call_VM_leaf_base( 70 address entry_point, // the entry point 71 int number_of_arguments, // the number of arguments to pop after the call 72 Label &retaddr) { 73 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr); 74 } 75 76 // This is the base routine called by the different versions of call_VM. The interpreter 77 // may customize this version by overriding it for its purposes (e.g., to save/restore 78 // additional registers when doing a VM call). 79 // 80 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base 81 // returns the register which contains the thread upon return. If a thread register has been 82 // specified, the return value will correspond to that register. If no last_java_sp is specified 83 // (noreg) than rsp will be used instead. 84 virtual void call_VM_base( // returns the register containing the thread upon return 85 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 86 Register java_thread, // the thread if computed before ; use noreg otherwise 87 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 88 address entry_point, // the entry point 89 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 90 bool check_exceptions // whether to check for pending exceptions after return 91 ); 92 93 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 94 95 enum KlassDecodeMode { 96 KlassDecodeNone, 97 KlassDecodeZero, 98 KlassDecodeXor, 99 KlassDecodeMovk 100 }; 101 102 KlassDecodeMode klass_decode_mode(); 103 104 private: 105 static KlassDecodeMode _klass_decode_mode; 106 107 public: 108 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 109 110 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 111 // The implementation is only non-empty for the InterpreterMacroAssembler, 112 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 113 virtual void check_and_handle_popframe(Register java_thread); 114 virtual void check_and_handle_earlyret(Register java_thread); 115 116 void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1); 117 void rt_call(address dest, Register tmp = rscratch1); 118 119 // Load Effective Address 120 void lea(Register r, const Address &a) { 121 InstructionMark im(this); 122 a.lea(this, r); 123 } 124 125 /* Sometimes we get misaligned loads and stores, usually from Unsafe 126 accesses, and these can exceed the offset range. */ 127 Address legitimize_address(const Address &a, int size, Register scratch) { 128 if (a.getMode() == Address::base_plus_offset) { 129 if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) { 130 block_comment("legitimize_address {"); 131 lea(scratch, a); 132 block_comment("} legitimize_address"); 133 return Address(scratch); 134 } 135 } 136 return a; 137 } 138 139 void addmw(Address a, Register incr, Register scratch) { 140 ldrw(scratch, a); 141 addw(scratch, scratch, incr); 142 strw(scratch, a); 143 } 144 145 // Add constant to memory word 146 void addmw(Address a, int imm, Register scratch) { 147 ldrw(scratch, a); 148 if (imm > 0) 149 addw(scratch, scratch, (unsigned)imm); 150 else 151 subw(scratch, scratch, (unsigned)-imm); 152 strw(scratch, a); 153 } 154 155 void bind(Label& L) { 156 Assembler::bind(L); 157 code()->clear_last_insn(); 158 } 159 160 void membar(Membar_mask_bits order_constraint); 161 162 using Assembler::ldr; 163 using Assembler::str; 164 using Assembler::ldrw; 165 using Assembler::strw; 166 167 void ldr(Register Rx, const Address &adr); 168 void ldrw(Register Rw, const Address &adr); 169 void str(Register Rx, const Address &adr); 170 void strw(Register Rx, const Address &adr); 171 172 // Frame creation and destruction shared between JITs. 173 void build_frame(int framesize); 174 void remove_frame(int framesize); 175 176 virtual void _call_Unimplemented(address call_site) { 177 mov(rscratch2, call_site); 178 } 179 180 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__ 181 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention." 182 // https://reviews.llvm.org/D3311 183 184 #ifdef _WIN64 185 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__) 186 #else 187 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__) 188 #endif 189 190 // aliases defined in AARCH64 spec 191 192 template<class T> 193 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); } 194 195 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); } 196 inline void cmp(Register Rd, unsigned imm) = delete; 197 198 template<class T> 199 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); } 200 201 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); } 202 inline void cmn(Register Rd, unsigned imm) = delete; 203 204 void cset(Register Rd, Assembler::Condition cond) { 205 csinc(Rd, zr, zr, ~cond); 206 } 207 void csetw(Register Rd, Assembler::Condition cond) { 208 csincw(Rd, zr, zr, ~cond); 209 } 210 211 void cneg(Register Rd, Register Rn, Assembler::Condition cond) { 212 csneg(Rd, Rn, Rn, ~cond); 213 } 214 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) { 215 csnegw(Rd, Rn, Rn, ~cond); 216 } 217 218 inline void movw(Register Rd, Register Rn) { 219 if (Rd == sp || Rn == sp) { 220 Assembler::addw(Rd, Rn, 0U); 221 } else { 222 orrw(Rd, zr, Rn); 223 } 224 } 225 inline void mov(Register Rd, Register Rn) { 226 assert(Rd != r31_sp && Rn != r31_sp, "should be"); 227 if (Rd == Rn) { 228 } else if (Rd == sp || Rn == sp) { 229 Assembler::add(Rd, Rn, 0U); 230 } else { 231 orr(Rd, zr, Rn); 232 } 233 } 234 235 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); } 236 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); } 237 238 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); } 239 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); } 240 241 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); } 242 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); } 243 244 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 245 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 246 } 247 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) { 248 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 249 } 250 251 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 252 bfmw(Rd, Rn, lsb, (lsb + width - 1)); 253 } 254 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) { 255 bfm(Rd, Rn, lsb , (lsb + width - 1)); 256 } 257 258 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 259 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 260 } 261 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 262 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 263 } 264 265 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 266 sbfmw(Rd, Rn, lsb, (lsb + width - 1)); 267 } 268 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 269 sbfm(Rd, Rn, lsb , (lsb + width - 1)); 270 } 271 272 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 273 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 274 } 275 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 276 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 277 } 278 279 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 280 ubfmw(Rd, Rn, lsb, (lsb + width - 1)); 281 } 282 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 283 ubfm(Rd, Rn, lsb , (lsb + width - 1)); 284 } 285 286 inline void asrw(Register Rd, Register Rn, unsigned imm) { 287 sbfmw(Rd, Rn, imm, 31); 288 } 289 290 inline void asr(Register Rd, Register Rn, unsigned imm) { 291 sbfm(Rd, Rn, imm, 63); 292 } 293 294 inline void lslw(Register Rd, Register Rn, unsigned imm) { 295 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm)); 296 } 297 298 inline void lsl(Register Rd, Register Rn, unsigned imm) { 299 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm)); 300 } 301 302 inline void lsrw(Register Rd, Register Rn, unsigned imm) { 303 ubfmw(Rd, Rn, imm, 31); 304 } 305 306 inline void lsr(Register Rd, Register Rn, unsigned imm) { 307 ubfm(Rd, Rn, imm, 63); 308 } 309 310 inline void rorw(Register Rd, Register Rn, unsigned imm) { 311 extrw(Rd, Rn, Rn, imm); 312 } 313 314 inline void ror(Register Rd, Register Rn, unsigned imm) { 315 extr(Rd, Rn, Rn, imm); 316 } 317 318 inline void sxtbw(Register Rd, Register Rn) { 319 sbfmw(Rd, Rn, 0, 7); 320 } 321 inline void sxthw(Register Rd, Register Rn) { 322 sbfmw(Rd, Rn, 0, 15); 323 } 324 inline void sxtb(Register Rd, Register Rn) { 325 sbfm(Rd, Rn, 0, 7); 326 } 327 inline void sxth(Register Rd, Register Rn) { 328 sbfm(Rd, Rn, 0, 15); 329 } 330 inline void sxtw(Register Rd, Register Rn) { 331 sbfm(Rd, Rn, 0, 31); 332 } 333 334 inline void uxtbw(Register Rd, Register Rn) { 335 ubfmw(Rd, Rn, 0, 7); 336 } 337 inline void uxthw(Register Rd, Register Rn) { 338 ubfmw(Rd, Rn, 0, 15); 339 } 340 inline void uxtb(Register Rd, Register Rn) { 341 ubfm(Rd, Rn, 0, 7); 342 } 343 inline void uxth(Register Rd, Register Rn) { 344 ubfm(Rd, Rn, 0, 15); 345 } 346 inline void uxtw(Register Rd, Register Rn) { 347 ubfm(Rd, Rn, 0, 31); 348 } 349 350 inline void cmnw(Register Rn, Register Rm) { 351 addsw(zr, Rn, Rm); 352 } 353 inline void cmn(Register Rn, Register Rm) { 354 adds(zr, Rn, Rm); 355 } 356 357 inline void cmpw(Register Rn, Register Rm) { 358 subsw(zr, Rn, Rm); 359 } 360 inline void cmp(Register Rn, Register Rm) { 361 subs(zr, Rn, Rm); 362 } 363 364 inline void negw(Register Rd, Register Rn) { 365 subw(Rd, zr, Rn); 366 } 367 368 inline void neg(Register Rd, Register Rn) { 369 sub(Rd, zr, Rn); 370 } 371 372 inline void negsw(Register Rd, Register Rn) { 373 subsw(Rd, zr, Rn); 374 } 375 376 inline void negs(Register Rd, Register Rn) { 377 subs(Rd, zr, Rn); 378 } 379 380 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 381 addsw(zr, Rn, Rm, kind, shift); 382 } 383 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 384 adds(zr, Rn, Rm, kind, shift); 385 } 386 387 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 388 subsw(zr, Rn, Rm, kind, shift); 389 } 390 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 391 subs(zr, Rn, Rm, kind, shift); 392 } 393 394 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 395 subw(Rd, zr, Rn, kind, shift); 396 } 397 398 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 399 sub(Rd, zr, Rn, kind, shift); 400 } 401 402 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 403 subsw(Rd, zr, Rn, kind, shift); 404 } 405 406 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 407 subs(Rd, zr, Rn, kind, shift); 408 } 409 410 inline void mnegw(Register Rd, Register Rn, Register Rm) { 411 msubw(Rd, Rn, Rm, zr); 412 } 413 inline void mneg(Register Rd, Register Rn, Register Rm) { 414 msub(Rd, Rn, Rm, zr); 415 } 416 417 inline void mulw(Register Rd, Register Rn, Register Rm) { 418 maddw(Rd, Rn, Rm, zr); 419 } 420 inline void mul(Register Rd, Register Rn, Register Rm) { 421 madd(Rd, Rn, Rm, zr); 422 } 423 424 inline void smnegl(Register Rd, Register Rn, Register Rm) { 425 smsubl(Rd, Rn, Rm, zr); 426 } 427 inline void smull(Register Rd, Register Rn, Register Rm) { 428 smaddl(Rd, Rn, Rm, zr); 429 } 430 431 inline void umnegl(Register Rd, Register Rn, Register Rm) { 432 umsubl(Rd, Rn, Rm, zr); 433 } 434 inline void umull(Register Rd, Register Rn, Register Rm) { 435 umaddl(Rd, Rn, Rm, zr); 436 } 437 438 #define WRAP(INSN) \ 439 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \ 440 if (VM_Version::supports_a53mac() && Ra != zr) \ 441 nop(); \ 442 Assembler::INSN(Rd, Rn, Rm, Ra); \ 443 } 444 445 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw) 446 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl) 447 #undef WRAP 448 449 450 // macro assembly operations needed for aarch64 451 452 // first two private routines for loading 32 bit or 64 bit constants 453 private: 454 455 void mov_immediate64(Register dst, uint64_t imm64); 456 void mov_immediate32(Register dst, uint32_t imm32); 457 458 int push(unsigned int bitset, Register stack); 459 int pop(unsigned int bitset, Register stack); 460 461 int push_fp(unsigned int bitset, Register stack); 462 int pop_fp(unsigned int bitset, Register stack); 463 464 int push_p(unsigned int bitset, Register stack); 465 int pop_p(unsigned int bitset, Register stack); 466 467 void mov(Register dst, Address a); 468 469 public: 470 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); } 471 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); } 472 473 void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); } 474 void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); } 475 476 static RegSet call_clobbered_gp_registers(); 477 478 void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); } 479 void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); } 480 481 // Push and pop everything that might be clobbered by a native 482 // runtime call except rscratch1 and rscratch2. (They are always 483 // scratch, so we don't have to protect them.) Only save the lower 484 // 64 bits of each vector register. Additional registers can be excluded 485 // in a passed RegSet. 486 void push_call_clobbered_registers_except(RegSet exclude); 487 void pop_call_clobbered_registers_except(RegSet exclude); 488 489 void push_call_clobbered_registers() { 490 push_call_clobbered_registers_except(RegSet()); 491 } 492 void pop_call_clobbered_registers() { 493 pop_call_clobbered_registers_except(RegSet()); 494 } 495 496 497 // now mov instructions for loading absolute addresses and 32 or 498 // 64 bit integers 499 500 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); } 501 502 template<typename T, ENABLE_IF(std::is_integral<T>::value)> 503 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); } 504 505 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); } 506 507 void mov(Register dst, RegisterOrConstant src) { 508 if (src.is_register()) 509 mov(dst, src.as_register()); 510 else 511 mov(dst, src.as_constant()); 512 } 513 514 void movptr(Register r, uintptr_t imm64); 515 516 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64); 517 518 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { 519 orr(Vd, T, Vn, Vn); 520 } 521 522 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) { 523 fcvtsh(tmp, src); 524 smov(dst, tmp, H, 0); 525 } 526 527 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) { 528 mov(tmp, H, 0, src); 529 fcvths(dst, tmp); 530 } 531 532 // Generalized Test Bit And Branch, including a "far" variety which 533 // spans more than 32KiB. 534 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) { 535 assert(cond == EQ || cond == NE, "must be"); 536 537 if (isfar) 538 cond = ~cond; 539 540 void (Assembler::* branch)(Register Rt, int bitpos, Label &L); 541 if (cond == Assembler::EQ) 542 branch = &Assembler::tbz; 543 else 544 branch = &Assembler::tbnz; 545 546 if (isfar) { 547 Label L; 548 (this->*branch)(Rt, bitpos, L); 549 b(dest); 550 bind(L); 551 } else { 552 (this->*branch)(Rt, bitpos, dest); 553 } 554 } 555 556 // macro instructions for accessing and updating floating point 557 // status register 558 // 559 // FPSR : op1 == 011 560 // CRn == 0100 561 // CRm == 0100 562 // op2 == 001 563 564 inline void get_fpsr(Register reg) 565 { 566 mrs(0b11, 0b0100, 0b0100, 0b001, reg); 567 } 568 569 inline void set_fpsr(Register reg) 570 { 571 msr(0b011, 0b0100, 0b0100, 0b001, reg); 572 } 573 574 inline void clear_fpsr() 575 { 576 msr(0b011, 0b0100, 0b0100, 0b001, zr); 577 } 578 579 // FPCR : op1 == 011 580 // CRn == 0100 581 // CRm == 0100 582 // op2 == 000 583 584 inline void get_fpcr(Register reg) { 585 mrs(0b11, 0b0100, 0b0100, 0b000, reg); 586 } 587 588 inline void set_fpcr(Register reg) { 589 msr(0b011, 0b0100, 0b0100, 0b000, reg); 590 } 591 592 // DCZID_EL0: op1 == 011 593 // CRn == 0000 594 // CRm == 0000 595 // op2 == 111 596 inline void get_dczid_el0(Register reg) 597 { 598 mrs(0b011, 0b0000, 0b0000, 0b111, reg); 599 } 600 601 // CTR_EL0: op1 == 011 602 // CRn == 0000 603 // CRm == 0000 604 // op2 == 001 605 inline void get_ctr_el0(Register reg) 606 { 607 mrs(0b011, 0b0000, 0b0000, 0b001, reg); 608 } 609 610 inline void get_nzcv(Register reg) { 611 mrs(0b011, 0b0100, 0b0010, 0b000, reg); 612 } 613 614 inline void set_nzcv(Register reg) { 615 msr(0b011, 0b0100, 0b0010, 0b000, reg); 616 } 617 618 // idiv variant which deals with MINLONG as dividend and -1 as divisor 619 int corrected_idivl(Register result, Register ra, Register rb, 620 bool want_remainder, Register tmp = rscratch1); 621 int corrected_idivq(Register result, Register ra, Register rb, 622 bool want_remainder, Register tmp = rscratch1); 623 624 // Support for null-checks 625 // 626 // Generates code that causes a null OS exception if the content of reg is null. 627 // If the accessed location is M[reg + offset] and the offset is known, provide the 628 // offset. No explicit code generation is needed if the offset is within a certain 629 // range (0 <= offset <= page_size). 630 631 virtual void null_check(Register reg, int offset = -1); 632 static bool needs_explicit_null_check(intptr_t offset); 633 static bool uses_implicit_null_check(void* address); 634 635 // markWord tests, kills markWord reg 636 void test_markword_is_inline_type(Register markword, Label& is_inline_type); 637 638 // inlineKlass queries, kills temp_reg 639 void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type); 640 void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type); 641 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type); 642 643 // Get the default value oop for the given InlineKlass 644 void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj); 645 // The empty value oop, for the given InlineKlass ("empty" as in no instance fields) 646 // get_default_value_oop with extra assertion for empty inline klass 647 void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj); 648 649 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free); 650 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free); 651 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat); 652 void test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker); 653 654 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays 655 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label); 656 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array); 657 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array); 658 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array); 659 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array); 660 661 // Check array klass layout helper for flat or null-free arrays... 662 void test_flat_array_layout(Register lh, Label& is_flat_array); 663 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array); 664 665 static address target_addr_for_insn(address insn_addr, unsigned insn); 666 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn); 667 static address target_addr_for_insn(address insn_addr) { 668 unsigned insn = *(unsigned*)insn_addr; 669 return target_addr_for_insn(insn_addr, insn); 670 } 671 static address target_addr_for_insn_or_null(address insn_addr) { 672 unsigned insn = *(unsigned*)insn_addr; 673 return target_addr_for_insn_or_null(insn_addr, insn); 674 } 675 676 // Required platform-specific helpers for Label::patch_instructions. 677 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 678 static int pd_patch_instruction_size(address branch, address target); 679 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) { 680 pd_patch_instruction_size(branch, target); 681 } 682 static address pd_call_destination(address branch) { 683 return target_addr_for_insn(branch); 684 } 685 #ifndef PRODUCT 686 static void pd_print_patched_instruction(address branch); 687 #endif 688 689 static int patch_oop(address insn_addr, address o); 690 static int patch_narrow_klass(address insn_addr, narrowKlass n); 691 692 // Return whether code is emitted to a scratch blob. 693 virtual bool in_scratch_emit_size() { 694 return false; 695 } 696 address emit_trampoline_stub(int insts_call_instruction_offset, address target); 697 static int max_trampoline_stub_size(); 698 void emit_static_call_stub(); 699 static int static_call_stub_size(); 700 701 // The following 4 methods return the offset of the appropriate move instruction 702 703 // Support for fast byte/short loading with zero extension (depending on particular CPU) 704 int load_unsigned_byte(Register dst, Address src); 705 int load_unsigned_short(Register dst, Address src); 706 707 // Support for fast byte/short loading with sign extension (depending on particular CPU) 708 int load_signed_byte(Register dst, Address src); 709 int load_signed_short(Register dst, Address src); 710 711 int load_signed_byte32(Register dst, Address src); 712 int load_signed_short32(Register dst, Address src); 713 714 // Support for sign-extension (hi:lo = extend_sign(lo)) 715 void extend_sign(Register hi, Register lo); 716 717 // Load and store values by size and signed-ness 718 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed); 719 void store_sized_value(Address dst, Register src, size_t size_in_bytes); 720 721 // Support for inc/dec with optimal instruction selection depending on value 722 723 // x86_64 aliases an unqualified register/address increment and 724 // decrement to call incrementq and decrementq but also supports 725 // explicitly sized calls to incrementq/decrementq or 726 // incrementl/decrementl 727 728 // for aarch64 the proper convention would be to use 729 // increment/decrement for 64 bit operations and 730 // incrementw/decrementw for 32 bit operations. so when porting 731 // x86_64 code we can leave calls to increment/decrement as is, 732 // replace incrementq/decrementq with increment/decrement and 733 // replace incrementl/decrementl with incrementw/decrementw. 734 735 // n.b. increment/decrement calls with an Address destination will 736 // need to use a scratch register to load the value to be 737 // incremented. increment/decrement calls which add or subtract a 738 // constant value greater than 2^12 will need to use a 2nd scratch 739 // register to hold the constant. so, a register increment/decrement 740 // may trash rscratch2 and an address increment/decrement trash 741 // rscratch and rscratch2 742 743 void decrementw(Address dst, int value = 1); 744 void decrementw(Register reg, int value = 1); 745 746 void decrement(Register reg, int value = 1); 747 void decrement(Address dst, int value = 1); 748 749 void incrementw(Address dst, int value = 1); 750 void incrementw(Register reg, int value = 1); 751 752 void increment(Register reg, int value = 1); 753 void increment(Address dst, int value = 1); 754 755 756 // Alignment 757 void align(int modulus); 758 void align(int modulus, int target); 759 760 // nop 761 void post_call_nop(); 762 763 // Stack frame creation/removal 764 void enter(bool strip_ret_addr = false); 765 void leave(); 766 767 // ROP Protection 768 void protect_return_address(); 769 void protect_return_address(Register return_reg); 770 void authenticate_return_address(); 771 void authenticate_return_address(Register return_reg); 772 void strip_return_address(); 773 void check_return_address(Register return_reg=lr) PRODUCT_RETURN; 774 775 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 776 // The pointer will be loaded into the thread register. 777 void get_thread(Register thread); 778 779 // support for argument shuffling 780 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1); 781 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1); 782 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1); 783 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1); 784 void object_move( 785 OopMap* map, 786 int oop_handle_offset, 787 int framesize_in_slots, 788 VMRegPair src, 789 VMRegPair dst, 790 bool is_receiver, 791 int* receiver_offset); 792 793 794 // Support for VM calls 795 // 796 // It is imperative that all calls into the VM are handled via the call_VM macros. 797 // They make sure that the stack linkage is setup correctly. call_VM's correspond 798 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 799 800 801 void call_VM(Register oop_result, 802 address entry_point, 803 bool check_exceptions = true); 804 void call_VM(Register oop_result, 805 address entry_point, 806 Register arg_1, 807 bool check_exceptions = true); 808 void call_VM(Register oop_result, 809 address entry_point, 810 Register arg_1, Register arg_2, 811 bool check_exceptions = true); 812 void call_VM(Register oop_result, 813 address entry_point, 814 Register arg_1, Register arg_2, Register arg_3, 815 bool check_exceptions = true); 816 817 // Overloadings with last_Java_sp 818 void call_VM(Register oop_result, 819 Register last_java_sp, 820 address entry_point, 821 int number_of_arguments = 0, 822 bool check_exceptions = true); 823 void call_VM(Register oop_result, 824 Register last_java_sp, 825 address entry_point, 826 Register arg_1, bool 827 check_exceptions = true); 828 void call_VM(Register oop_result, 829 Register last_java_sp, 830 address entry_point, 831 Register arg_1, Register arg_2, 832 bool check_exceptions = true); 833 void call_VM(Register oop_result, 834 Register last_java_sp, 835 address entry_point, 836 Register arg_1, Register arg_2, Register arg_3, 837 bool check_exceptions = true); 838 839 void get_vm_result (Register oop_result, Register thread); 840 void get_vm_result_2(Register metadata_result, Register thread); 841 842 // These always tightly bind to MacroAssembler::call_VM_base 843 // bypassing the virtual implementation 844 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 845 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 846 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 847 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 848 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 849 850 void call_VM_leaf(address entry_point, 851 int number_of_arguments = 0); 852 void call_VM_leaf(address entry_point, 853 Register arg_1); 854 void call_VM_leaf(address entry_point, 855 Register arg_1, Register arg_2); 856 void call_VM_leaf(address entry_point, 857 Register arg_1, Register arg_2, Register arg_3); 858 859 // These always tightly bind to MacroAssembler::call_VM_leaf_base 860 // bypassing the virtual implementation 861 void super_call_VM_leaf(address entry_point); 862 void super_call_VM_leaf(address entry_point, Register arg_1); 863 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 864 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 865 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 866 867 // last Java Frame (fills frame anchor) 868 void set_last_Java_frame(Register last_java_sp, 869 Register last_java_fp, 870 address last_java_pc, 871 Register scratch); 872 873 void set_last_Java_frame(Register last_java_sp, 874 Register last_java_fp, 875 Label &last_java_pc, 876 Register scratch); 877 878 void set_last_Java_frame(Register last_java_sp, 879 Register last_java_fp, 880 Register last_java_pc, 881 Register scratch); 882 883 void reset_last_Java_frame(Register thread); 884 885 // thread in the default location (rthread) 886 void reset_last_Java_frame(bool clear_fp); 887 888 // Stores 889 void store_check(Register obj); // store check for obj - register is destroyed afterwards 890 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 891 892 void resolve_jobject(Register value, Register tmp1, Register tmp2); 893 void resolve_global_jobject(Register value, Register tmp1, Register tmp2); 894 895 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 896 void c2bool(Register x); 897 898 void load_method_holder_cld(Register rresult, Register rmethod); 899 void load_method_holder(Register holder, Register method); 900 901 // oop manipulations 902 void load_metadata(Register dst, Register src); 903 904 void load_klass(Register dst, Register src); 905 void store_klass(Register dst, Register src); 906 void cmp_klass(Register oop, Register trial_klass, Register tmp); 907 908 void resolve_weak_handle(Register result, Register tmp1, Register tmp2); 909 void resolve_oop_handle(Register result, Register tmp1, Register tmp2); 910 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2); 911 912 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src, 913 Register tmp1, Register tmp2); 914 915 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val, 916 Register tmp1, Register tmp2, Register tmp3); 917 918 void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register inline_klass); 919 920 // inline type data payload offsets... 921 void first_field_offset(Register inline_klass, Register offset); 922 void data_for_oop(Register oop, Register data, Register inline_klass); 923 // get data payload ptr a flat value array at index, kills rcx and index 924 void data_for_value_array_index(Register array, Register array_klass, 925 Register index, Register data); 926 927 void load_heap_oop(Register dst, Address src, Register tmp1, 928 Register tmp2, DecoratorSet decorators = 0); 929 930 void load_heap_oop_not_null(Register dst, Address src, Register tmp1, 931 Register tmp2, DecoratorSet decorators = 0); 932 void store_heap_oop(Address dst, Register val, Register tmp1, 933 Register tmp2, Register tmp3, DecoratorSet decorators = 0); 934 935 // currently unimplemented 936 // Used for storing null. All other oop constants should be 937 // stored using routines that take a jobject. 938 void store_heap_oop_null(Address dst); 939 940 void load_prototype_header(Register dst, Register src); 941 942 void store_klass_gap(Register dst, Register src); 943 944 // This dummy is to prevent a call to store_heap_oop from 945 // converting a zero (like null) into a Register by giving 946 // the compiler two choices it can't resolve 947 948 void store_heap_oop(Address dst, void* dummy); 949 950 void encode_heap_oop(Register d, Register s); 951 void encode_heap_oop(Register r) { encode_heap_oop(r, r); } 952 void decode_heap_oop(Register d, Register s); 953 void decode_heap_oop(Register r) { decode_heap_oop(r, r); } 954 void encode_heap_oop_not_null(Register r); 955 void decode_heap_oop_not_null(Register r); 956 void encode_heap_oop_not_null(Register dst, Register src); 957 void decode_heap_oop_not_null(Register dst, Register src); 958 959 void set_narrow_oop(Register dst, jobject obj); 960 961 void encode_klass_not_null(Register r); 962 void decode_klass_not_null(Register r); 963 void encode_klass_not_null(Register dst, Register src); 964 void decode_klass_not_null(Register dst, Register src); 965 966 void set_narrow_klass(Register dst, Klass* k); 967 968 // if heap base register is used - reinit it with the correct value 969 void reinit_heapbase(); 970 971 DEBUG_ONLY(void verify_heapbase(const char* msg);) 972 973 void push_CPU_state(bool save_vectors = false, bool use_sve = false, 974 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0); 975 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false, 976 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0); 977 978 void push_cont_fastpath(Register java_thread); 979 void pop_cont_fastpath(Register java_thread); 980 981 // Round up to a power of two 982 void round_to(Register reg, int modulus); 983 984 // java.lang.Math::round intrinsics 985 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp); 986 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp); 987 988 // allocation 989 990 // Object / value buffer allocation... 991 // Allocate instance of klass, assumes klass initialized by caller 992 // new_obj prefers to be rax 993 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64) 994 void allocate_instance(Register klass, Register new_obj, 995 Register t1, Register t2, 996 bool clear_fields, Label& alloc_failed); 997 998 void tlab_allocate( 999 Register obj, // result: pointer to object after successful allocation 1000 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 1001 int con_size_in_bytes, // object size in bytes if known at compile time 1002 Register t1, // temp register 1003 Register t2, // temp register 1004 Label& slow_case // continuation point if fast allocation fails 1005 ); 1006 void verify_tlab(); 1007 1008 // For field "index" within "klass", return inline_klass ... 1009 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass); 1010 1011 // interface method calling 1012 void lookup_interface_method(Register recv_klass, 1013 Register intf_klass, 1014 RegisterOrConstant itable_index, 1015 Register method_result, 1016 Register scan_temp, 1017 Label& no_such_interface, 1018 bool return_method = true); 1019 1020 void lookup_interface_method_stub(Register recv_klass, 1021 Register holder_klass, 1022 Register resolved_klass, 1023 Register method_result, 1024 Register temp_reg, 1025 Register temp_reg2, 1026 int itable_index, 1027 Label& L_no_such_interface); 1028 1029 // virtual method calling 1030 // n.b. x86 allows RegisterOrConstant for vtable_index 1031 void lookup_virtual_method(Register recv_klass, 1032 RegisterOrConstant vtable_index, 1033 Register method_result); 1034 1035 // Test sub_klass against super_klass, with fast and slow paths. 1036 1037 // The fast path produces a tri-state answer: yes / no / maybe-slow. 1038 // One of the three labels can be null, meaning take the fall-through. 1039 // If super_check_offset is -1, the value is loaded up from super_klass. 1040 // No registers are killed, except temp_reg. 1041 void check_klass_subtype_fast_path(Register sub_klass, 1042 Register super_klass, 1043 Register temp_reg, 1044 Label* L_success, 1045 Label* L_failure, 1046 Label* L_slow_path, 1047 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 1048 1049 // The rest of the type check; must be wired to a corresponding fast path. 1050 // It does not repeat the fast path logic, so don't use it standalone. 1051 // The temp_reg and temp2_reg can be noreg, if no temps are available. 1052 // Updates the sub's secondary super cache as necessary. 1053 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 1054 void check_klass_subtype_slow_path(Register sub_klass, 1055 Register super_klass, 1056 Register temp_reg, 1057 Register temp2_reg, 1058 Label* L_success, 1059 Label* L_failure, 1060 bool set_cond_codes = false); 1061 1062 // Simplified, combined version, good for typical uses. 1063 // Falls through on failure. 1064 void check_klass_subtype(Register sub_klass, 1065 Register super_klass, 1066 Register temp_reg, 1067 Label& L_success); 1068 1069 void clinit_barrier(Register klass, 1070 Register thread, 1071 Label* L_fast_path = nullptr, 1072 Label* L_slow_path = nullptr); 1073 1074 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 1075 1076 void verify_sve_vector_length(Register tmp = rscratch1); 1077 void reinitialize_ptrue() { 1078 if (UseSVE > 0) { 1079 sve_ptrue(ptrue, B); 1080 } 1081 } 1082 void verify_ptrue(); 1083 1084 // Debugging 1085 1086 // only if +VerifyOops 1087 void _verify_oop(Register reg, const char* s, const char* file, int line); 1088 void _verify_oop_addr(Address addr, const char * s, const char* file, int line); 1089 1090 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) { 1091 if (VerifyOops) { 1092 _verify_oop(reg, s, file, line); 1093 } 1094 } 1095 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) { 1096 if (VerifyOops) { 1097 _verify_oop_addr(reg, s, file, line); 1098 } 1099 } 1100 1101 // TODO: verify method and klass metadata (compare against vptr?) 1102 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 1103 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 1104 1105 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__) 1106 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__) 1107 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__) 1108 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 1109 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 1110 1111 // Restore cpu control state after JNI call 1112 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2); 1113 1114 // prints msg, dumps registers and stops execution 1115 void stop(const char* msg); 1116 1117 static void debug64(char* msg, int64_t pc, int64_t regs[]); 1118 1119 void untested() { stop("untested"); } 1120 1121 void unimplemented(const char* what = ""); 1122 1123 void should_not_reach_here() { stop("should not reach here"); } 1124 1125 void _assert_asm(Condition cc, const char* msg); 1126 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg) 1127 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg)) 1128 1129 // Stack overflow checking 1130 void bang_stack_with_offset(int offset) { 1131 // stack grows down, caller passes positive offset 1132 assert(offset > 0, "must bang with negative offset"); 1133 sub(rscratch2, sp, offset); 1134 str(zr, Address(rscratch2)); 1135 } 1136 1137 // Writes to stack successive pages until offset reached to check for 1138 // stack overflow + shadow pages. Also, clobbers tmp 1139 void bang_stack_size(Register size, Register tmp); 1140 1141 // Check for reserved stack access in method being exited (for JIT) 1142 void reserved_stack_check(); 1143 1144 // Arithmetics 1145 1146 void addptr(const Address &dst, int32_t src); 1147 void cmpptr(Register src1, Address src2); 1148 1149 void cmpoop(Register obj1, Register obj2); 1150 1151 // Various forms of CAS 1152 1153 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp, 1154 Label &succeed, Label *fail); 1155 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 1156 Label &succeed, Label *fail); 1157 1158 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 1159 Label &succeed, Label *fail); 1160 1161 void atomic_add(Register prev, RegisterOrConstant incr, Register addr); 1162 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr); 1163 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr); 1164 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr); 1165 1166 void atomic_xchg(Register prev, Register newv, Register addr); 1167 void atomic_xchgw(Register prev, Register newv, Register addr); 1168 void atomic_xchgl(Register prev, Register newv, Register addr); 1169 void atomic_xchglw(Register prev, Register newv, Register addr); 1170 void atomic_xchgal(Register prev, Register newv, Register addr); 1171 void atomic_xchgalw(Register prev, Register newv, Register addr); 1172 1173 void orptr(Address adr, RegisterOrConstant src) { 1174 ldr(rscratch1, adr); 1175 if (src.is_register()) 1176 orr(rscratch1, rscratch1, src.as_register()); 1177 else 1178 orr(rscratch1, rscratch1, src.as_constant()); 1179 str(rscratch1, adr); 1180 } 1181 1182 // A generic CAS; success or failure is in the EQ flag. 1183 // Clobbers rscratch1 1184 void cmpxchg(Register addr, Register expected, Register new_val, 1185 enum operand_size size, 1186 bool acquire, bool release, bool weak, 1187 Register result); 1188 1189 #ifdef ASSERT 1190 // Template short-hand support to clean-up after a failed call to trampoline 1191 // call generation (see trampoline_call() below), when a set of Labels must 1192 // be reset (before returning). 1193 template<typename Label, typename... More> 1194 void reset_labels(Label &lbl, More&... more) { 1195 lbl.reset(); reset_labels(more...); 1196 } 1197 template<typename Label> 1198 void reset_labels(Label &lbl) { 1199 lbl.reset(); 1200 } 1201 #endif 1202 1203 private: 1204 void compare_eq(Register rn, Register rm, enum operand_size size); 1205 1206 public: 1207 // AArch64 OpenJDK uses four different types of calls: 1208 // - direct call: bl pc_relative_offset 1209 // This is the shortest and the fastest, but the offset has the range: 1210 // +/-128MB for the release build, +/-2MB for the debug build. 1211 // 1212 // - far call: adrp reg, pc_relative_offset; add; bl reg 1213 // This is longer than a direct call. The offset has 1214 // the range +/-4GB. As the code cache size is limited to 4GB, 1215 // far calls can reach anywhere in the code cache. If a jump is 1216 // needed rather than a call, a far jump 'b reg' can be used instead. 1217 // All instructions are embedded at a call site. 1218 // 1219 // - trampoline call: 1220 // This is only available in C1/C2-generated code (nmethod). It is a combination 1221 // of a direct call, which is used if the destination of a call is in range, 1222 // and a register-indirect call. It has the advantages of reaching anywhere in 1223 // the AArch64 address space and being patchable at runtime when the generated 1224 // code is being executed by other threads. 1225 // 1226 // [Main code section] 1227 // bl trampoline 1228 // [Stub code section] 1229 // trampoline: 1230 // ldr reg, pc + 8 1231 // br reg 1232 // <64-bit destination address> 1233 // 1234 // If the destination is in range when the generated code is moved to the code 1235 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline 1236 // is not used. 1237 // The optimization does not remove the trampoline from the stub section. 1238 // This is necessary because the trampoline may well be redirected later when 1239 // code is patched, and the new destination may not be reachable by a simple BR 1240 // instruction. 1241 // 1242 // - indirect call: move reg, address; blr reg 1243 // This too can reach anywhere in the address space, but it cannot be 1244 // patched while code is running, so it must only be modified at a safepoint. 1245 // This form of call is most suitable for targets at fixed addresses, which 1246 // will never be patched. 1247 // 1248 // The patching we do conforms to the "Concurrent modification and 1249 // execution of instructions" section of the Arm Architectural 1250 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC, 1251 // or SVC instructions to be modified while another thread is 1252 // executing them. 1253 // 1254 // To patch a trampoline call when the BL can't reach, we first modify 1255 // the 64-bit destination address in the trampoline, then modify the 1256 // BL to point to the trampoline, then flush the instruction cache to 1257 // broadcast the change to all executing threads. See 1258 // NativeCall::set_destination_mt_safe for the details. 1259 // 1260 // There is a benign race in that the other thread might observe the 1261 // modified BL before it observes the modified 64-bit destination 1262 // address. That does not matter because the destination method has been 1263 // invalidated, so there will be a trap at its start. 1264 // For this to work, the destination address in the trampoline is 1265 // always updated, even if we're not using the trampoline. 1266 1267 // Emit a direct call if the entry address will always be in range, 1268 // otherwise a trampoline call. 1269 // Supported entry.rspec(): 1270 // - relocInfo::runtime_call_type 1271 // - relocInfo::opt_virtual_call_type 1272 // - relocInfo::static_call_type 1273 // - relocInfo::virtual_call_type 1274 // 1275 // Return: the call PC or null if CodeCache is full. 1276 address trampoline_call(Address entry); 1277 1278 static bool far_branches() { 1279 return ReservedCodeCacheSize > branch_range; 1280 } 1281 1282 // Check if branches to the non nmethod section require a far jump 1283 static bool codestub_branch_needs_far_jump() { 1284 return CodeCache::max_distance_to_non_nmethod() > branch_range; 1285 } 1286 1287 // Emit a direct call/jump if the entry address will always be in range, 1288 // otherwise a far call/jump. 1289 // The address must be inside the code cache. 1290 // Supported entry.rspec(): 1291 // - relocInfo::external_word_type 1292 // - relocInfo::runtime_call_type 1293 // - relocInfo::none 1294 // In the case of a far call/jump, the entry address is put in the tmp register. 1295 // The tmp register is invalidated. 1296 // 1297 // Far_jump returns the amount of the emitted code. 1298 void far_call(Address entry, Register tmp = rscratch1); 1299 int far_jump(Address entry, Register tmp = rscratch1); 1300 1301 static int far_codestub_branch_size() { 1302 if (codestub_branch_needs_far_jump()) { 1303 return 3 * 4; // adrp, add, br 1304 } else { 1305 return 4; 1306 } 1307 } 1308 1309 // Emit the CompiledIC call idiom 1310 address ic_call(address entry, jint method_index = 0); 1311 static int ic_check_size(); 1312 int ic_check(int end_alignment); 1313 1314 public: 1315 1316 // Data 1317 1318 void mov_metadata(Register dst, Metadata* obj); 1319 Address allocate_metadata_address(Metadata* obj); 1320 Address constant_oop_address(jobject obj); 1321 1322 void movoop(Register dst, jobject obj); 1323 1324 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic. 1325 void kernel_crc32(Register crc, Register buf, Register len, 1326 Register table0, Register table1, Register table2, Register table3, 1327 Register tmp, Register tmp2, Register tmp3); 1328 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic. 1329 void kernel_crc32c(Register crc, Register buf, Register len, 1330 Register table0, Register table1, Register table2, Register table3, 1331 Register tmp, Register tmp2, Register tmp3); 1332 1333 // Stack push and pop individual 64 bit registers 1334 void push(Register src); 1335 void pop(Register dst); 1336 1337 void repne_scan(Register addr, Register value, Register count, 1338 Register scratch); 1339 void repne_scanw(Register addr, Register value, Register count, 1340 Register scratch); 1341 1342 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm); 1343 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift); 1344 1345 // If a constant does not fit in an immediate field, generate some 1346 // number of MOV instructions and then perform the operation 1347 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm, 1348 add_sub_imm_insn insn1, 1349 add_sub_reg_insn insn2, bool is32); 1350 // Separate vsn which sets the flags 1351 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm, 1352 add_sub_imm_insn insn1, 1353 add_sub_reg_insn insn2, bool is32); 1354 1355 #define WRAP(INSN, is32) \ 1356 void INSN(Register Rd, Register Rn, uint64_t imm) { \ 1357 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \ 1358 } \ 1359 \ 1360 void INSN(Register Rd, Register Rn, Register Rm, \ 1361 enum shift_kind kind, unsigned shift = 0) { \ 1362 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1363 } \ 1364 \ 1365 void INSN(Register Rd, Register Rn, Register Rm) { \ 1366 Assembler::INSN(Rd, Rn, Rm); \ 1367 } \ 1368 \ 1369 void INSN(Register Rd, Register Rn, Register Rm, \ 1370 ext::operation option, int amount = 0) { \ 1371 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1372 } 1373 1374 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true) 1375 1376 #undef WRAP 1377 #define WRAP(INSN, is32) \ 1378 void INSN(Register Rd, Register Rn, uint64_t imm) { \ 1379 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \ 1380 } \ 1381 \ 1382 void INSN(Register Rd, Register Rn, Register Rm, \ 1383 enum shift_kind kind, unsigned shift = 0) { \ 1384 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1385 } \ 1386 \ 1387 void INSN(Register Rd, Register Rn, Register Rm) { \ 1388 Assembler::INSN(Rd, Rn, Rm); \ 1389 } \ 1390 \ 1391 void INSN(Register Rd, Register Rn, Register Rm, \ 1392 ext::operation option, int amount = 0) { \ 1393 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1394 } 1395 1396 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true) 1397 1398 void add(Register Rd, Register Rn, RegisterOrConstant increment); 1399 void addw(Register Rd, Register Rn, RegisterOrConstant increment); 1400 void sub(Register Rd, Register Rn, RegisterOrConstant decrement); 1401 void subw(Register Rd, Register Rn, RegisterOrConstant decrement); 1402 1403 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset); 1404 1405 void verified_entry(Compile* C, int sp_inc); 1406 1407 // Inline type specific methods 1408 #include "asm/macroAssembler_common.hpp" 1409 1410 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true); 1411 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]); 1412 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, 1413 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index, 1414 RegState reg_state[]); 1415 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index, 1416 VMRegPair* from, int from_count, int& from_index, VMReg to, 1417 RegState reg_state[], Register val_array); 1418 int extend_stack_for_inline_args(int args_on_stack); 1419 void remove_frame(int initial_framesize, bool needs_stack_repair); 1420 VMReg spill_reg_for(VMReg reg); 1421 void save_stack_increment(int sp_inc, int frame_size); 1422 1423 void tableswitch(Register index, jint lowbound, jint highbound, 1424 Label &jumptable, Label &jumptable_end, int stride = 1) { 1425 adr(rscratch1, jumptable); 1426 subsw(rscratch2, index, lowbound); 1427 subsw(zr, rscratch2, highbound - lowbound); 1428 br(Assembler::HS, jumptable_end); 1429 add(rscratch1, rscratch1, rscratch2, 1430 ext::sxtw, exact_log2(stride * Assembler::instruction_size)); 1431 br(rscratch1); 1432 } 1433 1434 // Form an address from base + offset in Rd. Rd may or may not 1435 // actually be used: you must use the Address that is returned. It 1436 // is up to you to ensure that the shift provided matches the size 1437 // of your data. 1438 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift); 1439 1440 // Return true iff an address is within the 48-bit AArch64 address 1441 // space. 1442 bool is_valid_AArch64_address(address a) { 1443 return ((uint64_t)a >> 48) == 0; 1444 } 1445 1446 // Load the base of the cardtable byte map into reg. 1447 void load_byte_map_base(Register reg); 1448 1449 // Prolog generator routines to support switch between x86 code and 1450 // generated ARM code 1451 1452 // routine to generate an x86 prolog for a stub function which 1453 // bootstraps into the generated ARM code which directly follows the 1454 // stub 1455 // 1456 1457 public: 1458 1459 void ldr_constant(Register dest, const Address &const_addr) { 1460 if (NearCpool) { 1461 ldr(dest, const_addr); 1462 } else { 1463 uint64_t offset; 1464 adrp(dest, InternalAddress(const_addr.target()), offset); 1465 ldr(dest, Address(dest, offset)); 1466 } 1467 } 1468 1469 address read_polling_page(Register r, relocInfo::relocType rtype); 1470 void get_polling_page(Register dest, relocInfo::relocType rtype); 1471 1472 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic. 1473 void update_byte_crc32(Register crc, Register val, Register table); 1474 void update_word_crc32(Register crc, Register v, Register tmp, 1475 Register table0, Register table1, Register table2, Register table3, 1476 bool upper = false); 1477 1478 address count_positives(Register ary1, Register len, Register result); 1479 1480 address arrays_equals(Register a1, Register a2, Register result, Register cnt1, 1481 Register tmp1, Register tmp2, Register tmp3, int elem_size); 1482 1483 void string_equals(Register a1, Register a2, Register result, Register cnt1); 1484 1485 void fill_words(Register base, Register cnt, Register value); 1486 void fill_words(Register base, uint64_t cnt, Register value); 1487 1488 address zero_words(Register base, uint64_t cnt); 1489 address zero_words(Register ptr, Register cnt); 1490 void zero_dcache_blocks(Register base, Register cnt); 1491 1492 static const int zero_words_block_size; 1493 1494 address byte_array_inflate(Register src, Register dst, Register len, 1495 FloatRegister vtmp1, FloatRegister vtmp2, 1496 FloatRegister vtmp3, Register tmp4); 1497 1498 void char_array_compress(Register src, Register dst, Register len, 1499 Register res, 1500 FloatRegister vtmp0, FloatRegister vtmp1, 1501 FloatRegister vtmp2, FloatRegister vtmp3, 1502 FloatRegister vtmp4, FloatRegister vtmp5); 1503 1504 void encode_iso_array(Register src, Register dst, 1505 Register len, Register res, bool ascii, 1506 FloatRegister vtmp0, FloatRegister vtmp1, 1507 FloatRegister vtmp2, FloatRegister vtmp3, 1508 FloatRegister vtmp4, FloatRegister vtmp5); 1509 1510 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi, 1511 address pio2, address dsin_coef, address dcos_coef); 1512 private: 1513 // begin trigonometric functions support block 1514 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2); 1515 void generate__kernel_rem_pio2(address two_over_pi, address pio2); 1516 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef); 1517 void generate_kernel_cos(FloatRegister x, address dcos_coef); 1518 // end trigonometric functions support block 1519 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 1520 Register src1, Register src2); 1521 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 1522 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2); 1523 } 1524 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 1525 Register y, Register y_idx, Register z, 1526 Register carry, Register product, 1527 Register idx, Register kdx); 1528 void multiply_128_x_128_loop(Register y, Register z, 1529 Register carry, Register carry2, 1530 Register idx, Register jdx, 1531 Register yz_idx1, Register yz_idx2, 1532 Register tmp, Register tmp3, Register tmp4, 1533 Register tmp7, Register product_hi); 1534 void kernel_crc32_using_crypto_pmull(Register crc, Register buf, 1535 Register len, Register tmp0, Register tmp1, Register tmp2, 1536 Register tmp3); 1537 void kernel_crc32_using_crc32(Register crc, Register buf, 1538 Register len, Register tmp0, Register tmp1, Register tmp2, 1539 Register tmp3); 1540 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf, 1541 Register len, Register tmp0, Register tmp1, Register tmp2, 1542 Register tmp3); 1543 void kernel_crc32c_using_crc32c(Register crc, Register buf, 1544 Register len, Register tmp0, Register tmp1, Register tmp2, 1545 Register tmp3); 1546 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf, 1547 Register len, Register tmp0, Register tmp1, Register tmp2, 1548 size_t table_offset); 1549 1550 void ghash_modmul (FloatRegister result, 1551 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b, 1552 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p, 1553 FloatRegister t1, FloatRegister t2, FloatRegister t3); 1554 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state); 1555 public: 1556 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, 1557 Register zlen, Register tmp1, Register tmp2, Register tmp3, 1558 Register tmp4, Register tmp5, Register tmp6, Register tmp7); 1559 void mul_add(Register out, Register in, Register offs, Register len, Register k); 1560 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi, 1561 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0, 1562 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3); 1563 void ghash_multiply_wide(int index, 1564 FloatRegister result_lo, FloatRegister result_hi, 1565 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0, 1566 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3); 1567 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi, 1568 FloatRegister p, FloatRegister z, FloatRegister t1); 1569 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi, 1570 FloatRegister p, FloatRegister z, FloatRegister t1); 1571 void ghash_processBlocks_wide(address p, Register state, Register subkeyH, 1572 Register data, Register blocks, int unrolls); 1573 1574 1575 void aesenc_loadkeys(Register key, Register keylen); 1576 void aesecb_encrypt(Register from, Register to, Register keylen, 1577 FloatRegister data = v0, int unrolls = 1); 1578 void aesecb_decrypt(Register from, Register to, Register key, Register keylen); 1579 void aes_round(FloatRegister input, FloatRegister subkey); 1580 1581 // ChaCha20 functions support block 1582 void cc20_quarter_round(FloatRegister aVec, FloatRegister bVec, 1583 FloatRegister cVec, FloatRegister dVec, FloatRegister scratch, 1584 FloatRegister tbl); 1585 void cc20_shift_lane_org(FloatRegister bVec, FloatRegister cVec, 1586 FloatRegister dVec, bool colToDiag); 1587 1588 // Place an ISB after code may have been modified due to a safepoint. 1589 void safepoint_isb(); 1590 1591 private: 1592 // Return the effective address r + (r1 << ext) + offset. 1593 // Uses rscratch2. 1594 Address offsetted_address(Register r, Register r1, Address::extend ext, 1595 int offset, int size); 1596 1597 private: 1598 // Returns an address on the stack which is reachable with a ldr/str of size 1599 // Uses rscratch2 if the address is not directly reachable 1600 Address spill_address(int size, int offset, Register tmp=rscratch2); 1601 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2); 1602 1603 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const; 1604 1605 // Check whether two loads/stores can be merged into ldp/stp. 1606 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const; 1607 1608 // Merge current load/store with previous load/store into ldp/stp. 1609 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store); 1610 1611 // Try to merge two loads/stores into ldp/stp. If success, returns true else false. 1612 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store); 1613 1614 public: 1615 void spill(Register Rx, bool is64, int offset) { 1616 if (is64) { 1617 str(Rx, spill_address(8, offset)); 1618 } else { 1619 strw(Rx, spill_address(4, offset)); 1620 } 1621 } 1622 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) { 1623 str(Vx, T, spill_address(1 << (int)T, offset)); 1624 } 1625 1626 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) { 1627 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset)); 1628 } 1629 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) { 1630 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset)); 1631 } 1632 1633 void unspill(Register Rx, bool is64, int offset) { 1634 if (is64) { 1635 ldr(Rx, spill_address(8, offset)); 1636 } else { 1637 ldrw(Rx, spill_address(4, offset)); 1638 } 1639 } 1640 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) { 1641 ldr(Vx, T, spill_address(1 << (int)T, offset)); 1642 } 1643 1644 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) { 1645 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset)); 1646 } 1647 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) { 1648 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset)); 1649 } 1650 1651 void spill_copy128(int src_offset, int dst_offset, 1652 Register tmp1=rscratch1, Register tmp2=rscratch2) { 1653 if (src_offset < 512 && (src_offset & 7) == 0 && 1654 dst_offset < 512 && (dst_offset & 7) == 0) { 1655 ldp(tmp1, tmp2, Address(sp, src_offset)); 1656 stp(tmp1, tmp2, Address(sp, dst_offset)); 1657 } else { 1658 unspill(tmp1, true, src_offset); 1659 spill(tmp1, true, dst_offset); 1660 unspill(tmp1, true, src_offset+8); 1661 spill(tmp1, true, dst_offset+8); 1662 } 1663 } 1664 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset, 1665 int sve_vec_reg_size_in_bytes) { 1666 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size"); 1667 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) { 1668 spill_copy128(src_offset, dst_offset); 1669 src_offset += 16; 1670 dst_offset += 16; 1671 } 1672 } 1673 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset, 1674 int sve_predicate_reg_size_in_bytes) { 1675 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset)); 1676 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset)); 1677 reinitialize_ptrue(); 1678 } 1679 void cache_wb(Address line); 1680 void cache_wbsync(bool is_pre); 1681 1682 // Code for java.lang.Thread::onSpinWait() intrinsic. 1683 void spin_wait(); 1684 1685 void lightweight_lock(Register obj, Register hdr, Register t1, Register t2, Label& slow); 1686 void lightweight_unlock(Register obj, Register hdr, Register t1, Register t2, Label& slow); 1687 1688 private: 1689 // Check the current thread doesn't need a cross modify fence. 1690 void verify_cross_modify_fence_not_required() PRODUCT_RETURN; 1691 1692 }; 1693 1694 #ifdef ASSERT 1695 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } 1696 #endif 1697 1698 /** 1699 * class SkipIfEqual: 1700 * 1701 * Instantiating this class will result in assembly code being output that will 1702 * jump around any code emitted between the creation of the instance and it's 1703 * automatic destruction at the end of a scope block, depending on the value of 1704 * the flag passed to the constructor, which will be checked at run-time. 1705 */ 1706 class SkipIfEqual { 1707 private: 1708 MacroAssembler* _masm; 1709 Label _label; 1710 1711 public: 1712 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 1713 ~SkipIfEqual(); 1714 }; 1715 1716 struct tableswitch { 1717 Register _reg; 1718 int _insn_index; jint _first_key; jint _last_key; 1719 Label _after; 1720 Label _branches; 1721 }; 1722 1723 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP