1 /* 2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP 27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP 28 29 #include "asm/assembler.inline.hpp" 30 #include "code/vmreg.hpp" 31 #include "metaprogramming/enableIf.hpp" 32 #include "oops/compressedOops.hpp" 33 #include "oops/compressedKlass.hpp" 34 #include "runtime/vm_version.hpp" 35 #include "utilities/macros.hpp" 36 #include "utilities/powerOfTwo.hpp" 37 #include "runtime/signature.hpp" 38 39 40 class ciInlineKlass; 41 42 class OopMap; 43 44 // MacroAssembler extends Assembler by frequently used macros. 45 // 46 // Instructions for which a 'better' code sequence exists depending 47 // on arguments should also go in here. 48 49 class MacroAssembler: public Assembler { 50 friend class LIR_Assembler; 51 52 public: 53 using Assembler::mov; 54 using Assembler::movi; 55 56 protected: 57 58 // Support for VM calls 59 // 60 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 61 // may customize this version by overriding it for its purposes (e.g., to save/restore 62 // additional registers when doing a VM call). 63 virtual void call_VM_leaf_base( 64 address entry_point, // the entry point 65 int number_of_arguments, // the number of arguments to pop after the call 66 Label *retaddr = nullptr 67 ); 68 69 virtual void call_VM_leaf_base( 70 address entry_point, // the entry point 71 int number_of_arguments, // the number of arguments to pop after the call 72 Label &retaddr) { 73 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr); 74 } 75 76 // This is the base routine called by the different versions of call_VM. The interpreter 77 // may customize this version by overriding it for its purposes (e.g., to save/restore 78 // additional registers when doing a VM call). 79 // 80 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base 81 // returns the register which contains the thread upon return. If a thread register has been 82 // specified, the return value will correspond to that register. If no last_java_sp is specified 83 // (noreg) than rsp will be used instead. 84 virtual void call_VM_base( // returns the register containing the thread upon return 85 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 86 Register java_thread, // the thread if computed before ; use noreg otherwise 87 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 88 address entry_point, // the entry point 89 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 90 bool check_exceptions // whether to check for pending exceptions after return 91 ); 92 93 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 94 95 enum KlassDecodeMode { 96 KlassDecodeNone, 97 KlassDecodeZero, 98 KlassDecodeXor, 99 KlassDecodeMovk 100 }; 101 102 // Calculate decoding mode based on given parameters, used for checking then ultimately setting. 103 static KlassDecodeMode klass_decode_mode(address base, int shift, const size_t range); 104 105 private: 106 static KlassDecodeMode _klass_decode_mode; 107 108 // Returns above setting with asserts 109 static KlassDecodeMode klass_decode_mode(); 110 111 public: 112 // Checks the decode mode and returns false if not compatible with preferred decoding mode. 113 static bool check_klass_decode_mode(address base, int shift, const size_t range); 114 115 // Sets the decode mode and returns false if cannot be set. 116 static bool set_klass_decode_mode(address base, int shift, const size_t range); 117 118 public: 119 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 120 121 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 122 // The implementation is only non-empty for the InterpreterMacroAssembler, 123 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 124 virtual void check_and_handle_popframe(Register java_thread); 125 virtual void check_and_handle_earlyret(Register java_thread); 126 127 void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1); 128 void rt_call(address dest, Register tmp = rscratch1); 129 130 // Load Effective Address 131 void lea(Register r, const Address &a) { 132 InstructionMark im(this); 133 a.lea(this, r); 134 } 135 136 /* Sometimes we get misaligned loads and stores, usually from Unsafe 137 accesses, and these can exceed the offset range. */ 138 Address legitimize_address(const Address &a, int size, Register scratch) { 139 if (a.getMode() == Address::base_plus_offset) { 140 if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) { 141 block_comment("legitimize_address {"); 142 lea(scratch, a); 143 block_comment("} legitimize_address"); 144 return Address(scratch); 145 } 146 } 147 return a; 148 } 149 150 void addmw(Address a, Register incr, Register scratch) { 151 ldrw(scratch, a); 152 addw(scratch, scratch, incr); 153 strw(scratch, a); 154 } 155 156 // Add constant to memory word 157 void addmw(Address a, int imm, Register scratch) { 158 ldrw(scratch, a); 159 if (imm > 0) 160 addw(scratch, scratch, (unsigned)imm); 161 else 162 subw(scratch, scratch, (unsigned)-imm); 163 strw(scratch, a); 164 } 165 166 void bind(Label& L) { 167 Assembler::bind(L); 168 code()->clear_last_insn(); 169 code()->set_last_label(pc()); 170 } 171 172 void membar(Membar_mask_bits order_constraint); 173 174 using Assembler::ldr; 175 using Assembler::str; 176 using Assembler::ldrw; 177 using Assembler::strw; 178 179 void ldr(Register Rx, const Address &adr); 180 void ldrw(Register Rw, const Address &adr); 181 void str(Register Rx, const Address &adr); 182 void strw(Register Rx, const Address &adr); 183 184 // Frame creation and destruction shared between JITs. 185 void build_frame(int framesize); 186 void remove_frame(int framesize); 187 188 virtual void _call_Unimplemented(address call_site) { 189 mov(rscratch2, call_site); 190 } 191 192 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__ 193 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention." 194 // https://reviews.llvm.org/D3311 195 196 #ifdef _WIN64 197 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__) 198 #else 199 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__) 200 #endif 201 202 // aliases defined in AARCH64 spec 203 204 template<class T> 205 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); } 206 207 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); } 208 inline void cmp(Register Rd, unsigned imm) = delete; 209 210 template<class T> 211 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); } 212 213 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); } 214 inline void cmn(Register Rd, unsigned imm) = delete; 215 216 void cset(Register Rd, Assembler::Condition cond) { 217 csinc(Rd, zr, zr, ~cond); 218 } 219 void csetw(Register Rd, Assembler::Condition cond) { 220 csincw(Rd, zr, zr, ~cond); 221 } 222 223 void cneg(Register Rd, Register Rn, Assembler::Condition cond) { 224 csneg(Rd, Rn, Rn, ~cond); 225 } 226 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) { 227 csnegw(Rd, Rn, Rn, ~cond); 228 } 229 230 inline void movw(Register Rd, Register Rn) { 231 if (Rd == sp || Rn == sp) { 232 Assembler::addw(Rd, Rn, 0U); 233 } else { 234 orrw(Rd, zr, Rn); 235 } 236 } 237 inline void mov(Register Rd, Register Rn) { 238 assert(Rd != r31_sp && Rn != r31_sp, "should be"); 239 if (Rd == Rn) { 240 } else if (Rd == sp || Rn == sp) { 241 Assembler::add(Rd, Rn, 0U); 242 } else { 243 orr(Rd, zr, Rn); 244 } 245 } 246 247 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); } 248 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); } 249 250 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); } 251 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); } 252 253 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); } 254 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); } 255 256 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 257 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 258 } 259 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) { 260 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 261 } 262 263 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 264 bfmw(Rd, Rn, lsb, (lsb + width - 1)); 265 } 266 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) { 267 bfm(Rd, Rn, lsb , (lsb + width - 1)); 268 } 269 270 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 271 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 272 } 273 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 274 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 275 } 276 277 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 278 sbfmw(Rd, Rn, lsb, (lsb + width - 1)); 279 } 280 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 281 sbfm(Rd, Rn, lsb , (lsb + width - 1)); 282 } 283 284 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 285 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 286 } 287 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 288 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 289 } 290 291 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 292 ubfmw(Rd, Rn, lsb, (lsb + width - 1)); 293 } 294 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 295 ubfm(Rd, Rn, lsb , (lsb + width - 1)); 296 } 297 298 inline void asrw(Register Rd, Register Rn, unsigned imm) { 299 sbfmw(Rd, Rn, imm, 31); 300 } 301 302 inline void asr(Register Rd, Register Rn, unsigned imm) { 303 sbfm(Rd, Rn, imm, 63); 304 } 305 306 inline void lslw(Register Rd, Register Rn, unsigned imm) { 307 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm)); 308 } 309 310 inline void lsl(Register Rd, Register Rn, unsigned imm) { 311 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm)); 312 } 313 314 inline void lsrw(Register Rd, Register Rn, unsigned imm) { 315 ubfmw(Rd, Rn, imm, 31); 316 } 317 318 inline void lsr(Register Rd, Register Rn, unsigned imm) { 319 ubfm(Rd, Rn, imm, 63); 320 } 321 322 inline void rorw(Register Rd, Register Rn, unsigned imm) { 323 extrw(Rd, Rn, Rn, imm); 324 } 325 326 inline void ror(Register Rd, Register Rn, unsigned imm) { 327 extr(Rd, Rn, Rn, imm); 328 } 329 330 inline void sxtbw(Register Rd, Register Rn) { 331 sbfmw(Rd, Rn, 0, 7); 332 } 333 inline void sxthw(Register Rd, Register Rn) { 334 sbfmw(Rd, Rn, 0, 15); 335 } 336 inline void sxtb(Register Rd, Register Rn) { 337 sbfm(Rd, Rn, 0, 7); 338 } 339 inline void sxth(Register Rd, Register Rn) { 340 sbfm(Rd, Rn, 0, 15); 341 } 342 inline void sxtw(Register Rd, Register Rn) { 343 sbfm(Rd, Rn, 0, 31); 344 } 345 346 inline void uxtbw(Register Rd, Register Rn) { 347 ubfmw(Rd, Rn, 0, 7); 348 } 349 inline void uxthw(Register Rd, Register Rn) { 350 ubfmw(Rd, Rn, 0, 15); 351 } 352 inline void uxtb(Register Rd, Register Rn) { 353 ubfm(Rd, Rn, 0, 7); 354 } 355 inline void uxth(Register Rd, Register Rn) { 356 ubfm(Rd, Rn, 0, 15); 357 } 358 inline void uxtw(Register Rd, Register Rn) { 359 ubfm(Rd, Rn, 0, 31); 360 } 361 362 inline void cmnw(Register Rn, Register Rm) { 363 addsw(zr, Rn, Rm); 364 } 365 inline void cmn(Register Rn, Register Rm) { 366 adds(zr, Rn, Rm); 367 } 368 369 inline void cmpw(Register Rn, Register Rm) { 370 subsw(zr, Rn, Rm); 371 } 372 inline void cmp(Register Rn, Register Rm) { 373 subs(zr, Rn, Rm); 374 } 375 376 inline void negw(Register Rd, Register Rn) { 377 subw(Rd, zr, Rn); 378 } 379 380 inline void neg(Register Rd, Register Rn) { 381 sub(Rd, zr, Rn); 382 } 383 384 inline void negsw(Register Rd, Register Rn) { 385 subsw(Rd, zr, Rn); 386 } 387 388 inline void negs(Register Rd, Register Rn) { 389 subs(Rd, zr, Rn); 390 } 391 392 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 393 addsw(zr, Rn, Rm, kind, shift); 394 } 395 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 396 adds(zr, Rn, Rm, kind, shift); 397 } 398 399 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 400 subsw(zr, Rn, Rm, kind, shift); 401 } 402 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 403 subs(zr, Rn, Rm, kind, shift); 404 } 405 406 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 407 subw(Rd, zr, Rn, kind, shift); 408 } 409 410 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 411 sub(Rd, zr, Rn, kind, shift); 412 } 413 414 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 415 subsw(Rd, zr, Rn, kind, shift); 416 } 417 418 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 419 subs(Rd, zr, Rn, kind, shift); 420 } 421 422 inline void mnegw(Register Rd, Register Rn, Register Rm) { 423 msubw(Rd, Rn, Rm, zr); 424 } 425 inline void mneg(Register Rd, Register Rn, Register Rm) { 426 msub(Rd, Rn, Rm, zr); 427 } 428 429 inline void mulw(Register Rd, Register Rn, Register Rm) { 430 maddw(Rd, Rn, Rm, zr); 431 } 432 inline void mul(Register Rd, Register Rn, Register Rm) { 433 madd(Rd, Rn, Rm, zr); 434 } 435 436 inline void smnegl(Register Rd, Register Rn, Register Rm) { 437 smsubl(Rd, Rn, Rm, zr); 438 } 439 inline void smull(Register Rd, Register Rn, Register Rm) { 440 smaddl(Rd, Rn, Rm, zr); 441 } 442 443 inline void umnegl(Register Rd, Register Rn, Register Rm) { 444 umsubl(Rd, Rn, Rm, zr); 445 } 446 inline void umull(Register Rd, Register Rn, Register Rm) { 447 umaddl(Rd, Rn, Rm, zr); 448 } 449 450 #define WRAP(INSN) \ 451 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \ 452 if (VM_Version::supports_a53mac() && Ra != zr) \ 453 nop(); \ 454 Assembler::INSN(Rd, Rn, Rm, Ra); \ 455 } 456 457 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw) 458 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl) 459 #undef WRAP 460 461 462 // macro assembly operations needed for aarch64 463 464 public: 465 466 enum FpPushPopMode { 467 PushPopFull, 468 PushPopSVE, 469 PushPopNeon, 470 PushPopFp 471 }; 472 473 // first two private routines for loading 32 bit or 64 bit constants 474 private: 475 476 void mov_immediate64(Register dst, uint64_t imm64); 477 void mov_immediate32(Register dst, uint32_t imm32); 478 479 int push(unsigned int bitset, Register stack); 480 int pop(unsigned int bitset, Register stack); 481 482 int push_fp(unsigned int bitset, Register stack, FpPushPopMode mode); 483 int pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode); 484 485 int push_p(unsigned int bitset, Register stack); 486 int pop_p(unsigned int bitset, Register stack); 487 488 void mov(Register dst, Address a); 489 490 public: 491 492 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); } 493 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); } 494 495 void push_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) push_fp(regs.bits(), stack, mode); } 496 void pop_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) pop_fp(regs.bits(), stack, mode); } 497 498 static RegSet call_clobbered_gp_registers(); 499 500 void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); } 501 void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); } 502 503 // Push and pop everything that might be clobbered by a native 504 // runtime call except rscratch1 and rscratch2. (They are always 505 // scratch, so we don't have to protect them.) Only save the lower 506 // 64 bits of each vector register. Additional registers can be excluded 507 // in a passed RegSet. 508 void push_call_clobbered_registers_except(RegSet exclude); 509 void pop_call_clobbered_registers_except(RegSet exclude); 510 511 void push_call_clobbered_registers() { 512 push_call_clobbered_registers_except(RegSet()); 513 } 514 void pop_call_clobbered_registers() { 515 pop_call_clobbered_registers_except(RegSet()); 516 } 517 518 519 // now mov instructions for loading absolute addresses and 32 or 520 // 64 bit integers 521 522 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); } 523 524 template<typename T, ENABLE_IF(std::is_integral<T>::value)> 525 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); } 526 527 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); } 528 529 void mov(Register dst, RegisterOrConstant src) { 530 if (src.is_register()) 531 mov(dst, src.as_register()); 532 else 533 mov(dst, src.as_constant()); 534 } 535 536 void movptr(Register r, uintptr_t imm64); 537 538 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64); 539 540 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { 541 orr(Vd, T, Vn, Vn); 542 } 543 544 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) { 545 fcvtsh(tmp, src); 546 smov(dst, tmp, H, 0); 547 } 548 549 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) { 550 mov(tmp, H, 0, src); 551 fcvths(dst, tmp); 552 } 553 554 // Generalized Test Bit And Branch, including a "far" variety which 555 // spans more than 32KiB. 556 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) { 557 assert(cond == EQ || cond == NE, "must be"); 558 559 if (isfar) 560 cond = ~cond; 561 562 void (Assembler::* branch)(Register Rt, int bitpos, Label &L); 563 if (cond == Assembler::EQ) 564 branch = &Assembler::tbz; 565 else 566 branch = &Assembler::tbnz; 567 568 if (isfar) { 569 Label L; 570 (this->*branch)(Rt, bitpos, L); 571 b(dest); 572 bind(L); 573 } else { 574 (this->*branch)(Rt, bitpos, dest); 575 } 576 } 577 578 // macro instructions for accessing and updating floating point 579 // status register 580 // 581 // FPSR : op1 == 011 582 // CRn == 0100 583 // CRm == 0100 584 // op2 == 001 585 586 inline void get_fpsr(Register reg) 587 { 588 mrs(0b11, 0b0100, 0b0100, 0b001, reg); 589 } 590 591 inline void set_fpsr(Register reg) 592 { 593 msr(0b011, 0b0100, 0b0100, 0b001, reg); 594 } 595 596 inline void clear_fpsr() 597 { 598 msr(0b011, 0b0100, 0b0100, 0b001, zr); 599 } 600 601 // FPCR : op1 == 011 602 // CRn == 0100 603 // CRm == 0100 604 // op2 == 000 605 606 inline void get_fpcr(Register reg) { 607 mrs(0b11, 0b0100, 0b0100, 0b000, reg); 608 } 609 610 inline void set_fpcr(Register reg) { 611 msr(0b011, 0b0100, 0b0100, 0b000, reg); 612 } 613 614 // DCZID_EL0: op1 == 011 615 // CRn == 0000 616 // CRm == 0000 617 // op2 == 111 618 inline void get_dczid_el0(Register reg) 619 { 620 mrs(0b011, 0b0000, 0b0000, 0b111, reg); 621 } 622 623 // CTR_EL0: op1 == 011 624 // CRn == 0000 625 // CRm == 0000 626 // op2 == 001 627 inline void get_ctr_el0(Register reg) 628 { 629 mrs(0b011, 0b0000, 0b0000, 0b001, reg); 630 } 631 632 inline void get_nzcv(Register reg) { 633 mrs(0b011, 0b0100, 0b0010, 0b000, reg); 634 } 635 636 inline void set_nzcv(Register reg) { 637 msr(0b011, 0b0100, 0b0010, 0b000, reg); 638 } 639 640 // idiv variant which deals with MINLONG as dividend and -1 as divisor 641 int corrected_idivl(Register result, Register ra, Register rb, 642 bool want_remainder, Register tmp = rscratch1); 643 int corrected_idivq(Register result, Register ra, Register rb, 644 bool want_remainder, Register tmp = rscratch1); 645 646 // Support for null-checks 647 // 648 // Generates code that causes a null OS exception if the content of reg is null. 649 // If the accessed location is M[reg + offset] and the offset is known, provide the 650 // offset. No explicit code generation is needed if the offset is within a certain 651 // range (0 <= offset <= page_size). 652 653 virtual void null_check(Register reg, int offset = -1); 654 static bool needs_explicit_null_check(intptr_t offset); 655 static bool uses_implicit_null_check(void* address); 656 657 // markWord tests, kills markWord reg 658 void test_markword_is_inline_type(Register markword, Label& is_inline_type); 659 660 // inlineKlass queries, kills temp_reg 661 void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type); 662 void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type); 663 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type); 664 665 // Get the default value oop for the given InlineKlass 666 void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj); 667 // The empty value oop, for the given InlineKlass ("empty" as in no instance fields) 668 // get_default_value_oop with extra assertion for empty inline klass 669 void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj); 670 671 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free); 672 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free); 673 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat); 674 void test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker); 675 676 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays 677 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label); 678 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array); 679 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array); 680 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array); 681 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array); 682 683 // Check array klass layout helper for flat or null-free arrays... 684 void test_flat_array_layout(Register lh, Label& is_flat_array); 685 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array); 686 687 static address target_addr_for_insn(address insn_addr, unsigned insn); 688 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn); 689 static address target_addr_for_insn(address insn_addr) { 690 unsigned insn = *(unsigned*)insn_addr; 691 return target_addr_for_insn(insn_addr, insn); 692 } 693 static address target_addr_for_insn_or_null(address insn_addr) { 694 unsigned insn = *(unsigned*)insn_addr; 695 return target_addr_for_insn_or_null(insn_addr, insn); 696 } 697 698 // Required platform-specific helpers for Label::patch_instructions. 699 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 700 static int pd_patch_instruction_size(address branch, address target); 701 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) { 702 pd_patch_instruction_size(branch, target); 703 } 704 static address pd_call_destination(address branch) { 705 return target_addr_for_insn(branch); 706 } 707 #ifndef PRODUCT 708 static void pd_print_patched_instruction(address branch); 709 #endif 710 711 static int patch_oop(address insn_addr, address o); 712 static int patch_narrow_klass(address insn_addr, narrowKlass n); 713 714 // Return whether code is emitted to a scratch blob. 715 virtual bool in_scratch_emit_size() { 716 return false; 717 } 718 address emit_trampoline_stub(int insts_call_instruction_offset, address target); 719 static int max_trampoline_stub_size(); 720 void emit_static_call_stub(); 721 static int static_call_stub_size(); 722 723 // The following 4 methods return the offset of the appropriate move instruction 724 725 // Support for fast byte/short loading with zero extension (depending on particular CPU) 726 int load_unsigned_byte(Register dst, Address src); 727 int load_unsigned_short(Register dst, Address src); 728 729 // Support for fast byte/short loading with sign extension (depending on particular CPU) 730 int load_signed_byte(Register dst, Address src); 731 int load_signed_short(Register dst, Address src); 732 733 int load_signed_byte32(Register dst, Address src); 734 int load_signed_short32(Register dst, Address src); 735 736 // Support for sign-extension (hi:lo = extend_sign(lo)) 737 void extend_sign(Register hi, Register lo); 738 739 // Load and store values by size and signed-ness 740 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed); 741 void store_sized_value(Address dst, Register src, size_t size_in_bytes); 742 743 // Support for inc/dec with optimal instruction selection depending on value 744 745 // x86_64 aliases an unqualified register/address increment and 746 // decrement to call incrementq and decrementq but also supports 747 // explicitly sized calls to incrementq/decrementq or 748 // incrementl/decrementl 749 750 // for aarch64 the proper convention would be to use 751 // increment/decrement for 64 bit operations and 752 // incrementw/decrementw for 32 bit operations. so when porting 753 // x86_64 code we can leave calls to increment/decrement as is, 754 // replace incrementq/decrementq with increment/decrement and 755 // replace incrementl/decrementl with incrementw/decrementw. 756 757 // n.b. increment/decrement calls with an Address destination will 758 // need to use a scratch register to load the value to be 759 // incremented. increment/decrement calls which add or subtract a 760 // constant value greater than 2^12 will need to use a 2nd scratch 761 // register to hold the constant. so, a register increment/decrement 762 // may trash rscratch2 and an address increment/decrement trash 763 // rscratch and rscratch2 764 765 void decrementw(Address dst, int value = 1); 766 void decrementw(Register reg, int value = 1); 767 768 void decrement(Register reg, int value = 1); 769 void decrement(Address dst, int value = 1); 770 771 void incrementw(Address dst, int value = 1); 772 void incrementw(Register reg, int value = 1); 773 774 void increment(Register reg, int value = 1); 775 void increment(Address dst, int value = 1); 776 777 778 // Alignment 779 void align(int modulus); 780 void align(int modulus, int target); 781 782 // nop 783 void post_call_nop(); 784 785 // Stack frame creation/removal 786 void enter(bool strip_ret_addr = false); 787 void leave(); 788 789 // ROP Protection 790 void protect_return_address(); 791 void protect_return_address(Register return_reg); 792 void authenticate_return_address(); 793 void authenticate_return_address(Register return_reg); 794 void strip_return_address(); 795 void check_return_address(Register return_reg=lr) PRODUCT_RETURN; 796 797 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 798 // The pointer will be loaded into the thread register. 799 void get_thread(Register thread); 800 801 // support for argument shuffling 802 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1); 803 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1); 804 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1); 805 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1); 806 void object_move( 807 OopMap* map, 808 int oop_handle_offset, 809 int framesize_in_slots, 810 VMRegPair src, 811 VMRegPair dst, 812 bool is_receiver, 813 int* receiver_offset); 814 815 816 // Support for VM calls 817 // 818 // It is imperative that all calls into the VM are handled via the call_VM macros. 819 // They make sure that the stack linkage is setup correctly. call_VM's correspond 820 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 821 822 823 void call_VM(Register oop_result, 824 address entry_point, 825 bool check_exceptions = true); 826 void call_VM(Register oop_result, 827 address entry_point, 828 Register arg_1, 829 bool check_exceptions = true); 830 void call_VM(Register oop_result, 831 address entry_point, 832 Register arg_1, Register arg_2, 833 bool check_exceptions = true); 834 void call_VM(Register oop_result, 835 address entry_point, 836 Register arg_1, Register arg_2, Register arg_3, 837 bool check_exceptions = true); 838 839 // Overloadings with last_Java_sp 840 void call_VM(Register oop_result, 841 Register last_java_sp, 842 address entry_point, 843 int number_of_arguments = 0, 844 bool check_exceptions = true); 845 void call_VM(Register oop_result, 846 Register last_java_sp, 847 address entry_point, 848 Register arg_1, bool 849 check_exceptions = true); 850 void call_VM(Register oop_result, 851 Register last_java_sp, 852 address entry_point, 853 Register arg_1, Register arg_2, 854 bool check_exceptions = true); 855 void call_VM(Register oop_result, 856 Register last_java_sp, 857 address entry_point, 858 Register arg_1, Register arg_2, Register arg_3, 859 bool check_exceptions = true); 860 861 void get_vm_result (Register oop_result, Register thread); 862 void get_vm_result_2(Register metadata_result, Register thread); 863 864 // These always tightly bind to MacroAssembler::call_VM_base 865 // bypassing the virtual implementation 866 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 867 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 868 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 869 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 870 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 871 872 void call_VM_leaf(address entry_point, 873 int number_of_arguments = 0); 874 void call_VM_leaf(address entry_point, 875 Register arg_1); 876 void call_VM_leaf(address entry_point, 877 Register arg_1, Register arg_2); 878 void call_VM_leaf(address entry_point, 879 Register arg_1, Register arg_2, Register arg_3); 880 881 // These always tightly bind to MacroAssembler::call_VM_leaf_base 882 // bypassing the virtual implementation 883 void super_call_VM_leaf(address entry_point); 884 void super_call_VM_leaf(address entry_point, Register arg_1); 885 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 886 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 887 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 888 889 // last Java Frame (fills frame anchor) 890 void set_last_Java_frame(Register last_java_sp, 891 Register last_java_fp, 892 address last_java_pc, 893 Register scratch); 894 895 void set_last_Java_frame(Register last_java_sp, 896 Register last_java_fp, 897 Label &last_java_pc, 898 Register scratch); 899 900 void set_last_Java_frame(Register last_java_sp, 901 Register last_java_fp, 902 Register last_java_pc, 903 Register scratch); 904 905 void reset_last_Java_frame(Register thread); 906 907 // thread in the default location (rthread) 908 void reset_last_Java_frame(bool clear_fp); 909 910 // Stores 911 void store_check(Register obj); // store check for obj - register is destroyed afterwards 912 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 913 914 void resolve_jobject(Register value, Register tmp1, Register tmp2); 915 void resolve_global_jobject(Register value, Register tmp1, Register tmp2); 916 917 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 918 void c2bool(Register x); 919 920 void load_method_holder_cld(Register rresult, Register rmethod); 921 void load_method_holder(Register holder, Register method); 922 923 // oop manipulations 924 void load_metadata(Register dst, Register src); 925 926 void load_narrow_klass_compact(Register dst, Register src); 927 void load_klass(Register dst, Register src); 928 void store_klass(Register dst, Register src); 929 void cmp_klass(Register obj, Register klass, Register tmp); 930 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2); 931 932 void resolve_weak_handle(Register result, Register tmp1, Register tmp2); 933 void resolve_oop_handle(Register result, Register tmp1, Register tmp2); 934 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2); 935 936 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src, 937 Register tmp1, Register tmp2); 938 939 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val, 940 Register tmp1, Register tmp2, Register tmp3); 941 942 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info); 943 944 // inline type data payload offsets... 945 void payload_offset(Register inline_klass, Register offset); 946 void payload_address(Register oop, Register data, Register inline_klass); 947 // get data payload ptr a flat value array at index, kills rcx and index 948 void data_for_value_array_index(Register array, Register array_klass, 949 Register index, Register data); 950 951 void load_heap_oop(Register dst, Address src, Register tmp1, 952 Register tmp2, DecoratorSet decorators = 0); 953 954 void load_heap_oop_not_null(Register dst, Address src, Register tmp1, 955 Register tmp2, DecoratorSet decorators = 0); 956 void store_heap_oop(Address dst, Register val, Register tmp1, 957 Register tmp2, Register tmp3, DecoratorSet decorators = 0); 958 959 // currently unimplemented 960 // Used for storing null. All other oop constants should be 961 // stored using routines that take a jobject. 962 void store_heap_oop_null(Address dst); 963 964 void load_prototype_header(Register dst, Register src); 965 966 void store_klass_gap(Register dst, Register src); 967 968 // This dummy is to prevent a call to store_heap_oop from 969 // converting a zero (like null) into a Register by giving 970 // the compiler two choices it can't resolve 971 972 void store_heap_oop(Address dst, void* dummy); 973 974 void encode_heap_oop(Register d, Register s); 975 void encode_heap_oop(Register r) { encode_heap_oop(r, r); } 976 void decode_heap_oop(Register d, Register s); 977 void decode_heap_oop(Register r) { decode_heap_oop(r, r); } 978 void encode_heap_oop_not_null(Register r); 979 void decode_heap_oop_not_null(Register r); 980 void encode_heap_oop_not_null(Register dst, Register src); 981 void decode_heap_oop_not_null(Register dst, Register src); 982 983 void set_narrow_oop(Register dst, jobject obj); 984 985 void encode_klass_not_null(Register r); 986 void decode_klass_not_null(Register r); 987 void encode_klass_not_null(Register dst, Register src); 988 void decode_klass_not_null(Register dst, Register src); 989 990 void set_narrow_klass(Register dst, Klass* k); 991 992 // if heap base register is used - reinit it with the correct value 993 void reinit_heapbase(); 994 995 DEBUG_ONLY(void verify_heapbase(const char* msg);) 996 997 void push_CPU_state(bool save_vectors = false, bool use_sve = false, 998 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0); 999 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false, 1000 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0); 1001 1002 void push_cont_fastpath(Register java_thread = rthread); 1003 void pop_cont_fastpath(Register java_thread = rthread); 1004 1005 void inc_held_monitor_count(Register tmp); 1006 void dec_held_monitor_count(Register tmp); 1007 1008 // Round up to a power of two 1009 void round_to(Register reg, int modulus); 1010 1011 // java.lang.Math::round intrinsics 1012 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp); 1013 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp); 1014 1015 // allocation 1016 1017 // Object / value buffer allocation... 1018 // Allocate instance of klass, assumes klass initialized by caller 1019 // new_obj prefers to be rax 1020 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64) 1021 void allocate_instance(Register klass, Register new_obj, 1022 Register t1, Register t2, 1023 bool clear_fields, Label& alloc_failed); 1024 1025 void tlab_allocate( 1026 Register obj, // result: pointer to object after successful allocation 1027 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 1028 int con_size_in_bytes, // object size in bytes if known at compile time 1029 Register t1, // temp register 1030 Register t2, // temp register 1031 Label& slow_case // continuation point if fast allocation fails 1032 ); 1033 void verify_tlab(); 1034 1035 // For field "index" within "klass", return inline_klass ... 1036 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass); 1037 void inline_layout_info(Register holder_klass, Register index, Register layout_info); 1038 1039 1040 // interface method calling 1041 void lookup_interface_method(Register recv_klass, 1042 Register intf_klass, 1043 RegisterOrConstant itable_index, 1044 Register method_result, 1045 Register scan_temp, 1046 Label& no_such_interface, 1047 bool return_method = true); 1048 1049 void lookup_interface_method_stub(Register recv_klass, 1050 Register holder_klass, 1051 Register resolved_klass, 1052 Register method_result, 1053 Register temp_reg, 1054 Register temp_reg2, 1055 int itable_index, 1056 Label& L_no_such_interface); 1057 1058 // virtual method calling 1059 // n.b. x86 allows RegisterOrConstant for vtable_index 1060 void lookup_virtual_method(Register recv_klass, 1061 RegisterOrConstant vtable_index, 1062 Register method_result); 1063 1064 // Test sub_klass against super_klass, with fast and slow paths. 1065 1066 // The fast path produces a tri-state answer: yes / no / maybe-slow. 1067 // One of the three labels can be null, meaning take the fall-through. 1068 // If super_check_offset is -1, the value is loaded up from super_klass. 1069 // No registers are killed, except temp_reg. 1070 void check_klass_subtype_fast_path(Register sub_klass, 1071 Register super_klass, 1072 Register temp_reg, 1073 Label* L_success, 1074 Label* L_failure, 1075 Label* L_slow_path, 1076 Register super_check_offset = noreg); 1077 1078 // The rest of the type check; must be wired to a corresponding fast path. 1079 // It does not repeat the fast path logic, so don't use it standalone. 1080 // The temp_reg and temp2_reg can be noreg, if no temps are available. 1081 // Updates the sub's secondary super cache as necessary. 1082 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 1083 void check_klass_subtype_slow_path(Register sub_klass, 1084 Register super_klass, 1085 Register temp_reg, 1086 Register temp2_reg, 1087 Label* L_success, 1088 Label* L_failure, 1089 bool set_cond_codes = false); 1090 1091 void check_klass_subtype_slow_path_linear(Register sub_klass, 1092 Register super_klass, 1093 Register temp_reg, 1094 Register temp2_reg, 1095 Label* L_success, 1096 Label* L_failure, 1097 bool set_cond_codes = false); 1098 1099 void check_klass_subtype_slow_path_table(Register sub_klass, 1100 Register super_klass, 1101 Register temp_reg, 1102 Register temp2_reg, 1103 Register temp3_reg, 1104 Register result_reg, 1105 FloatRegister vtemp_reg, 1106 Label* L_success, 1107 Label* L_failure, 1108 bool set_cond_codes = false); 1109 1110 // If r is valid, return r. 1111 // If r is invalid, remove a register r2 from available_regs, add r2 1112 // to regs_to_push, then return r2. 1113 Register allocate_if_noreg(const Register r, 1114 RegSetIterator<Register> &available_regs, 1115 RegSet ®s_to_push); 1116 1117 // Secondary subtype checking 1118 void lookup_secondary_supers_table_var(Register sub_klass, 1119 Register r_super_klass, 1120 Register temp1, 1121 Register temp2, 1122 Register temp3, 1123 FloatRegister vtemp, 1124 Register result, 1125 Label *L_success); 1126 1127 1128 // As above, but with a constant super_klass. 1129 // The result is in Register result, not the condition codes. 1130 bool lookup_secondary_supers_table_const(Register r_sub_klass, 1131 Register r_super_klass, 1132 Register temp1, 1133 Register temp2, 1134 Register temp3, 1135 FloatRegister vtemp, 1136 Register result, 1137 u1 super_klass_slot, 1138 bool stub_is_near = false); 1139 1140 void verify_secondary_supers_table(Register r_sub_klass, 1141 Register r_super_klass, 1142 Register temp1, 1143 Register temp2, 1144 Register result); 1145 1146 void lookup_secondary_supers_table_slow_path(Register r_super_klass, 1147 Register r_array_base, 1148 Register r_array_index, 1149 Register r_bitmap, 1150 Register temp1, 1151 Register result, 1152 bool is_stub = true); 1153 1154 // Simplified, combined version, good for typical uses. 1155 // Falls through on failure. 1156 void check_klass_subtype(Register sub_klass, 1157 Register super_klass, 1158 Register temp_reg, 1159 Label& L_success); 1160 1161 void clinit_barrier(Register klass, 1162 Register thread, 1163 Label* L_fast_path = nullptr, 1164 Label* L_slow_path = nullptr); 1165 1166 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 1167 1168 void verify_sve_vector_length(Register tmp = rscratch1); 1169 void reinitialize_ptrue() { 1170 if (UseSVE > 0) { 1171 sve_ptrue(ptrue, B); 1172 } 1173 } 1174 void verify_ptrue(); 1175 1176 // Debugging 1177 1178 // only if +VerifyOops 1179 void _verify_oop(Register reg, const char* s, const char* file, int line); 1180 void _verify_oop_addr(Address addr, const char * s, const char* file, int line); 1181 1182 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) { 1183 if (VerifyOops) { 1184 _verify_oop(reg, s, file, line); 1185 } 1186 } 1187 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) { 1188 if (VerifyOops) { 1189 _verify_oop_addr(reg, s, file, line); 1190 } 1191 } 1192 1193 // TODO: verify method and klass metadata (compare against vptr?) 1194 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 1195 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 1196 1197 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__) 1198 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__) 1199 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__) 1200 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 1201 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 1202 1203 // Restore cpu control state after JNI call 1204 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2); 1205 1206 // prints msg, dumps registers and stops execution 1207 void stop(const char* msg); 1208 1209 static void debug64(char* msg, int64_t pc, int64_t regs[]); 1210 1211 void untested() { stop("untested"); } 1212 1213 void unimplemented(const char* what = ""); 1214 1215 void should_not_reach_here() { stop("should not reach here"); } 1216 1217 void _assert_asm(Condition cc, const char* msg); 1218 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg) 1219 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg)) 1220 1221 // Stack overflow checking 1222 void bang_stack_with_offset(int offset) { 1223 // stack grows down, caller passes positive offset 1224 assert(offset > 0, "must bang with negative offset"); 1225 sub(rscratch2, sp, offset); 1226 str(zr, Address(rscratch2)); 1227 } 1228 1229 // Writes to stack successive pages until offset reached to check for 1230 // stack overflow + shadow pages. Also, clobbers tmp 1231 void bang_stack_size(Register size, Register tmp); 1232 1233 // Check for reserved stack access in method being exited (for JIT) 1234 void reserved_stack_check(); 1235 1236 // Arithmetics 1237 1238 // Clobber: rscratch1, rscratch2 1239 void addptr(const Address &dst, int32_t src); 1240 1241 // Clobber: rscratch1 1242 void cmpptr(Register src1, Address src2); 1243 1244 void cmpoop(Register obj1, Register obj2); 1245 1246 // Various forms of CAS 1247 1248 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp, 1249 Label &succeed, Label *fail); 1250 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 1251 Label &succeed, Label *fail); 1252 1253 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 1254 Label &succeed, Label *fail); 1255 1256 void atomic_add(Register prev, RegisterOrConstant incr, Register addr); 1257 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr); 1258 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr); 1259 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr); 1260 1261 void atomic_xchg(Register prev, Register newv, Register addr); 1262 void atomic_xchgw(Register prev, Register newv, Register addr); 1263 void atomic_xchgl(Register prev, Register newv, Register addr); 1264 void atomic_xchglw(Register prev, Register newv, Register addr); 1265 void atomic_xchgal(Register prev, Register newv, Register addr); 1266 void atomic_xchgalw(Register prev, Register newv, Register addr); 1267 1268 void orptr(Address adr, RegisterOrConstant src) { 1269 ldr(rscratch1, adr); 1270 if (src.is_register()) 1271 orr(rscratch1, rscratch1, src.as_register()); 1272 else 1273 orr(rscratch1, rscratch1, src.as_constant()); 1274 str(rscratch1, adr); 1275 } 1276 1277 // A generic CAS; success or failure is in the EQ flag. 1278 // Clobbers rscratch1 1279 void cmpxchg(Register addr, Register expected, Register new_val, 1280 enum operand_size size, 1281 bool acquire, bool release, bool weak, 1282 Register result); 1283 1284 #ifdef ASSERT 1285 // Template short-hand support to clean-up after a failed call to trampoline 1286 // call generation (see trampoline_call() below), when a set of Labels must 1287 // be reset (before returning). 1288 template<typename Label, typename... More> 1289 void reset_labels(Label &lbl, More&... more) { 1290 lbl.reset(); reset_labels(more...); 1291 } 1292 template<typename Label> 1293 void reset_labels(Label &lbl) { 1294 lbl.reset(); 1295 } 1296 #endif 1297 1298 private: 1299 void compare_eq(Register rn, Register rm, enum operand_size size); 1300 1301 public: 1302 // AArch64 OpenJDK uses four different types of calls: 1303 // - direct call: bl pc_relative_offset 1304 // This is the shortest and the fastest, but the offset has the range: 1305 // +/-128MB for the release build, +/-2MB for the debug build. 1306 // 1307 // - far call: adrp reg, pc_relative_offset; add; bl reg 1308 // This is longer than a direct call. The offset has 1309 // the range +/-4GB. As the code cache size is limited to 4GB, 1310 // far calls can reach anywhere in the code cache. If a jump is 1311 // needed rather than a call, a far jump 'b reg' can be used instead. 1312 // All instructions are embedded at a call site. 1313 // 1314 // - trampoline call: 1315 // This is only available in C1/C2-generated code (nmethod). It is a combination 1316 // of a direct call, which is used if the destination of a call is in range, 1317 // and a register-indirect call. It has the advantages of reaching anywhere in 1318 // the AArch64 address space and being patchable at runtime when the generated 1319 // code is being executed by other threads. 1320 // 1321 // [Main code section] 1322 // bl trampoline 1323 // [Stub code section] 1324 // trampoline: 1325 // ldr reg, pc + 8 1326 // br reg 1327 // <64-bit destination address> 1328 // 1329 // If the destination is in range when the generated code is moved to the code 1330 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline 1331 // is not used. 1332 // The optimization does not remove the trampoline from the stub section. 1333 // This is necessary because the trampoline may well be redirected later when 1334 // code is patched, and the new destination may not be reachable by a simple BR 1335 // instruction. 1336 // 1337 // - indirect call: move reg, address; blr reg 1338 // This too can reach anywhere in the address space, but it cannot be 1339 // patched while code is running, so it must only be modified at a safepoint. 1340 // This form of call is most suitable for targets at fixed addresses, which 1341 // will never be patched. 1342 // 1343 // The patching we do conforms to the "Concurrent modification and 1344 // execution of instructions" section of the Arm Architectural 1345 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC, 1346 // or SVC instructions to be modified while another thread is 1347 // executing them. 1348 // 1349 // To patch a trampoline call when the BL can't reach, we first modify 1350 // the 64-bit destination address in the trampoline, then modify the 1351 // BL to point to the trampoline, then flush the instruction cache to 1352 // broadcast the change to all executing threads. See 1353 // NativeCall::set_destination_mt_safe for the details. 1354 // 1355 // There is a benign race in that the other thread might observe the 1356 // modified BL before it observes the modified 64-bit destination 1357 // address. That does not matter because the destination method has been 1358 // invalidated, so there will be a trap at its start. 1359 // For this to work, the destination address in the trampoline is 1360 // always updated, even if we're not using the trampoline. 1361 1362 // Emit a direct call if the entry address will always be in range, 1363 // otherwise a trampoline call. 1364 // Supported entry.rspec(): 1365 // - relocInfo::runtime_call_type 1366 // - relocInfo::opt_virtual_call_type 1367 // - relocInfo::static_call_type 1368 // - relocInfo::virtual_call_type 1369 // 1370 // Return: the call PC or null if CodeCache is full. 1371 // Clobbers: rscratch1 1372 address trampoline_call(Address entry); 1373 1374 static bool far_branches() { 1375 return ReservedCodeCacheSize > branch_range; 1376 } 1377 1378 // Check if branches to the non nmethod section require a far jump 1379 static bool codestub_branch_needs_far_jump() { 1380 return CodeCache::max_distance_to_non_nmethod() > branch_range; 1381 } 1382 1383 // Emit a direct call/jump if the entry address will always be in range, 1384 // otherwise a far call/jump. 1385 // The address must be inside the code cache. 1386 // Supported entry.rspec(): 1387 // - relocInfo::external_word_type 1388 // - relocInfo::runtime_call_type 1389 // - relocInfo::none 1390 // In the case of a far call/jump, the entry address is put in the tmp register. 1391 // The tmp register is invalidated. 1392 // 1393 // Far_jump returns the amount of the emitted code. 1394 void far_call(Address entry, Register tmp = rscratch1); 1395 int far_jump(Address entry, Register tmp = rscratch1); 1396 1397 static int far_codestub_branch_size() { 1398 if (codestub_branch_needs_far_jump()) { 1399 return 3 * 4; // adrp, add, br 1400 } else { 1401 return 4; 1402 } 1403 } 1404 1405 // Emit the CompiledIC call idiom 1406 address ic_call(address entry, jint method_index = 0); 1407 static int ic_check_size(); 1408 int ic_check(int end_alignment); 1409 1410 public: 1411 1412 // Data 1413 1414 void mov_metadata(Register dst, Metadata* obj); 1415 Address allocate_metadata_address(Metadata* obj); 1416 Address constant_oop_address(jobject obj); 1417 1418 void movoop(Register dst, jobject obj); 1419 1420 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic. 1421 void kernel_crc32(Register crc, Register buf, Register len, 1422 Register table0, Register table1, Register table2, Register table3, 1423 Register tmp, Register tmp2, Register tmp3); 1424 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic. 1425 void kernel_crc32c(Register crc, Register buf, Register len, 1426 Register table0, Register table1, Register table2, Register table3, 1427 Register tmp, Register tmp2, Register tmp3); 1428 1429 // Stack push and pop individual 64 bit registers 1430 void push(Register src); 1431 void pop(Register dst); 1432 1433 void repne_scan(Register addr, Register value, Register count, 1434 Register scratch); 1435 void repne_scanw(Register addr, Register value, Register count, 1436 Register scratch); 1437 1438 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm); 1439 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift); 1440 1441 // If a constant does not fit in an immediate field, generate some 1442 // number of MOV instructions and then perform the operation 1443 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm, 1444 add_sub_imm_insn insn1, 1445 add_sub_reg_insn insn2, bool is32); 1446 // Separate vsn which sets the flags 1447 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm, 1448 add_sub_imm_insn insn1, 1449 add_sub_reg_insn insn2, bool is32); 1450 1451 #define WRAP(INSN, is32) \ 1452 void INSN(Register Rd, Register Rn, uint64_t imm) { \ 1453 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \ 1454 } \ 1455 \ 1456 void INSN(Register Rd, Register Rn, Register Rm, \ 1457 enum shift_kind kind, unsigned shift = 0) { \ 1458 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1459 } \ 1460 \ 1461 void INSN(Register Rd, Register Rn, Register Rm) { \ 1462 Assembler::INSN(Rd, Rn, Rm); \ 1463 } \ 1464 \ 1465 void INSN(Register Rd, Register Rn, Register Rm, \ 1466 ext::operation option, int amount = 0) { \ 1467 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1468 } 1469 1470 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true) 1471 1472 #undef WRAP 1473 #define WRAP(INSN, is32) \ 1474 void INSN(Register Rd, Register Rn, uint64_t imm) { \ 1475 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \ 1476 } \ 1477 \ 1478 void INSN(Register Rd, Register Rn, Register Rm, \ 1479 enum shift_kind kind, unsigned shift = 0) { \ 1480 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1481 } \ 1482 \ 1483 void INSN(Register Rd, Register Rn, Register Rm) { \ 1484 Assembler::INSN(Rd, Rn, Rm); \ 1485 } \ 1486 \ 1487 void INSN(Register Rd, Register Rn, Register Rm, \ 1488 ext::operation option, int amount = 0) { \ 1489 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1490 } 1491 1492 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true) 1493 1494 void add(Register Rd, Register Rn, RegisterOrConstant increment); 1495 void addw(Register Rd, Register Rn, RegisterOrConstant increment); 1496 void sub(Register Rd, Register Rn, RegisterOrConstant decrement); 1497 void subw(Register Rd, Register Rn, RegisterOrConstant decrement); 1498 1499 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset); 1500 1501 void verified_entry(Compile* C, int sp_inc); 1502 1503 // Inline type specific methods 1504 #include "asm/macroAssembler_common.hpp" 1505 1506 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true); 1507 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]); 1508 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, 1509 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index, 1510 RegState reg_state[]); 1511 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index, 1512 VMRegPair* from, int from_count, int& from_index, VMReg to, 1513 RegState reg_state[], Register val_array); 1514 int extend_stack_for_inline_args(int args_on_stack); 1515 void remove_frame(int initial_framesize, bool needs_stack_repair); 1516 VMReg spill_reg_for(VMReg reg); 1517 void save_stack_increment(int sp_inc, int frame_size); 1518 1519 void tableswitch(Register index, jint lowbound, jint highbound, 1520 Label &jumptable, Label &jumptable_end, int stride = 1) { 1521 adr(rscratch1, jumptable); 1522 subsw(rscratch2, index, lowbound); 1523 subsw(zr, rscratch2, highbound - lowbound); 1524 br(Assembler::HS, jumptable_end); 1525 add(rscratch1, rscratch1, rscratch2, 1526 ext::sxtw, exact_log2(stride * Assembler::instruction_size)); 1527 br(rscratch1); 1528 } 1529 1530 // Form an address from base + offset in Rd. Rd may or may not 1531 // actually be used: you must use the Address that is returned. It 1532 // is up to you to ensure that the shift provided matches the size 1533 // of your data. 1534 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift); 1535 1536 // Return true iff an address is within the 48-bit AArch64 address 1537 // space. 1538 bool is_valid_AArch64_address(address a) { 1539 return ((uint64_t)a >> 48) == 0; 1540 } 1541 1542 // Load the base of the cardtable byte map into reg. 1543 void load_byte_map_base(Register reg); 1544 1545 // Prolog generator routines to support switch between x86 code and 1546 // generated ARM code 1547 1548 // routine to generate an x86 prolog for a stub function which 1549 // bootstraps into the generated ARM code which directly follows the 1550 // stub 1551 // 1552 1553 public: 1554 1555 void ldr_constant(Register dest, const Address &const_addr) { 1556 if (NearCpool) { 1557 ldr(dest, const_addr); 1558 } else { 1559 uint64_t offset; 1560 adrp(dest, InternalAddress(const_addr.target()), offset); 1561 ldr(dest, Address(dest, offset)); 1562 } 1563 } 1564 1565 address read_polling_page(Register r, relocInfo::relocType rtype); 1566 void get_polling_page(Register dest, relocInfo::relocType rtype); 1567 1568 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic. 1569 void update_byte_crc32(Register crc, Register val, Register table); 1570 void update_word_crc32(Register crc, Register v, Register tmp, 1571 Register table0, Register table1, Register table2, Register table3, 1572 bool upper = false); 1573 1574 address count_positives(Register ary1, Register len, Register result); 1575 1576 address arrays_equals(Register a1, Register a2, Register result, Register cnt1, 1577 Register tmp1, Register tmp2, Register tmp3, int elem_size); 1578 1579 // Ensure that the inline code and the stub use the same registers. 1580 #define ARRAYS_HASHCODE_REGISTERS \ 1581 do { \ 1582 assert(result == r0 && \ 1583 ary == r1 && \ 1584 cnt == r2 && \ 1585 vdata0 == v3 && \ 1586 vdata1 == v2 && \ 1587 vdata2 == v1 && \ 1588 vdata3 == v0 && \ 1589 vmul0 == v4 && \ 1590 vmul1 == v5 && \ 1591 vmul2 == v6 && \ 1592 vmul3 == v7 && \ 1593 vpow == v12 && \ 1594 vpowm == v13, "registers must match aarch64.ad"); \ 1595 } while (0) 1596 1597 void string_equals(Register a1, Register a2, Register result, Register cnt1); 1598 1599 void fill_words(Register base, Register cnt, Register value); 1600 void fill_words(Register base, uint64_t cnt, Register value); 1601 1602 address zero_words(Register base, uint64_t cnt); 1603 address zero_words(Register ptr, Register cnt); 1604 void zero_dcache_blocks(Register base, Register cnt); 1605 1606 static const int zero_words_block_size; 1607 1608 address byte_array_inflate(Register src, Register dst, Register len, 1609 FloatRegister vtmp1, FloatRegister vtmp2, 1610 FloatRegister vtmp3, Register tmp4); 1611 1612 void char_array_compress(Register src, Register dst, Register len, 1613 Register res, 1614 FloatRegister vtmp0, FloatRegister vtmp1, 1615 FloatRegister vtmp2, FloatRegister vtmp3, 1616 FloatRegister vtmp4, FloatRegister vtmp5); 1617 1618 void encode_iso_array(Register src, Register dst, 1619 Register len, Register res, bool ascii, 1620 FloatRegister vtmp0, FloatRegister vtmp1, 1621 FloatRegister vtmp2, FloatRegister vtmp3, 1622 FloatRegister vtmp4, FloatRegister vtmp5); 1623 1624 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi, 1625 address pio2, address dsin_coef, address dcos_coef); 1626 private: 1627 // begin trigonometric functions support block 1628 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2); 1629 void generate__kernel_rem_pio2(address two_over_pi, address pio2); 1630 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef); 1631 void generate_kernel_cos(FloatRegister x, address dcos_coef); 1632 // end trigonometric functions support block 1633 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 1634 Register src1, Register src2); 1635 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 1636 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2); 1637 } 1638 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 1639 Register y, Register y_idx, Register z, 1640 Register carry, Register product, 1641 Register idx, Register kdx); 1642 void multiply_128_x_128_loop(Register y, Register z, 1643 Register carry, Register carry2, 1644 Register idx, Register jdx, 1645 Register yz_idx1, Register yz_idx2, 1646 Register tmp, Register tmp3, Register tmp4, 1647 Register tmp7, Register product_hi); 1648 void kernel_crc32_using_crypto_pmull(Register crc, Register buf, 1649 Register len, Register tmp0, Register tmp1, Register tmp2, 1650 Register tmp3); 1651 void kernel_crc32_using_crc32(Register crc, Register buf, 1652 Register len, Register tmp0, Register tmp1, Register tmp2, 1653 Register tmp3); 1654 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf, 1655 Register len, Register tmp0, Register tmp1, Register tmp2, 1656 Register tmp3); 1657 void kernel_crc32c_using_crc32c(Register crc, Register buf, 1658 Register len, Register tmp0, Register tmp1, Register tmp2, 1659 Register tmp3); 1660 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf, 1661 Register len, Register tmp0, Register tmp1, Register tmp2, 1662 size_t table_offset); 1663 1664 void ghash_modmul (FloatRegister result, 1665 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b, 1666 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p, 1667 FloatRegister t1, FloatRegister t2, FloatRegister t3); 1668 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state); 1669 public: 1670 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, 1671 Register tmp0, Register tmp1, Register tmp2, Register tmp3, 1672 Register tmp4, Register tmp5, Register tmp6, Register tmp7); 1673 void mul_add(Register out, Register in, Register offs, Register len, Register k); 1674 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi, 1675 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0, 1676 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3); 1677 void ghash_multiply_wide(int index, 1678 FloatRegister result_lo, FloatRegister result_hi, 1679 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0, 1680 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3); 1681 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi, 1682 FloatRegister p, FloatRegister z, FloatRegister t1); 1683 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi, 1684 FloatRegister p, FloatRegister z, FloatRegister t1); 1685 void ghash_processBlocks_wide(address p, Register state, Register subkeyH, 1686 Register data, Register blocks, int unrolls); 1687 1688 1689 void aesenc_loadkeys(Register key, Register keylen); 1690 void aesecb_encrypt(Register from, Register to, Register keylen, 1691 FloatRegister data = v0, int unrolls = 1); 1692 void aesecb_decrypt(Register from, Register to, Register key, Register keylen); 1693 void aes_round(FloatRegister input, FloatRegister subkey); 1694 1695 // ChaCha20 functions support block 1696 void cc20_quarter_round(FloatRegister aVec, FloatRegister bVec, 1697 FloatRegister cVec, FloatRegister dVec, FloatRegister scratch, 1698 FloatRegister tbl); 1699 void cc20_shift_lane_org(FloatRegister bVec, FloatRegister cVec, 1700 FloatRegister dVec, bool colToDiag); 1701 1702 // Place an ISB after code may have been modified due to a safepoint. 1703 void safepoint_isb(); 1704 1705 private: 1706 // Return the effective address r + (r1 << ext) + offset. 1707 // Uses rscratch2. 1708 Address offsetted_address(Register r, Register r1, Address::extend ext, 1709 int offset, int size); 1710 1711 private: 1712 // Returns an address on the stack which is reachable with a ldr/str of size 1713 // Uses rscratch2 if the address is not directly reachable 1714 Address spill_address(int size, int offset, Register tmp=rscratch2); 1715 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2); 1716 1717 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const; 1718 1719 // Check whether two loads/stores can be merged into ldp/stp. 1720 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const; 1721 1722 // Merge current load/store with previous load/store into ldp/stp. 1723 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store); 1724 1725 // Try to merge two loads/stores into ldp/stp. If success, returns true else false. 1726 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store); 1727 1728 public: 1729 void spill(Register Rx, bool is64, int offset) { 1730 if (is64) { 1731 str(Rx, spill_address(8, offset)); 1732 } else { 1733 strw(Rx, spill_address(4, offset)); 1734 } 1735 } 1736 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) { 1737 str(Vx, T, spill_address(1 << (int)T, offset)); 1738 } 1739 1740 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) { 1741 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset)); 1742 } 1743 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) { 1744 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset)); 1745 } 1746 1747 void unspill(Register Rx, bool is64, int offset) { 1748 if (is64) { 1749 ldr(Rx, spill_address(8, offset)); 1750 } else { 1751 ldrw(Rx, spill_address(4, offset)); 1752 } 1753 } 1754 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) { 1755 ldr(Vx, T, spill_address(1 << (int)T, offset)); 1756 } 1757 1758 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) { 1759 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset)); 1760 } 1761 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) { 1762 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset)); 1763 } 1764 1765 void spill_copy128(int src_offset, int dst_offset, 1766 Register tmp1=rscratch1, Register tmp2=rscratch2) { 1767 if (src_offset < 512 && (src_offset & 7) == 0 && 1768 dst_offset < 512 && (dst_offset & 7) == 0) { 1769 ldp(tmp1, tmp2, Address(sp, src_offset)); 1770 stp(tmp1, tmp2, Address(sp, dst_offset)); 1771 } else { 1772 unspill(tmp1, true, src_offset); 1773 spill(tmp1, true, dst_offset); 1774 unspill(tmp1, true, src_offset+8); 1775 spill(tmp1, true, dst_offset+8); 1776 } 1777 } 1778 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset, 1779 int sve_vec_reg_size_in_bytes) { 1780 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size"); 1781 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) { 1782 spill_copy128(src_offset, dst_offset); 1783 src_offset += 16; 1784 dst_offset += 16; 1785 } 1786 } 1787 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset, 1788 int sve_predicate_reg_size_in_bytes) { 1789 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset)); 1790 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset)); 1791 reinitialize_ptrue(); 1792 } 1793 void cache_wb(Address line); 1794 void cache_wbsync(bool is_pre); 1795 1796 // Code for java.lang.Thread::onSpinWait() intrinsic. 1797 void spin_wait(); 1798 1799 void lightweight_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow); 1800 void lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow); 1801 1802 private: 1803 // Check the current thread doesn't need a cross modify fence. 1804 void verify_cross_modify_fence_not_required() PRODUCT_RETURN; 1805 1806 }; 1807 1808 #ifdef ASSERT 1809 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } 1810 #endif 1811 1812 struct tableswitch { 1813 Register _reg; 1814 int _insn_index; jint _first_key; jint _last_key; 1815 Label _after; 1816 Label _branches; 1817 }; 1818 1819 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP