1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/macros.hpp"
37 #include "utilities/powerOfTwo.hpp"
38 #include "runtime/signature.hpp"
39
40
41 class ciInlineKlass;
42
43 class OopMap;
44
45 // MacroAssembler extends Assembler by frequently used macros.
46 //
47 // Instructions for which a 'better' code sequence exists depending
48 // on arguments should also go in here.
49
50 class MacroAssembler: public Assembler {
51 friend class LIR_Assembler;
52
53 public:
54 using Assembler::mov;
55 using Assembler::movi;
56
57 protected:
58
59 // Support for VM calls
60 //
61 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
62 // may customize this version by overriding it for its purposes (e.g., to save/restore
63 // additional registers when doing a VM call).
64 virtual void call_VM_leaf_base(
65 address entry_point, // the entry point
66 int number_of_arguments, // the number of arguments to pop after the call
67 Label *retaddr = nullptr
68 );
69
70 virtual void call_VM_leaf_base(
71 address entry_point, // the entry point
72 int number_of_arguments, // the number of arguments to pop after the call
73 Label &retaddr) {
74 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
75 }
76
77 // This is the base routine called by the different versions of call_VM. The interpreter
78 // may customize this version by overriding it for its purposes (e.g., to save/restore
79 // additional registers when doing a VM call).
80 //
81 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
82 // returns the register which contains the thread upon return. If a thread register has been
83 // specified, the return value will correspond to that register. If no last_java_sp is specified
84 // (noreg) than rsp will be used instead.
85 virtual void call_VM_base( // returns the register containing the thread upon return
86 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
87 Register java_thread, // the thread if computed before ; use noreg otherwise
88 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
89 Label* return_pc, // to set up last_Java_frame; use nullptr otherwise
90 address entry_point, // the entry point
91 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
92 bool check_exceptions // whether to check for pending exceptions after return
93 );
94
95 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
96
97 enum KlassDecodeMode {
98 KlassDecodeNone,
99 KlassDecodeZero,
100 KlassDecodeXor,
101 KlassDecodeMovk
102 };
103
104 // Calculate decoding mode based on given parameters, used for checking then ultimately setting.
105 static KlassDecodeMode klass_decode_mode(address base, int shift, const size_t range);
106
107 private:
108 static KlassDecodeMode _klass_decode_mode;
109
110 // Returns above setting with asserts
111 static KlassDecodeMode klass_decode_mode();
112
113 public:
114 // Checks the decode mode and returns false if not compatible with preferred decoding mode.
115 static bool check_klass_decode_mode(address base, int shift, const size_t range);
116
117 // Sets the decode mode and returns false if cannot be set.
118 static bool set_klass_decode_mode(address base, int shift, const size_t range);
119
120 public:
121 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
122
123 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
124 // The implementation is only non-empty for the InterpreterMacroAssembler,
125 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
126 virtual void check_and_handle_popframe(Register java_thread);
127 virtual void check_and_handle_earlyret(Register java_thread);
128
129 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp = rscratch1);
130 void rt_call(address dest, Register tmp = rscratch1);
131
132 // Load Effective Address
133 void lea(Register r, const Address &a) {
134 InstructionMark im(this);
135 a.lea(this, r);
136 }
137
138 // Whether materializing the given address for a LDR/STR requires an
139 // additional lea instruction.
140 static bool legitimize_address_requires_lea(const Address &a, int size) {
141 return a.getMode() == Address::base_plus_offset &&
142 !Address::offset_ok_for_immed(a.offset(), exact_log2(size));
143 }
144
145 /* Sometimes we get misaligned loads and stores, usually from Unsafe
146 accesses, and these can exceed the offset range. */
147 Address legitimize_address(const Address &a, int size, Register scratch) {
148 if (legitimize_address_requires_lea(a, size)) {
149 block_comment("legitimize_address {");
150 lea(scratch, a);
151 block_comment("} legitimize_address");
152 return Address(scratch);
153 }
154 return a;
155 }
156
157 void addmw(Address a, Register incr, Register scratch) {
158 ldrw(scratch, a);
159 addw(scratch, scratch, incr);
160 strw(scratch, a);
161 }
162
163 // Add constant to memory word
164 void addmw(Address a, int imm, Register scratch) {
165 ldrw(scratch, a);
166 if (imm > 0)
167 addw(scratch, scratch, (unsigned)imm);
168 else
169 subw(scratch, scratch, (unsigned)-imm);
170 strw(scratch, a);
171 }
172
173 void bind(Label& L) {
174 Assembler::bind(L);
175 code()->clear_last_insn();
176 code()->set_last_label(pc());
177 }
178
179 void membar(Membar_mask_bits order_constraint);
180
181 using Assembler::ldr;
182 using Assembler::str;
183 using Assembler::ldrw;
184 using Assembler::strw;
185
186 void ldr(Register Rx, const Address &adr);
187 void ldrw(Register Rw, const Address &adr);
188 void str(Register Rx, const Address &adr);
189 void strw(Register Rx, const Address &adr);
190
191 // Frame creation and destruction shared between JITs.
192 DEBUG_ONLY(void build_frame(int framesize);)
193 void build_frame(int framesize DEBUG_ONLY(COMMA bool zap_rfp_lr_spills));
194 void remove_frame(int framesize);
195
196 virtual void _call_Unimplemented(address call_site) {
197 mov(rscratch2, call_site);
198 }
199
200 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
201 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
202 // https://reviews.llvm.org/D3311
203
204 #ifdef _WIN64
205 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
206 #else
207 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
208 #endif
209
210 // aliases defined in AARCH64 spec
211
212 template<class T>
213 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
214
215 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
216 inline void cmp(Register Rd, unsigned imm) = delete;
217
218 template<class T>
219 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
220
221 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
222 inline void cmn(Register Rd, unsigned imm) = delete;
223
224 void cset(Register Rd, Assembler::Condition cond) {
225 csinc(Rd, zr, zr, ~cond);
226 }
227 void csetw(Register Rd, Assembler::Condition cond) {
228 csincw(Rd, zr, zr, ~cond);
229 }
230
231 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
232 csneg(Rd, Rn, Rn, ~cond);
233 }
234 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
235 csnegw(Rd, Rn, Rn, ~cond);
236 }
237
238 inline void movw(Register Rd, Register Rn) {
239 if (Rd == sp || Rn == sp) {
240 Assembler::addw(Rd, Rn, 0U);
241 } else {
242 orrw(Rd, zr, Rn);
243 }
244 }
245 inline void mov(Register Rd, Register Rn) {
246 assert(Rd != r31_sp && Rn != r31_sp, "should be");
247 if (Rd == Rn) {
248 } else if (Rd == sp || Rn == sp) {
249 Assembler::add(Rd, Rn, 0U);
250 } else {
251 orr(Rd, zr, Rn);
252 }
253 }
254
255 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
256 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
257
258 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
259 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
260
261 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
262 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
263
264 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
265 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
266 }
267 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
268 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
269 }
270
271 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
272 bfmw(Rd, Rn, lsb, (lsb + width - 1));
273 }
274 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
275 bfm(Rd, Rn, lsb , (lsb + width - 1));
276 }
277
278 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
279 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
280 }
281 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
282 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
283 }
284
285 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
286 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
287 }
288 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
289 sbfm(Rd, Rn, lsb , (lsb + width - 1));
290 }
291
292 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
293 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
294 }
295 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
296 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
297 }
298
299 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
300 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
301 }
302 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
303 ubfm(Rd, Rn, lsb , (lsb + width - 1));
304 }
305
306 inline void asrw(Register Rd, Register Rn, unsigned imm) {
307 sbfmw(Rd, Rn, imm, 31);
308 }
309
310 inline void asr(Register Rd, Register Rn, unsigned imm) {
311 sbfm(Rd, Rn, imm, 63);
312 }
313
314 inline void lslw(Register Rd, Register Rn, unsigned imm) {
315 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
316 }
317
318 inline void lsl(Register Rd, Register Rn, unsigned imm) {
319 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
320 }
321
322 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
323 ubfmw(Rd, Rn, imm, 31);
324 }
325
326 inline void lsr(Register Rd, Register Rn, unsigned imm) {
327 ubfm(Rd, Rn, imm, 63);
328 }
329
330 inline void rorw(Register Rd, Register Rn, unsigned imm) {
331 extrw(Rd, Rn, Rn, imm);
332 }
333
334 inline void ror(Register Rd, Register Rn, unsigned imm) {
335 extr(Rd, Rn, Rn, imm);
336 }
337
338 inline void rolw(Register Rd, Register Rn, unsigned imm) {
339 extrw(Rd, Rn, Rn, (32 - imm));
340 }
341
342 inline void rol(Register Rd, Register Rn, unsigned imm) {
343 extr(Rd, Rn, Rn, (64 - imm));
344 }
345
346 using Assembler::rax1;
347 using Assembler::eor3;
348
349 inline void rax1(Register Rd, Register Rn, Register Rm) {
350 eor(Rd, Rn, Rm, ROR, 63); // Rd = Rn ^ rol(Rm, 1)
351 }
352
353 inline void eor3(Register Rd, Register Rn, Register Rm, Register Rk) {
354 assert(Rd != Rn, "Use tmp register");
355 eor(Rd, Rm, Rk);
356 eor(Rd, Rd, Rn);
357 }
358
359 inline void sxtbw(Register Rd, Register Rn) {
360 sbfmw(Rd, Rn, 0, 7);
361 }
362 inline void sxthw(Register Rd, Register Rn) {
363 sbfmw(Rd, Rn, 0, 15);
364 }
365 inline void sxtb(Register Rd, Register Rn) {
366 sbfm(Rd, Rn, 0, 7);
367 }
368 inline void sxth(Register Rd, Register Rn) {
369 sbfm(Rd, Rn, 0, 15);
370 }
371 inline void sxtw(Register Rd, Register Rn) {
372 sbfm(Rd, Rn, 0, 31);
373 }
374
375 inline void uxtbw(Register Rd, Register Rn) {
376 ubfmw(Rd, Rn, 0, 7);
377 }
378 inline void uxthw(Register Rd, Register Rn) {
379 ubfmw(Rd, Rn, 0, 15);
380 }
381 inline void uxtb(Register Rd, Register Rn) {
382 ubfm(Rd, Rn, 0, 7);
383 }
384 inline void uxth(Register Rd, Register Rn) {
385 ubfm(Rd, Rn, 0, 15);
386 }
387 inline void uxtw(Register Rd, Register Rn) {
388 ubfm(Rd, Rn, 0, 31);
389 }
390
391 inline void cmnw(Register Rn, Register Rm) {
392 addsw(zr, Rn, Rm);
393 }
394 inline void cmn(Register Rn, Register Rm) {
395 adds(zr, Rn, Rm);
396 }
397
398 inline void cmpw(Register Rn, Register Rm) {
399 subsw(zr, Rn, Rm);
400 }
401 inline void cmp(Register Rn, Register Rm) {
402 subs(zr, Rn, Rm);
403 }
404
405 inline void negw(Register Rd, Register Rn) {
406 subw(Rd, zr, Rn);
407 }
408
409 inline void neg(Register Rd, Register Rn) {
410 sub(Rd, zr, Rn);
411 }
412
413 inline void negsw(Register Rd, Register Rn) {
414 subsw(Rd, zr, Rn);
415 }
416
417 inline void negs(Register Rd, Register Rn) {
418 subs(Rd, zr, Rn);
419 }
420
421 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
422 addsw(zr, Rn, Rm, kind, shift);
423 }
424 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
425 adds(zr, Rn, Rm, kind, shift);
426 }
427
428 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
429 subsw(zr, Rn, Rm, kind, shift);
430 }
431 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
432 subs(zr, Rn, Rm, kind, shift);
433 }
434
435 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
436 subw(Rd, zr, Rn, kind, shift);
437 }
438
439 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
440 sub(Rd, zr, Rn, kind, shift);
441 }
442
443 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
444 subsw(Rd, zr, Rn, kind, shift);
445 }
446
447 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
448 subs(Rd, zr, Rn, kind, shift);
449 }
450
451 inline void mnegw(Register Rd, Register Rn, Register Rm) {
452 msubw(Rd, Rn, Rm, zr);
453 }
454 inline void mneg(Register Rd, Register Rn, Register Rm) {
455 msub(Rd, Rn, Rm, zr);
456 }
457
458 inline void mulw(Register Rd, Register Rn, Register Rm) {
459 maddw(Rd, Rn, Rm, zr);
460 }
461 inline void mul(Register Rd, Register Rn, Register Rm) {
462 madd(Rd, Rn, Rm, zr);
463 }
464
465 inline void smnegl(Register Rd, Register Rn, Register Rm) {
466 smsubl(Rd, Rn, Rm, zr);
467 }
468 inline void smull(Register Rd, Register Rn, Register Rm) {
469 smaddl(Rd, Rn, Rm, zr);
470 }
471
472 inline void umnegl(Register Rd, Register Rn, Register Rm) {
473 umsubl(Rd, Rn, Rm, zr);
474 }
475 inline void umull(Register Rd, Register Rn, Register Rm) {
476 umaddl(Rd, Rn, Rm, zr);
477 }
478
479 #define WRAP(INSN) \
480 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
481 if (VM_Version::supports_a53mac() && Ra != zr) \
482 nop(); \
483 Assembler::INSN(Rd, Rn, Rm, Ra); \
484 }
485
486 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
487 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
488 #undef WRAP
489
490
491 // macro assembly operations needed for aarch64
492
493 public:
494
495 enum FpPushPopMode {
496 PushPopFull,
497 PushPopSVE,
498 PushPopNeon,
499 PushPopFp
500 };
501
502 // first two private routines for loading 32 bit or 64 bit constants
503 private:
504
505 void mov_immediate64(Register dst, uint64_t imm64);
506 void mov_immediate32(Register dst, uint32_t imm32);
507
508 int push(unsigned int bitset, Register stack);
509 int pop(unsigned int bitset, Register stack);
510
511 int push_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
512 int pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
513
514 int push_p(unsigned int bitset, Register stack);
515 int pop_p(unsigned int bitset, Register stack);
516
517 void mov(Register dst, Address a);
518
519 public:
520
521 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
522 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
523
524 void push_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) push_fp(regs.bits(), stack, mode); }
525 void pop_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) pop_fp(regs.bits(), stack, mode); }
526
527 static RegSet call_clobbered_gp_registers();
528
529 void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
530 void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
531
532 // Push and pop everything that might be clobbered by a native
533 // runtime call except rscratch1 and rscratch2. (They are always
534 // scratch, so we don't have to protect them.) Only save the lower
535 // 64 bits of each vector register. Additional registers can be excluded
536 // in a passed RegSet.
537 void push_call_clobbered_registers_except(RegSet exclude);
538 void pop_call_clobbered_registers_except(RegSet exclude);
539
540 void push_call_clobbered_registers() {
541 push_call_clobbered_registers_except(RegSet());
542 }
543 void pop_call_clobbered_registers() {
544 pop_call_clobbered_registers_except(RegSet());
545 }
546
547
548 // now mov instructions for loading absolute addresses and 32 or
549 // 64 bit integers
550
551 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
552
553 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
554 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
555
556 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
557
558 void mov(Register dst, RegisterOrConstant src) {
559 if (src.is_register())
560 mov(dst, src.as_register());
561 else
562 mov(dst, src.as_constant());
563 }
564
565 void movptr(Register r, uintptr_t imm64);
566
567 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
568
569 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
570 orr(Vd, T, Vn, Vn);
571 }
572
573 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
574 fcvtsh(tmp, src);
575 smov(dst, tmp, H, 0);
576 }
577
578 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
579 mov(tmp, H, 0, src);
580 fcvths(dst, tmp);
581 }
582
583 // Generalized Test Bit And Branch, including a "far" variety which
584 // spans more than 32KiB.
585 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
586 assert(cond == EQ || cond == NE, "must be");
587
588 if (isfar)
589 cond = ~cond;
590
591 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
592 if (cond == Assembler::EQ)
593 branch = &Assembler::tbz;
594 else
595 branch = &Assembler::tbnz;
596
597 if (isfar) {
598 Label L;
599 (this->*branch)(Rt, bitpos, L);
600 b(dest);
601 bind(L);
602 } else {
603 (this->*branch)(Rt, bitpos, dest);
604 }
605 }
606
607 // macro instructions for accessing and updating floating point
608 // status register
609 //
610 // FPSR : op1 == 011
611 // CRn == 0100
612 // CRm == 0100
613 // op2 == 001
614
615 inline void get_fpsr(Register reg)
616 {
617 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
618 }
619
620 inline void set_fpsr(Register reg)
621 {
622 msr(0b011, 0b0100, 0b0100, 0b001, reg);
623 }
624
625 inline void clear_fpsr()
626 {
627 msr(0b011, 0b0100, 0b0100, 0b001, zr);
628 }
629
630 // FPCR : op1 == 011
631 // CRn == 0100
632 // CRm == 0100
633 // op2 == 000
634
635 inline void get_fpcr(Register reg) {
636 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
637 }
638
639 inline void set_fpcr(Register reg) {
640 msr(0b011, 0b0100, 0b0100, 0b000, reg);
641 }
642
643 // DCZID_EL0: op1 == 011
644 // CRn == 0000
645 // CRm == 0000
646 // op2 == 111
647 inline void get_dczid_el0(Register reg)
648 {
649 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
650 }
651
652 // CTR_EL0: op1 == 011
653 // CRn == 0000
654 // CRm == 0000
655 // op2 == 001
656 inline void get_ctr_el0(Register reg)
657 {
658 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
659 }
660
661 inline void get_nzcv(Register reg) {
662 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
663 }
664
665 inline void set_nzcv(Register reg) {
666 msr(0b011, 0b0100, 0b0010, 0b000, reg);
667 }
668
669 // idiv variant which deals with MINLONG as dividend and -1 as divisor
670 int corrected_idivl(Register result, Register ra, Register rb,
671 bool want_remainder, Register tmp = rscratch1);
672 int corrected_idivq(Register result, Register ra, Register rb,
673 bool want_remainder, Register tmp = rscratch1);
674
675 // Support for null-checks
676 //
677 // Generates code that causes a null OS exception if the content of reg is null.
678 // If the accessed location is M[reg + offset] and the offset is known, provide the
679 // offset. No explicit code generation is needed if the offset is within a certain
680 // range (0 <= offset <= page_size).
681
682 virtual void null_check(Register reg, int offset = -1);
683 static bool needs_explicit_null_check(intptr_t offset);
684 static bool uses_implicit_null_check(void* address);
685
686 // markWord tests, kills markWord reg
687 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
688
689 // inlineKlass queries, kills temp_reg
690 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
691
692 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
693 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
694 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
695 void test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker);
696
697 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
698 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
699 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
700 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
701 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
702 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
703
704 // Check array klass layout helper for flat or null-free arrays...
705 void test_flat_array_layout(Register lh, Label& is_flat_array);
706 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array);
707
708 static address target_addr_for_insn(address insn_addr);
709 static address target_addr_for_insn_or_null(address insn_addr);
710
711 // Required platform-specific helpers for Label::patch_instructions.
712 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
713 static int pd_patch_instruction_size(address branch, address target);
714 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
715 pd_patch_instruction_size(branch, target);
716 }
717 static address pd_call_destination(address branch) {
718 return target_addr_for_insn(branch);
719 }
720 #ifndef PRODUCT
721 static void pd_print_patched_instruction(address branch);
722 #endif
723
724 static int patch_oop(address insn_addr, address o);
725 static int patch_narrow_klass(address insn_addr, narrowKlass n);
726
727 // Return whether code is emitted to a scratch blob.
728 virtual bool in_scratch_emit_size() {
729 return false;
730 }
731 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
732 static int max_trampoline_stub_size();
733 void emit_static_call_stub();
734 static int static_call_stub_size();
735
736 // The following 4 methods return the offset of the appropriate move instruction
737
738 // Support for fast byte/short loading with zero extension (depending on particular CPU)
739 int load_unsigned_byte(Register dst, Address src);
740 int load_unsigned_short(Register dst, Address src);
741
742 // Support for fast byte/short loading with sign extension (depending on particular CPU)
743 int load_signed_byte(Register dst, Address src);
744 int load_signed_short(Register dst, Address src);
745
746 int load_signed_byte32(Register dst, Address src);
747 int load_signed_short32(Register dst, Address src);
748
749 // Support for sign-extension (hi:lo = extend_sign(lo))
750 void extend_sign(Register hi, Register lo);
751
752 // Load and store values by size and signed-ness
753 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
754 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
755
756 // Support for inc/dec with optimal instruction selection depending on value
757
758 // x86_64 aliases an unqualified register/address increment and
759 // decrement to call incrementq and decrementq but also supports
760 // explicitly sized calls to incrementq/decrementq or
761 // incrementl/decrementl
762
763 // for aarch64 the proper convention would be to use
764 // increment/decrement for 64 bit operations and
765 // incrementw/decrementw for 32 bit operations. so when porting
766 // x86_64 code we can leave calls to increment/decrement as is,
767 // replace incrementq/decrementq with increment/decrement and
768 // replace incrementl/decrementl with incrementw/decrementw.
769
770 // n.b. increment/decrement calls with an Address destination will
771 // need to use a scratch register to load the value to be
772 // incremented. increment/decrement calls which add or subtract a
773 // constant value greater than 2^12 will need to use a 2nd scratch
774 // register to hold the constant. so, a register increment/decrement
775 // may trash rscratch2 and an address increment/decrement trash
776 // rscratch and rscratch2
777
778 void decrementw(Address dst, int value = 1);
779 void decrementw(Register reg, int value = 1);
780
781 void decrement(Register reg, int value = 1);
782 void decrement(Address dst, int value = 1);
783
784 void incrementw(Address dst, int value = 1);
785 void incrementw(Register reg, int value = 1);
786
787 void increment(Register reg, int value = 1);
788 void increment(Address dst, int value = 1);
789
790
791 // Alignment
792 void align(int modulus);
793 void align(int modulus, int target);
794
795 // nop
796 void post_call_nop();
797
798 // Stack frame creation/removal
799 void enter(bool strip_ret_addr = false);
800 void leave();
801
802 // ROP Protection
803 void protect_return_address();
804 void protect_return_address(Register return_reg);
805 void authenticate_return_address();
806 void authenticate_return_address(Register return_reg);
807 void strip_return_address();
808 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
809
810 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
811 // The pointer will be loaded into the thread register.
812 void get_thread(Register thread);
813
814 // support for argument shuffling
815 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
816 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
817 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
818 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
819 void object_move(
820 OopMap* map,
821 int oop_handle_offset,
822 int framesize_in_slots,
823 VMRegPair src,
824 VMRegPair dst,
825 bool is_receiver,
826 int* receiver_offset);
827
828
829 // Support for VM calls
830 //
831 // It is imperative that all calls into the VM are handled via the call_VM macros.
832 // They make sure that the stack linkage is setup correctly. call_VM's correspond
833 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
834
835
836 void call_VM(Register oop_result,
837 address entry_point,
838 bool check_exceptions = true);
839 void call_VM(Register oop_result,
840 address entry_point,
841 Register arg_1,
842 bool check_exceptions = true);
843 void call_VM(Register oop_result,
844 address entry_point,
845 Register arg_1, Register arg_2,
846 bool check_exceptions = true);
847 void call_VM(Register oop_result,
848 address entry_point,
849 Register arg_1, Register arg_2, Register arg_3,
850 bool check_exceptions = true);
851
852 // Overloadings with last_Java_sp
853 void call_VM(Register oop_result,
854 Register last_java_sp,
855 address entry_point,
856 int number_of_arguments = 0,
857 bool check_exceptions = true);
858 void call_VM(Register oop_result,
859 Register last_java_sp,
860 address entry_point,
861 Register arg_1, bool
862 check_exceptions = true);
863 void call_VM(Register oop_result,
864 Register last_java_sp,
865 address entry_point,
866 Register arg_1, Register arg_2,
867 bool check_exceptions = true);
868 void call_VM(Register oop_result,
869 Register last_java_sp,
870 address entry_point,
871 Register arg_1, Register arg_2, Register arg_3,
872 bool check_exceptions = true);
873
874 void get_vm_result_oop(Register oop_result, Register thread);
875 void get_vm_result_metadata(Register metadata_result, Register thread);
876
877 // These always tightly bind to MacroAssembler::call_VM_base
878 // bypassing the virtual implementation
879 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
880 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
881 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
882 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
883 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
884
885 void call_VM_leaf(address entry_point,
886 int number_of_arguments = 0);
887 void call_VM_leaf(address entry_point,
888 Register arg_1);
889 void call_VM_leaf(address entry_point,
890 Register arg_1, Register arg_2);
891 void call_VM_leaf(address entry_point,
892 Register arg_1, Register arg_2, Register arg_3);
893
894 // These always tightly bind to MacroAssembler::call_VM_leaf_base
895 // bypassing the virtual implementation
896 void super_call_VM_leaf(address entry_point);
897 void super_call_VM_leaf(address entry_point, Register arg_1);
898 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
899 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
900 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
901
902 // last Java Frame (fills frame anchor)
903 void set_last_Java_frame(Register last_java_sp,
904 Register last_java_fp,
905 address last_java_pc,
906 Register scratch);
907
908 void set_last_Java_frame(Register last_java_sp,
909 Register last_java_fp,
910 Label &last_java_pc,
911 Register scratch);
912
913 void set_last_Java_frame(Register last_java_sp,
914 Register last_java_fp,
915 Register last_java_pc,
916 Register scratch);
917
918 void reset_last_Java_frame(Register thread);
919
920 // thread in the default location (rthread)
921 void reset_last_Java_frame(bool clear_fp);
922
923 // Stores
924 void store_check(Register obj); // store check for obj - register is destroyed afterwards
925 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
926
927 void resolve_jobject(Register value, Register tmp1, Register tmp2);
928 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
929
930 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
931 void c2bool(Register x);
932
933 void load_method_holder_cld(Register rresult, Register rmethod);
934 void load_method_holder(Register holder, Register method);
935
936 // oop manipulations
937 void load_metadata(Register dst, Register src);
938
939 void load_narrow_klass_compact(Register dst, Register src);
940 void load_klass(Register dst, Register src);
941 void store_klass(Register dst, Register src);
942 void cmp_klass(Register obj, Register klass, Register tmp);
943 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
944
945 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
946 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
947 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
948
949 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
950 Register tmp1, Register tmp2);
951
952 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
953 Register tmp1, Register tmp2, Register tmp3);
954
955 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
956
957 // inline type data payload offsets...
958 void payload_offset(Register inline_klass, Register offset);
959 void payload_address(Register oop, Register data, Register inline_klass);
960 // get data payload ptr a flat value array at index, kills rcx and index
961 void data_for_value_array_index(Register array, Register array_klass,
962 Register index, Register data);
963
964 void load_heap_oop(Register dst, Address src, Register tmp1,
965 Register tmp2, DecoratorSet decorators = 0);
966
967 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
968 Register tmp2, DecoratorSet decorators = 0);
969 void store_heap_oop(Address dst, Register val, Register tmp1,
970 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
971
972 // currently unimplemented
973 // Used for storing null. All other oop constants should be
974 // stored using routines that take a jobject.
975 void store_heap_oop_null(Address dst);
976
977 void load_prototype_header(Register dst, Register src);
978
979 void store_klass_gap(Register dst, Register src);
980
981 // This dummy is to prevent a call to store_heap_oop from
982 // converting a zero (like null) into a Register by giving
983 // the compiler two choices it can't resolve
984
985 void store_heap_oop(Address dst, void* dummy);
986
987 void encode_heap_oop(Register d, Register s);
988 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
989 void decode_heap_oop(Register d, Register s);
990 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
991 void encode_heap_oop_not_null(Register r);
992 void decode_heap_oop_not_null(Register r);
993 void encode_heap_oop_not_null(Register dst, Register src);
994 void decode_heap_oop_not_null(Register dst, Register src);
995
996 void set_narrow_oop(Register dst, jobject obj);
997
998 void decode_klass_not_null_for_aot(Register dst, Register src);
999 void encode_klass_not_null_for_aot(Register dst, Register src);
1000 void encode_klass_not_null(Register r);
1001 void decode_klass_not_null(Register r);
1002 void encode_klass_not_null(Register dst, Register src);
1003 void decode_klass_not_null(Register dst, Register src);
1004
1005 void set_narrow_klass(Register dst, Klass* k);
1006
1007 // if heap base register is used - reinit it with the correct value
1008 void reinit_heapbase();
1009
1010 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1011
1012 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
1013 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1014 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
1015 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1016
1017 void push_cont_fastpath(Register java_thread = rthread);
1018 void pop_cont_fastpath(Register java_thread = rthread);
1019
1020 // Round up to a power of two
1021 void round_to(Register reg, int modulus);
1022
1023 // java.lang.Math::round intrinsics
1024 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1025 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1026
1027 // allocation
1028
1029 // Object / value buffer allocation...
1030 // Allocate instance of klass, assumes klass initialized by caller
1031 // new_obj prefers to be rax
1032 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
1033 void allocate_instance(Register klass, Register new_obj,
1034 Register t1, Register t2,
1035 bool clear_fields, Label& alloc_failed);
1036
1037 void tlab_allocate(
1038 Register obj, // result: pointer to object after successful allocation
1039 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1040 int con_size_in_bytes, // object size in bytes if known at compile time
1041 Register t1, // temp register
1042 Register t2, // temp register
1043 Label& slow_case // continuation point if fast allocation fails
1044 );
1045 void verify_tlab();
1046
1047 // For field "index" within "klass", return inline_klass ...
1048 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
1049 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
1050
1051
1052 // interface method calling
1053 void lookup_interface_method(Register recv_klass,
1054 Register intf_klass,
1055 RegisterOrConstant itable_index,
1056 Register method_result,
1057 Register scan_temp,
1058 Label& no_such_interface,
1059 bool return_method = true);
1060
1061 void lookup_interface_method_stub(Register recv_klass,
1062 Register holder_klass,
1063 Register resolved_klass,
1064 Register method_result,
1065 Register temp_reg,
1066 Register temp_reg2,
1067 int itable_index,
1068 Label& L_no_such_interface);
1069
1070 // virtual method calling
1071 // n.b. x86 allows RegisterOrConstant for vtable_index
1072 void lookup_virtual_method(Register recv_klass,
1073 RegisterOrConstant vtable_index,
1074 Register method_result);
1075
1076 // Test sub_klass against super_klass, with fast and slow paths.
1077
1078 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1079 // One of the three labels can be null, meaning take the fall-through.
1080 // If super_check_offset is -1, the value is loaded up from super_klass.
1081 // No registers are killed, except temp_reg.
1082 void check_klass_subtype_fast_path(Register sub_klass,
1083 Register super_klass,
1084 Register temp_reg,
1085 Label* L_success,
1086 Label* L_failure,
1087 Label* L_slow_path,
1088 Register super_check_offset = noreg);
1089
1090 // The rest of the type check; must be wired to a corresponding fast path.
1091 // It does not repeat the fast path logic, so don't use it standalone.
1092 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1093 // Updates the sub's secondary super cache as necessary.
1094 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1095 void check_klass_subtype_slow_path(Register sub_klass,
1096 Register super_klass,
1097 Register temp_reg,
1098 Register temp2_reg,
1099 Label* L_success,
1100 Label* L_failure,
1101 bool set_cond_codes = false);
1102
1103 void check_klass_subtype_slow_path_linear(Register sub_klass,
1104 Register super_klass,
1105 Register temp_reg,
1106 Register temp2_reg,
1107 Label* L_success,
1108 Label* L_failure,
1109 bool set_cond_codes = false);
1110
1111 void check_klass_subtype_slow_path_table(Register sub_klass,
1112 Register super_klass,
1113 Register temp_reg,
1114 Register temp2_reg,
1115 Register temp3_reg,
1116 Register result_reg,
1117 FloatRegister vtemp_reg,
1118 Label* L_success,
1119 Label* L_failure,
1120 bool set_cond_codes = false);
1121
1122 // If r is valid, return r.
1123 // If r is invalid, remove a register r2 from available_regs, add r2
1124 // to regs_to_push, then return r2.
1125 Register allocate_if_noreg(const Register r,
1126 RegSetIterator<Register> &available_regs,
1127 RegSet ®s_to_push);
1128
1129 // Secondary subtype checking
1130 void lookup_secondary_supers_table_var(Register sub_klass,
1131 Register r_super_klass,
1132 Register temp1,
1133 Register temp2,
1134 Register temp3,
1135 FloatRegister vtemp,
1136 Register result,
1137 Label *L_success);
1138
1139
1140 // As above, but with a constant super_klass.
1141 // The result is in Register result, not the condition codes.
1142 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1143 Register r_super_klass,
1144 Register temp1,
1145 Register temp2,
1146 Register temp3,
1147 FloatRegister vtemp,
1148 Register result,
1149 u1 super_klass_slot,
1150 bool stub_is_near = false);
1151
1152 void verify_secondary_supers_table(Register r_sub_klass,
1153 Register r_super_klass,
1154 Register temp1,
1155 Register temp2,
1156 Register result);
1157
1158 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1159 Register r_array_base,
1160 Register r_array_index,
1161 Register r_bitmap,
1162 Register temp1,
1163 Register result,
1164 bool is_stub = true);
1165
1166 // Simplified, combined version, good for typical uses.
1167 // Falls through on failure.
1168 void check_klass_subtype(Register sub_klass,
1169 Register super_klass,
1170 Register temp_reg,
1171 Label& L_success);
1172
1173 void clinit_barrier(Register klass,
1174 Register thread,
1175 Label* L_fast_path = nullptr,
1176 Label* L_slow_path = nullptr);
1177
1178 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1179
1180 void verify_sve_vector_length(Register tmp = rscratch1);
1181 void reinitialize_ptrue() {
1182 if (UseSVE > 0) {
1183 sve_ptrue(ptrue, B);
1184 }
1185 }
1186 void verify_ptrue();
1187
1188 // Debugging
1189
1190 // only if +VerifyOops
1191 void _verify_oop(Register reg, const char* s, const char* file, int line);
1192 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1193
1194 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1195 if (VerifyOops) {
1196 _verify_oop(reg, s, file, line);
1197 }
1198 }
1199 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1200 if (VerifyOops) {
1201 _verify_oop_addr(reg, s, file, line);
1202 }
1203 }
1204
1205 // TODO: verify method and klass metadata (compare against vptr?)
1206 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1207 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1208
1209 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1210 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1211 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1212 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1213 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1214
1215 // Restore cpu control state after JNI call
1216 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1217
1218 // prints msg, dumps registers and stops execution
1219 void stop(const char* msg);
1220
1221 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1222
1223 void untested() { stop("untested"); }
1224
1225 void unimplemented(const char* what = "");
1226
1227 void should_not_reach_here() { stop("should not reach here"); }
1228
1229 void _assert_asm(Condition cc, const char* msg);
1230 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1231 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1232
1233 // Stack overflow checking
1234 void bang_stack_with_offset(int offset) {
1235 // stack grows down, caller passes positive offset
1236 assert(offset > 0, "must bang with negative offset");
1237 sub(rscratch2, sp, offset);
1238 str(zr, Address(rscratch2));
1239 }
1240
1241 // Writes to stack successive pages until offset reached to check for
1242 // stack overflow + shadow pages. Also, clobbers tmp
1243 void bang_stack_size(Register size, Register tmp);
1244
1245 // Check for reserved stack access in method being exited (for JIT)
1246 void reserved_stack_check();
1247
1248 // Arithmetics
1249
1250 // Clobber: rscratch1, rscratch2
1251 void addptr(const Address &dst, int32_t src);
1252
1253 // Clobber: rscratch1
1254 void cmpptr(Register src1, Address src2);
1255
1256 void cmpoop(Register obj1, Register obj2);
1257
1258 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1259 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1260 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1261 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1262
1263 void atomic_xchg(Register prev, Register newv, Register addr);
1264 void atomic_xchgw(Register prev, Register newv, Register addr);
1265 void atomic_xchgl(Register prev, Register newv, Register addr);
1266 void atomic_xchglw(Register prev, Register newv, Register addr);
1267 void atomic_xchgal(Register prev, Register newv, Register addr);
1268 void atomic_xchgalw(Register prev, Register newv, Register addr);
1269
1270 void orptr(Address adr, RegisterOrConstant src) {
1271 ldr(rscratch1, adr);
1272 if (src.is_register())
1273 orr(rscratch1, rscratch1, src.as_register());
1274 else
1275 orr(rscratch1, rscratch1, src.as_constant());
1276 str(rscratch1, adr);
1277 }
1278
1279 // A generic CAS; success or failure is in the EQ flag.
1280 // Clobbers rscratch1
1281 void cmpxchg(Register addr, Register expected, Register new_val,
1282 enum operand_size size,
1283 bool acquire, bool release, bool weak,
1284 Register result);
1285
1286 #ifdef ASSERT
1287 // Template short-hand support to clean-up after a failed call to trampoline
1288 // call generation (see trampoline_call() below), when a set of Labels must
1289 // be reset (before returning).
1290 template<typename Label, typename... More>
1291 void reset_labels(Label &lbl, More&... more) {
1292 lbl.reset(); reset_labels(more...);
1293 }
1294 template<typename Label>
1295 void reset_labels(Label &lbl) {
1296 lbl.reset();
1297 }
1298 #endif
1299
1300 private:
1301 void compare_eq(Register rn, Register rm, enum operand_size size);
1302
1303 public:
1304 // AArch64 OpenJDK uses four different types of calls:
1305 // - direct call: bl pc_relative_offset
1306 // This is the shortest and the fastest, but the offset has the range:
1307 // +/-128MB for the release build, +/-2MB for the debug build.
1308 //
1309 // - far call: adrp reg, pc_relative_offset; add; bl reg
1310 // This is longer than a direct call. The offset has
1311 // the range +/-4GB. As the code cache size is limited to 4GB,
1312 // far calls can reach anywhere in the code cache. If a jump is
1313 // needed rather than a call, a far jump 'b reg' can be used instead.
1314 // All instructions are embedded at a call site.
1315 //
1316 // - trampoline call:
1317 // This is only available in C1/C2-generated code (nmethod). It is a combination
1318 // of a direct call, which is used if the destination of a call is in range,
1319 // and a register-indirect call. It has the advantages of reaching anywhere in
1320 // the AArch64 address space and being patchable at runtime when the generated
1321 // code is being executed by other threads.
1322 //
1323 // [Main code section]
1324 // bl trampoline
1325 // [Stub code section]
1326 // trampoline:
1327 // ldr reg, pc + 8
1328 // br reg
1329 // <64-bit destination address>
1330 //
1331 // If the destination is in range when the generated code is moved to the code
1332 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1333 // is not used.
1334 // The optimization does not remove the trampoline from the stub section.
1335 // This is necessary because the trampoline may well be redirected later when
1336 // code is patched, and the new destination may not be reachable by a simple BR
1337 // instruction.
1338 //
1339 // - indirect call: move reg, address; blr reg
1340 // This too can reach anywhere in the address space, but it cannot be
1341 // patched while code is running, so it must only be modified at a safepoint.
1342 // This form of call is most suitable for targets at fixed addresses, which
1343 // will never be patched.
1344 //
1345 // The patching we do conforms to the "Concurrent modification and
1346 // execution of instructions" section of the Arm Architectural
1347 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1348 // or SVC instructions to be modified while another thread is
1349 // executing them.
1350 //
1351 // To patch a trampoline call when the BL can't reach, we first modify
1352 // the 64-bit destination address in the trampoline, then modify the
1353 // BL to point to the trampoline, then flush the instruction cache to
1354 // broadcast the change to all executing threads. See
1355 // NativeCall::set_destination_mt_safe for the details.
1356 //
1357 // There is a benign race in that the other thread might observe the
1358 // modified BL before it observes the modified 64-bit destination
1359 // address. That does not matter because the destination method has been
1360 // invalidated, so there will be a trap at its start.
1361 // For this to work, the destination address in the trampoline is
1362 // always updated, even if we're not using the trampoline.
1363
1364 // Emit a direct call if the entry address will always be in range,
1365 // otherwise a trampoline call.
1366 // Supported entry.rspec():
1367 // - relocInfo::runtime_call_type
1368 // - relocInfo::opt_virtual_call_type
1369 // - relocInfo::static_call_type
1370 // - relocInfo::virtual_call_type
1371 //
1372 // Return: the call PC or null if CodeCache is full.
1373 // Clobbers: rscratch1
1374 address trampoline_call(Address entry);
1375
1376 static bool far_branches() {
1377 return ReservedCodeCacheSize > branch_range;
1378 }
1379
1380 // Check if branches to the non nmethod section require a far jump
1381 static bool codestub_branch_needs_far_jump() {
1382 if (AOTCodeCache::is_on_for_dump()) {
1383 // To calculate far_codestub_branch_size correctly.
1384 return true;
1385 }
1386 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1387 }
1388
1389 // Emit a direct call/jump if the entry address will always be in range,
1390 // otherwise a far call/jump.
1391 // The address must be inside the code cache.
1392 // Supported entry.rspec():
1393 // - relocInfo::external_word_type
1394 // - relocInfo::runtime_call_type
1395 // - relocInfo::none
1396 // In the case of a far call/jump, the entry address is put in the tmp register.
1397 // The tmp register is invalidated.
1398 //
1399 // Far_jump returns the amount of the emitted code.
1400 void far_call(Address entry, Register tmp = rscratch1);
1401 int far_jump(Address entry, Register tmp = rscratch1);
1402
1403 static int far_codestub_branch_size() {
1404 if (codestub_branch_needs_far_jump()) {
1405 return 3 * 4; // adrp, add, br
1406 } else {
1407 return 4;
1408 }
1409 }
1410
1411 // Emit the CompiledIC call idiom
1412 address ic_call(address entry, jint method_index = 0);
1413 static int ic_check_size();
1414 int ic_check(int end_alignment);
1415
1416 public:
1417
1418 // Data
1419
1420 void mov_metadata(Register dst, Metadata* obj);
1421 Address allocate_metadata_address(Metadata* obj);
1422 Address constant_oop_address(jobject obj);
1423
1424 void movoop(Register dst, jobject obj);
1425
1426 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1427 void kernel_crc32(Register crc, Register buf, Register len,
1428 Register table0, Register table1, Register table2, Register table3,
1429 Register tmp, Register tmp2, Register tmp3);
1430 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1431 void kernel_crc32c(Register crc, Register buf, Register len,
1432 Register table0, Register table1, Register table2, Register table3,
1433 Register tmp, Register tmp2, Register tmp3);
1434
1435 // Stack push and pop individual 64 bit registers
1436 void push(Register src);
1437 void pop(Register dst);
1438
1439 void repne_scan(Register addr, Register value, Register count,
1440 Register scratch);
1441 void repne_scanw(Register addr, Register value, Register count,
1442 Register scratch);
1443
1444 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1445 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1446
1447 // If a constant does not fit in an immediate field, generate some
1448 // number of MOV instructions and then perform the operation
1449 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1450 add_sub_imm_insn insn1,
1451 add_sub_reg_insn insn2, bool is32);
1452 // Separate vsn which sets the flags
1453 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1454 add_sub_imm_insn insn1,
1455 add_sub_reg_insn insn2, bool is32);
1456
1457 #define WRAP(INSN, is32) \
1458 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1459 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1460 } \
1461 \
1462 void INSN(Register Rd, Register Rn, Register Rm, \
1463 enum shift_kind kind, unsigned shift = 0) { \
1464 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1465 } \
1466 \
1467 void INSN(Register Rd, Register Rn, Register Rm) { \
1468 Assembler::INSN(Rd, Rn, Rm); \
1469 } \
1470 \
1471 void INSN(Register Rd, Register Rn, Register Rm, \
1472 ext::operation option, int amount = 0) { \
1473 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1474 }
1475
1476 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1477
1478 #undef WRAP
1479 #define WRAP(INSN, is32) \
1480 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1481 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1482 } \
1483 \
1484 void INSN(Register Rd, Register Rn, Register Rm, \
1485 enum shift_kind kind, unsigned shift = 0) { \
1486 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1487 } \
1488 \
1489 void INSN(Register Rd, Register Rn, Register Rm) { \
1490 Assembler::INSN(Rd, Rn, Rm); \
1491 } \
1492 \
1493 void INSN(Register Rd, Register Rn, Register Rm, \
1494 ext::operation option, int amount = 0) { \
1495 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1496 }
1497
1498 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1499
1500 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1501 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1502 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1503 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1504
1505 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1506
1507 void verified_entry(Compile* C, int sp_inc);
1508
1509 // Inline type specific methods
1510 #include "asm/macroAssembler_common.hpp"
1511
1512 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1513 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1514 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1515 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1516 RegState reg_state[]);
1517 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1518 VMRegPair* from, int from_count, int& from_index, VMReg to,
1519 RegState reg_state[], Register val_array);
1520 int extend_stack_for_inline_args(int args_on_stack);
1521 void remove_frame(int initial_framesize, bool needs_stack_repair);
1522 VMReg spill_reg_for(VMReg reg);
1523 void save_stack_increment(int sp_inc, int frame_size);
1524
1525 void tableswitch(Register index, jint lowbound, jint highbound,
1526 Label &jumptable, Label &jumptable_end, int stride = 1) {
1527 adr(rscratch1, jumptable);
1528 subsw(rscratch2, index, lowbound);
1529 subsw(zr, rscratch2, highbound - lowbound);
1530 br(Assembler::HS, jumptable_end);
1531 add(rscratch1, rscratch1, rscratch2,
1532 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1533 br(rscratch1);
1534 }
1535
1536 // Form an address from base + offset in Rd. Rd may or may not
1537 // actually be used: you must use the Address that is returned. It
1538 // is up to you to ensure that the shift provided matches the size
1539 // of your data.
1540 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1541
1542 // Return true iff an address is within the 48-bit AArch64 address
1543 // space.
1544 bool is_valid_AArch64_address(address a) {
1545 return ((uint64_t)a >> 48) == 0;
1546 }
1547
1548 // Load the base of the cardtable byte map into reg.
1549 void load_byte_map_base(Register reg);
1550
1551 // Prolog generator routines to support switch between x86 code and
1552 // generated ARM code
1553
1554 // routine to generate an x86 prolog for a stub function which
1555 // bootstraps into the generated ARM code which directly follows the
1556 // stub
1557 //
1558
1559 public:
1560
1561 address read_polling_page(Register r, relocInfo::relocType rtype);
1562 void get_polling_page(Register dest, relocInfo::relocType rtype);
1563
1564 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1565 void update_byte_crc32(Register crc, Register val, Register table);
1566 void update_word_crc32(Register crc, Register v, Register tmp,
1567 Register table0, Register table1, Register table2, Register table3,
1568 bool upper = false);
1569
1570 address count_positives(Register ary1, Register len, Register result);
1571
1572 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1573 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1574
1575 // Ensure that the inline code and the stub use the same registers.
1576 #define ARRAYS_HASHCODE_REGISTERS \
1577 do { \
1578 assert(result == r0 && \
1579 ary == r1 && \
1580 cnt == r2 && \
1581 vdata0 == v3 && \
1582 vdata1 == v2 && \
1583 vdata2 == v1 && \
1584 vdata3 == v0 && \
1585 vmul0 == v4 && \
1586 vmul1 == v5 && \
1587 vmul2 == v6 && \
1588 vmul3 == v7 && \
1589 vpow == v12 && \
1590 vpowm == v13, "registers must match aarch64.ad"); \
1591 } while (0)
1592
1593 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1594
1595 void fill_words(Register base, Register cnt, Register value);
1596 void fill_words(Register base, uint64_t cnt, Register value);
1597
1598 address zero_words(Register base, uint64_t cnt);
1599 address zero_words(Register ptr, Register cnt);
1600 void zero_dcache_blocks(Register base, Register cnt);
1601
1602 static const int zero_words_block_size;
1603
1604 address byte_array_inflate(Register src, Register dst, Register len,
1605 FloatRegister vtmp1, FloatRegister vtmp2,
1606 FloatRegister vtmp3, Register tmp4);
1607
1608 void char_array_compress(Register src, Register dst, Register len,
1609 Register res,
1610 FloatRegister vtmp0, FloatRegister vtmp1,
1611 FloatRegister vtmp2, FloatRegister vtmp3,
1612 FloatRegister vtmp4, FloatRegister vtmp5);
1613
1614 void encode_iso_array(Register src, Register dst,
1615 Register len, Register res, bool ascii,
1616 FloatRegister vtmp0, FloatRegister vtmp1,
1617 FloatRegister vtmp2, FloatRegister vtmp3,
1618 FloatRegister vtmp4, FloatRegister vtmp5);
1619
1620 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1621 address pio2, address dsin_coef, address dcos_coef);
1622 private:
1623 // begin trigonometric functions support block
1624 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1625 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1626 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1627 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1628 // end trigonometric functions support block
1629 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1630 Register src1, Register src2);
1631 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1632 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1633 }
1634 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1635 Register y, Register y_idx, Register z,
1636 Register carry, Register product,
1637 Register idx, Register kdx);
1638 void multiply_128_x_128_loop(Register y, Register z,
1639 Register carry, Register carry2,
1640 Register idx, Register jdx,
1641 Register yz_idx1, Register yz_idx2,
1642 Register tmp, Register tmp3, Register tmp4,
1643 Register tmp7, Register product_hi);
1644 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1645 Register len, Register tmp0, Register tmp1, Register tmp2,
1646 Register tmp3);
1647 void kernel_crc32_using_crc32(Register crc, Register buf,
1648 Register len, Register tmp0, Register tmp1, Register tmp2,
1649 Register tmp3);
1650 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1651 Register len, Register tmp0, Register tmp1, Register tmp2,
1652 Register tmp3);
1653 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1654 Register len, Register tmp0, Register tmp1, Register tmp2,
1655 Register tmp3);
1656 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1657 Register len, Register tmp0, Register tmp1, Register tmp2,
1658 size_t table_offset);
1659
1660 void ghash_modmul (FloatRegister result,
1661 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1662 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1663 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1664 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1665 public:
1666 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1667 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1668 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1669 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1670 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1671 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1672 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1673 void ghash_multiply_wide(int index,
1674 FloatRegister result_lo, FloatRegister result_hi,
1675 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1676 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1677 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1678 FloatRegister p, FloatRegister z, FloatRegister t1);
1679 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1680 FloatRegister p, FloatRegister z, FloatRegister t1);
1681 void ghash_processBlocks_wide(Label& p, Register state, Register subkeyH,
1682 Register data, Register blocks, int unrolls);
1683
1684
1685 void aesenc_loadkeys(Register key, Register keylen);
1686 void aesecb_encrypt(Register from, Register to, Register keylen,
1687 FloatRegister data = v0, int unrolls = 1);
1688 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1689 void aes_round(FloatRegister input, FloatRegister subkey);
1690
1691 // ChaCha20 functions support block
1692 void cc20_qr_add4(FloatRegister (&addFirst)[4],
1693 FloatRegister (&addSecond)[4]);
1694 void cc20_qr_xor4(FloatRegister (&firstElem)[4],
1695 FloatRegister (&secondElem)[4], FloatRegister (&result)[4]);
1696 void cc20_qr_lrot4(FloatRegister (&sourceReg)[4],
1697 FloatRegister (&destReg)[4], int bits, FloatRegister table);
1698 void cc20_set_qr_registers(FloatRegister (&vectorSet)[4],
1699 const FloatRegister (&stateVectors)[16], int idx1, int idx2,
1700 int idx3, int idx4);
1701
1702 // Place an ISB after code may have been modified due to a safepoint.
1703 void safepoint_isb();
1704
1705 private:
1706 // Return the effective address r + (r1 << ext) + offset.
1707 // Uses rscratch2.
1708 Address offsetted_address(Register r, Register r1, Address::extend ext,
1709 int offset, int size);
1710
1711 private:
1712 // Returns an address on the stack which is reachable with a ldr/str of size
1713 // Uses rscratch2 if the address is not directly reachable
1714 Address spill_address(int size, int offset, Register tmp=rscratch2);
1715 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1716
1717 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1718
1719 // Check whether two loads/stores can be merged into ldp/stp.
1720 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1721
1722 // Merge current load/store with previous load/store into ldp/stp.
1723 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1724
1725 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1726 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1727
1728 public:
1729 void spill(Register Rx, bool is64, int offset) {
1730 if (is64) {
1731 str(Rx, spill_address(8, offset));
1732 } else {
1733 strw(Rx, spill_address(4, offset));
1734 }
1735 }
1736 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1737 str(Vx, T, spill_address(1 << (int)T, offset));
1738 }
1739
1740 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1741 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1742 }
1743 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1744 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1745 }
1746
1747 void unspill(Register Rx, bool is64, int offset) {
1748 if (is64) {
1749 ldr(Rx, spill_address(8, offset));
1750 } else {
1751 ldrw(Rx, spill_address(4, offset));
1752 }
1753 }
1754 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1755 ldr(Vx, T, spill_address(1 << (int)T, offset));
1756 }
1757
1758 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1759 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1760 }
1761 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1762 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1763 }
1764
1765 void spill_copy128(int src_offset, int dst_offset,
1766 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1767 if (src_offset < 512 && (src_offset & 7) == 0 &&
1768 dst_offset < 512 && (dst_offset & 7) == 0) {
1769 ldp(tmp1, tmp2, Address(sp, src_offset));
1770 stp(tmp1, tmp2, Address(sp, dst_offset));
1771 } else {
1772 unspill(tmp1, true, src_offset);
1773 spill(tmp1, true, dst_offset);
1774 unspill(tmp1, true, src_offset+8);
1775 spill(tmp1, true, dst_offset+8);
1776 }
1777 }
1778 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1779 int sve_vec_reg_size_in_bytes) {
1780 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1781 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1782 spill_copy128(src_offset, dst_offset);
1783 src_offset += 16;
1784 dst_offset += 16;
1785 }
1786 }
1787 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1788 int sve_predicate_reg_size_in_bytes) {
1789 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1790 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1791 reinitialize_ptrue();
1792 }
1793 void cache_wb(Address line);
1794 void cache_wbsync(bool is_pre);
1795
1796 // Code for java.lang.Thread::onSpinWait() intrinsic.
1797 void spin_wait();
1798
1799 void lightweight_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1800 void lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1801
1802 private:
1803 // Check the current thread doesn't need a cross modify fence.
1804 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1805
1806 };
1807
1808 #ifdef ASSERT
1809 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1810 #endif
1811
1812 struct tableswitch {
1813 Register _reg;
1814 int _insn_index; jint _first_key; jint _last_key;
1815 Label _after;
1816 Label _branches;
1817 };
1818
1819 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP