1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/globalDefinitions.hpp"
37 #include "utilities/macros.hpp"
38 #include "utilities/powerOfTwo.hpp"
39 #include "runtime/signature.hpp"
40
41
42 class ciInlineKlass;
43
44 class OopMap;
45
46 // MacroAssembler extends Assembler by frequently used macros.
47 //
48 // Instructions for which a 'better' code sequence exists depending
49 // on arguments should also go in here.
50
51 class MacroAssembler: public Assembler {
52 friend class LIR_Assembler;
53
54 public:
55 using Assembler::mov;
56 using Assembler::movi;
57
58 protected:
59
60 // Support for VM calls
61 //
62 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
63 // may customize this version by overriding it for its purposes (e.g., to save/restore
64 // additional registers when doing a VM call).
65 virtual void call_VM_leaf_base(
66 address entry_point, // the entry point
67 int number_of_arguments, // the number of arguments to pop after the call
68 Label *retaddr = nullptr
69 );
70
71 virtual void call_VM_leaf_base(
72 address entry_point, // the entry point
73 int number_of_arguments, // the number of arguments to pop after the call
74 Label &retaddr) {
75 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
76 }
77
78 // This is the base routine called by the different versions of call_VM. The interpreter
79 // may customize this version by overriding it for its purposes (e.g., to save/restore
80 // additional registers when doing a VM call).
81 //
82 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
83 // returns the register which contains the thread upon return. If a thread register has been
84 // specified, the return value will correspond to that register. If no last_java_sp is specified
85 // (noreg) than rsp will be used instead.
86 virtual void call_VM_base( // returns the register containing the thread upon return
87 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
88 Register java_thread, // the thread if computed before ; use noreg otherwise
89 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
90 Label* return_pc, // to set up last_Java_frame; use nullptr otherwise
91 address entry_point, // the entry point
92 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
93 bool check_exceptions // whether to check for pending exceptions after return
94 );
95
96 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
97
98 enum KlassDecodeMode {
99 KlassDecodeNone,
100 KlassDecodeZero,
101 KlassDecodeXor,
102 KlassDecodeMovk
103 };
104
105 // Calculate decoding mode based on given parameters, used for checking then ultimately setting.
106 static KlassDecodeMode klass_decode_mode(address base, int shift, const size_t range);
107
108 private:
109 static KlassDecodeMode _klass_decode_mode;
110
111 // Returns above setting with asserts
112 static KlassDecodeMode klass_decode_mode();
113
114 public:
115 // Checks the decode mode and returns false if not compatible with preferred decoding mode.
116 static bool check_klass_decode_mode(address base, int shift, const size_t range);
117
118 // Sets the decode mode and returns false if cannot be set.
119 static bool set_klass_decode_mode(address base, int shift, const size_t range);
120
121 public:
122 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
123
124 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
125 // The implementation is only non-empty for the InterpreterMacroAssembler,
126 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
127 virtual void check_and_handle_popframe(Register java_thread);
128 virtual void check_and_handle_earlyret(Register java_thread);
129
130 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp = rscratch1);
131 void rt_call(address dest, Register tmp = rscratch1);
132
133 // Load Effective Address
134 void lea(Register r, const Address &a) {
135 InstructionMark im(this);
136 a.lea(this, r);
137 }
138
139 // Whether materializing the given address for a LDR/STR requires an
140 // additional lea instruction.
141 static bool legitimize_address_requires_lea(const Address &a, int size) {
142 return a.getMode() == Address::base_plus_offset &&
143 !Address::offset_ok_for_immed(a.offset(), exact_log2(size));
144 }
145
146 /* Sometimes we get misaligned loads and stores, usually from Unsafe
147 accesses, and these can exceed the offset range. */
148 Address legitimize_address(const Address &a, int size, Register scratch) {
149 if (legitimize_address_requires_lea(a, size)) {
150 block_comment("legitimize_address {");
151 lea(scratch, a);
152 block_comment("} legitimize_address");
153 return Address(scratch);
154 }
155 return a;
156 }
157
158 void addmw(Address a, Register incr, Register scratch) {
159 ldrw(scratch, a);
160 addw(scratch, scratch, incr);
161 strw(scratch, a);
162 }
163
164 // Add constant to memory word
165 void addmw(Address a, int imm, Register scratch) {
166 ldrw(scratch, a);
167 if (imm > 0)
168 addw(scratch, scratch, (unsigned)imm);
169 else
170 subw(scratch, scratch, (unsigned)-imm);
171 strw(scratch, a);
172 }
173
174 void bind(Label& L) {
175 Assembler::bind(L);
176 code()->clear_last_merge_candidate();
177 code()->set_last_label(pc());
178 }
179
180 void membar(Membar_mask_bits order_constraint);
181
182 using Assembler::ldr;
183 using Assembler::str;
184 using Assembler::ldrw;
185 using Assembler::strw;
186
187 void ldr(Register Rx, const Address &adr);
188 void ldrw(Register Rw, const Address &adr);
189 void str(Register Rx, const Address &adr);
190 void strw(Register Rx, const Address &adr);
191
192 // Frame creation and destruction shared between JITs.
193 DEBUG_ONLY(void build_frame(int framesize);)
194 void build_frame(int framesize DEBUG_ONLY(COMMA bool zap_rfp_lr_spills));
195 void remove_frame(int framesize);
196
197 virtual void _call_Unimplemented(address call_site) {
198 mov(rscratch2, call_site);
199 }
200
201 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
202 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
203 // https://reviews.llvm.org/D3311
204
205 #ifdef _WIN64
206 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
207 #else
208 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
209 #endif
210
211 // aliases defined in AARCH64 spec
212
213 template<class T>
214 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
215
216 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
217 inline void cmp(Register Rd, unsigned imm) = delete;
218
219 template<class T>
220 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
221
222 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
223 inline void cmn(Register Rd, unsigned imm) = delete;
224
225 void cset(Register Rd, Assembler::Condition cond) {
226 csinc(Rd, zr, zr, ~cond);
227 }
228 void csetw(Register Rd, Assembler::Condition cond) {
229 csincw(Rd, zr, zr, ~cond);
230 }
231
232 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
233 csneg(Rd, Rn, Rn, ~cond);
234 }
235 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
236 csnegw(Rd, Rn, Rn, ~cond);
237 }
238
239 inline void movw(Register Rd, Register Rn) {
240 if (Rd == sp || Rn == sp) {
241 Assembler::addw(Rd, Rn, 0U);
242 } else {
243 orrw(Rd, zr, Rn);
244 }
245 }
246 inline void mov(Register Rd, Register Rn) {
247 assert(Rd != r31_sp && Rn != r31_sp, "should be");
248 if (Rd == Rn) {
249 } else if (Rd == sp || Rn == sp) {
250 Assembler::add(Rd, Rn, 0U);
251 } else {
252 orr(Rd, zr, Rn);
253 }
254 }
255
256 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
257 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
258
259 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
260 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
261
262 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
263 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
264
265 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
266 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
267 }
268 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
269 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
270 }
271
272 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
273 bfmw(Rd, Rn, lsb, (lsb + width - 1));
274 }
275 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
276 bfm(Rd, Rn, lsb , (lsb + width - 1));
277 }
278
279 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
280 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
281 }
282 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
283 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
284 }
285
286 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
287 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
288 }
289 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
290 sbfm(Rd, Rn, lsb , (lsb + width - 1));
291 }
292
293 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
294 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
295 }
296 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
297 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
298 }
299
300 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
301 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
302 }
303 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
304 ubfm(Rd, Rn, lsb , (lsb + width - 1));
305 }
306
307 inline void asrw(Register Rd, Register Rn, unsigned imm) {
308 sbfmw(Rd, Rn, imm, 31);
309 }
310
311 inline void asr(Register Rd, Register Rn, unsigned imm) {
312 sbfm(Rd, Rn, imm, 63);
313 }
314
315 inline void lslw(Register Rd, Register Rn, unsigned imm) {
316 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
317 }
318
319 inline void lsl(Register Rd, Register Rn, unsigned imm) {
320 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
321 }
322
323 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
324 ubfmw(Rd, Rn, imm, 31);
325 }
326
327 inline void lsr(Register Rd, Register Rn, unsigned imm) {
328 ubfm(Rd, Rn, imm, 63);
329 }
330
331 inline void rorw(Register Rd, Register Rn, unsigned imm) {
332 extrw(Rd, Rn, Rn, imm);
333 }
334
335 inline void ror(Register Rd, Register Rn, unsigned imm) {
336 extr(Rd, Rn, Rn, imm);
337 }
338
339 inline void rolw(Register Rd, Register Rn, unsigned imm) {
340 extrw(Rd, Rn, Rn, (32 - imm));
341 }
342
343 inline void rol(Register Rd, Register Rn, unsigned imm) {
344 extr(Rd, Rn, Rn, (64 - imm));
345 }
346
347 using Assembler::rax1;
348 using Assembler::eor3;
349
350 inline void rax1(Register Rd, Register Rn, Register Rm) {
351 eor(Rd, Rn, Rm, ROR, 63); // Rd = Rn ^ rol(Rm, 1)
352 }
353
354 inline void eor3(Register Rd, Register Rn, Register Rm, Register Rk) {
355 assert(Rd != Rn, "Use tmp register");
356 eor(Rd, Rm, Rk);
357 eor(Rd, Rd, Rn);
358 }
359
360 inline void sxtbw(Register Rd, Register Rn) {
361 sbfmw(Rd, Rn, 0, 7);
362 }
363 inline void sxthw(Register Rd, Register Rn) {
364 sbfmw(Rd, Rn, 0, 15);
365 }
366 inline void sxtb(Register Rd, Register Rn) {
367 sbfm(Rd, Rn, 0, 7);
368 }
369 inline void sxth(Register Rd, Register Rn) {
370 sbfm(Rd, Rn, 0, 15);
371 }
372 inline void sxtw(Register Rd, Register Rn) {
373 sbfm(Rd, Rn, 0, 31);
374 }
375
376 inline void uxtbw(Register Rd, Register Rn) {
377 ubfmw(Rd, Rn, 0, 7);
378 }
379 inline void uxthw(Register Rd, Register Rn) {
380 ubfmw(Rd, Rn, 0, 15);
381 }
382 inline void uxtb(Register Rd, Register Rn) {
383 ubfm(Rd, Rn, 0, 7);
384 }
385 inline void uxth(Register Rd, Register Rn) {
386 ubfm(Rd, Rn, 0, 15);
387 }
388 inline void uxtw(Register Rd, Register Rn) {
389 ubfm(Rd, Rn, 0, 31);
390 }
391
392 inline void cmnw(Register Rn, Register Rm) {
393 addsw(zr, Rn, Rm);
394 }
395 inline void cmn(Register Rn, Register Rm) {
396 adds(zr, Rn, Rm);
397 }
398
399 inline void cmpw(Register Rn, Register Rm) {
400 subsw(zr, Rn, Rm);
401 }
402 inline void cmp(Register Rn, Register Rm) {
403 subs(zr, Rn, Rm);
404 }
405
406 inline void negw(Register Rd, Register Rn) {
407 subw(Rd, zr, Rn);
408 }
409
410 inline void neg(Register Rd, Register Rn) {
411 sub(Rd, zr, Rn);
412 }
413
414 inline void negsw(Register Rd, Register Rn) {
415 subsw(Rd, zr, Rn);
416 }
417
418 inline void negs(Register Rd, Register Rn) {
419 subs(Rd, zr, Rn);
420 }
421
422 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
423 addsw(zr, Rn, Rm, kind, shift);
424 }
425 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
426 adds(zr, Rn, Rm, kind, shift);
427 }
428
429 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
430 subsw(zr, Rn, Rm, kind, shift);
431 }
432 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
433 subs(zr, Rn, Rm, kind, shift);
434 }
435
436 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
437 subw(Rd, zr, Rn, kind, shift);
438 }
439
440 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
441 sub(Rd, zr, Rn, kind, shift);
442 }
443
444 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
445 subsw(Rd, zr, Rn, kind, shift);
446 }
447
448 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
449 subs(Rd, zr, Rn, kind, shift);
450 }
451
452 inline void mnegw(Register Rd, Register Rn, Register Rm) {
453 msubw(Rd, Rn, Rm, zr);
454 }
455 inline void mneg(Register Rd, Register Rn, Register Rm) {
456 msub(Rd, Rn, Rm, zr);
457 }
458
459 inline void mulw(Register Rd, Register Rn, Register Rm) {
460 maddw(Rd, Rn, Rm, zr);
461 }
462 inline void mul(Register Rd, Register Rn, Register Rm) {
463 madd(Rd, Rn, Rm, zr);
464 }
465
466 inline void smnegl(Register Rd, Register Rn, Register Rm) {
467 smsubl(Rd, Rn, Rm, zr);
468 }
469 inline void smull(Register Rd, Register Rn, Register Rm) {
470 smaddl(Rd, Rn, Rm, zr);
471 }
472
473 inline void umnegl(Register Rd, Register Rn, Register Rm) {
474 umsubl(Rd, Rn, Rm, zr);
475 }
476 inline void umull(Register Rd, Register Rn, Register Rm) {
477 umaddl(Rd, Rn, Rm, zr);
478 }
479
480 #define WRAP(INSN) \
481 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
482 if (VM_Version::supports_a53mac() && Ra != zr) \
483 nop(); \
484 Assembler::INSN(Rd, Rn, Rm, Ra); \
485 }
486
487 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
488 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
489 #undef WRAP
490
491
492 // macro assembly operations needed for aarch64
493
494 public:
495
496 enum FpPushPopMode {
497 PushPopFull,
498 PushPopSVE,
499 PushPopNeon,
500 PushPopFp
501 };
502
503 // first two private routines for loading 32 bit or 64 bit constants
504 private:
505
506 void mov_immediate64(Register dst, uint64_t imm64);
507 void mov_immediate32(Register dst, uint32_t imm32);
508
509 void mov(Register dst, Address a);
510
511 public:
512
513 int push(RegSet regset, Register stack);
514 int pop(RegSet regset, Register stack);
515
516 int push_fp(FloatRegSet regset, Register stack, FpPushPopMode mode = PushPopFull);
517 int pop_fp(FloatRegSet regset, Register stack, FpPushPopMode mode = PushPopFull);
518
519 static RegSet call_clobbered_gp_registers();
520
521 int push_p(PRegSet regset, Register stack);
522 int pop_p(PRegSet regset, Register stack);
523
524 // Push and pop everything that might be clobbered by a native
525 // runtime call except rscratch1 and rscratch2. (They are always
526 // scratch, so we don't have to protect them.) Only save the lower
527 // 64 bits of each vector register. Additional registers can be excluded
528 // in a passed RegSet.
529 void push_call_clobbered_registers_except(RegSet exclude);
530 void pop_call_clobbered_registers_except(RegSet exclude);
531
532 void push_call_clobbered_registers() {
533 push_call_clobbered_registers_except(RegSet());
534 }
535 void pop_call_clobbered_registers() {
536 pop_call_clobbered_registers_except(RegSet());
537 }
538
539
540 // now mov instructions for loading absolute addresses and 32 or
541 // 64 bit integers
542
543 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
544
545 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
546 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
547
548 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
549
550 void mov(Register dst, RegisterOrConstant src) {
551 if (src.is_register())
552 mov(dst, src.as_register());
553 else
554 mov(dst, src.as_constant());
555 }
556
557 void movptr(Register r, uintptr_t imm64);
558
559 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
560
561 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
562 orr(Vd, T, Vn, Vn);
563 }
564
565 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
566 fcvtsh(tmp, src);
567 smov(dst, tmp, H, 0);
568 }
569
570 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
571 mov(tmp, H, 0, src);
572 fcvths(dst, tmp);
573 }
574
575 // Generalized Test Bit And Branch, including a "far" variety which
576 // spans more than 32KiB.
577 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
578 assert(cond == EQ || cond == NE, "must be");
579
580 if (isfar)
581 cond = ~cond;
582
583 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
584 if (cond == Assembler::EQ)
585 branch = &Assembler::tbz;
586 else
587 branch = &Assembler::tbnz;
588
589 if (isfar) {
590 Label L;
591 (this->*branch)(Rt, bitpos, L);
592 b(dest);
593 bind(L);
594 } else {
595 (this->*branch)(Rt, bitpos, dest);
596 }
597 }
598
599 // macro instructions for accessing and updating floating point
600 // status register
601 //
602 // FPSR : op1 == 011
603 // CRn == 0100
604 // CRm == 0100
605 // op2 == 001
606
607 inline void get_fpsr(Register reg)
608 {
609 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
610 }
611
612 inline void set_fpsr(Register reg)
613 {
614 msr(0b011, 0b0100, 0b0100, 0b001, reg);
615 }
616
617 inline void clear_fpsr()
618 {
619 msr(0b011, 0b0100, 0b0100, 0b001, zr);
620 }
621
622 // FPCR : op1 == 011
623 // CRn == 0100
624 // CRm == 0100
625 // op2 == 000
626
627 inline void get_fpcr(Register reg) {
628 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
629 }
630
631 inline void set_fpcr(Register reg) {
632 msr(0b011, 0b0100, 0b0100, 0b000, reg);
633 }
634
635 // DCZID_EL0: op1 == 011
636 // CRn == 0000
637 // CRm == 0000
638 // op2 == 111
639 inline void get_dczid_el0(Register reg)
640 {
641 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
642 }
643
644 // CTR_EL0: op1 == 011
645 // CRn == 0000
646 // CRm == 0000
647 // op2 == 001
648 inline void get_ctr_el0(Register reg)
649 {
650 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
651 }
652
653 inline void get_nzcv(Register reg) {
654 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
655 }
656
657 inline void set_nzcv(Register reg) {
658 msr(0b011, 0b0100, 0b0010, 0b000, reg);
659 }
660
661 // CNTVCTSS_EL0: op1 == 011
662 // CRn == 1110
663 // CRm == 0000
664 // op2 == 110
665 inline void get_cntvctss_el0(Register reg) {
666 mrs(0b011, 0b1110, 0b0000, 0b110, reg);
667 }
668
669 // idiv variant which deals with MINLONG as dividend and -1 as divisor
670 int corrected_idivl(Register result, Register ra, Register rb,
671 bool want_remainder, Register tmp = rscratch1);
672 int corrected_idivq(Register result, Register ra, Register rb,
673 bool want_remainder, Register tmp = rscratch1);
674
675 // Support for null-checks
676 //
677 // Generates code that causes a null OS exception if the content of reg is null.
678 // If the accessed location is M[reg + offset] and the offset is known, provide the
679 // offset. No explicit code generation is needed if the offset is within a certain
680 // range (0 <= offset <= page_size).
681
682 virtual void null_check(Register reg, int offset = -1);
683 static bool needs_explicit_null_check(intptr_t offset);
684 static bool uses_implicit_null_check(void* address);
685
686 // markWord tests, kills markWord reg
687 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
688
689 // inlineKlass queries, kills temp_reg
690 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
691
692 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
693 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
694 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
695
696 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
697 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
698 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
699 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
700 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
701 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
702
703 // Check array klass layout helper for flat or null-free arrays...
704 void test_flat_array_layout(Register lh, Label& is_flat_array);
705
706 static address target_addr_for_insn(address insn_addr);
707
708 // Required platform-specific helpers for Label::patch_instructions.
709 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
710 static int pd_patch_instruction_size(address branch, address target);
711 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
712 pd_patch_instruction_size(branch, target);
713 }
714 static address pd_call_destination(address branch) {
715 return target_addr_for_insn(branch);
716 }
717 #ifndef PRODUCT
718 static void pd_print_patched_instruction(address branch);
719 #endif
720
721 static int patch_oop(address insn_addr, address o);
722
723 // Return whether code is emitted to a scratch blob.
724 virtual bool in_scratch_emit_size() {
725 return false;
726 }
727 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
728 static int max_trampoline_stub_size();
729 void emit_static_call_stub();
730 static int static_call_stub_size();
731
732 // The following 4 methods return the offset of the appropriate move instruction
733
734 // Support for fast byte/short loading with zero extension (depending on particular CPU)
735 int load_unsigned_byte(Register dst, Address src);
736 int load_unsigned_short(Register dst, Address src);
737
738 // Support for fast byte/short loading with sign extension (depending on particular CPU)
739 int load_signed_byte(Register dst, Address src);
740 int load_signed_short(Register dst, Address src);
741
742 int load_signed_byte32(Register dst, Address src);
743 int load_signed_short32(Register dst, Address src);
744
745 // Support for sign-extension (hi:lo = extend_sign(lo))
746 void extend_sign(Register hi, Register lo);
747
748 // Clean up a subword typed value to the representation in compliance with JVMS ยง2.3
749 void narrow_subword_type(Register reg, BasicType bt);
750
751 // Load and store values by size and signed-ness
752 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
753 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
754
755 // Support for inc/dec with optimal instruction selection depending on value
756
757 // x86_64 aliases an unqualified register/address increment and
758 // decrement to call incrementq and decrementq but also supports
759 // explicitly sized calls to incrementq/decrementq or
760 // incrementl/decrementl
761
762 // for aarch64 the proper convention would be to use
763 // increment/decrement for 64 bit operations and
764 // incrementw/decrementw for 32 bit operations. so when porting
765 // x86_64 code we can leave calls to increment/decrement as is,
766 // replace incrementq/decrementq with increment/decrement and
767 // replace incrementl/decrementl with incrementw/decrementw.
768
769 // n.b. increment/decrement calls with an Address destination will
770 // need to use a scratch register to load the value to be
771 // incremented. increment/decrement calls which add or subtract a
772 // constant value greater than 2^12 will need to use a 2nd scratch
773 // register to hold the constant. so, a register increment/decrement
774 // may trash rscratch2 and an address increment/decrement trash
775 // rscratch and rscratch2
776
777 void decrementw(Address dst, int value = 1);
778 void decrementw(Register reg, int value = 1);
779
780 void decrement(Register reg, int value = 1);
781 void decrement(Address dst, int value = 1);
782
783 void incrementw(Address dst, int value = 1);
784 void incrementw(Register reg, int value = 1);
785
786 void increment(Register reg, int value = 1);
787 void increment(Address dst, int value = 1);
788
789
790 // Alignment
791 void align(int modulus);
792 void align(int modulus, int target);
793
794 // nop
795 void post_call_nop();
796
797 // Stack frame creation/removal
798 void enter(bool strip_ret_addr = false);
799 void leave();
800
801 // ROP Protection
802 void protect_return_address();
803 void protect_return_address(Register return_reg);
804 void authenticate_return_address();
805 void authenticate_return_address(Register return_reg);
806 void strip_return_address();
807 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
808
809 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
810 // The pointer will be loaded into the thread register.
811 void get_thread(Register thread);
812
813 // support for argument shuffling
814 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
815 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
816 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
817 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
818 void object_move(
819 OopMap* map,
820 int oop_handle_offset,
821 int framesize_in_slots,
822 VMRegPair src,
823 VMRegPair dst,
824 bool is_receiver,
825 int* receiver_offset);
826
827
828 // Support for VM calls
829 //
830 // It is imperative that all calls into the VM are handled via the call_VM macros.
831 // They make sure that the stack linkage is setup correctly. call_VM's correspond
832 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
833
834
835 void call_VM(Register oop_result,
836 address entry_point,
837 bool check_exceptions = true);
838 void call_VM(Register oop_result,
839 address entry_point,
840 Register arg_1,
841 bool check_exceptions = true);
842 void call_VM(Register oop_result,
843 address entry_point,
844 Register arg_1, Register arg_2,
845 bool check_exceptions = true);
846 void call_VM(Register oop_result,
847 address entry_point,
848 Register arg_1, Register arg_2, Register arg_3,
849 bool check_exceptions = true);
850
851 // Overloadings with last_Java_sp
852 void call_VM(Register oop_result,
853 Register last_java_sp,
854 address entry_point,
855 int number_of_arguments = 0,
856 bool check_exceptions = true);
857 void call_VM(Register oop_result,
858 Register last_java_sp,
859 address entry_point,
860 Register arg_1, bool
861 check_exceptions = true);
862 void call_VM(Register oop_result,
863 Register last_java_sp,
864 address entry_point,
865 Register arg_1, Register arg_2,
866 bool check_exceptions = true);
867 void call_VM(Register oop_result,
868 Register last_java_sp,
869 address entry_point,
870 Register arg_1, Register arg_2, Register arg_3,
871 bool check_exceptions = true);
872
873 void get_vm_result_oop(Register oop_result, Register thread);
874 void get_vm_result_metadata(Register metadata_result, Register thread);
875
876 // These always tightly bind to MacroAssembler::call_VM_base
877 // bypassing the virtual implementation
878 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
879 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
880 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
881 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
882 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
883
884 void call_VM_leaf(address entry_point,
885 int number_of_arguments = 0);
886 void call_VM_leaf(address entry_point,
887 Register arg_1);
888 void call_VM_leaf(address entry_point,
889 Register arg_1, Register arg_2);
890 void call_VM_leaf(address entry_point,
891 Register arg_1, Register arg_2, Register arg_3);
892
893 // These always tightly bind to MacroAssembler::call_VM_leaf_base
894 // bypassing the virtual implementation
895 void super_call_VM_leaf(address entry_point);
896 void super_call_VM_leaf(address entry_point, Register arg_1);
897 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
898 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
899 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
900
901 // last Java Frame (fills frame anchor)
902 void set_last_Java_frame(Register last_java_sp,
903 Register last_java_fp,
904 address last_java_pc,
905 Register scratch);
906
907 void set_last_Java_frame(Register last_java_sp,
908 Register last_java_fp,
909 Label &last_java_pc,
910 Register scratch);
911
912 void set_last_Java_frame(Register last_java_sp,
913 Register last_java_fp,
914 Register last_java_pc,
915 Register scratch);
916
917 void reset_last_Java_frame(Register thread);
918
919 // thread in the default location (rthread)
920 void reset_last_Java_frame(bool clear_fp);
921
922 void resolve_jobject(Register value, Register tmp1, Register tmp2);
923 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
924
925 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
926 void c2bool(Register x);
927
928 void load_method_holder_cld(Register rresult, Register rmethod);
929 void load_method_holder(Register holder, Register method);
930
931 // oop manipulations
932 void load_metadata(Register dst, Register src);
933
934 void load_narrow_klass_compact(Register dst, Register src);
935 void load_klass(Register dst, Register src);
936 void store_klass(Register dst, Register src);
937 void cmp_klass(Register obj, Register klass, Register tmp);
938 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
939
940 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
941 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
942 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
943
944 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
945 Register tmp1, Register tmp2);
946
947 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
948 Register tmp1, Register tmp2, Register tmp3);
949
950 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
951
952 // inline type data payload offsets...
953 void payload_offset(Register inline_klass, Register offset);
954 void payload_address(Register oop, Register data, Register inline_klass);
955
956 void load_heap_oop(Register dst, Address src, Register tmp1,
957 Register tmp2, DecoratorSet decorators = 0);
958
959 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
960 Register tmp2, DecoratorSet decorators = 0);
961 void store_heap_oop(Address dst, Register val, Register tmp1,
962 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
963
964 // currently unimplemented
965 // Used for storing null. All other oop constants should be
966 // stored using routines that take a jobject.
967 void store_heap_oop_null(Address dst);
968
969 void load_prototype_header(Register dst, Register src);
970
971 void store_klass_gap(Register dst, Register src);
972
973 // This dummy is to prevent a call to store_heap_oop from
974 // converting a zero (like null) into a Register by giving
975 // the compiler two choices it can't resolve
976
977 void store_heap_oop(Address dst, void* dummy);
978
979 void encode_heap_oop(Register d, Register s);
980 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
981 void decode_heap_oop(Register d, Register s);
982 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
983 void encode_heap_oop_not_null(Register r);
984 void decode_heap_oop_not_null(Register r);
985 void encode_heap_oop_not_null(Register dst, Register src);
986 void decode_heap_oop_not_null(Register dst, Register src);
987
988 void set_narrow_oop(Register dst, jobject obj);
989
990 void decode_klass_not_null_for_aot(Register dst, Register src);
991 void encode_klass_not_null_for_aot(Register dst, Register src);
992 void encode_klass_not_null(Register r);
993 void decode_klass_not_null(Register r);
994 void encode_klass_not_null(Register dst, Register src);
995 void decode_klass_not_null(Register dst, Register src);
996
997 void set_narrow_klass(Register dst, Klass* k);
998
999 // if heap base register is used - reinit it with the correct value
1000 void reinit_heapbase();
1001
1002 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1003
1004 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
1005 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1006 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
1007 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1008
1009 void push_cont_fastpath(Register java_thread = rthread);
1010 void pop_cont_fastpath(Register java_thread = rthread);
1011
1012 // Round up to a power of two
1013 void round_to(Register reg, int modulus);
1014
1015 // java.lang.Math::round intrinsics
1016 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1017 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1018
1019 // allocation
1020
1021 void tlab_allocate(
1022 Register obj, // result: pointer to object after successful allocation
1023 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1024 int con_size_in_bytes, // object size in bytes if known at compile time
1025 Register t1, // temp register
1026 Register t2, // temp register
1027 Label& slow_case // continuation point if fast allocation fails
1028 );
1029 void verify_tlab();
1030
1031 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
1032
1033 // interface method calling
1034 void lookup_interface_method(Register recv_klass,
1035 Register intf_klass,
1036 RegisterOrConstant itable_index,
1037 Register method_result,
1038 Register scan_temp,
1039 Label& no_such_interface,
1040 bool return_method = true);
1041
1042 void lookup_interface_method_stub(Register recv_klass,
1043 Register holder_klass,
1044 Register resolved_klass,
1045 Register method_result,
1046 Register temp_reg,
1047 Register temp_reg2,
1048 int itable_index,
1049 Label& L_no_such_interface);
1050
1051 // virtual method calling
1052 // n.b. x86 allows RegisterOrConstant for vtable_index
1053 void lookup_virtual_method(Register recv_klass,
1054 RegisterOrConstant vtable_index,
1055 Register method_result);
1056
1057 // Test sub_klass against super_klass, with fast and slow paths.
1058
1059 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1060 // One of the three labels can be null, meaning take the fall-through.
1061 // If super_check_offset is -1, the value is loaded up from super_klass.
1062 // No registers are killed, except temp_reg.
1063 void check_klass_subtype_fast_path(Register sub_klass,
1064 Register super_klass,
1065 Register temp_reg,
1066 Label* L_success,
1067 Label* L_failure,
1068 Label* L_slow_path,
1069 Register super_check_offset = noreg);
1070
1071 // The rest of the type check; must be wired to a corresponding fast path.
1072 // It does not repeat the fast path logic, so don't use it standalone.
1073 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1074 // Updates the sub's secondary super cache as necessary.
1075 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1076 void check_klass_subtype_slow_path(Register sub_klass,
1077 Register super_klass,
1078 Register temp_reg,
1079 Register temp2_reg,
1080 Label* L_success,
1081 Label* L_failure,
1082 bool set_cond_codes = false);
1083
1084 void check_klass_subtype_slow_path_linear(Register sub_klass,
1085 Register super_klass,
1086 Register temp_reg,
1087 Register temp2_reg,
1088 Label* L_success,
1089 Label* L_failure,
1090 bool set_cond_codes = false);
1091
1092 void check_klass_subtype_slow_path_table(Register sub_klass,
1093 Register super_klass,
1094 Register temp_reg,
1095 Register temp2_reg,
1096 Register temp3_reg,
1097 Register result_reg,
1098 FloatRegister vtemp_reg,
1099 Label* L_success,
1100 Label* L_failure,
1101 bool set_cond_codes = false);
1102
1103 // If r is valid, return r.
1104 // If r is invalid, remove a register r2 from available_regs, add r2
1105 // to regs_to_push, then return r2.
1106 Register allocate_if_noreg(const Register r,
1107 RegSetIterator<Register> &available_regs,
1108 RegSet ®s_to_push);
1109
1110 // Secondary subtype checking
1111 void lookup_secondary_supers_table_var(Register sub_klass,
1112 Register r_super_klass,
1113 Register temp1,
1114 Register temp2,
1115 Register temp3,
1116 FloatRegister vtemp,
1117 Register result,
1118 Label *L_success);
1119
1120
1121 // As above, but with a constant super_klass.
1122 // The result is in Register result, not the condition codes.
1123 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1124 Register r_super_klass,
1125 Register temp1,
1126 Register temp2,
1127 Register temp3,
1128 FloatRegister vtemp,
1129 Register result,
1130 u1 super_klass_slot,
1131 bool stub_is_near = false);
1132
1133 void verify_secondary_supers_table(Register r_sub_klass,
1134 Register r_super_klass,
1135 Register temp1,
1136 Register temp2,
1137 Register result);
1138
1139 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1140 Register r_array_base,
1141 Register r_array_index,
1142 Register r_bitmap,
1143 Register temp1,
1144 Register result,
1145 bool is_stub = true);
1146
1147 // Simplified, combined version, good for typical uses.
1148 // Falls through on failure.
1149 void check_klass_subtype(Register sub_klass,
1150 Register super_klass,
1151 Register temp_reg,
1152 Label& L_success);
1153
1154 void clinit_barrier(Register klass,
1155 Register thread,
1156 Label* L_fast_path = nullptr,
1157 Label* L_slow_path = nullptr);
1158
1159 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1160
1161 void profile_receiver_type(Register recv, Register mdp, int mdp_offset);
1162
1163 void verify_sve_vector_length(Register tmp = rscratch1);
1164 void reinitialize_ptrue() {
1165 if (UseSVE > 0) {
1166 sve_ptrue(ptrue, B);
1167 }
1168 }
1169 void verify_ptrue();
1170
1171 // Debugging
1172
1173 // only if +VerifyOops
1174 void _verify_oop(Register reg, const char* s, const char* file, int line);
1175 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1176
1177 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1178 if (VerifyOops) {
1179 _verify_oop(reg, s, file, line);
1180 }
1181 }
1182 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1183 if (VerifyOops) {
1184 _verify_oop_addr(reg, s, file, line);
1185 }
1186 }
1187
1188 // TODO: verify method and klass metadata (compare against vptr?)
1189 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1190 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1191
1192 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1193 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1194 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1195 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1196 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1197
1198 // Restore cpu control state after JNI call
1199 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1200
1201 // prints msg, dumps registers and stops execution
1202 void stop(const char* msg);
1203
1204 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1205
1206 void untested() { stop("untested"); }
1207
1208 void unimplemented(const char* what = "");
1209
1210 void should_not_reach_here() { stop("should not reach here"); }
1211
1212 void _assert_asm(Condition cc, const char* msg);
1213 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1214 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1215
1216 // Stack overflow checking
1217 void bang_stack_with_offset(int offset) {
1218 // stack grows down, caller passes positive offset
1219 assert(offset > 0, "must bang with negative offset");
1220 sub(rscratch2, sp, offset);
1221 str(zr, Address(rscratch2));
1222 }
1223
1224 // Writes to stack successive pages until offset reached to check for
1225 // stack overflow + shadow pages. Also, clobbers tmp
1226 void bang_stack_size(Register size, Register tmp);
1227
1228 // Check for reserved stack access in method being exited (for JIT)
1229 void reserved_stack_check();
1230
1231 // Arithmetics
1232
1233 // Clobber: rscratch1, rscratch2
1234 void addptr(const Address &dst, int32_t src);
1235
1236 // Clobber: rscratch1
1237 void cmpptr(Register src1, Address src2);
1238
1239 void cmpoop(Register obj1, Register obj2);
1240
1241 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1242 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1243 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1244 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1245
1246 void atomic_xchg(Register prev, Register newv, Register addr);
1247 void atomic_xchgw(Register prev, Register newv, Register addr);
1248 void atomic_xchgl(Register prev, Register newv, Register addr);
1249 void atomic_xchglw(Register prev, Register newv, Register addr);
1250 void atomic_xchgal(Register prev, Register newv, Register addr);
1251 void atomic_xchgalw(Register prev, Register newv, Register addr);
1252
1253 void orptr(Address adr, RegisterOrConstant src) {
1254 ldr(rscratch1, adr);
1255 if (src.is_register())
1256 orr(rscratch1, rscratch1, src.as_register());
1257 else
1258 orr(rscratch1, rscratch1, src.as_constant());
1259 str(rscratch1, adr);
1260 }
1261
1262 // A generic CAS; success or failure is in the EQ flag.
1263 // Clobbers rscratch1
1264 void cmpxchg(Register addr, Register expected, Register new_val,
1265 enum operand_size size,
1266 bool acquire, bool release, bool weak,
1267 Register result);
1268
1269 #ifdef ASSERT
1270 // Template short-hand support to clean-up after a failed call to trampoline
1271 // call generation (see trampoline_call() below), when a set of Labels must
1272 // be reset (before returning).
1273 template<typename Label, typename... More>
1274 void reset_labels(Label &lbl, More&... more) {
1275 lbl.reset(); reset_labels(more...);
1276 }
1277 template<typename Label>
1278 void reset_labels(Label &lbl) {
1279 lbl.reset();
1280 }
1281 #endif
1282
1283 private:
1284 void compare_eq(Register rn, Register rm, enum operand_size size);
1285
1286 public:
1287 // AArch64 OpenJDK uses four different types of calls:
1288 // - direct call: bl pc_relative_offset
1289 // This is the shortest and the fastest, but the offset has the range:
1290 // +/-128MB for the release build, +/-2MB for the debug build.
1291 //
1292 // - far call: adrp reg, pc_relative_offset; add; bl reg
1293 // This is longer than a direct call. The offset has
1294 // the range +/-4GB. As the code cache size is limited to 4GB,
1295 // far calls can reach anywhere in the code cache. If a jump is
1296 // needed rather than a call, a far jump 'b reg' can be used instead.
1297 // All instructions are embedded at a call site.
1298 //
1299 // - trampoline call:
1300 // This is only available in C1/C2-generated code (nmethod). It is a combination
1301 // of a direct call, which is used if the destination of a call is in range,
1302 // and a register-indirect call. It has the advantages of reaching anywhere in
1303 // the AArch64 address space and being patchable at runtime when the generated
1304 // code is being executed by other threads.
1305 //
1306 // [Main code section]
1307 // bl trampoline
1308 // [Stub code section]
1309 // trampoline:
1310 // ldr reg, pc + 8
1311 // br reg
1312 // <64-bit destination address>
1313 //
1314 // If the destination is in range when the generated code is moved to the code
1315 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1316 // is not used.
1317 // The optimization does not remove the trampoline from the stub section.
1318 // This is necessary because the trampoline may well be redirected later when
1319 // code is patched, and the new destination may not be reachable by a simple BR
1320 // instruction.
1321 //
1322 // - indirect call: move reg, address; blr reg
1323 // This too can reach anywhere in the address space, but it cannot be
1324 // patched while code is running, so it must only be modified at a safepoint.
1325 // This form of call is most suitable for targets at fixed addresses, which
1326 // will never be patched.
1327 //
1328 // The patching we do conforms to the "Concurrent modification and
1329 // execution of instructions" section of the Arm Architectural
1330 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1331 // or SVC instructions to be modified while another thread is
1332 // executing them.
1333 //
1334 // To patch a trampoline call when the BL can't reach, we first modify
1335 // the 64-bit destination address in the trampoline, then modify the
1336 // BL to point to the trampoline, then flush the instruction cache to
1337 // broadcast the change to all executing threads. See
1338 // NativeCall::set_destination_mt_safe for the details.
1339 //
1340 // There is a benign race in that the other thread might observe the
1341 // modified BL before it observes the modified 64-bit destination
1342 // address. That does not matter because the destination method has been
1343 // invalidated, so there will be a trap at its start.
1344 // For this to work, the destination address in the trampoline is
1345 // always updated, even if we're not using the trampoline.
1346
1347 // Emit a direct call if the entry address will always be in range,
1348 // otherwise a trampoline call.
1349 // Supported entry.rspec():
1350 // - relocInfo::runtime_call_type
1351 // - relocInfo::opt_virtual_call_type
1352 // - relocInfo::static_call_type
1353 // - relocInfo::virtual_call_type
1354 //
1355 // Return: the call PC or null if CodeCache is full.
1356 // Clobbers: rscratch1
1357 address trampoline_call(Address entry);
1358
1359 static bool far_branches() {
1360 return ReservedCodeCacheSize > branch_range;
1361 }
1362
1363 // Check if branches to the non nmethod section require a far jump
1364 static bool codestub_branch_needs_far_jump() {
1365 if (AOTCodeCache::is_on_for_dump()) {
1366 // To calculate far_codestub_branch_size correctly.
1367 return true;
1368 }
1369 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1370 }
1371
1372 // Emit a direct call/jump if the entry address will always be in range,
1373 // otherwise a far call/jump.
1374 // The address must be inside the code cache.
1375 // Supported entry.rspec():
1376 // - relocInfo::external_word_type
1377 // - relocInfo::runtime_call_type
1378 // - relocInfo::none
1379 // In the case of a far call/jump, the entry address is put in the tmp register.
1380 // The tmp register is invalidated.
1381 //
1382 // Far_jump returns the amount of the emitted code.
1383 void far_call(Address entry, Register tmp = rscratch1);
1384 int far_jump(Address entry, Register tmp = rscratch1);
1385
1386 static int far_codestub_branch_size() {
1387 if (codestub_branch_needs_far_jump()) {
1388 return 3 * 4; // adrp, add, br
1389 } else {
1390 return 4;
1391 }
1392 }
1393
1394 // Emit the CompiledIC call idiom
1395 address ic_call(address entry, jint method_index = 0);
1396 static int ic_check_size();
1397 int ic_check(int end_alignment);
1398
1399 public:
1400
1401 // Data
1402
1403 void mov_metadata(Register dst, Metadata* obj);
1404 Address allocate_metadata_address(Metadata* obj);
1405 Address constant_oop_address(jobject obj);
1406
1407 void movoop(Register dst, jobject obj);
1408
1409 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1410 void kernel_crc32(Register crc, Register buf, Register len,
1411 Register table0, Register table1, Register table2, Register table3,
1412 Register tmp, Register tmp2, Register tmp3);
1413 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1414 void kernel_crc32c(Register crc, Register buf, Register len,
1415 Register table0, Register table1, Register table2, Register table3,
1416 Register tmp, Register tmp2, Register tmp3);
1417
1418 // Stack push and pop individual 64 bit registers
1419 void push(Register src);
1420 void pop(Register dst);
1421
1422 void repne_scan(Register addr, Register value, Register count,
1423 Register scratch);
1424 void repne_scanw(Register addr, Register value, Register count,
1425 Register scratch);
1426
1427 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1428 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1429
1430 // If a constant does not fit in an immediate field, generate some
1431 // number of MOV instructions and then perform the operation
1432 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1433 add_sub_imm_insn insn1,
1434 add_sub_reg_insn insn2, bool is32);
1435 // Separate vsn which sets the flags
1436 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1437 add_sub_imm_insn insn1,
1438 add_sub_reg_insn insn2, bool is32);
1439
1440 #define WRAP(INSN, is32) \
1441 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1442 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1443 } \
1444 \
1445 void INSN(Register Rd, Register Rn, Register Rm, \
1446 enum shift_kind kind, unsigned shift = 0) { \
1447 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1448 } \
1449 \
1450 void INSN(Register Rd, Register Rn, Register Rm) { \
1451 Assembler::INSN(Rd, Rn, Rm); \
1452 } \
1453 \
1454 void INSN(Register Rd, Register Rn, Register Rm, \
1455 ext::operation option, int amount = 0) { \
1456 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1457 }
1458
1459 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1460
1461 #undef WRAP
1462 #define WRAP(INSN, is32) \
1463 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1464 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1465 } \
1466 \
1467 void INSN(Register Rd, Register Rn, Register Rm, \
1468 enum shift_kind kind, unsigned shift = 0) { \
1469 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1470 } \
1471 \
1472 void INSN(Register Rd, Register Rn, Register Rm) { \
1473 Assembler::INSN(Rd, Rn, Rm); \
1474 } \
1475 \
1476 void INSN(Register Rd, Register Rn, Register Rm, \
1477 ext::operation option, int amount = 0) { \
1478 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1479 }
1480
1481 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1482
1483 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1484 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1485 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1486 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1487
1488 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1489
1490 void verified_entry(Compile* C, int sp_inc);
1491
1492 // Inline type specific methods
1493 #include "asm/macroAssembler_common.hpp"
1494
1495 void save_stack_increment(int sp_inc, int frame_size);
1496
1497 void tableswitch(Register index, jint lowbound, jint highbound,
1498 Label &jumptable, Label &jumptable_end, int stride = 1) {
1499 adr(rscratch1, jumptable);
1500 subsw(rscratch2, index, lowbound);
1501 subsw(zr, rscratch2, highbound - lowbound);
1502 br(Assembler::HS, jumptable_end);
1503 add(rscratch1, rscratch1, rscratch2,
1504 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1505 br(rscratch1);
1506 }
1507
1508 // Form an address from base + offset in Rd. Rd may or may not
1509 // actually be used: you must use the Address that is returned. It
1510 // is up to you to ensure that the shift provided matches the size
1511 // of your data.
1512 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1513
1514 // Return true iff an address is within the 48-bit AArch64 address
1515 // space.
1516 bool is_valid_AArch64_address(address a) {
1517 return ((uint64_t)a >> 48) == 0;
1518 }
1519
1520 // Load the base of the cardtable byte map into reg.
1521 void load_byte_map_base(Register reg);
1522
1523 // Load a constant address in the AOT Runtime Constants area
1524 void load_aotrc_address(Register reg, address a);
1525
1526 // Prolog generator routines to support switch between x86 code and
1527 // generated ARM code
1528
1529 // routine to generate an x86 prolog for a stub function which
1530 // bootstraps into the generated ARM code which directly follows the
1531 // stub
1532 //
1533
1534 public:
1535
1536 address read_polling_page(Register r, relocInfo::relocType rtype);
1537 void get_polling_page(Register dest, relocInfo::relocType rtype);
1538
1539 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1540 void update_byte_crc32(Register crc, Register val, Register table);
1541 void update_word_crc32(Register crc, Register v, Register tmp,
1542 Register table0, Register table1, Register table2, Register table3,
1543 bool upper = false);
1544
1545 address count_positives(Register ary1, Register len, Register result);
1546
1547 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1548 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1549
1550 // Ensure that the inline code and the stub use the same registers.
1551 #define ARRAYS_HASHCODE_REGISTERS \
1552 do { \
1553 assert(result == r0 && \
1554 ary == r1 && \
1555 cnt == r2 && \
1556 vdata0 == v3 && \
1557 vdata1 == v2 && \
1558 vdata2 == v1 && \
1559 vdata3 == v0 && \
1560 vmul0 == v4 && \
1561 vmul1 == v5 && \
1562 vmul2 == v6 && \
1563 vmul3 == v7 && \
1564 vpow == v12 && \
1565 vpowm == v13, "registers must match aarch64.ad"); \
1566 } while (0)
1567
1568 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1569
1570 void fill_words(Register base, Register cnt, Register value);
1571 void fill_words(Register base, uint64_t cnt, Register value);
1572
1573 address zero_words(Register base, uint64_t cnt);
1574 address zero_words(Register ptr, Register cnt);
1575 void zero_dcache_blocks(Register base, Register cnt);
1576
1577 static const int zero_words_block_size;
1578
1579 address byte_array_inflate(Register src, Register dst, Register len,
1580 FloatRegister vtmp1, FloatRegister vtmp2,
1581 FloatRegister vtmp3, Register tmp4);
1582
1583 void char_array_compress(Register src, Register dst, Register len,
1584 Register res,
1585 FloatRegister vtmp0, FloatRegister vtmp1,
1586 FloatRegister vtmp2, FloatRegister vtmp3,
1587 FloatRegister vtmp4, FloatRegister vtmp5);
1588
1589 void encode_iso_array(Register src, Register dst,
1590 Register len, Register res, bool ascii,
1591 FloatRegister vtmp0, FloatRegister vtmp1,
1592 FloatRegister vtmp2, FloatRegister vtmp3,
1593 FloatRegister vtmp4, FloatRegister vtmp5);
1594
1595 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1596 address pio2, address dsin_coef, address dcos_coef);
1597 private:
1598 // begin trigonometric functions support block
1599 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1600 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1601 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1602 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1603 // end trigonometric functions support block
1604 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1605 Register src1, Register src2);
1606 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1607 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1608 }
1609 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1610 Register y, Register y_idx, Register z,
1611 Register carry, Register product,
1612 Register idx, Register kdx);
1613 void multiply_128_x_128_loop(Register y, Register z,
1614 Register carry, Register carry2,
1615 Register idx, Register jdx,
1616 Register yz_idx1, Register yz_idx2,
1617 Register tmp, Register tmp3, Register tmp4,
1618 Register tmp7, Register product_hi);
1619 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1620 Register len, Register tmp0, Register tmp1, Register tmp2,
1621 Register tmp3);
1622 void kernel_crc32_using_crc32(Register crc, Register buf,
1623 Register len, Register tmp0, Register tmp1, Register tmp2,
1624 Register tmp3);
1625 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1626 Register len, Register tmp0, Register tmp1, Register tmp2,
1627 Register tmp3);
1628 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1629 Register len, Register tmp0, Register tmp1, Register tmp2,
1630 Register tmp3);
1631 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1632 Register len, Register tmp0, Register tmp1, Register tmp2,
1633 size_t table_offset);
1634
1635 void ghash_modmul (FloatRegister result,
1636 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1637 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1638 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1639 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1640 public:
1641 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1642 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1643 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1644 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1645 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1646 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1647 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1648 void ghash_multiply_wide(int index,
1649 FloatRegister result_lo, FloatRegister result_hi,
1650 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1651 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1652 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1653 FloatRegister p, FloatRegister z, FloatRegister t1);
1654 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1655 FloatRegister p, FloatRegister z, FloatRegister t1);
1656 void ghash_processBlocks_wide(Label& p, Register state, Register subkeyH,
1657 Register data, Register blocks, int unrolls);
1658
1659
1660 void aesenc_loadkeys(Register key, Register keylen);
1661 void aesecb_encrypt(Register from, Register to, Register keylen,
1662 FloatRegister data = v0, int unrolls = 1);
1663 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1664 void aes_round(FloatRegister input, FloatRegister subkey);
1665
1666 // ChaCha20 functions support block
1667 void cc20_qr_add4(FloatRegister (&addFirst)[4],
1668 FloatRegister (&addSecond)[4]);
1669 void cc20_qr_xor4(FloatRegister (&firstElem)[4],
1670 FloatRegister (&secondElem)[4], FloatRegister (&result)[4]);
1671 void cc20_qr_lrot4(FloatRegister (&sourceReg)[4],
1672 FloatRegister (&destReg)[4], int bits, FloatRegister table);
1673 void cc20_set_qr_registers(FloatRegister (&vectorSet)[4],
1674 const FloatRegister (&stateVectors)[16], int idx1, int idx2,
1675 int idx3, int idx4);
1676
1677 // Rotate using ORR (for identity) or USHR + SLI.
1678 void neon_vector_rotate(FloatRegister dst, SIMD_Arrangement T,
1679 FloatRegister src, int shift_amount);
1680
1681 // Place an ISB after code may have been modified due to a safepoint.
1682 void safepoint_isb();
1683
1684 private:
1685 // Return the effective address r + (r1 << ext) + offset.
1686 // Uses rscratch2.
1687 Address offsetted_address(Register r, Register r1, Address::extend ext,
1688 int offset, int size);
1689
1690 private:
1691 // Returns an address on the stack which is reachable with a ldr/str of size
1692 // Uses rscratch2 if the address is not directly reachable
1693 Address spill_address(int size, int offset, Register tmp=rscratch2);
1694 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1695
1696 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1697
1698 // Check whether two loads/stores can be merged into ldp/stp.
1699 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1700
1701 // Merge current load/store with previous load/store into ldp/stp.
1702 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1703
1704 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1705 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1706
1707 public:
1708 void spill(Register Rx, bool is64, int offset) {
1709 if (is64) {
1710 str(Rx, spill_address(8, offset));
1711 } else {
1712 strw(Rx, spill_address(4, offset));
1713 }
1714 }
1715 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1716 str(Vx, T, spill_address(1 << (int)T, offset));
1717 }
1718
1719 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1720 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1721 }
1722 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1723 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1724 }
1725
1726 void unspill(Register Rx, bool is64, int offset) {
1727 if (is64) {
1728 ldr(Rx, spill_address(8, offset));
1729 } else {
1730 ldrw(Rx, spill_address(4, offset));
1731 }
1732 }
1733 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1734 ldr(Vx, T, spill_address(1 << (int)T, offset));
1735 }
1736
1737 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1738 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1739 }
1740 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1741 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1742 }
1743
1744 void spill_copy128(int src_offset, int dst_offset,
1745 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1746 if (src_offset < 512 && (src_offset & 7) == 0 &&
1747 dst_offset < 512 && (dst_offset & 7) == 0) {
1748 ldp(tmp1, tmp2, Address(sp, src_offset));
1749 stp(tmp1, tmp2, Address(sp, dst_offset));
1750 } else {
1751 unspill(tmp1, true, src_offset);
1752 spill(tmp1, true, dst_offset);
1753 unspill(tmp1, true, src_offset+8);
1754 spill(tmp1, true, dst_offset+8);
1755 }
1756 }
1757 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1758 int sve_vec_reg_size_in_bytes) {
1759 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1760 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1761 spill_copy128(src_offset, dst_offset);
1762 src_offset += 16;
1763 dst_offset += 16;
1764 }
1765 }
1766 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1767 int sve_predicate_reg_size_in_bytes) {
1768 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1769 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1770 reinitialize_ptrue();
1771 }
1772 void cache_wb(Address line);
1773 void cache_wbsync(bool is_pre);
1774
1775 // Code for java.lang.Thread::onSpinWait() intrinsic.
1776 void spin_wait();
1777 void spin_wait_wfet(int delay_ns);
1778
1779 void fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1780 void fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1781
1782 private:
1783 // Check the current thread doesn't need a cross modify fence.
1784 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1785 void try_to_replace_prev_vector_copy_with_movprfx(FloatRegister dst);
1786
1787 public:
1788 void maybe_movprfx(FloatRegister dst, FloatRegister src) {
1789 if (dst != src) {
1790 sve_movprfx(dst, src);
1791 }
1792 }
1793
1794 // Wrappers for SVE explicit destructive instructions, overriding the
1795 // same-signature Assembler entry points to enable movprfx fusion optimization.
1796 //
1797 // Implicit destructive instructions (e.g. predicated unary ops like sve_abs/
1798 // sve_neg/sve_not, whose ISA encoding allows Zd != Zn but whose use as a Java
1799 // Vector API masked operation requires pass-through of the first source) are
1800 // not covered here. For those, the .ad file is responsible for emitting
1801 // movprfx explicitly via maybe_movprfx() before the destructive op.
1802 #define SVE_DESTRUCTIVE_BINARY_INS(NAME) \
1803 using Assembler::NAME; \
1804 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, \
1805 FloatRegister Zm) { \
1806 if (Zd != Zm) { \
1807 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1808 } \
1809 Assembler::NAME(Zd, T, Pg, Zm); \
1810 }
1811
1812 #define SVE_DESTRUCTIVE_BINARY_5(I1, I2, I3, I4, I5) \
1813 SVE_DESTRUCTIVE_BINARY_INS(I1); SVE_DESTRUCTIVE_BINARY_INS(I2); \
1814 SVE_DESTRUCTIVE_BINARY_INS(I3); SVE_DESTRUCTIVE_BINARY_INS(I4); \
1815 SVE_DESTRUCTIVE_BINARY_INS(I5);
1816
1817 SVE_DESTRUCTIVE_BINARY_5(sve_add, sve_and, sve_asr, sve_bic, sve_eor)
1818 SVE_DESTRUCTIVE_BINARY_5(sve_fabd, sve_fadd, sve_fdiv, sve_fmax, sve_fmin)
1819 SVE_DESTRUCTIVE_BINARY_5(sve_fmul, sve_fsub, sve_lsl, sve_lsr, sve_mul)
1820 SVE_DESTRUCTIVE_BINARY_5(sve_orr, sve_smax, sve_smin, sve_sqadd, sve_sqsub)
1821 SVE_DESTRUCTIVE_BINARY_5(sve_sub, sve_uqadd, sve_uqsub, sve_umax, sve_umin)
1822
1823 #undef SVE_DESTRUCTIVE_BINARY_INS
1824 #undef SVE_DESTRUCTIVE_BINARY_5
1825
1826 #define SVE_DESTRUCTIVE_SHIFT_IMM_INS(NAME) \
1827 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, int shift) { \
1828 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1829 Assembler::NAME(Zd, T, Pg, shift); \
1830 }
1831
1832 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_asr);
1833 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_lsl);
1834 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_lsr);
1835
1836 #undef SVE_DESTRUCTIVE_SHIFT_IMM_INS
1837
1838 #define SVE_DESTRUCTIVE_UNPRED_IMM_INS(NAME, IMM_TYPE) \
1839 void NAME(FloatRegister Zd, SIMD_RegVariant T, IMM_TYPE imm) { \
1840 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1841 Assembler::NAME(Zd, T, imm); \
1842 }
1843
1844 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_add, unsigned);
1845 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_sub, unsigned);
1846 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_and, uint64_t);
1847 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_eor, uint64_t);
1848 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_orr, uint64_t);
1849
1850 #undef SVE_DESTRUCTIVE_UNPRED_IMM_INS
1851
1852 #define SVE_DESTRUCTIVE_TERNARY_INS(NAME) \
1853 using Assembler::NAME; \
1854 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, \
1855 FloatRegister Zn, FloatRegister Zm) { \
1856 if (Zd != Zn && Zd != Zm) { \
1857 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1858 } \
1859 Assembler::NAME(Zd, T, Pg, Zn, Zm); \
1860 }
1861
1862 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmad);
1863 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmla);
1864 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmls);
1865 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmsb);
1866 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmad);
1867 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmla);
1868 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmls);
1869 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmsb);
1870 SVE_DESTRUCTIVE_TERNARY_INS(sve_mla);
1871 SVE_DESTRUCTIVE_TERNARY_INS(sve_mls);
1872
1873 #undef SVE_DESTRUCTIVE_TERNARY_INS
1874
1875 using Assembler::sve_eor3;
1876 void sve_eor3(FloatRegister Zd, FloatRegister Zm, FloatRegister Zk) {
1877 if (Zd != Zm && Zd != Zk) {
1878 try_to_replace_prev_vector_copy_with_movprfx(Zd);
1879 }
1880 Assembler::sve_eor3(Zd, Zm, Zk);
1881 }
1882 };
1883
1884 #ifdef ASSERT
1885 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1886 #endif
1887
1888 struct tableswitch {
1889 Register _reg;
1890 int _insn_index; jint _first_key; jint _last_key;
1891 Label _after;
1892 Label _branches;
1893 };
1894
1895 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP