1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/atomicAccess.hpp"
36 #include "runtime/vm_version.hpp"
37 #include "utilities/globalDefinitions.hpp"
38 #include "utilities/macros.hpp"
39 #include "utilities/powerOfTwo.hpp"
40 #include "runtime/signature.hpp"
41
42
43 class ciInlineKlass;
44
45 class OopMap;
46
47 // MacroAssembler extends Assembler by frequently used macros.
48 //
49 // Instructions for which a 'better' code sequence exists depending
50 // on arguments should also go in here.
51
52 class MacroAssembler: public Assembler {
53 friend class LIR_Assembler;
54
55 public:
56 using Assembler::mov;
57 using Assembler::movi;
58
59 protected:
60
61 // Support for VM calls
62 //
63 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
64 // may customize this version by overriding it for its purposes (e.g., to save/restore
65 // additional registers when doing a VM call).
66 virtual void call_VM_leaf_base(
67 address entry_point, // the entry point
68 int number_of_arguments, // the number of arguments to pop after the call
69 Label *retaddr = nullptr
70 );
71
72 virtual void call_VM_leaf_base(
73 address entry_point, // the entry point
74 int number_of_arguments, // the number of arguments to pop after the call
75 Label &retaddr) {
76 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
77 }
78
79 // This is the base routine called by the different versions of call_VM. The interpreter
80 // may customize this version by overriding it for its purposes (e.g., to save/restore
81 // additional registers when doing a VM call).
82 //
83 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
84 // returns the register which contains the thread upon return. If a thread register has been
85 // specified, the return value will correspond to that register. If no last_java_sp is specified
86 // (noreg) than rsp will be used instead.
87 virtual void call_VM_base( // returns the register containing the thread upon return
88 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
89 Register java_thread, // the thread if computed before ; use noreg otherwise
90 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
91 Label* return_pc, // to set up last_Java_frame; use nullptr otherwise
92 address entry_point, // the entry point
93 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
94 bool check_exceptions // whether to check for pending exceptions after return
95 );
96
97 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
98
99 enum KlassDecodeMode {
100 KlassDecodeNone,
101 KlassDecodeZero,
102 KlassDecodeXor,
103 KlassDecodeMovk
104 };
105
106 // Calculate decoding mode based on given parameters, used for checking then ultimately setting.
107 static KlassDecodeMode klass_decode_mode(address base, int shift, const size_t range);
108
109 private:
110 static KlassDecodeMode _klass_decode_mode;
111
112 // Returns above setting with asserts
113 static KlassDecodeMode klass_decode_mode();
114
115 public:
116 // Checks the decode mode and returns false if not compatible with preferred decoding mode.
117 static bool check_klass_decode_mode(address base, int shift, const size_t range);
118
119 // Sets the decode mode and returns false if cannot be set.
120 static bool set_klass_decode_mode(address base, int shift, const size_t range);
121
122 public:
123 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
124
125 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
126 // The implementation is only non-empty for the InterpreterMacroAssembler,
127 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
128 virtual void check_and_handle_popframe(Register java_thread);
129 virtual void check_and_handle_earlyret(Register java_thread);
130
131 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp = rscratch1);
132 void rt_call(address dest, Register tmp = rscratch1);
133
134 // Load Effective Address
135 void lea(Register r, const Address &a) {
136 InstructionMark im(this);
137 a.lea(this, r);
138 }
139
140 // Whether materializing the given address for a LDR/STR requires an
141 // additional lea instruction.
142 static bool legitimize_address_requires_lea(const Address &a, int size) {
143 return a.getMode() == Address::base_plus_offset &&
144 !Address::offset_ok_for_immed(a.offset(), exact_log2(size));
145 }
146
147 /* Sometimes we get misaligned loads and stores, usually from Unsafe
148 accesses, and these can exceed the offset range. */
149 Address legitimize_address(const Address &a, int size, Register scratch) {
150 if (legitimize_address_requires_lea(a, size)) {
151 block_comment("legitimize_address {");
152 lea(scratch, a);
153 block_comment("} legitimize_address");
154 return Address(scratch);
155 }
156 return a;
157 }
158
159 void addmw(Address a, Register incr, Register scratch) {
160 ldrw(scratch, a);
161 addw(scratch, scratch, incr);
162 strw(scratch, a);
163 }
164
165 // Add constant to memory word
166 void addmw(Address a, int imm, Register scratch) {
167 ldrw(scratch, a);
168 if (imm > 0)
169 addw(scratch, scratch, (unsigned)imm);
170 else
171 subw(scratch, scratch, (unsigned)-imm);
172 strw(scratch, a);
173 }
174
175 void bind(Label& L) {
176 Assembler::bind(L);
177 code()->clear_last_merge_candidate();
178 code()->set_last_label(pc());
179 }
180
181 void membar(Membar_mask_bits order_constraint);
182
183 using Assembler::ldr;
184 using Assembler::str;
185 using Assembler::ldrw;
186 using Assembler::strw;
187
188 void ldr(Register Rx, const Address &adr);
189 void ldrw(Register Rw, const Address &adr);
190 void str(Register Rx, const Address &adr);
191 void strw(Register Rx, const Address &adr);
192
193 // Frame creation and destruction shared between JITs.
194 DEBUG_ONLY(void build_frame(int framesize);)
195 void build_frame(int framesize DEBUG_ONLY(COMMA bool zap_rfp_lr_spills));
196 void remove_frame(int framesize);
197
198 virtual void _call_Unimplemented(address call_site) {
199 mov(rscratch2, call_site);
200 }
201
202 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
203 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
204 // https://reviews.llvm.org/D3311
205
206 #ifdef _WIN64
207 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
208 #else
209 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
210 #endif
211
212 // aliases defined in AARCH64 spec
213
214 template<class T>
215 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
216
217 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
218 inline void cmp(Register Rd, unsigned imm) = delete;
219
220 template<class T>
221 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
222
223 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
224 inline void cmn(Register Rd, unsigned imm) = delete;
225
226 void cset(Register Rd, Assembler::Condition cond) {
227 csinc(Rd, zr, zr, ~cond);
228 }
229 void csetw(Register Rd, Assembler::Condition cond) {
230 csincw(Rd, zr, zr, ~cond);
231 }
232
233 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
234 csneg(Rd, Rn, Rn, ~cond);
235 }
236 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
237 csnegw(Rd, Rn, Rn, ~cond);
238 }
239
240 inline void movw(Register Rd, Register Rn) {
241 if (Rd == sp || Rn == sp) {
242 Assembler::addw(Rd, Rn, 0U);
243 } else {
244 orrw(Rd, zr, Rn);
245 }
246 }
247 inline void mov(Register Rd, Register Rn) {
248 assert(Rd != r31_sp && Rn != r31_sp, "should be");
249 if (Rd == Rn) {
250 } else if (Rd == sp || Rn == sp) {
251 Assembler::add(Rd, Rn, 0U);
252 } else {
253 orr(Rd, zr, Rn);
254 }
255 }
256
257 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
258 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
259
260 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
261 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
262
263 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
264 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
265
266 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
267 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
268 }
269 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
270 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
271 }
272
273 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
274 bfmw(Rd, Rn, lsb, (lsb + width - 1));
275 }
276 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
277 bfm(Rd, Rn, lsb , (lsb + width - 1));
278 }
279
280 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
281 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
282 }
283 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
284 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
285 }
286
287 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
288 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
289 }
290 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
291 sbfm(Rd, Rn, lsb , (lsb + width - 1));
292 }
293
294 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
295 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
296 }
297 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
298 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
299 }
300
301 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
302 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
303 }
304 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
305 ubfm(Rd, Rn, lsb , (lsb + width - 1));
306 }
307
308 inline void asrw(Register Rd, Register Rn, unsigned imm) {
309 sbfmw(Rd, Rn, imm, 31);
310 }
311
312 inline void asr(Register Rd, Register Rn, unsigned imm) {
313 sbfm(Rd, Rn, imm, 63);
314 }
315
316 inline void lslw(Register Rd, Register Rn, unsigned imm) {
317 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
318 }
319
320 inline void lsl(Register Rd, Register Rn, unsigned imm) {
321 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
322 }
323
324 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
325 ubfmw(Rd, Rn, imm, 31);
326 }
327
328 inline void lsr(Register Rd, Register Rn, unsigned imm) {
329 ubfm(Rd, Rn, imm, 63);
330 }
331
332 inline void rorw(Register Rd, Register Rn, unsigned imm) {
333 extrw(Rd, Rn, Rn, imm);
334 }
335
336 inline void ror(Register Rd, Register Rn, unsigned imm) {
337 extr(Rd, Rn, Rn, imm);
338 }
339
340 inline void rolw(Register Rd, Register Rn, unsigned imm) {
341 extrw(Rd, Rn, Rn, (32 - imm));
342 }
343
344 inline void rol(Register Rd, Register Rn, unsigned imm) {
345 extr(Rd, Rn, Rn, (64 - imm));
346 }
347
348 using Assembler::rax1;
349 using Assembler::eor3;
350
351 inline void rax1(Register Rd, Register Rn, Register Rm) {
352 eor(Rd, Rn, Rm, ROR, 63); // Rd = Rn ^ rol(Rm, 1)
353 }
354
355 inline void eor3(Register Rd, Register Rn, Register Rm, Register Rk) {
356 assert(Rd != Rn, "Use tmp register");
357 eor(Rd, Rm, Rk);
358 eor(Rd, Rd, Rn);
359 }
360
361 inline void sxtbw(Register Rd, Register Rn) {
362 sbfmw(Rd, Rn, 0, 7);
363 }
364 inline void sxthw(Register Rd, Register Rn) {
365 sbfmw(Rd, Rn, 0, 15);
366 }
367 inline void sxtb(Register Rd, Register Rn) {
368 sbfm(Rd, Rn, 0, 7);
369 }
370 inline void sxth(Register Rd, Register Rn) {
371 sbfm(Rd, Rn, 0, 15);
372 }
373 inline void sxtw(Register Rd, Register Rn) {
374 sbfm(Rd, Rn, 0, 31);
375 }
376
377 inline void uxtbw(Register Rd, Register Rn) {
378 ubfmw(Rd, Rn, 0, 7);
379 }
380 inline void uxthw(Register Rd, Register Rn) {
381 ubfmw(Rd, Rn, 0, 15);
382 }
383 inline void uxtb(Register Rd, Register Rn) {
384 ubfm(Rd, Rn, 0, 7);
385 }
386 inline void uxth(Register Rd, Register Rn) {
387 ubfm(Rd, Rn, 0, 15);
388 }
389 inline void uxtw(Register Rd, Register Rn) {
390 ubfm(Rd, Rn, 0, 31);
391 }
392
393 inline void cmnw(Register Rn, Register Rm) {
394 addsw(zr, Rn, Rm);
395 }
396 inline void cmn(Register Rn, Register Rm) {
397 adds(zr, Rn, Rm);
398 }
399
400 inline void cmpw(Register Rn, Register Rm) {
401 subsw(zr, Rn, Rm);
402 }
403 inline void cmp(Register Rn, Register Rm) {
404 subs(zr, Rn, Rm);
405 }
406
407 inline void negw(Register Rd, Register Rn) {
408 subw(Rd, zr, Rn);
409 }
410
411 inline void neg(Register Rd, Register Rn) {
412 sub(Rd, zr, Rn);
413 }
414
415 inline void negsw(Register Rd, Register Rn) {
416 subsw(Rd, zr, Rn);
417 }
418
419 inline void negs(Register Rd, Register Rn) {
420 subs(Rd, zr, Rn);
421 }
422
423 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
424 addsw(zr, Rn, Rm, kind, shift);
425 }
426 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
427 adds(zr, Rn, Rm, kind, shift);
428 }
429
430 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
431 subsw(zr, Rn, Rm, kind, shift);
432 }
433 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
434 subs(zr, Rn, Rm, kind, shift);
435 }
436
437 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
438 subw(Rd, zr, Rn, kind, shift);
439 }
440
441 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
442 sub(Rd, zr, Rn, kind, shift);
443 }
444
445 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
446 subsw(Rd, zr, Rn, kind, shift);
447 }
448
449 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
450 subs(Rd, zr, Rn, kind, shift);
451 }
452
453 inline void mnegw(Register Rd, Register Rn, Register Rm) {
454 msubw(Rd, Rn, Rm, zr);
455 }
456 inline void mneg(Register Rd, Register Rn, Register Rm) {
457 msub(Rd, Rn, Rm, zr);
458 }
459
460 inline void mulw(Register Rd, Register Rn, Register Rm) {
461 maddw(Rd, Rn, Rm, zr);
462 }
463 inline void mul(Register Rd, Register Rn, Register Rm) {
464 madd(Rd, Rn, Rm, zr);
465 }
466
467 inline void smnegl(Register Rd, Register Rn, Register Rm) {
468 smsubl(Rd, Rn, Rm, zr);
469 }
470 inline void smull(Register Rd, Register Rn, Register Rm) {
471 smaddl(Rd, Rn, Rm, zr);
472 }
473
474 inline void umnegl(Register Rd, Register Rn, Register Rm) {
475 umsubl(Rd, Rn, Rm, zr);
476 }
477 inline void umull(Register Rd, Register Rn, Register Rm) {
478 umaddl(Rd, Rn, Rm, zr);
479 }
480
481 #define WRAP(INSN) \
482 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
483 if (VM_Version::supports_a53mac() && Ra != zr) \
484 nop(); \
485 Assembler::INSN(Rd, Rn, Rm, Ra); \
486 }
487
488 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
489 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
490 #undef WRAP
491
492 using Assembler::andw, Assembler::andr;
493 void andw(Register Rd, Register Rn, uint64_t imm) {
494 if (operand_valid_for_logical_immediate(/*is32*/true, imm)) {
495 Assembler::andw(Rd, Rn, imm);
496 } else {
497 assert(Rd != Rn, "must be");
498 movw(Rd, imm);
499 andw(Rd, Rn, Rd);
500 }
501 }
502 void andr(Register Rd, Register Rn, uint64_t imm) {
503 if (operand_valid_for_logical_immediate(/*is32*/false, imm)) {
504 Assembler::andr(Rd, Rn, imm);
505 } else {
506 assert(Rd != Rn, "must be");
507 mov(Rd, imm);
508 andr(Rd, Rn, Rd);
509 }
510 }
511
512 // macro assembly operations needed for aarch64
513
514 public:
515
516 enum FpPushPopMode {
517 PushPopFull,
518 PushPopSVE,
519 PushPopNeon,
520 PushPopFp
521 };
522
523 // first two private routines for loading 32 bit or 64 bit constants
524 private:
525
526 void mov_immediate64(Register dst, uint64_t imm64);
527 void mov_immediate32(Register dst, uint32_t imm32);
528
529 void mov(Register dst, Address a);
530
531 public:
532
533 int push(RegSet regset, Register stack);
534 int pop(RegSet regset, Register stack);
535
536 int push_fp(FloatRegSet regset, Register stack, FpPushPopMode mode = PushPopFull);
537 int pop_fp(FloatRegSet regset, Register stack, FpPushPopMode mode = PushPopFull);
538
539 static RegSet call_clobbered_gp_registers();
540
541 int push_p(PRegSet regset, Register stack);
542 int pop_p(PRegSet regset, Register stack);
543
544 // Push and pop everything that might be clobbered by a native
545 // runtime call except rscratch1 and rscratch2. (They are always
546 // scratch, so we don't have to protect them.) Only save the lower
547 // 64 bits of each vector register. Additional registers can be excluded
548 // in a passed RegSet.
549 void push_call_clobbered_registers_except(RegSet exclude);
550 void pop_call_clobbered_registers_except(RegSet exclude);
551
552 void push_call_clobbered_registers() {
553 push_call_clobbered_registers_except(RegSet());
554 }
555 void pop_call_clobbered_registers() {
556 pop_call_clobbered_registers_except(RegSet());
557 }
558
559
560 // now mov instructions for loading absolute addresses and 32 or
561 // 64 bit integers
562
563 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
564
565 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
566 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
567
568 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
569
570 void mov(Register dst, RegisterOrConstant src) {
571 if (src.is_register())
572 mov(dst, src.as_register());
573 else
574 mov(dst, src.as_constant());
575 }
576
577 void movptr(Register r, uintptr_t imm64);
578
579 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
580
581 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
582 orr(Vd, T, Vn, Vn);
583 }
584
585 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
586 fcvtsh(tmp, src);
587 smov(dst, tmp, H, 0);
588 }
589
590 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
591 mov(tmp, H, 0, src);
592 fcvths(dst, tmp);
593 }
594
595 // Generalized Test Bit And Branch, including a "far" variety which
596 // spans more than 32KiB.
597 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
598 assert(cond == EQ || cond == NE, "must be");
599
600 if (isfar)
601 cond = ~cond;
602
603 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
604 if (cond == Assembler::EQ)
605 branch = &Assembler::tbz;
606 else
607 branch = &Assembler::tbnz;
608
609 if (isfar) {
610 Label L;
611 (this->*branch)(Rt, bitpos, L);
612 b(dest);
613 bind(L);
614 } else {
615 (this->*branch)(Rt, bitpos, dest);
616 }
617 }
618
619 // macro instructions for accessing and updating floating point
620 // status register
621 //
622 // FPSR : op1 == 011
623 // CRn == 0100
624 // CRm == 0100
625 // op2 == 001
626
627 inline void get_fpsr(Register reg)
628 {
629 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
630 }
631
632 inline void set_fpsr(Register reg)
633 {
634 msr(0b011, 0b0100, 0b0100, 0b001, reg);
635 }
636
637 inline void clear_fpsr()
638 {
639 msr(0b011, 0b0100, 0b0100, 0b001, zr);
640 }
641
642 // FPCR : op1 == 011
643 // CRn == 0100
644 // CRm == 0100
645 // op2 == 000
646
647 inline void get_fpcr(Register reg) {
648 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
649 }
650
651 inline void set_fpcr(Register reg) {
652 msr(0b011, 0b0100, 0b0100, 0b000, reg);
653 }
654
655 // DCZID_EL0: op1 == 011
656 // CRn == 0000
657 // CRm == 0000
658 // op2 == 111
659 inline void get_dczid_el0(Register reg)
660 {
661 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
662 }
663
664 // CTR_EL0: op1 == 011
665 // CRn == 0000
666 // CRm == 0000
667 // op2 == 001
668 inline void get_ctr_el0(Register reg)
669 {
670 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
671 }
672
673 inline void get_nzcv(Register reg) {
674 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
675 }
676
677 inline void set_nzcv(Register reg) {
678 msr(0b011, 0b0100, 0b0010, 0b000, reg);
679 }
680
681 // CNTVCTSS_EL0: op1 == 011
682 // CRn == 1110
683 // CRm == 0000
684 // op2 == 110
685 inline void get_cntvctss_el0(Register reg) {
686 mrs(0b011, 0b1110, 0b0000, 0b110, reg);
687 }
688
689 // idiv variant which deals with MINLONG as dividend and -1 as divisor
690 int corrected_idivl(Register result, Register ra, Register rb,
691 bool want_remainder, Register tmp = rscratch1);
692 int corrected_idivq(Register result, Register ra, Register rb,
693 bool want_remainder, Register tmp = rscratch1);
694
695 // Support for null-checks
696 //
697 // Generates code that causes a null OS exception if the content of reg is null.
698 // If the accessed location is M[reg + offset] and the offset is known, provide the
699 // offset. No explicit code generation is needed if the offset is within a certain
700 // range (0 <= offset <= page_size).
701
702 virtual void null_check(Register reg, int offset = -1);
703 static bool needs_explicit_null_check(intptr_t offset);
704 static bool uses_implicit_null_check(void* address);
705
706 // markWord tests, kills markWord reg
707 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
708
709 // inlineKlass queries, kills temp_reg
710 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
711
712 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
713 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
714 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
715
716 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
717 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
718 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
719 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
720 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
721 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
722
723 // Check array klass layout helper for flat or null-free arrays...
724 void test_flat_array_layout(Register lh, Label& is_flat_array);
725
726 static address target_addr_for_insn(address insn_addr);
727
728 // Required platform-specific helpers for Label::patch_instructions.
729 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
730 static int pd_patch_instruction_size(address branch, address target);
731 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
732 pd_patch_instruction_size(branch, target);
733 }
734 static address pd_call_destination(address branch) {
735 return target_addr_for_insn(branch);
736 }
737 #ifndef PRODUCT
738 static void pd_print_patched_instruction(address branch);
739 #endif
740
741 static int patch_oop(address insn_addr, address o);
742
743 // Return whether code is emitted to a scratch blob.
744 virtual bool in_scratch_emit_size() {
745 return false;
746 }
747 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
748 static int max_trampoline_stub_size();
749 void emit_static_call_stub();
750 static int static_call_stub_size();
751
752 // The following 4 methods return the offset of the appropriate move instruction
753
754 // Support for fast byte/short loading with zero extension (depending on particular CPU)
755 int load_unsigned_byte(Register dst, Address src);
756 int load_unsigned_short(Register dst, Address src);
757
758 // Support for fast byte/short loading with sign extension (depending on particular CPU)
759 int load_signed_byte(Register dst, Address src);
760 int load_signed_short(Register dst, Address src);
761
762 int load_signed_byte32(Register dst, Address src);
763 int load_signed_short32(Register dst, Address src);
764
765 // Support for sign-extension (hi:lo = extend_sign(lo))
766 void extend_sign(Register hi, Register lo);
767
768 // Clean up a subword typed value to the representation in compliance with JVMS ยง2.3
769 void narrow_subword_type(Register reg, BasicType bt);
770
771 // Load and store values by size and signed-ness
772 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
773 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
774
775 // Support for inc/dec with optimal instruction selection depending on value
776
777 // x86_64 aliases an unqualified register/address increment and
778 // decrement to call incrementq and decrementq but also supports
779 // explicitly sized calls to incrementq/decrementq or
780 // incrementl/decrementl
781
782 // for aarch64 the proper convention would be to use
783 // increment/decrement for 64 bit operations and
784 // incrementw/decrementw for 32 bit operations. so when porting
785 // x86_64 code we can leave calls to increment/decrement as is,
786 // replace incrementq/decrementq with increment/decrement and
787 // replace incrementl/decrementl with incrementw/decrementw.
788
789 // n.b. increment/decrement calls with an Address destination will
790 // need to use a scratch register to load the value to be
791 // incremented. increment/decrement calls which add or subtract a
792 // constant value greater than 2^24 will need to use a 2nd scratch
793 // register to hold the constant. so, a register increment/decrement
794 // may trash rscratch2 and an address increment/decrement trash
795 // rscratch and rscratch2
796
797 void decrementw(Address dst, int value = 1);
798 void decrementw(Register reg, int value = 1);
799
800 void decrement(Register reg, int value = 1);
801 void decrement(Address dst, int value = 1);
802
803 void incrementw(Address dst, int value = 1, Register result = rscratch1);
804 void incrementw(Register reg, int value = 1);
805
806 void increment(Register reg, int value = 1);
807 void increment(Address dst, int value = 1, Register result = rscratch1);
808
809
810 // Alignment
811 void align(int modulus);
812 void align(int modulus, int target);
813
814 // nop
815 void post_call_nop();
816
817 // Stack frame creation/removal
818 void enter(bool strip_ret_addr = false);
819 void leave();
820
821 // ROP Protection
822 void protect_return_address();
823 void protect_return_address(Register return_reg);
824 void authenticate_return_address();
825 void authenticate_return_address(Register return_reg);
826 void strip_return_address();
827 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
828
829 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
830 // The pointer will be loaded into the thread register.
831 void get_thread(Register thread);
832
833 // support for argument shuffling
834 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
835 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
836 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
837 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
838 void object_move(
839 OopMap* map,
840 int oop_handle_offset,
841 int framesize_in_slots,
842 VMRegPair src,
843 VMRegPair dst,
844 bool is_receiver,
845 int* receiver_offset);
846
847
848 // Support for VM calls
849 //
850 // It is imperative that all calls into the VM are handled via the call_VM macros.
851 // They make sure that the stack linkage is setup correctly. call_VM's correspond
852 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
853
854
855 void call_VM(Register oop_result,
856 address entry_point,
857 bool check_exceptions = true);
858 void call_VM(Register oop_result,
859 address entry_point,
860 Register arg_1,
861 bool check_exceptions = true);
862 void call_VM(Register oop_result,
863 address entry_point,
864 Register arg_1, Register arg_2,
865 bool check_exceptions = true);
866 void call_VM(Register oop_result,
867 address entry_point,
868 Register arg_1, Register arg_2, Register arg_3,
869 bool check_exceptions = true);
870
871 // Overloadings with last_Java_sp
872 void call_VM(Register oop_result,
873 Register last_java_sp,
874 address entry_point,
875 int number_of_arguments = 0,
876 bool check_exceptions = true);
877 void call_VM(Register oop_result,
878 Register last_java_sp,
879 address entry_point,
880 Register arg_1, bool
881 check_exceptions = true);
882 void call_VM(Register oop_result,
883 Register last_java_sp,
884 address entry_point,
885 Register arg_1, Register arg_2,
886 bool check_exceptions = true);
887 void call_VM(Register oop_result,
888 Register last_java_sp,
889 address entry_point,
890 Register arg_1, Register arg_2, Register arg_3,
891 bool check_exceptions = true);
892
893 void get_vm_result_oop(Register oop_result, Register thread);
894 void get_vm_result_metadata(Register metadata_result, Register thread);
895
896 // These always tightly bind to MacroAssembler::call_VM_base
897 // bypassing the virtual implementation
898 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
899 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
900 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
901 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
902 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
903
904 void call_VM_leaf(address entry_point,
905 int number_of_arguments = 0);
906 void call_VM_leaf(address entry_point,
907 Register arg_1);
908 void call_VM_leaf(address entry_point,
909 Register arg_1, Register arg_2);
910 void call_VM_leaf(address entry_point,
911 Register arg_1, Register arg_2, Register arg_3);
912
913 // These always tightly bind to MacroAssembler::call_VM_leaf_base
914 // bypassing the virtual implementation
915 void super_call_VM_leaf(address entry_point);
916 void super_call_VM_leaf(address entry_point, Register arg_1);
917 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
918 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
919 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
920
921 // last Java Frame (fills frame anchor)
922 void set_last_Java_frame(Register last_java_sp,
923 Register last_java_fp,
924 address last_java_pc,
925 Register scratch);
926
927 void set_last_Java_frame(Register last_java_sp,
928 Register last_java_fp,
929 Label &last_java_pc,
930 Register scratch);
931
932 void set_last_Java_frame(Register last_java_sp,
933 Register last_java_fp,
934 Register last_java_pc,
935 Register scratch);
936
937 void reset_last_Java_frame(Register thread);
938
939 // thread in the default location (rthread)
940 void reset_last_Java_frame(bool clear_fp);
941
942 void resolve_jobject(Register value, Register tmp1, Register tmp2);
943 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
944
945 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
946 void c2bool(Register x);
947
948 void load_method_holder_cld(Register rresult, Register rmethod);
949 void load_method_holder(Register holder, Register method);
950
951 // oop manipulations
952 void load_metadata(Register dst, Register src);
953
954 void load_narrow_klass_compact(Register dst, Register src);
955 void load_klass(Register dst, Register src);
956 void store_klass(Register dst, Register src);
957 void cmp_klass(Register obj, Register klass, Register tmp);
958 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
959
960 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
961 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
962 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
963
964 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
965 Register tmp1, Register tmp2);
966
967 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
968 Register tmp1, Register tmp2, Register tmp3);
969
970 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
971
972 // inline type data payload offsets...
973 void payload_offset(Register inline_klass, Register offset);
974 void payload_address(Register oop, Register data, Register inline_klass);
975
976 void load_heap_oop(Register dst, Address src, Register tmp1,
977 Register tmp2, DecoratorSet decorators = 0);
978
979 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
980 Register tmp2, DecoratorSet decorators = 0);
981 void store_heap_oop(Address dst, Register val, Register tmp1,
982 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
983
984 // currently unimplemented
985 // Used for storing null. All other oop constants should be
986 // stored using routines that take a jobject.
987 void store_heap_oop_null(Address dst);
988
989 void load_prototype_header(Register dst, Register src);
990
991 void store_klass_gap(Register dst, Register src);
992
993 // This dummy is to prevent a call to store_heap_oop from
994 // converting a zero (like null) into a Register by giving
995 // the compiler two choices it can't resolve
996
997 void store_heap_oop(Address dst, void* dummy);
998
999 void encode_heap_oop(Register d, Register s);
1000 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
1001 void decode_heap_oop(Register d, Register s);
1002 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
1003 void encode_heap_oop_not_null(Register r);
1004 void decode_heap_oop_not_null(Register r);
1005 void encode_heap_oop_not_null(Register dst, Register src);
1006 void decode_heap_oop_not_null(Register dst, Register src);
1007
1008 void set_narrow_oop(Register dst, jobject obj);
1009
1010 void decode_klass_not_null_for_aot(Register dst, Register src);
1011 void encode_klass_not_null_for_aot(Register dst, Register src);
1012 void encode_klass_not_null(Register r);
1013 void decode_klass_not_null(Register r);
1014 void encode_klass_not_null(Register dst, Register src);
1015 void decode_klass_not_null(Register dst, Register src);
1016
1017 void set_narrow_klass(Register dst, Klass* k);
1018
1019 // if heap base register is used - reinit it with the correct value
1020 void reinit_heapbase();
1021
1022 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1023
1024 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
1025 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1026 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
1027 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1028
1029 void push_cont_fastpath(Register java_thread = rthread);
1030 void pop_cont_fastpath(Register java_thread = rthread);
1031
1032 // Round up to a power of two
1033 void round_to(Register reg, int modulus);
1034
1035 // java.lang.Math::round intrinsics
1036 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1037 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1038
1039 // allocation
1040
1041 void tlab_allocate(
1042 Register obj, // result: pointer to object after successful allocation
1043 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1044 int con_size_in_bytes, // object size in bytes if known at compile time
1045 Register t1, // temp register
1046 Register t2, // temp register
1047 Label& slow_case // continuation point if fast allocation fails
1048 );
1049 void verify_tlab();
1050
1051 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
1052
1053 // interface method calling
1054 void lookup_interface_method(Register recv_klass,
1055 Register intf_klass,
1056 RegisterOrConstant itable_index,
1057 Register method_result,
1058 Register scan_temp,
1059 Label& no_such_interface,
1060 bool return_method = true);
1061
1062 void lookup_interface_method_stub(Register recv_klass,
1063 Register holder_klass,
1064 Register resolved_klass,
1065 Register method_result,
1066 Register temp_reg,
1067 Register temp_reg2,
1068 int itable_index,
1069 Label& L_no_such_interface);
1070
1071 // virtual method calling
1072 // n.b. x86 allows RegisterOrConstant for vtable_index
1073 void lookup_virtual_method(Register recv_klass,
1074 RegisterOrConstant vtable_index,
1075 Register method_result);
1076
1077 // Test sub_klass against super_klass, with fast and slow paths.
1078
1079 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1080 // One of the three labels can be null, meaning take the fall-through.
1081 // If super_check_offset is -1, the value is loaded up from super_klass.
1082 // No registers are killed, except temp_reg.
1083 void check_klass_subtype_fast_path(Register sub_klass,
1084 Register super_klass,
1085 Register temp_reg,
1086 Label* L_success,
1087 Label* L_failure,
1088 Label* L_slow_path,
1089 Register super_check_offset = noreg);
1090
1091 // The rest of the type check; must be wired to a corresponding fast path.
1092 // It does not repeat the fast path logic, so don't use it standalone.
1093 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1094 // Updates the sub's secondary super cache as necessary.
1095 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1096 void check_klass_subtype_slow_path(Register sub_klass,
1097 Register super_klass,
1098 Register temp_reg,
1099 Register temp2_reg,
1100 Label* L_success,
1101 Label* L_failure,
1102 bool set_cond_codes = false);
1103
1104 void check_klass_subtype_slow_path_linear(Register sub_klass,
1105 Register super_klass,
1106 Register temp_reg,
1107 Register temp2_reg,
1108 Label* L_success,
1109 Label* L_failure,
1110 bool set_cond_codes = false);
1111
1112 void check_klass_subtype_slow_path_table(Register sub_klass,
1113 Register super_klass,
1114 Register temp_reg,
1115 Register temp2_reg,
1116 Register temp3_reg,
1117 Register result_reg,
1118 FloatRegister vtemp_reg,
1119 Label* L_success,
1120 Label* L_failure,
1121 bool set_cond_codes = false);
1122
1123 // If r is valid, return r.
1124 // If r is invalid, remove a register r2 from available_regs, add r2
1125 // to regs_to_push, then return r2.
1126 Register allocate_if_noreg(const Register r,
1127 RegSetIterator<Register> &available_regs,
1128 RegSet ®s_to_push);
1129
1130 // Secondary subtype checking
1131 void lookup_secondary_supers_table_var(Register sub_klass,
1132 Register r_super_klass,
1133 Register temp1,
1134 Register temp2,
1135 Register temp3,
1136 FloatRegister vtemp,
1137 Register result,
1138 Label *L_success);
1139
1140
1141 // As above, but with a constant super_klass.
1142 // The result is in Register result, not the condition codes.
1143 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1144 Register r_super_klass,
1145 Register temp1,
1146 Register temp2,
1147 Register temp3,
1148 FloatRegister vtemp,
1149 Register result,
1150 u1 super_klass_slot,
1151 bool stub_is_near = false);
1152
1153 void verify_secondary_supers_table(Register r_sub_klass,
1154 Register r_super_klass,
1155 Register temp1,
1156 Register temp2,
1157 Register result);
1158
1159 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1160 Register r_array_base,
1161 Register r_array_index,
1162 Register r_bitmap,
1163 Register temp1,
1164 Register result,
1165 bool is_stub = true);
1166
1167 // Simplified, combined version, good for typical uses.
1168 // Falls through on failure.
1169 void check_klass_subtype(Register sub_klass,
1170 Register super_klass,
1171 Register temp_reg,
1172 Label& L_success);
1173
1174 void clinit_barrier(Register klass,
1175 Register thread,
1176 Label* L_fast_path = nullptr,
1177 Label* L_slow_path = nullptr);
1178
1179 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1180
1181 void profile_receiver_type(Register recv, Register mdp, int mdp_offset);
1182
1183 void verify_sve_vector_length(Register tmp = rscratch1);
1184 void reinitialize_ptrue() {
1185 if (UseSVE > 0) {
1186 sve_ptrue(ptrue, B);
1187 }
1188 }
1189 void verify_ptrue();
1190
1191 // Debugging
1192
1193 // only if +VerifyOops
1194 void _verify_oop(Register reg, const char* s, const char* file, int line);
1195 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1196
1197 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1198 if (VerifyOops) {
1199 _verify_oop(reg, s, file, line);
1200 }
1201 }
1202 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1203 if (VerifyOops) {
1204 _verify_oop_addr(reg, s, file, line);
1205 }
1206 }
1207
1208 // TODO: verify method and klass metadata (compare against vptr?)
1209 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1210 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1211
1212 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1213 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1214 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1215 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1216 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1217
1218 // Restore cpu control state after JNI call
1219 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1220
1221 // prints msg, dumps registers and stops execution
1222 void stop(const char* msg);
1223
1224 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1225
1226 void untested() { stop("untested"); }
1227
1228 void unimplemented(const char* what = "");
1229
1230 void should_not_reach_here() { stop("should not reach here"); }
1231
1232 void _assert_asm(Condition cc, const char* msg);
1233 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1234 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1235
1236 // Stack overflow checking
1237 void bang_stack_with_offset(int offset) {
1238 // stack grows down, caller passes positive offset
1239 assert(offset > 0, "must bang with negative offset");
1240 sub(rscratch2, sp, offset);
1241 str(zr, Address(rscratch2));
1242 }
1243
1244 // Writes to stack successive pages until offset reached to check for
1245 // stack overflow + shadow pages. Also, clobbers tmp
1246 void bang_stack_size(Register size, Register tmp);
1247
1248 // Check for reserved stack access in method being exited (for JIT)
1249 void reserved_stack_check();
1250
1251 // Arithmetics
1252
1253 // Clobber: rscratch1, rscratch2
1254 void addptr(const Address &dst, int32_t src);
1255
1256 // Clobber: rscratch1
1257 void cmpptr(Register src1, Address src2);
1258
1259 void cmpoop(Register obj1, Register obj2);
1260
1261 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1262 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1263 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1264 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1265
1266 void atomic_xchg(Register prev, Register newv, Register addr);
1267 void atomic_xchgw(Register prev, Register newv, Register addr);
1268 void atomic_xchgl(Register prev, Register newv, Register addr);
1269 void atomic_xchglw(Register prev, Register newv, Register addr);
1270 void atomic_xchgal(Register prev, Register newv, Register addr);
1271 void atomic_xchgalw(Register prev, Register newv, Register addr);
1272
1273 void orptr(Address adr, RegisterOrConstant src) {
1274 ldr(rscratch1, adr);
1275 if (src.is_register())
1276 orr(rscratch1, rscratch1, src.as_register());
1277 else
1278 orr(rscratch1, rscratch1, src.as_constant());
1279 str(rscratch1, adr);
1280 }
1281
1282 private:
1283 // A generic CAS; success or failure is in the EQ flag.
1284 // Clobbers rscratch1
1285 void cmpxchg(Register addr, Register expected, Register new_val,
1286 enum operand_size size, enum atomic_memory_order order,
1287 bool weak, Register result);
1288
1289 public:
1290 void cmpxchg(Register addr, Register expected, Register new_val,
1291 enum operand_size size, enum atomic_memory_order order,
1292 Register result = noreg) {
1293 cmpxchg(addr, expected, new_val, size, order, /* weak */ false, result);
1294 }
1295
1296 void cmpxchg_weak(Register addr, Register expected, Register new_val,
1297 enum operand_size size, enum atomic_memory_order order,
1298 Register result = noreg) {
1299 cmpxchg(addr, expected, new_val, size, order, /* weak */ true, result);
1300 }
1301
1302 #ifdef ASSERT
1303 // Template short-hand support to clean-up after a failed call to trampoline
1304 // call generation (see trampoline_call() below), when a set of Labels must
1305 // be reset (before returning).
1306 template<typename Label, typename... More>
1307 void reset_labels(Label &lbl, More&... more) {
1308 lbl.reset(); reset_labels(more...);
1309 }
1310 template<typename Label>
1311 void reset_labels(Label &lbl) {
1312 lbl.reset();
1313 }
1314 #endif
1315
1316 private:
1317 void compare_eq(Register rn, Register rm, enum operand_size size);
1318
1319 public:
1320 // AArch64 OpenJDK uses four different types of calls:
1321 // - direct call: bl pc_relative_offset
1322 // This is the shortest and the fastest, but the offset has the range:
1323 // +/-128MB for the release build, +/-2MB for the debug build.
1324 //
1325 // - far call: adrp reg, pc_relative_offset; add; bl reg
1326 // This is longer than a direct call. The offset has
1327 // the range +/-4GB. As the code cache size is limited to 4GB,
1328 // far calls can reach anywhere in the code cache. If a jump is
1329 // needed rather than a call, a far jump 'b reg' can be used instead.
1330 // All instructions are embedded at a call site.
1331 //
1332 // - trampoline call:
1333 // This is only available in C1/C2-generated code (nmethod). It is a combination
1334 // of a direct call, which is used if the destination of a call is in range,
1335 // and a register-indirect call. It has the advantages of reaching anywhere in
1336 // the AArch64 address space and being patchable at runtime when the generated
1337 // code is being executed by other threads.
1338 //
1339 // [Main code section]
1340 // bl trampoline
1341 // [Stub code section]
1342 // trampoline:
1343 // ldr reg, pc + 8
1344 // br reg
1345 // <64-bit destination address>
1346 //
1347 // If the destination is in range when the generated code is moved to the code
1348 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1349 // is not used.
1350 // The optimization does not remove the trampoline from the stub section.
1351 // This is necessary because the trampoline may well be redirected later when
1352 // code is patched, and the new destination may not be reachable by a simple BR
1353 // instruction.
1354 //
1355 // - indirect call: move reg, address; blr reg
1356 // This too can reach anywhere in the address space, but it cannot be
1357 // patched while code is running, so it must only be modified at a safepoint.
1358 // This form of call is most suitable for targets at fixed addresses, which
1359 // will never be patched.
1360 //
1361 // The patching we do conforms to the "Concurrent modification and
1362 // execution of instructions" section of the Arm Architectural
1363 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1364 // or SVC instructions to be modified while another thread is
1365 // executing them.
1366 //
1367 // To patch a trampoline call when the BL can't reach, we first modify
1368 // the 64-bit destination address in the trampoline, then modify the
1369 // BL to point to the trampoline, then flush the instruction cache to
1370 // broadcast the change to all executing threads. See
1371 // NativeCall::set_destination_mt_safe for the details.
1372 //
1373 // There is a benign race in that the other thread might observe the
1374 // modified BL before it observes the modified 64-bit destination
1375 // address. That does not matter because the destination method has been
1376 // invalidated, so there will be a trap at its start.
1377 // For this to work, the destination address in the trampoline is
1378 // always updated, even if we're not using the trampoline.
1379
1380 // Emit a direct call if the entry address will always be in range,
1381 // otherwise a trampoline call.
1382 // Supported entry.rspec():
1383 // - relocInfo::runtime_call_type
1384 // - relocInfo::opt_virtual_call_type
1385 // - relocInfo::static_call_type
1386 // - relocInfo::virtual_call_type
1387 //
1388 // Return: the call PC or null if CodeCache is full.
1389 // Clobbers: rscratch1
1390 address trampoline_call(Address entry);
1391
1392 static bool far_branches() {
1393 return ReservedCodeCacheSize > branch_range;
1394 }
1395
1396 // Check if branches to the non nmethod section require a far jump
1397 static bool codestub_branch_needs_far_jump() {
1398 if (AOTCodeCache::is_on_for_dump()) {
1399 // To calculate far_codestub_branch_size correctly.
1400 return true;
1401 }
1402 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1403 }
1404
1405 // Emit a direct call/jump if the entry address will always be in range,
1406 // otherwise a far call/jump.
1407 // The address must be inside the code cache.
1408 // Supported entry.rspec():
1409 // - relocInfo::external_word_type
1410 // - relocInfo::runtime_call_type
1411 // - relocInfo::none
1412 // In the case of a far call/jump, the entry address is put in the tmp register.
1413 // The tmp register is invalidated.
1414 //
1415 // Far_jump returns the amount of the emitted code.
1416 void far_call(Address entry, Register tmp = rscratch1);
1417 int far_jump(Address entry, Register tmp = rscratch1);
1418
1419 static int far_codestub_branch_size() {
1420 if (codestub_branch_needs_far_jump()) {
1421 return 3 * 4; // adrp, add, br
1422 } else {
1423 return 4;
1424 }
1425 }
1426
1427 // Emit the CompiledIC call idiom
1428 address ic_call(address entry, jint method_index = 0);
1429 static int ic_check_size();
1430 int ic_check(int end_alignment);
1431
1432 public:
1433
1434 // Data
1435
1436 void mov_metadata(Register dst, Metadata* obj);
1437 Address allocate_metadata_address(Metadata* obj);
1438 Address constant_oop_address(jobject obj);
1439
1440 void movoop(Register dst, jobject obj);
1441
1442 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1443 void kernel_crc32(Register crc, Register buf, Register len,
1444 Register table0, Register table1, Register table2, Register table3,
1445 Register tmp, Register tmp2, Register tmp3);
1446 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1447 void kernel_crc32c(Register crc, Register buf, Register len,
1448 Register table0, Register table1, Register table2, Register table3,
1449 Register tmp, Register tmp2, Register tmp3);
1450
1451 // Stack push and pop individual 64 bit registers
1452 void push(Register src);
1453 void pop(Register dst);
1454
1455 void repne_scan(Register addr, Register value, Register count,
1456 Register scratch);
1457 void repne_scanw(Register addr, Register value, Register count,
1458 Register scratch);
1459
1460 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1461 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1462
1463 // If a constant does not fit in an immediate field, generate some
1464 // number of MOV instructions and then perform the operation
1465 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1466 add_sub_imm_insn insn1,
1467 add_sub_reg_insn insn2, bool is32);
1468 // Separate vsn which sets the flags
1469 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1470 add_sub_imm_insn insn1,
1471 add_sub_reg_insn insn2, bool is32);
1472
1473 #define WRAP(INSN, is32) \
1474 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1475 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1476 } \
1477 \
1478 void INSN(Register Rd, Register Rn, Register Rm, \
1479 enum shift_kind kind, unsigned shift = 0) { \
1480 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1481 } \
1482 \
1483 void INSN(Register Rd, Register Rn, Register Rm) { \
1484 Assembler::INSN(Rd, Rn, Rm); \
1485 } \
1486 \
1487 void INSN(Register Rd, Register Rn, Register Rm, \
1488 ext::operation option, int amount = 0) { \
1489 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1490 }
1491
1492 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1493
1494 #undef WRAP
1495 #define WRAP(INSN, is32) \
1496 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1497 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1498 } \
1499 \
1500 void INSN(Register Rd, Register Rn, Register Rm, \
1501 enum shift_kind kind, unsigned shift = 0) { \
1502 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1503 } \
1504 \
1505 void INSN(Register Rd, Register Rn, Register Rm) { \
1506 Assembler::INSN(Rd, Rn, Rm); \
1507 } \
1508 \
1509 void INSN(Register Rd, Register Rn, Register Rm, \
1510 ext::operation option, int amount = 0) { \
1511 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1512 }
1513
1514 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1515
1516 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1517 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1518 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1519 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1520
1521 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1522
1523 void verified_entry(Compile* C, int sp_inc);
1524
1525 // Inline type specific methods
1526 #include "asm/macroAssembler_common.hpp"
1527
1528 void save_stack_increment(int sp_inc, int frame_size);
1529
1530 void tableswitch(Register index, jint lowbound, jint highbound,
1531 Label &jumptable, Label &jumptable_end, int stride = 1) {
1532 adr(rscratch1, jumptable);
1533 subsw(rscratch2, index, lowbound);
1534 subsw(zr, rscratch2, highbound - lowbound);
1535 br(Assembler::HS, jumptable_end);
1536 add(rscratch1, rscratch1, rscratch2,
1537 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1538 br(rscratch1);
1539 }
1540
1541 // Form an address from base + offset in Rd. Rd may or may not
1542 // actually be used: you must use the Address that is returned. It
1543 // is up to you to ensure that the shift provided matches the size
1544 // of your data.
1545 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1546
1547 // Return true iff an address is within the 48-bit AArch64 address
1548 // space.
1549 bool is_valid_AArch64_address(address a) {
1550 return ((uint64_t)a >> 48) == 0;
1551 }
1552
1553 // Load the base of the cardtable byte map into reg.
1554 void load_byte_map_base(Register reg);
1555
1556 // Load a constant address in the AOT Runtime Constants area
1557 void load_aotrc_address(Register reg, address a);
1558
1559 // Prolog generator routines to support switch between x86 code and
1560 // generated ARM code
1561
1562 // routine to generate an x86 prolog for a stub function which
1563 // bootstraps into the generated ARM code which directly follows the
1564 // stub
1565 //
1566
1567 public:
1568
1569 address read_polling_page(Register r, relocInfo::relocType rtype);
1570 void get_polling_page(Register dest, relocInfo::relocType rtype);
1571
1572 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1573 void update_byte_crc32(Register crc, Register val, Register table);
1574 void update_word_crc32(Register crc, Register v, Register tmp,
1575 Register table0, Register table1, Register table2, Register table3,
1576 bool upper = false);
1577
1578 address count_positives(Register ary1, Register len, Register result);
1579
1580 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1581 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1582
1583 // Ensure that the inline code and the stub use the same registers.
1584 #define ARRAYS_HASHCODE_REGISTERS \
1585 do { \
1586 assert(result == r0 && \
1587 ary == r1 && \
1588 cnt == r2 && \
1589 vdata0 == v3 && \
1590 vdata1 == v2 && \
1591 vdata2 == v1 && \
1592 vdata3 == v0 && \
1593 vmul0 == v4 && \
1594 vmul1 == v5 && \
1595 vmul2 == v6 && \
1596 vmul3 == v7 && \
1597 vpow == v12 && \
1598 vpowm == v13, "registers must match aarch64.ad"); \
1599 } while (0)
1600
1601 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1602
1603 void fill_words(Register base, Register cnt, Register value);
1604 void fill_words(Register base, uint64_t cnt, Register value);
1605
1606 address zero_words(Register base, uint64_t cnt);
1607 address zero_words(Register ptr, Register cnt);
1608 void zero_dcache_blocks(Register base, Register cnt);
1609
1610 static const int zero_words_block_size;
1611
1612 address byte_array_inflate(Register src, Register dst, Register len,
1613 FloatRegister vtmp1, FloatRegister vtmp2,
1614 FloatRegister vtmp3, Register tmp4);
1615
1616 void char_array_compress(Register src, Register dst, Register len,
1617 Register res,
1618 FloatRegister vtmp0, FloatRegister vtmp1,
1619 FloatRegister vtmp2, FloatRegister vtmp3,
1620 FloatRegister vtmp4, FloatRegister vtmp5);
1621
1622 void encode_iso_array(Register src, Register dst,
1623 Register len, Register res, bool ascii,
1624 FloatRegister vtmp0, FloatRegister vtmp1,
1625 FloatRegister vtmp2, FloatRegister vtmp3,
1626 FloatRegister vtmp4, FloatRegister vtmp5);
1627
1628 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1629 address pio2, address dsin_coef, address dcos_coef);
1630 private:
1631 // begin trigonometric functions support block
1632 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1633 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1634 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1635 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1636 // end trigonometric functions support block
1637 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1638 Register src1, Register src2);
1639 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1640 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1641 }
1642 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1643 Register y, Register y_idx, Register z,
1644 Register carry, Register product,
1645 Register idx, Register kdx);
1646 void multiply_128_x_128_loop(Register y, Register z,
1647 Register carry, Register carry2,
1648 Register idx, Register jdx,
1649 Register yz_idx1, Register yz_idx2,
1650 Register tmp, Register tmp3, Register tmp4,
1651 Register tmp7, Register product_hi);
1652 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1653 Register len, Register tmp0, Register tmp1, Register tmp2,
1654 Register tmp3);
1655 void kernel_crc32_using_crc32(Register crc, Register buf,
1656 Register len, Register tmp0, Register tmp1, Register tmp2,
1657 Register tmp3);
1658 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1659 Register len, Register tmp0, Register tmp1, Register tmp2,
1660 Register tmp3);
1661 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1662 Register len, Register tmp0, Register tmp1, Register tmp2,
1663 Register tmp3);
1664 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1665 Register len, Register tmp0, Register tmp1, Register tmp2,
1666 size_t table_offset);
1667
1668 void ghash_modmul (FloatRegister result,
1669 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1670 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1671 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1672 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1673 public:
1674 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1675 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1676 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1677 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1678 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1679 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1680 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1681 void ghash_multiply_wide(int index,
1682 FloatRegister result_lo, FloatRegister result_hi,
1683 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1684 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1685 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1686 FloatRegister p, FloatRegister z, FloatRegister t1);
1687 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1688 FloatRegister p, FloatRegister z, FloatRegister t1);
1689 void ghash_processBlocks_wide(Label& p, Register state, Register subkeyH,
1690 Register data, Register blocks, int unrolls);
1691
1692
1693 void aesenc_loadkeys(Register key, Register keylen);
1694 void aesecb_encrypt(Register from, Register to, Register keylen,
1695 FloatRegister data = v0, int unrolls = 1);
1696 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1697 void aes_round(FloatRegister input, FloatRegister subkey);
1698
1699 // ChaCha20 functions support block
1700 void cc20_qr_add4(FloatRegister (&addFirst)[4],
1701 FloatRegister (&addSecond)[4]);
1702 void cc20_qr_xor4(FloatRegister (&firstElem)[4],
1703 FloatRegister (&secondElem)[4], FloatRegister (&result)[4]);
1704 void cc20_qr_lrot4(FloatRegister (&sourceReg)[4],
1705 FloatRegister (&destReg)[4], int bits, FloatRegister table);
1706 void cc20_set_qr_registers(FloatRegister (&vectorSet)[4],
1707 const FloatRegister (&stateVectors)[16], int idx1, int idx2,
1708 int idx3, int idx4);
1709
1710 // Rotate using ORR (for identity) or USHR + SLI.
1711 void neon_vector_rotate(FloatRegister dst, SIMD_Arrangement T,
1712 FloatRegister src, int shift_amount);
1713
1714 // Place an ISB after code may have been modified due to a safepoint.
1715 void safepoint_isb();
1716
1717 private:
1718 // Return the effective address r + (r1 << ext) + offset.
1719 // Uses rscratch2.
1720 Address offsetted_address(Register r, Register r1, Address::extend ext,
1721 int offset, int size);
1722
1723 private:
1724 // Returns an address on the stack which is reachable with a ldr/str of size
1725 // Uses rscratch2 if the address is not directly reachable
1726 Address spill_address(int size, int offset, Register tmp=rscratch2);
1727 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1728
1729 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1730
1731 // Check whether two loads/stores can be merged into ldp/stp.
1732 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1733
1734 // Merge current load/store with previous load/store into ldp/stp.
1735 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1736
1737 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1738 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1739
1740 public:
1741 void spill(Register Rx, bool is64, int offset) {
1742 if (is64) {
1743 str(Rx, spill_address(8, offset));
1744 } else {
1745 strw(Rx, spill_address(4, offset));
1746 }
1747 }
1748 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1749 str(Vx, T, spill_address(1 << (int)T, offset));
1750 }
1751
1752 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1753 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1754 }
1755 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1756 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1757 }
1758
1759 void unspill(Register Rx, bool is64, int offset) {
1760 if (is64) {
1761 ldr(Rx, spill_address(8, offset));
1762 } else {
1763 ldrw(Rx, spill_address(4, offset));
1764 }
1765 }
1766 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1767 ldr(Vx, T, spill_address(1 << (int)T, offset));
1768 }
1769
1770 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1771 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1772 }
1773 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1774 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1775 }
1776
1777 void spill_copy128(int src_offset, int dst_offset,
1778 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1779 if (src_offset < 512 && (src_offset & 7) == 0 &&
1780 dst_offset < 512 && (dst_offset & 7) == 0) {
1781 ldp(tmp1, tmp2, Address(sp, src_offset));
1782 stp(tmp1, tmp2, Address(sp, dst_offset));
1783 } else {
1784 unspill(tmp1, true, src_offset);
1785 spill(tmp1, true, dst_offset);
1786 unspill(tmp1, true, src_offset+8);
1787 spill(tmp1, true, dst_offset+8);
1788 }
1789 }
1790 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1791 int sve_vec_reg_size_in_bytes) {
1792 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1793 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1794 spill_copy128(src_offset, dst_offset);
1795 src_offset += 16;
1796 dst_offset += 16;
1797 }
1798 }
1799 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1800 int sve_predicate_reg_size_in_bytes) {
1801 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1802 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1803 reinitialize_ptrue();
1804 }
1805 void cache_wb(Address line);
1806 void cache_wbsync(bool is_pre);
1807
1808 // Code for java.lang.Thread::onSpinWait() intrinsic.
1809 void spin_wait();
1810 void spin_wait_wfet(int delay_ns);
1811
1812 void fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1813 void fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1814
1815 private:
1816 // Check the current thread doesn't need a cross modify fence.
1817 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1818 void try_to_replace_prev_vector_copy_with_movprfx(FloatRegister dst);
1819
1820 public:
1821 void maybe_movprfx(FloatRegister dst, FloatRegister src) {
1822 if (dst != src) {
1823 sve_movprfx(dst, src);
1824 }
1825 }
1826
1827 // Wrappers for SVE explicit destructive instructions, overriding the
1828 // same-signature Assembler entry points to enable movprfx fusion optimization.
1829 //
1830 // Implicit destructive instructions (e.g. predicated unary ops like sve_abs/
1831 // sve_neg/sve_not, whose ISA encoding allows Zd != Zn but whose use as a Java
1832 // Vector API masked operation requires pass-through of the first source) are
1833 // not covered here. For those, the .ad file is responsible for emitting
1834 // movprfx explicitly via maybe_movprfx() before the destructive op.
1835 #define SVE_DESTRUCTIVE_BINARY_INS(NAME) \
1836 using Assembler::NAME; \
1837 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, \
1838 FloatRegister Zm) { \
1839 if (Zd != Zm) { \
1840 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1841 } \
1842 Assembler::NAME(Zd, T, Pg, Zm); \
1843 }
1844
1845 #define SVE_DESTRUCTIVE_BINARY_5(I1, I2, I3, I4, I5) \
1846 SVE_DESTRUCTIVE_BINARY_INS(I1); SVE_DESTRUCTIVE_BINARY_INS(I2); \
1847 SVE_DESTRUCTIVE_BINARY_INS(I3); SVE_DESTRUCTIVE_BINARY_INS(I4); \
1848 SVE_DESTRUCTIVE_BINARY_INS(I5);
1849
1850 SVE_DESTRUCTIVE_BINARY_5(sve_add, sve_and, sve_asr, sve_bic, sve_eor)
1851 SVE_DESTRUCTIVE_BINARY_5(sve_fabd, sve_fadd, sve_fdiv, sve_fmax, sve_fmin)
1852 SVE_DESTRUCTIVE_BINARY_5(sve_fmul, sve_fsub, sve_lsl, sve_lsr, sve_mul)
1853 SVE_DESTRUCTIVE_BINARY_5(sve_orr, sve_smax, sve_smin, sve_sqadd, sve_sqsub)
1854 SVE_DESTRUCTIVE_BINARY_5(sve_sub, sve_uqadd, sve_uqsub, sve_umax, sve_umin)
1855
1856 #undef SVE_DESTRUCTIVE_BINARY_INS
1857 #undef SVE_DESTRUCTIVE_BINARY_5
1858
1859 #define SVE_DESTRUCTIVE_SHIFT_IMM_INS(NAME) \
1860 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, int shift) { \
1861 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1862 Assembler::NAME(Zd, T, Pg, shift); \
1863 }
1864
1865 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_asr);
1866 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_lsl);
1867 SVE_DESTRUCTIVE_SHIFT_IMM_INS(sve_lsr);
1868
1869 #undef SVE_DESTRUCTIVE_SHIFT_IMM_INS
1870
1871 #define SVE_DESTRUCTIVE_UNPRED_IMM_INS(NAME, IMM_TYPE) \
1872 void NAME(FloatRegister Zd, SIMD_RegVariant T, IMM_TYPE imm) { \
1873 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1874 Assembler::NAME(Zd, T, imm); \
1875 }
1876
1877 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_add, unsigned);
1878 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_sub, unsigned);
1879 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_and, uint64_t);
1880 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_eor, uint64_t);
1881 SVE_DESTRUCTIVE_UNPRED_IMM_INS(sve_orr, uint64_t);
1882
1883 #undef SVE_DESTRUCTIVE_UNPRED_IMM_INS
1884
1885 #define SVE_DESTRUCTIVE_TERNARY_INS(NAME) \
1886 using Assembler::NAME; \
1887 void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, \
1888 FloatRegister Zn, FloatRegister Zm) { \
1889 if (Zd != Zn && Zd != Zm) { \
1890 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1891 } \
1892 Assembler::NAME(Zd, T, Pg, Zn, Zm); \
1893 }
1894
1895 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmad);
1896 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmla);
1897 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmls);
1898 SVE_DESTRUCTIVE_TERNARY_INS(sve_fmsb);
1899 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmad);
1900 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmla);
1901 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmls);
1902 SVE_DESTRUCTIVE_TERNARY_INS(sve_fnmsb);
1903 SVE_DESTRUCTIVE_TERNARY_INS(sve_mla);
1904 SVE_DESTRUCTIVE_TERNARY_INS(sve_mls);
1905
1906 #undef SVE_DESTRUCTIVE_TERNARY_INS
1907
1908 #define SVE_DESTRUCTIVE_TERNARY_UNPRED_INS(NAME) \
1909 using Assembler::NAME; \
1910 void NAME(FloatRegister Zd, FloatRegister Zm, FloatRegister Zk) { \
1911 if (Zd != Zm && Zd != Zk) { \
1912 try_to_replace_prev_vector_copy_with_movprfx(Zd); \
1913 } \
1914 Assembler::NAME(Zd, Zm, Zk); \
1915 }
1916
1917 SVE_DESTRUCTIVE_TERNARY_UNPRED_INS(sve_bsl);
1918 SVE_DESTRUCTIVE_TERNARY_UNPRED_INS(sve_eor3);
1919
1920 #undef SVE_DESTRUCTIVE_TERNARY_UNPRED_INS
1921 };
1922
1923 #ifdef ASSERT
1924 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1925 #endif
1926
1927 struct tableswitch {
1928 Register _reg;
1929 int _insn_index; jint _first_key; jint _last_key;
1930 Label _after;
1931 Label _branches;
1932 };
1933
1934 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP