1 /*
   2  * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "code/vmreg.hpp"
  31 #include "metaprogramming/enableIf.hpp"
  32 #include "oops/compressedOops.hpp"
  33 #include "runtime/vm_version.hpp"
  34 #include "utilities/macros.hpp"
  35 #include "utilities/powerOfTwo.hpp"
  36 #include "runtime/signature.hpp"
  37 
  38 
  39 class ciInlineKlass;
  40 
  41 class OopMap;
  42 
  43 // MacroAssembler extends Assembler by frequently used macros.
  44 //
  45 // Instructions for which a 'better' code sequence exists depending
  46 // on arguments should also go in here.
  47 
  48 class MacroAssembler: public Assembler {
  49   friend class LIR_Assembler;
  50 
  51  public:
  52   using Assembler::mov;
  53   using Assembler::movi;
  54 
  55  protected:
  56 
  57   // Support for VM calls
  58   //
  59   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  60   // may customize this version by overriding it for its purposes (e.g., to save/restore
  61   // additional registers when doing a VM call).
  62   virtual void call_VM_leaf_base(
  63     address entry_point,               // the entry point
  64     int     number_of_arguments,        // the number of arguments to pop after the call
  65     Label *retaddr = NULL
  66   );
  67 
  68   virtual void call_VM_leaf_base(
  69     address entry_point,               // the entry point
  70     int     number_of_arguments,        // the number of arguments to pop after the call
  71     Label &retaddr) {
  72     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  73   }
  74 
  75   // This is the base routine called by the different versions of call_VM. The interpreter
  76   // may customize this version by overriding it for its purposes (e.g., to save/restore
  77   // additional registers when doing a VM call).
  78   //
  79   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  80   // returns the register which contains the thread upon return. If a thread register has been
  81   // specified, the return value will correspond to that register. If no last_java_sp is specified
  82   // (noreg) than rsp will be used instead.
  83   virtual void call_VM_base(           // returns the register containing the thread upon return
  84     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  85     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  86     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  87     address  entry_point,              // the entry point
  88     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  89     bool     check_exceptions          // whether to check for pending exceptions after return
  90   );
  91 
  92   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  93 
  94   enum KlassDecodeMode {
  95     KlassDecodeNone,
  96     KlassDecodeZero,
  97     KlassDecodeXor,
  98     KlassDecodeMovk
  99   };
 100 
 101   KlassDecodeMode klass_decode_mode();
 102 
 103  private:
 104   static KlassDecodeMode _klass_decode_mode;
 105 
 106  public:
 107   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
 108 
 109  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 110  // The implementation is only non-empty for the InterpreterMacroAssembler,
 111  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 112  virtual void check_and_handle_popframe(Register java_thread);
 113  virtual void check_and_handle_earlyret(Register java_thread);
 114 
 115   void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1);
 116   void rt_call(address dest, Register tmp = rscratch1);
 117 
 118   // Helper functions for statistics gathering.
 119   // Unconditional atomic increment.
 120   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 121   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 122     lea(tmp1, counter_addr);
 123     atomic_incw(tmp1, tmp2, tmp3);
 124   }
 125   // Load Effective Address
 126   void lea(Register r, const Address &a) {
 127     InstructionMark im(this);
 128     code_section()->relocate(inst_mark(), a.rspec());
 129     a.lea(this, r);
 130   }
 131 
 132   /* Sometimes we get misaligned loads and stores, usually from Unsafe
 133      accesses, and these can exceed the offset range. */
 134   Address legitimize_address(const Address &a, int size, Register scratch) {
 135     if (a.getMode() == Address::base_plus_offset) {
 136       if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
 137         block_comment("legitimize_address {");
 138         lea(scratch, a);
 139         block_comment("} legitimize_address");
 140         return Address(scratch);
 141       }
 142     }
 143     return a;
 144   }
 145 
 146   void addmw(Address a, Register incr, Register scratch) {
 147     ldrw(scratch, a);
 148     addw(scratch, scratch, incr);
 149     strw(scratch, a);
 150   }
 151 
 152   // Add constant to memory word
 153   void addmw(Address a, int imm, Register scratch) {
 154     ldrw(scratch, a);
 155     if (imm > 0)
 156       addw(scratch, scratch, (unsigned)imm);
 157     else
 158       subw(scratch, scratch, (unsigned)-imm);
 159     strw(scratch, a);
 160   }
 161 
 162   void bind(Label& L) {
 163     Assembler::bind(L);
 164     code()->clear_last_insn();
 165   }
 166 
 167   void membar(Membar_mask_bits order_constraint);
 168 
 169   using Assembler::ldr;
 170   using Assembler::str;
 171   using Assembler::ldrw;
 172   using Assembler::strw;
 173 
 174   void ldr(Register Rx, const Address &adr);
 175   void ldrw(Register Rw, const Address &adr);
 176   void str(Register Rx, const Address &adr);
 177   void strw(Register Rx, const Address &adr);
 178 
 179   // Frame creation and destruction shared between JITs.
 180   void build_frame(int framesize);
 181   void remove_frame(int framesize);
 182 
 183   virtual void _call_Unimplemented(address call_site) {
 184     mov(rscratch2, call_site);
 185   }
 186 
 187 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
 188 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
 189 // https://reviews.llvm.org/D3311
 190 
 191 #ifdef _WIN64
 192 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
 193 #else
 194 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 195 #endif
 196 
 197   // aliases defined in AARCH64 spec
 198 
 199   template<class T>
 200   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 201 
 202   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 203   inline void cmp(Register Rd, unsigned imm) = delete;
 204 
 205   template<class T>
 206   inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
 207 
 208   inline void cmn(Register Rd, unsigned char imm8)  { adds(zr, Rd, imm8); }
 209   inline void cmn(Register Rd, unsigned imm) = delete;
 210 
 211   void cset(Register Rd, Assembler::Condition cond) {
 212     csinc(Rd, zr, zr, ~cond);
 213   }
 214   void csetw(Register Rd, Assembler::Condition cond) {
 215     csincw(Rd, zr, zr, ~cond);
 216   }
 217 
 218   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 219     csneg(Rd, Rn, Rn, ~cond);
 220   }
 221   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 222     csnegw(Rd, Rn, Rn, ~cond);
 223   }
 224 
 225   inline void movw(Register Rd, Register Rn) {
 226     if (Rd == sp || Rn == sp) {
 227       Assembler::addw(Rd, Rn, 0U);
 228     } else {
 229       orrw(Rd, zr, Rn);
 230     }
 231   }
 232   inline void mov(Register Rd, Register Rn) {
 233     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 234     if (Rd == Rn) {
 235     } else if (Rd == sp || Rn == sp) {
 236       Assembler::add(Rd, Rn, 0U);
 237     } else {
 238       orr(Rd, zr, Rn);
 239     }
 240   }
 241 
 242   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 243   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 244 
 245   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 246   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 247 
 248   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 249   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 250 
 251   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 252     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 253   }
 254   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 255     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 256   }
 257 
 258   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 259     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 260   }
 261   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 262     bfm(Rd, Rn, lsb , (lsb + width - 1));
 263   }
 264 
 265   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 266     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 267   }
 268   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 269     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 270   }
 271 
 272   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 273     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 274   }
 275   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 276     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 277   }
 278 
 279   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 280     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 281   }
 282   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 283     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 284   }
 285 
 286   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 287     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 288   }
 289   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 290     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 291   }
 292 
 293   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 294     sbfmw(Rd, Rn, imm, 31);
 295   }
 296 
 297   inline void asr(Register Rd, Register Rn, unsigned imm) {
 298     sbfm(Rd, Rn, imm, 63);
 299   }
 300 
 301   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 302     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 303   }
 304 
 305   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 306     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 307   }
 308 
 309   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 310     ubfmw(Rd, Rn, imm, 31);
 311   }
 312 
 313   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 314     ubfm(Rd, Rn, imm, 63);
 315   }
 316 
 317   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 318     extrw(Rd, Rn, Rn, imm);
 319   }
 320 
 321   inline void ror(Register Rd, Register Rn, unsigned imm) {
 322     extr(Rd, Rn, Rn, imm);
 323   }
 324 
 325   inline void sxtbw(Register Rd, Register Rn) {
 326     sbfmw(Rd, Rn, 0, 7);
 327   }
 328   inline void sxthw(Register Rd, Register Rn) {
 329     sbfmw(Rd, Rn, 0, 15);
 330   }
 331   inline void sxtb(Register Rd, Register Rn) {
 332     sbfm(Rd, Rn, 0, 7);
 333   }
 334   inline void sxth(Register Rd, Register Rn) {
 335     sbfm(Rd, Rn, 0, 15);
 336   }
 337   inline void sxtw(Register Rd, Register Rn) {
 338     sbfm(Rd, Rn, 0, 31);
 339   }
 340 
 341   inline void uxtbw(Register Rd, Register Rn) {
 342     ubfmw(Rd, Rn, 0, 7);
 343   }
 344   inline void uxthw(Register Rd, Register Rn) {
 345     ubfmw(Rd, Rn, 0, 15);
 346   }
 347   inline void uxtb(Register Rd, Register Rn) {
 348     ubfm(Rd, Rn, 0, 7);
 349   }
 350   inline void uxth(Register Rd, Register Rn) {
 351     ubfm(Rd, Rn, 0, 15);
 352   }
 353   inline void uxtw(Register Rd, Register Rn) {
 354     ubfm(Rd, Rn, 0, 31);
 355   }
 356 
 357   inline void cmnw(Register Rn, Register Rm) {
 358     addsw(zr, Rn, Rm);
 359   }
 360   inline void cmn(Register Rn, Register Rm) {
 361     adds(zr, Rn, Rm);
 362   }
 363 
 364   inline void cmpw(Register Rn, Register Rm) {
 365     subsw(zr, Rn, Rm);
 366   }
 367   inline void cmp(Register Rn, Register Rm) {
 368     subs(zr, Rn, Rm);
 369   }
 370 
 371   inline void negw(Register Rd, Register Rn) {
 372     subw(Rd, zr, Rn);
 373   }
 374 
 375   inline void neg(Register Rd, Register Rn) {
 376     sub(Rd, zr, Rn);
 377   }
 378 
 379   inline void negsw(Register Rd, Register Rn) {
 380     subsw(Rd, zr, Rn);
 381   }
 382 
 383   inline void negs(Register Rd, Register Rn) {
 384     subs(Rd, zr, Rn);
 385   }
 386 
 387   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 388     addsw(zr, Rn, Rm, kind, shift);
 389   }
 390   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 391     adds(zr, Rn, Rm, kind, shift);
 392   }
 393 
 394   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 395     subsw(zr, Rn, Rm, kind, shift);
 396   }
 397   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 398     subs(zr, Rn, Rm, kind, shift);
 399   }
 400 
 401   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 402     subw(Rd, zr, Rn, kind, shift);
 403   }
 404 
 405   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 406     sub(Rd, zr, Rn, kind, shift);
 407   }
 408 
 409   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 410     subsw(Rd, zr, Rn, kind, shift);
 411   }
 412 
 413   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 414     subs(Rd, zr, Rn, kind, shift);
 415   }
 416 
 417   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 418     msubw(Rd, Rn, Rm, zr);
 419   }
 420   inline void mneg(Register Rd, Register Rn, Register Rm) {
 421     msub(Rd, Rn, Rm, zr);
 422   }
 423 
 424   inline void mulw(Register Rd, Register Rn, Register Rm) {
 425     maddw(Rd, Rn, Rm, zr);
 426   }
 427   inline void mul(Register Rd, Register Rn, Register Rm) {
 428     madd(Rd, Rn, Rm, zr);
 429   }
 430 
 431   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 432     smsubl(Rd, Rn, Rm, zr);
 433   }
 434   inline void smull(Register Rd, Register Rn, Register Rm) {
 435     smaddl(Rd, Rn, Rm, zr);
 436   }
 437 
 438   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 439     umsubl(Rd, Rn, Rm, zr);
 440   }
 441   inline void umull(Register Rd, Register Rn, Register Rm) {
 442     umaddl(Rd, Rn, Rm, zr);
 443   }
 444 
 445 #define WRAP(INSN)                                                            \
 446   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 447     if (VM_Version::supports_a53mac() && Ra != zr)                            \
 448       nop();                                                                  \
 449     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 450   }
 451 
 452   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 453   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 454 #undef WRAP
 455 
 456 
 457   // macro assembly operations needed for aarch64
 458 
 459   // first two private routines for loading 32 bit or 64 bit constants
 460 private:
 461 
 462   void mov_immediate64(Register dst, uint64_t imm64);
 463   void mov_immediate32(Register dst, uint32_t imm32);
 464 
 465   int push(unsigned int bitset, Register stack);
 466   int pop(unsigned int bitset, Register stack);
 467 
 468   int push_fp(unsigned int bitset, Register stack);
 469   int pop_fp(unsigned int bitset, Register stack);
 470 
 471   int push_p(unsigned int bitset, Register stack);
 472   int pop_p(unsigned int bitset, Register stack);
 473 
 474   void mov(Register dst, Address a);
 475 
 476 public:
 477   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 478   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 479 
 480   void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
 481   void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
 482 
 483   static RegSet call_clobbered_gp_registers();
 484 
 485   void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
 486   void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
 487 
 488   // Push and pop everything that might be clobbered by a native
 489   // runtime call except rscratch1 and rscratch2.  (They are always
 490   // scratch, so we don't have to protect them.)  Only save the lower
 491   // 64 bits of each vector register. Additional registers can be excluded
 492   // in a passed RegSet.
 493   void push_call_clobbered_registers_except(RegSet exclude);
 494   void pop_call_clobbered_registers_except(RegSet exclude);
 495 
 496   void push_call_clobbered_registers() {
 497     push_call_clobbered_registers_except(RegSet());
 498   }
 499   void pop_call_clobbered_registers() {
 500     pop_call_clobbered_registers_except(RegSet());
 501   }
 502 
 503 
 504   // now mov instructions for loading absolute addresses and 32 or
 505   // 64 bit integers
 506 
 507   inline void mov(Register dst, address addr)             { mov_immediate64(dst, (uint64_t)addr); }
 508 
 509   template<typename T, ENABLE_IF(std::is_integral<T>::value)>
 510   inline void mov(Register dst, T o)                      { mov_immediate64(dst, (uint64_t)o); }
 511 
 512   inline void movw(Register dst, uint32_t imm32)          { mov_immediate32(dst, imm32); }
 513 
 514   void mov(Register dst, RegisterOrConstant src) {
 515     if (src.is_register())
 516       mov(dst, src.as_register());
 517     else
 518       mov(dst, src.as_constant());
 519   }
 520 
 521   void movptr(Register r, uintptr_t imm64);
 522 
 523   void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
 524 
 525   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 526     orr(Vd, T, Vn, Vn);
 527   }
 528 
 529 
 530 public:
 531 
 532   // Generalized Test Bit And Branch, including a "far" variety which
 533   // spans more than 32KiB.
 534   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
 535     assert(cond == EQ || cond == NE, "must be");
 536 
 537     if (isfar)
 538       cond = ~cond;
 539 
 540     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 541     if (cond == Assembler::EQ)
 542       branch = &Assembler::tbz;
 543     else
 544       branch = &Assembler::tbnz;
 545 
 546     if (isfar) {
 547       Label L;
 548       (this->*branch)(Rt, bitpos, L);
 549       b(dest);
 550       bind(L);
 551     } else {
 552       (this->*branch)(Rt, bitpos, dest);
 553     }
 554   }
 555 
 556   // macro instructions for accessing and updating floating point
 557   // status register
 558   //
 559   // FPSR : op1 == 011
 560   //        CRn == 0100
 561   //        CRm == 0100
 562   //        op2 == 001
 563 
 564   inline void get_fpsr(Register reg)
 565   {
 566     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 567   }
 568 
 569   inline void set_fpsr(Register reg)
 570   {
 571     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 572   }
 573 
 574   inline void clear_fpsr()
 575   {
 576     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 577   }
 578 
 579   // DCZID_EL0: op1 == 011
 580   //            CRn == 0000
 581   //            CRm == 0000
 582   //            op2 == 111
 583   inline void get_dczid_el0(Register reg)
 584   {
 585     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 586   }
 587 
 588   // CTR_EL0:   op1 == 011
 589   //            CRn == 0000
 590   //            CRm == 0000
 591   //            op2 == 001
 592   inline void get_ctr_el0(Register reg)
 593   {
 594     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 595   }
 596 
 597   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 598   int corrected_idivl(Register result, Register ra, Register rb,
 599                       bool want_remainder, Register tmp = rscratch1);
 600   int corrected_idivq(Register result, Register ra, Register rb,
 601                       bool want_remainder, Register tmp = rscratch1);
 602 
 603   // Support for NULL-checks
 604   //
 605   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 606   // If the accessed location is M[reg + offset] and the offset is known, provide the
 607   // offset. No explicit code generation is needed if the offset is within a certain
 608   // range (0 <= offset <= page_size).
 609 
 610   virtual void null_check(Register reg, int offset = -1);
 611   static bool needs_explicit_null_check(intptr_t offset);
 612   static bool uses_implicit_null_check(void* address);
 613 
 614   // markWord tests, kills markWord reg
 615   void test_markword_is_inline_type(Register markword, Label& is_inline_type);
 616 
 617   // inlineKlass queries, kills temp_reg
 618   void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type);
 619   void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type);
 620   void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type);
 621 
 622   // Get the default value oop for the given InlineKlass
 623   void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj);
 624   // The empty value oop, for the given InlineKlass ("empty" as in no instance fields)
 625   // get_default_value_oop with extra assertion for empty inline klass
 626   void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj);
 627 
 628   void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
 629   void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
 630   void test_field_is_inlined(Register flags, Register temp_reg, Label& is_flattened);
 631 
 632   // Check oops for special arrays, i.e. flattened and/or null-free
 633   void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
 634   void test_flattened_array_oop(Register klass, Register temp_reg, Label& is_flattened_array);
 635   void test_non_flattened_array_oop(Register oop, Register temp_reg, Label&is_non_flattened_array);
 636   void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
 637   void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
 638 
 639   // Check array klass layout helper for flatten or null-free arrays...
 640   void test_flattened_array_layout(Register lh, Label& is_flattened_array);
 641   void test_non_flattened_array_layout(Register lh, Label& is_non_flattened_array);
 642   void test_null_free_array_layout(Register lh, Label& is_null_free_array);
 643   void test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array);
 644 
 645   static address target_addr_for_insn(address insn_addr, unsigned insn);
 646   static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
 647   static address target_addr_for_insn(address insn_addr) {
 648     unsigned insn = *(unsigned*)insn_addr;
 649     return target_addr_for_insn(insn_addr, insn);
 650   }
 651   static address target_addr_for_insn_or_null(address insn_addr) {
 652     unsigned insn = *(unsigned*)insn_addr;
 653     return target_addr_for_insn_or_null(insn_addr, insn);
 654   }
 655 
 656   // Required platform-specific helpers for Label::patch_instructions.
 657   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 658   static int pd_patch_instruction_size(address branch, address target);
 659   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 660     pd_patch_instruction_size(branch, target);
 661   }
 662   static address pd_call_destination(address branch) {
 663     return target_addr_for_insn(branch);
 664   }
 665 #ifndef PRODUCT
 666   static void pd_print_patched_instruction(address branch);
 667 #endif
 668 
 669   static int patch_oop(address insn_addr, address o);
 670   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 671 
 672   // Return whether code is emitted to a scratch blob.
 673   virtual bool in_scratch_emit_size() {
 674     return false;
 675   }
 676   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 677   void emit_static_call_stub();
 678 
 679   // The following 4 methods return the offset of the appropriate move instruction
 680 
 681   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 682   int load_unsigned_byte(Register dst, Address src);
 683   int load_unsigned_short(Register dst, Address src);
 684 
 685   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 686   int load_signed_byte(Register dst, Address src);
 687   int load_signed_short(Register dst, Address src);
 688 
 689   int load_signed_byte32(Register dst, Address src);
 690   int load_signed_short32(Register dst, Address src);
 691 
 692   // Support for sign-extension (hi:lo = extend_sign(lo))
 693   void extend_sign(Register hi, Register lo);
 694 
 695   // Load and store values by size and signed-ness
 696   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 697   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 698 
 699   // Support for inc/dec with optimal instruction selection depending on value
 700 
 701   // x86_64 aliases an unqualified register/address increment and
 702   // decrement to call incrementq and decrementq but also supports
 703   // explicitly sized calls to incrementq/decrementq or
 704   // incrementl/decrementl
 705 
 706   // for aarch64 the proper convention would be to use
 707   // increment/decrement for 64 bit operations and
 708   // incrementw/decrementw for 32 bit operations. so when porting
 709   // x86_64 code we can leave calls to increment/decrement as is,
 710   // replace incrementq/decrementq with increment/decrement and
 711   // replace incrementl/decrementl with incrementw/decrementw.
 712 
 713   // n.b. increment/decrement calls with an Address destination will
 714   // need to use a scratch register to load the value to be
 715   // incremented. increment/decrement calls which add or subtract a
 716   // constant value greater than 2^12 will need to use a 2nd scratch
 717   // register to hold the constant. so, a register increment/decrement
 718   // may trash rscratch2 and an address increment/decrement trash
 719   // rscratch and rscratch2
 720 
 721   void decrementw(Address dst, int value = 1);
 722   void decrementw(Register reg, int value = 1);
 723 
 724   void decrement(Register reg, int value = 1);
 725   void decrement(Address dst, int value = 1);
 726 
 727   void incrementw(Address dst, int value = 1);
 728   void incrementw(Register reg, int value = 1);
 729 
 730   void increment(Register reg, int value = 1);
 731   void increment(Address dst, int value = 1);
 732 
 733 
 734   // Alignment
 735   void align(int modulus);
 736 
 737   // nop
 738   void post_call_nop();
 739 
 740   // Stack frame creation/removal
 741   void enter(bool strip_ret_addr = false);
 742   void leave();
 743 
 744   // ROP Protection
 745   void protect_return_address();
 746   void protect_return_address(Register return_reg, Register temp_reg);
 747   void authenticate_return_address(Register return_reg = lr);
 748   void authenticate_return_address(Register return_reg, Register temp_reg);
 749   void strip_return_address();
 750   void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
 751 
 752   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 753   // The pointer will be loaded into the thread register.
 754   void get_thread(Register thread);
 755 
 756   // support for argument shuffling
 757   void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 758   void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 759   void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 760   void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
 761   void object_move(
 762                    OopMap* map,
 763                    int oop_handle_offset,
 764                    int framesize_in_slots,
 765                    VMRegPair src,
 766                    VMRegPair dst,
 767                    bool is_receiver,
 768                    int* receiver_offset);
 769 
 770 
 771   // Support for VM calls
 772   //
 773   // It is imperative that all calls into the VM are handled via the call_VM macros.
 774   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 775   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 776 
 777 
 778   void call_VM(Register oop_result,
 779                address entry_point,
 780                bool check_exceptions = true);
 781   void call_VM(Register oop_result,
 782                address entry_point,
 783                Register arg_1,
 784                bool check_exceptions = true);
 785   void call_VM(Register oop_result,
 786                address entry_point,
 787                Register arg_1, Register arg_2,
 788                bool check_exceptions = true);
 789   void call_VM(Register oop_result,
 790                address entry_point,
 791                Register arg_1, Register arg_2, Register arg_3,
 792                bool check_exceptions = true);
 793 
 794   // Overloadings with last_Java_sp
 795   void call_VM(Register oop_result,
 796                Register last_java_sp,
 797                address entry_point,
 798                int number_of_arguments = 0,
 799                bool check_exceptions = true);
 800   void call_VM(Register oop_result,
 801                Register last_java_sp,
 802                address entry_point,
 803                Register arg_1, bool
 804                check_exceptions = true);
 805   void call_VM(Register oop_result,
 806                Register last_java_sp,
 807                address entry_point,
 808                Register arg_1, Register arg_2,
 809                bool check_exceptions = true);
 810   void call_VM(Register oop_result,
 811                Register last_java_sp,
 812                address entry_point,
 813                Register arg_1, Register arg_2, Register arg_3,
 814                bool check_exceptions = true);
 815 
 816   void get_vm_result  (Register oop_result, Register thread);
 817   void get_vm_result_2(Register metadata_result, Register thread);
 818 
 819   // These always tightly bind to MacroAssembler::call_VM_base
 820   // bypassing the virtual implementation
 821   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 822   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 823   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 824   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 825   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 826 
 827   void call_VM_leaf(address entry_point,
 828                     int number_of_arguments = 0);
 829   void call_VM_leaf(address entry_point,
 830                     Register arg_1);
 831   void call_VM_leaf(address entry_point,
 832                     Register arg_1, Register arg_2);
 833   void call_VM_leaf(address entry_point,
 834                     Register arg_1, Register arg_2, Register arg_3);
 835 
 836   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 837   // bypassing the virtual implementation
 838   void super_call_VM_leaf(address entry_point);
 839   void super_call_VM_leaf(address entry_point, Register arg_1);
 840   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 841   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 842   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 843 
 844   // last Java Frame (fills frame anchor)
 845   void set_last_Java_frame(Register last_java_sp,
 846                            Register last_java_fp,
 847                            address last_java_pc,
 848                            Register scratch);
 849 
 850   void set_last_Java_frame(Register last_java_sp,
 851                            Register last_java_fp,
 852                            Label &last_java_pc,
 853                            Register scratch);
 854 
 855   void set_last_Java_frame(Register last_java_sp,
 856                            Register last_java_fp,
 857                            Register last_java_pc,
 858                            Register scratch);
 859 
 860   void reset_last_Java_frame(Register thread);
 861 
 862   // thread in the default location (rthread)
 863   void reset_last_Java_frame(bool clear_fp);
 864 
 865   // Stores
 866   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 867   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 868 
 869   void resolve_jobject(Register value, Register tmp1, Register tmp2);
 870 
 871   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 872   void c2bool(Register x);
 873 
 874   void load_method_holder_cld(Register rresult, Register rmethod);
 875   void load_method_holder(Register holder, Register method);
 876 
 877   // oop manipulations
 878   void load_metadata(Register dst, Register src);
 879 
 880   void load_klass(Register dst, Register src);
 881   void store_klass(Register dst, Register src);
 882   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 883 
 884   void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
 885   void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
 886   void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
 887 
 888   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 889                       Register tmp1, Register tmp2);
 890 
 891   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 892                        Register tmp1, Register tmp2, Register tmp3);
 893 
 894   void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register inline_klass);
 895 
 896   // inline type data payload offsets...
 897   void first_field_offset(Register inline_klass, Register offset);
 898   void data_for_oop(Register oop, Register data, Register inline_klass);
 899   // get data payload ptr a flat value array at index, kills rcx and index
 900   void data_for_value_array_index(Register array, Register array_klass,
 901                                   Register index, Register data);
 902 
 903   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 904                      Register tmp2 = noreg, DecoratorSet decorators = 0);
 905 
 906   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 907                               Register tmp2 = noreg, DecoratorSet decorators = 0);
 908   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 909                       Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
 910 
 911   // currently unimplemented
 912   // Used for storing NULL. All other oop constants should be
 913   // stored using routines that take a jobject.
 914   void store_heap_oop_null(Address dst);
 915 
 916   void load_prototype_header(Register dst, Register src);
 917 
 918   void store_klass_gap(Register dst, Register src);
 919 
 920   // This dummy is to prevent a call to store_heap_oop from
 921   // converting a zero (like NULL) into a Register by giving
 922   // the compiler two choices it can't resolve
 923 
 924   void store_heap_oop(Address dst, void* dummy);
 925 
 926   void encode_heap_oop(Register d, Register s);
 927   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 928   void decode_heap_oop(Register d, Register s);
 929   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 930   void encode_heap_oop_not_null(Register r);
 931   void decode_heap_oop_not_null(Register r);
 932   void encode_heap_oop_not_null(Register dst, Register src);
 933   void decode_heap_oop_not_null(Register dst, Register src);
 934 
 935   void set_narrow_oop(Register dst, jobject obj);
 936 
 937   void encode_klass_not_null(Register r);
 938   void decode_klass_not_null(Register r);
 939   void encode_klass_not_null(Register dst, Register src);
 940   void decode_klass_not_null(Register dst, Register src);
 941 
 942   void set_narrow_klass(Register dst, Klass* k);
 943 
 944   // if heap base register is used - reinit it with the correct value
 945   void reinit_heapbase();
 946 
 947   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 948 
 949   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 950                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 951   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 952                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 953 
 954   void push_cont_fastpath(Register java_thread);
 955   void pop_cont_fastpath(Register java_thread);
 956 
 957   // Round up to a power of two
 958   void round_to(Register reg, int modulus);
 959 
 960   // java.lang.Math::round intrinsics
 961   void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
 962   void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
 963 
 964   // allocation
 965 
 966   // Object / value buffer allocation...
 967   // Allocate instance of klass, assumes klass initialized by caller
 968   // new_obj prefers to be rax
 969   // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
 970   void allocate_instance(Register klass, Register new_obj,
 971                          Register t1, Register t2,
 972                          bool clear_fields, Label& alloc_failed);
 973 
 974   void tlab_allocate(
 975     Register obj,                      // result: pointer to object after successful allocation
 976     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 977     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 978     Register t1,                       // temp register
 979     Register t2,                       // temp register
 980     Label&   slow_case                 // continuation point if fast allocation fails
 981   );
 982   void verify_tlab();
 983 
 984   // For field "index" within "klass", return inline_klass ...
 985   void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
 986 
 987   // interface method calling
 988   void lookup_interface_method(Register recv_klass,
 989                                Register intf_klass,
 990                                RegisterOrConstant itable_index,
 991                                Register method_result,
 992                                Register scan_temp,
 993                                Label& no_such_interface,
 994                    bool return_method = true);
 995 
 996   // virtual method calling
 997   // n.b. x86 allows RegisterOrConstant for vtable_index
 998   void lookup_virtual_method(Register recv_klass,
 999                              RegisterOrConstant vtable_index,
1000                              Register method_result);
1001 
1002   // Test sub_klass against super_klass, with fast and slow paths.
1003 
1004   // The fast path produces a tri-state answer: yes / no / maybe-slow.
1005   // One of the three labels can be NULL, meaning take the fall-through.
1006   // If super_check_offset is -1, the value is loaded up from super_klass.
1007   // No registers are killed, except temp_reg.
1008   void check_klass_subtype_fast_path(Register sub_klass,
1009                                      Register super_klass,
1010                                      Register temp_reg,
1011                                      Label* L_success,
1012                                      Label* L_failure,
1013                                      Label* L_slow_path,
1014                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1015 
1016   // The rest of the type check; must be wired to a corresponding fast path.
1017   // It does not repeat the fast path logic, so don't use it standalone.
1018   // The temp_reg and temp2_reg can be noreg, if no temps are available.
1019   // Updates the sub's secondary super cache as necessary.
1020   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1021   void check_klass_subtype_slow_path(Register sub_klass,
1022                                      Register super_klass,
1023                                      Register temp_reg,
1024                                      Register temp2_reg,
1025                                      Label* L_success,
1026                                      Label* L_failure,
1027                                      bool set_cond_codes = false);
1028 
1029   // Simplified, combined version, good for typical uses.
1030   // Falls through on failure.
1031   void check_klass_subtype(Register sub_klass,
1032                            Register super_klass,
1033                            Register temp_reg,
1034                            Label& L_success);
1035 
1036   void clinit_barrier(Register klass,
1037                       Register thread,
1038                       Label* L_fast_path = NULL,
1039                       Label* L_slow_path = NULL);
1040 
1041   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1042 
1043   void verify_sve_vector_length(Register tmp = rscratch1);
1044   void reinitialize_ptrue() {
1045     if (UseSVE > 0) {
1046       sve_ptrue(ptrue, B);
1047     }
1048   }
1049   void verify_ptrue();
1050 
1051   // Debugging
1052 
1053   // only if +VerifyOops
1054   void _verify_oop(Register reg, const char* s, const char* file, int line);
1055   void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1056 
1057   void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1058     if (VerifyOops) {
1059       _verify_oop(reg, s, file, line);
1060     }
1061   }
1062   void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1063     if (VerifyOops) {
1064       _verify_oop_addr(reg, s, file, line);
1065     }
1066   }
1067 
1068 // TODO: verify method and klass metadata (compare against vptr?)
1069   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1070   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1071 
1072 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1073 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1074 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1075 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1076 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1077 
1078   // only if +VerifyFPU
1079   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1080 
1081   // prints msg, dumps registers and stops execution
1082   void stop(const char* msg);
1083 
1084   static void debug64(char* msg, int64_t pc, int64_t regs[]);
1085 
1086   void untested()                                { stop("untested"); }
1087 
1088   void unimplemented(const char* what = "");
1089 
1090   void should_not_reach_here()                   { stop("should not reach here"); }
1091 
1092   void _assert_asm(Condition cc, const char* msg);
1093 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1094 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1095 
1096   // Stack overflow checking
1097   void bang_stack_with_offset(int offset) {
1098     // stack grows down, caller passes positive offset
1099     assert(offset > 0, "must bang with negative offset");
1100     sub(rscratch2, sp, offset);
1101     str(zr, Address(rscratch2));
1102   }
1103 
1104   // Writes to stack successive pages until offset reached to check for
1105   // stack overflow + shadow pages.  Also, clobbers tmp
1106   void bang_stack_size(Register size, Register tmp);
1107 
1108   // Check for reserved stack access in method being exited (for JIT)
1109   void reserved_stack_check();
1110 
1111   // Arithmetics
1112 
1113   void addptr(const Address &dst, int32_t src);
1114   void cmpptr(Register src1, Address src2);
1115 
1116   void cmpoop(Register obj1, Register obj2);
1117 
1118   // Various forms of CAS
1119 
1120   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1121                           Label &succeed, Label *fail);
1122   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1123                   Label &succeed, Label *fail);
1124 
1125   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1126                   Label &succeed, Label *fail);
1127 
1128   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1129   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1130   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1131   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1132 
1133   void atomic_xchg(Register prev, Register newv, Register addr);
1134   void atomic_xchgw(Register prev, Register newv, Register addr);
1135   void atomic_xchgl(Register prev, Register newv, Register addr);
1136   void atomic_xchglw(Register prev, Register newv, Register addr);
1137   void atomic_xchgal(Register prev, Register newv, Register addr);
1138   void atomic_xchgalw(Register prev, Register newv, Register addr);
1139 
1140   void orptr(Address adr, RegisterOrConstant src) {
1141     ldr(rscratch1, adr);
1142     if (src.is_register())
1143       orr(rscratch1, rscratch1, src.as_register());
1144     else
1145       orr(rscratch1, rscratch1, src.as_constant());
1146     str(rscratch1, adr);
1147   }
1148 
1149   // A generic CAS; success or failure is in the EQ flag.
1150   // Clobbers rscratch1
1151   void cmpxchg(Register addr, Register expected, Register new_val,
1152                enum operand_size size,
1153                bool acquire, bool release, bool weak,
1154                Register result);
1155 
1156 private:
1157   void compare_eq(Register rn, Register rm, enum operand_size size);
1158 
1159 #ifdef ASSERT
1160   // Template short-hand support to clean-up after a failed call to trampoline
1161   // call generation (see trampoline_call() below),  when a set of Labels must
1162   // be reset (before returning).
1163   template<typename Label, typename... More>
1164   void reset_labels(Label &lbl, More&... more) {
1165     lbl.reset(); reset_labels(more...);
1166   }
1167   template<typename Label>
1168   void reset_labels(Label &lbl) {
1169     lbl.reset();
1170   }
1171 #endif
1172 
1173 public:
1174   // AArch64 OpenJDK uses four different types of calls:
1175   //   - direct call: bl pc_relative_offset
1176   //     This is the shortest and the fastest, but the offset has the range:
1177   //     +/-128MB for the release build, +/-2MB for the debug build.
1178   //
1179   //   - far call: adrp reg, pc_relative_offset; add; bl reg
1180   //     This is longer than a direct call. The offset has
1181   //     the range +/-4GB. As the code cache size is limited to 4GB,
1182   //     far calls can reach anywhere in the code cache. If a jump is
1183   //     needed rather than a call, a far jump 'b reg' can be used instead.
1184   //     All instructions are embedded at a call site.
1185   //
1186   //   - trampoline call:
1187   //     This is only available in C1/C2-generated code (nmethod). It is a combination
1188   //     of a direct call, which is used if the destination of a call is in range,
1189   //     and a register-indirect call. It has the advantages of reaching anywhere in
1190   //     the AArch64 address space and being patchable at runtime when the generated
1191   //     code is being executed by other threads.
1192   //
1193   //     [Main code section]
1194   //       bl trampoline
1195   //     [Stub code section]
1196   //     trampoline:
1197   //       ldr reg, pc + 8
1198   //       br reg
1199   //       <64-bit destination address>
1200   //
1201   //     If the destination is in range when the generated code is moved to the code
1202   //     cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1203   //     is not used.
1204   //     The optimization does not remove the trampoline from the stub section.
1205   //     This is necessary because the trampoline may well be redirected later when
1206   //     code is patched, and the new destination may not be reachable by a simple BR
1207   //     instruction.
1208   //
1209   //   - indirect call: move reg, address; blr reg
1210   //     This too can reach anywhere in the address space, but it cannot be
1211   //     patched while code is running, so it must only be modified at a safepoint.
1212   //     This form of call is most suitable for targets at fixed addresses, which
1213   //     will never be patched.
1214   //
1215   // The patching we do conforms to the "Concurrent modification and
1216   // execution of instructions" section of the Arm Architectural
1217   // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1218   // or SVC instructions to be modified while another thread is
1219   // executing them.
1220   //
1221   // To patch a trampoline call when the BL can't reach, we first modify
1222   // the 64-bit destination address in the trampoline, then modify the
1223   // BL to point to the trampoline, then flush the instruction cache to
1224   // broadcast the change to all executing threads. See
1225   // NativeCall::set_destination_mt_safe for the details.
1226   //
1227   // There is a benign race in that the other thread might observe the
1228   // modified BL before it observes the modified 64-bit destination
1229   // address. That does not matter because the destination method has been
1230   // invalidated, so there will be a trap at its start.
1231   // For this to work, the destination address in the trampoline is
1232   // always updated, even if we're not using the trampoline.
1233 
1234   // Emit a direct call if the entry address will always be in range,
1235   // otherwise a trampoline call.
1236   // Supported entry.rspec():
1237   // - relocInfo::runtime_call_type
1238   // - relocInfo::opt_virtual_call_type
1239   // - relocInfo::static_call_type
1240   // - relocInfo::virtual_call_type
1241   //
1242   // Return: the call PC or NULL if CodeCache is full.
1243   address trampoline_call(Address entry);
1244 
1245   static bool far_branches() {
1246     return ReservedCodeCacheSize > branch_range;
1247   }
1248 
1249   // Check if branches to the the non nmethod section require a far jump
1250   static bool codestub_branch_needs_far_jump() {
1251     return CodeCache::max_distance_to_non_nmethod() > branch_range;
1252   }
1253 
1254   // Emit a direct call/jump if the entry address will always be in range,
1255   // otherwise a far call/jump.
1256   // The address must be inside the code cache.
1257   // Supported entry.rspec():
1258   // - relocInfo::external_word_type
1259   // - relocInfo::runtime_call_type
1260   // - relocInfo::none
1261   // In the case of a far call/jump, the entry address is put in the tmp register.
1262   // The tmp register is invalidated.
1263   //
1264   // Far_jump returns the amount of the emitted code.
1265   void far_call(Address entry, Register tmp = rscratch1);
1266   int far_jump(Address entry, Register tmp = rscratch1);
1267 
1268   static int far_codestub_branch_size() {
1269     if (codestub_branch_needs_far_jump()) {
1270       return 3 * 4;  // adrp, add, br
1271     } else {
1272       return 4;
1273     }
1274   }
1275 
1276   // Emit the CompiledIC call idiom
1277   address ic_call(address entry, jint method_index = 0);
1278 
1279 public:
1280 
1281   // Data
1282 
1283   void mov_metadata(Register dst, Metadata* obj);
1284   Address allocate_metadata_address(Metadata* obj);
1285   Address constant_oop_address(jobject obj);
1286 
1287   void movoop(Register dst, jobject obj);
1288 
1289   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1290   void kernel_crc32(Register crc, Register buf, Register len,
1291         Register table0, Register table1, Register table2, Register table3,
1292         Register tmp, Register tmp2, Register tmp3);
1293   // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1294   void kernel_crc32c(Register crc, Register buf, Register len,
1295         Register table0, Register table1, Register table2, Register table3,
1296         Register tmp, Register tmp2, Register tmp3);
1297 
1298   // Stack push and pop individual 64 bit registers
1299   void push(Register src);
1300   void pop(Register dst);
1301 
1302   void repne_scan(Register addr, Register value, Register count,
1303                   Register scratch);
1304   void repne_scanw(Register addr, Register value, Register count,
1305                    Register scratch);
1306 
1307   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1308   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1309 
1310   // If a constant does not fit in an immediate field, generate some
1311   // number of MOV instructions and then perform the operation
1312   void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1313                              add_sub_imm_insn insn1,
1314                              add_sub_reg_insn insn2, bool is32);
1315   // Separate vsn which sets the flags
1316   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1317                                add_sub_imm_insn insn1,
1318                                add_sub_reg_insn insn2, bool is32);
1319 
1320 #define WRAP(INSN, is32)                                                \
1321   void INSN(Register Rd, Register Rn, uint64_t imm) {                   \
1322     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1323   }                                                                     \
1324                                                                         \
1325   void INSN(Register Rd, Register Rn, Register Rm,                      \
1326              enum shift_kind kind, unsigned shift = 0) {                \
1327     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1328   }                                                                     \
1329                                                                         \
1330   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1331     Assembler::INSN(Rd, Rn, Rm);                                        \
1332   }                                                                     \
1333                                                                         \
1334   void INSN(Register Rd, Register Rn, Register Rm,                      \
1335            ext::operation option, int amount = 0) {                     \
1336     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1337   }
1338 
1339   WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1340 
1341 #undef WRAP
1342 #define WRAP(INSN, is32)                                                \
1343   void INSN(Register Rd, Register Rn, uint64_t imm) {                   \
1344     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1345   }                                                                     \
1346                                                                         \
1347   void INSN(Register Rd, Register Rn, Register Rm,                      \
1348              enum shift_kind kind, unsigned shift = 0) {                \
1349     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1350   }                                                                     \
1351                                                                         \
1352   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1353     Assembler::INSN(Rd, Rn, Rm);                                        \
1354   }                                                                     \
1355                                                                         \
1356   void INSN(Register Rd, Register Rn, Register Rm,                      \
1357            ext::operation option, int amount = 0) {                     \
1358     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1359   }
1360 
1361   WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1362 
1363   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1364   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1365   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1366   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1367 
1368   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1369 
1370   void verified_entry(Compile* C, int sp_inc);
1371 
1372   // Inline type specific methods
1373   #include "asm/macroAssembler_common.hpp"
1374 
1375   int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1376   bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1377   bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1378                             VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1379                             RegState reg_state[]);
1380   bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1381                           VMRegPair* from, int from_count, int& from_index, VMReg to,
1382                           RegState reg_state[], Register val_array);
1383   int extend_stack_for_inline_args(int args_on_stack);
1384   void remove_frame(int initial_framesize, bool needs_stack_repair);
1385   VMReg spill_reg_for(VMReg reg);
1386   void save_stack_increment(int sp_inc, int frame_size);
1387 
1388   void tableswitch(Register index, jint lowbound, jint highbound,
1389                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1390     adr(rscratch1, jumptable);
1391     subsw(rscratch2, index, lowbound);
1392     subsw(zr, rscratch2, highbound - lowbound);
1393     br(Assembler::HS, jumptable_end);
1394     add(rscratch1, rscratch1, rscratch2,
1395         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1396     br(rscratch1);
1397   }
1398 
1399   // Form an address from base + offset in Rd.  Rd may or may not
1400   // actually be used: you must use the Address that is returned.  It
1401   // is up to you to ensure that the shift provided matches the size
1402   // of your data.
1403   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1404 
1405   // Return true iff an address is within the 48-bit AArch64 address
1406   // space.
1407   bool is_valid_AArch64_address(address a) {
1408     return ((uint64_t)a >> 48) == 0;
1409   }
1410 
1411   // Load the base of the cardtable byte map into reg.
1412   void load_byte_map_base(Register reg);
1413 
1414   // Prolog generator routines to support switch between x86 code and
1415   // generated ARM code
1416 
1417   // routine to generate an x86 prolog for a stub function which
1418   // bootstraps into the generated ARM code which directly follows the
1419   // stub
1420   //
1421 
1422   public:
1423 
1424   void ldr_constant(Register dest, const Address &const_addr) {
1425     if (NearCpool) {
1426       ldr(dest, const_addr);
1427     } else {
1428       uint64_t offset;
1429       adrp(dest, InternalAddress(const_addr.target()), offset);
1430       ldr(dest, Address(dest, offset));
1431     }
1432   }
1433 
1434   address read_polling_page(Register r, relocInfo::relocType rtype);
1435   void get_polling_page(Register dest, relocInfo::relocType rtype);
1436 
1437   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1438   void update_byte_crc32(Register crc, Register val, Register table);
1439   void update_word_crc32(Register crc, Register v, Register tmp,
1440         Register table0, Register table1, Register table2, Register table3,
1441         bool upper = false);
1442 
1443   address count_positives(Register ary1, Register len, Register result);
1444 
1445   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1446                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1447 
1448   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1449                      int elem_size);
1450 
1451   void fill_words(Register base, Register cnt, Register value);
1452   void fill_words(Register base, uint64_t cnt, Register value);
1453 
1454   address zero_words(Register base, uint64_t cnt);
1455   address zero_words(Register ptr, Register cnt);
1456   void zero_dcache_blocks(Register base, Register cnt);
1457 
1458   static const int zero_words_block_size;
1459 
1460   address byte_array_inflate(Register src, Register dst, Register len,
1461                              FloatRegister vtmp1, FloatRegister vtmp2,
1462                              FloatRegister vtmp3, Register tmp4);
1463 
1464   void char_array_compress(Register src, Register dst, Register len,
1465                            Register res,
1466                            FloatRegister vtmp0, FloatRegister vtmp1,
1467                            FloatRegister vtmp2, FloatRegister vtmp3);
1468 
1469   void encode_iso_array(Register src, Register dst,
1470                         Register len, Register res, bool ascii,
1471                         FloatRegister vtmp0, FloatRegister vtmp1,
1472                         FloatRegister vtmp2, FloatRegister vtmp3);
1473 
1474   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1475                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1476                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1477                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1478                 Register tmp3, Register tmp4, Register tmp5);
1479   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1480       address pio2, address dsin_coef, address dcos_coef);
1481  private:
1482   // begin trigonometric functions support block
1483   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1484   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1485   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1486   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1487   // end trigonometric functions support block
1488   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1489                        Register src1, Register src2);
1490   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1491     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1492   }
1493   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1494                              Register y, Register y_idx, Register z,
1495                              Register carry, Register product,
1496                              Register idx, Register kdx);
1497   void multiply_128_x_128_loop(Register y, Register z,
1498                                Register carry, Register carry2,
1499                                Register idx, Register jdx,
1500                                Register yz_idx1, Register yz_idx2,
1501                                Register tmp, Register tmp3, Register tmp4,
1502                                Register tmp7, Register product_hi);
1503   void kernel_crc32_using_crc32(Register crc, Register buf,
1504         Register len, Register tmp0, Register tmp1, Register tmp2,
1505         Register tmp3);
1506   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1507         Register len, Register tmp0, Register tmp1, Register tmp2,
1508         Register tmp3);
1509 
1510   void ghash_modmul (FloatRegister result,
1511                      FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1512                      FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1513                      FloatRegister t1, FloatRegister t2, FloatRegister t3);
1514   void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1515 public:
1516   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1517                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1518                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1519   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1520   void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1521                       FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1522                       FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1523   void ghash_multiply_wide(int index,
1524                            FloatRegister result_lo, FloatRegister result_hi,
1525                            FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1526                            FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1527   void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1528                     FloatRegister p, FloatRegister z, FloatRegister t1);
1529   void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1530                     FloatRegister p, FloatRegister z, FloatRegister t1);
1531   void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1532                                 Register data, Register blocks, int unrolls);
1533 
1534 
1535   void aesenc_loadkeys(Register key, Register keylen);
1536   void aesecb_encrypt(Register from, Register to, Register keylen,
1537                       FloatRegister data = v0, int unrolls = 1);
1538   void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1539   void aes_round(FloatRegister input, FloatRegister subkey);
1540 
1541   // Place an ISB after code may have been modified due to a safepoint.
1542   void safepoint_isb();
1543 
1544 private:
1545   // Return the effective address r + (r1 << ext) + offset.
1546   // Uses rscratch2.
1547   Address offsetted_address(Register r, Register r1, Address::extend ext,
1548                             int offset, int size);
1549 
1550 private:
1551   // Returns an address on the stack which is reachable with a ldr/str of size
1552   // Uses rscratch2 if the address is not directly reachable
1553   Address spill_address(int size, int offset, Register tmp=rscratch2);
1554   Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1555 
1556   bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1557 
1558   // Check whether two loads/stores can be merged into ldp/stp.
1559   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1560 
1561   // Merge current load/store with previous load/store into ldp/stp.
1562   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1563 
1564   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1565   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1566 
1567 public:
1568   void spill(Register Rx, bool is64, int offset) {
1569     if (is64) {
1570       str(Rx, spill_address(8, offset));
1571     } else {
1572       strw(Rx, spill_address(4, offset));
1573     }
1574   }
1575   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1576     str(Vx, T, spill_address(1 << (int)T, offset));
1577   }
1578 
1579   void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1580     sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1581   }
1582   void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1583     sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1584   }
1585 
1586   void unspill(Register Rx, bool is64, int offset) {
1587     if (is64) {
1588       ldr(Rx, spill_address(8, offset));
1589     } else {
1590       ldrw(Rx, spill_address(4, offset));
1591     }
1592   }
1593   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1594     ldr(Vx, T, spill_address(1 << (int)T, offset));
1595   }
1596 
1597   void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1598     sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1599   }
1600   void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1601     sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1602   }
1603 
1604   void spill_copy128(int src_offset, int dst_offset,
1605                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1606     if (src_offset < 512 && (src_offset & 7) == 0 &&
1607         dst_offset < 512 && (dst_offset & 7) == 0) {
1608       ldp(tmp1, tmp2, Address(sp, src_offset));
1609       stp(tmp1, tmp2, Address(sp, dst_offset));
1610     } else {
1611       unspill(tmp1, true, src_offset);
1612       spill(tmp1, true, dst_offset);
1613       unspill(tmp1, true, src_offset+8);
1614       spill(tmp1, true, dst_offset+8);
1615     }
1616   }
1617   void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1618                                             int sve_vec_reg_size_in_bytes) {
1619     assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1620     for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1621       spill_copy128(src_offset, dst_offset);
1622       src_offset += 16;
1623       dst_offset += 16;
1624     }
1625   }
1626   void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1627                                                int sve_predicate_reg_size_in_bytes) {
1628     sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1629     sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1630     reinitialize_ptrue();
1631   }
1632   void cache_wb(Address line);
1633   void cache_wbsync(bool is_pre);
1634 
1635   // Code for java.lang.Thread::onSpinWait() intrinsic.
1636   void spin_wait();
1637 
1638 private:
1639   // Check the current thread doesn't need a cross modify fence.
1640   void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1641 
1642 };
1643 
1644 #ifdef ASSERT
1645 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1646 #endif
1647 
1648 /**
1649  * class SkipIfEqual:
1650  *
1651  * Instantiating this class will result in assembly code being output that will
1652  * jump around any code emitted between the creation of the instance and it's
1653  * automatic destruction at the end of a scope block, depending on the value of
1654  * the flag passed to the constructor, which will be checked at run-time.
1655  */
1656 class SkipIfEqual {
1657  private:
1658   MacroAssembler* _masm;
1659   Label _label;
1660 
1661  public:
1662    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1663    ~SkipIfEqual();
1664 };
1665 
1666 struct tableswitch {
1667   Register _reg;
1668   int _insn_index; jint _first_key; jint _last_key;
1669   Label _after;
1670   Label _branches;
1671 };
1672 
1673 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP