1 /* 2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP 27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP 28 29 #include "asm/assembler.inline.hpp" 30 #include "code/vmreg.hpp" 31 #include "metaprogramming/enableIf.hpp" 32 #include "oops/compressedOops.hpp" 33 #include "oops/compressedKlass.hpp" 34 #include "runtime/vm_version.hpp" 35 #include "utilities/macros.hpp" 36 #include "utilities/powerOfTwo.hpp" 37 #include "runtime/signature.hpp" 38 39 40 class ciInlineKlass; 41 42 class OopMap; 43 44 // MacroAssembler extends Assembler by frequently used macros. 45 // 46 // Instructions for which a 'better' code sequence exists depending 47 // on arguments should also go in here. 48 49 class MacroAssembler: public Assembler { 50 friend class LIR_Assembler; 51 52 public: 53 using Assembler::mov; 54 using Assembler::movi; 55 56 protected: 57 58 // Support for VM calls 59 // 60 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 61 // may customize this version by overriding it for its purposes (e.g., to save/restore 62 // additional registers when doing a VM call). 63 virtual void call_VM_leaf_base( 64 address entry_point, // the entry point 65 int number_of_arguments, // the number of arguments to pop after the call 66 Label *retaddr = nullptr 67 ); 68 69 virtual void call_VM_leaf_base( 70 address entry_point, // the entry point 71 int number_of_arguments, // the number of arguments to pop after the call 72 Label &retaddr) { 73 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr); 74 } 75 76 // This is the base routine called by the different versions of call_VM. The interpreter 77 // may customize this version by overriding it for its purposes (e.g., to save/restore 78 // additional registers when doing a VM call). 79 // 80 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base 81 // returns the register which contains the thread upon return. If a thread register has been 82 // specified, the return value will correspond to that register. If no last_java_sp is specified 83 // (noreg) than rsp will be used instead. 84 virtual void call_VM_base( // returns the register containing the thread upon return 85 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 86 Register java_thread, // the thread if computed before ; use noreg otherwise 87 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 88 address entry_point, // the entry point 89 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 90 bool check_exceptions // whether to check for pending exceptions after return 91 ); 92 93 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 94 95 enum KlassDecodeMode { 96 KlassDecodeNone, 97 KlassDecodeZero, 98 KlassDecodeXor, 99 KlassDecodeMovk 100 }; 101 102 KlassDecodeMode klass_decode_mode(); 103 104 private: 105 static KlassDecodeMode _klass_decode_mode; 106 107 public: 108 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 109 110 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 111 // The implementation is only non-empty for the InterpreterMacroAssembler, 112 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 113 virtual void check_and_handle_popframe(Register java_thread); 114 virtual void check_and_handle_earlyret(Register java_thread); 115 116 void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1); 117 void rt_call(address dest, Register tmp = rscratch1); 118 119 // Load Effective Address 120 void lea(Register r, const Address &a) { 121 InstructionMark im(this); 122 a.lea(this, r); 123 } 124 125 /* Sometimes we get misaligned loads and stores, usually from Unsafe 126 accesses, and these can exceed the offset range. */ 127 Address legitimize_address(const Address &a, int size, Register scratch) { 128 if (a.getMode() == Address::base_plus_offset) { 129 if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) { 130 block_comment("legitimize_address {"); 131 lea(scratch, a); 132 block_comment("} legitimize_address"); 133 return Address(scratch); 134 } 135 } 136 return a; 137 } 138 139 void addmw(Address a, Register incr, Register scratch) { 140 ldrw(scratch, a); 141 addw(scratch, scratch, incr); 142 strw(scratch, a); 143 } 144 145 // Add constant to memory word 146 void addmw(Address a, int imm, Register scratch) { 147 ldrw(scratch, a); 148 if (imm > 0) 149 addw(scratch, scratch, (unsigned)imm); 150 else 151 subw(scratch, scratch, (unsigned)-imm); 152 strw(scratch, a); 153 } 154 155 void bind(Label& L) { 156 Assembler::bind(L); 157 code()->clear_last_insn(); 158 code()->set_last_label(pc()); 159 } 160 161 void membar(Membar_mask_bits order_constraint); 162 163 using Assembler::ldr; 164 using Assembler::str; 165 using Assembler::ldrw; 166 using Assembler::strw; 167 168 void ldr(Register Rx, const Address &adr); 169 void ldrw(Register Rw, const Address &adr); 170 void str(Register Rx, const Address &adr); 171 void strw(Register Rx, const Address &adr); 172 173 // Frame creation and destruction shared between JITs. 174 void build_frame(int framesize); 175 void remove_frame(int framesize); 176 177 virtual void _call_Unimplemented(address call_site) { 178 mov(rscratch2, call_site); 179 } 180 181 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__ 182 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention." 183 // https://reviews.llvm.org/D3311 184 185 #ifdef _WIN64 186 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__) 187 #else 188 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__) 189 #endif 190 191 // aliases defined in AARCH64 spec 192 193 template<class T> 194 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); } 195 196 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); } 197 inline void cmp(Register Rd, unsigned imm) = delete; 198 199 template<class T> 200 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); } 201 202 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); } 203 inline void cmn(Register Rd, unsigned imm) = delete; 204 205 void cset(Register Rd, Assembler::Condition cond) { 206 csinc(Rd, zr, zr, ~cond); 207 } 208 void csetw(Register Rd, Assembler::Condition cond) { 209 csincw(Rd, zr, zr, ~cond); 210 } 211 212 void cneg(Register Rd, Register Rn, Assembler::Condition cond) { 213 csneg(Rd, Rn, Rn, ~cond); 214 } 215 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) { 216 csnegw(Rd, Rn, Rn, ~cond); 217 } 218 219 inline void movw(Register Rd, Register Rn) { 220 if (Rd == sp || Rn == sp) { 221 Assembler::addw(Rd, Rn, 0U); 222 } else { 223 orrw(Rd, zr, Rn); 224 } 225 } 226 inline void mov(Register Rd, Register Rn) { 227 assert(Rd != r31_sp && Rn != r31_sp, "should be"); 228 if (Rd == Rn) { 229 } else if (Rd == sp || Rn == sp) { 230 Assembler::add(Rd, Rn, 0U); 231 } else { 232 orr(Rd, zr, Rn); 233 } 234 } 235 236 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); } 237 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); } 238 239 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); } 240 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); } 241 242 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); } 243 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); } 244 245 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 246 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 247 } 248 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) { 249 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 250 } 251 252 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 253 bfmw(Rd, Rn, lsb, (lsb + width - 1)); 254 } 255 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) { 256 bfm(Rd, Rn, lsb , (lsb + width - 1)); 257 } 258 259 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 260 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 261 } 262 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 263 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 264 } 265 266 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 267 sbfmw(Rd, Rn, lsb, (lsb + width - 1)); 268 } 269 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 270 sbfm(Rd, Rn, lsb , (lsb + width - 1)); 271 } 272 273 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 274 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1)); 275 } 276 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) { 277 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1)); 278 } 279 280 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) { 281 ubfmw(Rd, Rn, lsb, (lsb + width - 1)); 282 } 283 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) { 284 ubfm(Rd, Rn, lsb , (lsb + width - 1)); 285 } 286 287 inline void asrw(Register Rd, Register Rn, unsigned imm) { 288 sbfmw(Rd, Rn, imm, 31); 289 } 290 291 inline void asr(Register Rd, Register Rn, unsigned imm) { 292 sbfm(Rd, Rn, imm, 63); 293 } 294 295 inline void lslw(Register Rd, Register Rn, unsigned imm) { 296 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm)); 297 } 298 299 inline void lsl(Register Rd, Register Rn, unsigned imm) { 300 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm)); 301 } 302 303 inline void lsrw(Register Rd, Register Rn, unsigned imm) { 304 ubfmw(Rd, Rn, imm, 31); 305 } 306 307 inline void lsr(Register Rd, Register Rn, unsigned imm) { 308 ubfm(Rd, Rn, imm, 63); 309 } 310 311 inline void rorw(Register Rd, Register Rn, unsigned imm) { 312 extrw(Rd, Rn, Rn, imm); 313 } 314 315 inline void ror(Register Rd, Register Rn, unsigned imm) { 316 extr(Rd, Rn, Rn, imm); 317 } 318 319 inline void sxtbw(Register Rd, Register Rn) { 320 sbfmw(Rd, Rn, 0, 7); 321 } 322 inline void sxthw(Register Rd, Register Rn) { 323 sbfmw(Rd, Rn, 0, 15); 324 } 325 inline void sxtb(Register Rd, Register Rn) { 326 sbfm(Rd, Rn, 0, 7); 327 } 328 inline void sxth(Register Rd, Register Rn) { 329 sbfm(Rd, Rn, 0, 15); 330 } 331 inline void sxtw(Register Rd, Register Rn) { 332 sbfm(Rd, Rn, 0, 31); 333 } 334 335 inline void uxtbw(Register Rd, Register Rn) { 336 ubfmw(Rd, Rn, 0, 7); 337 } 338 inline void uxthw(Register Rd, Register Rn) { 339 ubfmw(Rd, Rn, 0, 15); 340 } 341 inline void uxtb(Register Rd, Register Rn) { 342 ubfm(Rd, Rn, 0, 7); 343 } 344 inline void uxth(Register Rd, Register Rn) { 345 ubfm(Rd, Rn, 0, 15); 346 } 347 inline void uxtw(Register Rd, Register Rn) { 348 ubfm(Rd, Rn, 0, 31); 349 } 350 351 inline void cmnw(Register Rn, Register Rm) { 352 addsw(zr, Rn, Rm); 353 } 354 inline void cmn(Register Rn, Register Rm) { 355 adds(zr, Rn, Rm); 356 } 357 358 inline void cmpw(Register Rn, Register Rm) { 359 subsw(zr, Rn, Rm); 360 } 361 inline void cmp(Register Rn, Register Rm) { 362 subs(zr, Rn, Rm); 363 } 364 365 inline void negw(Register Rd, Register Rn) { 366 subw(Rd, zr, Rn); 367 } 368 369 inline void neg(Register Rd, Register Rn) { 370 sub(Rd, zr, Rn); 371 } 372 373 inline void negsw(Register Rd, Register Rn) { 374 subsw(Rd, zr, Rn); 375 } 376 377 inline void negs(Register Rd, Register Rn) { 378 subs(Rd, zr, Rn); 379 } 380 381 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 382 addsw(zr, Rn, Rm, kind, shift); 383 } 384 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 385 adds(zr, Rn, Rm, kind, shift); 386 } 387 388 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 389 subsw(zr, Rn, Rm, kind, shift); 390 } 391 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) { 392 subs(zr, Rn, Rm, kind, shift); 393 } 394 395 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 396 subw(Rd, zr, Rn, kind, shift); 397 } 398 399 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 400 sub(Rd, zr, Rn, kind, shift); 401 } 402 403 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 404 subsw(Rd, zr, Rn, kind, shift); 405 } 406 407 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) { 408 subs(Rd, zr, Rn, kind, shift); 409 } 410 411 inline void mnegw(Register Rd, Register Rn, Register Rm) { 412 msubw(Rd, Rn, Rm, zr); 413 } 414 inline void mneg(Register Rd, Register Rn, Register Rm) { 415 msub(Rd, Rn, Rm, zr); 416 } 417 418 inline void mulw(Register Rd, Register Rn, Register Rm) { 419 maddw(Rd, Rn, Rm, zr); 420 } 421 inline void mul(Register Rd, Register Rn, Register Rm) { 422 madd(Rd, Rn, Rm, zr); 423 } 424 425 inline void smnegl(Register Rd, Register Rn, Register Rm) { 426 smsubl(Rd, Rn, Rm, zr); 427 } 428 inline void smull(Register Rd, Register Rn, Register Rm) { 429 smaddl(Rd, Rn, Rm, zr); 430 } 431 432 inline void umnegl(Register Rd, Register Rn, Register Rm) { 433 umsubl(Rd, Rn, Rm, zr); 434 } 435 inline void umull(Register Rd, Register Rn, Register Rm) { 436 umaddl(Rd, Rn, Rm, zr); 437 } 438 439 #define WRAP(INSN) \ 440 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \ 441 if (VM_Version::supports_a53mac() && Ra != zr) \ 442 nop(); \ 443 Assembler::INSN(Rd, Rn, Rm, Ra); \ 444 } 445 446 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw) 447 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl) 448 #undef WRAP 449 450 451 // macro assembly operations needed for aarch64 452 453 public: 454 455 enum FpPushPopMode { 456 PushPopFull, 457 PushPopSVE, 458 PushPopNeon, 459 PushPopFp 460 }; 461 462 // first two private routines for loading 32 bit or 64 bit constants 463 private: 464 465 void mov_immediate64(Register dst, uint64_t imm64); 466 void mov_immediate32(Register dst, uint32_t imm32); 467 468 int push(unsigned int bitset, Register stack); 469 int pop(unsigned int bitset, Register stack); 470 471 int push_fp(unsigned int bitset, Register stack, FpPushPopMode mode); 472 int pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode); 473 474 int push_p(unsigned int bitset, Register stack); 475 int pop_p(unsigned int bitset, Register stack); 476 477 void mov(Register dst, Address a); 478 479 public: 480 481 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); } 482 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); } 483 484 void push_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) push_fp(regs.bits(), stack, mode); } 485 void pop_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) pop_fp(regs.bits(), stack, mode); } 486 487 static RegSet call_clobbered_gp_registers(); 488 489 void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); } 490 void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); } 491 492 // Push and pop everything that might be clobbered by a native 493 // runtime call except rscratch1 and rscratch2. (They are always 494 // scratch, so we don't have to protect them.) Only save the lower 495 // 64 bits of each vector register. Additional registers can be excluded 496 // in a passed RegSet. 497 void push_call_clobbered_registers_except(RegSet exclude); 498 void pop_call_clobbered_registers_except(RegSet exclude); 499 500 void push_call_clobbered_registers() { 501 push_call_clobbered_registers_except(RegSet()); 502 } 503 void pop_call_clobbered_registers() { 504 pop_call_clobbered_registers_except(RegSet()); 505 } 506 507 508 // now mov instructions for loading absolute addresses and 32 or 509 // 64 bit integers 510 511 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); } 512 513 template<typename T, ENABLE_IF(std::is_integral<T>::value)> 514 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); } 515 516 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); } 517 518 void mov(Register dst, RegisterOrConstant src) { 519 if (src.is_register()) 520 mov(dst, src.as_register()); 521 else 522 mov(dst, src.as_constant()); 523 } 524 525 void movptr(Register r, uintptr_t imm64); 526 527 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64); 528 529 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { 530 orr(Vd, T, Vn, Vn); 531 } 532 533 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) { 534 fcvtsh(tmp, src); 535 smov(dst, tmp, H, 0); 536 } 537 538 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) { 539 mov(tmp, H, 0, src); 540 fcvths(dst, tmp); 541 } 542 543 // Generalized Test Bit And Branch, including a "far" variety which 544 // spans more than 32KiB. 545 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) { 546 assert(cond == EQ || cond == NE, "must be"); 547 548 if (isfar) 549 cond = ~cond; 550 551 void (Assembler::* branch)(Register Rt, int bitpos, Label &L); 552 if (cond == Assembler::EQ) 553 branch = &Assembler::tbz; 554 else 555 branch = &Assembler::tbnz; 556 557 if (isfar) { 558 Label L; 559 (this->*branch)(Rt, bitpos, L); 560 b(dest); 561 bind(L); 562 } else { 563 (this->*branch)(Rt, bitpos, dest); 564 } 565 } 566 567 // macro instructions for accessing and updating floating point 568 // status register 569 // 570 // FPSR : op1 == 011 571 // CRn == 0100 572 // CRm == 0100 573 // op2 == 001 574 575 inline void get_fpsr(Register reg) 576 { 577 mrs(0b11, 0b0100, 0b0100, 0b001, reg); 578 } 579 580 inline void set_fpsr(Register reg) 581 { 582 msr(0b011, 0b0100, 0b0100, 0b001, reg); 583 } 584 585 inline void clear_fpsr() 586 { 587 msr(0b011, 0b0100, 0b0100, 0b001, zr); 588 } 589 590 // FPCR : op1 == 011 591 // CRn == 0100 592 // CRm == 0100 593 // op2 == 000 594 595 inline void get_fpcr(Register reg) { 596 mrs(0b11, 0b0100, 0b0100, 0b000, reg); 597 } 598 599 inline void set_fpcr(Register reg) { 600 msr(0b011, 0b0100, 0b0100, 0b000, reg); 601 } 602 603 // DCZID_EL0: op1 == 011 604 // CRn == 0000 605 // CRm == 0000 606 // op2 == 111 607 inline void get_dczid_el0(Register reg) 608 { 609 mrs(0b011, 0b0000, 0b0000, 0b111, reg); 610 } 611 612 // CTR_EL0: op1 == 011 613 // CRn == 0000 614 // CRm == 0000 615 // op2 == 001 616 inline void get_ctr_el0(Register reg) 617 { 618 mrs(0b011, 0b0000, 0b0000, 0b001, reg); 619 } 620 621 inline void get_nzcv(Register reg) { 622 mrs(0b011, 0b0100, 0b0010, 0b000, reg); 623 } 624 625 inline void set_nzcv(Register reg) { 626 msr(0b011, 0b0100, 0b0010, 0b000, reg); 627 } 628 629 // idiv variant which deals with MINLONG as dividend and -1 as divisor 630 int corrected_idivl(Register result, Register ra, Register rb, 631 bool want_remainder, Register tmp = rscratch1); 632 int corrected_idivq(Register result, Register ra, Register rb, 633 bool want_remainder, Register tmp = rscratch1); 634 635 // Support for null-checks 636 // 637 // Generates code that causes a null OS exception if the content of reg is null. 638 // If the accessed location is M[reg + offset] and the offset is known, provide the 639 // offset. No explicit code generation is needed if the offset is within a certain 640 // range (0 <= offset <= page_size). 641 642 virtual void null_check(Register reg, int offset = -1); 643 static bool needs_explicit_null_check(intptr_t offset); 644 static bool uses_implicit_null_check(void* address); 645 646 // markWord tests, kills markWord reg 647 void test_markword_is_inline_type(Register markword, Label& is_inline_type); 648 649 // inlineKlass queries, kills temp_reg 650 void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type); 651 void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type); 652 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type); 653 654 // Get the default value oop for the given InlineKlass 655 void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj); 656 // The empty value oop, for the given InlineKlass ("empty" as in no instance fields) 657 // get_default_value_oop with extra assertion for empty inline klass 658 void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj); 659 660 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free); 661 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free); 662 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat); 663 void test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker); 664 665 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays 666 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label); 667 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array); 668 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array); 669 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array); 670 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array); 671 672 // Check array klass layout helper for flat or null-free arrays... 673 void test_flat_array_layout(Register lh, Label& is_flat_array); 674 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array); 675 676 static address target_addr_for_insn(address insn_addr, unsigned insn); 677 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn); 678 static address target_addr_for_insn(address insn_addr) { 679 unsigned insn = *(unsigned*)insn_addr; 680 return target_addr_for_insn(insn_addr, insn); 681 } 682 static address target_addr_for_insn_or_null(address insn_addr) { 683 unsigned insn = *(unsigned*)insn_addr; 684 return target_addr_for_insn_or_null(insn_addr, insn); 685 } 686 687 // Required platform-specific helpers for Label::patch_instructions. 688 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 689 static int pd_patch_instruction_size(address branch, address target); 690 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) { 691 pd_patch_instruction_size(branch, target); 692 } 693 static address pd_call_destination(address branch) { 694 return target_addr_for_insn(branch); 695 } 696 #ifndef PRODUCT 697 static void pd_print_patched_instruction(address branch); 698 #endif 699 700 static int patch_oop(address insn_addr, address o); 701 static int patch_narrow_klass(address insn_addr, narrowKlass n); 702 703 // Return whether code is emitted to a scratch blob. 704 virtual bool in_scratch_emit_size() { 705 return false; 706 } 707 address emit_trampoline_stub(int insts_call_instruction_offset, address target); 708 static int max_trampoline_stub_size(); 709 void emit_static_call_stub(); 710 static int static_call_stub_size(); 711 712 // The following 4 methods return the offset of the appropriate move instruction 713 714 // Support for fast byte/short loading with zero extension (depending on particular CPU) 715 int load_unsigned_byte(Register dst, Address src); 716 int load_unsigned_short(Register dst, Address src); 717 718 // Support for fast byte/short loading with sign extension (depending on particular CPU) 719 int load_signed_byte(Register dst, Address src); 720 int load_signed_short(Register dst, Address src); 721 722 int load_signed_byte32(Register dst, Address src); 723 int load_signed_short32(Register dst, Address src); 724 725 // Support for sign-extension (hi:lo = extend_sign(lo)) 726 void extend_sign(Register hi, Register lo); 727 728 // Load and store values by size and signed-ness 729 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed); 730 void store_sized_value(Address dst, Register src, size_t size_in_bytes); 731 732 // Support for inc/dec with optimal instruction selection depending on value 733 734 // x86_64 aliases an unqualified register/address increment and 735 // decrement to call incrementq and decrementq but also supports 736 // explicitly sized calls to incrementq/decrementq or 737 // incrementl/decrementl 738 739 // for aarch64 the proper convention would be to use 740 // increment/decrement for 64 bit operations and 741 // incrementw/decrementw for 32 bit operations. so when porting 742 // x86_64 code we can leave calls to increment/decrement as is, 743 // replace incrementq/decrementq with increment/decrement and 744 // replace incrementl/decrementl with incrementw/decrementw. 745 746 // n.b. increment/decrement calls with an Address destination will 747 // need to use a scratch register to load the value to be 748 // incremented. increment/decrement calls which add or subtract a 749 // constant value greater than 2^12 will need to use a 2nd scratch 750 // register to hold the constant. so, a register increment/decrement 751 // may trash rscratch2 and an address increment/decrement trash 752 // rscratch and rscratch2 753 754 void decrementw(Address dst, int value = 1); 755 void decrementw(Register reg, int value = 1); 756 757 void decrement(Register reg, int value = 1); 758 void decrement(Address dst, int value = 1); 759 760 void incrementw(Address dst, int value = 1); 761 void incrementw(Register reg, int value = 1); 762 763 void increment(Register reg, int value = 1); 764 void increment(Address dst, int value = 1); 765 766 767 // Alignment 768 void align(int modulus); 769 void align(int modulus, int target); 770 771 // nop 772 void post_call_nop(); 773 774 // Stack frame creation/removal 775 void enter(bool strip_ret_addr = false); 776 void leave(); 777 778 // ROP Protection 779 void protect_return_address(); 780 void protect_return_address(Register return_reg); 781 void authenticate_return_address(); 782 void authenticate_return_address(Register return_reg); 783 void strip_return_address(); 784 void check_return_address(Register return_reg=lr) PRODUCT_RETURN; 785 786 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 787 // The pointer will be loaded into the thread register. 788 void get_thread(Register thread); 789 790 // support for argument shuffling 791 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1); 792 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1); 793 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1); 794 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1); 795 void object_move( 796 OopMap* map, 797 int oop_handle_offset, 798 int framesize_in_slots, 799 VMRegPair src, 800 VMRegPair dst, 801 bool is_receiver, 802 int* receiver_offset); 803 804 805 // Support for VM calls 806 // 807 // It is imperative that all calls into the VM are handled via the call_VM macros. 808 // They make sure that the stack linkage is setup correctly. call_VM's correspond 809 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 810 811 812 void call_VM(Register oop_result, 813 address entry_point, 814 bool check_exceptions = true); 815 void call_VM(Register oop_result, 816 address entry_point, 817 Register arg_1, 818 bool check_exceptions = true); 819 void call_VM(Register oop_result, 820 address entry_point, 821 Register arg_1, Register arg_2, 822 bool check_exceptions = true); 823 void call_VM(Register oop_result, 824 address entry_point, 825 Register arg_1, Register arg_2, Register arg_3, 826 bool check_exceptions = true); 827 828 // Overloadings with last_Java_sp 829 void call_VM(Register oop_result, 830 Register last_java_sp, 831 address entry_point, 832 int number_of_arguments = 0, 833 bool check_exceptions = true); 834 void call_VM(Register oop_result, 835 Register last_java_sp, 836 address entry_point, 837 Register arg_1, bool 838 check_exceptions = true); 839 void call_VM(Register oop_result, 840 Register last_java_sp, 841 address entry_point, 842 Register arg_1, Register arg_2, 843 bool check_exceptions = true); 844 void call_VM(Register oop_result, 845 Register last_java_sp, 846 address entry_point, 847 Register arg_1, Register arg_2, Register arg_3, 848 bool check_exceptions = true); 849 850 void get_vm_result (Register oop_result, Register thread); 851 void get_vm_result_2(Register metadata_result, Register thread); 852 853 // These always tightly bind to MacroAssembler::call_VM_base 854 // bypassing the virtual implementation 855 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 856 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 857 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 858 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 859 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 860 861 void call_VM_leaf(address entry_point, 862 int number_of_arguments = 0); 863 void call_VM_leaf(address entry_point, 864 Register arg_1); 865 void call_VM_leaf(address entry_point, 866 Register arg_1, Register arg_2); 867 void call_VM_leaf(address entry_point, 868 Register arg_1, Register arg_2, Register arg_3); 869 870 // These always tightly bind to MacroAssembler::call_VM_leaf_base 871 // bypassing the virtual implementation 872 void super_call_VM_leaf(address entry_point); 873 void super_call_VM_leaf(address entry_point, Register arg_1); 874 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 875 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 876 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 877 878 // last Java Frame (fills frame anchor) 879 void set_last_Java_frame(Register last_java_sp, 880 Register last_java_fp, 881 address last_java_pc, 882 Register scratch); 883 884 void set_last_Java_frame(Register last_java_sp, 885 Register last_java_fp, 886 Label &last_java_pc, 887 Register scratch); 888 889 void set_last_Java_frame(Register last_java_sp, 890 Register last_java_fp, 891 Register last_java_pc, 892 Register scratch); 893 894 void reset_last_Java_frame(Register thread); 895 896 // thread in the default location (rthread) 897 void reset_last_Java_frame(bool clear_fp); 898 899 // Stores 900 void store_check(Register obj); // store check for obj - register is destroyed afterwards 901 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 902 903 void resolve_jobject(Register value, Register tmp1, Register tmp2); 904 void resolve_global_jobject(Register value, Register tmp1, Register tmp2); 905 906 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 907 void c2bool(Register x); 908 909 void load_method_holder_cld(Register rresult, Register rmethod); 910 void load_method_holder(Register holder, Register method); 911 912 // oop manipulations 913 void load_metadata(Register dst, Register src); 914 915 void load_klass(Register dst, Register src); 916 void store_klass(Register dst, Register src); 917 void cmp_klass(Register oop, Register trial_klass, Register tmp); 918 919 void resolve_weak_handle(Register result, Register tmp1, Register tmp2); 920 void resolve_oop_handle(Register result, Register tmp1, Register tmp2); 921 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2); 922 923 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src, 924 Register tmp1, Register tmp2); 925 926 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val, 927 Register tmp1, Register tmp2, Register tmp3); 928 929 void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register inline_klass); 930 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info); 931 932 // inline type data payload offsets... 933 void first_field_offset(Register inline_klass, Register offset); 934 void data_for_oop(Register oop, Register data, Register inline_klass); 935 // get data payload ptr a flat value array at index, kills rcx and index 936 void data_for_value_array_index(Register array, Register array_klass, 937 Register index, Register data); 938 939 void load_heap_oop(Register dst, Address src, Register tmp1, 940 Register tmp2, DecoratorSet decorators = 0); 941 942 void load_heap_oop_not_null(Register dst, Address src, Register tmp1, 943 Register tmp2, DecoratorSet decorators = 0); 944 void store_heap_oop(Address dst, Register val, Register tmp1, 945 Register tmp2, Register tmp3, DecoratorSet decorators = 0); 946 947 // currently unimplemented 948 // Used for storing null. All other oop constants should be 949 // stored using routines that take a jobject. 950 void store_heap_oop_null(Address dst); 951 952 void load_prototype_header(Register dst, Register src); 953 954 void store_klass_gap(Register dst, Register src); 955 956 // This dummy is to prevent a call to store_heap_oop from 957 // converting a zero (like null) into a Register by giving 958 // the compiler two choices it can't resolve 959 960 void store_heap_oop(Address dst, void* dummy); 961 962 void encode_heap_oop(Register d, Register s); 963 void encode_heap_oop(Register r) { encode_heap_oop(r, r); } 964 void decode_heap_oop(Register d, Register s); 965 void decode_heap_oop(Register r) { decode_heap_oop(r, r); } 966 void encode_heap_oop_not_null(Register r); 967 void decode_heap_oop_not_null(Register r); 968 void encode_heap_oop_not_null(Register dst, Register src); 969 void decode_heap_oop_not_null(Register dst, Register src); 970 971 void set_narrow_oop(Register dst, jobject obj); 972 973 void encode_klass_not_null(Register r); 974 void decode_klass_not_null(Register r); 975 void encode_klass_not_null(Register dst, Register src); 976 void decode_klass_not_null(Register dst, Register src); 977 978 void set_narrow_klass(Register dst, Klass* k); 979 980 // if heap base register is used - reinit it with the correct value 981 void reinit_heapbase(); 982 983 DEBUG_ONLY(void verify_heapbase(const char* msg);) 984 985 void push_CPU_state(bool save_vectors = false, bool use_sve = false, 986 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0); 987 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false, 988 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0); 989 990 void push_cont_fastpath(Register java_thread); 991 void pop_cont_fastpath(Register java_thread); 992 993 // Round up to a power of two 994 void round_to(Register reg, int modulus); 995 996 // java.lang.Math::round intrinsics 997 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp); 998 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp); 999 1000 // allocation 1001 1002 // Object / value buffer allocation... 1003 // Allocate instance of klass, assumes klass initialized by caller 1004 // new_obj prefers to be rax 1005 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64) 1006 void allocate_instance(Register klass, Register new_obj, 1007 Register t1, Register t2, 1008 bool clear_fields, Label& alloc_failed); 1009 1010 void tlab_allocate( 1011 Register obj, // result: pointer to object after successful allocation 1012 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 1013 int con_size_in_bytes, // object size in bytes if known at compile time 1014 Register t1, // temp register 1015 Register t2, // temp register 1016 Label& slow_case // continuation point if fast allocation fails 1017 ); 1018 void verify_tlab(); 1019 1020 // For field "index" within "klass", return inline_klass ... 1021 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass); 1022 void inline_layout_info(Register holder_klass, Register index, Register layout_info); 1023 1024 1025 // interface method calling 1026 void lookup_interface_method(Register recv_klass, 1027 Register intf_klass, 1028 RegisterOrConstant itable_index, 1029 Register method_result, 1030 Register scan_temp, 1031 Label& no_such_interface, 1032 bool return_method = true); 1033 1034 void lookup_interface_method_stub(Register recv_klass, 1035 Register holder_klass, 1036 Register resolved_klass, 1037 Register method_result, 1038 Register temp_reg, 1039 Register temp_reg2, 1040 int itable_index, 1041 Label& L_no_such_interface); 1042 1043 // virtual method calling 1044 // n.b. x86 allows RegisterOrConstant for vtable_index 1045 void lookup_virtual_method(Register recv_klass, 1046 RegisterOrConstant vtable_index, 1047 Register method_result); 1048 1049 // Test sub_klass against super_klass, with fast and slow paths. 1050 1051 // The fast path produces a tri-state answer: yes / no / maybe-slow. 1052 // One of the three labels can be null, meaning take the fall-through. 1053 // If super_check_offset is -1, the value is loaded up from super_klass. 1054 // No registers are killed, except temp_reg. 1055 void check_klass_subtype_fast_path(Register sub_klass, 1056 Register super_klass, 1057 Register temp_reg, 1058 Label* L_success, 1059 Label* L_failure, 1060 Label* L_slow_path, 1061 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 1062 1063 // The rest of the type check; must be wired to a corresponding fast path. 1064 // It does not repeat the fast path logic, so don't use it standalone. 1065 // The temp_reg and temp2_reg can be noreg, if no temps are available. 1066 // Updates the sub's secondary super cache as necessary. 1067 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 1068 void check_klass_subtype_slow_path(Register sub_klass, 1069 Register super_klass, 1070 Register temp_reg, 1071 Register temp2_reg, 1072 Label* L_success, 1073 Label* L_failure, 1074 bool set_cond_codes = false); 1075 1076 // As above, but with a constant super_klass. 1077 // The result is in Register result, not the condition codes. 1078 bool lookup_secondary_supers_table(Register r_sub_klass, 1079 Register r_super_klass, 1080 Register temp1, 1081 Register temp2, 1082 Register temp3, 1083 FloatRegister vtemp, 1084 Register result, 1085 u1 super_klass_slot, 1086 bool stub_is_near = false); 1087 1088 void verify_secondary_supers_table(Register r_sub_klass, 1089 Register r_super_klass, 1090 Register temp1, 1091 Register temp2, 1092 Register result); 1093 1094 void lookup_secondary_supers_table_slow_path(Register r_super_klass, 1095 Register r_array_base, 1096 Register r_array_index, 1097 Register r_bitmap, 1098 Register temp1, 1099 Register result); 1100 1101 // Simplified, combined version, good for typical uses. 1102 // Falls through on failure. 1103 void check_klass_subtype(Register sub_klass, 1104 Register super_klass, 1105 Register temp_reg, 1106 Label& L_success); 1107 1108 void clinit_barrier(Register klass, 1109 Register thread, 1110 Label* L_fast_path = nullptr, 1111 Label* L_slow_path = nullptr); 1112 1113 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 1114 1115 void verify_sve_vector_length(Register tmp = rscratch1); 1116 void reinitialize_ptrue() { 1117 if (UseSVE > 0) { 1118 sve_ptrue(ptrue, B); 1119 } 1120 } 1121 void verify_ptrue(); 1122 1123 // Debugging 1124 1125 // only if +VerifyOops 1126 void _verify_oop(Register reg, const char* s, const char* file, int line); 1127 void _verify_oop_addr(Address addr, const char * s, const char* file, int line); 1128 1129 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) { 1130 if (VerifyOops) { 1131 _verify_oop(reg, s, file, line); 1132 } 1133 } 1134 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) { 1135 if (VerifyOops) { 1136 _verify_oop_addr(reg, s, file, line); 1137 } 1138 } 1139 1140 // TODO: verify method and klass metadata (compare against vptr?) 1141 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 1142 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 1143 1144 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__) 1145 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__) 1146 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__) 1147 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 1148 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 1149 1150 // Restore cpu control state after JNI call 1151 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2); 1152 1153 // prints msg, dumps registers and stops execution 1154 void stop(const char* msg); 1155 1156 static void debug64(char* msg, int64_t pc, int64_t regs[]); 1157 1158 void untested() { stop("untested"); } 1159 1160 void unimplemented(const char* what = ""); 1161 1162 void should_not_reach_here() { stop("should not reach here"); } 1163 1164 void _assert_asm(Condition cc, const char* msg); 1165 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg) 1166 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg)) 1167 1168 // Stack overflow checking 1169 void bang_stack_with_offset(int offset) { 1170 // stack grows down, caller passes positive offset 1171 assert(offset > 0, "must bang with negative offset"); 1172 sub(rscratch2, sp, offset); 1173 str(zr, Address(rscratch2)); 1174 } 1175 1176 // Writes to stack successive pages until offset reached to check for 1177 // stack overflow + shadow pages. Also, clobbers tmp 1178 void bang_stack_size(Register size, Register tmp); 1179 1180 // Check for reserved stack access in method being exited (for JIT) 1181 void reserved_stack_check(); 1182 1183 // Arithmetics 1184 1185 void addptr(const Address &dst, int32_t src); 1186 void cmpptr(Register src1, Address src2); 1187 1188 void cmpoop(Register obj1, Register obj2); 1189 1190 // Various forms of CAS 1191 1192 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp, 1193 Label &succeed, Label *fail); 1194 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 1195 Label &succeed, Label *fail); 1196 1197 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 1198 Label &succeed, Label *fail); 1199 1200 void atomic_add(Register prev, RegisterOrConstant incr, Register addr); 1201 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr); 1202 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr); 1203 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr); 1204 1205 void atomic_xchg(Register prev, Register newv, Register addr); 1206 void atomic_xchgw(Register prev, Register newv, Register addr); 1207 void atomic_xchgl(Register prev, Register newv, Register addr); 1208 void atomic_xchglw(Register prev, Register newv, Register addr); 1209 void atomic_xchgal(Register prev, Register newv, Register addr); 1210 void atomic_xchgalw(Register prev, Register newv, Register addr); 1211 1212 void orptr(Address adr, RegisterOrConstant src) { 1213 ldr(rscratch1, adr); 1214 if (src.is_register()) 1215 orr(rscratch1, rscratch1, src.as_register()); 1216 else 1217 orr(rscratch1, rscratch1, src.as_constant()); 1218 str(rscratch1, adr); 1219 } 1220 1221 // A generic CAS; success or failure is in the EQ flag. 1222 // Clobbers rscratch1 1223 void cmpxchg(Register addr, Register expected, Register new_val, 1224 enum operand_size size, 1225 bool acquire, bool release, bool weak, 1226 Register result); 1227 1228 #ifdef ASSERT 1229 // Template short-hand support to clean-up after a failed call to trampoline 1230 // call generation (see trampoline_call() below), when a set of Labels must 1231 // be reset (before returning). 1232 template<typename Label, typename... More> 1233 void reset_labels(Label &lbl, More&... more) { 1234 lbl.reset(); reset_labels(more...); 1235 } 1236 template<typename Label> 1237 void reset_labels(Label &lbl) { 1238 lbl.reset(); 1239 } 1240 #endif 1241 1242 private: 1243 void compare_eq(Register rn, Register rm, enum operand_size size); 1244 1245 public: 1246 // AArch64 OpenJDK uses four different types of calls: 1247 // - direct call: bl pc_relative_offset 1248 // This is the shortest and the fastest, but the offset has the range: 1249 // +/-128MB for the release build, +/-2MB for the debug build. 1250 // 1251 // - far call: adrp reg, pc_relative_offset; add; bl reg 1252 // This is longer than a direct call. The offset has 1253 // the range +/-4GB. As the code cache size is limited to 4GB, 1254 // far calls can reach anywhere in the code cache. If a jump is 1255 // needed rather than a call, a far jump 'b reg' can be used instead. 1256 // All instructions are embedded at a call site. 1257 // 1258 // - trampoline call: 1259 // This is only available in C1/C2-generated code (nmethod). It is a combination 1260 // of a direct call, which is used if the destination of a call is in range, 1261 // and a register-indirect call. It has the advantages of reaching anywhere in 1262 // the AArch64 address space and being patchable at runtime when the generated 1263 // code is being executed by other threads. 1264 // 1265 // [Main code section] 1266 // bl trampoline 1267 // [Stub code section] 1268 // trampoline: 1269 // ldr reg, pc + 8 1270 // br reg 1271 // <64-bit destination address> 1272 // 1273 // If the destination is in range when the generated code is moved to the code 1274 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline 1275 // is not used. 1276 // The optimization does not remove the trampoline from the stub section. 1277 // This is necessary because the trampoline may well be redirected later when 1278 // code is patched, and the new destination may not be reachable by a simple BR 1279 // instruction. 1280 // 1281 // - indirect call: move reg, address; blr reg 1282 // This too can reach anywhere in the address space, but it cannot be 1283 // patched while code is running, so it must only be modified at a safepoint. 1284 // This form of call is most suitable for targets at fixed addresses, which 1285 // will never be patched. 1286 // 1287 // The patching we do conforms to the "Concurrent modification and 1288 // execution of instructions" section of the Arm Architectural 1289 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC, 1290 // or SVC instructions to be modified while another thread is 1291 // executing them. 1292 // 1293 // To patch a trampoline call when the BL can't reach, we first modify 1294 // the 64-bit destination address in the trampoline, then modify the 1295 // BL to point to the trampoline, then flush the instruction cache to 1296 // broadcast the change to all executing threads. See 1297 // NativeCall::set_destination_mt_safe for the details. 1298 // 1299 // There is a benign race in that the other thread might observe the 1300 // modified BL before it observes the modified 64-bit destination 1301 // address. That does not matter because the destination method has been 1302 // invalidated, so there will be a trap at its start. 1303 // For this to work, the destination address in the trampoline is 1304 // always updated, even if we're not using the trampoline. 1305 1306 // Emit a direct call if the entry address will always be in range, 1307 // otherwise a trampoline call. 1308 // Supported entry.rspec(): 1309 // - relocInfo::runtime_call_type 1310 // - relocInfo::opt_virtual_call_type 1311 // - relocInfo::static_call_type 1312 // - relocInfo::virtual_call_type 1313 // 1314 // Return: the call PC or null if CodeCache is full. 1315 // Clobbers: rscratch1 1316 address trampoline_call(Address entry); 1317 1318 static bool far_branches() { 1319 return ReservedCodeCacheSize > branch_range; 1320 } 1321 1322 // Check if branches to the non nmethod section require a far jump 1323 static bool codestub_branch_needs_far_jump() { 1324 return CodeCache::max_distance_to_non_nmethod() > branch_range; 1325 } 1326 1327 // Emit a direct call/jump if the entry address will always be in range, 1328 // otherwise a far call/jump. 1329 // The address must be inside the code cache. 1330 // Supported entry.rspec(): 1331 // - relocInfo::external_word_type 1332 // - relocInfo::runtime_call_type 1333 // - relocInfo::none 1334 // In the case of a far call/jump, the entry address is put in the tmp register. 1335 // The tmp register is invalidated. 1336 // 1337 // Far_jump returns the amount of the emitted code. 1338 void far_call(Address entry, Register tmp = rscratch1); 1339 int far_jump(Address entry, Register tmp = rscratch1); 1340 1341 static int far_codestub_branch_size() { 1342 if (codestub_branch_needs_far_jump()) { 1343 return 3 * 4; // adrp, add, br 1344 } else { 1345 return 4; 1346 } 1347 } 1348 1349 // Emit the CompiledIC call idiom 1350 address ic_call(address entry, jint method_index = 0); 1351 static int ic_check_size(); 1352 int ic_check(int end_alignment); 1353 1354 public: 1355 1356 // Data 1357 1358 void mov_metadata(Register dst, Metadata* obj); 1359 Address allocate_metadata_address(Metadata* obj); 1360 Address constant_oop_address(jobject obj); 1361 1362 void movoop(Register dst, jobject obj); 1363 1364 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic. 1365 void kernel_crc32(Register crc, Register buf, Register len, 1366 Register table0, Register table1, Register table2, Register table3, 1367 Register tmp, Register tmp2, Register tmp3); 1368 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic. 1369 void kernel_crc32c(Register crc, Register buf, Register len, 1370 Register table0, Register table1, Register table2, Register table3, 1371 Register tmp, Register tmp2, Register tmp3); 1372 1373 // Stack push and pop individual 64 bit registers 1374 void push(Register src); 1375 void pop(Register dst); 1376 1377 void repne_scan(Register addr, Register value, Register count, 1378 Register scratch); 1379 void repne_scanw(Register addr, Register value, Register count, 1380 Register scratch); 1381 1382 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm); 1383 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift); 1384 1385 // If a constant does not fit in an immediate field, generate some 1386 // number of MOV instructions and then perform the operation 1387 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm, 1388 add_sub_imm_insn insn1, 1389 add_sub_reg_insn insn2, bool is32); 1390 // Separate vsn which sets the flags 1391 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm, 1392 add_sub_imm_insn insn1, 1393 add_sub_reg_insn insn2, bool is32); 1394 1395 #define WRAP(INSN, is32) \ 1396 void INSN(Register Rd, Register Rn, uint64_t imm) { \ 1397 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \ 1398 } \ 1399 \ 1400 void INSN(Register Rd, Register Rn, Register Rm, \ 1401 enum shift_kind kind, unsigned shift = 0) { \ 1402 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1403 } \ 1404 \ 1405 void INSN(Register Rd, Register Rn, Register Rm) { \ 1406 Assembler::INSN(Rd, Rn, Rm); \ 1407 } \ 1408 \ 1409 void INSN(Register Rd, Register Rn, Register Rm, \ 1410 ext::operation option, int amount = 0) { \ 1411 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1412 } 1413 1414 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true) 1415 1416 #undef WRAP 1417 #define WRAP(INSN, is32) \ 1418 void INSN(Register Rd, Register Rn, uint64_t imm) { \ 1419 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \ 1420 } \ 1421 \ 1422 void INSN(Register Rd, Register Rn, Register Rm, \ 1423 enum shift_kind kind, unsigned shift = 0) { \ 1424 Assembler::INSN(Rd, Rn, Rm, kind, shift); \ 1425 } \ 1426 \ 1427 void INSN(Register Rd, Register Rn, Register Rm) { \ 1428 Assembler::INSN(Rd, Rn, Rm); \ 1429 } \ 1430 \ 1431 void INSN(Register Rd, Register Rn, Register Rm, \ 1432 ext::operation option, int amount = 0) { \ 1433 Assembler::INSN(Rd, Rn, Rm, option, amount); \ 1434 } 1435 1436 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true) 1437 1438 void add(Register Rd, Register Rn, RegisterOrConstant increment); 1439 void addw(Register Rd, Register Rn, RegisterOrConstant increment); 1440 void sub(Register Rd, Register Rn, RegisterOrConstant decrement); 1441 void subw(Register Rd, Register Rn, RegisterOrConstant decrement); 1442 1443 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset); 1444 1445 void verified_entry(Compile* C, int sp_inc); 1446 1447 // Inline type specific methods 1448 #include "asm/macroAssembler_common.hpp" 1449 1450 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true); 1451 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]); 1452 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, 1453 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index, 1454 RegState reg_state[]); 1455 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index, 1456 VMRegPair* from, int from_count, int& from_index, VMReg to, 1457 RegState reg_state[], Register val_array); 1458 int extend_stack_for_inline_args(int args_on_stack); 1459 void remove_frame(int initial_framesize, bool needs_stack_repair); 1460 VMReg spill_reg_for(VMReg reg); 1461 void save_stack_increment(int sp_inc, int frame_size); 1462 1463 void tableswitch(Register index, jint lowbound, jint highbound, 1464 Label &jumptable, Label &jumptable_end, int stride = 1) { 1465 adr(rscratch1, jumptable); 1466 subsw(rscratch2, index, lowbound); 1467 subsw(zr, rscratch2, highbound - lowbound); 1468 br(Assembler::HS, jumptable_end); 1469 add(rscratch1, rscratch1, rscratch2, 1470 ext::sxtw, exact_log2(stride * Assembler::instruction_size)); 1471 br(rscratch1); 1472 } 1473 1474 // Form an address from base + offset in Rd. Rd may or may not 1475 // actually be used: you must use the Address that is returned. It 1476 // is up to you to ensure that the shift provided matches the size 1477 // of your data. 1478 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift); 1479 1480 // Return true iff an address is within the 48-bit AArch64 address 1481 // space. 1482 bool is_valid_AArch64_address(address a) { 1483 return ((uint64_t)a >> 48) == 0; 1484 } 1485 1486 // Load the base of the cardtable byte map into reg. 1487 void load_byte_map_base(Register reg); 1488 1489 // Prolog generator routines to support switch between x86 code and 1490 // generated ARM code 1491 1492 // routine to generate an x86 prolog for a stub function which 1493 // bootstraps into the generated ARM code which directly follows the 1494 // stub 1495 // 1496 1497 public: 1498 1499 void ldr_constant(Register dest, const Address &const_addr) { 1500 if (NearCpool) { 1501 ldr(dest, const_addr); 1502 } else { 1503 uint64_t offset; 1504 adrp(dest, InternalAddress(const_addr.target()), offset); 1505 ldr(dest, Address(dest, offset)); 1506 } 1507 } 1508 1509 address read_polling_page(Register r, relocInfo::relocType rtype); 1510 void get_polling_page(Register dest, relocInfo::relocType rtype); 1511 1512 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic. 1513 void update_byte_crc32(Register crc, Register val, Register table); 1514 void update_word_crc32(Register crc, Register v, Register tmp, 1515 Register table0, Register table1, Register table2, Register table3, 1516 bool upper = false); 1517 1518 address count_positives(Register ary1, Register len, Register result); 1519 1520 address arrays_equals(Register a1, Register a2, Register result, Register cnt1, 1521 Register tmp1, Register tmp2, Register tmp3, int elem_size); 1522 1523 void string_equals(Register a1, Register a2, Register result, Register cnt1); 1524 1525 void fill_words(Register base, Register cnt, Register value); 1526 void fill_words(Register base, uint64_t cnt, Register value); 1527 1528 address zero_words(Register base, uint64_t cnt); 1529 address zero_words(Register ptr, Register cnt); 1530 void zero_dcache_blocks(Register base, Register cnt); 1531 1532 static const int zero_words_block_size; 1533 1534 address byte_array_inflate(Register src, Register dst, Register len, 1535 FloatRegister vtmp1, FloatRegister vtmp2, 1536 FloatRegister vtmp3, Register tmp4); 1537 1538 void char_array_compress(Register src, Register dst, Register len, 1539 Register res, 1540 FloatRegister vtmp0, FloatRegister vtmp1, 1541 FloatRegister vtmp2, FloatRegister vtmp3, 1542 FloatRegister vtmp4, FloatRegister vtmp5); 1543 1544 void encode_iso_array(Register src, Register dst, 1545 Register len, Register res, bool ascii, 1546 FloatRegister vtmp0, FloatRegister vtmp1, 1547 FloatRegister vtmp2, FloatRegister vtmp3, 1548 FloatRegister vtmp4, FloatRegister vtmp5); 1549 1550 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi, 1551 address pio2, address dsin_coef, address dcos_coef); 1552 private: 1553 // begin trigonometric functions support block 1554 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2); 1555 void generate__kernel_rem_pio2(address two_over_pi, address pio2); 1556 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef); 1557 void generate_kernel_cos(FloatRegister x, address dcos_coef); 1558 // end trigonometric functions support block 1559 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 1560 Register src1, Register src2); 1561 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 1562 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2); 1563 } 1564 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 1565 Register y, Register y_idx, Register z, 1566 Register carry, Register product, 1567 Register idx, Register kdx); 1568 void multiply_128_x_128_loop(Register y, Register z, 1569 Register carry, Register carry2, 1570 Register idx, Register jdx, 1571 Register yz_idx1, Register yz_idx2, 1572 Register tmp, Register tmp3, Register tmp4, 1573 Register tmp7, Register product_hi); 1574 void kernel_crc32_using_crypto_pmull(Register crc, Register buf, 1575 Register len, Register tmp0, Register tmp1, Register tmp2, 1576 Register tmp3); 1577 void kernel_crc32_using_crc32(Register crc, Register buf, 1578 Register len, Register tmp0, Register tmp1, Register tmp2, 1579 Register tmp3); 1580 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf, 1581 Register len, Register tmp0, Register tmp1, Register tmp2, 1582 Register tmp3); 1583 void kernel_crc32c_using_crc32c(Register crc, Register buf, 1584 Register len, Register tmp0, Register tmp1, Register tmp2, 1585 Register tmp3); 1586 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf, 1587 Register len, Register tmp0, Register tmp1, Register tmp2, 1588 size_t table_offset); 1589 1590 void ghash_modmul (FloatRegister result, 1591 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b, 1592 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p, 1593 FloatRegister t1, FloatRegister t2, FloatRegister t3); 1594 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state); 1595 public: 1596 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, 1597 Register tmp0, Register tmp1, Register tmp2, Register tmp3, 1598 Register tmp4, Register tmp5, Register tmp6, Register tmp7); 1599 void mul_add(Register out, Register in, Register offs, Register len, Register k); 1600 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi, 1601 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0, 1602 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3); 1603 void ghash_multiply_wide(int index, 1604 FloatRegister result_lo, FloatRegister result_hi, 1605 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0, 1606 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3); 1607 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi, 1608 FloatRegister p, FloatRegister z, FloatRegister t1); 1609 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi, 1610 FloatRegister p, FloatRegister z, FloatRegister t1); 1611 void ghash_processBlocks_wide(address p, Register state, Register subkeyH, 1612 Register data, Register blocks, int unrolls); 1613 1614 1615 void aesenc_loadkeys(Register key, Register keylen); 1616 void aesecb_encrypt(Register from, Register to, Register keylen, 1617 FloatRegister data = v0, int unrolls = 1); 1618 void aesecb_decrypt(Register from, Register to, Register key, Register keylen); 1619 void aes_round(FloatRegister input, FloatRegister subkey); 1620 1621 // ChaCha20 functions support block 1622 void cc20_quarter_round(FloatRegister aVec, FloatRegister bVec, 1623 FloatRegister cVec, FloatRegister dVec, FloatRegister scratch, 1624 FloatRegister tbl); 1625 void cc20_shift_lane_org(FloatRegister bVec, FloatRegister cVec, 1626 FloatRegister dVec, bool colToDiag); 1627 1628 // Place an ISB after code may have been modified due to a safepoint. 1629 void safepoint_isb(); 1630 1631 private: 1632 // Return the effective address r + (r1 << ext) + offset. 1633 // Uses rscratch2. 1634 Address offsetted_address(Register r, Register r1, Address::extend ext, 1635 int offset, int size); 1636 1637 private: 1638 // Returns an address on the stack which is reachable with a ldr/str of size 1639 // Uses rscratch2 if the address is not directly reachable 1640 Address spill_address(int size, int offset, Register tmp=rscratch2); 1641 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2); 1642 1643 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const; 1644 1645 // Check whether two loads/stores can be merged into ldp/stp. 1646 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const; 1647 1648 // Merge current load/store with previous load/store into ldp/stp. 1649 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store); 1650 1651 // Try to merge two loads/stores into ldp/stp. If success, returns true else false. 1652 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store); 1653 1654 public: 1655 void spill(Register Rx, bool is64, int offset) { 1656 if (is64) { 1657 str(Rx, spill_address(8, offset)); 1658 } else { 1659 strw(Rx, spill_address(4, offset)); 1660 } 1661 } 1662 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) { 1663 str(Vx, T, spill_address(1 << (int)T, offset)); 1664 } 1665 1666 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) { 1667 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset)); 1668 } 1669 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) { 1670 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset)); 1671 } 1672 1673 void unspill(Register Rx, bool is64, int offset) { 1674 if (is64) { 1675 ldr(Rx, spill_address(8, offset)); 1676 } else { 1677 ldrw(Rx, spill_address(4, offset)); 1678 } 1679 } 1680 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) { 1681 ldr(Vx, T, spill_address(1 << (int)T, offset)); 1682 } 1683 1684 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) { 1685 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset)); 1686 } 1687 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) { 1688 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset)); 1689 } 1690 1691 void spill_copy128(int src_offset, int dst_offset, 1692 Register tmp1=rscratch1, Register tmp2=rscratch2) { 1693 if (src_offset < 512 && (src_offset & 7) == 0 && 1694 dst_offset < 512 && (dst_offset & 7) == 0) { 1695 ldp(tmp1, tmp2, Address(sp, src_offset)); 1696 stp(tmp1, tmp2, Address(sp, dst_offset)); 1697 } else { 1698 unspill(tmp1, true, src_offset); 1699 spill(tmp1, true, dst_offset); 1700 unspill(tmp1, true, src_offset+8); 1701 spill(tmp1, true, dst_offset+8); 1702 } 1703 } 1704 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset, 1705 int sve_vec_reg_size_in_bytes) { 1706 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size"); 1707 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) { 1708 spill_copy128(src_offset, dst_offset); 1709 src_offset += 16; 1710 dst_offset += 16; 1711 } 1712 } 1713 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset, 1714 int sve_predicate_reg_size_in_bytes) { 1715 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset)); 1716 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset)); 1717 reinitialize_ptrue(); 1718 } 1719 void cache_wb(Address line); 1720 void cache_wbsync(bool is_pre); 1721 1722 // Code for java.lang.Thread::onSpinWait() intrinsic. 1723 void spin_wait(); 1724 1725 void lightweight_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow); 1726 void lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow); 1727 1728 private: 1729 // Check the current thread doesn't need a cross modify fence. 1730 void verify_cross_modify_fence_not_required() PRODUCT_RETURN; 1731 1732 }; 1733 1734 #ifdef ASSERT 1735 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } 1736 #endif 1737 1738 /** 1739 * class SkipIfEqual: 1740 * 1741 * Instantiating this class will result in assembly code being output that will 1742 * jump around any code emitted between the creation of the instance and it's 1743 * automatic destruction at the end of a scope block, depending on the value of 1744 * the flag passed to the constructor, which will be checked at run-time. 1745 */ 1746 class SkipIfEqual { 1747 private: 1748 MacroAssembler* _masm; 1749 Label _label; 1750 1751 public: 1752 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 1753 ~SkipIfEqual(); 1754 }; 1755 1756 struct tableswitch { 1757 Register _reg; 1758 int _insn_index; jint _first_key; jint _last_key; 1759 Label _after; 1760 Label _branches; 1761 }; 1762 1763 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP --- EOF ---