1 /*
2 * Copyright (c) 2008, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/macroAssembler.inline.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc/shared/collectedHeap.hpp"
34 #include "memory/universe.hpp"
35 #include "nativeInst_arm.hpp"
36 #include "oops/objArrayKlass.hpp"
37 #include "runtime/frame.inline.hpp"
38 #include "runtime/sharedRuntime.hpp"
39 #include "runtime/stubRoutines.hpp"
40 #include "utilities/powerOfTwo.hpp"
41 #include "vmreg_arm.inline.hpp"
42
43 #define __ _masm->
44
45 // Note: Rtemp usage is this file should not impact C2 and should be
46 // correct as long as it is not implicitly used in lower layers (the
47 // arm [macro]assembler) and used with care in the other C1 specific
48 // files.
49
50 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
51 ShouldNotCallThis(); // Not used on ARM
52 return false;
53 }
54
55
56 LIR_Opr LIR_Assembler::receiverOpr() {
57 // The first register in Java calling conventions
58 return FrameMap::R0_oop_opr;
59 }
60
61 LIR_Opr LIR_Assembler::osrBufferPointer() {
62 return FrameMap::as_pointer_opr(R0);
63 }
64
65 #ifndef PRODUCT
66 void LIR_Assembler::verify_reserved_argument_area_size(int args_count) {
67 assert(args_count * wordSize <= frame_map()->reserved_argument_area_size(), "not enough space for arguments");
68 }
69 #endif // !PRODUCT
70
71 void LIR_Assembler::store_parameter(jint c, int offset_from_sp_in_words) {
72 assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
73 int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
74 assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
75 __ mov_slow(Rtemp, c);
76 __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
77 }
78
79 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_sp_in_words) {
80 assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
81 int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
82 assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
83 __ mov_metadata(Rtemp, m);
84 __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
85 }
86
87 //--------------fpu register translations-----------------------
88
89
90 void LIR_Assembler::breakpoint() {
91 __ breakpoint();
92 }
93
94 void LIR_Assembler::push(LIR_Opr opr) {
95 Unimplemented();
96 }
97
98 void LIR_Assembler::pop(LIR_Opr opr) {
99 Unimplemented();
100 }
101
102 //-------------------------------------------
103 Address LIR_Assembler::as_Address(LIR_Address* addr) {
104 Register base = addr->base()->as_pointer_register();
105
106
107 if (addr->index()->is_illegal() || addr->index()->is_constant()) {
108 int offset = addr->disp();
109 if (addr->index()->is_constant()) {
110 offset += addr->index()->as_constant_ptr()->as_jint() << addr->scale();
111 }
112
113 if ((offset <= -4096) || (offset >= 4096)) {
114 BAILOUT_("offset not in range", Address(base));
115 }
116
117 return Address(base, offset);
118
119 } else {
120 assert(addr->disp() == 0, "can't have both");
121 int scale = addr->scale();
122
123 assert(addr->index()->is_single_cpu(), "should be");
124 return scale >= 0 ? Address(base, addr->index()->as_register(), lsl, scale) :
125 Address(base, addr->index()->as_register(), lsr, -scale);
126 }
127 }
128
129 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
130 Address base = as_Address(addr);
131 assert(base.index() == noreg, "must be");
132 if (base.disp() + BytesPerWord >= 4096) { BAILOUT_("offset not in range", Address(base.base(),0)); }
133 return Address(base.base(), base.disp() + BytesPerWord);
134 }
135
136 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
137 return as_Address(addr);
138 }
139
140
141 void LIR_Assembler::osr_entry() {
142 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
143 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
144 ValueStack* entry_state = osr_entry->end()->state();
145 int number_of_locks = entry_state->locks_size();
146
147 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
148 Register OSR_buf = osrBufferPointer()->as_pointer_register();
149
150 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
151 int monitor_offset = (method()->max_locals() + 2 * (number_of_locks - 1)) * BytesPerWord;
152 for (int i = 0; i < number_of_locks; i++) {
153 int slot_offset = monitor_offset - (i * 2 * BytesPerWord);
154 if (slot_offset >= 4096 - BytesPerWord) {
155 __ add_slow(R2, OSR_buf, slot_offset);
156 __ ldr(R1, Address(R2, 0*BytesPerWord));
157 __ ldr(R2, Address(R2, 1*BytesPerWord));
158 } else {
159 __ ldr(R1, Address(OSR_buf, slot_offset + 0*BytesPerWord));
160 __ ldr(R2, Address(OSR_buf, slot_offset + 1*BytesPerWord));
161 }
162 __ str(R1, frame_map()->address_for_monitor_lock(i));
163 __ str(R2, frame_map()->address_for_monitor_object(i));
164 }
165 }
166
167
168 int LIR_Assembler::check_icache() {
169 return __ ic_check(CodeEntryAlignment);
170 }
171
172 void LIR_Assembler::clinit_barrier(ciMethod* method) {
173 ShouldNotReachHere(); // not implemented
174 }
175
176 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
177 jobject o = (jobject)Universe::non_oop_word();
178 int index = __ oop_recorder()->allocate_oop_index(o);
179
180 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), index);
181
182 __ patchable_mov_oop(reg, o, index);
183 patching_epilog(patch, lir_patch_normal, reg, info);
184 }
185
186
187 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
188 Metadata* o = (Metadata*)Universe::non_oop_word();
189 int index = __ oop_recorder()->allocate_metadata_index(o);
190 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
191
192 __ patchable_mov_metadata(reg, o, index);
193 patching_epilog(patch, lir_patch_normal, reg, info);
194 }
195
196
197 int LIR_Assembler::initial_frame_size_in_bytes() const {
198 // Subtracts two words to account for return address and link
199 return frame_map()->framesize()*VMRegImpl::stack_slot_size - 2*wordSize;
200 }
201
202
203 int LIR_Assembler::emit_exception_handler() {
204 address handler_base = __ start_a_stub(exception_handler_size());
205 if (handler_base == nullptr) {
206 bailout("exception handler overflow");
207 return -1;
208 }
209
210 int offset = code_offset();
211
212 // check that there is really an exception
213 __ verify_not_null_oop(Rexception_obj);
214
215 __ call(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id), relocInfo::runtime_call_type);
216 __ should_not_reach_here();
217
218 assert(code_offset() - offset <= exception_handler_size(), "overflow");
219 __ end_a_stub();
220
221 return offset;
222 }
223
224 // Emit the code to remove the frame from the stack in the exception
225 // unwind path.
226 int LIR_Assembler::emit_unwind_handler() {
227 #ifndef PRODUCT
228 if (CommentedAssembly) {
229 _masm->block_comment("Unwind handler");
230 }
231 #endif
232
233 int offset = code_offset();
234
235 // Fetch the exception from TLS and clear out exception related thread state
236 Register zero = __ zero_register(Rtemp);
237 __ ldr(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
238 __ str(zero, Address(Rthread, JavaThread::exception_oop_offset()));
239 __ str(zero, Address(Rthread, JavaThread::exception_pc_offset()));
240
241 __ bind(_unwind_handler_entry);
242 __ verify_not_null_oop(Rexception_obj);
243
244 // Perform needed unlocking
245 MonitorExitStub* stub = nullptr;
246 if (method()->is_synchronized()) {
247 monitor_address(0, FrameMap::R0_opr);
248 stub = new MonitorExitStub(FrameMap::R0_opr, 0);
249 __ unlock_object(R2, R1, R0, *stub->entry());
250 __ bind(*stub->continuation());
251 }
252
253 // remove the activation and dispatch to the unwind handler
254 __ remove_frame(initial_frame_size_in_bytes()); // restores FP and LR
255 __ jump(Runtime1::entry_for(StubId::c1_unwind_exception_id), relocInfo::runtime_call_type, Rtemp);
256
257 // Emit the slow path assembly
258 if (stub != nullptr) {
259 stub->emit_code(this);
260 }
261
262 return offset;
263 }
264
265
266 int LIR_Assembler::emit_deopt_handler() {
267 address handler_base = __ start_a_stub(deopt_handler_size());
268 if (handler_base == nullptr) {
269 bailout("deopt handler overflow");
270 return -1;
271 }
272
273 int offset = code_offset();
274
275 Label start;
276 __ bind(start);
277
278 __ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, noreg);
279
280 int entry_offset = __ offset();
281 __ mov_relative_address(LR, __ pc());
282 __ push(LR); // stub expects LR to be saved
283 __ b(start);
284
285 assert(code_offset() - offset <= deopt_handler_size(), "overflow");
286 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
287 "out of bounds read in post-call NOP check");
288 __ end_a_stub();
289
290 return entry_offset;
291 }
292
293
294 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
295 // Pop the frame before safepoint polling
296 __ remove_frame(initial_frame_size_in_bytes());
297 __ read_polling_page(Rtemp, relocInfo::poll_return_type);
298 __ ret();
299 }
300
301 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
302
303 int offset = __ offset();
304 __ get_polling_page(Rtemp);
305 __ relocate(relocInfo::poll_type);
306 add_debug_info_for_branch(info); // help pc_desc_at to find correct scope for current PC
307 __ ldr(Rtemp, Address(Rtemp));
308
309 return offset;
310 }
311
312
313 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
314 if (from_reg != to_reg) {
315 __ mov(to_reg, from_reg);
316 }
317 }
318
319 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
320 assert(src->is_constant() && dest->is_register(), "must be");
321 LIR_Const* c = src->as_constant_ptr();
322
323 switch (c->type()) {
324 case T_ADDRESS:
325 case T_INT:
326 assert(patch_code == lir_patch_none, "no patching handled here");
327 __ mov_slow(dest->as_register(), c->as_jint());
328 break;
329
330 case T_LONG:
331 assert(patch_code == lir_patch_none, "no patching handled here");
332 __ mov_slow(dest->as_register_lo(), c->as_jint_lo());
333 __ mov_slow(dest->as_register_hi(), c->as_jint_hi());
334 break;
335
336 case T_OBJECT:
337 if (patch_code == lir_patch_none) {
338 __ mov_oop(dest->as_register(), c->as_jobject());
339 } else {
340 jobject2reg_with_patching(dest->as_register(), info);
341 }
342 break;
343
344 case T_METADATA:
345 if (patch_code == lir_patch_none) {
346 __ mov_metadata(dest->as_register(), c->as_metadata());
347 } else {
348 klass2reg_with_patching(dest->as_register(), info);
349 }
350 break;
351
352 case T_FLOAT:
353 if (dest->is_single_fpu()) {
354 __ mov_float(dest->as_float_reg(), c->as_jfloat());
355 } else {
356 // Simple getters can return float constant directly into r0
357 __ mov_slow(dest->as_register(), c->as_jint_bits());
358 }
359 break;
360
361 case T_DOUBLE:
362 if (dest->is_double_fpu()) {
363 __ mov_double(dest->as_double_reg(), c->as_jdouble());
364 } else {
365 // Simple getters can return double constant directly into r1r0
366 __ mov_slow(dest->as_register_lo(), c->as_jint_lo_bits());
367 __ mov_slow(dest->as_register_hi(), c->as_jint_hi_bits());
368 }
369 break;
370
371 default:
372 ShouldNotReachHere();
373 }
374 }
375
376 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
377 assert(src->is_constant(), "must be");
378 assert(dest->is_stack(), "must be");
379 LIR_Const* c = src->as_constant_ptr();
380
381 switch (c->type()) {
382 case T_INT: // fall through
383 case T_FLOAT:
384 __ mov_slow(Rtemp, c->as_jint_bits());
385 __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
386 break;
387
388 case T_ADDRESS:
389 __ mov_slow(Rtemp, c->as_jint());
390 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
391 break;
392
393 case T_OBJECT:
394 __ mov_oop(Rtemp, c->as_jobject());
395 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
396 break;
397
398 case T_LONG: // fall through
399 case T_DOUBLE:
400 __ mov_slow(Rtemp, c->as_jint_lo_bits());
401 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
402 if (c->as_jint_hi_bits() != c->as_jint_lo_bits()) {
403 __ mov_slow(Rtemp, c->as_jint_hi_bits());
404 }
405 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
406 break;
407
408 default:
409 ShouldNotReachHere();
410 }
411 }
412
413 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
414 CodeEmitInfo* info, bool wide) {
415 assert((src->as_constant_ptr()->type() == T_OBJECT && src->as_constant_ptr()->as_jobject() == nullptr),"cannot handle otherwise");
416 __ mov(Rtemp, 0);
417
418 int null_check_offset = code_offset();
419 __ str(Rtemp, as_Address(dest->as_address_ptr()));
420
421 if (info != nullptr) {
422 assert(false, "arm32 didn't support this before, investigate if bug");
423 add_debug_info_for_null_check(null_check_offset, info);
424 }
425 }
426
427 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
428 assert(src->is_register() && dest->is_register(), "must be");
429
430 if (src->is_single_cpu()) {
431 if (dest->is_single_cpu()) {
432 move_regs(src->as_register(), dest->as_register());
433 } else if (dest->is_single_fpu()) {
434 __ fmsr(dest->as_float_reg(), src->as_register());
435 } else {
436 ShouldNotReachHere();
437 }
438 } else if (src->is_double_cpu()) {
439 if (dest->is_double_cpu()) {
440 __ long_move(dest->as_register_lo(), dest->as_register_hi(), src->as_register_lo(), src->as_register_hi());
441 } else {
442 __ fmdrr(dest->as_double_reg(), src->as_register_lo(), src->as_register_hi());
443 }
444 } else if (src->is_single_fpu()) {
445 if (dest->is_single_fpu()) {
446 __ mov_float(dest->as_float_reg(), src->as_float_reg());
447 } else if (dest->is_single_cpu()) {
448 __ mov_fpr2gpr_float(dest->as_register(), src->as_float_reg());
449 } else {
450 ShouldNotReachHere();
451 }
452 } else if (src->is_double_fpu()) {
453 if (dest->is_double_fpu()) {
454 __ mov_double(dest->as_double_reg(), src->as_double_reg());
455 } else if (dest->is_double_cpu()) {
456 __ fmrrd(dest->as_register_lo(), dest->as_register_hi(), src->as_double_reg());
457 } else {
458 ShouldNotReachHere();
459 }
460 } else {
461 ShouldNotReachHere();
462 }
463 }
464
465 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
466 assert(src->is_register(), "should not call otherwise");
467 assert(dest->is_stack(), "should not call otherwise");
468
469 Address addr = dest->is_single_word() ?
470 frame_map()->address_for_slot(dest->single_stack_ix()) :
471 frame_map()->address_for_slot(dest->double_stack_ix());
472
473 assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
474 if (src->is_single_fpu() || src->is_double_fpu()) {
475 if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
476 }
477
478 if (src->is_single_cpu()) {
479 switch (type) {
480 case T_OBJECT:
481 case T_ARRAY: __ verify_oop(src->as_register()); // fall through
482 case T_ADDRESS:
483 case T_METADATA: __ str(src->as_register(), addr); break;
484 case T_FLOAT: // used in intBitsToFloat intrinsic implementation, fall through
485 case T_INT: __ str_32(src->as_register(), addr); break;
486 default:
487 ShouldNotReachHere();
488 }
489 } else if (src->is_double_cpu()) {
490 __ str(src->as_register_lo(), addr);
491 __ str(src->as_register_hi(), frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
492 } else if (src->is_single_fpu()) {
493 __ str_float(src->as_float_reg(), addr);
494 } else if (src->is_double_fpu()) {
495 __ str_double(src->as_double_reg(), addr);
496 } else {
497 ShouldNotReachHere();
498 }
499 }
500
501
502 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
503 LIR_PatchCode patch_code, CodeEmitInfo* info,
504 bool wide) {
505 LIR_Address* to_addr = dest->as_address_ptr();
506 Register base_reg = to_addr->base()->as_pointer_register();
507 const bool needs_patching = (patch_code != lir_patch_none);
508
509 PatchingStub* patch = nullptr;
510 if (needs_patching) {
511 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
512 }
513
514 int null_check_offset = code_offset();
515
516 switch (type) {
517 case T_ARRAY:
518 case T_OBJECT:
519 if (UseCompressedOops && !wide) {
520 ShouldNotReachHere();
521 } else {
522 __ str(src->as_register(), as_Address(to_addr));
523 }
524 break;
525
526 case T_ADDRESS:
527 __ str(src->as_pointer_register(), as_Address(to_addr));
528 break;
529
530 case T_BYTE:
531 case T_BOOLEAN:
532 __ strb(src->as_register(), as_Address(to_addr));
533 break;
534
535 case T_CHAR:
536 case T_SHORT:
537 __ strh(src->as_register(), as_Address(to_addr));
538 break;
539
540 case T_INT:
541 #ifdef __SOFTFP__
542 case T_FLOAT:
543 #endif // __SOFTFP__
544 __ str_32(src->as_register(), as_Address(to_addr));
545 break;
546
547
548 #ifdef __SOFTFP__
549 case T_DOUBLE:
550 #endif // __SOFTFP__
551 case T_LONG: {
552 Register from_lo = src->as_register_lo();
553 Register from_hi = src->as_register_hi();
554 if (to_addr->index()->is_register()) {
555 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
556 assert(to_addr->disp() == 0, "Not yet supporting both");
557 __ add(Rtemp, base_reg, to_addr->index()->as_register());
558 base_reg = Rtemp;
559 __ str(from_lo, Address(Rtemp));
560 if (patch != nullptr) {
561 __ nop(); // see comment before patching_epilog for 2nd str
562 patching_epilog(patch, lir_patch_low, base_reg, info);
563 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
564 patch_code = lir_patch_high;
565 }
566 __ str(from_hi, Address(Rtemp, BytesPerWord));
567 } else if (base_reg == from_lo) {
568 __ str(from_hi, as_Address_hi(to_addr));
569 if (patch != nullptr) {
570 __ nop(); // see comment before patching_epilog for 2nd str
571 patching_epilog(patch, lir_patch_high, base_reg, info);
572 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
573 patch_code = lir_patch_low;
574 }
575 __ str(from_lo, as_Address_lo(to_addr));
576 } else {
577 __ str(from_lo, as_Address_lo(to_addr));
578 if (patch != nullptr) {
579 __ nop(); // see comment before patching_epilog for 2nd str
580 patching_epilog(patch, lir_patch_low, base_reg, info);
581 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
582 patch_code = lir_patch_high;
583 }
584 __ str(from_hi, as_Address_hi(to_addr));
585 }
586 break;
587 }
588
589 #ifndef __SOFTFP__
590 case T_FLOAT:
591 if (to_addr->index()->is_register()) {
592 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
593 __ add(Rtemp, base_reg, to_addr->index()->as_register());
594 if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
595 __ fsts(src->as_float_reg(), Address(Rtemp, to_addr->disp()));
596 } else {
597 __ fsts(src->as_float_reg(), as_Address(to_addr));
598 }
599 break;
600
601 case T_DOUBLE:
602 if (to_addr->index()->is_register()) {
603 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
604 __ add(Rtemp, base_reg, to_addr->index()->as_register());
605 if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
606 __ fstd(src->as_double_reg(), Address(Rtemp, to_addr->disp()));
607 } else {
608 __ fstd(src->as_double_reg(), as_Address(to_addr));
609 }
610 break;
611 #endif // __SOFTFP__
612
613
614 default:
615 ShouldNotReachHere();
616 }
617
618 if (info != nullptr) {
619 add_debug_info_for_null_check(null_check_offset, info);
620 }
621
622 if (patch != nullptr) {
623 // Offset embedded into LDR/STR instruction may appear not enough
624 // to address a field. So, provide a space for one more instruction
625 // that will deal with larger offsets.
626 __ nop();
627 patching_epilog(patch, patch_code, base_reg, info);
628 }
629 }
630
631
632 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
633 assert(src->is_stack(), "should not call otherwise");
634 assert(dest->is_register(), "should not call otherwise");
635
636 Address addr = src->is_single_word() ?
637 frame_map()->address_for_slot(src->single_stack_ix()) :
638 frame_map()->address_for_slot(src->double_stack_ix());
639
640 assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
641 if (dest->is_single_fpu() || dest->is_double_fpu()) {
642 if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
643 }
644
645 if (dest->is_single_cpu()) {
646 switch (type) {
647 case T_OBJECT:
648 case T_ARRAY:
649 case T_ADDRESS:
650 case T_METADATA: __ ldr(dest->as_register(), addr); break;
651 case T_FLOAT: // used in floatToRawIntBits intrinsic implementation
652 case T_INT: __ ldr_u32(dest->as_register(), addr); break;
653 default:
654 ShouldNotReachHere();
655 }
656 if ((type == T_OBJECT) || (type == T_ARRAY)) {
657 __ verify_oop(dest->as_register());
658 }
659 } else if (dest->is_double_cpu()) {
660 __ ldr(dest->as_register_lo(), addr);
661 __ ldr(dest->as_register_hi(), frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
662 } else if (dest->is_single_fpu()) {
663 __ ldr_float(dest->as_float_reg(), addr);
664 } else if (dest->is_double_fpu()) {
665 __ ldr_double(dest->as_double_reg(), addr);
666 } else {
667 ShouldNotReachHere();
668 }
669 }
670
671
672 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
673 if (src->is_single_stack()) {
674 switch (src->type()) {
675 case T_OBJECT:
676 case T_ARRAY:
677 case T_ADDRESS:
678 case T_METADATA:
679 __ ldr(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
680 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
681 break;
682
683 case T_INT:
684 case T_FLOAT:
685 __ ldr_u32(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
686 __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
687 break;
688
689 default:
690 ShouldNotReachHere();
691 }
692 } else {
693 assert(src->is_double_stack(), "must be");
694 __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes));
695 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
696 __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
697 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
698 }
699 }
700
701
702 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
703 LIR_PatchCode patch_code, CodeEmitInfo* info,
704 bool wide) {
705 assert(src->is_address(), "should not call otherwise");
706 assert(dest->is_register(), "should not call otherwise");
707 LIR_Address* addr = src->as_address_ptr();
708
709 Register base_reg = addr->base()->as_pointer_register();
710
711 PatchingStub* patch = nullptr;
712 if (patch_code != lir_patch_none) {
713 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
714 }
715 if (info != nullptr) {
716 add_debug_info_for_null_check_here(info);
717 }
718
719 switch (type) {
720 case T_OBJECT: // fall through
721 case T_ARRAY:
722 if (UseCompressedOops && !wide) {
723 __ ldr_u32(dest->as_register(), as_Address(addr));
724 } else {
725 __ ldr(dest->as_register(), as_Address(addr));
726 }
727 break;
728
729 case T_ADDRESS:
730 __ ldr(dest->as_pointer_register(), as_Address(addr));
731 break;
732
733 case T_INT:
734 #ifdef __SOFTFP__
735 case T_FLOAT:
736 #endif // __SOFTFP__
737 __ ldr(dest->as_pointer_register(), as_Address(addr));
738 break;
739
740 case T_BOOLEAN:
741 __ ldrb(dest->as_register(), as_Address(addr));
742 break;
743
744 case T_BYTE:
745 __ ldrsb(dest->as_register(), as_Address(addr));
746 break;
747
748 case T_CHAR:
749 __ ldrh(dest->as_register(), as_Address(addr));
750 break;
751
752 case T_SHORT:
753 __ ldrsh(dest->as_register(), as_Address(addr));
754 break;
755
756
757 #ifdef __SOFTFP__
758 case T_DOUBLE:
759 #endif // __SOFTFP__
760 case T_LONG: {
761 Register to_lo = dest->as_register_lo();
762 Register to_hi = dest->as_register_hi();
763 if (addr->index()->is_register()) {
764 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
765 assert(addr->disp() == 0, "Not yet supporting both");
766 __ add(Rtemp, base_reg, addr->index()->as_register());
767 base_reg = Rtemp;
768 __ ldr(to_lo, Address(Rtemp));
769 if (patch != nullptr) {
770 __ nop(); // see comment before patching_epilog for 2nd ldr
771 patching_epilog(patch, lir_patch_low, base_reg, info);
772 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
773 patch_code = lir_patch_high;
774 }
775 __ ldr(to_hi, Address(Rtemp, BytesPerWord));
776 } else if (base_reg == to_lo) {
777 __ ldr(to_hi, as_Address_hi(addr));
778 if (patch != nullptr) {
779 __ nop(); // see comment before patching_epilog for 2nd ldr
780 patching_epilog(patch, lir_patch_high, base_reg, info);
781 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
782 patch_code = lir_patch_low;
783 }
784 __ ldr(to_lo, as_Address_lo(addr));
785 } else {
786 __ ldr(to_lo, as_Address_lo(addr));
787 if (patch != nullptr) {
788 __ nop(); // see comment before patching_epilog for 2nd ldr
789 patching_epilog(patch, lir_patch_low, base_reg, info);
790 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
791 patch_code = lir_patch_high;
792 }
793 __ ldr(to_hi, as_Address_hi(addr));
794 }
795 break;
796 }
797
798 #ifndef __SOFTFP__
799 case T_FLOAT:
800 if (addr->index()->is_register()) {
801 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
802 __ add(Rtemp, base_reg, addr->index()->as_register());
803 if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
804 __ flds(dest->as_float_reg(), Address(Rtemp, addr->disp()));
805 } else {
806 __ flds(dest->as_float_reg(), as_Address(addr));
807 }
808 break;
809
810 case T_DOUBLE:
811 if (addr->index()->is_register()) {
812 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
813 __ add(Rtemp, base_reg, addr->index()->as_register());
814 if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
815 __ fldd(dest->as_double_reg(), Address(Rtemp, addr->disp()));
816 } else {
817 __ fldd(dest->as_double_reg(), as_Address(addr));
818 }
819 break;
820 #endif // __SOFTFP__
821
822
823 default:
824 ShouldNotReachHere();
825 }
826
827 if (patch != nullptr) {
828 // Offset embedded into LDR/STR instruction may appear not enough
829 // to address a field. So, provide a space for one more instruction
830 // that will deal with larger offsets.
831 __ nop();
832 patching_epilog(patch, patch_code, base_reg, info);
833 }
834
835 }
836
837
838 void LIR_Assembler::emit_op3(LIR_Op3* op) {
839 bool is_32 = op->result_opr()->is_single_cpu();
840
841 if (op->code() == lir_idiv && op->in_opr2()->is_constant() && is_32) {
842 int c = op->in_opr2()->as_constant_ptr()->as_jint();
843 assert(is_power_of_2(c), "non power-of-2 constant should be put in a register");
844
845 Register left = op->in_opr1()->as_register();
846 Register dest = op->result_opr()->as_register();
847 if (c == 1) {
848 __ mov(dest, left);
849 } else if (c == 2) {
850 __ add_32(dest, left, AsmOperand(left, lsr, 31));
851 __ asr_32(dest, dest, 1);
852 } else if (c != (int) 0x80000000) {
853 int power = log2i_exact(c);
854 __ asr_32(Rtemp, left, 31);
855 __ add_32(dest, left, AsmOperand(Rtemp, lsr, 32-power)); // dest = left + (left < 0 ? 2^power - 1 : 0);
856 __ asr_32(dest, dest, power); // dest = dest >>> power;
857 } else {
858 // x/0x80000000 is a special case, since dividend is a power of two, but is negative.
859 // The only possible result values are 0 and 1, with 1 only for dividend == divisor == 0x80000000.
860 __ cmp_32(left, c);
861 __ mov(dest, 0, ne);
862 __ mov(dest, 1, eq);
863 }
864 } else {
865 assert(op->code() == lir_idiv || op->code() == lir_irem, "unexpected op3");
866 __ call(StubRoutines::Arm::idiv_irem_entry(), relocInfo::runtime_call_type);
867 add_debug_info_for_div0_here(op->info());
868 }
869 }
870
871
872 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
873 #ifdef ASSERT
874 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
875 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
876 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
877 assert(op->info() == nullptr, "CodeEmitInfo?");
878 #endif // ASSERT
879
880 #ifdef __SOFTFP__
881 assert (op->code() != lir_cond_float_branch, "this should be impossible");
882 #else
883 if (op->code() == lir_cond_float_branch) {
884 __ fmstat();
885 __ b(*(op->ublock()->label()), vs);
886 }
887 #endif // __SOFTFP__
888
889 AsmCondition acond = al;
890 switch (op->cond()) {
891 case lir_cond_equal: acond = eq; break;
892 case lir_cond_notEqual: acond = ne; break;
893 case lir_cond_less: acond = lt; break;
894 case lir_cond_lessEqual: acond = le; break;
895 case lir_cond_greaterEqual: acond = ge; break;
896 case lir_cond_greater: acond = gt; break;
897 case lir_cond_aboveEqual: acond = hs; break;
898 case lir_cond_belowEqual: acond = ls; break;
899 default: assert(op->cond() == lir_cond_always, "must be");
900 }
901 __ b(*(op->label()), acond);
902 }
903
904
905 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
906 LIR_Opr src = op->in_opr();
907 LIR_Opr dest = op->result_opr();
908
909 switch (op->bytecode()) {
910 case Bytecodes::_i2l:
911 move_regs(src->as_register(), dest->as_register_lo());
912 __ mov(dest->as_register_hi(), AsmOperand(src->as_register(), asr, 31));
913 break;
914 case Bytecodes::_l2i:
915 move_regs(src->as_register_lo(), dest->as_register());
916 break;
917 case Bytecodes::_i2b:
918 __ sign_extend(dest->as_register(), src->as_register(), 8);
919 break;
920 case Bytecodes::_i2s:
921 __ sign_extend(dest->as_register(), src->as_register(), 16);
922 break;
923 case Bytecodes::_i2c:
924 __ zero_extend(dest->as_register(), src->as_register(), 16);
925 break;
926 case Bytecodes::_f2d:
927 __ convert_f2d(dest->as_double_reg(), src->as_float_reg());
928 break;
929 case Bytecodes::_d2f:
930 __ convert_d2f(dest->as_float_reg(), src->as_double_reg());
931 break;
932 case Bytecodes::_i2f:
933 __ fmsr(Stemp, src->as_register());
934 __ fsitos(dest->as_float_reg(), Stemp);
935 break;
936 case Bytecodes::_i2d:
937 __ fmsr(Stemp, src->as_register());
938 __ fsitod(dest->as_double_reg(), Stemp);
939 break;
940 case Bytecodes::_f2i:
941 __ ftosizs(Stemp, src->as_float_reg());
942 __ fmrs(dest->as_register(), Stemp);
943 break;
944 case Bytecodes::_d2i:
945 __ ftosizd(Stemp, src->as_double_reg());
946 __ fmrs(dest->as_register(), Stemp);
947 break;
948 default:
949 ShouldNotReachHere();
950 }
951 }
952
953
954 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
955 if (op->init_check()) {
956 Register tmp = op->tmp1()->as_register();
957 __ ldrb(tmp, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
958 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::LoadLoad | MacroAssembler::LoadStore), Rtemp);
959 add_debug_info_for_null_check_here(op->stub()->info());
960 __ cmp(tmp, InstanceKlass::fully_initialized);
961 __ b(*op->stub()->entry(), ne);
962 }
963 __ allocate_object(op->obj()->as_register(),
964 op->tmp1()->as_register(),
965 op->tmp2()->as_register(),
966 op->tmp3()->as_register(),
967 op->header_size(),
968 op->object_size(),
969 op->klass()->as_register(),
970 *op->stub()->entry());
971 __ bind(*op->stub()->continuation());
972 }
973
974 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
975 if (UseSlowPath ||
976 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
977 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
978 __ b(*op->stub()->entry());
979 } else {
980 __ allocate_array(op->obj()->as_register(),
981 op->len()->as_register(),
982 op->tmp1()->as_register(),
983 op->tmp2()->as_register(),
984 op->tmp3()->as_register(),
985 arrayOopDesc::base_offset_in_bytes(op->type()),
986 type2aelembytes(op->type()),
987 op->klass()->as_register(),
988 *op->stub()->entry());
989 }
990 __ bind(*op->stub()->continuation());
991 }
992
993 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
994 ciMethodData *md, ciProfileData *data,
995 Register recv, Register tmp1, Label* update_done) {
996 assert_different_registers(mdo, recv, tmp1);
997 uint i;
998 for (i = 0; i < VirtualCallData::row_limit(); i++) {
999 Label next_test;
1000 // See if the receiver is receiver[n].
1001 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
1002 mdo_offset_bias);
1003 __ ldr(tmp1, receiver_addr);
1004 __ verify_klass_ptr(tmp1);
1005 __ cmp(recv, tmp1);
1006 __ b(next_test, ne);
1007 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1008 mdo_offset_bias);
1009 __ ldr(tmp1, data_addr);
1010 __ add(tmp1, tmp1, DataLayout::counter_increment);
1011 __ str(tmp1, data_addr);
1012 __ b(*update_done);
1013 __ bind(next_test);
1014 }
1015
1016 // Didn't find receiver; find next empty slot and fill it in
1017 for (i = 0; i < VirtualCallData::row_limit(); i++) {
1018 Label next_test;
1019 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
1020 mdo_offset_bias);
1021 __ ldr(tmp1, recv_addr);
1022 __ cbnz(tmp1, next_test);
1023 __ str(recv, recv_addr);
1024 __ mov(tmp1, DataLayout::counter_increment);
1025 __ str(tmp1, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1026 mdo_offset_bias));
1027 __ b(*update_done);
1028 __ bind(next_test);
1029 }
1030 }
1031
1032 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
1033 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
1034 md = method->method_data_or_null();
1035 assert(md != nullptr, "Sanity");
1036 data = md->bci_to_data(bci);
1037 assert(data != nullptr, "need data for checkcast");
1038 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1039 if (md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes() >= 4096) {
1040 // The offset is large so bias the mdo by the base of the slot so
1041 // that the ldr can use an immediate offset to reference the slots of the data
1042 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
1043 }
1044 }
1045
1046 // On 32-bit ARM, code before this helper should test obj for null (ZF should be set if obj is null).
1047 void LIR_Assembler::typecheck_profile_helper1(ciMethod* method, int bci,
1048 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias,
1049 Register obj, Register mdo, Register data_val, Label* obj_is_null) {
1050 assert(method != nullptr, "Should have method");
1051 assert_different_registers(obj, mdo, data_val);
1052 setup_md_access(method, bci, md, data, mdo_offset_bias);
1053 Label not_null;
1054 __ b(not_null, ne);
1055 __ mov_metadata(mdo, md->constant_encoding());
1056 if (mdo_offset_bias > 0) {
1057 __ mov_slow(data_val, mdo_offset_bias);
1058 __ add(mdo, mdo, data_val);
1059 }
1060 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
1061 __ ldrb(data_val, flags_addr);
1062 __ orr(data_val, data_val, (uint)BitData::null_seen_byte_constant());
1063 __ strb(data_val, flags_addr);
1064 __ b(*obj_is_null);
1065 __ bind(not_null);
1066 }
1067
1068 void LIR_Assembler::typecheck_profile_helper2(ciMethodData* md, ciProfileData* data, int mdo_offset_bias,
1069 Register mdo, Register recv, Register value, Register tmp1,
1070 Label* profile_cast_success, Label* profile_cast_failure,
1071 Label* success, Label* failure) {
1072 assert_different_registers(mdo, value, tmp1);
1073 __ bind(*profile_cast_success);
1074 __ mov_metadata(mdo, md->constant_encoding());
1075 if (mdo_offset_bias > 0) {
1076 __ mov_slow(tmp1, mdo_offset_bias);
1077 __ add(mdo, mdo, tmp1);
1078 }
1079 __ load_klass(recv, value);
1080 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
1081 __ b(*success);
1082 // Cast failure case
1083 __ bind(*profile_cast_failure);
1084 __ mov_metadata(mdo, md->constant_encoding());
1085 if (mdo_offset_bias > 0) {
1086 __ mov_slow(tmp1, mdo_offset_bias);
1087 __ add(mdo, mdo, tmp1);
1088 }
1089 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
1090 __ ldr(tmp1, data_addr);
1091 __ sub(tmp1, tmp1, DataLayout::counter_increment);
1092 __ str(tmp1, data_addr);
1093 __ b(*failure);
1094 }
1095
1096 // Sets `res` to true, if `cond` holds.
1097 static void set_instanceof_result(MacroAssembler* _masm, Register res, AsmCondition cond) {
1098 __ mov(res, 1, cond);
1099 }
1100
1101
1102 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1103 // TODO: ARM - can be more effective with one more register
1104 switch (op->code()) {
1105 case lir_store_check: {
1106 CodeStub* stub = op->stub();
1107 Register value = op->object()->as_register();
1108 Register array = op->array()->as_register();
1109 Register klass_RInfo = op->tmp1()->as_register();
1110 Register k_RInfo = op->tmp2()->as_register();
1111 assert_different_registers(klass_RInfo, k_RInfo, Rtemp);
1112 if (op->should_profile()) {
1113 assert_different_registers(value, klass_RInfo, k_RInfo, Rtemp);
1114 }
1115
1116 // check if it needs to be profiled
1117 ciMethodData* md;
1118 ciProfileData* data;
1119 int mdo_offset_bias = 0;
1120 Label profile_cast_success, profile_cast_failure, done;
1121 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1122 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1123
1124 if (op->should_profile()) {
1125 __ cmp(value, 0);
1126 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, value, k_RInfo, Rtemp, &done);
1127 } else {
1128 __ cbz(value, done);
1129 }
1130 assert_different_registers(k_RInfo, value);
1131 add_debug_info_for_null_check_here(op->info_for_exception());
1132 __ load_klass(k_RInfo, array);
1133 __ load_klass(klass_RInfo, value);
1134 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1135 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1136 // check for immediate positive hit
1137 __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1138 __ cmp(klass_RInfo, k_RInfo);
1139 __ cond_cmp(Rtemp, k_RInfo, ne);
1140 __ b(*success_target, eq);
1141 // check for immediate negative hit
1142 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1143 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1144 __ b(*failure_target, ne);
1145 // slow case
1146 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1147 __ call(Runtime1::entry_for(StubId::c1_slow_subtype_check_id), relocInfo::runtime_call_type);
1148 __ cbz(R0, *failure_target);
1149 if (op->should_profile()) {
1150 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1151 if (mdo == value) {
1152 mdo = k_RInfo;
1153 recv = klass_RInfo;
1154 }
1155 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, value, tmp1,
1156 &profile_cast_success, &profile_cast_failure,
1157 &done, stub->entry());
1158 }
1159 __ bind(done);
1160 break;
1161 }
1162
1163 case lir_checkcast: {
1164 CodeStub* stub = op->stub();
1165 Register obj = op->object()->as_register();
1166 Register res = op->result_opr()->as_register();
1167 Register klass_RInfo = op->tmp1()->as_register();
1168 Register k_RInfo = op->tmp2()->as_register();
1169 ciKlass* k = op->klass();
1170 assert_different_registers(res, k_RInfo, klass_RInfo, Rtemp);
1171
1172 if (stub->is_simple_exception_stub()) {
1173 // TODO: ARM - Late binding is used to prevent confusion of register allocator
1174 assert(stub->is_exception_throw_stub(), "must be");
1175 ((SimpleExceptionStub*)stub)->set_obj(op->result_opr());
1176 }
1177 ciMethodData* md;
1178 ciProfileData* data;
1179 int mdo_offset_bias = 0;
1180
1181 Label done;
1182
1183 Label profile_cast_failure, profile_cast_success;
1184 Label *failure_target = op->should_profile() ? &profile_cast_failure : op->stub()->entry();
1185 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1186
1187
1188 __ movs(res, obj);
1189 if (op->should_profile()) {
1190 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1191 } else {
1192 __ b(done, eq);
1193 }
1194 if (k->is_loaded()) {
1195 __ mov_metadata(k_RInfo, k->constant_encoding());
1196 } else if (k_RInfo != obj) {
1197 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1198 __ movs(res, obj);
1199 } else {
1200 // Patching doesn't update "res" register after GC, so do patching first
1201 klass2reg_with_patching(Rtemp, op->info_for_patch());
1202 __ movs(res, obj);
1203 __ mov(k_RInfo, Rtemp);
1204 }
1205 __ load_klass(klass_RInfo, res, ne);
1206
1207 if (op->fast_check()) {
1208 __ cmp(klass_RInfo, k_RInfo, ne);
1209 __ b(*failure_target, ne);
1210 } else if (k->is_loaded()) {
1211 __ b(*success_target, eq);
1212 __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1213 if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1214 __ cmp(Rtemp, k_RInfo);
1215 __ b(*failure_target, ne);
1216 } else {
1217 __ cmp(klass_RInfo, k_RInfo);
1218 __ cmp(Rtemp, k_RInfo, ne);
1219 __ b(*success_target, eq);
1220 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1221 __ call(Runtime1::entry_for(StubId::c1_slow_subtype_check_id), relocInfo::runtime_call_type);
1222 __ cbz(R0, *failure_target);
1223 }
1224 } else {
1225 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1226 __ b(*success_target, eq);
1227 // check for immediate positive hit
1228 __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1229 __ cmp(klass_RInfo, k_RInfo);
1230 __ cmp(Rtemp, k_RInfo, ne);
1231 __ b(*success_target, eq);
1232 // check for immediate negative hit
1233 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1234 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1235 __ b(*failure_target, ne);
1236 // slow case
1237 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1238 __ call(Runtime1::entry_for(StubId::c1_slow_subtype_check_id), relocInfo::runtime_call_type);
1239 __ cbz(R0, *failure_target);
1240 }
1241
1242 if (op->should_profile()) {
1243 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1244 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1245 &profile_cast_success, &profile_cast_failure,
1246 &done, stub->entry());
1247 }
1248 __ bind(done);
1249 break;
1250 }
1251
1252 case lir_instanceof: {
1253 Register obj = op->object()->as_register();
1254 Register res = op->result_opr()->as_register();
1255 Register klass_RInfo = op->tmp1()->as_register();
1256 Register k_RInfo = op->tmp2()->as_register();
1257 ciKlass* k = op->klass();
1258 assert_different_registers(res, klass_RInfo, k_RInfo, Rtemp);
1259
1260 ciMethodData* md;
1261 ciProfileData* data;
1262 int mdo_offset_bias = 0;
1263
1264 Label done;
1265
1266 Label profile_cast_failure, profile_cast_success;
1267 Label *failure_target = op->should_profile() ? &profile_cast_failure : &done;
1268 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1269
1270 __ movs(res, obj);
1271
1272 if (op->should_profile()) {
1273 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1274 } else {
1275 __ b(done, eq);
1276 }
1277
1278 if (k->is_loaded()) {
1279 __ mov_metadata(k_RInfo, k->constant_encoding());
1280 } else {
1281 op->info_for_patch()->add_register_oop(FrameMap::as_oop_opr(res));
1282 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1283 }
1284 __ load_klass(klass_RInfo, res);
1285
1286 if (!op->should_profile()) {
1287 __ mov(res, 0);
1288 }
1289
1290 if (op->fast_check()) {
1291 __ cmp(klass_RInfo, k_RInfo);
1292 if (!op->should_profile()) {
1293 set_instanceof_result(_masm, res, eq);
1294 } else {
1295 __ b(profile_cast_failure, ne);
1296 }
1297 } else if (k->is_loaded()) {
1298 __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1299 if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1300 __ cmp(Rtemp, k_RInfo);
1301 if (!op->should_profile()) {
1302 set_instanceof_result(_masm, res, eq);
1303 } else {
1304 __ b(profile_cast_failure, ne);
1305 }
1306 } else {
1307 __ cmp(klass_RInfo, k_RInfo);
1308 __ cond_cmp(Rtemp, k_RInfo, ne);
1309 if (!op->should_profile()) {
1310 set_instanceof_result(_masm, res, eq);
1311 }
1312 __ b(*success_target, eq);
1313 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1314 __ call(Runtime1::entry_for(StubId::c1_slow_subtype_check_id), relocInfo::runtime_call_type);
1315 if (!op->should_profile()) {
1316 move_regs(R0, res);
1317 } else {
1318 __ cbz(R0, *failure_target);
1319 }
1320 }
1321 } else {
1322 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1323 // check for immediate positive hit
1324 __ cmp(klass_RInfo, k_RInfo);
1325 if (!op->should_profile()) {
1326 __ ldr(res, Address(klass_RInfo, Rtemp), ne);
1327 __ cond_cmp(res, k_RInfo, ne);
1328 set_instanceof_result(_masm, res, eq);
1329 } else {
1330 __ ldr(Rtemp, Address(klass_RInfo, Rtemp), ne);
1331 __ cond_cmp(Rtemp, k_RInfo, ne);
1332 }
1333 __ b(*success_target, eq);
1334 // check for immediate negative hit
1335 if (op->should_profile()) {
1336 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1337 }
1338 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1339 if (!op->should_profile()) {
1340 __ mov(res, 0, ne);
1341 }
1342 __ b(*failure_target, ne);
1343 // slow case
1344 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1345 __ call(Runtime1::entry_for(StubId::c1_slow_subtype_check_id), relocInfo::runtime_call_type);
1346 if (!op->should_profile()) {
1347 move_regs(R0, res);
1348 }
1349 if (op->should_profile()) {
1350 __ cbz(R0, *failure_target);
1351 }
1352 }
1353
1354 if (op->should_profile()) {
1355 Label done_ok, done_failure;
1356 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1357 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1358 &profile_cast_success, &profile_cast_failure,
1359 &done_ok, &done_failure);
1360 __ bind(done_failure);
1361 __ mov(res, 0);
1362 __ b(done);
1363 __ bind(done_ok);
1364 __ mov(res, 1);
1365 }
1366 __ bind(done);
1367 break;
1368 }
1369 default:
1370 ShouldNotReachHere();
1371 }
1372 }
1373
1374
1375 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1376 // if (*addr == cmpval) {
1377 // *addr = newval;
1378 // dest = 1;
1379 // } else {
1380 // dest = 0;
1381 // }
1382 // FIXME: membar_release
1383 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
1384 Register addr = op->addr()->is_register() ?
1385 op->addr()->as_pointer_register() :
1386 op->addr()->as_address_ptr()->base()->as_pointer_register();
1387 assert(op->addr()->is_register() || op->addr()->as_address_ptr()->disp() == 0, "unexpected disp");
1388 assert(op->addr()->is_register() || op->addr()->as_address_ptr()->index() == LIR_Opr::illegalOpr(), "unexpected index");
1389 if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
1390 Register cmpval = op->cmp_value()->as_register();
1391 Register newval = op->new_value()->as_register();
1392 Register dest = op->result_opr()->as_register();
1393 assert_different_registers(dest, addr, cmpval, newval, Rtemp);
1394
1395 __ atomic_cas_bool(cmpval, newval, addr, 0, Rtemp); // Rtemp free by default at C1 LIR layer
1396 __ mov(dest, 1, eq);
1397 __ mov(dest, 0, ne);
1398 } else if (op->code() == lir_cas_long) {
1399 Register cmp_value_lo = op->cmp_value()->as_register_lo();
1400 Register cmp_value_hi = op->cmp_value()->as_register_hi();
1401 Register new_value_lo = op->new_value()->as_register_lo();
1402 Register new_value_hi = op->new_value()->as_register_hi();
1403 Register dest = op->result_opr()->as_register();
1404 Register tmp_lo = op->tmp1()->as_register_lo();
1405 Register tmp_hi = op->tmp1()->as_register_hi();
1406
1407 assert_different_registers(tmp_lo, tmp_hi, cmp_value_lo, cmp_value_hi, dest, new_value_lo, new_value_hi, addr);
1408 assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
1409 assert(new_value_hi->encoding() == new_value_lo->encoding() + 1, "non aligned register pair");
1410 assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
1411 assert((new_value_lo->encoding() & 0x1) == 0, "misaligned register pair");
1412 __ atomic_cas64(tmp_lo, tmp_hi, dest, cmp_value_lo, cmp_value_hi,
1413 new_value_lo, new_value_hi, addr, 0);
1414 } else {
1415 Unimplemented();
1416 }
1417 // FIXME: is full membar really needed instead of just membar_acquire?
1418 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
1419 }
1420
1421
1422 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1423 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1424 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on arm");
1425
1426 AsmCondition acond = al;
1427 AsmCondition ncond = nv;
1428 if (opr1 != opr2) {
1429 switch (condition) {
1430 case lir_cond_equal: acond = eq; ncond = ne; break;
1431 case lir_cond_notEqual: acond = ne; ncond = eq; break;
1432 case lir_cond_less: acond = lt; ncond = ge; break;
1433 case lir_cond_lessEqual: acond = le; ncond = gt; break;
1434 case lir_cond_greaterEqual: acond = ge; ncond = lt; break;
1435 case lir_cond_greater: acond = gt; ncond = le; break;
1436 case lir_cond_aboveEqual: acond = hs; ncond = lo; break;
1437 case lir_cond_belowEqual: acond = ls; ncond = hi; break;
1438 default: ShouldNotReachHere();
1439 }
1440 }
1441
1442 for (;;) { // two iterations only
1443 if (opr1 == result) {
1444 // do nothing
1445 } else if (opr1->is_single_cpu()) {
1446 __ mov(result->as_register(), opr1->as_register(), acond);
1447 } else if (opr1->is_double_cpu()) {
1448 __ long_move(result->as_register_lo(), result->as_register_hi(),
1449 opr1->as_register_lo(), opr1->as_register_hi(), acond);
1450 } else if (opr1->is_single_stack()) {
1451 __ ldr(result->as_register(), frame_map()->address_for_slot(opr1->single_stack_ix()), acond);
1452 } else if (opr1->is_double_stack()) {
1453 __ ldr(result->as_register_lo(),
1454 frame_map()->address_for_slot(opr1->double_stack_ix(), lo_word_offset_in_bytes), acond);
1455 __ ldr(result->as_register_hi(),
1456 frame_map()->address_for_slot(opr1->double_stack_ix(), hi_word_offset_in_bytes), acond);
1457 } else if (opr1->is_illegal()) {
1458 // do nothing: this part of the cmove has been optimized away in the peephole optimizer
1459 } else {
1460 assert(opr1->is_constant(), "must be");
1461 LIR_Const* c = opr1->as_constant_ptr();
1462
1463 switch (c->type()) {
1464 case T_INT:
1465 __ mov_slow(result->as_register(), c->as_jint(), acond);
1466 break;
1467 case T_LONG:
1468 __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1469 __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1470 break;
1471 case T_OBJECT:
1472 __ mov_oop(result->as_register(), c->as_jobject(), 0, acond);
1473 break;
1474 case T_FLOAT:
1475 #ifdef __SOFTFP__
1476 // not generated now.
1477 __ mov_slow(result->as_register(), c->as_jint(), acond);
1478 #else
1479 __ mov_float(result->as_float_reg(), c->as_jfloat(), acond);
1480 #endif // __SOFTFP__
1481 break;
1482 case T_DOUBLE:
1483 #ifdef __SOFTFP__
1484 // not generated now.
1485 __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1486 __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1487 #else
1488 __ mov_double(result->as_double_reg(), c->as_jdouble(), acond);
1489 #endif // __SOFTFP__
1490 break;
1491 case T_METADATA:
1492 __ mov_metadata(result->as_register(), c->as_metadata(), acond);
1493 break;
1494 default:
1495 ShouldNotReachHere();
1496 }
1497 }
1498
1499 // Negate the condition and repeat the algorithm with the second operand
1500 if (opr1 == opr2) { break; }
1501 opr1 = opr2;
1502 acond = ncond;
1503 }
1504 }
1505
1506 #ifdef ASSERT
1507 static int reg_size(LIR_Opr op) {
1508 switch (op->type()) {
1509 case T_FLOAT:
1510 case T_INT: return BytesPerInt;
1511 case T_LONG:
1512 case T_DOUBLE: return BytesPerLong;
1513 case T_OBJECT:
1514 case T_ARRAY:
1515 case T_METADATA: return BytesPerWord;
1516 case T_ADDRESS:
1517 case T_ILLEGAL: // fall through
1518 default: ShouldNotReachHere(); return -1;
1519 }
1520 }
1521 #endif
1522
1523 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1524 assert(info == nullptr, "unused on this code path");
1525 assert(dest->is_register(), "wrong items state");
1526
1527 if (right->is_address()) {
1528 // special case for adding shifted/extended register
1529 const Register res = dest->as_pointer_register();
1530 const Register lreg = left->as_pointer_register();
1531 const LIR_Address* addr = right->as_address_ptr();
1532
1533 assert(addr->base()->as_pointer_register() == lreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1534
1535 int scale = addr->scale();
1536 AsmShift shift = lsl;
1537
1538
1539 assert(reg_size(addr->base()) == reg_size(addr->index()), "should be");
1540 assert(reg_size(addr->base()) == reg_size(dest), "should be");
1541 assert(reg_size(dest) == wordSize, "should be");
1542
1543 AsmOperand operand(addr->index()->as_pointer_register(), shift, scale);
1544 switch (code) {
1545 case lir_add: __ add(res, lreg, operand); break;
1546 case lir_sub: __ sub(res, lreg, operand); break;
1547 default: ShouldNotReachHere();
1548 }
1549
1550 } else if (left->is_address()) {
1551 assert(code == lir_sub && right->is_single_cpu(), "special case used by strength_reduce_multiply()");
1552 const LIR_Address* addr = left->as_address_ptr();
1553 const Register res = dest->as_register();
1554 const Register rreg = right->as_register();
1555 assert(addr->base()->as_register() == rreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1556 __ rsb(res, rreg, AsmOperand(addr->index()->as_register(), lsl, addr->scale()));
1557
1558 } else if (dest->is_single_cpu()) {
1559 assert(left->is_single_cpu(), "unexpected left operand");
1560
1561 const Register res = dest->as_register();
1562 const Register lreg = left->as_register();
1563
1564 if (right->is_single_cpu()) {
1565 const Register rreg = right->as_register();
1566 switch (code) {
1567 case lir_add: __ add_32(res, lreg, rreg); break;
1568 case lir_sub: __ sub_32(res, lreg, rreg); break;
1569 case lir_mul: __ mul_32(res, lreg, rreg); break;
1570 default: ShouldNotReachHere();
1571 }
1572 } else {
1573 assert(right->is_constant(), "must be");
1574 const jint c = right->as_constant_ptr()->as_jint();
1575 if (!Assembler::is_arith_imm_in_range(c)) {
1576 BAILOUT("illegal arithmetic operand");
1577 }
1578 switch (code) {
1579 case lir_add: __ add_32(res, lreg, c); break;
1580 case lir_sub: __ sub_32(res, lreg, c); break;
1581 default: ShouldNotReachHere();
1582 }
1583 }
1584
1585 } else if (dest->is_double_cpu()) {
1586 Register res_lo = dest->as_register_lo();
1587 Register res_hi = dest->as_register_hi();
1588 Register lreg_lo = left->as_register_lo();
1589 Register lreg_hi = left->as_register_hi();
1590 if (right->is_double_cpu()) {
1591 Register rreg_lo = right->as_register_lo();
1592 Register rreg_hi = right->as_register_hi();
1593 if (res_lo == lreg_hi || res_lo == rreg_hi) {
1594 res_lo = Rtemp;
1595 }
1596 switch (code) {
1597 case lir_add:
1598 __ adds(res_lo, lreg_lo, rreg_lo);
1599 __ adc(res_hi, lreg_hi, rreg_hi);
1600 break;
1601 case lir_sub:
1602 __ subs(res_lo, lreg_lo, rreg_lo);
1603 __ sbc(res_hi, lreg_hi, rreg_hi);
1604 break;
1605 default:
1606 ShouldNotReachHere();
1607 }
1608 } else {
1609 assert(right->is_constant(), "must be");
1610 assert((right->as_constant_ptr()->as_jlong() >> 32) == 0, "out of range");
1611 const jint c = (jint) right->as_constant_ptr()->as_jlong();
1612 if (res_lo == lreg_hi) {
1613 res_lo = Rtemp;
1614 }
1615 switch (code) {
1616 case lir_add:
1617 __ adds(res_lo, lreg_lo, c);
1618 __ adc(res_hi, lreg_hi, 0);
1619 break;
1620 case lir_sub:
1621 __ subs(res_lo, lreg_lo, c);
1622 __ sbc(res_hi, lreg_hi, 0);
1623 break;
1624 default:
1625 ShouldNotReachHere();
1626 }
1627 }
1628 move_regs(res_lo, dest->as_register_lo());
1629
1630 } else if (dest->is_single_fpu()) {
1631 assert(left->is_single_fpu(), "must be");
1632 assert(right->is_single_fpu(), "must be");
1633 const FloatRegister res = dest->as_float_reg();
1634 const FloatRegister lreg = left->as_float_reg();
1635 const FloatRegister rreg = right->as_float_reg();
1636 switch (code) {
1637 case lir_add: __ add_float(res, lreg, rreg); break;
1638 case lir_sub: __ sub_float(res, lreg, rreg); break;
1639 case lir_mul: __ mul_float(res, lreg, rreg); break;
1640 case lir_div: __ div_float(res, lreg, rreg); break;
1641 default: ShouldNotReachHere();
1642 }
1643 } else if (dest->is_double_fpu()) {
1644 assert(left->is_double_fpu(), "must be");
1645 assert(right->is_double_fpu(), "must be");
1646 const FloatRegister res = dest->as_double_reg();
1647 const FloatRegister lreg = left->as_double_reg();
1648 const FloatRegister rreg = right->as_double_reg();
1649 switch (code) {
1650 case lir_add: __ add_double(res, lreg, rreg); break;
1651 case lir_sub: __ sub_double(res, lreg, rreg); break;
1652 case lir_mul: __ mul_double(res, lreg, rreg); break;
1653 case lir_div: __ div_double(res, lreg, rreg); break;
1654 default: ShouldNotReachHere();
1655 }
1656 } else {
1657 ShouldNotReachHere();
1658 }
1659 }
1660
1661
1662 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1663 switch (code) {
1664 case lir_abs:
1665 __ abs_double(dest->as_double_reg(), value->as_double_reg());
1666 break;
1667 case lir_sqrt:
1668 __ sqrt_double(dest->as_double_reg(), value->as_double_reg());
1669 break;
1670 default:
1671 ShouldNotReachHere();
1672 }
1673 }
1674
1675
1676 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1677 assert(dest->is_register(), "wrong items state");
1678 assert(left->is_register(), "wrong items state");
1679
1680 if (dest->is_single_cpu()) {
1681
1682 const Register res = dest->as_register();
1683 const Register lreg = left->as_register();
1684
1685 if (right->is_single_cpu()) {
1686 const Register rreg = right->as_register();
1687 switch (code) {
1688 case lir_logic_and: __ and_32(res, lreg, rreg); break;
1689 case lir_logic_or: __ orr_32(res, lreg, rreg); break;
1690 case lir_logic_xor: __ eor_32(res, lreg, rreg); break;
1691 default: ShouldNotReachHere();
1692 }
1693 } else {
1694 assert(right->is_constant(), "must be");
1695 const uint c = (uint)right->as_constant_ptr()->as_jint();
1696 if (!Assembler::is_arith_imm_in_range(c)) {
1697 BAILOUT("illegal arithmetic operand");
1698 }
1699 switch (code) {
1700 case lir_logic_and: __ and_32(res, lreg, c); break;
1701 case lir_logic_or: __ orr_32(res, lreg, c); break;
1702 case lir_logic_xor: __ eor_32(res, lreg, c); break;
1703 default: ShouldNotReachHere();
1704 }
1705 }
1706 } else {
1707 assert(dest->is_double_cpu(), "should be");
1708 Register res_lo = dest->as_register_lo();
1709
1710 assert (dest->type() == T_LONG, "unexpected result type");
1711 assert (left->type() == T_LONG, "unexpected left type");
1712 assert (right->type() == T_LONG, "unexpected right type");
1713
1714 const Register res_hi = dest->as_register_hi();
1715 const Register lreg_lo = left->as_register_lo();
1716 const Register lreg_hi = left->as_register_hi();
1717
1718 if (right->is_register()) {
1719 const Register rreg_lo = right->as_register_lo();
1720 const Register rreg_hi = right->as_register_hi();
1721 if (res_lo == lreg_hi || res_lo == rreg_hi) {
1722 res_lo = Rtemp; // Temp register helps to avoid overlap between result and input
1723 }
1724 switch (code) {
1725 case lir_logic_and:
1726 __ andr(res_lo, lreg_lo, rreg_lo);
1727 __ andr(res_hi, lreg_hi, rreg_hi);
1728 break;
1729 case lir_logic_or:
1730 __ orr(res_lo, lreg_lo, rreg_lo);
1731 __ orr(res_hi, lreg_hi, rreg_hi);
1732 break;
1733 case lir_logic_xor:
1734 __ eor(res_lo, lreg_lo, rreg_lo);
1735 __ eor(res_hi, lreg_hi, rreg_hi);
1736 break;
1737 default:
1738 ShouldNotReachHere();
1739 }
1740 move_regs(res_lo, dest->as_register_lo());
1741 } else {
1742 assert(right->is_constant(), "must be");
1743 const jint c_lo = (jint) right->as_constant_ptr()->as_jlong();
1744 const jint c_hi = (jint) (right->as_constant_ptr()->as_jlong() >> 32);
1745 // Case for logic_or from do_ClassIDIntrinsic()
1746 if (c_hi == 0 && AsmOperand::is_rotated_imm(c_lo)) {
1747 switch (code) {
1748 case lir_logic_and:
1749 __ andr(res_lo, lreg_lo, c_lo);
1750 __ mov(res_hi, 0);
1751 break;
1752 case lir_logic_or:
1753 __ orr(res_lo, lreg_lo, c_lo);
1754 break;
1755 case lir_logic_xor:
1756 __ eor(res_lo, lreg_lo, c_lo);
1757 break;
1758 default:
1759 ShouldNotReachHere();
1760 }
1761 } else if (code == lir_logic_and &&
1762 c_hi == -1 &&
1763 (AsmOperand::is_rotated_imm(c_lo) ||
1764 AsmOperand::is_rotated_imm(~c_lo))) {
1765 // Another case which handles logic_and from do_ClassIDIntrinsic()
1766 if (AsmOperand::is_rotated_imm(c_lo)) {
1767 __ andr(res_lo, lreg_lo, c_lo);
1768 } else {
1769 __ bic(res_lo, lreg_lo, ~c_lo);
1770 }
1771 if (res_hi != lreg_hi) {
1772 __ mov(res_hi, lreg_hi);
1773 }
1774 } else {
1775 BAILOUT("64 bit constant cannot be inlined");
1776 }
1777 }
1778 }
1779 }
1780
1781
1782
1783 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1784 if (opr1->is_single_cpu()) {
1785 if (opr2->is_constant()) {
1786 switch (opr2->as_constant_ptr()->type()) {
1787 case T_INT: {
1788 const jint c = opr2->as_constant_ptr()->as_jint();
1789 if (Assembler::is_arith_imm_in_range(c)) {
1790 __ cmp_32(opr1->as_register(), c);
1791 } else if (Assembler::is_arith_imm_in_range(-c)) {
1792 __ cmn_32(opr1->as_register(), -c);
1793 } else {
1794 // This can happen when compiling lookupswitch
1795 __ mov_slow(Rtemp, c);
1796 __ cmp_32(opr1->as_register(), Rtemp);
1797 }
1798 break;
1799 }
1800 case T_OBJECT:
1801 assert(opr2->as_constant_ptr()->as_jobject() == nullptr, "cannot handle otherwise");
1802 __ cmp(opr1->as_register(), 0);
1803 break;
1804 case T_METADATA:
1805 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "Only equality tests");
1806 assert(opr2->as_constant_ptr()->as_metadata() == nullptr, "cannot handle otherwise");
1807 __ cmp(opr1->as_register(), 0);
1808 break;
1809 default:
1810 ShouldNotReachHere();
1811 }
1812 } else if (opr2->is_single_cpu()) {
1813 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1814 assert(opr2->type() == T_OBJECT || opr2->type() == T_ARRAY, "incompatibe type");
1815 __ cmpoop(opr1->as_register(), opr2->as_register());
1816 } else if (opr1->type() == T_METADATA || opr1->type() == T_ADDRESS) {
1817 assert(opr2->type() == T_METADATA || opr2->type() == T_ADDRESS, "incompatibe type");
1818 __ cmp(opr1->as_register(), opr2->as_register());
1819 } else {
1820 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_METADATA && opr2->type() != T_ADDRESS, "incompatibe type");
1821 __ cmp_32(opr1->as_register(), opr2->as_register());
1822 }
1823 } else {
1824 ShouldNotReachHere();
1825 }
1826 } else if (opr1->is_double_cpu()) {
1827 Register xlo = opr1->as_register_lo();
1828 Register xhi = opr1->as_register_hi();
1829 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1830 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "cannot handle otherwise");
1831 __ orrs(Rtemp, xlo, xhi);
1832 } else if (opr2->is_register()) {
1833 Register ylo = opr2->as_register_lo();
1834 Register yhi = opr2->as_register_hi();
1835 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1836 __ teq(xhi, yhi);
1837 __ teq(xlo, ylo, eq);
1838 } else {
1839 __ subs(Rtemp, xlo, ylo);
1840 __ sbcs(Rtemp, xhi, yhi);
1841 }
1842 } else {
1843 ShouldNotReachHere();
1844 }
1845 } else if (opr1->is_single_fpu()) {
1846 if (opr2->is_constant()) {
1847 assert(opr2->as_jfloat() == 0.0f, "cannot handle otherwise");
1848 __ cmp_zero_float(opr1->as_float_reg());
1849 } else {
1850 __ cmp_float(opr1->as_float_reg(), opr2->as_float_reg());
1851 }
1852 } else if (opr1->is_double_fpu()) {
1853 if (opr2->is_constant()) {
1854 assert(opr2->as_jdouble() == 0.0, "cannot handle otherwise");
1855 __ cmp_zero_double(opr1->as_double_reg());
1856 } else {
1857 __ cmp_double(opr1->as_double_reg(), opr2->as_double_reg());
1858 }
1859 } else {
1860 ShouldNotReachHere();
1861 }
1862 }
1863
1864 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1865 const Register res = dst->as_register();
1866 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1867 comp_op(lir_cond_unknown, left, right, op);
1868 __ fmstat();
1869 if (code == lir_ucmp_fd2i) { // unordered is less
1870 __ mvn(res, 0, lt);
1871 __ mov(res, 1, ge);
1872 } else { // unordered is greater
1873 __ mov(res, 1, cs);
1874 __ mvn(res, 0, cc);
1875 }
1876 __ mov(res, 0, eq);
1877
1878 } else {
1879 assert(code == lir_cmp_l2i, "must be");
1880
1881 Label done;
1882 const Register xlo = left->as_register_lo();
1883 const Register xhi = left->as_register_hi();
1884 const Register ylo = right->as_register_lo();
1885 const Register yhi = right->as_register_hi();
1886 __ cmp(xhi, yhi);
1887 __ mov(res, 1, gt);
1888 __ mvn(res, 0, lt);
1889 __ b(done, ne);
1890 __ subs(res, xlo, ylo);
1891 __ mov(res, 1, hi);
1892 __ mvn(res, 0, lo);
1893 __ bind(done);
1894 }
1895 }
1896
1897
1898 void LIR_Assembler::align_call(LIR_Code code) {
1899 // Not needed
1900 }
1901
1902
1903 void LIR_Assembler::call(LIR_OpJavaCall *op, relocInfo::relocType rtype) {
1904 int ret_addr_offset = __ patchable_call(op->addr(), rtype);
1905 assert(ret_addr_offset == __ offset(), "embedded return address not allowed");
1906 add_call_info_here(op->info());
1907 }
1908
1909
1910 void LIR_Assembler::ic_call(LIR_OpJavaCall *op) {
1911 bool near_range = __ cache_fully_reachable();
1912 address oop_address = pc();
1913
1914 bool use_movw = VM_Version::supports_movw();
1915
1916 // Ricklass may contain something that is not a metadata pointer so
1917 // mov_metadata can't be used
1918 InlinedAddress value((address)Universe::non_oop_word());
1919 InlinedAddress addr(op->addr());
1920 if (use_movw) {
1921 __ movw(Ricklass, ((unsigned int)Universe::non_oop_word()) & 0xffff);
1922 __ movt(Ricklass, ((unsigned int)Universe::non_oop_word()) >> 16);
1923 } else {
1924 // No movw/movt, must be load a pc relative value but no
1925 // relocation so no metadata table to load from.
1926 // Use a b instruction rather than a bl, inline constant after the
1927 // branch, use a PC relative ldr to load the constant, arrange for
1928 // the call to return after the constant(s).
1929 __ ldr_literal(Ricklass, value);
1930 }
1931 __ relocate(virtual_call_Relocation::spec(oop_address));
1932 if (near_range && use_movw) {
1933 __ bl(op->addr());
1934 } else {
1935 Label call_return;
1936 __ adr(LR, call_return);
1937 if (near_range) {
1938 __ b(op->addr());
1939 } else {
1940 __ indirect_jump(addr, Rtemp);
1941 __ bind_literal(addr);
1942 }
1943 if (!use_movw) {
1944 __ bind_literal(value);
1945 }
1946 __ bind(call_return);
1947 }
1948 add_call_info(code_offset(), op->info());
1949 }
1950
1951 void LIR_Assembler::emit_static_call_stub() {
1952 address call_pc = __ pc();
1953 address stub = __ start_a_stub(call_stub_size());
1954 if (stub == nullptr) {
1955 BAILOUT("static call stub overflow");
1956 }
1957
1958 DEBUG_ONLY(int offset = code_offset();)
1959
1960 InlinedMetadata metadata_literal(nullptr);
1961 __ relocate(static_stub_Relocation::spec(call_pc));
1962 // If not a single instruction, NativeMovConstReg::next_instruction_address()
1963 // must jump over the whole following ldr_literal.
1964 // (See CompiledDirectCall::set_to_interpreted())
1965 #ifdef ASSERT
1966 address ldr_site = __ pc();
1967 #endif
1968 __ ldr_literal(Rmethod, metadata_literal);
1969 assert(nativeMovConstReg_at(ldr_site)->next_instruction_address() == __ pc(), "Fix ldr_literal or its parsing");
1970 bool near_range = __ cache_fully_reachable();
1971 InlinedAddress dest((address)-1);
1972 if (near_range) {
1973 address branch_site = __ pc();
1974 __ b(branch_site); // b to self maps to special NativeJump -1 destination
1975 } else {
1976 __ indirect_jump(dest, Rtemp);
1977 }
1978 __ bind_literal(metadata_literal); // includes spec_for_immediate reloc
1979 if (!near_range) {
1980 __ bind_literal(dest); // special NativeJump -1 destination
1981 }
1982
1983 assert(code_offset() - offset <= call_stub_size(), "overflow");
1984 __ end_a_stub();
1985 }
1986
1987 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1988 assert(exceptionOop->as_register() == Rexception_obj, "must match");
1989 assert(exceptionPC->as_register() == Rexception_pc, "must match");
1990 info->add_register_oop(exceptionOop);
1991
1992 StubId handle_id = compilation()->has_fpu_code() ?
1993 StubId::c1_handle_exception_id :
1994 StubId::c1_handle_exception_nofpu_id;
1995 Label return_address;
1996 __ adr(Rexception_pc, return_address);
1997 __ call(Runtime1::entry_for(handle_id), relocInfo::runtime_call_type);
1998 __ bind(return_address);
1999 add_call_info_here(info); // for exception handler
2000 }
2001
2002 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2003 assert(exceptionOop->as_register() == Rexception_obj, "must match");
2004 __ b(_unwind_handler_entry);
2005 }
2006
2007 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2008 AsmShift shift = lsl;
2009 switch (code) {
2010 case lir_shl: shift = lsl; break;
2011 case lir_shr: shift = asr; break;
2012 case lir_ushr: shift = lsr; break;
2013 default: ShouldNotReachHere();
2014 }
2015
2016 if (dest->is_single_cpu()) {
2017 __ andr(Rtemp, count->as_register(), 31);
2018 __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, Rtemp));
2019 } else if (dest->is_double_cpu()) {
2020 Register dest_lo = dest->as_register_lo();
2021 Register dest_hi = dest->as_register_hi();
2022 Register src_lo = left->as_register_lo();
2023 Register src_hi = left->as_register_hi();
2024 Register Rcount = count->as_register();
2025 // Resolve possible register conflicts
2026 if (shift == lsl && dest_hi == src_lo) {
2027 dest_hi = Rtemp;
2028 } else if (shift != lsl && dest_lo == src_hi) {
2029 dest_lo = Rtemp;
2030 } else if (dest_lo == src_lo && dest_hi == src_hi) {
2031 dest_lo = Rtemp;
2032 } else if (dest_lo == Rcount || dest_hi == Rcount) {
2033 Rcount = Rtemp;
2034 }
2035 __ andr(Rcount, count->as_register(), 63);
2036 __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, Rcount);
2037 move_regs(dest_lo, dest->as_register_lo());
2038 move_regs(dest_hi, dest->as_register_hi());
2039 } else {
2040 ShouldNotReachHere();
2041 }
2042 }
2043
2044
2045 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2046 AsmShift shift = lsl;
2047 switch (code) {
2048 case lir_shl: shift = lsl; break;
2049 case lir_shr: shift = asr; break;
2050 case lir_ushr: shift = lsr; break;
2051 default: ShouldNotReachHere();
2052 }
2053
2054 if (dest->is_single_cpu()) {
2055 count &= 31;
2056 if (count != 0) {
2057 __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, count));
2058 } else {
2059 move_regs(left->as_register(), dest->as_register());
2060 }
2061 } else if (dest->is_double_cpu()) {
2062 count &= 63;
2063 if (count != 0) {
2064 Register dest_lo = dest->as_register_lo();
2065 Register dest_hi = dest->as_register_hi();
2066 Register src_lo = left->as_register_lo();
2067 Register src_hi = left->as_register_hi();
2068 // Resolve possible register conflicts
2069 if (shift == lsl && dest_hi == src_lo) {
2070 dest_hi = Rtemp;
2071 } else if (shift != lsl && dest_lo == src_hi) {
2072 dest_lo = Rtemp;
2073 }
2074 __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, count);
2075 move_regs(dest_lo, dest->as_register_lo());
2076 move_regs(dest_hi, dest->as_register_hi());
2077 } else {
2078 __ long_move(dest->as_register_lo(), dest->as_register_hi(),
2079 left->as_register_lo(), left->as_register_hi());
2080 }
2081 } else {
2082 ShouldNotReachHere();
2083 }
2084 }
2085
2086
2087 // Saves 4 given registers in reserved argument area.
2088 void LIR_Assembler::save_in_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2089 verify_reserved_argument_area_size(4);
2090 __ stmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4));
2091 }
2092
2093 // Restores 4 given registers from reserved argument area.
2094 void LIR_Assembler::restore_from_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2095 __ ldmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4), no_writeback);
2096 }
2097
2098
2099 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2100 ciArrayKlass* default_type = op->expected_type();
2101 Register src = op->src()->as_register();
2102 Register src_pos = op->src_pos()->as_register();
2103 Register dst = op->dst()->as_register();
2104 Register dst_pos = op->dst_pos()->as_register();
2105 Register length = op->length()->as_register();
2106 Register tmp = op->tmp()->as_register();
2107 Register tmp2 = Rtemp;
2108
2109 assert(src == R0 && src_pos == R1 && dst == R2 && dst_pos == R3, "code assumption");
2110
2111 CodeStub* stub = op->stub();
2112
2113 int flags = op->flags();
2114 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2115 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2116
2117 // If we don't know anything or it's an object array, just go through the generic arraycopy
2118 if (default_type == nullptr) {
2119
2120 // save arguments, because they will be killed by a runtime call
2121 save_in_reserved_area(R0, R1, R2, R3);
2122
2123 // pass length argument on SP[0]
2124 __ str(length, Address(SP, -2*wordSize, pre_indexed)); // 2 words for a proper stack alignment
2125
2126 address copyfunc_addr = StubRoutines::generic_arraycopy();
2127 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2128 #ifndef PRODUCT
2129 if (PrintC1Statistics) {
2130 __ inc_counter((address)&Runtime1::_generic_arraycopystub_cnt, tmp, tmp2);
2131 }
2132 #endif // !PRODUCT
2133 // the stub is in the code cache so close enough
2134 __ call(copyfunc_addr, relocInfo::runtime_call_type);
2135
2136 __ add(SP, SP, 2*wordSize);
2137
2138 __ cbz_32(R0, *stub->continuation());
2139
2140 __ mvn_32(tmp, R0);
2141 restore_from_reserved_area(R0, R1, R2, R3); // load saved arguments in slow case only
2142 __ sub_32(length, length, tmp);
2143 __ add_32(src_pos, src_pos, tmp);
2144 __ add_32(dst_pos, dst_pos, tmp);
2145
2146 __ b(*stub->entry());
2147
2148 __ bind(*stub->continuation());
2149 return;
2150 }
2151
2152 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(),
2153 "must be true at this point");
2154 int elem_size = type2aelembytes(basic_type);
2155 int shift = exact_log2(elem_size);
2156
2157 // Check for null
2158 if (flags & LIR_OpArrayCopy::src_null_check) {
2159 if (flags & LIR_OpArrayCopy::dst_null_check) {
2160 __ cmp(src, 0);
2161 __ cond_cmp(dst, 0, ne); // make one instruction shorter if both checks are needed
2162 __ b(*stub->entry(), eq);
2163 } else {
2164 __ cbz(src, *stub->entry());
2165 }
2166 } else if (flags & LIR_OpArrayCopy::dst_null_check) {
2167 __ cbz(dst, *stub->entry());
2168 }
2169
2170 // If the compiler was not able to prove that exact type of the source or the destination
2171 // of the arraycopy is an array type, check at runtime if the source or the destination is
2172 // an instance type.
2173 if (flags & LIR_OpArrayCopy::type_check) {
2174 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2175 __ load_klass(tmp, dst);
2176 __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2177 __ mov_slow(tmp, Klass::_lh_neutral_value);
2178 __ cmp_32(tmp2, tmp);
2179 __ b(*stub->entry(), ge);
2180 }
2181
2182 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2183 __ load_klass(tmp, src);
2184 __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2185 __ mov_slow(tmp, Klass::_lh_neutral_value);
2186 __ cmp_32(tmp2, tmp);
2187 __ b(*stub->entry(), ge);
2188 }
2189 }
2190
2191 // Check if negative
2192 const int all_positive_checks = LIR_OpArrayCopy::src_pos_positive_check |
2193 LIR_OpArrayCopy::dst_pos_positive_check |
2194 LIR_OpArrayCopy::length_positive_check;
2195 switch (flags & all_positive_checks) {
2196 case LIR_OpArrayCopy::src_pos_positive_check:
2197 __ branch_if_negative_32(src_pos, *stub->entry());
2198 break;
2199 case LIR_OpArrayCopy::dst_pos_positive_check:
2200 __ branch_if_negative_32(dst_pos, *stub->entry());
2201 break;
2202 case LIR_OpArrayCopy::length_positive_check:
2203 __ branch_if_negative_32(length, *stub->entry());
2204 break;
2205 case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::dst_pos_positive_check:
2206 __ branch_if_any_negative_32(src_pos, dst_pos, tmp, *stub->entry());
2207 break;
2208 case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2209 __ branch_if_any_negative_32(src_pos, length, tmp, *stub->entry());
2210 break;
2211 case LIR_OpArrayCopy::dst_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2212 __ branch_if_any_negative_32(dst_pos, length, tmp, *stub->entry());
2213 break;
2214 case all_positive_checks:
2215 __ branch_if_any_negative_32(src_pos, dst_pos, length, tmp, *stub->entry());
2216 break;
2217 default:
2218 assert((flags & all_positive_checks) == 0, "the last option");
2219 }
2220
2221 // Range checks
2222 if (flags & LIR_OpArrayCopy::src_range_check) {
2223 __ ldr_s32(tmp2, Address(src, arrayOopDesc::length_offset_in_bytes()));
2224 __ add_32(tmp, src_pos, length);
2225 __ cmp_32(tmp, tmp2);
2226 __ b(*stub->entry(), hi);
2227 }
2228 if (flags & LIR_OpArrayCopy::dst_range_check) {
2229 __ ldr_s32(tmp2, Address(dst, arrayOopDesc::length_offset_in_bytes()));
2230 __ add_32(tmp, dst_pos, length);
2231 __ cmp_32(tmp, tmp2);
2232 __ b(*stub->entry(), hi);
2233 }
2234
2235 // Check if src and dst are of the same type
2236 if (flags & LIR_OpArrayCopy::type_check) {
2237 // We don't know the array types are compatible
2238 if (basic_type != T_OBJECT) {
2239 // Simple test for basic type arrays
2240 __ load_klass(tmp, src);
2241 __ load_klass(tmp2, dst);
2242 __ cmp(tmp, tmp2);
2243 __ b(*stub->entry(), ne);
2244 } else {
2245 // For object arrays, if src is a sub class of dst then we can
2246 // safely do the copy.
2247 Label cont, slow;
2248
2249 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2250
2251 __ load_klass(tmp, src);
2252 __ load_klass(tmp2, dst);
2253
2254 // We are at a call so all live registers are saved before we
2255 // get here
2256 assert_different_registers(tmp, tmp2, R6, altFP_7_11);
2257
2258 __ check_klass_subtype_fast_path(tmp, tmp2, R6, altFP_7_11, &cont, copyfunc_addr == nullptr ? stub->entry() : &slow, nullptr);
2259
2260 __ mov(R6, R0);
2261 __ mov(altFP_7_11, R1);
2262 __ mov(R0, tmp);
2263 __ mov(R1, tmp2);
2264 __ call(Runtime1::entry_for(StubId::c1_slow_subtype_check_id), relocInfo::runtime_call_type); // does not blow any registers except R0, LR and Rtemp
2265 __ cmp_32(R0, 0);
2266 __ mov(R0, R6);
2267 __ mov(R1, altFP_7_11);
2268
2269 if (copyfunc_addr != nullptr) { // use stub if available
2270 // src is not a sub class of dst so we have to do a
2271 // per-element check.
2272
2273 __ b(cont, ne);
2274
2275 __ bind(slow);
2276
2277 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2278 if ((flags & mask) != mask) {
2279 // Check that at least both of them object arrays.
2280 assert(flags & mask, "one of the two should be known to be an object array");
2281
2282 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2283 __ load_klass(tmp, src);
2284 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2285 __ load_klass(tmp, dst);
2286 }
2287 int lh_offset = in_bytes(Klass::layout_helper_offset());
2288
2289 __ ldr_u32(tmp2, Address(tmp, lh_offset));
2290
2291 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2292 __ mov_slow(tmp, objArray_lh);
2293 __ cmp_32(tmp, tmp2);
2294 __ b(*stub->entry(), ne);
2295 }
2296
2297 save_in_reserved_area(R0, R1, R2, R3);
2298
2299 Register src_ptr = R0;
2300 Register dst_ptr = R1;
2301 Register len = R2;
2302 Register chk_off = R3;
2303 Register super_k = tmp;
2304
2305 __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2306 __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2307
2308 __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2309 __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2310 __ load_klass(tmp, dst);
2311
2312 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2313 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2314
2315 __ ldr(super_k, Address(tmp, ek_offset));
2316
2317 __ mov(len, length);
2318 __ ldr_u32(chk_off, Address(super_k, sco_offset));
2319 __ push(super_k);
2320
2321 __ call(copyfunc_addr, relocInfo::runtime_call_type);
2322
2323 #ifndef PRODUCT
2324 if (PrintC1Statistics) {
2325 Label failed;
2326 __ cbnz_32(R0, failed);
2327 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, tmp, tmp2);
2328 __ bind(failed);
2329 }
2330 #endif // PRODUCT
2331
2332 __ add(SP, SP, wordSize); // Drop super_k argument
2333
2334 __ cbz_32(R0, *stub->continuation());
2335 __ mvn_32(tmp, R0);
2336
2337 // load saved arguments in slow case only
2338 restore_from_reserved_area(R0, R1, R2, R3);
2339
2340 __ sub_32(length, length, tmp);
2341 __ add_32(src_pos, src_pos, tmp);
2342 __ add_32(dst_pos, dst_pos, tmp);
2343
2344 #ifndef PRODUCT
2345 if (PrintC1Statistics) {
2346 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, tmp, tmp2);
2347 }
2348 #endif
2349
2350 __ b(*stub->entry());
2351
2352 __ bind(cont);
2353 } else {
2354 __ b(*stub->entry(), eq);
2355 __ bind(cont);
2356 }
2357 }
2358 }
2359
2360 #ifndef PRODUCT
2361 if (PrintC1Statistics) {
2362 address counter = Runtime1::arraycopy_count_address(basic_type);
2363 __ inc_counter(counter, tmp, tmp2);
2364 }
2365 #endif // !PRODUCT
2366
2367 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2368 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2369 const char *name;
2370 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2371
2372 Register src_ptr = R0;
2373 Register dst_ptr = R1;
2374 Register len = R2;
2375
2376 __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2377 __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2378
2379 __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2380 __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2381
2382 __ mov(len, length);
2383
2384 __ call(entry, relocInfo::runtime_call_type);
2385
2386 __ bind(*stub->continuation());
2387 }
2388
2389 #ifdef ASSERT
2390 // emit run-time assertion
2391 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2392 assert(op->code() == lir_assert, "must be");
2393
2394 if (op->in_opr1()->is_valid()) {
2395 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2396 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2397 } else {
2398 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2399 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2400 }
2401
2402 Label ok;
2403 if (op->condition() != lir_cond_always) {
2404 AsmCondition acond = al;
2405 switch (op->condition()) {
2406 case lir_cond_equal: acond = eq; break;
2407 case lir_cond_notEqual: acond = ne; break;
2408 case lir_cond_less: acond = lt; break;
2409 case lir_cond_lessEqual: acond = le; break;
2410 case lir_cond_greaterEqual: acond = ge; break;
2411 case lir_cond_greater: acond = gt; break;
2412 case lir_cond_aboveEqual: acond = hs; break;
2413 case lir_cond_belowEqual: acond = ls; break;
2414 default: ShouldNotReachHere();
2415 }
2416 __ b(ok, acond);
2417 }
2418 if (op->halt()) {
2419 const char* str = __ code_string(op->msg());
2420 __ stop(str);
2421 } else {
2422 breakpoint();
2423 }
2424 __ bind(ok);
2425 }
2426 #endif // ASSERT
2427
2428 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2429 fatal("CRC32 intrinsic is not implemented on this platform");
2430 }
2431
2432 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2433 Register obj = op->obj_opr()->as_pointer_register();
2434 Register hdr = op->hdr_opr()->as_pointer_register();
2435 Register lock = op->lock_opr()->as_pointer_register();
2436
2437 if (op->code() == lir_lock) {
2438 int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry());
2439 if (op->info() != nullptr) {
2440 add_debug_info_for_null_check(null_check_offset, op->info());
2441 }
2442 } else if (op->code() == lir_unlock) {
2443 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2444 } else {
2445 ShouldNotReachHere();
2446 }
2447 __ bind(*op->stub()->continuation());
2448 }
2449
2450 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2451 Register obj = op->obj()->as_pointer_register();
2452 Register result = op->result_opr()->as_pointer_register();
2453
2454 CodeEmitInfo* info = op->info();
2455 if (info != nullptr) {
2456 add_debug_info_for_null_check_here(info);
2457 }
2458 __ ldr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
2459 }
2460
2461 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2462 ciMethod* method = op->profiled_method();
2463 int bci = op->profiled_bci();
2464 ciMethod* callee = op->profiled_callee();
2465
2466 // Update counter for all call types
2467 ciMethodData* md = method->method_data_or_null();
2468 assert(md != nullptr, "Sanity");
2469 ciProfileData* data = md->bci_to_data(bci);
2470 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2471 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2472 Register mdo = op->mdo()->as_register();
2473 assert(op->tmp1()->is_register(), "tmp1 must be allocated");
2474 Register tmp1 = op->tmp1()->as_pointer_register();
2475 assert_different_registers(mdo, tmp1);
2476 __ mov_metadata(mdo, md->constant_encoding());
2477 int mdo_offset_bias = 0;
2478 int max_offset = 4096;
2479 if (md->byte_offset_of_slot(data, CounterData::count_offset()) + data->size_in_bytes() >= max_offset) {
2480 // The offset is large so bias the mdo by the base of the slot so
2481 // that the ldr can use an immediate offset to reference the slots of the data
2482 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2483 __ mov_slow(tmp1, mdo_offset_bias);
2484 __ add(mdo, mdo, tmp1);
2485 }
2486
2487 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2488 // Perform additional virtual call profiling for invokevirtual and
2489 // invokeinterface bytecodes
2490 if (op->should_profile_receiver_type()) {
2491 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2492 Register recv = op->recv()->as_register();
2493 assert_different_registers(mdo, tmp1, recv);
2494 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2495 ciKlass* known_klass = op->known_holder();
2496 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2497 // We know the type that will be seen at this call site; we can
2498 // statically update the MethodData* rather than needing to do
2499 // dynamic tests on the receiver type
2500
2501 // NOTE: we should probably put a lock around this search to
2502 // avoid collisions by concurrent compilations
2503 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2504 uint i;
2505 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2506 ciKlass* receiver = vc_data->receiver(i);
2507 if (known_klass->equals(receiver)) {
2508 Address data_addr(mdo, md->byte_offset_of_slot(data,
2509 VirtualCallData::receiver_count_offset(i)) -
2510 mdo_offset_bias);
2511 __ ldr(tmp1, data_addr);
2512 __ add(tmp1, tmp1, DataLayout::counter_increment);
2513 __ str(tmp1, data_addr);
2514 return;
2515 }
2516 }
2517
2518 // Receiver type not found in profile data; select an empty slot
2519
2520 // Note that this is less efficient than it should be because it
2521 // always does a write to the receiver part of the
2522 // VirtualCallData rather than just the first time
2523 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2524 ciKlass* receiver = vc_data->receiver(i);
2525 if (receiver == nullptr) {
2526 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2527 mdo_offset_bias);
2528 __ mov_metadata(tmp1, known_klass->constant_encoding());
2529 __ str(tmp1, recv_addr);
2530 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2531 mdo_offset_bias);
2532 __ ldr(tmp1, data_addr);
2533 __ add(tmp1, tmp1, DataLayout::counter_increment);
2534 __ str(tmp1, data_addr);
2535 return;
2536 }
2537 }
2538 } else {
2539 __ load_klass(recv, recv);
2540 Label update_done;
2541 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2542 // Receiver did not match any saved receiver and there is no empty row for it.
2543 // Increment total counter to indicate polymorphic case.
2544 __ ldr(tmp1, counter_addr);
2545 __ add(tmp1, tmp1, DataLayout::counter_increment);
2546 __ str(tmp1, counter_addr);
2547
2548 __ bind(update_done);
2549 }
2550 } else {
2551 // Static call
2552 __ ldr(tmp1, counter_addr);
2553 __ add(tmp1, tmp1, DataLayout::counter_increment);
2554 __ str(tmp1, counter_addr);
2555 }
2556 }
2557
2558 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2559 fatal("Type profiling not implemented on this platform");
2560 }
2561
2562 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2563 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2564 __ add_slow(dst->as_pointer_register(), mon_addr.base(), mon_addr.disp());
2565 }
2566
2567
2568 void LIR_Assembler::align_backward_branch_target() {
2569 // Some ARM processors do better with 8-byte branch target alignment
2570 __ align(8);
2571 }
2572
2573
2574 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2575 // tmp must be unused
2576 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2577
2578 if (left->is_single_cpu()) {
2579 assert (dest->type() == T_INT, "unexpected result type");
2580 assert (left->type() == T_INT, "unexpected left type");
2581 __ neg_32(dest->as_register(), left->as_register());
2582 } else if (left->is_double_cpu()) {
2583 Register dest_lo = dest->as_register_lo();
2584 Register dest_hi = dest->as_register_hi();
2585 Register src_lo = left->as_register_lo();
2586 Register src_hi = left->as_register_hi();
2587 if (dest_lo == src_hi) {
2588 dest_lo = Rtemp;
2589 }
2590 __ rsbs(dest_lo, src_lo, 0);
2591 __ rsc(dest_hi, src_hi, 0);
2592 move_regs(dest_lo, dest->as_register_lo());
2593 } else if (left->is_single_fpu()) {
2594 __ neg_float(dest->as_float_reg(), left->as_float_reg());
2595 } else if (left->is_double_fpu()) {
2596 __ neg_double(dest->as_double_reg(), left->as_double_reg());
2597 } else {
2598 ShouldNotReachHere();
2599 }
2600 }
2601
2602
2603 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2604 assert(patch_code == lir_patch_none, "Patch code not supported");
2605 LIR_Address* addr = addr_opr->as_address_ptr();
2606 if (addr->index()->is_illegal()) {
2607 jint c = addr->disp();
2608 if (!Assembler::is_arith_imm_in_range(c)) {
2609 BAILOUT("illegal arithmetic operand");
2610 }
2611 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), c);
2612 } else {
2613 assert(addr->disp() == 0, "cannot handle otherwise");
2614 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(),
2615 AsmOperand(addr->index()->as_pointer_register(), lsl, addr->scale()));
2616 }
2617 }
2618
2619
2620 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2621 assert(!tmp->is_valid(), "don't need temporary");
2622 __ call(dest);
2623 if (info != nullptr) {
2624 add_call_info_here(info);
2625 }
2626 }
2627
2628
2629 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2630 assert((src->is_double_cpu() && dest->is_address()) ||
2631 (src->is_address() && dest->is_double_cpu()),
2632 "Simple move_op is called for all other cases");
2633
2634 int null_check_offset;
2635 if (dest->is_address()) {
2636 // Store
2637 const LIR_Address* addr = dest->as_address_ptr();
2638 const Register src_lo = src->as_register_lo();
2639 const Register src_hi = src->as_register_hi();
2640 assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2641
2642 if (src_lo->encoding() < src_hi->encoding()) {
2643 null_check_offset = __ offset();
2644 __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(src_hi));
2645 } else {
2646 assert(src_lo->encoding() < Rtemp->encoding(), "Rtemp is higher than any allocatable register");
2647 __ mov(Rtemp, src_hi);
2648 null_check_offset = __ offset();
2649 __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(Rtemp));
2650 }
2651 } else {
2652 // Load
2653 const LIR_Address* addr = src->as_address_ptr();
2654 const Register dest_lo = dest->as_register_lo();
2655 const Register dest_hi = dest->as_register_hi();
2656 assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2657
2658 null_check_offset = __ offset();
2659 if (dest_lo->encoding() < dest_hi->encoding()) {
2660 __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(dest_hi));
2661 } else {
2662 assert(dest_lo->encoding() < Rtemp->encoding(), "Rtemp is higher than any allocatable register");
2663 __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(Rtemp));
2664 __ mov(dest_hi, Rtemp);
2665 }
2666 }
2667
2668 if (info != nullptr) {
2669 add_debug_info_for_null_check(null_check_offset, info);
2670 }
2671 }
2672
2673
2674 void LIR_Assembler::membar() {
2675 __ membar(MacroAssembler::StoreLoad, Rtemp);
2676 }
2677
2678 void LIR_Assembler::membar_acquire() {
2679 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::LoadLoad | MacroAssembler::LoadStore), Rtemp);
2680 }
2681
2682 void LIR_Assembler::membar_release() {
2683 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2684 }
2685
2686 void LIR_Assembler::membar_loadload() {
2687 __ membar(MacroAssembler::LoadLoad, Rtemp);
2688 }
2689
2690 void LIR_Assembler::membar_storestore() {
2691 __ membar(MacroAssembler::StoreStore, Rtemp);
2692 }
2693
2694 void LIR_Assembler::membar_loadstore() {
2695 __ membar(MacroAssembler::LoadStore, Rtemp);
2696 }
2697
2698 void LIR_Assembler::membar_storeload() {
2699 __ membar(MacroAssembler::StoreLoad, Rtemp);
2700 }
2701
2702 void LIR_Assembler::on_spin_wait() {
2703 Unimplemented();
2704 }
2705
2706 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2707 // Not used on ARM
2708 Unimplemented();
2709 }
2710
2711 void LIR_Assembler::peephole(LIR_List* lir) {
2712 LIR_OpList* inst = lir->instructions_list();
2713 const int inst_length = inst->length();
2714 for (int i = 0; i < inst_length; i++) {
2715 LIR_Op* op = inst->at(i);
2716 switch (op->code()) {
2717 case lir_cmp: {
2718 // Replace:
2719 // cmp rX, y
2720 // cmove [EQ] y, z, rX
2721 // with
2722 // cmp rX, y
2723 // cmove [EQ] illegalOpr, z, rX
2724 //
2725 // or
2726 // cmp rX, y
2727 // cmove [NE] z, y, rX
2728 // with
2729 // cmp rX, y
2730 // cmove [NE] z, illegalOpr, rX
2731 //
2732 // moves from illegalOpr should be removed when converting LIR to native assembly
2733
2734 LIR_Op2* cmp = op->as_Op2();
2735 assert(cmp != nullptr, "cmp LIR instruction is not an op2");
2736
2737 if (i + 1 < inst_length) {
2738 LIR_Op2* cmove = inst->at(i + 1)->as_Op2();
2739 if (cmove != nullptr && cmove->code() == lir_cmove) {
2740 LIR_Opr cmove_res = cmove->result_opr();
2741 bool res_is_op1 = cmove_res == cmp->in_opr1();
2742 bool res_is_op2 = cmove_res == cmp->in_opr2();
2743 LIR_Opr cmp_res, cmp_arg;
2744 if (res_is_op1) {
2745 cmp_res = cmp->in_opr1();
2746 cmp_arg = cmp->in_opr2();
2747 } else if (res_is_op2) {
2748 cmp_res = cmp->in_opr2();
2749 cmp_arg = cmp->in_opr1();
2750 } else {
2751 cmp_res = LIR_OprFact::illegalOpr;
2752 cmp_arg = LIR_OprFact::illegalOpr;
2753 }
2754
2755 if (cmp_res != LIR_OprFact::illegalOpr) {
2756 LIR_Condition cond = cmove->condition();
2757 if (cond == lir_cond_equal && cmove->in_opr1() == cmp_arg) {
2758 cmove->set_in_opr1(LIR_OprFact::illegalOpr);
2759 } else if (cond == lir_cond_notEqual && cmove->in_opr2() == cmp_arg) {
2760 cmove->set_in_opr2(LIR_OprFact::illegalOpr);
2761 }
2762 }
2763 }
2764 }
2765 break;
2766 }
2767
2768 default:
2769 break;
2770 }
2771 }
2772 }
2773
2774 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2775 assert(src->is_address(), "sanity");
2776 Address addr = as_Address(src->as_address_ptr());
2777
2778 if (code == lir_xchg) {
2779 } else {
2780 assert (!data->is_oop(), "xadd for oops");
2781 }
2782
2783 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2784
2785 Label retry;
2786 __ bind(retry);
2787
2788 if (data->type() == T_INT || data->is_oop()) {
2789 Register dst = dest->as_register();
2790 Register new_val = noreg;
2791 __ ldrex(dst, addr);
2792 if (code == lir_xadd) {
2793 Register tmp_reg = tmp->as_register();
2794 if (data->is_constant()) {
2795 assert_different_registers(dst, tmp_reg);
2796 __ add_32(tmp_reg, dst, data->as_constant_ptr()->as_jint());
2797 } else {
2798 assert_different_registers(dst, tmp_reg, data->as_register());
2799 __ add_32(tmp_reg, dst, data->as_register());
2800 }
2801 new_val = tmp_reg;
2802 } else {
2803 if (UseCompressedOops && data->is_oop()) {
2804 new_val = tmp->as_pointer_register();
2805 } else {
2806 new_val = data->as_register();
2807 }
2808 assert_different_registers(dst, new_val);
2809 }
2810 __ strex(Rtemp, new_val, addr);
2811
2812 } else if (data->type() == T_LONG) {
2813 Register dst_lo = dest->as_register_lo();
2814 Register new_val_lo = noreg;
2815 Register dst_hi = dest->as_register_hi();
2816
2817 assert(dst_hi->encoding() == dst_lo->encoding() + 1, "non aligned register pair");
2818 assert((dst_lo->encoding() & 0x1) == 0, "misaligned register pair");
2819
2820 __ bind(retry);
2821 __ ldrexd(dst_lo, addr);
2822 if (code == lir_xadd) {
2823 Register tmp_lo = tmp->as_register_lo();
2824 Register tmp_hi = tmp->as_register_hi();
2825
2826 assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
2827 assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
2828
2829 if (data->is_constant()) {
2830 jlong c = data->as_constant_ptr()->as_jlong();
2831 assert((jlong)((jint)c) == c, "overflow");
2832 assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi);
2833 __ adds(tmp_lo, dst_lo, (jint)c);
2834 __ adc(tmp_hi, dst_hi, 0);
2835 } else {
2836 Register new_val_lo = data->as_register_lo();
2837 Register new_val_hi = data->as_register_hi();
2838 __ adds(tmp_lo, dst_lo, new_val_lo);
2839 __ adc(tmp_hi, dst_hi, new_val_hi);
2840 assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi, new_val_lo, new_val_hi);
2841 }
2842 new_val_lo = tmp_lo;
2843 } else {
2844 new_val_lo = data->as_register_lo();
2845 Register new_val_hi = data->as_register_hi();
2846
2847 assert_different_registers(dst_lo, dst_hi, new_val_lo, new_val_hi);
2848 assert(new_val_hi->encoding() == new_val_lo->encoding() + 1, "non aligned register pair");
2849 assert((new_val_lo->encoding() & 0x1) == 0, "misaligned register pair");
2850 }
2851 __ strexd(Rtemp, new_val_lo, addr);
2852 } else {
2853 ShouldNotReachHere();
2854 }
2855
2856 __ cbnz_32(Rtemp, retry);
2857 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
2858
2859 }
2860
2861 #undef __