1 /*
2 * Copyright (c) 2008, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/macroAssembler.inline.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc/shared/collectedHeap.hpp"
34 #include "memory/universe.hpp"
35 #include "nativeInst_arm.hpp"
36 #include "oops/objArrayKlass.hpp"
37 #include "runtime/frame.inline.hpp"
38 #include "runtime/sharedRuntime.hpp"
39 #include "runtime/stubRoutines.hpp"
40 #include "utilities/powerOfTwo.hpp"
41 #include "vmreg_arm.inline.hpp"
42
43 #define __ _masm->
44
45 // Note: Rtemp usage is this file should not impact C2 and should be
46 // correct as long as it is not implicitly used in lower layers (the
47 // arm [macro]assembler) and used with care in the other C1 specific
48 // files.
49
50 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
51 ShouldNotCallThis(); // Not used on ARM
52 return false;
53 }
54
55
56 LIR_Opr LIR_Assembler::receiverOpr() {
57 // The first register in Java calling conventions
58 return FrameMap::R0_oop_opr;
59 }
60
61 LIR_Opr LIR_Assembler::osrBufferPointer() {
62 return FrameMap::as_pointer_opr(R0);
63 }
64
65 #ifndef PRODUCT
66 void LIR_Assembler::verify_reserved_argument_area_size(int args_count) {
67 assert(args_count * wordSize <= frame_map()->reserved_argument_area_size(), "not enough space for arguments");
68 }
69 #endif // !PRODUCT
70
71 void LIR_Assembler::store_parameter(jint c, int offset_from_sp_in_words) {
72 assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
73 int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
74 assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
75 __ mov_slow(Rtemp, c);
76 __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
77 }
78
79 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_sp_in_words) {
80 assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
81 int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
82 assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
83 __ mov_metadata(Rtemp, m);
84 __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
85 }
86
87 //--------------fpu register translations-----------------------
88
89
90 void LIR_Assembler::breakpoint() {
91 __ breakpoint();
92 }
93
94 void LIR_Assembler::push(LIR_Opr opr) {
95 Unimplemented();
96 }
97
98 void LIR_Assembler::pop(LIR_Opr opr) {
99 Unimplemented();
100 }
101
102 //-------------------------------------------
103 Address LIR_Assembler::as_Address(LIR_Address* addr) {
104 Register base = addr->base()->as_pointer_register();
105
106
107 if (addr->index()->is_illegal() || addr->index()->is_constant()) {
108 int offset = addr->disp();
109 if (addr->index()->is_constant()) {
110 offset += addr->index()->as_constant_ptr()->as_jint() << addr->scale();
111 }
112
113 if ((offset <= -4096) || (offset >= 4096)) {
114 BAILOUT_("offset not in range", Address(base));
115 }
116
117 return Address(base, offset);
118
119 } else {
120 assert(addr->disp() == 0, "can't have both");
121 int scale = addr->scale();
122
123 assert(addr->index()->is_single_cpu(), "should be");
124 return scale >= 0 ? Address(base, addr->index()->as_register(), lsl, scale) :
125 Address(base, addr->index()->as_register(), lsr, -scale);
126 }
127 }
128
129 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
130 Address base = as_Address(addr);
131 assert(base.index() == noreg, "must be");
132 if (base.disp() + BytesPerWord >= 4096) { BAILOUT_("offset not in range", Address(base.base(),0)); }
133 return Address(base.base(), base.disp() + BytesPerWord);
134 }
135
136 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
137 return as_Address(addr);
138 }
139
140
141 void LIR_Assembler::osr_entry() {
142 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
143 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
144 ValueStack* entry_state = osr_entry->end()->state();
145 int number_of_locks = entry_state->locks_size();
146
147 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
148 Register OSR_buf = osrBufferPointer()->as_pointer_register();
149
150 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
151 int monitor_offset = (method()->max_locals() + 2 * (number_of_locks - 1)) * BytesPerWord;
152 for (int i = 0; i < number_of_locks; i++) {
153 int slot_offset = monitor_offset - (i * 2 * BytesPerWord);
154 if (slot_offset >= 4096 - BytesPerWord) {
155 __ add_slow(R2, OSR_buf, slot_offset);
156 __ ldr(R1, Address(R2, 0*BytesPerWord));
157 __ ldr(R2, Address(R2, 1*BytesPerWord));
158 } else {
159 __ ldr(R1, Address(OSR_buf, slot_offset + 0*BytesPerWord));
160 __ ldr(R2, Address(OSR_buf, slot_offset + 1*BytesPerWord));
161 }
162 __ str(R1, frame_map()->address_for_monitor_lock(i));
163 __ str(R2, frame_map()->address_for_monitor_object(i));
164 }
165 }
166
167
168 int LIR_Assembler::check_icache() {
169 return __ ic_check(CodeEntryAlignment);
170 }
171
172 void LIR_Assembler::clinit_barrier(ciMethod* method) {
173 ShouldNotReachHere(); // not implemented
174 }
175
176 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
177 jobject o = (jobject)Universe::non_oop_word();
178 int index = __ oop_recorder()->allocate_oop_index(o);
179
180 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), index);
181
182 __ patchable_mov_oop(reg, o, index);
183 patching_epilog(patch, lir_patch_normal, reg, info);
184 }
185
186
187 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
188 Metadata* o = (Metadata*)Universe::non_oop_word();
189 int index = __ oop_recorder()->allocate_metadata_index(o);
190 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
191
192 __ patchable_mov_metadata(reg, o, index);
193 patching_epilog(patch, lir_patch_normal, reg, info);
194 }
195
196
197 int LIR_Assembler::initial_frame_size_in_bytes() const {
198 // Subtracts two words to account for return address and link
199 return frame_map()->framesize()*VMRegImpl::stack_slot_size - 2*wordSize;
200 }
201
202
203 int LIR_Assembler::emit_exception_handler() {
204 address handler_base = __ start_a_stub(exception_handler_size());
205 if (handler_base == nullptr) {
206 bailout("exception handler overflow");
207 return -1;
208 }
209
210 int offset = code_offset();
211
212 // check that there is really an exception
213 __ verify_not_null_oop(Rexception_obj);
214
215 __ call(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id), relocInfo::runtime_call_type);
216 __ should_not_reach_here();
217
218 assert(code_offset() - offset <= exception_handler_size(), "overflow");
219 __ end_a_stub();
220
221 return offset;
222 }
223
224 // Emit the code to remove the frame from the stack in the exception
225 // unwind path.
226 int LIR_Assembler::emit_unwind_handler() {
227 #ifndef PRODUCT
228 if (CommentedAssembly) {
229 _masm->block_comment("Unwind handler");
230 }
231 #endif
232
233 int offset = code_offset();
234
235 // Fetch the exception from TLS and clear out exception related thread state
236 Register zero = __ zero_register(Rtemp);
237 __ ldr(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
238 __ str(zero, Address(Rthread, JavaThread::exception_oop_offset()));
239 __ str(zero, Address(Rthread, JavaThread::exception_pc_offset()));
240
241 __ bind(_unwind_handler_entry);
242 __ verify_not_null_oop(Rexception_obj);
243
244 // Perform needed unlocking
245 MonitorExitStub* stub = nullptr;
246 if (method()->is_synchronized()) {
247 monitor_address(0, FrameMap::R0_opr);
248 stub = new MonitorExitStub(FrameMap::R0_opr, 0);
249 __ unlock_object(R2, R1, R0, *stub->entry());
250 __ bind(*stub->continuation());
251 }
252
253 // remove the activation and dispatch to the unwind handler
254 __ remove_frame(initial_frame_size_in_bytes()); // restores FP and LR
255 __ jump(Runtime1::entry_for(StubId::c1_unwind_exception_id), relocInfo::runtime_call_type, Rtemp);
256
257 // Emit the slow path assembly
258 if (stub != nullptr) {
259 stub->emit_code(this);
260 }
261
262 return offset;
263 }
264
265
266 int LIR_Assembler::emit_deopt_handler() {
267 address handler_base = __ start_a_stub(deopt_handler_size());
268 if (handler_base == nullptr) {
269 bailout("deopt handler overflow");
270 return -1;
271 }
272
273 int offset = code_offset();
274
275 Label start;
276 __ bind(start);
277
278 __ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, noreg);
279
280 int entry_offset = __ offset();
281 __ mov_relative_address(LR, __ pc());
282 __ push(LR); // stub expects LR to be saved
283 __ b(start);
284
285 assert(code_offset() - offset <= deopt_handler_size(), "overflow");
286 __ end_a_stub();
287
288 return entry_offset;
289 }
290
291
292 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
293 // Pop the frame before safepoint polling
294 __ remove_frame(initial_frame_size_in_bytes());
295 __ read_polling_page(Rtemp, relocInfo::poll_return_type);
296 __ ret();
297 }
298
299 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
300
301 int offset = __ offset();
302 __ get_polling_page(Rtemp);
303 __ relocate(relocInfo::poll_type);
304 add_debug_info_for_branch(info); // help pc_desc_at to find correct scope for current PC
305 __ ldr(Rtemp, Address(Rtemp));
306
307 return offset;
308 }
309
310
311 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
312 if (from_reg != to_reg) {
313 __ mov(to_reg, from_reg);
314 }
315 }
316
317 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
318 assert(src->is_constant() && dest->is_register(), "must be");
319 LIR_Const* c = src->as_constant_ptr();
320
321 switch (c->type()) {
322 case T_ADDRESS:
323 case T_INT:
324 assert(patch_code == lir_patch_none, "no patching handled here");
325 __ mov_slow(dest->as_register(), c->as_jint());
326 break;
327
328 case T_LONG:
329 assert(patch_code == lir_patch_none, "no patching handled here");
330 __ mov_slow(dest->as_register_lo(), c->as_jint_lo());
331 __ mov_slow(dest->as_register_hi(), c->as_jint_hi());
332 break;
333
334 case T_OBJECT:
335 if (patch_code == lir_patch_none) {
336 __ mov_oop(dest->as_register(), c->as_jobject());
337 } else {
338 jobject2reg_with_patching(dest->as_register(), info);
339 }
340 break;
341
342 case T_METADATA:
343 if (patch_code == lir_patch_none) {
344 __ mov_metadata(dest->as_register(), c->as_metadata());
345 } else {
346 klass2reg_with_patching(dest->as_register(), info);
347 }
348 break;
349
350 case T_FLOAT:
351 if (dest->is_single_fpu()) {
352 __ mov_float(dest->as_float_reg(), c->as_jfloat());
353 } else {
354 // Simple getters can return float constant directly into r0
355 __ mov_slow(dest->as_register(), c->as_jint_bits());
356 }
357 break;
358
359 case T_DOUBLE:
360 if (dest->is_double_fpu()) {
361 __ mov_double(dest->as_double_reg(), c->as_jdouble());
362 } else {
363 // Simple getters can return double constant directly into r1r0
364 __ mov_slow(dest->as_register_lo(), c->as_jint_lo_bits());
365 __ mov_slow(dest->as_register_hi(), c->as_jint_hi_bits());
366 }
367 break;
368
369 default:
370 ShouldNotReachHere();
371 }
372 }
373
374 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
375 assert(src->is_constant(), "must be");
376 assert(dest->is_stack(), "must be");
377 LIR_Const* c = src->as_constant_ptr();
378
379 switch (c->type()) {
380 case T_INT: // fall through
381 case T_FLOAT:
382 __ mov_slow(Rtemp, c->as_jint_bits());
383 __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
384 break;
385
386 case T_ADDRESS:
387 __ mov_slow(Rtemp, c->as_jint());
388 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
389 break;
390
391 case T_OBJECT:
392 __ mov_oop(Rtemp, c->as_jobject());
393 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
394 break;
395
396 case T_LONG: // fall through
397 case T_DOUBLE:
398 __ mov_slow(Rtemp, c->as_jint_lo_bits());
399 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
400 if (c->as_jint_hi_bits() != c->as_jint_lo_bits()) {
401 __ mov_slow(Rtemp, c->as_jint_hi_bits());
402 }
403 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
404 break;
405
406 default:
407 ShouldNotReachHere();
408 }
409 }
410
411 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
412 CodeEmitInfo* info, bool wide) {
413 assert((src->as_constant_ptr()->type() == T_OBJECT && src->as_constant_ptr()->as_jobject() == nullptr),"cannot handle otherwise");
414 __ mov(Rtemp, 0);
415
416 int null_check_offset = code_offset();
417 __ str(Rtemp, as_Address(dest->as_address_ptr()));
418
419 if (info != nullptr) {
420 assert(false, "arm32 didn't support this before, investigate if bug");
421 add_debug_info_for_null_check(null_check_offset, info);
422 }
423 }
424
425 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
426 assert(src->is_register() && dest->is_register(), "must be");
427
428 if (src->is_single_cpu()) {
429 if (dest->is_single_cpu()) {
430 move_regs(src->as_register(), dest->as_register());
431 } else if (dest->is_single_fpu()) {
432 __ fmsr(dest->as_float_reg(), src->as_register());
433 } else {
434 ShouldNotReachHere();
435 }
436 } else if (src->is_double_cpu()) {
437 if (dest->is_double_cpu()) {
438 __ long_move(dest->as_register_lo(), dest->as_register_hi(), src->as_register_lo(), src->as_register_hi());
439 } else {
440 __ fmdrr(dest->as_double_reg(), src->as_register_lo(), src->as_register_hi());
441 }
442 } else if (src->is_single_fpu()) {
443 if (dest->is_single_fpu()) {
444 __ mov_float(dest->as_float_reg(), src->as_float_reg());
445 } else if (dest->is_single_cpu()) {
446 __ mov_fpr2gpr_float(dest->as_register(), src->as_float_reg());
447 } else {
448 ShouldNotReachHere();
449 }
450 } else if (src->is_double_fpu()) {
451 if (dest->is_double_fpu()) {
452 __ mov_double(dest->as_double_reg(), src->as_double_reg());
453 } else if (dest->is_double_cpu()) {
454 __ fmrrd(dest->as_register_lo(), dest->as_register_hi(), src->as_double_reg());
455 } else {
456 ShouldNotReachHere();
457 }
458 } else {
459 ShouldNotReachHere();
460 }
461 }
462
463 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
464 assert(src->is_register(), "should not call otherwise");
465 assert(dest->is_stack(), "should not call otherwise");
466
467 Address addr = dest->is_single_word() ?
468 frame_map()->address_for_slot(dest->single_stack_ix()) :
469 frame_map()->address_for_slot(dest->double_stack_ix());
470
471 assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
472 if (src->is_single_fpu() || src->is_double_fpu()) {
473 if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
474 }
475
476 if (src->is_single_cpu()) {
477 switch (type) {
478 case T_OBJECT:
479 case T_ARRAY: __ verify_oop(src->as_register()); // fall through
480 case T_ADDRESS:
481 case T_METADATA: __ str(src->as_register(), addr); break;
482 case T_FLOAT: // used in intBitsToFloat intrinsic implementation, fall through
483 case T_INT: __ str_32(src->as_register(), addr); break;
484 default:
485 ShouldNotReachHere();
486 }
487 } else if (src->is_double_cpu()) {
488 __ str(src->as_register_lo(), addr);
489 __ str(src->as_register_hi(), frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
490 } else if (src->is_single_fpu()) {
491 __ str_float(src->as_float_reg(), addr);
492 } else if (src->is_double_fpu()) {
493 __ str_double(src->as_double_reg(), addr);
494 } else {
495 ShouldNotReachHere();
496 }
497 }
498
499
500 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
501 LIR_PatchCode patch_code, CodeEmitInfo* info,
502 bool wide) {
503 LIR_Address* to_addr = dest->as_address_ptr();
504 Register base_reg = to_addr->base()->as_pointer_register();
505 const bool needs_patching = (patch_code != lir_patch_none);
506
507 PatchingStub* patch = nullptr;
508 if (needs_patching) {
509 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
510 }
511
512 int null_check_offset = code_offset();
513
514 switch (type) {
515 case T_ARRAY:
516 case T_OBJECT:
517 if (UseCompressedOops && !wide) {
518 ShouldNotReachHere();
519 } else {
520 __ str(src->as_register(), as_Address(to_addr));
521 }
522 break;
523
524 case T_ADDRESS:
525 __ str(src->as_pointer_register(), as_Address(to_addr));
526 break;
527
528 case T_BYTE:
529 case T_BOOLEAN:
530 __ strb(src->as_register(), as_Address(to_addr));
531 break;
532
533 case T_CHAR:
534 case T_SHORT:
535 __ strh(src->as_register(), as_Address(to_addr));
536 break;
537
538 case T_INT:
539 #ifdef __SOFTFP__
540 case T_FLOAT:
541 #endif // __SOFTFP__
542 __ str_32(src->as_register(), as_Address(to_addr));
543 break;
544
545
546 #ifdef __SOFTFP__
547 case T_DOUBLE:
548 #endif // __SOFTFP__
549 case T_LONG: {
550 Register from_lo = src->as_register_lo();
551 Register from_hi = src->as_register_hi();
552 if (to_addr->index()->is_register()) {
553 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
554 assert(to_addr->disp() == 0, "Not yet supporting both");
555 __ add(Rtemp, base_reg, to_addr->index()->as_register());
556 base_reg = Rtemp;
557 __ str(from_lo, Address(Rtemp));
558 if (patch != nullptr) {
559 __ nop(); // see comment before patching_epilog for 2nd str
560 patching_epilog(patch, lir_patch_low, base_reg, info);
561 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
562 patch_code = lir_patch_high;
563 }
564 __ str(from_hi, Address(Rtemp, BytesPerWord));
565 } else if (base_reg == from_lo) {
566 __ str(from_hi, as_Address_hi(to_addr));
567 if (patch != nullptr) {
568 __ nop(); // see comment before patching_epilog for 2nd str
569 patching_epilog(patch, lir_patch_high, base_reg, info);
570 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
571 patch_code = lir_patch_low;
572 }
573 __ str(from_lo, as_Address_lo(to_addr));
574 } else {
575 __ str(from_lo, as_Address_lo(to_addr));
576 if (patch != nullptr) {
577 __ nop(); // see comment before patching_epilog for 2nd str
578 patching_epilog(patch, lir_patch_low, base_reg, info);
579 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
580 patch_code = lir_patch_high;
581 }
582 __ str(from_hi, as_Address_hi(to_addr));
583 }
584 break;
585 }
586
587 #ifndef __SOFTFP__
588 case T_FLOAT:
589 if (to_addr->index()->is_register()) {
590 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
591 __ add(Rtemp, base_reg, to_addr->index()->as_register());
592 if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
593 __ fsts(src->as_float_reg(), Address(Rtemp, to_addr->disp()));
594 } else {
595 __ fsts(src->as_float_reg(), as_Address(to_addr));
596 }
597 break;
598
599 case T_DOUBLE:
600 if (to_addr->index()->is_register()) {
601 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
602 __ add(Rtemp, base_reg, to_addr->index()->as_register());
603 if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
604 __ fstd(src->as_double_reg(), Address(Rtemp, to_addr->disp()));
605 } else {
606 __ fstd(src->as_double_reg(), as_Address(to_addr));
607 }
608 break;
609 #endif // __SOFTFP__
610
611
612 default:
613 ShouldNotReachHere();
614 }
615
616 if (info != nullptr) {
617 add_debug_info_for_null_check(null_check_offset, info);
618 }
619
620 if (patch != nullptr) {
621 // Offset embedded into LDR/STR instruction may appear not enough
622 // to address a field. So, provide a space for one more instruction
623 // that will deal with larger offsets.
624 __ nop();
625 patching_epilog(patch, patch_code, base_reg, info);
626 }
627 }
628
629
630 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
631 assert(src->is_stack(), "should not call otherwise");
632 assert(dest->is_register(), "should not call otherwise");
633
634 Address addr = src->is_single_word() ?
635 frame_map()->address_for_slot(src->single_stack_ix()) :
636 frame_map()->address_for_slot(src->double_stack_ix());
637
638 assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
639 if (dest->is_single_fpu() || dest->is_double_fpu()) {
640 if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
641 }
642
643 if (dest->is_single_cpu()) {
644 switch (type) {
645 case T_OBJECT:
646 case T_ARRAY:
647 case T_ADDRESS:
648 case T_METADATA: __ ldr(dest->as_register(), addr); break;
649 case T_FLOAT: // used in floatToRawIntBits intrinsic implementation
650 case T_INT: __ ldr_u32(dest->as_register(), addr); break;
651 default:
652 ShouldNotReachHere();
653 }
654 if ((type == T_OBJECT) || (type == T_ARRAY)) {
655 __ verify_oop(dest->as_register());
656 }
657 } else if (dest->is_double_cpu()) {
658 __ ldr(dest->as_register_lo(), addr);
659 __ ldr(dest->as_register_hi(), frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
660 } else if (dest->is_single_fpu()) {
661 __ ldr_float(dest->as_float_reg(), addr);
662 } else if (dest->is_double_fpu()) {
663 __ ldr_double(dest->as_double_reg(), addr);
664 } else {
665 ShouldNotReachHere();
666 }
667 }
668
669
670 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
671 if (src->is_single_stack()) {
672 switch (src->type()) {
673 case T_OBJECT:
674 case T_ARRAY:
675 case T_ADDRESS:
676 case T_METADATA:
677 __ ldr(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
678 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
679 break;
680
681 case T_INT:
682 case T_FLOAT:
683 __ ldr_u32(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
684 __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
685 break;
686
687 default:
688 ShouldNotReachHere();
689 }
690 } else {
691 assert(src->is_double_stack(), "must be");
692 __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes));
693 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
694 __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
695 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
696 }
697 }
698
699
700 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
701 LIR_PatchCode patch_code, CodeEmitInfo* info,
702 bool wide) {
703 assert(src->is_address(), "should not call otherwise");
704 assert(dest->is_register(), "should not call otherwise");
705 LIR_Address* addr = src->as_address_ptr();
706
707 Register base_reg = addr->base()->as_pointer_register();
708
709 PatchingStub* patch = nullptr;
710 if (patch_code != lir_patch_none) {
711 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
712 }
713 if (info != nullptr) {
714 add_debug_info_for_null_check_here(info);
715 }
716
717 switch (type) {
718 case T_OBJECT: // fall through
719 case T_ARRAY:
720 if (UseCompressedOops && !wide) {
721 __ ldr_u32(dest->as_register(), as_Address(addr));
722 } else {
723 __ ldr(dest->as_register(), as_Address(addr));
724 }
725 break;
726
727 case T_ADDRESS:
728 __ ldr(dest->as_pointer_register(), as_Address(addr));
729 break;
730
731 case T_INT:
732 #ifdef __SOFTFP__
733 case T_FLOAT:
734 #endif // __SOFTFP__
735 __ ldr(dest->as_pointer_register(), as_Address(addr));
736 break;
737
738 case T_BOOLEAN:
739 __ ldrb(dest->as_register(), as_Address(addr));
740 break;
741
742 case T_BYTE:
743 __ ldrsb(dest->as_register(), as_Address(addr));
744 break;
745
746 case T_CHAR:
747 __ ldrh(dest->as_register(), as_Address(addr));
748 break;
749
750 case T_SHORT:
751 __ ldrsh(dest->as_register(), as_Address(addr));
752 break;
753
754
755 #ifdef __SOFTFP__
756 case T_DOUBLE:
757 #endif // __SOFTFP__
758 case T_LONG: {
759 Register to_lo = dest->as_register_lo();
760 Register to_hi = dest->as_register_hi();
761 if (addr->index()->is_register()) {
762 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
763 assert(addr->disp() == 0, "Not yet supporting both");
764 __ add(Rtemp, base_reg, addr->index()->as_register());
765 base_reg = Rtemp;
766 __ ldr(to_lo, Address(Rtemp));
767 if (patch != nullptr) {
768 __ nop(); // see comment before patching_epilog for 2nd ldr
769 patching_epilog(patch, lir_patch_low, base_reg, info);
770 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
771 patch_code = lir_patch_high;
772 }
773 __ ldr(to_hi, Address(Rtemp, BytesPerWord));
774 } else if (base_reg == to_lo) {
775 __ ldr(to_hi, as_Address_hi(addr));
776 if (patch != nullptr) {
777 __ nop(); // see comment before patching_epilog for 2nd ldr
778 patching_epilog(patch, lir_patch_high, base_reg, info);
779 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
780 patch_code = lir_patch_low;
781 }
782 __ ldr(to_lo, as_Address_lo(addr));
783 } else {
784 __ ldr(to_lo, as_Address_lo(addr));
785 if (patch != nullptr) {
786 __ nop(); // see comment before patching_epilog for 2nd ldr
787 patching_epilog(patch, lir_patch_low, base_reg, info);
788 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
789 patch_code = lir_patch_high;
790 }
791 __ ldr(to_hi, as_Address_hi(addr));
792 }
793 break;
794 }
795
796 #ifndef __SOFTFP__
797 case T_FLOAT:
798 if (addr->index()->is_register()) {
799 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
800 __ add(Rtemp, base_reg, addr->index()->as_register());
801 if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
802 __ flds(dest->as_float_reg(), Address(Rtemp, addr->disp()));
803 } else {
804 __ flds(dest->as_float_reg(), as_Address(addr));
805 }
806 break;
807
808 case T_DOUBLE:
809 if (addr->index()->is_register()) {
810 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
811 __ add(Rtemp, base_reg, addr->index()->as_register());
812 if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
813 __ fldd(dest->as_double_reg(), Address(Rtemp, addr->disp()));
814 } else {
815 __ fldd(dest->as_double_reg(), as_Address(addr));
816 }
817 break;
818 #endif // __SOFTFP__
819
820
821 default:
822 ShouldNotReachHere();
823 }
824
825 if (patch != nullptr) {
826 // Offset embedded into LDR/STR instruction may appear not enough
827 // to address a field. So, provide a space for one more instruction
828 // that will deal with larger offsets.
829 __ nop();
830 patching_epilog(patch, patch_code, base_reg, info);
831 }
832
833 }
834
835
836 void LIR_Assembler::emit_op3(LIR_Op3* op) {
837 bool is_32 = op->result_opr()->is_single_cpu();
838
839 if (op->code() == lir_idiv && op->in_opr2()->is_constant() && is_32) {
840 int c = op->in_opr2()->as_constant_ptr()->as_jint();
841 assert(is_power_of_2(c), "non power-of-2 constant should be put in a register");
842
843 Register left = op->in_opr1()->as_register();
844 Register dest = op->result_opr()->as_register();
845 if (c == 1) {
846 __ mov(dest, left);
847 } else if (c == 2) {
848 __ add_32(dest, left, AsmOperand(left, lsr, 31));
849 __ asr_32(dest, dest, 1);
850 } else if (c != (int) 0x80000000) {
851 int power = log2i_exact(c);
852 __ asr_32(Rtemp, left, 31);
853 __ add_32(dest, left, AsmOperand(Rtemp, lsr, 32-power)); // dest = left + (left < 0 ? 2^power - 1 : 0);
854 __ asr_32(dest, dest, power); // dest = dest >>> power;
855 } else {
856 // x/0x80000000 is a special case, since dividend is a power of two, but is negative.
857 // The only possible result values are 0 and 1, with 1 only for dividend == divisor == 0x80000000.
858 __ cmp_32(left, c);
859 __ mov(dest, 0, ne);
860 __ mov(dest, 1, eq);
861 }
862 } else {
863 assert(op->code() == lir_idiv || op->code() == lir_irem, "unexpected op3");
864 __ call(StubRoutines::Arm::idiv_irem_entry(), relocInfo::runtime_call_type);
865 add_debug_info_for_div0_here(op->info());
866 }
867 }
868
869
870 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
871 #ifdef ASSERT
872 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
873 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
874 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
875 assert(op->info() == nullptr, "CodeEmitInfo?");
876 #endif // ASSERT
877
878 #ifdef __SOFTFP__
879 assert (op->code() != lir_cond_float_branch, "this should be impossible");
880 #else
881 if (op->code() == lir_cond_float_branch) {
882 __ fmstat();
883 __ b(*(op->ublock()->label()), vs);
884 }
885 #endif // __SOFTFP__
886
887 AsmCondition acond = al;
888 switch (op->cond()) {
889 case lir_cond_equal: acond = eq; break;
890 case lir_cond_notEqual: acond = ne; break;
891 case lir_cond_less: acond = lt; break;
892 case lir_cond_lessEqual: acond = le; break;
893 case lir_cond_greaterEqual: acond = ge; break;
894 case lir_cond_greater: acond = gt; break;
895 case lir_cond_aboveEqual: acond = hs; break;
896 case lir_cond_belowEqual: acond = ls; break;
897 default: assert(op->cond() == lir_cond_always, "must be");
898 }
899 __ b(*(op->label()), acond);
900 }
901
902
903 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
904 LIR_Opr src = op->in_opr();
905 LIR_Opr dest = op->result_opr();
906
907 switch (op->bytecode()) {
908 case Bytecodes::_i2l:
909 move_regs(src->as_register(), dest->as_register_lo());
910 __ mov(dest->as_register_hi(), AsmOperand(src->as_register(), asr, 31));
911 break;
912 case Bytecodes::_l2i:
913 move_regs(src->as_register_lo(), dest->as_register());
914 break;
915 case Bytecodes::_i2b:
916 __ sign_extend(dest->as_register(), src->as_register(), 8);
917 break;
918 case Bytecodes::_i2s:
919 __ sign_extend(dest->as_register(), src->as_register(), 16);
920 break;
921 case Bytecodes::_i2c:
922 __ zero_extend(dest->as_register(), src->as_register(), 16);
923 break;
924 case Bytecodes::_f2d:
925 __ convert_f2d(dest->as_double_reg(), src->as_float_reg());
926 break;
927 case Bytecodes::_d2f:
928 __ convert_d2f(dest->as_float_reg(), src->as_double_reg());
929 break;
930 case Bytecodes::_i2f:
931 __ fmsr(Stemp, src->as_register());
932 __ fsitos(dest->as_float_reg(), Stemp);
933 break;
934 case Bytecodes::_i2d:
935 __ fmsr(Stemp, src->as_register());
936 __ fsitod(dest->as_double_reg(), Stemp);
937 break;
938 case Bytecodes::_f2i:
939 __ ftosizs(Stemp, src->as_float_reg());
940 __ fmrs(dest->as_register(), Stemp);
941 break;
942 case Bytecodes::_d2i:
943 __ ftosizd(Stemp, src->as_double_reg());
944 __ fmrs(dest->as_register(), Stemp);
945 break;
946 default:
947 ShouldNotReachHere();
948 }
949 }
950
951
952 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
953 if (op->init_check()) {
954 Register tmp = op->tmp1()->as_register();
955 __ ldrb(tmp, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
956 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::LoadLoad | MacroAssembler::LoadStore), Rtemp);
957 add_debug_info_for_null_check_here(op->stub()->info());
958 __ cmp(tmp, InstanceKlass::fully_initialized);
959 __ b(*op->stub()->entry(), ne);
960 }
961 __ allocate_object(op->obj()->as_register(),
962 op->tmp1()->as_register(),
963 op->tmp2()->as_register(),
964 op->tmp3()->as_register(),
965 op->header_size(),
966 op->object_size(),
967 op->klass()->as_register(),
968 *op->stub()->entry());
969 __ bind(*op->stub()->continuation());
970 }
971
972 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
973 if (UseSlowPath ||
974 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
975 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
976 __ b(*op->stub()->entry());
977 } else {
978 __ allocate_array(op->obj()->as_register(),
979 op->len()->as_register(),
980 op->tmp1()->as_register(),
981 op->tmp2()->as_register(),
982 op->tmp3()->as_register(),
983 arrayOopDesc::base_offset_in_bytes(op->type()),
984 type2aelembytes(op->type()),
985 op->klass()->as_register(),
986 *op->stub()->entry());
987 }
988 __ bind(*op->stub()->continuation());
989 }
990
991 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
992 ciMethodData *md, ciProfileData *data,
993 Register recv, Register tmp1, Label* update_done) {
994 assert_different_registers(mdo, recv, tmp1);
995 uint i;
996 for (i = 0; i < VirtualCallData::row_limit(); i++) {
997 Label next_test;
998 // See if the receiver is receiver[n].
999 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
1000 mdo_offset_bias);
1001 __ ldr(tmp1, receiver_addr);
1002 __ verify_klass_ptr(tmp1);
1003 __ cmp(recv, tmp1);
1004 __ b(next_test, ne);
1005 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1006 mdo_offset_bias);
1007 __ ldr(tmp1, data_addr);
1008 __ add(tmp1, tmp1, DataLayout::counter_increment);
1009 __ str(tmp1, data_addr);
1010 __ b(*update_done);
1011 __ bind(next_test);
1012 }
1013
1014 // Didn't find receiver; find next empty slot and fill it in
1015 for (i = 0; i < VirtualCallData::row_limit(); i++) {
1016 Label next_test;
1017 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
1018 mdo_offset_bias);
1019 __ ldr(tmp1, recv_addr);
1020 __ cbnz(tmp1, next_test);
1021 __ str(recv, recv_addr);
1022 __ mov(tmp1, DataLayout::counter_increment);
1023 __ str(tmp1, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1024 mdo_offset_bias));
1025 __ b(*update_done);
1026 __ bind(next_test);
1027 }
1028 }
1029
1030 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
1031 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
1032 md = method->method_data_or_null();
1033 assert(md != nullptr, "Sanity");
1034 data = md->bci_to_data(bci);
1035 assert(data != nullptr, "need data for checkcast");
1036 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1037 if (md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes() >= 4096) {
1038 // The offset is large so bias the mdo by the base of the slot so
1039 // that the ldr can use an immediate offset to reference the slots of the data
1040 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
1041 }
1042 }
1043
1044 // On 32-bit ARM, code before this helper should test obj for null (ZF should be set if obj is null).
1045 void LIR_Assembler::typecheck_profile_helper1(ciMethod* method, int bci,
1046 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias,
1047 Register obj, Register mdo, Register data_val, Label* obj_is_null) {
1048 assert(method != nullptr, "Should have method");
1049 assert_different_registers(obj, mdo, data_val);
1050 setup_md_access(method, bci, md, data, mdo_offset_bias);
1051 Label not_null;
1052 __ b(not_null, ne);
1053 __ mov_metadata(mdo, md->constant_encoding());
1054 if (mdo_offset_bias > 0) {
1055 __ mov_slow(data_val, mdo_offset_bias);
1056 __ add(mdo, mdo, data_val);
1057 }
1058 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
1059 __ ldrb(data_val, flags_addr);
1060 __ orr(data_val, data_val, (uint)BitData::null_seen_byte_constant());
1061 __ strb(data_val, flags_addr);
1062 __ b(*obj_is_null);
1063 __ bind(not_null);
1064 }
1065
1066 void LIR_Assembler::typecheck_profile_helper2(ciMethodData* md, ciProfileData* data, int mdo_offset_bias,
1067 Register mdo, Register recv, Register value, Register tmp1,
1068 Label* profile_cast_success, Label* profile_cast_failure,
1069 Label* success, Label* failure) {
1070 assert_different_registers(mdo, value, tmp1);
1071 __ bind(*profile_cast_success);
1072 __ mov_metadata(mdo, md->constant_encoding());
1073 if (mdo_offset_bias > 0) {
1074 __ mov_slow(tmp1, mdo_offset_bias);
1075 __ add(mdo, mdo, tmp1);
1076 }
1077 __ load_klass(recv, value);
1078 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
1079 __ b(*success);
1080 // Cast failure case
1081 __ bind(*profile_cast_failure);
1082 __ mov_metadata(mdo, md->constant_encoding());
1083 if (mdo_offset_bias > 0) {
1084 __ mov_slow(tmp1, mdo_offset_bias);
1085 __ add(mdo, mdo, tmp1);
1086 }
1087 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
1088 __ ldr(tmp1, data_addr);
1089 __ sub(tmp1, tmp1, DataLayout::counter_increment);
1090 __ str(tmp1, data_addr);
1091 __ b(*failure);
1092 }
1093
1094 // Sets `res` to true, if `cond` holds.
1095 static void set_instanceof_result(MacroAssembler* _masm, Register res, AsmCondition cond) {
1096 __ mov(res, 1, cond);
1097 }
1098
1099
1100 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1101 // TODO: ARM - can be more effective with one more register
1102 switch (op->code()) {
1103 case lir_store_check: {
1104 CodeStub* stub = op->stub();
1105 Register value = op->object()->as_register();
1106 Register array = op->array()->as_register();
1107 Register klass_RInfo = op->tmp1()->as_register();
1108 Register k_RInfo = op->tmp2()->as_register();
1109 assert_different_registers(klass_RInfo, k_RInfo, Rtemp);
1110 if (op->should_profile()) {
1111 assert_different_registers(value, klass_RInfo, k_RInfo, Rtemp);
1112 }
1113
1114 // check if it needs to be profiled
1115 ciMethodData* md;
1116 ciProfileData* data;
1117 int mdo_offset_bias = 0;
1118 Label profile_cast_success, profile_cast_failure, done;
1119 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1120 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1121
1122 if (op->should_profile()) {
1123 __ cmp(value, 0);
1124 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, value, k_RInfo, Rtemp, &done);
1125 } else {
1126 __ cbz(value, done);
1127 }
1128 assert_different_registers(k_RInfo, value);
1129 add_debug_info_for_null_check_here(op->info_for_exception());
1130 __ load_klass(k_RInfo, array);
1131 __ load_klass(klass_RInfo, value);
1132 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1133 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1134 // check for immediate positive hit
1135 __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1136 __ cmp(klass_RInfo, k_RInfo);
1137 __ cond_cmp(Rtemp, k_RInfo, ne);
1138 __ b(*success_target, eq);
1139 // check for immediate negative hit
1140 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1141 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1142 __ b(*failure_target, ne);
1143 // slow case
1144 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1145 __ call(Runtime1::entry_for(StubId::c1_slow_subtype_check_id), relocInfo::runtime_call_type);
1146 __ cbz(R0, *failure_target);
1147 if (op->should_profile()) {
1148 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1149 if (mdo == value) {
1150 mdo = k_RInfo;
1151 recv = klass_RInfo;
1152 }
1153 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, value, tmp1,
1154 &profile_cast_success, &profile_cast_failure,
1155 &done, stub->entry());
1156 }
1157 __ bind(done);
1158 break;
1159 }
1160
1161 case lir_checkcast: {
1162 CodeStub* stub = op->stub();
1163 Register obj = op->object()->as_register();
1164 Register res = op->result_opr()->as_register();
1165 Register klass_RInfo = op->tmp1()->as_register();
1166 Register k_RInfo = op->tmp2()->as_register();
1167 ciKlass* k = op->klass();
1168 assert_different_registers(res, k_RInfo, klass_RInfo, Rtemp);
1169
1170 if (stub->is_simple_exception_stub()) {
1171 // TODO: ARM - Late binding is used to prevent confusion of register allocator
1172 assert(stub->is_exception_throw_stub(), "must be");
1173 ((SimpleExceptionStub*)stub)->set_obj(op->result_opr());
1174 }
1175 ciMethodData* md;
1176 ciProfileData* data;
1177 int mdo_offset_bias = 0;
1178
1179 Label done;
1180
1181 Label profile_cast_failure, profile_cast_success;
1182 Label *failure_target = op->should_profile() ? &profile_cast_failure : op->stub()->entry();
1183 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1184
1185
1186 __ movs(res, obj);
1187 if (op->should_profile()) {
1188 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1189 } else {
1190 __ b(done, eq);
1191 }
1192 if (k->is_loaded()) {
1193 __ mov_metadata(k_RInfo, k->constant_encoding());
1194 } else if (k_RInfo != obj) {
1195 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1196 __ movs(res, obj);
1197 } else {
1198 // Patching doesn't update "res" register after GC, so do patching first
1199 klass2reg_with_patching(Rtemp, op->info_for_patch());
1200 __ movs(res, obj);
1201 __ mov(k_RInfo, Rtemp);
1202 }
1203 __ load_klass(klass_RInfo, res, ne);
1204
1205 if (op->fast_check()) {
1206 __ cmp(klass_RInfo, k_RInfo, ne);
1207 __ b(*failure_target, ne);
1208 } else if (k->is_loaded()) {
1209 __ b(*success_target, eq);
1210 __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1211 if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1212 __ cmp(Rtemp, k_RInfo);
1213 __ b(*failure_target, ne);
1214 } else {
1215 __ cmp(klass_RInfo, k_RInfo);
1216 __ cmp(Rtemp, k_RInfo, ne);
1217 __ b(*success_target, eq);
1218 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1219 __ call(Runtime1::entry_for(StubId::c1_slow_subtype_check_id), relocInfo::runtime_call_type);
1220 __ cbz(R0, *failure_target);
1221 }
1222 } else {
1223 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1224 __ b(*success_target, eq);
1225 // check for immediate positive hit
1226 __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1227 __ cmp(klass_RInfo, k_RInfo);
1228 __ cmp(Rtemp, k_RInfo, ne);
1229 __ b(*success_target, eq);
1230 // check for immediate negative hit
1231 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1232 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1233 __ b(*failure_target, ne);
1234 // slow case
1235 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1236 __ call(Runtime1::entry_for(StubId::c1_slow_subtype_check_id), relocInfo::runtime_call_type);
1237 __ cbz(R0, *failure_target);
1238 }
1239
1240 if (op->should_profile()) {
1241 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1242 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1243 &profile_cast_success, &profile_cast_failure,
1244 &done, stub->entry());
1245 }
1246 __ bind(done);
1247 break;
1248 }
1249
1250 case lir_instanceof: {
1251 Register obj = op->object()->as_register();
1252 Register res = op->result_opr()->as_register();
1253 Register klass_RInfo = op->tmp1()->as_register();
1254 Register k_RInfo = op->tmp2()->as_register();
1255 ciKlass* k = op->klass();
1256 assert_different_registers(res, klass_RInfo, k_RInfo, Rtemp);
1257
1258 ciMethodData* md;
1259 ciProfileData* data;
1260 int mdo_offset_bias = 0;
1261
1262 Label done;
1263
1264 Label profile_cast_failure, profile_cast_success;
1265 Label *failure_target = op->should_profile() ? &profile_cast_failure : &done;
1266 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1267
1268 __ movs(res, obj);
1269
1270 if (op->should_profile()) {
1271 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1272 } else {
1273 __ b(done, eq);
1274 }
1275
1276 if (k->is_loaded()) {
1277 __ mov_metadata(k_RInfo, k->constant_encoding());
1278 } else {
1279 op->info_for_patch()->add_register_oop(FrameMap::as_oop_opr(res));
1280 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1281 }
1282 __ load_klass(klass_RInfo, res);
1283
1284 if (!op->should_profile()) {
1285 __ mov(res, 0);
1286 }
1287
1288 if (op->fast_check()) {
1289 __ cmp(klass_RInfo, k_RInfo);
1290 if (!op->should_profile()) {
1291 set_instanceof_result(_masm, res, eq);
1292 } else {
1293 __ b(profile_cast_failure, ne);
1294 }
1295 } else if (k->is_loaded()) {
1296 __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1297 if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1298 __ cmp(Rtemp, k_RInfo);
1299 if (!op->should_profile()) {
1300 set_instanceof_result(_masm, res, eq);
1301 } else {
1302 __ b(profile_cast_failure, ne);
1303 }
1304 } else {
1305 __ cmp(klass_RInfo, k_RInfo);
1306 __ cond_cmp(Rtemp, k_RInfo, ne);
1307 if (!op->should_profile()) {
1308 set_instanceof_result(_masm, res, eq);
1309 }
1310 __ b(*success_target, eq);
1311 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1312 __ call(Runtime1::entry_for(StubId::c1_slow_subtype_check_id), relocInfo::runtime_call_type);
1313 if (!op->should_profile()) {
1314 move_regs(R0, res);
1315 } else {
1316 __ cbz(R0, *failure_target);
1317 }
1318 }
1319 } else {
1320 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1321 // check for immediate positive hit
1322 __ cmp(klass_RInfo, k_RInfo);
1323 if (!op->should_profile()) {
1324 __ ldr(res, Address(klass_RInfo, Rtemp), ne);
1325 __ cond_cmp(res, k_RInfo, ne);
1326 set_instanceof_result(_masm, res, eq);
1327 } else {
1328 __ ldr(Rtemp, Address(klass_RInfo, Rtemp), ne);
1329 __ cond_cmp(Rtemp, k_RInfo, ne);
1330 }
1331 __ b(*success_target, eq);
1332 // check for immediate negative hit
1333 if (op->should_profile()) {
1334 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1335 }
1336 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1337 if (!op->should_profile()) {
1338 __ mov(res, 0, ne);
1339 }
1340 __ b(*failure_target, ne);
1341 // slow case
1342 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1343 __ call(Runtime1::entry_for(StubId::c1_slow_subtype_check_id), relocInfo::runtime_call_type);
1344 if (!op->should_profile()) {
1345 move_regs(R0, res);
1346 }
1347 if (op->should_profile()) {
1348 __ cbz(R0, *failure_target);
1349 }
1350 }
1351
1352 if (op->should_profile()) {
1353 Label done_ok, done_failure;
1354 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1355 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1356 &profile_cast_success, &profile_cast_failure,
1357 &done_ok, &done_failure);
1358 __ bind(done_failure);
1359 __ mov(res, 0);
1360 __ b(done);
1361 __ bind(done_ok);
1362 __ mov(res, 1);
1363 }
1364 __ bind(done);
1365 break;
1366 }
1367 default:
1368 ShouldNotReachHere();
1369 }
1370 }
1371
1372
1373 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1374 // if (*addr == cmpval) {
1375 // *addr = newval;
1376 // dest = 1;
1377 // } else {
1378 // dest = 0;
1379 // }
1380 // FIXME: membar_release
1381 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
1382 Register addr = op->addr()->is_register() ?
1383 op->addr()->as_pointer_register() :
1384 op->addr()->as_address_ptr()->base()->as_pointer_register();
1385 assert(op->addr()->is_register() || op->addr()->as_address_ptr()->disp() == 0, "unexpected disp");
1386 assert(op->addr()->is_register() || op->addr()->as_address_ptr()->index() == LIR_Opr::illegalOpr(), "unexpected index");
1387 if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
1388 Register cmpval = op->cmp_value()->as_register();
1389 Register newval = op->new_value()->as_register();
1390 Register dest = op->result_opr()->as_register();
1391 assert_different_registers(dest, addr, cmpval, newval, Rtemp);
1392
1393 __ atomic_cas_bool(cmpval, newval, addr, 0, Rtemp); // Rtemp free by default at C1 LIR layer
1394 __ mov(dest, 1, eq);
1395 __ mov(dest, 0, ne);
1396 } else if (op->code() == lir_cas_long) {
1397 Register cmp_value_lo = op->cmp_value()->as_register_lo();
1398 Register cmp_value_hi = op->cmp_value()->as_register_hi();
1399 Register new_value_lo = op->new_value()->as_register_lo();
1400 Register new_value_hi = op->new_value()->as_register_hi();
1401 Register dest = op->result_opr()->as_register();
1402 Register tmp_lo = op->tmp1()->as_register_lo();
1403 Register tmp_hi = op->tmp1()->as_register_hi();
1404
1405 assert_different_registers(tmp_lo, tmp_hi, cmp_value_lo, cmp_value_hi, dest, new_value_lo, new_value_hi, addr);
1406 assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
1407 assert(new_value_hi->encoding() == new_value_lo->encoding() + 1, "non aligned register pair");
1408 assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
1409 assert((new_value_lo->encoding() & 0x1) == 0, "misaligned register pair");
1410 __ atomic_cas64(tmp_lo, tmp_hi, dest, cmp_value_lo, cmp_value_hi,
1411 new_value_lo, new_value_hi, addr, 0);
1412 } else {
1413 Unimplemented();
1414 }
1415 // FIXME: is full membar really needed instead of just membar_acquire?
1416 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
1417 }
1418
1419
1420 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1421 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1422 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on arm");
1423
1424 AsmCondition acond = al;
1425 AsmCondition ncond = nv;
1426 if (opr1 != opr2) {
1427 switch (condition) {
1428 case lir_cond_equal: acond = eq; ncond = ne; break;
1429 case lir_cond_notEqual: acond = ne; ncond = eq; break;
1430 case lir_cond_less: acond = lt; ncond = ge; break;
1431 case lir_cond_lessEqual: acond = le; ncond = gt; break;
1432 case lir_cond_greaterEqual: acond = ge; ncond = lt; break;
1433 case lir_cond_greater: acond = gt; ncond = le; break;
1434 case lir_cond_aboveEqual: acond = hs; ncond = lo; break;
1435 case lir_cond_belowEqual: acond = ls; ncond = hi; break;
1436 default: ShouldNotReachHere();
1437 }
1438 }
1439
1440 for (;;) { // two iterations only
1441 if (opr1 == result) {
1442 // do nothing
1443 } else if (opr1->is_single_cpu()) {
1444 __ mov(result->as_register(), opr1->as_register(), acond);
1445 } else if (opr1->is_double_cpu()) {
1446 __ long_move(result->as_register_lo(), result->as_register_hi(),
1447 opr1->as_register_lo(), opr1->as_register_hi(), acond);
1448 } else if (opr1->is_single_stack()) {
1449 __ ldr(result->as_register(), frame_map()->address_for_slot(opr1->single_stack_ix()), acond);
1450 } else if (opr1->is_double_stack()) {
1451 __ ldr(result->as_register_lo(),
1452 frame_map()->address_for_slot(opr1->double_stack_ix(), lo_word_offset_in_bytes), acond);
1453 __ ldr(result->as_register_hi(),
1454 frame_map()->address_for_slot(opr1->double_stack_ix(), hi_word_offset_in_bytes), acond);
1455 } else if (opr1->is_illegal()) {
1456 // do nothing: this part of the cmove has been optimized away in the peephole optimizer
1457 } else {
1458 assert(opr1->is_constant(), "must be");
1459 LIR_Const* c = opr1->as_constant_ptr();
1460
1461 switch (c->type()) {
1462 case T_INT:
1463 __ mov_slow(result->as_register(), c->as_jint(), acond);
1464 break;
1465 case T_LONG:
1466 __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1467 __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1468 break;
1469 case T_OBJECT:
1470 __ mov_oop(result->as_register(), c->as_jobject(), 0, acond);
1471 break;
1472 case T_FLOAT:
1473 #ifdef __SOFTFP__
1474 // not generated now.
1475 __ mov_slow(result->as_register(), c->as_jint(), acond);
1476 #else
1477 __ mov_float(result->as_float_reg(), c->as_jfloat(), acond);
1478 #endif // __SOFTFP__
1479 break;
1480 case T_DOUBLE:
1481 #ifdef __SOFTFP__
1482 // not generated now.
1483 __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1484 __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1485 #else
1486 __ mov_double(result->as_double_reg(), c->as_jdouble(), acond);
1487 #endif // __SOFTFP__
1488 break;
1489 case T_METADATA:
1490 __ mov_metadata(result->as_register(), c->as_metadata(), acond);
1491 break;
1492 default:
1493 ShouldNotReachHere();
1494 }
1495 }
1496
1497 // Negate the condition and repeat the algorithm with the second operand
1498 if (opr1 == opr2) { break; }
1499 opr1 = opr2;
1500 acond = ncond;
1501 }
1502 }
1503
1504 #ifdef ASSERT
1505 static int reg_size(LIR_Opr op) {
1506 switch (op->type()) {
1507 case T_FLOAT:
1508 case T_INT: return BytesPerInt;
1509 case T_LONG:
1510 case T_DOUBLE: return BytesPerLong;
1511 case T_OBJECT:
1512 case T_ARRAY:
1513 case T_METADATA: return BytesPerWord;
1514 case T_ADDRESS:
1515 case T_ILLEGAL: // fall through
1516 default: ShouldNotReachHere(); return -1;
1517 }
1518 }
1519 #endif
1520
1521 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1522 assert(info == nullptr, "unused on this code path");
1523 assert(dest->is_register(), "wrong items state");
1524
1525 if (right->is_address()) {
1526 // special case for adding shifted/extended register
1527 const Register res = dest->as_pointer_register();
1528 const Register lreg = left->as_pointer_register();
1529 const LIR_Address* addr = right->as_address_ptr();
1530
1531 assert(addr->base()->as_pointer_register() == lreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1532
1533 int scale = addr->scale();
1534 AsmShift shift = lsl;
1535
1536
1537 assert(reg_size(addr->base()) == reg_size(addr->index()), "should be");
1538 assert(reg_size(addr->base()) == reg_size(dest), "should be");
1539 assert(reg_size(dest) == wordSize, "should be");
1540
1541 AsmOperand operand(addr->index()->as_pointer_register(), shift, scale);
1542 switch (code) {
1543 case lir_add: __ add(res, lreg, operand); break;
1544 case lir_sub: __ sub(res, lreg, operand); break;
1545 default: ShouldNotReachHere();
1546 }
1547
1548 } else if (left->is_address()) {
1549 assert(code == lir_sub && right->is_single_cpu(), "special case used by strength_reduce_multiply()");
1550 const LIR_Address* addr = left->as_address_ptr();
1551 const Register res = dest->as_register();
1552 const Register rreg = right->as_register();
1553 assert(addr->base()->as_register() == rreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1554 __ rsb(res, rreg, AsmOperand(addr->index()->as_register(), lsl, addr->scale()));
1555
1556 } else if (dest->is_single_cpu()) {
1557 assert(left->is_single_cpu(), "unexpected left operand");
1558
1559 const Register res = dest->as_register();
1560 const Register lreg = left->as_register();
1561
1562 if (right->is_single_cpu()) {
1563 const Register rreg = right->as_register();
1564 switch (code) {
1565 case lir_add: __ add_32(res, lreg, rreg); break;
1566 case lir_sub: __ sub_32(res, lreg, rreg); break;
1567 case lir_mul: __ mul_32(res, lreg, rreg); break;
1568 default: ShouldNotReachHere();
1569 }
1570 } else {
1571 assert(right->is_constant(), "must be");
1572 const jint c = right->as_constant_ptr()->as_jint();
1573 if (!Assembler::is_arith_imm_in_range(c)) {
1574 BAILOUT("illegal arithmetic operand");
1575 }
1576 switch (code) {
1577 case lir_add: __ add_32(res, lreg, c); break;
1578 case lir_sub: __ sub_32(res, lreg, c); break;
1579 default: ShouldNotReachHere();
1580 }
1581 }
1582
1583 } else if (dest->is_double_cpu()) {
1584 Register res_lo = dest->as_register_lo();
1585 Register res_hi = dest->as_register_hi();
1586 Register lreg_lo = left->as_register_lo();
1587 Register lreg_hi = left->as_register_hi();
1588 if (right->is_double_cpu()) {
1589 Register rreg_lo = right->as_register_lo();
1590 Register rreg_hi = right->as_register_hi();
1591 if (res_lo == lreg_hi || res_lo == rreg_hi) {
1592 res_lo = Rtemp;
1593 }
1594 switch (code) {
1595 case lir_add:
1596 __ adds(res_lo, lreg_lo, rreg_lo);
1597 __ adc(res_hi, lreg_hi, rreg_hi);
1598 break;
1599 case lir_sub:
1600 __ subs(res_lo, lreg_lo, rreg_lo);
1601 __ sbc(res_hi, lreg_hi, rreg_hi);
1602 break;
1603 default:
1604 ShouldNotReachHere();
1605 }
1606 } else {
1607 assert(right->is_constant(), "must be");
1608 assert((right->as_constant_ptr()->as_jlong() >> 32) == 0, "out of range");
1609 const jint c = (jint) right->as_constant_ptr()->as_jlong();
1610 if (res_lo == lreg_hi) {
1611 res_lo = Rtemp;
1612 }
1613 switch (code) {
1614 case lir_add:
1615 __ adds(res_lo, lreg_lo, c);
1616 __ adc(res_hi, lreg_hi, 0);
1617 break;
1618 case lir_sub:
1619 __ subs(res_lo, lreg_lo, c);
1620 __ sbc(res_hi, lreg_hi, 0);
1621 break;
1622 default:
1623 ShouldNotReachHere();
1624 }
1625 }
1626 move_regs(res_lo, dest->as_register_lo());
1627
1628 } else if (dest->is_single_fpu()) {
1629 assert(left->is_single_fpu(), "must be");
1630 assert(right->is_single_fpu(), "must be");
1631 const FloatRegister res = dest->as_float_reg();
1632 const FloatRegister lreg = left->as_float_reg();
1633 const FloatRegister rreg = right->as_float_reg();
1634 switch (code) {
1635 case lir_add: __ add_float(res, lreg, rreg); break;
1636 case lir_sub: __ sub_float(res, lreg, rreg); break;
1637 case lir_mul: __ mul_float(res, lreg, rreg); break;
1638 case lir_div: __ div_float(res, lreg, rreg); break;
1639 default: ShouldNotReachHere();
1640 }
1641 } else if (dest->is_double_fpu()) {
1642 assert(left->is_double_fpu(), "must be");
1643 assert(right->is_double_fpu(), "must be");
1644 const FloatRegister res = dest->as_double_reg();
1645 const FloatRegister lreg = left->as_double_reg();
1646 const FloatRegister rreg = right->as_double_reg();
1647 switch (code) {
1648 case lir_add: __ add_double(res, lreg, rreg); break;
1649 case lir_sub: __ sub_double(res, lreg, rreg); break;
1650 case lir_mul: __ mul_double(res, lreg, rreg); break;
1651 case lir_div: __ div_double(res, lreg, rreg); break;
1652 default: ShouldNotReachHere();
1653 }
1654 } else {
1655 ShouldNotReachHere();
1656 }
1657 }
1658
1659
1660 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1661 switch (code) {
1662 case lir_abs:
1663 __ abs_double(dest->as_double_reg(), value->as_double_reg());
1664 break;
1665 case lir_sqrt:
1666 __ sqrt_double(dest->as_double_reg(), value->as_double_reg());
1667 break;
1668 default:
1669 ShouldNotReachHere();
1670 }
1671 }
1672
1673
1674 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1675 assert(dest->is_register(), "wrong items state");
1676 assert(left->is_register(), "wrong items state");
1677
1678 if (dest->is_single_cpu()) {
1679
1680 const Register res = dest->as_register();
1681 const Register lreg = left->as_register();
1682
1683 if (right->is_single_cpu()) {
1684 const Register rreg = right->as_register();
1685 switch (code) {
1686 case lir_logic_and: __ and_32(res, lreg, rreg); break;
1687 case lir_logic_or: __ orr_32(res, lreg, rreg); break;
1688 case lir_logic_xor: __ eor_32(res, lreg, rreg); break;
1689 default: ShouldNotReachHere();
1690 }
1691 } else {
1692 assert(right->is_constant(), "must be");
1693 const uint c = (uint)right->as_constant_ptr()->as_jint();
1694 if (!Assembler::is_arith_imm_in_range(c)) {
1695 BAILOUT("illegal arithmetic operand");
1696 }
1697 switch (code) {
1698 case lir_logic_and: __ and_32(res, lreg, c); break;
1699 case lir_logic_or: __ orr_32(res, lreg, c); break;
1700 case lir_logic_xor: __ eor_32(res, lreg, c); break;
1701 default: ShouldNotReachHere();
1702 }
1703 }
1704 } else {
1705 assert(dest->is_double_cpu(), "should be");
1706 Register res_lo = dest->as_register_lo();
1707
1708 assert (dest->type() == T_LONG, "unexpected result type");
1709 assert (left->type() == T_LONG, "unexpected left type");
1710 assert (right->type() == T_LONG, "unexpected right type");
1711
1712 const Register res_hi = dest->as_register_hi();
1713 const Register lreg_lo = left->as_register_lo();
1714 const Register lreg_hi = left->as_register_hi();
1715
1716 if (right->is_register()) {
1717 const Register rreg_lo = right->as_register_lo();
1718 const Register rreg_hi = right->as_register_hi();
1719 if (res_lo == lreg_hi || res_lo == rreg_hi) {
1720 res_lo = Rtemp; // Temp register helps to avoid overlap between result and input
1721 }
1722 switch (code) {
1723 case lir_logic_and:
1724 __ andr(res_lo, lreg_lo, rreg_lo);
1725 __ andr(res_hi, lreg_hi, rreg_hi);
1726 break;
1727 case lir_logic_or:
1728 __ orr(res_lo, lreg_lo, rreg_lo);
1729 __ orr(res_hi, lreg_hi, rreg_hi);
1730 break;
1731 case lir_logic_xor:
1732 __ eor(res_lo, lreg_lo, rreg_lo);
1733 __ eor(res_hi, lreg_hi, rreg_hi);
1734 break;
1735 default:
1736 ShouldNotReachHere();
1737 }
1738 move_regs(res_lo, dest->as_register_lo());
1739 } else {
1740 assert(right->is_constant(), "must be");
1741 const jint c_lo = (jint) right->as_constant_ptr()->as_jlong();
1742 const jint c_hi = (jint) (right->as_constant_ptr()->as_jlong() >> 32);
1743 // Case for logic_or from do_ClassIDIntrinsic()
1744 if (c_hi == 0 && AsmOperand::is_rotated_imm(c_lo)) {
1745 switch (code) {
1746 case lir_logic_and:
1747 __ andr(res_lo, lreg_lo, c_lo);
1748 __ mov(res_hi, 0);
1749 break;
1750 case lir_logic_or:
1751 __ orr(res_lo, lreg_lo, c_lo);
1752 break;
1753 case lir_logic_xor:
1754 __ eor(res_lo, lreg_lo, c_lo);
1755 break;
1756 default:
1757 ShouldNotReachHere();
1758 }
1759 } else if (code == lir_logic_and &&
1760 c_hi == -1 &&
1761 (AsmOperand::is_rotated_imm(c_lo) ||
1762 AsmOperand::is_rotated_imm(~c_lo))) {
1763 // Another case which handles logic_and from do_ClassIDIntrinsic()
1764 if (AsmOperand::is_rotated_imm(c_lo)) {
1765 __ andr(res_lo, lreg_lo, c_lo);
1766 } else {
1767 __ bic(res_lo, lreg_lo, ~c_lo);
1768 }
1769 if (res_hi != lreg_hi) {
1770 __ mov(res_hi, lreg_hi);
1771 }
1772 } else {
1773 BAILOUT("64 bit constant cannot be inlined");
1774 }
1775 }
1776 }
1777 }
1778
1779
1780
1781 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1782 if (opr1->is_single_cpu()) {
1783 if (opr2->is_constant()) {
1784 switch (opr2->as_constant_ptr()->type()) {
1785 case T_INT: {
1786 const jint c = opr2->as_constant_ptr()->as_jint();
1787 if (Assembler::is_arith_imm_in_range(c)) {
1788 __ cmp_32(opr1->as_register(), c);
1789 } else if (Assembler::is_arith_imm_in_range(-c)) {
1790 __ cmn_32(opr1->as_register(), -c);
1791 } else {
1792 // This can happen when compiling lookupswitch
1793 __ mov_slow(Rtemp, c);
1794 __ cmp_32(opr1->as_register(), Rtemp);
1795 }
1796 break;
1797 }
1798 case T_OBJECT:
1799 assert(opr2->as_constant_ptr()->as_jobject() == nullptr, "cannot handle otherwise");
1800 __ cmp(opr1->as_register(), 0);
1801 break;
1802 case T_METADATA:
1803 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "Only equality tests");
1804 assert(opr2->as_constant_ptr()->as_metadata() == nullptr, "cannot handle otherwise");
1805 __ cmp(opr1->as_register(), 0);
1806 break;
1807 default:
1808 ShouldNotReachHere();
1809 }
1810 } else if (opr2->is_single_cpu()) {
1811 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1812 assert(opr2->type() == T_OBJECT || opr2->type() == T_ARRAY, "incompatibe type");
1813 __ cmpoop(opr1->as_register(), opr2->as_register());
1814 } else if (opr1->type() == T_METADATA || opr1->type() == T_ADDRESS) {
1815 assert(opr2->type() == T_METADATA || opr2->type() == T_ADDRESS, "incompatibe type");
1816 __ cmp(opr1->as_register(), opr2->as_register());
1817 } else {
1818 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_METADATA && opr2->type() != T_ADDRESS, "incompatibe type");
1819 __ cmp_32(opr1->as_register(), opr2->as_register());
1820 }
1821 } else {
1822 ShouldNotReachHere();
1823 }
1824 } else if (opr1->is_double_cpu()) {
1825 Register xlo = opr1->as_register_lo();
1826 Register xhi = opr1->as_register_hi();
1827 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1828 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "cannot handle otherwise");
1829 __ orrs(Rtemp, xlo, xhi);
1830 } else if (opr2->is_register()) {
1831 Register ylo = opr2->as_register_lo();
1832 Register yhi = opr2->as_register_hi();
1833 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1834 __ teq(xhi, yhi);
1835 __ teq(xlo, ylo, eq);
1836 } else {
1837 __ subs(Rtemp, xlo, ylo);
1838 __ sbcs(Rtemp, xhi, yhi);
1839 }
1840 } else {
1841 ShouldNotReachHere();
1842 }
1843 } else if (opr1->is_single_fpu()) {
1844 if (opr2->is_constant()) {
1845 assert(opr2->as_jfloat() == 0.0f, "cannot handle otherwise");
1846 __ cmp_zero_float(opr1->as_float_reg());
1847 } else {
1848 __ cmp_float(opr1->as_float_reg(), opr2->as_float_reg());
1849 }
1850 } else if (opr1->is_double_fpu()) {
1851 if (opr2->is_constant()) {
1852 assert(opr2->as_jdouble() == 0.0, "cannot handle otherwise");
1853 __ cmp_zero_double(opr1->as_double_reg());
1854 } else {
1855 __ cmp_double(opr1->as_double_reg(), opr2->as_double_reg());
1856 }
1857 } else {
1858 ShouldNotReachHere();
1859 }
1860 }
1861
1862 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1863 const Register res = dst->as_register();
1864 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1865 comp_op(lir_cond_unknown, left, right, op);
1866 __ fmstat();
1867 if (code == lir_ucmp_fd2i) { // unordered is less
1868 __ mvn(res, 0, lt);
1869 __ mov(res, 1, ge);
1870 } else { // unordered is greater
1871 __ mov(res, 1, cs);
1872 __ mvn(res, 0, cc);
1873 }
1874 __ mov(res, 0, eq);
1875
1876 } else {
1877 assert(code == lir_cmp_l2i, "must be");
1878
1879 Label done;
1880 const Register xlo = left->as_register_lo();
1881 const Register xhi = left->as_register_hi();
1882 const Register ylo = right->as_register_lo();
1883 const Register yhi = right->as_register_hi();
1884 __ cmp(xhi, yhi);
1885 __ mov(res, 1, gt);
1886 __ mvn(res, 0, lt);
1887 __ b(done, ne);
1888 __ subs(res, xlo, ylo);
1889 __ mov(res, 1, hi);
1890 __ mvn(res, 0, lo);
1891 __ bind(done);
1892 }
1893 }
1894
1895
1896 void LIR_Assembler::align_call(LIR_Code code) {
1897 // Not needed
1898 }
1899
1900
1901 void LIR_Assembler::call(LIR_OpJavaCall *op, relocInfo::relocType rtype) {
1902 int ret_addr_offset = __ patchable_call(op->addr(), rtype);
1903 assert(ret_addr_offset == __ offset(), "embedded return address not allowed");
1904 add_call_info_here(op->info());
1905 }
1906
1907
1908 void LIR_Assembler::ic_call(LIR_OpJavaCall *op) {
1909 bool near_range = __ cache_fully_reachable();
1910 address oop_address = pc();
1911
1912 bool use_movw = VM_Version::supports_movw();
1913
1914 // Ricklass may contain something that is not a metadata pointer so
1915 // mov_metadata can't be used
1916 InlinedAddress value((address)Universe::non_oop_word());
1917 InlinedAddress addr(op->addr());
1918 if (use_movw) {
1919 __ movw(Ricklass, ((unsigned int)Universe::non_oop_word()) & 0xffff);
1920 __ movt(Ricklass, ((unsigned int)Universe::non_oop_word()) >> 16);
1921 } else {
1922 // No movw/movt, must be load a pc relative value but no
1923 // relocation so no metadata table to load from.
1924 // Use a b instruction rather than a bl, inline constant after the
1925 // branch, use a PC relative ldr to load the constant, arrange for
1926 // the call to return after the constant(s).
1927 __ ldr_literal(Ricklass, value);
1928 }
1929 __ relocate(virtual_call_Relocation::spec(oop_address));
1930 if (near_range && use_movw) {
1931 __ bl(op->addr());
1932 } else {
1933 Label call_return;
1934 __ adr(LR, call_return);
1935 if (near_range) {
1936 __ b(op->addr());
1937 } else {
1938 __ indirect_jump(addr, Rtemp);
1939 __ bind_literal(addr);
1940 }
1941 if (!use_movw) {
1942 __ bind_literal(value);
1943 }
1944 __ bind(call_return);
1945 }
1946 add_call_info(code_offset(), op->info());
1947 }
1948
1949 void LIR_Assembler::emit_static_call_stub() {
1950 address call_pc = __ pc();
1951 address stub = __ start_a_stub(call_stub_size());
1952 if (stub == nullptr) {
1953 BAILOUT("static call stub overflow");
1954 }
1955
1956 DEBUG_ONLY(int offset = code_offset();)
1957
1958 InlinedMetadata metadata_literal(nullptr);
1959 __ relocate(static_stub_Relocation::spec(call_pc));
1960 // If not a single instruction, NativeMovConstReg::next_instruction_address()
1961 // must jump over the whole following ldr_literal.
1962 // (See CompiledDirectCall::set_to_interpreted())
1963 #ifdef ASSERT
1964 address ldr_site = __ pc();
1965 #endif
1966 __ ldr_literal(Rmethod, metadata_literal);
1967 assert(nativeMovConstReg_at(ldr_site)->next_instruction_address() == __ pc(), "Fix ldr_literal or its parsing");
1968 bool near_range = __ cache_fully_reachable();
1969 InlinedAddress dest((address)-1);
1970 if (near_range) {
1971 address branch_site = __ pc();
1972 __ b(branch_site); // b to self maps to special NativeJump -1 destination
1973 } else {
1974 __ indirect_jump(dest, Rtemp);
1975 }
1976 __ bind_literal(metadata_literal); // includes spec_for_immediate reloc
1977 if (!near_range) {
1978 __ bind_literal(dest); // special NativeJump -1 destination
1979 }
1980
1981 assert(code_offset() - offset <= call_stub_size(), "overflow");
1982 __ end_a_stub();
1983 }
1984
1985 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1986 assert(exceptionOop->as_register() == Rexception_obj, "must match");
1987 assert(exceptionPC->as_register() == Rexception_pc, "must match");
1988 info->add_register_oop(exceptionOop);
1989
1990 StubId handle_id = compilation()->has_fpu_code() ?
1991 StubId::c1_handle_exception_id :
1992 StubId::c1_handle_exception_nofpu_id;
1993 Label return_address;
1994 __ adr(Rexception_pc, return_address);
1995 __ call(Runtime1::entry_for(handle_id), relocInfo::runtime_call_type);
1996 __ bind(return_address);
1997 add_call_info_here(info); // for exception handler
1998 }
1999
2000 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2001 assert(exceptionOop->as_register() == Rexception_obj, "must match");
2002 __ b(_unwind_handler_entry);
2003 }
2004
2005 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2006 AsmShift shift = lsl;
2007 switch (code) {
2008 case lir_shl: shift = lsl; break;
2009 case lir_shr: shift = asr; break;
2010 case lir_ushr: shift = lsr; break;
2011 default: ShouldNotReachHere();
2012 }
2013
2014 if (dest->is_single_cpu()) {
2015 __ andr(Rtemp, count->as_register(), 31);
2016 __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, Rtemp));
2017 } else if (dest->is_double_cpu()) {
2018 Register dest_lo = dest->as_register_lo();
2019 Register dest_hi = dest->as_register_hi();
2020 Register src_lo = left->as_register_lo();
2021 Register src_hi = left->as_register_hi();
2022 Register Rcount = count->as_register();
2023 // Resolve possible register conflicts
2024 if (shift == lsl && dest_hi == src_lo) {
2025 dest_hi = Rtemp;
2026 } else if (shift != lsl && dest_lo == src_hi) {
2027 dest_lo = Rtemp;
2028 } else if (dest_lo == src_lo && dest_hi == src_hi) {
2029 dest_lo = Rtemp;
2030 } else if (dest_lo == Rcount || dest_hi == Rcount) {
2031 Rcount = Rtemp;
2032 }
2033 __ andr(Rcount, count->as_register(), 63);
2034 __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, Rcount);
2035 move_regs(dest_lo, dest->as_register_lo());
2036 move_regs(dest_hi, dest->as_register_hi());
2037 } else {
2038 ShouldNotReachHere();
2039 }
2040 }
2041
2042
2043 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2044 AsmShift shift = lsl;
2045 switch (code) {
2046 case lir_shl: shift = lsl; break;
2047 case lir_shr: shift = asr; break;
2048 case lir_ushr: shift = lsr; break;
2049 default: ShouldNotReachHere();
2050 }
2051
2052 if (dest->is_single_cpu()) {
2053 count &= 31;
2054 if (count != 0) {
2055 __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, count));
2056 } else {
2057 move_regs(left->as_register(), dest->as_register());
2058 }
2059 } else if (dest->is_double_cpu()) {
2060 count &= 63;
2061 if (count != 0) {
2062 Register dest_lo = dest->as_register_lo();
2063 Register dest_hi = dest->as_register_hi();
2064 Register src_lo = left->as_register_lo();
2065 Register src_hi = left->as_register_hi();
2066 // Resolve possible register conflicts
2067 if (shift == lsl && dest_hi == src_lo) {
2068 dest_hi = Rtemp;
2069 } else if (shift != lsl && dest_lo == src_hi) {
2070 dest_lo = Rtemp;
2071 }
2072 __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, count);
2073 move_regs(dest_lo, dest->as_register_lo());
2074 move_regs(dest_hi, dest->as_register_hi());
2075 } else {
2076 __ long_move(dest->as_register_lo(), dest->as_register_hi(),
2077 left->as_register_lo(), left->as_register_hi());
2078 }
2079 } else {
2080 ShouldNotReachHere();
2081 }
2082 }
2083
2084
2085 // Saves 4 given registers in reserved argument area.
2086 void LIR_Assembler::save_in_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2087 verify_reserved_argument_area_size(4);
2088 __ stmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4));
2089 }
2090
2091 // Restores 4 given registers from reserved argument area.
2092 void LIR_Assembler::restore_from_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2093 __ ldmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4), no_writeback);
2094 }
2095
2096
2097 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2098 ciArrayKlass* default_type = op->expected_type();
2099 Register src = op->src()->as_register();
2100 Register src_pos = op->src_pos()->as_register();
2101 Register dst = op->dst()->as_register();
2102 Register dst_pos = op->dst_pos()->as_register();
2103 Register length = op->length()->as_register();
2104 Register tmp = op->tmp()->as_register();
2105 Register tmp2 = Rtemp;
2106
2107 assert(src == R0 && src_pos == R1 && dst == R2 && dst_pos == R3, "code assumption");
2108
2109 CodeStub* stub = op->stub();
2110
2111 int flags = op->flags();
2112 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2113 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2114
2115 // If we don't know anything or it's an object array, just go through the generic arraycopy
2116 if (default_type == nullptr) {
2117
2118 // save arguments, because they will be killed by a runtime call
2119 save_in_reserved_area(R0, R1, R2, R3);
2120
2121 // pass length argument on SP[0]
2122 __ str(length, Address(SP, -2*wordSize, pre_indexed)); // 2 words for a proper stack alignment
2123
2124 address copyfunc_addr = StubRoutines::generic_arraycopy();
2125 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2126 #ifndef PRODUCT
2127 if (PrintC1Statistics) {
2128 __ inc_counter((address)&Runtime1::_generic_arraycopystub_cnt, tmp, tmp2);
2129 }
2130 #endif // !PRODUCT
2131 // the stub is in the code cache so close enough
2132 __ call(copyfunc_addr, relocInfo::runtime_call_type);
2133
2134 __ add(SP, SP, 2*wordSize);
2135
2136 __ cbz_32(R0, *stub->continuation());
2137
2138 __ mvn_32(tmp, R0);
2139 restore_from_reserved_area(R0, R1, R2, R3); // load saved arguments in slow case only
2140 __ sub_32(length, length, tmp);
2141 __ add_32(src_pos, src_pos, tmp);
2142 __ add_32(dst_pos, dst_pos, tmp);
2143
2144 __ b(*stub->entry());
2145
2146 __ bind(*stub->continuation());
2147 return;
2148 }
2149
2150 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(),
2151 "must be true at this point");
2152 int elem_size = type2aelembytes(basic_type);
2153 int shift = exact_log2(elem_size);
2154
2155 // Check for null
2156 if (flags & LIR_OpArrayCopy::src_null_check) {
2157 if (flags & LIR_OpArrayCopy::dst_null_check) {
2158 __ cmp(src, 0);
2159 __ cond_cmp(dst, 0, ne); // make one instruction shorter if both checks are needed
2160 __ b(*stub->entry(), eq);
2161 } else {
2162 __ cbz(src, *stub->entry());
2163 }
2164 } else if (flags & LIR_OpArrayCopy::dst_null_check) {
2165 __ cbz(dst, *stub->entry());
2166 }
2167
2168 // If the compiler was not able to prove that exact type of the source or the destination
2169 // of the arraycopy is an array type, check at runtime if the source or the destination is
2170 // an instance type.
2171 if (flags & LIR_OpArrayCopy::type_check) {
2172 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2173 __ load_klass(tmp, dst);
2174 __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2175 __ mov_slow(tmp, Klass::_lh_neutral_value);
2176 __ cmp_32(tmp2, tmp);
2177 __ b(*stub->entry(), ge);
2178 }
2179
2180 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2181 __ load_klass(tmp, src);
2182 __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2183 __ mov_slow(tmp, Klass::_lh_neutral_value);
2184 __ cmp_32(tmp2, tmp);
2185 __ b(*stub->entry(), ge);
2186 }
2187 }
2188
2189 // Check if negative
2190 const int all_positive_checks = LIR_OpArrayCopy::src_pos_positive_check |
2191 LIR_OpArrayCopy::dst_pos_positive_check |
2192 LIR_OpArrayCopy::length_positive_check;
2193 switch (flags & all_positive_checks) {
2194 case LIR_OpArrayCopy::src_pos_positive_check:
2195 __ branch_if_negative_32(src_pos, *stub->entry());
2196 break;
2197 case LIR_OpArrayCopy::dst_pos_positive_check:
2198 __ branch_if_negative_32(dst_pos, *stub->entry());
2199 break;
2200 case LIR_OpArrayCopy::length_positive_check:
2201 __ branch_if_negative_32(length, *stub->entry());
2202 break;
2203 case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::dst_pos_positive_check:
2204 __ branch_if_any_negative_32(src_pos, dst_pos, tmp, *stub->entry());
2205 break;
2206 case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2207 __ branch_if_any_negative_32(src_pos, length, tmp, *stub->entry());
2208 break;
2209 case LIR_OpArrayCopy::dst_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2210 __ branch_if_any_negative_32(dst_pos, length, tmp, *stub->entry());
2211 break;
2212 case all_positive_checks:
2213 __ branch_if_any_negative_32(src_pos, dst_pos, length, tmp, *stub->entry());
2214 break;
2215 default:
2216 assert((flags & all_positive_checks) == 0, "the last option");
2217 }
2218
2219 // Range checks
2220 if (flags & LIR_OpArrayCopy::src_range_check) {
2221 __ ldr_s32(tmp2, Address(src, arrayOopDesc::length_offset_in_bytes()));
2222 __ add_32(tmp, src_pos, length);
2223 __ cmp_32(tmp, tmp2);
2224 __ b(*stub->entry(), hi);
2225 }
2226 if (flags & LIR_OpArrayCopy::dst_range_check) {
2227 __ ldr_s32(tmp2, Address(dst, arrayOopDesc::length_offset_in_bytes()));
2228 __ add_32(tmp, dst_pos, length);
2229 __ cmp_32(tmp, tmp2);
2230 __ b(*stub->entry(), hi);
2231 }
2232
2233 // Check if src and dst are of the same type
2234 if (flags & LIR_OpArrayCopy::type_check) {
2235 // We don't know the array types are compatible
2236 if (basic_type != T_OBJECT) {
2237 // Simple test for basic type arrays
2238 __ load_klass(tmp, src);
2239 __ load_klass(tmp2, dst);
2240 __ cmp(tmp, tmp2);
2241 __ b(*stub->entry(), ne);
2242 } else {
2243 // For object arrays, if src is a sub class of dst then we can
2244 // safely do the copy.
2245 Label cont, slow;
2246
2247 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2248
2249 __ load_klass(tmp, src);
2250 __ load_klass(tmp2, dst);
2251
2252 // We are at a call so all live registers are saved before we
2253 // get here
2254 assert_different_registers(tmp, tmp2, R6, altFP_7_11);
2255
2256 __ check_klass_subtype_fast_path(tmp, tmp2, R6, altFP_7_11, &cont, copyfunc_addr == nullptr ? stub->entry() : &slow, nullptr);
2257
2258 __ mov(R6, R0);
2259 __ mov(altFP_7_11, R1);
2260 __ mov(R0, tmp);
2261 __ mov(R1, tmp2);
2262 __ call(Runtime1::entry_for(StubId::c1_slow_subtype_check_id), relocInfo::runtime_call_type); // does not blow any registers except R0, LR and Rtemp
2263 __ cmp_32(R0, 0);
2264 __ mov(R0, R6);
2265 __ mov(R1, altFP_7_11);
2266
2267 if (copyfunc_addr != nullptr) { // use stub if available
2268 // src is not a sub class of dst so we have to do a
2269 // per-element check.
2270
2271 __ b(cont, ne);
2272
2273 __ bind(slow);
2274
2275 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2276 if ((flags & mask) != mask) {
2277 // Check that at least both of them object arrays.
2278 assert(flags & mask, "one of the two should be known to be an object array");
2279
2280 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2281 __ load_klass(tmp, src);
2282 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2283 __ load_klass(tmp, dst);
2284 }
2285 int lh_offset = in_bytes(Klass::layout_helper_offset());
2286
2287 __ ldr_u32(tmp2, Address(tmp, lh_offset));
2288
2289 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2290 __ mov_slow(tmp, objArray_lh);
2291 __ cmp_32(tmp, tmp2);
2292 __ b(*stub->entry(), ne);
2293 }
2294
2295 save_in_reserved_area(R0, R1, R2, R3);
2296
2297 Register src_ptr = R0;
2298 Register dst_ptr = R1;
2299 Register len = R2;
2300 Register chk_off = R3;
2301 Register super_k = tmp;
2302
2303 __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2304 __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2305
2306 __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2307 __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2308 __ load_klass(tmp, dst);
2309
2310 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2311 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2312
2313 __ ldr(super_k, Address(tmp, ek_offset));
2314
2315 __ mov(len, length);
2316 __ ldr_u32(chk_off, Address(super_k, sco_offset));
2317 __ push(super_k);
2318
2319 __ call(copyfunc_addr, relocInfo::runtime_call_type);
2320
2321 #ifndef PRODUCT
2322 if (PrintC1Statistics) {
2323 Label failed;
2324 __ cbnz_32(R0, failed);
2325 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, tmp, tmp2);
2326 __ bind(failed);
2327 }
2328 #endif // PRODUCT
2329
2330 __ add(SP, SP, wordSize); // Drop super_k argument
2331
2332 __ cbz_32(R0, *stub->continuation());
2333 __ mvn_32(tmp, R0);
2334
2335 // load saved arguments in slow case only
2336 restore_from_reserved_area(R0, R1, R2, R3);
2337
2338 __ sub_32(length, length, tmp);
2339 __ add_32(src_pos, src_pos, tmp);
2340 __ add_32(dst_pos, dst_pos, tmp);
2341
2342 #ifndef PRODUCT
2343 if (PrintC1Statistics) {
2344 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, tmp, tmp2);
2345 }
2346 #endif
2347
2348 __ b(*stub->entry());
2349
2350 __ bind(cont);
2351 } else {
2352 __ b(*stub->entry(), eq);
2353 __ bind(cont);
2354 }
2355 }
2356 }
2357
2358 #ifndef PRODUCT
2359 if (PrintC1Statistics) {
2360 address counter = Runtime1::arraycopy_count_address(basic_type);
2361 __ inc_counter(counter, tmp, tmp2);
2362 }
2363 #endif // !PRODUCT
2364
2365 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2366 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2367 const char *name;
2368 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2369
2370 Register src_ptr = R0;
2371 Register dst_ptr = R1;
2372 Register len = R2;
2373
2374 __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2375 __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2376
2377 __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2378 __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2379
2380 __ mov(len, length);
2381
2382 __ call(entry, relocInfo::runtime_call_type);
2383
2384 __ bind(*stub->continuation());
2385 }
2386
2387 #ifdef ASSERT
2388 // emit run-time assertion
2389 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2390 assert(op->code() == lir_assert, "must be");
2391
2392 if (op->in_opr1()->is_valid()) {
2393 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2394 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2395 } else {
2396 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2397 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2398 }
2399
2400 Label ok;
2401 if (op->condition() != lir_cond_always) {
2402 AsmCondition acond = al;
2403 switch (op->condition()) {
2404 case lir_cond_equal: acond = eq; break;
2405 case lir_cond_notEqual: acond = ne; break;
2406 case lir_cond_less: acond = lt; break;
2407 case lir_cond_lessEqual: acond = le; break;
2408 case lir_cond_greaterEqual: acond = ge; break;
2409 case lir_cond_greater: acond = gt; break;
2410 case lir_cond_aboveEqual: acond = hs; break;
2411 case lir_cond_belowEqual: acond = ls; break;
2412 default: ShouldNotReachHere();
2413 }
2414 __ b(ok, acond);
2415 }
2416 if (op->halt()) {
2417 const char* str = __ code_string(op->msg());
2418 __ stop(str);
2419 } else {
2420 breakpoint();
2421 }
2422 __ bind(ok);
2423 }
2424 #endif // ASSERT
2425
2426 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2427 fatal("CRC32 intrinsic is not implemented on this platform");
2428 }
2429
2430 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2431 Register obj = op->obj_opr()->as_pointer_register();
2432 Register hdr = op->hdr_opr()->as_pointer_register();
2433 Register lock = op->lock_opr()->as_pointer_register();
2434
2435 if (op->code() == lir_lock) {
2436 int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry());
2437 if (op->info() != nullptr) {
2438 add_debug_info_for_null_check(null_check_offset, op->info());
2439 }
2440 } else if (op->code() == lir_unlock) {
2441 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2442 } else {
2443 ShouldNotReachHere();
2444 }
2445 __ bind(*op->stub()->continuation());
2446 }
2447
2448 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2449 Register obj = op->obj()->as_pointer_register();
2450 Register result = op->result_opr()->as_pointer_register();
2451
2452 CodeEmitInfo* info = op->info();
2453 if (info != nullptr) {
2454 add_debug_info_for_null_check_here(info);
2455 }
2456 __ ldr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
2457 }
2458
2459 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2460 ciMethod* method = op->profiled_method();
2461 int bci = op->profiled_bci();
2462 ciMethod* callee = op->profiled_callee();
2463
2464 // Update counter for all call types
2465 ciMethodData* md = method->method_data_or_null();
2466 assert(md != nullptr, "Sanity");
2467 ciProfileData* data = md->bci_to_data(bci);
2468 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2469 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2470 Register mdo = op->mdo()->as_register();
2471 assert(op->tmp1()->is_register(), "tmp1 must be allocated");
2472 Register tmp1 = op->tmp1()->as_pointer_register();
2473 assert_different_registers(mdo, tmp1);
2474 __ mov_metadata(mdo, md->constant_encoding());
2475 int mdo_offset_bias = 0;
2476 int max_offset = 4096;
2477 if (md->byte_offset_of_slot(data, CounterData::count_offset()) + data->size_in_bytes() >= max_offset) {
2478 // The offset is large so bias the mdo by the base of the slot so
2479 // that the ldr can use an immediate offset to reference the slots of the data
2480 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2481 __ mov_slow(tmp1, mdo_offset_bias);
2482 __ add(mdo, mdo, tmp1);
2483 }
2484
2485 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2486 // Perform additional virtual call profiling for invokevirtual and
2487 // invokeinterface bytecodes
2488 if (op->should_profile_receiver_type()) {
2489 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2490 Register recv = op->recv()->as_register();
2491 assert_different_registers(mdo, tmp1, recv);
2492 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2493 ciKlass* known_klass = op->known_holder();
2494 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2495 // We know the type that will be seen at this call site; we can
2496 // statically update the MethodData* rather than needing to do
2497 // dynamic tests on the receiver type
2498
2499 // NOTE: we should probably put a lock around this search to
2500 // avoid collisions by concurrent compilations
2501 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2502 uint i;
2503 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2504 ciKlass* receiver = vc_data->receiver(i);
2505 if (known_klass->equals(receiver)) {
2506 Address data_addr(mdo, md->byte_offset_of_slot(data,
2507 VirtualCallData::receiver_count_offset(i)) -
2508 mdo_offset_bias);
2509 __ ldr(tmp1, data_addr);
2510 __ add(tmp1, tmp1, DataLayout::counter_increment);
2511 __ str(tmp1, data_addr);
2512 return;
2513 }
2514 }
2515
2516 // Receiver type not found in profile data; select an empty slot
2517
2518 // Note that this is less efficient than it should be because it
2519 // always does a write to the receiver part of the
2520 // VirtualCallData rather than just the first time
2521 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2522 ciKlass* receiver = vc_data->receiver(i);
2523 if (receiver == nullptr) {
2524 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2525 mdo_offset_bias);
2526 __ mov_metadata(tmp1, known_klass->constant_encoding());
2527 __ str(tmp1, recv_addr);
2528 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2529 mdo_offset_bias);
2530 __ ldr(tmp1, data_addr);
2531 __ add(tmp1, tmp1, DataLayout::counter_increment);
2532 __ str(tmp1, data_addr);
2533 return;
2534 }
2535 }
2536 } else {
2537 __ load_klass(recv, recv);
2538 Label update_done;
2539 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2540 // Receiver did not match any saved receiver and there is no empty row for it.
2541 // Increment total counter to indicate polymorphic case.
2542 __ ldr(tmp1, counter_addr);
2543 __ add(tmp1, tmp1, DataLayout::counter_increment);
2544 __ str(tmp1, counter_addr);
2545
2546 __ bind(update_done);
2547 }
2548 } else {
2549 // Static call
2550 __ ldr(tmp1, counter_addr);
2551 __ add(tmp1, tmp1, DataLayout::counter_increment);
2552 __ str(tmp1, counter_addr);
2553 }
2554 }
2555
2556 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2557 fatal("Type profiling not implemented on this platform");
2558 }
2559
2560 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2561 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2562 __ add_slow(dst->as_pointer_register(), mon_addr.base(), mon_addr.disp());
2563 }
2564
2565
2566 void LIR_Assembler::align_backward_branch_target() {
2567 // Some ARM processors do better with 8-byte branch target alignment
2568 __ align(8);
2569 }
2570
2571
2572 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2573 // tmp must be unused
2574 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2575
2576 if (left->is_single_cpu()) {
2577 assert (dest->type() == T_INT, "unexpected result type");
2578 assert (left->type() == T_INT, "unexpected left type");
2579 __ neg_32(dest->as_register(), left->as_register());
2580 } else if (left->is_double_cpu()) {
2581 Register dest_lo = dest->as_register_lo();
2582 Register dest_hi = dest->as_register_hi();
2583 Register src_lo = left->as_register_lo();
2584 Register src_hi = left->as_register_hi();
2585 if (dest_lo == src_hi) {
2586 dest_lo = Rtemp;
2587 }
2588 __ rsbs(dest_lo, src_lo, 0);
2589 __ rsc(dest_hi, src_hi, 0);
2590 move_regs(dest_lo, dest->as_register_lo());
2591 } else if (left->is_single_fpu()) {
2592 __ neg_float(dest->as_float_reg(), left->as_float_reg());
2593 } else if (left->is_double_fpu()) {
2594 __ neg_double(dest->as_double_reg(), left->as_double_reg());
2595 } else {
2596 ShouldNotReachHere();
2597 }
2598 }
2599
2600
2601 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2602 assert(patch_code == lir_patch_none, "Patch code not supported");
2603 LIR_Address* addr = addr_opr->as_address_ptr();
2604 if (addr->index()->is_illegal()) {
2605 jint c = addr->disp();
2606 if (!Assembler::is_arith_imm_in_range(c)) {
2607 BAILOUT("illegal arithmetic operand");
2608 }
2609 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), c);
2610 } else {
2611 assert(addr->disp() == 0, "cannot handle otherwise");
2612 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(),
2613 AsmOperand(addr->index()->as_pointer_register(), lsl, addr->scale()));
2614 }
2615 }
2616
2617
2618 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2619 assert(!tmp->is_valid(), "don't need temporary");
2620 __ call(dest);
2621 if (info != nullptr) {
2622 add_call_info_here(info);
2623 }
2624 }
2625
2626
2627 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2628 assert((src->is_double_cpu() && dest->is_address()) ||
2629 (src->is_address() && dest->is_double_cpu()),
2630 "Simple move_op is called for all other cases");
2631
2632 int null_check_offset;
2633 if (dest->is_address()) {
2634 // Store
2635 const LIR_Address* addr = dest->as_address_ptr();
2636 const Register src_lo = src->as_register_lo();
2637 const Register src_hi = src->as_register_hi();
2638 assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2639
2640 if (src_lo < src_hi) {
2641 null_check_offset = __ offset();
2642 __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(src_hi));
2643 } else {
2644 assert(src_lo < Rtemp, "Rtemp is higher than any allocatable register");
2645 __ mov(Rtemp, src_hi);
2646 null_check_offset = __ offset();
2647 __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(Rtemp));
2648 }
2649 } else {
2650 // Load
2651 const LIR_Address* addr = src->as_address_ptr();
2652 const Register dest_lo = dest->as_register_lo();
2653 const Register dest_hi = dest->as_register_hi();
2654 assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2655
2656 null_check_offset = __ offset();
2657 if (dest_lo < dest_hi) {
2658 __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(dest_hi));
2659 } else {
2660 assert(dest_lo < Rtemp, "Rtemp is higher than any allocatable register");
2661 __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(Rtemp));
2662 __ mov(dest_hi, Rtemp);
2663 }
2664 }
2665
2666 if (info != nullptr) {
2667 add_debug_info_for_null_check(null_check_offset, info);
2668 }
2669 }
2670
2671
2672 void LIR_Assembler::membar() {
2673 __ membar(MacroAssembler::StoreLoad, Rtemp);
2674 }
2675
2676 void LIR_Assembler::membar_acquire() {
2677 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::LoadLoad | MacroAssembler::LoadStore), Rtemp);
2678 }
2679
2680 void LIR_Assembler::membar_release() {
2681 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2682 }
2683
2684 void LIR_Assembler::membar_loadload() {
2685 __ membar(MacroAssembler::LoadLoad, Rtemp);
2686 }
2687
2688 void LIR_Assembler::membar_storestore() {
2689 __ membar(MacroAssembler::StoreStore, Rtemp);
2690 }
2691
2692 void LIR_Assembler::membar_loadstore() {
2693 __ membar(MacroAssembler::LoadStore, Rtemp);
2694 }
2695
2696 void LIR_Assembler::membar_storeload() {
2697 __ membar(MacroAssembler::StoreLoad, Rtemp);
2698 }
2699
2700 void LIR_Assembler::on_spin_wait() {
2701 Unimplemented();
2702 }
2703
2704 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2705 // Not used on ARM
2706 Unimplemented();
2707 }
2708
2709 void LIR_Assembler::peephole(LIR_List* lir) {
2710 LIR_OpList* inst = lir->instructions_list();
2711 const int inst_length = inst->length();
2712 for (int i = 0; i < inst_length; i++) {
2713 LIR_Op* op = inst->at(i);
2714 switch (op->code()) {
2715 case lir_cmp: {
2716 // Replace:
2717 // cmp rX, y
2718 // cmove [EQ] y, z, rX
2719 // with
2720 // cmp rX, y
2721 // cmove [EQ] illegalOpr, z, rX
2722 //
2723 // or
2724 // cmp rX, y
2725 // cmove [NE] z, y, rX
2726 // with
2727 // cmp rX, y
2728 // cmove [NE] z, illegalOpr, rX
2729 //
2730 // moves from illegalOpr should be removed when converting LIR to native assembly
2731
2732 LIR_Op2* cmp = op->as_Op2();
2733 assert(cmp != nullptr, "cmp LIR instruction is not an op2");
2734
2735 if (i + 1 < inst_length) {
2736 LIR_Op2* cmove = inst->at(i + 1)->as_Op2();
2737 if (cmove != nullptr && cmove->code() == lir_cmove) {
2738 LIR_Opr cmove_res = cmove->result_opr();
2739 bool res_is_op1 = cmove_res == cmp->in_opr1();
2740 bool res_is_op2 = cmove_res == cmp->in_opr2();
2741 LIR_Opr cmp_res, cmp_arg;
2742 if (res_is_op1) {
2743 cmp_res = cmp->in_opr1();
2744 cmp_arg = cmp->in_opr2();
2745 } else if (res_is_op2) {
2746 cmp_res = cmp->in_opr2();
2747 cmp_arg = cmp->in_opr1();
2748 } else {
2749 cmp_res = LIR_OprFact::illegalOpr;
2750 cmp_arg = LIR_OprFact::illegalOpr;
2751 }
2752
2753 if (cmp_res != LIR_OprFact::illegalOpr) {
2754 LIR_Condition cond = cmove->condition();
2755 if (cond == lir_cond_equal && cmove->in_opr1() == cmp_arg) {
2756 cmove->set_in_opr1(LIR_OprFact::illegalOpr);
2757 } else if (cond == lir_cond_notEqual && cmove->in_opr2() == cmp_arg) {
2758 cmove->set_in_opr2(LIR_OprFact::illegalOpr);
2759 }
2760 }
2761 }
2762 }
2763 break;
2764 }
2765
2766 default:
2767 break;
2768 }
2769 }
2770 }
2771
2772 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2773 assert(src->is_address(), "sanity");
2774 Address addr = as_Address(src->as_address_ptr());
2775
2776 if (code == lir_xchg) {
2777 } else {
2778 assert (!data->is_oop(), "xadd for oops");
2779 }
2780
2781 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2782
2783 Label retry;
2784 __ bind(retry);
2785
2786 if (data->type() == T_INT || data->is_oop()) {
2787 Register dst = dest->as_register();
2788 Register new_val = noreg;
2789 __ ldrex(dst, addr);
2790 if (code == lir_xadd) {
2791 Register tmp_reg = tmp->as_register();
2792 if (data->is_constant()) {
2793 assert_different_registers(dst, tmp_reg);
2794 __ add_32(tmp_reg, dst, data->as_constant_ptr()->as_jint());
2795 } else {
2796 assert_different_registers(dst, tmp_reg, data->as_register());
2797 __ add_32(tmp_reg, dst, data->as_register());
2798 }
2799 new_val = tmp_reg;
2800 } else {
2801 if (UseCompressedOops && data->is_oop()) {
2802 new_val = tmp->as_pointer_register();
2803 } else {
2804 new_val = data->as_register();
2805 }
2806 assert_different_registers(dst, new_val);
2807 }
2808 __ strex(Rtemp, new_val, addr);
2809
2810 } else if (data->type() == T_LONG) {
2811 Register dst_lo = dest->as_register_lo();
2812 Register new_val_lo = noreg;
2813 Register dst_hi = dest->as_register_hi();
2814
2815 assert(dst_hi->encoding() == dst_lo->encoding() + 1, "non aligned register pair");
2816 assert((dst_lo->encoding() & 0x1) == 0, "misaligned register pair");
2817
2818 __ bind(retry);
2819 __ ldrexd(dst_lo, addr);
2820 if (code == lir_xadd) {
2821 Register tmp_lo = tmp->as_register_lo();
2822 Register tmp_hi = tmp->as_register_hi();
2823
2824 assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
2825 assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
2826
2827 if (data->is_constant()) {
2828 jlong c = data->as_constant_ptr()->as_jlong();
2829 assert((jlong)((jint)c) == c, "overflow");
2830 assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi);
2831 __ adds(tmp_lo, dst_lo, (jint)c);
2832 __ adc(tmp_hi, dst_hi, 0);
2833 } else {
2834 Register new_val_lo = data->as_register_lo();
2835 Register new_val_hi = data->as_register_hi();
2836 __ adds(tmp_lo, dst_lo, new_val_lo);
2837 __ adc(tmp_hi, dst_hi, new_val_hi);
2838 assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi, new_val_lo, new_val_hi);
2839 }
2840 new_val_lo = tmp_lo;
2841 } else {
2842 new_val_lo = data->as_register_lo();
2843 Register new_val_hi = data->as_register_hi();
2844
2845 assert_different_registers(dst_lo, dst_hi, new_val_lo, new_val_hi);
2846 assert(new_val_hi->encoding() == new_val_lo->encoding() + 1, "non aligned register pair");
2847 assert((new_val_lo->encoding() & 0x1) == 0, "misaligned register pair");
2848 }
2849 __ strexd(Rtemp, new_val_lo, addr);
2850 } else {
2851 ShouldNotReachHere();
2852 }
2853
2854 __ cbnz_32(Rtemp, retry);
2855 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
2856
2857 }
2858
2859 #undef __