1 /*
2 * Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "memory/universe.hpp"
36 #include "nativeInst_arm.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/frame.inline.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/stubRoutines.hpp"
41 #include "utilities/powerOfTwo.hpp"
42 #include "vmreg_arm.inline.hpp"
43
44 #define __ _masm->
45
46 // Note: Rtemp usage is this file should not impact C2 and should be
47 // correct as long as it is not implicitly used in lower layers (the
48 // arm [macro]assembler) and used with care in the other C1 specific
49 // files.
50
51 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
52 ShouldNotCallThis(); // Not used on ARM
53 return false;
54 }
55
56
57 LIR_Opr LIR_Assembler::receiverOpr() {
58 // The first register in Java calling conventions
59 return FrameMap::R0_oop_opr;
60 }
61
62 LIR_Opr LIR_Assembler::osrBufferPointer() {
63 return FrameMap::as_pointer_opr(R0);
64 }
65
66 #ifndef PRODUCT
67 void LIR_Assembler::verify_reserved_argument_area_size(int args_count) {
68 assert(args_count * wordSize <= frame_map()->reserved_argument_area_size(), "not enough space for arguments");
69 }
70 #endif // !PRODUCT
71
72 void LIR_Assembler::store_parameter(jint c, int offset_from_sp_in_words) {
73 assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
74 int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
75 assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
76 __ mov_slow(Rtemp, c);
77 __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
78 }
79
80 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_sp_in_words) {
81 assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
82 int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
83 assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
84 __ mov_metadata(Rtemp, m);
85 __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
86 }
87
88 //--------------fpu register translations-----------------------
89
90
91 void LIR_Assembler::breakpoint() {
92 __ breakpoint();
93 }
94
95 void LIR_Assembler::push(LIR_Opr opr) {
96 Unimplemented();
97 }
98
99 void LIR_Assembler::pop(LIR_Opr opr) {
100 Unimplemented();
101 }
102
103 //-------------------------------------------
104 Address LIR_Assembler::as_Address(LIR_Address* addr) {
105 Register base = addr->base()->as_pointer_register();
106
107
108 if (addr->index()->is_illegal() || addr->index()->is_constant()) {
109 int offset = addr->disp();
110 if (addr->index()->is_constant()) {
111 offset += addr->index()->as_constant_ptr()->as_jint() << addr->scale();
112 }
113
114 if ((offset <= -4096) || (offset >= 4096)) {
115 BAILOUT_("offset not in range", Address(base));
116 }
117
118 return Address(base, offset);
119
120 } else {
121 assert(addr->disp() == 0, "can't have both");
122 int scale = addr->scale();
123
124 assert(addr->index()->is_single_cpu(), "should be");
125 return scale >= 0 ? Address(base, addr->index()->as_register(), lsl, scale) :
126 Address(base, addr->index()->as_register(), lsr, -scale);
127 }
128 }
129
130 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
131 Address base = as_Address(addr);
132 assert(base.index() == noreg, "must be");
133 if (base.disp() + BytesPerWord >= 4096) { BAILOUT_("offset not in range", Address(base.base(),0)); }
134 return Address(base.base(), base.disp() + BytesPerWord);
135 }
136
137 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
138 return as_Address(addr);
139 }
140
141
142 void LIR_Assembler::osr_entry() {
143 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
144 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
145 ValueStack* entry_state = osr_entry->end()->state();
146 int number_of_locks = entry_state->locks_size();
147
148 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
149 Register OSR_buf = osrBufferPointer()->as_pointer_register();
150
151 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
152 int monitor_offset = (method()->max_locals() + 2 * (number_of_locks - 1)) * BytesPerWord;
153 for (int i = 0; i < number_of_locks; i++) {
154 int slot_offset = monitor_offset - (i * 2 * BytesPerWord);
155 __ ldr(R1, Address(OSR_buf, slot_offset + 0*BytesPerWord));
156 __ ldr(R2, Address(OSR_buf, slot_offset + 1*BytesPerWord));
157 __ str(R1, frame_map()->address_for_monitor_lock(i));
158 __ str(R2, frame_map()->address_for_monitor_object(i));
159 }
160 }
161
162
163 int LIR_Assembler::check_icache() {
164 Register receiver = LIR_Assembler::receiverOpr()->as_register();
165 int offset = __ offset();
166 __ inline_cache_check(receiver, Ricklass);
167 return offset;
168 }
169
170 void LIR_Assembler::clinit_barrier(ciMethod* method) {
171 ShouldNotReachHere(); // not implemented
172 }
173
174 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
175 jobject o = (jobject)Universe::non_oop_word();
176 int index = __ oop_recorder()->allocate_oop_index(o);
177
178 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), index);
179
180 __ patchable_mov_oop(reg, o, index);
181 patching_epilog(patch, lir_patch_normal, reg, info);
182 }
183
184
185 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
186 Metadata* o = (Metadata*)Universe::non_oop_word();
187 int index = __ oop_recorder()->allocate_metadata_index(o);
188 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
189
190 __ patchable_mov_metadata(reg, o, index);
191 patching_epilog(patch, lir_patch_normal, reg, info);
192 }
193
194
195 int LIR_Assembler::initial_frame_size_in_bytes() const {
196 // Subtracts two words to account for return address and link
197 return frame_map()->framesize()*VMRegImpl::stack_slot_size - 2*wordSize;
198 }
199
200
201 int LIR_Assembler::emit_exception_handler() {
202 // TODO: ARM
203 __ nop(); // See comments in other ports
204
205 address handler_base = __ start_a_stub(exception_handler_size());
206 if (handler_base == NULL) {
207 bailout("exception handler overflow");
208 return -1;
209 }
210
211 int offset = code_offset();
212
213 // check that there is really an exception
214 __ verify_not_null_oop(Rexception_obj);
215
216 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
217 __ should_not_reach_here();
218
219 assert(code_offset() - offset <= exception_handler_size(), "overflow");
220 __ end_a_stub();
221
222 return offset;
223 }
224
225 // Emit the code to remove the frame from the stack in the exception
226 // unwind path.
227 int LIR_Assembler::emit_unwind_handler() {
228 #ifndef PRODUCT
229 if (CommentedAssembly) {
230 _masm->block_comment("Unwind handler");
231 }
232 #endif
233
234 int offset = code_offset();
235
236 // Fetch the exception from TLS and clear out exception related thread state
237 Register zero = __ zero_register(Rtemp);
238 __ ldr(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
239 __ str(zero, Address(Rthread, JavaThread::exception_oop_offset()));
240 __ str(zero, Address(Rthread, JavaThread::exception_pc_offset()));
241
242 __ bind(_unwind_handler_entry);
243 __ verify_not_null_oop(Rexception_obj);
244
245 // Preform needed unlocking
246 MonitorExitStub* stub = NULL;
247 if (method()->is_synchronized()) {
248 monitor_address(0, FrameMap::R0_opr);
249 stub = new MonitorExitStub(FrameMap::R0_opr, true, 0);
250 __ unlock_object(R2, R1, R0, *stub->entry());
251 __ bind(*stub->continuation());
252 }
253
254 // remove the activation and dispatch to the unwind handler
255 __ remove_frame(initial_frame_size_in_bytes()); // restores FP and LR
256 __ jump(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type, Rtemp);
257
258 // Emit the slow path assembly
259 if (stub != NULL) {
260 stub->emit_code(this);
261 }
262
263 return offset;
264 }
265
266
267 int LIR_Assembler::emit_deopt_handler() {
268 address handler_base = __ start_a_stub(deopt_handler_size());
269 if (handler_base == NULL) {
270 bailout("deopt handler overflow");
271 return -1;
272 }
273
274 int offset = code_offset();
275
276 __ mov_relative_address(LR, __ pc());
277 __ push(LR); // stub expects LR to be saved
278 __ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, noreg);
279
280 assert(code_offset() - offset <= deopt_handler_size(), "overflow");
281 __ end_a_stub();
282
283 return offset;
284 }
285
286
287 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
288 // Pop the frame before safepoint polling
289 __ remove_frame(initial_frame_size_in_bytes());
290 __ read_polling_page(Rtemp, relocInfo::poll_return_type);
291 __ ret();
292 }
293
294 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
295
296 int offset = __ offset();
297 __ get_polling_page(Rtemp);
298 __ relocate(relocInfo::poll_type);
299 add_debug_info_for_branch(info); // help pc_desc_at to find correct scope for current PC
300 __ ldr(Rtemp, Address(Rtemp));
301
302 return offset;
303 }
304
305
306 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
307 if (from_reg != to_reg) {
308 __ mov(to_reg, from_reg);
309 }
310 }
311
312 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
313 assert(src->is_constant() && dest->is_register(), "must be");
314 LIR_Const* c = src->as_constant_ptr();
315
316 switch (c->type()) {
317 case T_ADDRESS:
318 case T_INT:
319 assert(patch_code == lir_patch_none, "no patching handled here");
320 __ mov_slow(dest->as_register(), c->as_jint());
321 break;
322
323 case T_LONG:
324 assert(patch_code == lir_patch_none, "no patching handled here");
325 __ mov_slow(dest->as_register_lo(), c->as_jint_lo());
326 __ mov_slow(dest->as_register_hi(), c->as_jint_hi());
327 break;
328
329 case T_OBJECT:
330 if (patch_code == lir_patch_none) {
331 __ mov_oop(dest->as_register(), c->as_jobject());
332 } else {
333 jobject2reg_with_patching(dest->as_register(), info);
334 }
335 break;
336
337 case T_METADATA:
338 if (patch_code == lir_patch_none) {
339 __ mov_metadata(dest->as_register(), c->as_metadata());
340 } else {
341 klass2reg_with_patching(dest->as_register(), info);
342 }
343 break;
344
345 case T_FLOAT:
346 if (dest->is_single_fpu()) {
347 __ mov_float(dest->as_float_reg(), c->as_jfloat());
348 } else {
349 // Simple getters can return float constant directly into r0
350 __ mov_slow(dest->as_register(), c->as_jint_bits());
351 }
352 break;
353
354 case T_DOUBLE:
355 if (dest->is_double_fpu()) {
356 __ mov_double(dest->as_double_reg(), c->as_jdouble());
357 } else {
358 // Simple getters can return double constant directly into r1r0
359 __ mov_slow(dest->as_register_lo(), c->as_jint_lo_bits());
360 __ mov_slow(dest->as_register_hi(), c->as_jint_hi_bits());
361 }
362 break;
363
364 default:
365 ShouldNotReachHere();
366 }
367 }
368
369 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
370 assert(src->is_constant(), "must be");
371 assert(dest->is_stack(), "must be");
372 LIR_Const* c = src->as_constant_ptr();
373
374 switch (c->type()) {
375 case T_INT: // fall through
376 case T_FLOAT:
377 __ mov_slow(Rtemp, c->as_jint_bits());
378 __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
379 break;
380
381 case T_ADDRESS:
382 __ mov_slow(Rtemp, c->as_jint());
383 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
384 break;
385
386 case T_OBJECT:
387 __ mov_oop(Rtemp, c->as_jobject());
388 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
389 break;
390
391 case T_LONG: // fall through
392 case T_DOUBLE:
393 __ mov_slow(Rtemp, c->as_jint_lo_bits());
394 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
395 if (c->as_jint_hi_bits() != c->as_jint_lo_bits()) {
396 __ mov_slow(Rtemp, c->as_jint_hi_bits());
397 }
398 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
399 break;
400
401 default:
402 ShouldNotReachHere();
403 }
404 }
405
406 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
407 CodeEmitInfo* info, bool wide) {
408 assert((src->as_constant_ptr()->type() == T_OBJECT && src->as_constant_ptr()->as_jobject() == NULL),"cannot handle otherwise");
409 __ mov(Rtemp, 0);
410
411 int null_check_offset = code_offset();
412 __ str(Rtemp, as_Address(dest->as_address_ptr()));
413
414 if (info != NULL) {
415 assert(false, "arm32 didn't support this before, investigate if bug");
416 add_debug_info_for_null_check(null_check_offset, info);
417 }
418 }
419
420 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
421 assert(src->is_register() && dest->is_register(), "must be");
422
423 if (src->is_single_cpu()) {
424 if (dest->is_single_cpu()) {
425 move_regs(src->as_register(), dest->as_register());
426 } else if (dest->is_single_fpu()) {
427 __ fmsr(dest->as_float_reg(), src->as_register());
428 } else {
429 ShouldNotReachHere();
430 }
431 } else if (src->is_double_cpu()) {
432 if (dest->is_double_cpu()) {
433 __ long_move(dest->as_register_lo(), dest->as_register_hi(), src->as_register_lo(), src->as_register_hi());
434 } else {
435 __ fmdrr(dest->as_double_reg(), src->as_register_lo(), src->as_register_hi());
436 }
437 } else if (src->is_single_fpu()) {
438 if (dest->is_single_fpu()) {
439 __ mov_float(dest->as_float_reg(), src->as_float_reg());
440 } else if (dest->is_single_cpu()) {
441 __ mov_fpr2gpr_float(dest->as_register(), src->as_float_reg());
442 } else {
443 ShouldNotReachHere();
444 }
445 } else if (src->is_double_fpu()) {
446 if (dest->is_double_fpu()) {
447 __ mov_double(dest->as_double_reg(), src->as_double_reg());
448 } else if (dest->is_double_cpu()) {
449 __ fmrrd(dest->as_register_lo(), dest->as_register_hi(), src->as_double_reg());
450 } else {
451 ShouldNotReachHere();
452 }
453 } else {
454 ShouldNotReachHere();
455 }
456 }
457
458 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
459 assert(src->is_register(), "should not call otherwise");
460 assert(dest->is_stack(), "should not call otherwise");
461
462 Address addr = dest->is_single_word() ?
463 frame_map()->address_for_slot(dest->single_stack_ix()) :
464 frame_map()->address_for_slot(dest->double_stack_ix());
465
466 assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
467 if (src->is_single_fpu() || src->is_double_fpu()) {
468 if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
469 }
470
471 if (src->is_single_cpu()) {
472 switch (type) {
473 case T_OBJECT:
474 case T_ARRAY: __ verify_oop(src->as_register()); // fall through
475 case T_ADDRESS:
476 case T_METADATA: __ str(src->as_register(), addr); break;
477 case T_FLOAT: // used in intBitsToFloat intrinsic implementation, fall through
478 case T_INT: __ str_32(src->as_register(), addr); break;
479 default:
480 ShouldNotReachHere();
481 }
482 } else if (src->is_double_cpu()) {
483 __ str(src->as_register_lo(), addr);
484 __ str(src->as_register_hi(), frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
485 } else if (src->is_single_fpu()) {
486 __ str_float(src->as_float_reg(), addr);
487 } else if (src->is_double_fpu()) {
488 __ str_double(src->as_double_reg(), addr);
489 } else {
490 ShouldNotReachHere();
491 }
492 }
493
494
495 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
496 LIR_PatchCode patch_code, CodeEmitInfo* info,
497 bool pop_fpu_stack, bool wide) {
498 LIR_Address* to_addr = dest->as_address_ptr();
499 Register base_reg = to_addr->base()->as_pointer_register();
500 const bool needs_patching = (patch_code != lir_patch_none);
501
502 PatchingStub* patch = NULL;
503 if (needs_patching) {
504 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
505 }
506
507 int null_check_offset = code_offset();
508
509 switch (type) {
510 case T_ARRAY:
511 case T_OBJECT:
512 if (UseCompressedOops && !wide) {
513 ShouldNotReachHere();
514 } else {
515 __ str(src->as_register(), as_Address(to_addr));
516 }
517 break;
518
519 case T_ADDRESS:
520 __ str(src->as_pointer_register(), as_Address(to_addr));
521 break;
522
523 case T_BYTE:
524 case T_BOOLEAN:
525 __ strb(src->as_register(), as_Address(to_addr));
526 break;
527
528 case T_CHAR:
529 case T_SHORT:
530 __ strh(src->as_register(), as_Address(to_addr));
531 break;
532
533 case T_INT:
534 #ifdef __SOFTFP__
535 case T_FLOAT:
536 #endif // __SOFTFP__
537 __ str_32(src->as_register(), as_Address(to_addr));
538 break;
539
540
541 #ifdef __SOFTFP__
542 case T_DOUBLE:
543 #endif // __SOFTFP__
544 case T_LONG: {
545 Register from_lo = src->as_register_lo();
546 Register from_hi = src->as_register_hi();
547 if (to_addr->index()->is_register()) {
548 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
549 assert(to_addr->disp() == 0, "Not yet supporting both");
550 __ add(Rtemp, base_reg, to_addr->index()->as_register());
551 base_reg = Rtemp;
552 __ str(from_lo, Address(Rtemp));
553 if (patch != NULL) {
554 __ nop(); // see comment before patching_epilog for 2nd str
555 patching_epilog(patch, lir_patch_low, base_reg, info);
556 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
557 patch_code = lir_patch_high;
558 }
559 __ str(from_hi, Address(Rtemp, BytesPerWord));
560 } else if (base_reg == from_lo) {
561 __ str(from_hi, as_Address_hi(to_addr));
562 if (patch != NULL) {
563 __ nop(); // see comment before patching_epilog for 2nd str
564 patching_epilog(patch, lir_patch_high, base_reg, info);
565 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
566 patch_code = lir_patch_low;
567 }
568 __ str(from_lo, as_Address_lo(to_addr));
569 } else {
570 __ str(from_lo, as_Address_lo(to_addr));
571 if (patch != NULL) {
572 __ nop(); // see comment before patching_epilog for 2nd str
573 patching_epilog(patch, lir_patch_low, base_reg, info);
574 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
575 patch_code = lir_patch_high;
576 }
577 __ str(from_hi, as_Address_hi(to_addr));
578 }
579 break;
580 }
581
582 #ifndef __SOFTFP__
583 case T_FLOAT:
584 if (to_addr->index()->is_register()) {
585 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
586 __ add(Rtemp, base_reg, to_addr->index()->as_register());
587 if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
588 __ fsts(src->as_float_reg(), Address(Rtemp, to_addr->disp()));
589 } else {
590 __ fsts(src->as_float_reg(), as_Address(to_addr));
591 }
592 break;
593
594 case T_DOUBLE:
595 if (to_addr->index()->is_register()) {
596 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
597 __ add(Rtemp, base_reg, to_addr->index()->as_register());
598 if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
599 __ fstd(src->as_double_reg(), Address(Rtemp, to_addr->disp()));
600 } else {
601 __ fstd(src->as_double_reg(), as_Address(to_addr));
602 }
603 break;
604 #endif // __SOFTFP__
605
606
607 default:
608 ShouldNotReachHere();
609 }
610
611 if (info != NULL) {
612 add_debug_info_for_null_check(null_check_offset, info);
613 }
614
615 if (patch != NULL) {
616 // Offset embedded into LDR/STR instruction may appear not enough
617 // to address a field. So, provide a space for one more instruction
618 // that will deal with larger offsets.
619 __ nop();
620 patching_epilog(patch, patch_code, base_reg, info);
621 }
622 }
623
624
625 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
626 assert(src->is_stack(), "should not call otherwise");
627 assert(dest->is_register(), "should not call otherwise");
628
629 Address addr = src->is_single_word() ?
630 frame_map()->address_for_slot(src->single_stack_ix()) :
631 frame_map()->address_for_slot(src->double_stack_ix());
632
633 assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
634 if (dest->is_single_fpu() || dest->is_double_fpu()) {
635 if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
636 }
637
638 if (dest->is_single_cpu()) {
639 switch (type) {
640 case T_OBJECT:
641 case T_ARRAY:
642 case T_ADDRESS:
643 case T_METADATA: __ ldr(dest->as_register(), addr); break;
644 case T_FLOAT: // used in floatToRawIntBits intrinsic implemenation
645 case T_INT: __ ldr_u32(dest->as_register(), addr); break;
646 default:
647 ShouldNotReachHere();
648 }
649 if ((type == T_OBJECT) || (type == T_ARRAY)) {
650 __ verify_oop(dest->as_register());
651 }
652 } else if (dest->is_double_cpu()) {
653 __ ldr(dest->as_register_lo(), addr);
654 __ ldr(dest->as_register_hi(), frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
655 } else if (dest->is_single_fpu()) {
656 __ ldr_float(dest->as_float_reg(), addr);
657 } else if (dest->is_double_fpu()) {
658 __ ldr_double(dest->as_double_reg(), addr);
659 } else {
660 ShouldNotReachHere();
661 }
662 }
663
664
665 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
666 if (src->is_single_stack()) {
667 switch (src->type()) {
668 case T_OBJECT:
669 case T_ARRAY:
670 case T_ADDRESS:
671 case T_METADATA:
672 __ ldr(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
673 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
674 break;
675
676 case T_INT:
677 case T_FLOAT:
678 __ ldr_u32(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
679 __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
680 break;
681
682 default:
683 ShouldNotReachHere();
684 }
685 } else {
686 assert(src->is_double_stack(), "must be");
687 __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes));
688 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
689 __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
690 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
691 }
692 }
693
694
695 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
696 LIR_PatchCode patch_code, CodeEmitInfo* info,
697 bool wide) {
698 assert(src->is_address(), "should not call otherwise");
699 assert(dest->is_register(), "should not call otherwise");
700 LIR_Address* addr = src->as_address_ptr();
701
702 Register base_reg = addr->base()->as_pointer_register();
703
704 PatchingStub* patch = NULL;
705 if (patch_code != lir_patch_none) {
706 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
707 }
708 if (info != NULL) {
709 add_debug_info_for_null_check_here(info);
710 }
711
712 switch (type) {
713 case T_OBJECT: // fall through
714 case T_ARRAY:
715 if (UseCompressedOops && !wide) {
716 __ ldr_u32(dest->as_register(), as_Address(addr));
717 } else {
718 __ ldr(dest->as_register(), as_Address(addr));
719 }
720 break;
721
722 case T_ADDRESS:
723 __ ldr(dest->as_pointer_register(), as_Address(addr));
724 break;
725
726 case T_INT:
727 #ifdef __SOFTFP__
728 case T_FLOAT:
729 #endif // __SOFTFP__
730 __ ldr(dest->as_pointer_register(), as_Address(addr));
731 break;
732
733 case T_BOOLEAN:
734 __ ldrb(dest->as_register(), as_Address(addr));
735 break;
736
737 case T_BYTE:
738 __ ldrsb(dest->as_register(), as_Address(addr));
739 break;
740
741 case T_CHAR:
742 __ ldrh(dest->as_register(), as_Address(addr));
743 break;
744
745 case T_SHORT:
746 __ ldrsh(dest->as_register(), as_Address(addr));
747 break;
748
749
750 #ifdef __SOFTFP__
751 case T_DOUBLE:
752 #endif // __SOFTFP__
753 case T_LONG: {
754 Register to_lo = dest->as_register_lo();
755 Register to_hi = dest->as_register_hi();
756 if (addr->index()->is_register()) {
757 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
758 assert(addr->disp() == 0, "Not yet supporting both");
759 __ add(Rtemp, base_reg, addr->index()->as_register());
760 base_reg = Rtemp;
761 __ ldr(to_lo, Address(Rtemp));
762 if (patch != NULL) {
763 __ nop(); // see comment before patching_epilog for 2nd ldr
764 patching_epilog(patch, lir_patch_low, base_reg, info);
765 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
766 patch_code = lir_patch_high;
767 }
768 __ ldr(to_hi, Address(Rtemp, BytesPerWord));
769 } else if (base_reg == to_lo) {
770 __ ldr(to_hi, as_Address_hi(addr));
771 if (patch != NULL) {
772 __ nop(); // see comment before patching_epilog for 2nd ldr
773 patching_epilog(patch, lir_patch_high, base_reg, info);
774 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
775 patch_code = lir_patch_low;
776 }
777 __ ldr(to_lo, as_Address_lo(addr));
778 } else {
779 __ ldr(to_lo, as_Address_lo(addr));
780 if (patch != NULL) {
781 __ nop(); // see comment before patching_epilog for 2nd ldr
782 patching_epilog(patch, lir_patch_low, base_reg, info);
783 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
784 patch_code = lir_patch_high;
785 }
786 __ ldr(to_hi, as_Address_hi(addr));
787 }
788 break;
789 }
790
791 #ifndef __SOFTFP__
792 case T_FLOAT:
793 if (addr->index()->is_register()) {
794 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
795 __ add(Rtemp, base_reg, addr->index()->as_register());
796 if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
797 __ flds(dest->as_float_reg(), Address(Rtemp, addr->disp()));
798 } else {
799 __ flds(dest->as_float_reg(), as_Address(addr));
800 }
801 break;
802
803 case T_DOUBLE:
804 if (addr->index()->is_register()) {
805 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
806 __ add(Rtemp, base_reg, addr->index()->as_register());
807 if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
808 __ fldd(dest->as_double_reg(), Address(Rtemp, addr->disp()));
809 } else {
810 __ fldd(dest->as_double_reg(), as_Address(addr));
811 }
812 break;
813 #endif // __SOFTFP__
814
815
816 default:
817 ShouldNotReachHere();
818 }
819
820 if (patch != NULL) {
821 // Offset embedded into LDR/STR instruction may appear not enough
822 // to address a field. So, provide a space for one more instruction
823 // that will deal with larger offsets.
824 __ nop();
825 patching_epilog(patch, patch_code, base_reg, info);
826 }
827
828 }
829
830
831 void LIR_Assembler::emit_op3(LIR_Op3* op) {
832 bool is_32 = op->result_opr()->is_single_cpu();
833
834 if (op->code() == lir_idiv && op->in_opr2()->is_constant() && is_32) {
835 int c = op->in_opr2()->as_constant_ptr()->as_jint();
836 assert(is_power_of_2(c), "non power-of-2 constant should be put in a register");
837
838 Register left = op->in_opr1()->as_register();
839 Register dest = op->result_opr()->as_register();
840 if (c == 1) {
841 __ mov(dest, left);
842 } else if (c == 2) {
843 __ add_32(dest, left, AsmOperand(left, lsr, 31));
844 __ asr_32(dest, dest, 1);
845 } else if (c != (int) 0x80000000) {
846 int power = log2i_exact(c);
847 __ asr_32(Rtemp, left, 31);
848 __ add_32(dest, left, AsmOperand(Rtemp, lsr, 32-power)); // dest = left + (left < 0 ? 2^power - 1 : 0);
849 __ asr_32(dest, dest, power); // dest = dest >>> power;
850 } else {
851 // x/0x80000000 is a special case, since dividend is a power of two, but is negative.
852 // The only possible result values are 0 and 1, with 1 only for dividend == divisor == 0x80000000.
853 __ cmp_32(left, c);
854 __ mov(dest, 0, ne);
855 __ mov(dest, 1, eq);
856 }
857 } else {
858 assert(op->code() == lir_idiv || op->code() == lir_irem, "unexpected op3");
859 __ call(StubRoutines::Arm::idiv_irem_entry(), relocInfo::runtime_call_type);
860 add_debug_info_for_div0_here(op->info());
861 }
862 }
863
864
865 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
866 #ifdef ASSERT
867 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
868 if (op->block() != NULL) _branch_target_blocks.append(op->block());
869 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
870 assert(op->info() == NULL, "CodeEmitInfo?");
871 #endif // ASSERT
872
873 #ifdef __SOFTFP__
874 assert (op->code() != lir_cond_float_branch, "this should be impossible");
875 #else
876 if (op->code() == lir_cond_float_branch) {
877 __ fmstat();
878 __ b(*(op->ublock()->label()), vs);
879 }
880 #endif // __SOFTFP__
881
882 AsmCondition acond = al;
883 switch (op->cond()) {
884 case lir_cond_equal: acond = eq; break;
885 case lir_cond_notEqual: acond = ne; break;
886 case lir_cond_less: acond = lt; break;
887 case lir_cond_lessEqual: acond = le; break;
888 case lir_cond_greaterEqual: acond = ge; break;
889 case lir_cond_greater: acond = gt; break;
890 case lir_cond_aboveEqual: acond = hs; break;
891 case lir_cond_belowEqual: acond = ls; break;
892 default: assert(op->cond() == lir_cond_always, "must be");
893 }
894 __ b(*(op->label()), acond);
895 }
896
897
898 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
899 LIR_Opr src = op->in_opr();
900 LIR_Opr dest = op->result_opr();
901
902 switch (op->bytecode()) {
903 case Bytecodes::_i2l:
904 move_regs(src->as_register(), dest->as_register_lo());
905 __ mov(dest->as_register_hi(), AsmOperand(src->as_register(), asr, 31));
906 break;
907 case Bytecodes::_l2i:
908 move_regs(src->as_register_lo(), dest->as_register());
909 break;
910 case Bytecodes::_i2b:
911 __ sign_extend(dest->as_register(), src->as_register(), 8);
912 break;
913 case Bytecodes::_i2s:
914 __ sign_extend(dest->as_register(), src->as_register(), 16);
915 break;
916 case Bytecodes::_i2c:
917 __ zero_extend(dest->as_register(), src->as_register(), 16);
918 break;
919 case Bytecodes::_f2d:
920 __ convert_f2d(dest->as_double_reg(), src->as_float_reg());
921 break;
922 case Bytecodes::_d2f:
923 __ convert_d2f(dest->as_float_reg(), src->as_double_reg());
924 break;
925 case Bytecodes::_i2f:
926 __ fmsr(Stemp, src->as_register());
927 __ fsitos(dest->as_float_reg(), Stemp);
928 break;
929 case Bytecodes::_i2d:
930 __ fmsr(Stemp, src->as_register());
931 __ fsitod(dest->as_double_reg(), Stemp);
932 break;
933 case Bytecodes::_f2i:
934 __ ftosizs(Stemp, src->as_float_reg());
935 __ fmrs(dest->as_register(), Stemp);
936 break;
937 case Bytecodes::_d2i:
938 __ ftosizd(Stemp, src->as_double_reg());
939 __ fmrs(dest->as_register(), Stemp);
940 break;
941 default:
942 ShouldNotReachHere();
943 }
944 }
945
946
947 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
948 if (op->init_check()) {
949 Register tmp = op->tmp1()->as_register();
950 __ ldrb(tmp, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
951 add_debug_info_for_null_check_here(op->stub()->info());
952 __ cmp(tmp, InstanceKlass::fully_initialized);
953 __ b(*op->stub()->entry(), ne);
954 }
955 __ allocate_object(op->obj()->as_register(),
956 op->tmp1()->as_register(),
957 op->tmp2()->as_register(),
958 op->tmp3()->as_register(),
959 op->header_size(),
960 op->object_size(),
961 op->klass()->as_register(),
962 *op->stub()->entry());
963 __ bind(*op->stub()->continuation());
964 }
965
966 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
967 if (UseSlowPath ||
968 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
969 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
970 __ b(*op->stub()->entry());
971 } else {
972 __ allocate_array(op->obj()->as_register(),
973 op->len()->as_register(),
974 op->tmp1()->as_register(),
975 op->tmp2()->as_register(),
976 op->tmp3()->as_register(),
977 arrayOopDesc::header_size(op->type()),
978 type2aelembytes(op->type()),
979 op->klass()->as_register(),
980 *op->stub()->entry());
981 }
982 __ bind(*op->stub()->continuation());
983 }
984
985 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
986 ciMethodData *md, ciProfileData *data,
987 Register recv, Register tmp1, Label* update_done) {
988 assert_different_registers(mdo, recv, tmp1);
989 uint i;
990 for (i = 0; i < VirtualCallData::row_limit(); i++) {
991 Label next_test;
992 // See if the receiver is receiver[n].
993 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
994 mdo_offset_bias);
995 __ ldr(tmp1, receiver_addr);
996 __ verify_klass_ptr(tmp1);
997 __ cmp(recv, tmp1);
998 __ b(next_test, ne);
999 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1000 mdo_offset_bias);
1001 __ ldr(tmp1, data_addr);
1002 __ add(tmp1, tmp1, DataLayout::counter_increment);
1003 __ str(tmp1, data_addr);
1004 __ b(*update_done);
1005 __ bind(next_test);
1006 }
1007
1008 // Didn't find receiver; find next empty slot and fill it in
1009 for (i = 0; i < VirtualCallData::row_limit(); i++) {
1010 Label next_test;
1011 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
1012 mdo_offset_bias);
1013 __ ldr(tmp1, recv_addr);
1014 __ cbnz(tmp1, next_test);
1015 __ str(recv, recv_addr);
1016 __ mov(tmp1, DataLayout::counter_increment);
1017 __ str(tmp1, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1018 mdo_offset_bias));
1019 __ b(*update_done);
1020 __ bind(next_test);
1021 }
1022 }
1023
1024 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
1025 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
1026 md = method->method_data_or_null();
1027 assert(md != NULL, "Sanity");
1028 data = md->bci_to_data(bci);
1029 assert(data != NULL, "need data for checkcast");
1030 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1031 if (md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes() >= 4096) {
1032 // The offset is large so bias the mdo by the base of the slot so
1033 // that the ldr can use an immediate offset to reference the slots of the data
1034 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
1035 }
1036 }
1037
1038 // On 32-bit ARM, code before this helper should test obj for null (ZF should be set if obj is null).
1039 void LIR_Assembler::typecheck_profile_helper1(ciMethod* method, int bci,
1040 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias,
1041 Register obj, Register mdo, Register data_val, Label* obj_is_null) {
1042 assert(method != NULL, "Should have method");
1043 assert_different_registers(obj, mdo, data_val);
1044 setup_md_access(method, bci, md, data, mdo_offset_bias);
1045 Label not_null;
1046 __ b(not_null, ne);
1047 __ mov_metadata(mdo, md->constant_encoding());
1048 if (mdo_offset_bias > 0) {
1049 __ mov_slow(data_val, mdo_offset_bias);
1050 __ add(mdo, mdo, data_val);
1051 }
1052 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
1053 __ ldrb(data_val, flags_addr);
1054 __ orr(data_val, data_val, (uint)BitData::null_seen_byte_constant());
1055 __ strb(data_val, flags_addr);
1056 __ b(*obj_is_null);
1057 __ bind(not_null);
1058 }
1059
1060 void LIR_Assembler::typecheck_profile_helper2(ciMethodData* md, ciProfileData* data, int mdo_offset_bias,
1061 Register mdo, Register recv, Register value, Register tmp1,
1062 Label* profile_cast_success, Label* profile_cast_failure,
1063 Label* success, Label* failure) {
1064 assert_different_registers(mdo, value, tmp1);
1065 __ bind(*profile_cast_success);
1066 __ mov_metadata(mdo, md->constant_encoding());
1067 if (mdo_offset_bias > 0) {
1068 __ mov_slow(tmp1, mdo_offset_bias);
1069 __ add(mdo, mdo, tmp1);
1070 }
1071 __ load_klass(recv, value);
1072 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
1073 __ b(*success);
1074 // Cast failure case
1075 __ bind(*profile_cast_failure);
1076 __ mov_metadata(mdo, md->constant_encoding());
1077 if (mdo_offset_bias > 0) {
1078 __ mov_slow(tmp1, mdo_offset_bias);
1079 __ add(mdo, mdo, tmp1);
1080 }
1081 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
1082 __ ldr(tmp1, data_addr);
1083 __ sub(tmp1, tmp1, DataLayout::counter_increment);
1084 __ str(tmp1, data_addr);
1085 __ b(*failure);
1086 }
1087
1088 // Sets `res` to true, if `cond` holds.
1089 static void set_instanceof_result(MacroAssembler* _masm, Register res, AsmCondition cond) {
1090 __ mov(res, 1, cond);
1091 }
1092
1093
1094 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1095 // TODO: ARM - can be more effective with one more register
1096 switch (op->code()) {
1097 case lir_store_check: {
1098 CodeStub* stub = op->stub();
1099 Register value = op->object()->as_register();
1100 Register array = op->array()->as_register();
1101 Register klass_RInfo = op->tmp1()->as_register();
1102 Register k_RInfo = op->tmp2()->as_register();
1103 assert_different_registers(klass_RInfo, k_RInfo, Rtemp);
1104 if (op->should_profile()) {
1105 assert_different_registers(value, klass_RInfo, k_RInfo, Rtemp);
1106 }
1107
1108 // check if it needs to be profiled
1109 ciMethodData* md;
1110 ciProfileData* data;
1111 int mdo_offset_bias = 0;
1112 Label profile_cast_success, profile_cast_failure, done;
1113 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1114 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1115
1116 if (op->should_profile()) {
1117 __ cmp(value, 0);
1118 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, value, k_RInfo, Rtemp, &done);
1119 } else {
1120 __ cbz(value, done);
1121 }
1122 assert_different_registers(k_RInfo, value);
1123 add_debug_info_for_null_check_here(op->info_for_exception());
1124 __ load_klass(k_RInfo, array);
1125 __ load_klass(klass_RInfo, value);
1126 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1127 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1128 // check for immediate positive hit
1129 __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1130 __ cmp(klass_RInfo, k_RInfo);
1131 __ cond_cmp(Rtemp, k_RInfo, ne);
1132 __ b(*success_target, eq);
1133 // check for immediate negative hit
1134 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1135 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1136 __ b(*failure_target, ne);
1137 // slow case
1138 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1139 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1140 __ cbz(R0, *failure_target);
1141 if (op->should_profile()) {
1142 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1143 if (mdo == value) {
1144 mdo = k_RInfo;
1145 recv = klass_RInfo;
1146 }
1147 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, value, tmp1,
1148 &profile_cast_success, &profile_cast_failure,
1149 &done, stub->entry());
1150 }
1151 __ bind(done);
1152 break;
1153 }
1154
1155 case lir_checkcast: {
1156 CodeStub* stub = op->stub();
1157 Register obj = op->object()->as_register();
1158 Register res = op->result_opr()->as_register();
1159 Register klass_RInfo = op->tmp1()->as_register();
1160 Register k_RInfo = op->tmp2()->as_register();
1161 ciKlass* k = op->klass();
1162 assert_different_registers(res, k_RInfo, klass_RInfo, Rtemp);
1163
1164 if (stub->is_simple_exception_stub()) {
1165 // TODO: ARM - Late binding is used to prevent confusion of register allocator
1166 assert(stub->is_exception_throw_stub(), "must be");
1167 ((SimpleExceptionStub*)stub)->set_obj(op->result_opr());
1168 }
1169 ciMethodData* md;
1170 ciProfileData* data;
1171 int mdo_offset_bias = 0;
1172
1173 Label done;
1174
1175 Label profile_cast_failure, profile_cast_success;
1176 Label *failure_target = op->should_profile() ? &profile_cast_failure : op->stub()->entry();
1177 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1178
1179
1180 __ movs(res, obj);
1181 if (op->should_profile()) {
1182 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1183 } else {
1184 __ b(done, eq);
1185 }
1186 if (k->is_loaded()) {
1187 __ mov_metadata(k_RInfo, k->constant_encoding());
1188 } else if (k_RInfo != obj) {
1189 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1190 __ movs(res, obj);
1191 } else {
1192 // Patching doesn't update "res" register after GC, so do patching first
1193 klass2reg_with_patching(Rtemp, op->info_for_patch());
1194 __ movs(res, obj);
1195 __ mov(k_RInfo, Rtemp);
1196 }
1197 __ load_klass(klass_RInfo, res, ne);
1198
1199 if (op->fast_check()) {
1200 __ cmp(klass_RInfo, k_RInfo, ne);
1201 __ b(*failure_target, ne);
1202 } else if (k->is_loaded()) {
1203 __ b(*success_target, eq);
1204 __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1205 if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1206 __ cmp(Rtemp, k_RInfo);
1207 __ b(*failure_target, ne);
1208 } else {
1209 __ cmp(klass_RInfo, k_RInfo);
1210 __ cmp(Rtemp, k_RInfo, ne);
1211 __ b(*success_target, eq);
1212 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1213 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1214 __ cbz(R0, *failure_target);
1215 }
1216 } else {
1217 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1218 __ b(*success_target, eq);
1219 // check for immediate positive hit
1220 __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1221 __ cmp(klass_RInfo, k_RInfo);
1222 __ cmp(Rtemp, k_RInfo, ne);
1223 __ b(*success_target, eq);
1224 // check for immediate negative hit
1225 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1226 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1227 __ b(*failure_target, ne);
1228 // slow case
1229 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1230 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1231 __ cbz(R0, *failure_target);
1232 }
1233
1234 if (op->should_profile()) {
1235 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1236 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1237 &profile_cast_success, &profile_cast_failure,
1238 &done, stub->entry());
1239 }
1240 __ bind(done);
1241 break;
1242 }
1243
1244 case lir_instanceof: {
1245 Register obj = op->object()->as_register();
1246 Register res = op->result_opr()->as_register();
1247 Register klass_RInfo = op->tmp1()->as_register();
1248 Register k_RInfo = op->tmp2()->as_register();
1249 ciKlass* k = op->klass();
1250 assert_different_registers(res, klass_RInfo, k_RInfo, Rtemp);
1251
1252 ciMethodData* md;
1253 ciProfileData* data;
1254 int mdo_offset_bias = 0;
1255
1256 Label done;
1257
1258 Label profile_cast_failure, profile_cast_success;
1259 Label *failure_target = op->should_profile() ? &profile_cast_failure : &done;
1260 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1261
1262 __ movs(res, obj);
1263
1264 if (op->should_profile()) {
1265 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1266 } else {
1267 __ b(done, eq);
1268 }
1269
1270 if (k->is_loaded()) {
1271 __ mov_metadata(k_RInfo, k->constant_encoding());
1272 } else {
1273 op->info_for_patch()->add_register_oop(FrameMap::as_oop_opr(res));
1274 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1275 }
1276 __ load_klass(klass_RInfo, res);
1277
1278 if (!op->should_profile()) {
1279 __ mov(res, 0);
1280 }
1281
1282 if (op->fast_check()) {
1283 __ cmp(klass_RInfo, k_RInfo);
1284 if (!op->should_profile()) {
1285 set_instanceof_result(_masm, res, eq);
1286 } else {
1287 __ b(profile_cast_failure, ne);
1288 }
1289 } else if (k->is_loaded()) {
1290 __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1291 if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1292 __ cmp(Rtemp, k_RInfo);
1293 if (!op->should_profile()) {
1294 set_instanceof_result(_masm, res, eq);
1295 } else {
1296 __ b(profile_cast_failure, ne);
1297 }
1298 } else {
1299 __ cmp(klass_RInfo, k_RInfo);
1300 __ cond_cmp(Rtemp, k_RInfo, ne);
1301 if (!op->should_profile()) {
1302 set_instanceof_result(_masm, res, eq);
1303 }
1304 __ b(*success_target, eq);
1305 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1306 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1307 if (!op->should_profile()) {
1308 move_regs(R0, res);
1309 } else {
1310 __ cbz(R0, *failure_target);
1311 }
1312 }
1313 } else {
1314 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1315 // check for immediate positive hit
1316 __ cmp(klass_RInfo, k_RInfo);
1317 if (!op->should_profile()) {
1318 __ ldr(res, Address(klass_RInfo, Rtemp), ne);
1319 __ cond_cmp(res, k_RInfo, ne);
1320 set_instanceof_result(_masm, res, eq);
1321 } else {
1322 __ ldr(Rtemp, Address(klass_RInfo, Rtemp), ne);
1323 __ cond_cmp(Rtemp, k_RInfo, ne);
1324 }
1325 __ b(*success_target, eq);
1326 // check for immediate negative hit
1327 if (op->should_profile()) {
1328 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1329 }
1330 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1331 if (!op->should_profile()) {
1332 __ mov(res, 0, ne);
1333 }
1334 __ b(*failure_target, ne);
1335 // slow case
1336 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1337 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1338 if (!op->should_profile()) {
1339 move_regs(R0, res);
1340 }
1341 if (op->should_profile()) {
1342 __ cbz(R0, *failure_target);
1343 }
1344 }
1345
1346 if (op->should_profile()) {
1347 Label done_ok, done_failure;
1348 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1349 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1350 &profile_cast_success, &profile_cast_failure,
1351 &done_ok, &done_failure);
1352 __ bind(done_failure);
1353 __ mov(res, 0);
1354 __ b(done);
1355 __ bind(done_ok);
1356 __ mov(res, 1);
1357 }
1358 __ bind(done);
1359 break;
1360 }
1361 default:
1362 ShouldNotReachHere();
1363 }
1364 }
1365
1366
1367 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1368 // if (*addr == cmpval) {
1369 // *addr = newval;
1370 // dest = 1;
1371 // } else {
1372 // dest = 0;
1373 // }
1374 // FIXME: membar_release
1375 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
1376 Register addr = op->addr()->is_register() ?
1377 op->addr()->as_pointer_register() :
1378 op->addr()->as_address_ptr()->base()->as_pointer_register();
1379 assert(op->addr()->is_register() || op->addr()->as_address_ptr()->disp() == 0, "unexpected disp");
1380 assert(op->addr()->is_register() || op->addr()->as_address_ptr()->index() == LIR_Opr::illegalOpr(), "unexpected index");
1381 if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
1382 Register cmpval = op->cmp_value()->as_register();
1383 Register newval = op->new_value()->as_register();
1384 Register dest = op->result_opr()->as_register();
1385 assert_different_registers(dest, addr, cmpval, newval, Rtemp);
1386
1387 __ atomic_cas_bool(cmpval, newval, addr, 0, Rtemp); // Rtemp free by default at C1 LIR layer
1388 __ mov(dest, 1, eq);
1389 __ mov(dest, 0, ne);
1390 } else if (op->code() == lir_cas_long) {
1391 assert(VM_Version::supports_cx8(), "wrong machine");
1392 Register cmp_value_lo = op->cmp_value()->as_register_lo();
1393 Register cmp_value_hi = op->cmp_value()->as_register_hi();
1394 Register new_value_lo = op->new_value()->as_register_lo();
1395 Register new_value_hi = op->new_value()->as_register_hi();
1396 Register dest = op->result_opr()->as_register();
1397 Register tmp_lo = op->tmp1()->as_register_lo();
1398 Register tmp_hi = op->tmp1()->as_register_hi();
1399
1400 assert_different_registers(tmp_lo, tmp_hi, cmp_value_lo, cmp_value_hi, dest, new_value_lo, new_value_hi, addr);
1401 assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
1402 assert(new_value_hi->encoding() == new_value_lo->encoding() + 1, "non aligned register pair");
1403 assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
1404 assert((new_value_lo->encoding() & 0x1) == 0, "misaligned register pair");
1405 __ atomic_cas64(tmp_lo, tmp_hi, dest, cmp_value_lo, cmp_value_hi,
1406 new_value_lo, new_value_hi, addr, 0);
1407 } else {
1408 Unimplemented();
1409 }
1410 // FIXME: is full membar really needed instead of just membar_acquire?
1411 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
1412 }
1413
1414
1415 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1416 AsmCondition acond = al;
1417 AsmCondition ncond = nv;
1418 if (opr1 != opr2) {
1419 switch (condition) {
1420 case lir_cond_equal: acond = eq; ncond = ne; break;
1421 case lir_cond_notEqual: acond = ne; ncond = eq; break;
1422 case lir_cond_less: acond = lt; ncond = ge; break;
1423 case lir_cond_lessEqual: acond = le; ncond = gt; break;
1424 case lir_cond_greaterEqual: acond = ge; ncond = lt; break;
1425 case lir_cond_greater: acond = gt; ncond = le; break;
1426 case lir_cond_aboveEqual: acond = hs; ncond = lo; break;
1427 case lir_cond_belowEqual: acond = ls; ncond = hi; break;
1428 default: ShouldNotReachHere();
1429 }
1430 }
1431
1432 for (;;) { // two iterations only
1433 if (opr1 == result) {
1434 // do nothing
1435 } else if (opr1->is_single_cpu()) {
1436 __ mov(result->as_register(), opr1->as_register(), acond);
1437 } else if (opr1->is_double_cpu()) {
1438 __ long_move(result->as_register_lo(), result->as_register_hi(),
1439 opr1->as_register_lo(), opr1->as_register_hi(), acond);
1440 } else if (opr1->is_single_stack()) {
1441 __ ldr(result->as_register(), frame_map()->address_for_slot(opr1->single_stack_ix()), acond);
1442 } else if (opr1->is_double_stack()) {
1443 __ ldr(result->as_register_lo(),
1444 frame_map()->address_for_slot(opr1->double_stack_ix(), lo_word_offset_in_bytes), acond);
1445 __ ldr(result->as_register_hi(),
1446 frame_map()->address_for_slot(opr1->double_stack_ix(), hi_word_offset_in_bytes), acond);
1447 } else if (opr1->is_illegal()) {
1448 // do nothing: this part of the cmove has been optimized away in the peephole optimizer
1449 } else {
1450 assert(opr1->is_constant(), "must be");
1451 LIR_Const* c = opr1->as_constant_ptr();
1452
1453 switch (c->type()) {
1454 case T_INT:
1455 __ mov_slow(result->as_register(), c->as_jint(), acond);
1456 break;
1457 case T_LONG:
1458 __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1459 __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1460 break;
1461 case T_OBJECT:
1462 __ mov_oop(result->as_register(), c->as_jobject(), 0, acond);
1463 break;
1464 case T_FLOAT:
1465 #ifdef __SOFTFP__
1466 // not generated now.
1467 __ mov_slow(result->as_register(), c->as_jint(), acond);
1468 #else
1469 __ mov_float(result->as_float_reg(), c->as_jfloat(), acond);
1470 #endif // __SOFTFP__
1471 break;
1472 case T_DOUBLE:
1473 #ifdef __SOFTFP__
1474 // not generated now.
1475 __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1476 __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1477 #else
1478 __ mov_double(result->as_double_reg(), c->as_jdouble(), acond);
1479 #endif // __SOFTFP__
1480 break;
1481 default:
1482 ShouldNotReachHere();
1483 }
1484 }
1485
1486 // Negate the condition and repeat the algorithm with the second operand
1487 if (opr1 == opr2) { break; }
1488 opr1 = opr2;
1489 acond = ncond;
1490 }
1491 }
1492
1493 #ifdef ASSERT
1494 static int reg_size(LIR_Opr op) {
1495 switch (op->type()) {
1496 case T_FLOAT:
1497 case T_INT: return BytesPerInt;
1498 case T_LONG:
1499 case T_DOUBLE: return BytesPerLong;
1500 case T_OBJECT:
1501 case T_ARRAY:
1502 case T_METADATA: return BytesPerWord;
1503 case T_ADDRESS:
1504 case T_ILLEGAL: // fall through
1505 default: ShouldNotReachHere(); return -1;
1506 }
1507 }
1508 #endif
1509
1510 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1511 assert(info == NULL, "unused on this code path");
1512 assert(dest->is_register(), "wrong items state");
1513
1514 if (right->is_address()) {
1515 // special case for adding shifted/extended register
1516 const Register res = dest->as_pointer_register();
1517 const Register lreg = left->as_pointer_register();
1518 const LIR_Address* addr = right->as_address_ptr();
1519
1520 assert(addr->base()->as_pointer_register() == lreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1521
1522 int scale = addr->scale();
1523 AsmShift shift = lsl;
1524
1525
1526 assert(reg_size(addr->base()) == reg_size(addr->index()), "should be");
1527 assert(reg_size(addr->base()) == reg_size(dest), "should be");
1528 assert(reg_size(dest) == wordSize, "should be");
1529
1530 AsmOperand operand(addr->index()->as_pointer_register(), shift, scale);
1531 switch (code) {
1532 case lir_add: __ add(res, lreg, operand); break;
1533 case lir_sub: __ sub(res, lreg, operand); break;
1534 default: ShouldNotReachHere();
1535 }
1536
1537 } else if (left->is_address()) {
1538 assert(code == lir_sub && right->is_single_cpu(), "special case used by strength_reduce_multiply()");
1539 const LIR_Address* addr = left->as_address_ptr();
1540 const Register res = dest->as_register();
1541 const Register rreg = right->as_register();
1542 assert(addr->base()->as_register() == rreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1543 __ rsb(res, rreg, AsmOperand(addr->index()->as_register(), lsl, addr->scale()));
1544
1545 } else if (dest->is_single_cpu()) {
1546 assert(left->is_single_cpu(), "unexpected left operand");
1547
1548 const Register res = dest->as_register();
1549 const Register lreg = left->as_register();
1550
1551 if (right->is_single_cpu()) {
1552 const Register rreg = right->as_register();
1553 switch (code) {
1554 case lir_add: __ add_32(res, lreg, rreg); break;
1555 case lir_sub: __ sub_32(res, lreg, rreg); break;
1556 case lir_mul: __ mul_32(res, lreg, rreg); break;
1557 default: ShouldNotReachHere();
1558 }
1559 } else {
1560 assert(right->is_constant(), "must be");
1561 const jint c = right->as_constant_ptr()->as_jint();
1562 if (!Assembler::is_arith_imm_in_range(c)) {
1563 BAILOUT("illegal arithmetic operand");
1564 }
1565 switch (code) {
1566 case lir_add: __ add_32(res, lreg, c); break;
1567 case lir_sub: __ sub_32(res, lreg, c); break;
1568 default: ShouldNotReachHere();
1569 }
1570 }
1571
1572 } else if (dest->is_double_cpu()) {
1573 Register res_lo = dest->as_register_lo();
1574 Register res_hi = dest->as_register_hi();
1575 Register lreg_lo = left->as_register_lo();
1576 Register lreg_hi = left->as_register_hi();
1577 if (right->is_double_cpu()) {
1578 Register rreg_lo = right->as_register_lo();
1579 Register rreg_hi = right->as_register_hi();
1580 if (res_lo == lreg_hi || res_lo == rreg_hi) {
1581 res_lo = Rtemp;
1582 }
1583 switch (code) {
1584 case lir_add:
1585 __ adds(res_lo, lreg_lo, rreg_lo);
1586 __ adc(res_hi, lreg_hi, rreg_hi);
1587 break;
1588 case lir_sub:
1589 __ subs(res_lo, lreg_lo, rreg_lo);
1590 __ sbc(res_hi, lreg_hi, rreg_hi);
1591 break;
1592 default:
1593 ShouldNotReachHere();
1594 }
1595 } else {
1596 assert(right->is_constant(), "must be");
1597 assert((right->as_constant_ptr()->as_jlong() >> 32) == 0, "out of range");
1598 const jint c = (jint) right->as_constant_ptr()->as_jlong();
1599 if (res_lo == lreg_hi) {
1600 res_lo = Rtemp;
1601 }
1602 switch (code) {
1603 case lir_add:
1604 __ adds(res_lo, lreg_lo, c);
1605 __ adc(res_hi, lreg_hi, 0);
1606 break;
1607 case lir_sub:
1608 __ subs(res_lo, lreg_lo, c);
1609 __ sbc(res_hi, lreg_hi, 0);
1610 break;
1611 default:
1612 ShouldNotReachHere();
1613 }
1614 }
1615 move_regs(res_lo, dest->as_register_lo());
1616
1617 } else if (dest->is_single_fpu()) {
1618 assert(left->is_single_fpu(), "must be");
1619 assert(right->is_single_fpu(), "must be");
1620 const FloatRegister res = dest->as_float_reg();
1621 const FloatRegister lreg = left->as_float_reg();
1622 const FloatRegister rreg = right->as_float_reg();
1623 switch (code) {
1624 case lir_add: __ add_float(res, lreg, rreg); break;
1625 case lir_sub: __ sub_float(res, lreg, rreg); break;
1626 case lir_mul: __ mul_float(res, lreg, rreg); break;
1627 case lir_div: __ div_float(res, lreg, rreg); break;
1628 default: ShouldNotReachHere();
1629 }
1630 } else if (dest->is_double_fpu()) {
1631 assert(left->is_double_fpu(), "must be");
1632 assert(right->is_double_fpu(), "must be");
1633 const FloatRegister res = dest->as_double_reg();
1634 const FloatRegister lreg = left->as_double_reg();
1635 const FloatRegister rreg = right->as_double_reg();
1636 switch (code) {
1637 case lir_add: __ add_double(res, lreg, rreg); break;
1638 case lir_sub: __ sub_double(res, lreg, rreg); break;
1639 case lir_mul: __ mul_double(res, lreg, rreg); break;
1640 case lir_div: __ div_double(res, lreg, rreg); break;
1641 default: ShouldNotReachHere();
1642 }
1643 } else {
1644 ShouldNotReachHere();
1645 }
1646 }
1647
1648
1649 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1650 switch (code) {
1651 case lir_abs:
1652 __ abs_double(dest->as_double_reg(), value->as_double_reg());
1653 break;
1654 case lir_sqrt:
1655 __ sqrt_double(dest->as_double_reg(), value->as_double_reg());
1656 break;
1657 default:
1658 ShouldNotReachHere();
1659 }
1660 }
1661
1662
1663 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1664 assert(dest->is_register(), "wrong items state");
1665 assert(left->is_register(), "wrong items state");
1666
1667 if (dest->is_single_cpu()) {
1668
1669 const Register res = dest->as_register();
1670 const Register lreg = left->as_register();
1671
1672 if (right->is_single_cpu()) {
1673 const Register rreg = right->as_register();
1674 switch (code) {
1675 case lir_logic_and: __ and_32(res, lreg, rreg); break;
1676 case lir_logic_or: __ orr_32(res, lreg, rreg); break;
1677 case lir_logic_xor: __ eor_32(res, lreg, rreg); break;
1678 default: ShouldNotReachHere();
1679 }
1680 } else {
1681 assert(right->is_constant(), "must be");
1682 const uint c = (uint)right->as_constant_ptr()->as_jint();
1683 if (!Assembler::is_arith_imm_in_range(c)) {
1684 BAILOUT("illegal arithmetic operand");
1685 }
1686 switch (code) {
1687 case lir_logic_and: __ and_32(res, lreg, c); break;
1688 case lir_logic_or: __ orr_32(res, lreg, c); break;
1689 case lir_logic_xor: __ eor_32(res, lreg, c); break;
1690 default: ShouldNotReachHere();
1691 }
1692 }
1693 } else {
1694 assert(dest->is_double_cpu(), "should be");
1695 Register res_lo = dest->as_register_lo();
1696
1697 assert (dest->type() == T_LONG, "unexpected result type");
1698 assert (left->type() == T_LONG, "unexpected left type");
1699 assert (right->type() == T_LONG, "unexpected right type");
1700
1701 const Register res_hi = dest->as_register_hi();
1702 const Register lreg_lo = left->as_register_lo();
1703 const Register lreg_hi = left->as_register_hi();
1704
1705 if (right->is_register()) {
1706 const Register rreg_lo = right->as_register_lo();
1707 const Register rreg_hi = right->as_register_hi();
1708 if (res_lo == lreg_hi || res_lo == rreg_hi) {
1709 res_lo = Rtemp; // Temp register helps to avoid overlap between result and input
1710 }
1711 switch (code) {
1712 case lir_logic_and:
1713 __ andr(res_lo, lreg_lo, rreg_lo);
1714 __ andr(res_hi, lreg_hi, rreg_hi);
1715 break;
1716 case lir_logic_or:
1717 __ orr(res_lo, lreg_lo, rreg_lo);
1718 __ orr(res_hi, lreg_hi, rreg_hi);
1719 break;
1720 case lir_logic_xor:
1721 __ eor(res_lo, lreg_lo, rreg_lo);
1722 __ eor(res_hi, lreg_hi, rreg_hi);
1723 break;
1724 default:
1725 ShouldNotReachHere();
1726 }
1727 move_regs(res_lo, dest->as_register_lo());
1728 } else {
1729 assert(right->is_constant(), "must be");
1730 const jint c_lo = (jint) right->as_constant_ptr()->as_jlong();
1731 const jint c_hi = (jint) (right->as_constant_ptr()->as_jlong() >> 32);
1732 // Case for logic_or from do_ClassIDIntrinsic()
1733 if (c_hi == 0 && AsmOperand::is_rotated_imm(c_lo)) {
1734 switch (code) {
1735 case lir_logic_and:
1736 __ andr(res_lo, lreg_lo, c_lo);
1737 __ mov(res_hi, 0);
1738 break;
1739 case lir_logic_or:
1740 __ orr(res_lo, lreg_lo, c_lo);
1741 break;
1742 case lir_logic_xor:
1743 __ eor(res_lo, lreg_lo, c_lo);
1744 break;
1745 default:
1746 ShouldNotReachHere();
1747 }
1748 } else if (code == lir_logic_and &&
1749 c_hi == -1 &&
1750 (AsmOperand::is_rotated_imm(c_lo) ||
1751 AsmOperand::is_rotated_imm(~c_lo))) {
1752 // Another case which handles logic_and from do_ClassIDIntrinsic()
1753 if (AsmOperand::is_rotated_imm(c_lo)) {
1754 __ andr(res_lo, lreg_lo, c_lo);
1755 } else {
1756 __ bic(res_lo, lreg_lo, ~c_lo);
1757 }
1758 if (res_hi != lreg_hi) {
1759 __ mov(res_hi, lreg_hi);
1760 }
1761 } else {
1762 BAILOUT("64 bit constant cannot be inlined");
1763 }
1764 }
1765 }
1766 }
1767
1768
1769
1770 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1771 if (opr1->is_single_cpu()) {
1772 if (opr2->is_constant()) {
1773 switch (opr2->as_constant_ptr()->type()) {
1774 case T_INT: {
1775 const jint c = opr2->as_constant_ptr()->as_jint();
1776 if (Assembler::is_arith_imm_in_range(c)) {
1777 __ cmp_32(opr1->as_register(), c);
1778 } else if (Assembler::is_arith_imm_in_range(-c)) {
1779 __ cmn_32(opr1->as_register(), -c);
1780 } else {
1781 // This can happen when compiling lookupswitch
1782 __ mov_slow(Rtemp, c);
1783 __ cmp_32(opr1->as_register(), Rtemp);
1784 }
1785 break;
1786 }
1787 case T_OBJECT:
1788 assert(opr2->as_constant_ptr()->as_jobject() == NULL, "cannot handle otherwise");
1789 __ cmp(opr1->as_register(), 0);
1790 break;
1791 case T_METADATA:
1792 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "Only equality tests");
1793 assert(opr2->as_constant_ptr()->as_metadata() == NULL, "cannot handle otherwise");
1794 __ cmp(opr1->as_register(), 0);
1795 break;
1796 default:
1797 ShouldNotReachHere();
1798 }
1799 } else if (opr2->is_single_cpu()) {
1800 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1801 assert(opr2->type() == T_OBJECT || opr2->type() == T_ARRAY, "incompatibe type");
1802 __ cmpoop(opr1->as_register(), opr2->as_register());
1803 } else if (opr1->type() == T_METADATA || opr1->type() == T_ADDRESS) {
1804 assert(opr2->type() == T_METADATA || opr2->type() == T_ADDRESS, "incompatibe type");
1805 __ cmp(opr1->as_register(), opr2->as_register());
1806 } else {
1807 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_METADATA && opr2->type() != T_ADDRESS, "incompatibe type");
1808 __ cmp_32(opr1->as_register(), opr2->as_register());
1809 }
1810 } else {
1811 ShouldNotReachHere();
1812 }
1813 } else if (opr1->is_double_cpu()) {
1814 Register xlo = opr1->as_register_lo();
1815 Register xhi = opr1->as_register_hi();
1816 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1817 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "cannot handle otherwise");
1818 __ orrs(Rtemp, xlo, xhi);
1819 } else if (opr2->is_register()) {
1820 Register ylo = opr2->as_register_lo();
1821 Register yhi = opr2->as_register_hi();
1822 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1823 __ teq(xhi, yhi);
1824 __ teq(xlo, ylo, eq);
1825 } else {
1826 __ subs(Rtemp, xlo, ylo);
1827 __ sbcs(Rtemp, xhi, yhi);
1828 }
1829 } else {
1830 ShouldNotReachHere();
1831 }
1832 } else if (opr1->is_single_fpu()) {
1833 if (opr2->is_constant()) {
1834 assert(opr2->as_jfloat() == 0.0f, "cannot handle otherwise");
1835 __ cmp_zero_float(opr1->as_float_reg());
1836 } else {
1837 __ cmp_float(opr1->as_float_reg(), opr2->as_float_reg());
1838 }
1839 } else if (opr1->is_double_fpu()) {
1840 if (opr2->is_constant()) {
1841 assert(opr2->as_jdouble() == 0.0, "cannot handle otherwise");
1842 __ cmp_zero_double(opr1->as_double_reg());
1843 } else {
1844 __ cmp_double(opr1->as_double_reg(), opr2->as_double_reg());
1845 }
1846 } else {
1847 ShouldNotReachHere();
1848 }
1849 }
1850
1851 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1852 const Register res = dst->as_register();
1853 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1854 comp_op(lir_cond_unknown, left, right, op);
1855 __ fmstat();
1856 if (code == lir_ucmp_fd2i) { // unordered is less
1857 __ mvn(res, 0, lt);
1858 __ mov(res, 1, ge);
1859 } else { // unordered is greater
1860 __ mov(res, 1, cs);
1861 __ mvn(res, 0, cc);
1862 }
1863 __ mov(res, 0, eq);
1864
1865 } else {
1866 assert(code == lir_cmp_l2i, "must be");
1867
1868 Label done;
1869 const Register xlo = left->as_register_lo();
1870 const Register xhi = left->as_register_hi();
1871 const Register ylo = right->as_register_lo();
1872 const Register yhi = right->as_register_hi();
1873 __ cmp(xhi, yhi);
1874 __ mov(res, 1, gt);
1875 __ mvn(res, 0, lt);
1876 __ b(done, ne);
1877 __ subs(res, xlo, ylo);
1878 __ mov(res, 1, hi);
1879 __ mvn(res, 0, lo);
1880 __ bind(done);
1881 }
1882 }
1883
1884
1885 void LIR_Assembler::align_call(LIR_Code code) {
1886 // Not needed
1887 }
1888
1889
1890 void LIR_Assembler::call(LIR_OpJavaCall *op, relocInfo::relocType rtype) {
1891 int ret_addr_offset = __ patchable_call(op->addr(), rtype);
1892 assert(ret_addr_offset == __ offset(), "embedded return address not allowed");
1893 add_call_info_here(op->info());
1894 }
1895
1896
1897 void LIR_Assembler::ic_call(LIR_OpJavaCall *op) {
1898 bool near_range = __ cache_fully_reachable();
1899 address oop_address = pc();
1900
1901 bool use_movw = VM_Version::supports_movw();
1902
1903 // Ricklass may contain something that is not a metadata pointer so
1904 // mov_metadata can't be used
1905 InlinedAddress value((address)Universe::non_oop_word());
1906 InlinedAddress addr(op->addr());
1907 if (use_movw) {
1908 __ movw(Ricklass, ((unsigned int)Universe::non_oop_word()) & 0xffff);
1909 __ movt(Ricklass, ((unsigned int)Universe::non_oop_word()) >> 16);
1910 } else {
1911 // No movw/movt, must be load a pc relative value but no
1912 // relocation so no metadata table to load from.
1913 // Use a b instruction rather than a bl, inline constant after the
1914 // branch, use a PC relative ldr to load the constant, arrange for
1915 // the call to return after the constant(s).
1916 __ ldr_literal(Ricklass, value);
1917 }
1918 __ relocate(virtual_call_Relocation::spec(oop_address));
1919 if (near_range && use_movw) {
1920 __ bl(op->addr());
1921 } else {
1922 Label call_return;
1923 __ adr(LR, call_return);
1924 if (near_range) {
1925 __ b(op->addr());
1926 } else {
1927 __ indirect_jump(addr, Rtemp);
1928 __ bind_literal(addr);
1929 }
1930 if (!use_movw) {
1931 __ bind_literal(value);
1932 }
1933 __ bind(call_return);
1934 }
1935 add_call_info(code_offset(), op->info());
1936 }
1937
1938 void LIR_Assembler::emit_static_call_stub() {
1939 address call_pc = __ pc();
1940 address stub = __ start_a_stub(call_stub_size());
1941 if (stub == NULL) {
1942 BAILOUT("static call stub overflow");
1943 }
1944
1945 DEBUG_ONLY(int offset = code_offset();)
1946
1947 InlinedMetadata metadata_literal(NULL);
1948 __ relocate(static_stub_Relocation::spec(call_pc));
1949 // If not a single instruction, NativeMovConstReg::next_instruction_address()
1950 // must jump over the whole following ldr_literal.
1951 // (See CompiledStaticCall::set_to_interpreted())
1952 #ifdef ASSERT
1953 address ldr_site = __ pc();
1954 #endif
1955 __ ldr_literal(Rmethod, metadata_literal);
1956 assert(nativeMovConstReg_at(ldr_site)->next_instruction_address() == __ pc(), "Fix ldr_literal or its parsing");
1957 bool near_range = __ cache_fully_reachable();
1958 InlinedAddress dest((address)-1);
1959 if (near_range) {
1960 address branch_site = __ pc();
1961 __ b(branch_site); // b to self maps to special NativeJump -1 destination
1962 } else {
1963 __ indirect_jump(dest, Rtemp);
1964 }
1965 __ bind_literal(metadata_literal); // includes spec_for_immediate reloc
1966 if (!near_range) {
1967 __ bind_literal(dest); // special NativeJump -1 destination
1968 }
1969
1970 assert(code_offset() - offset <= call_stub_size(), "overflow");
1971 __ end_a_stub();
1972 }
1973
1974 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1975 assert(exceptionOop->as_register() == Rexception_obj, "must match");
1976 assert(exceptionPC->as_register() == Rexception_pc, "must match");
1977 info->add_register_oop(exceptionOop);
1978
1979 Runtime1::StubID handle_id = compilation()->has_fpu_code() ?
1980 Runtime1::handle_exception_id :
1981 Runtime1::handle_exception_nofpu_id;
1982 Label return_address;
1983 __ adr(Rexception_pc, return_address);
1984 __ call(Runtime1::entry_for(handle_id), relocInfo::runtime_call_type);
1985 __ bind(return_address);
1986 add_call_info_here(info); // for exception handler
1987 }
1988
1989 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1990 assert(exceptionOop->as_register() == Rexception_obj, "must match");
1991 __ b(_unwind_handler_entry);
1992 }
1993
1994 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
1995 AsmShift shift = lsl;
1996 switch (code) {
1997 case lir_shl: shift = lsl; break;
1998 case lir_shr: shift = asr; break;
1999 case lir_ushr: shift = lsr; break;
2000 default: ShouldNotReachHere();
2001 }
2002
2003 if (dest->is_single_cpu()) {
2004 __ andr(Rtemp, count->as_register(), 31);
2005 __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, Rtemp));
2006 } else if (dest->is_double_cpu()) {
2007 Register dest_lo = dest->as_register_lo();
2008 Register dest_hi = dest->as_register_hi();
2009 Register src_lo = left->as_register_lo();
2010 Register src_hi = left->as_register_hi();
2011 Register Rcount = count->as_register();
2012 // Resolve possible register conflicts
2013 if (shift == lsl && dest_hi == src_lo) {
2014 dest_hi = Rtemp;
2015 } else if (shift != lsl && dest_lo == src_hi) {
2016 dest_lo = Rtemp;
2017 } else if (dest_lo == src_lo && dest_hi == src_hi) {
2018 dest_lo = Rtemp;
2019 } else if (dest_lo == Rcount || dest_hi == Rcount) {
2020 Rcount = Rtemp;
2021 }
2022 __ andr(Rcount, count->as_register(), 63);
2023 __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, Rcount);
2024 move_regs(dest_lo, dest->as_register_lo());
2025 move_regs(dest_hi, dest->as_register_hi());
2026 } else {
2027 ShouldNotReachHere();
2028 }
2029 }
2030
2031
2032 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2033 AsmShift shift = lsl;
2034 switch (code) {
2035 case lir_shl: shift = lsl; break;
2036 case lir_shr: shift = asr; break;
2037 case lir_ushr: shift = lsr; break;
2038 default: ShouldNotReachHere();
2039 }
2040
2041 if (dest->is_single_cpu()) {
2042 count &= 31;
2043 if (count != 0) {
2044 __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, count));
2045 } else {
2046 move_regs(left->as_register(), dest->as_register());
2047 }
2048 } else if (dest->is_double_cpu()) {
2049 count &= 63;
2050 if (count != 0) {
2051 Register dest_lo = dest->as_register_lo();
2052 Register dest_hi = dest->as_register_hi();
2053 Register src_lo = left->as_register_lo();
2054 Register src_hi = left->as_register_hi();
2055 // Resolve possible register conflicts
2056 if (shift == lsl && dest_hi == src_lo) {
2057 dest_hi = Rtemp;
2058 } else if (shift != lsl && dest_lo == src_hi) {
2059 dest_lo = Rtemp;
2060 }
2061 __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, count);
2062 move_regs(dest_lo, dest->as_register_lo());
2063 move_regs(dest_hi, dest->as_register_hi());
2064 } else {
2065 __ long_move(dest->as_register_lo(), dest->as_register_hi(),
2066 left->as_register_lo(), left->as_register_hi());
2067 }
2068 } else {
2069 ShouldNotReachHere();
2070 }
2071 }
2072
2073
2074 // Saves 4 given registers in reserved argument area.
2075 void LIR_Assembler::save_in_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2076 verify_reserved_argument_area_size(4);
2077 __ stmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4));
2078 }
2079
2080 // Restores 4 given registers from reserved argument area.
2081 void LIR_Assembler::restore_from_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2082 __ ldmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4), no_writeback);
2083 }
2084
2085
2086 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2087 ciArrayKlass* default_type = op->expected_type();
2088 Register src = op->src()->as_register();
2089 Register src_pos = op->src_pos()->as_register();
2090 Register dst = op->dst()->as_register();
2091 Register dst_pos = op->dst_pos()->as_register();
2092 Register length = op->length()->as_register();
2093 Register tmp = op->tmp()->as_register();
2094 Register tmp2 = Rtemp;
2095
2096 assert(src == R0 && src_pos == R1 && dst == R2 && dst_pos == R3, "code assumption");
2097
2098 CodeStub* stub = op->stub();
2099
2100 int flags = op->flags();
2101 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2102 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2103
2104 // If we don't know anything or it's an object array, just go through the generic arraycopy
2105 if (default_type == NULL) {
2106
2107 // save arguments, because they will be killed by a runtime call
2108 save_in_reserved_area(R0, R1, R2, R3);
2109
2110 // pass length argument on SP[0]
2111 __ str(length, Address(SP, -2*wordSize, pre_indexed)); // 2 words for a proper stack alignment
2112
2113 address copyfunc_addr = StubRoutines::generic_arraycopy();
2114 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2115 #ifndef PRODUCT
2116 if (PrintC1Statistics) {
2117 __ inc_counter((address)&Runtime1::_generic_arraycopystub_cnt, tmp, tmp2);
2118 }
2119 #endif // !PRODUCT
2120 // the stub is in the code cache so close enough
2121 __ call(copyfunc_addr, relocInfo::runtime_call_type);
2122
2123 __ add(SP, SP, 2*wordSize);
2124
2125 __ cbz_32(R0, *stub->continuation());
2126
2127 __ mvn_32(tmp, R0);
2128 restore_from_reserved_area(R0, R1, R2, R3); // load saved arguments in slow case only
2129 __ sub_32(length, length, tmp);
2130 __ add_32(src_pos, src_pos, tmp);
2131 __ add_32(dst_pos, dst_pos, tmp);
2132
2133 __ b(*stub->entry());
2134
2135 __ bind(*stub->continuation());
2136 return;
2137 }
2138
2139 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(),
2140 "must be true at this point");
2141 int elem_size = type2aelembytes(basic_type);
2142 int shift = exact_log2(elem_size);
2143
2144 // Check for NULL
2145 if (flags & LIR_OpArrayCopy::src_null_check) {
2146 if (flags & LIR_OpArrayCopy::dst_null_check) {
2147 __ cmp(src, 0);
2148 __ cond_cmp(dst, 0, ne); // make one instruction shorter if both checks are needed
2149 __ b(*stub->entry(), eq);
2150 } else {
2151 __ cbz(src, *stub->entry());
2152 }
2153 } else if (flags & LIR_OpArrayCopy::dst_null_check) {
2154 __ cbz(dst, *stub->entry());
2155 }
2156
2157 // If the compiler was not able to prove that exact type of the source or the destination
2158 // of the arraycopy is an array type, check at runtime if the source or the destination is
2159 // an instance type.
2160 if (flags & LIR_OpArrayCopy::type_check) {
2161 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2162 __ load_klass(tmp, dst);
2163 __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2164 __ mov_slow(tmp, Klass::_lh_neutral_value);
2165 __ cmp_32(tmp2, tmp);
2166 __ b(*stub->entry(), ge);
2167 }
2168
2169 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2170 __ load_klass(tmp, src);
2171 __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2172 __ mov_slow(tmp, Klass::_lh_neutral_value);
2173 __ cmp_32(tmp2, tmp);
2174 __ b(*stub->entry(), ge);
2175 }
2176 }
2177
2178 // Check if negative
2179 const int all_positive_checks = LIR_OpArrayCopy::src_pos_positive_check |
2180 LIR_OpArrayCopy::dst_pos_positive_check |
2181 LIR_OpArrayCopy::length_positive_check;
2182 switch (flags & all_positive_checks) {
2183 case LIR_OpArrayCopy::src_pos_positive_check:
2184 __ branch_if_negative_32(src_pos, *stub->entry());
2185 break;
2186 case LIR_OpArrayCopy::dst_pos_positive_check:
2187 __ branch_if_negative_32(dst_pos, *stub->entry());
2188 break;
2189 case LIR_OpArrayCopy::length_positive_check:
2190 __ branch_if_negative_32(length, *stub->entry());
2191 break;
2192 case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::dst_pos_positive_check:
2193 __ branch_if_any_negative_32(src_pos, dst_pos, tmp, *stub->entry());
2194 break;
2195 case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2196 __ branch_if_any_negative_32(src_pos, length, tmp, *stub->entry());
2197 break;
2198 case LIR_OpArrayCopy::dst_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2199 __ branch_if_any_negative_32(dst_pos, length, tmp, *stub->entry());
2200 break;
2201 case all_positive_checks:
2202 __ branch_if_any_negative_32(src_pos, dst_pos, length, tmp, *stub->entry());
2203 break;
2204 default:
2205 assert((flags & all_positive_checks) == 0, "the last option");
2206 }
2207
2208 // Range checks
2209 if (flags & LIR_OpArrayCopy::src_range_check) {
2210 __ ldr_s32(tmp2, Address(src, arrayOopDesc::length_offset_in_bytes()));
2211 __ add_32(tmp, src_pos, length);
2212 __ cmp_32(tmp, tmp2);
2213 __ b(*stub->entry(), hi);
2214 }
2215 if (flags & LIR_OpArrayCopy::dst_range_check) {
2216 __ ldr_s32(tmp2, Address(dst, arrayOopDesc::length_offset_in_bytes()));
2217 __ add_32(tmp, dst_pos, length);
2218 __ cmp_32(tmp, tmp2);
2219 __ b(*stub->entry(), hi);
2220 }
2221
2222 // Check if src and dst are of the same type
2223 if (flags & LIR_OpArrayCopy::type_check) {
2224 // We don't know the array types are compatible
2225 if (basic_type != T_OBJECT) {
2226 // Simple test for basic type arrays
2227 if (UseCompressedClassPointers) {
2228 // We don't need decode because we just need to compare
2229 __ ldr_u32(tmp, Address(src, oopDesc::klass_offset_in_bytes()));
2230 __ ldr_u32(tmp2, Address(dst, oopDesc::klass_offset_in_bytes()));
2231 __ cmp_32(tmp, tmp2);
2232 } else {
2233 __ load_klass(tmp, src);
2234 __ load_klass(tmp2, dst);
2235 __ cmp(tmp, tmp2);
2236 }
2237 __ b(*stub->entry(), ne);
2238 } else {
2239 // For object arrays, if src is a sub class of dst then we can
2240 // safely do the copy.
2241 Label cont, slow;
2242
2243 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2244
2245 __ load_klass(tmp, src);
2246 __ load_klass(tmp2, dst);
2247
2248 // We are at a call so all live registers are saved before we
2249 // get here
2250 assert_different_registers(tmp, tmp2, R6, altFP_7_11);
2251
2252 __ check_klass_subtype_fast_path(tmp, tmp2, R6, altFP_7_11, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2253
2254 __ mov(R6, R0);
2255 __ mov(altFP_7_11, R1);
2256 __ mov(R0, tmp);
2257 __ mov(R1, tmp2);
2258 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); // does not blow any registers except R0, LR and Rtemp
2259 __ cmp_32(R0, 0);
2260 __ mov(R0, R6);
2261 __ mov(R1, altFP_7_11);
2262
2263 if (copyfunc_addr != NULL) { // use stub if available
2264 // src is not a sub class of dst so we have to do a
2265 // per-element check.
2266
2267 __ b(cont, ne);
2268
2269 __ bind(slow);
2270
2271 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2272 if ((flags & mask) != mask) {
2273 // Check that at least both of them object arrays.
2274 assert(flags & mask, "one of the two should be known to be an object array");
2275
2276 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2277 __ load_klass(tmp, src);
2278 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2279 __ load_klass(tmp, dst);
2280 }
2281 int lh_offset = in_bytes(Klass::layout_helper_offset());
2282
2283 __ ldr_u32(tmp2, Address(tmp, lh_offset));
2284
2285 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2286 __ mov_slow(tmp, objArray_lh);
2287 __ cmp_32(tmp, tmp2);
2288 __ b(*stub->entry(), ne);
2289 }
2290
2291 save_in_reserved_area(R0, R1, R2, R3);
2292
2293 Register src_ptr = R0;
2294 Register dst_ptr = R1;
2295 Register len = R2;
2296 Register chk_off = R3;
2297 Register super_k = tmp;
2298
2299 __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2300 __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2301
2302 __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2303 __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2304 __ load_klass(tmp, dst);
2305
2306 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2307 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2308
2309 __ ldr(super_k, Address(tmp, ek_offset));
2310
2311 __ mov(len, length);
2312 __ ldr_u32(chk_off, Address(super_k, sco_offset));
2313 __ push(super_k);
2314
2315 __ call(copyfunc_addr, relocInfo::runtime_call_type);
2316
2317 #ifndef PRODUCT
2318 if (PrintC1Statistics) {
2319 Label failed;
2320 __ cbnz_32(R0, failed);
2321 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, tmp, tmp2);
2322 __ bind(failed);
2323 }
2324 #endif // PRODUCT
2325
2326 __ add(SP, SP, wordSize); // Drop super_k argument
2327
2328 __ cbz_32(R0, *stub->continuation());
2329 __ mvn_32(tmp, R0);
2330
2331 // load saved arguments in slow case only
2332 restore_from_reserved_area(R0, R1, R2, R3);
2333
2334 __ sub_32(length, length, tmp);
2335 __ add_32(src_pos, src_pos, tmp);
2336 __ add_32(dst_pos, dst_pos, tmp);
2337
2338 #ifndef PRODUCT
2339 if (PrintC1Statistics) {
2340 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, tmp, tmp2);
2341 }
2342 #endif
2343
2344 __ b(*stub->entry());
2345
2346 __ bind(cont);
2347 } else {
2348 __ b(*stub->entry(), eq);
2349 __ bind(cont);
2350 }
2351 }
2352 }
2353
2354 #ifndef PRODUCT
2355 if (PrintC1Statistics) {
2356 address counter = Runtime1::arraycopy_count_address(basic_type);
2357 __ inc_counter(counter, tmp, tmp2);
2358 }
2359 #endif // !PRODUCT
2360
2361 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2362 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2363 const char *name;
2364 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2365
2366 Register src_ptr = R0;
2367 Register dst_ptr = R1;
2368 Register len = R2;
2369
2370 __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2371 __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2372
2373 __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2374 __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2375
2376 __ mov(len, length);
2377
2378 __ call(entry, relocInfo::runtime_call_type);
2379
2380 __ bind(*stub->continuation());
2381 }
2382
2383 #ifdef ASSERT
2384 // emit run-time assertion
2385 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2386 assert(op->code() == lir_assert, "must be");
2387
2388 if (op->in_opr1()->is_valid()) {
2389 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2390 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2391 } else {
2392 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2393 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2394 }
2395
2396 Label ok;
2397 if (op->condition() != lir_cond_always) {
2398 AsmCondition acond = al;
2399 switch (op->condition()) {
2400 case lir_cond_equal: acond = eq; break;
2401 case lir_cond_notEqual: acond = ne; break;
2402 case lir_cond_less: acond = lt; break;
2403 case lir_cond_lessEqual: acond = le; break;
2404 case lir_cond_greaterEqual: acond = ge; break;
2405 case lir_cond_greater: acond = gt; break;
2406 case lir_cond_aboveEqual: acond = hs; break;
2407 case lir_cond_belowEqual: acond = ls; break;
2408 default: ShouldNotReachHere();
2409 }
2410 __ b(ok, acond);
2411 }
2412 if (op->halt()) {
2413 const char* str = __ code_string(op->msg());
2414 __ stop(str);
2415 } else {
2416 breakpoint();
2417 }
2418 __ bind(ok);
2419 }
2420 #endif // ASSERT
2421
2422 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2423 fatal("CRC32 intrinsic is not implemented on this platform");
2424 }
2425
2426 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2427 Register obj = op->obj_opr()->as_pointer_register();
2428 Register hdr = op->hdr_opr()->as_pointer_register();
2429 Register lock = op->lock_opr()->as_pointer_register();
2430
2431 if (UseHeavyMonitors) {
2432 __ b(*op->stub()->entry());
2433 } else if (op->code() == lir_lock) {
2434 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2435 int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry());
2436 if (op->info() != NULL) {
2437 add_debug_info_for_null_check(null_check_offset, op->info());
2438 }
2439 } else if (op->code() == lir_unlock) {
2440 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2441 } else {
2442 ShouldNotReachHere();
2443 }
2444 __ bind(*op->stub()->continuation());
2445 }
2446
2447 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2448 Register obj = op->obj()->as_pointer_register();
2449 Register result = op->result_opr()->as_pointer_register();
2450
2451 CodeEmitInfo* info = op->info();
2452 if (info != NULL) {
2453 add_debug_info_for_null_check_here(info);
2454 }
2455
2456 if (UseCompressedClassPointers) { // On 32 bit arm??
2457 __ ldr_u32(result, Address(obj, oopDesc::klass_offset_in_bytes()));
2458 } else {
2459 __ ldr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
2460 }
2461 }
2462
2463 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2464 ciMethod* method = op->profiled_method();
2465 int bci = op->profiled_bci();
2466 ciMethod* callee = op->profiled_callee();
2467
2468 // Update counter for all call types
2469 ciMethodData* md = method->method_data_or_null();
2470 assert(md != NULL, "Sanity");
2471 ciProfileData* data = md->bci_to_data(bci);
2472 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2473 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2474 Register mdo = op->mdo()->as_register();
2475 assert(op->tmp1()->is_register(), "tmp1 must be allocated");
2476 Register tmp1 = op->tmp1()->as_pointer_register();
2477 assert_different_registers(mdo, tmp1);
2478 __ mov_metadata(mdo, md->constant_encoding());
2479 int mdo_offset_bias = 0;
2480 int max_offset = 4096;
2481 if (md->byte_offset_of_slot(data, CounterData::count_offset()) + data->size_in_bytes() >= max_offset) {
2482 // The offset is large so bias the mdo by the base of the slot so
2483 // that the ldr can use an immediate offset to reference the slots of the data
2484 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2485 __ mov_slow(tmp1, mdo_offset_bias);
2486 __ add(mdo, mdo, tmp1);
2487 }
2488
2489 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2490 // Perform additional virtual call profiling for invokevirtual and
2491 // invokeinterface bytecodes
2492 if (op->should_profile_receiver_type()) {
2493 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2494 Register recv = op->recv()->as_register();
2495 assert_different_registers(mdo, tmp1, recv);
2496 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2497 ciKlass* known_klass = op->known_holder();
2498 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2499 // We know the type that will be seen at this call site; we can
2500 // statically update the MethodData* rather than needing to do
2501 // dynamic tests on the receiver type
2502
2503 // NOTE: we should probably put a lock around this search to
2504 // avoid collisions by concurrent compilations
2505 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2506 uint i;
2507 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2508 ciKlass* receiver = vc_data->receiver(i);
2509 if (known_klass->equals(receiver)) {
2510 Address data_addr(mdo, md->byte_offset_of_slot(data,
2511 VirtualCallData::receiver_count_offset(i)) -
2512 mdo_offset_bias);
2513 __ ldr(tmp1, data_addr);
2514 __ add(tmp1, tmp1, DataLayout::counter_increment);
2515 __ str(tmp1, data_addr);
2516 return;
2517 }
2518 }
2519
2520 // Receiver type not found in profile data; select an empty slot
2521
2522 // Note that this is less efficient than it should be because it
2523 // always does a write to the receiver part of the
2524 // VirtualCallData rather than just the first time
2525 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2526 ciKlass* receiver = vc_data->receiver(i);
2527 if (receiver == NULL) {
2528 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2529 mdo_offset_bias);
2530 __ mov_metadata(tmp1, known_klass->constant_encoding());
2531 __ str(tmp1, recv_addr);
2532 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2533 mdo_offset_bias);
2534 __ ldr(tmp1, data_addr);
2535 __ add(tmp1, tmp1, DataLayout::counter_increment);
2536 __ str(tmp1, data_addr);
2537 return;
2538 }
2539 }
2540 } else {
2541 __ load_klass(recv, recv);
2542 Label update_done;
2543 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2544 // Receiver did not match any saved receiver and there is no empty row for it.
2545 // Increment total counter to indicate polymorphic case.
2546 __ ldr(tmp1, counter_addr);
2547 __ add(tmp1, tmp1, DataLayout::counter_increment);
2548 __ str(tmp1, counter_addr);
2549
2550 __ bind(update_done);
2551 }
2552 } else {
2553 // Static call
2554 __ ldr(tmp1, counter_addr);
2555 __ add(tmp1, tmp1, DataLayout::counter_increment);
2556 __ str(tmp1, counter_addr);
2557 }
2558 }
2559
2560 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2561 fatal("Type profiling not implemented on this platform");
2562 }
2563
2564 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
2565 Unimplemented();
2566 }
2567
2568 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2569 Unimplemented();
2570 }
2571
2572
2573 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2574 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2575 __ add_slow(dst->as_pointer_register(), mon_addr.base(), mon_addr.disp());
2576 }
2577
2578
2579 void LIR_Assembler::align_backward_branch_target() {
2580 // Some ARM processors do better with 8-byte branch target alignment
2581 __ align(8);
2582 }
2583
2584
2585 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2586 // tmp must be unused
2587 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2588
2589 if (left->is_single_cpu()) {
2590 assert (dest->type() == T_INT, "unexpected result type");
2591 assert (left->type() == T_INT, "unexpected left type");
2592 __ neg_32(dest->as_register(), left->as_register());
2593 } else if (left->is_double_cpu()) {
2594 Register dest_lo = dest->as_register_lo();
2595 Register dest_hi = dest->as_register_hi();
2596 Register src_lo = left->as_register_lo();
2597 Register src_hi = left->as_register_hi();
2598 if (dest_lo == src_hi) {
2599 dest_lo = Rtemp;
2600 }
2601 __ rsbs(dest_lo, src_lo, 0);
2602 __ rsc(dest_hi, src_hi, 0);
2603 move_regs(dest_lo, dest->as_register_lo());
2604 } else if (left->is_single_fpu()) {
2605 __ neg_float(dest->as_float_reg(), left->as_float_reg());
2606 } else if (left->is_double_fpu()) {
2607 __ neg_double(dest->as_double_reg(), left->as_double_reg());
2608 } else {
2609 ShouldNotReachHere();
2610 }
2611 }
2612
2613
2614 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2615 assert(patch_code == lir_patch_none, "Patch code not supported");
2616 LIR_Address* addr = addr_opr->as_address_ptr();
2617 if (addr->index()->is_illegal()) {
2618 jint c = addr->disp();
2619 if (!Assembler::is_arith_imm_in_range(c)) {
2620 BAILOUT("illegal arithmetic operand");
2621 }
2622 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), c);
2623 } else {
2624 assert(addr->disp() == 0, "cannot handle otherwise");
2625 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(),
2626 AsmOperand(addr->index()->as_pointer_register(), lsl, addr->scale()));
2627 }
2628 }
2629
2630
2631 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2632 assert(!tmp->is_valid(), "don't need temporary");
2633 __ call(dest);
2634 if (info != NULL) {
2635 add_call_info_here(info);
2636 }
2637 }
2638
2639
2640 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2641 assert(src->is_double_cpu() && dest->is_address() ||
2642 src->is_address() && dest->is_double_cpu(),
2643 "Simple move_op is called for all other cases");
2644
2645 int null_check_offset;
2646 if (dest->is_address()) {
2647 // Store
2648 const LIR_Address* addr = dest->as_address_ptr();
2649 const Register src_lo = src->as_register_lo();
2650 const Register src_hi = src->as_register_hi();
2651 assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2652
2653 if (src_lo < src_hi) {
2654 null_check_offset = __ offset();
2655 __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(src_hi));
2656 } else {
2657 assert(src_lo < Rtemp, "Rtemp is higher than any allocatable register");
2658 __ mov(Rtemp, src_hi);
2659 null_check_offset = __ offset();
2660 __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(Rtemp));
2661 }
2662 } else {
2663 // Load
2664 const LIR_Address* addr = src->as_address_ptr();
2665 const Register dest_lo = dest->as_register_lo();
2666 const Register dest_hi = dest->as_register_hi();
2667 assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2668
2669 null_check_offset = __ offset();
2670 if (dest_lo < dest_hi) {
2671 __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(dest_hi));
2672 } else {
2673 assert(dest_lo < Rtemp, "Rtemp is higher than any allocatable register");
2674 __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(Rtemp));
2675 __ mov(dest_hi, Rtemp);
2676 }
2677 }
2678
2679 if (info != NULL) {
2680 add_debug_info_for_null_check(null_check_offset, info);
2681 }
2682 }
2683
2684
2685 void LIR_Assembler::membar() {
2686 __ membar(MacroAssembler::StoreLoad, Rtemp);
2687 }
2688
2689 void LIR_Assembler::membar_acquire() {
2690 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::LoadLoad | MacroAssembler::LoadStore), Rtemp);
2691 }
2692
2693 void LIR_Assembler::membar_release() {
2694 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2695 }
2696
2697 void LIR_Assembler::membar_loadload() {
2698 __ membar(MacroAssembler::LoadLoad, Rtemp);
2699 }
2700
2701 void LIR_Assembler::membar_storestore() {
2702 __ membar(MacroAssembler::StoreStore, Rtemp);
2703 }
2704
2705 void LIR_Assembler::membar_loadstore() {
2706 __ membar(MacroAssembler::LoadStore, Rtemp);
2707 }
2708
2709 void LIR_Assembler::membar_storeload() {
2710 __ membar(MacroAssembler::StoreLoad, Rtemp);
2711 }
2712
2713 void LIR_Assembler::on_spin_wait() {
2714 Unimplemented();
2715 }
2716
2717 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2718 // Not used on ARM
2719 Unimplemented();
2720 }
2721
2722 void LIR_Assembler::peephole(LIR_List* lir) {
2723 LIR_OpList* inst = lir->instructions_list();
2724 const int inst_length = inst->length();
2725 for (int i = 0; i < inst_length; i++) {
2726 LIR_Op* op = inst->at(i);
2727 switch (op->code()) {
2728 case lir_cmp: {
2729 // Replace:
2730 // cmp rX, y
2731 // cmove [EQ] y, z, rX
2732 // with
2733 // cmp rX, y
2734 // cmove [EQ] illegalOpr, z, rX
2735 //
2736 // or
2737 // cmp rX, y
2738 // cmove [NE] z, y, rX
2739 // with
2740 // cmp rX, y
2741 // cmove [NE] z, illegalOpr, rX
2742 //
2743 // moves from illegalOpr should be removed when converting LIR to native assembly
2744
2745 LIR_Op2* cmp = op->as_Op2();
2746 assert(cmp != NULL, "cmp LIR instruction is not an op2");
2747
2748 if (i + 1 < inst_length) {
2749 LIR_Op2* cmove = inst->at(i + 1)->as_Op2();
2750 if (cmove != NULL && cmove->code() == lir_cmove) {
2751 LIR_Opr cmove_res = cmove->result_opr();
2752 bool res_is_op1 = cmove_res == cmp->in_opr1();
2753 bool res_is_op2 = cmove_res == cmp->in_opr2();
2754 LIR_Opr cmp_res, cmp_arg;
2755 if (res_is_op1) {
2756 cmp_res = cmp->in_opr1();
2757 cmp_arg = cmp->in_opr2();
2758 } else if (res_is_op2) {
2759 cmp_res = cmp->in_opr2();
2760 cmp_arg = cmp->in_opr1();
2761 } else {
2762 cmp_res = LIR_OprFact::illegalOpr;
2763 cmp_arg = LIR_OprFact::illegalOpr;
2764 }
2765
2766 if (cmp_res != LIR_OprFact::illegalOpr) {
2767 LIR_Condition cond = cmove->condition();
2768 if (cond == lir_cond_equal && cmove->in_opr1() == cmp_arg) {
2769 cmove->set_in_opr1(LIR_OprFact::illegalOpr);
2770 } else if (cond == lir_cond_notEqual && cmove->in_opr2() == cmp_arg) {
2771 cmove->set_in_opr2(LIR_OprFact::illegalOpr);
2772 }
2773 }
2774 }
2775 }
2776 break;
2777 }
2778
2779 default:
2780 break;
2781 }
2782 }
2783 }
2784
2785 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2786 assert(src->is_address(), "sanity");
2787 Address addr = as_Address(src->as_address_ptr());
2788
2789 if (code == lir_xchg) {
2790 } else {
2791 assert (!data->is_oop(), "xadd for oops");
2792 }
2793
2794 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2795
2796 Label retry;
2797 __ bind(retry);
2798
2799 if (data->type() == T_INT || data->is_oop()) {
2800 Register dst = dest->as_register();
2801 Register new_val = noreg;
2802 __ ldrex(dst, addr);
2803 if (code == lir_xadd) {
2804 Register tmp_reg = tmp->as_register();
2805 if (data->is_constant()) {
2806 assert_different_registers(dst, tmp_reg);
2807 __ add_32(tmp_reg, dst, data->as_constant_ptr()->as_jint());
2808 } else {
2809 assert_different_registers(dst, tmp_reg, data->as_register());
2810 __ add_32(tmp_reg, dst, data->as_register());
2811 }
2812 new_val = tmp_reg;
2813 } else {
2814 if (UseCompressedOops && data->is_oop()) {
2815 new_val = tmp->as_pointer_register();
2816 } else {
2817 new_val = data->as_register();
2818 }
2819 assert_different_registers(dst, new_val);
2820 }
2821 __ strex(Rtemp, new_val, addr);
2822
2823 } else if (data->type() == T_LONG) {
2824 Register dst_lo = dest->as_register_lo();
2825 Register new_val_lo = noreg;
2826 Register dst_hi = dest->as_register_hi();
2827
2828 assert(dst_hi->encoding() == dst_lo->encoding() + 1, "non aligned register pair");
2829 assert((dst_lo->encoding() & 0x1) == 0, "misaligned register pair");
2830
2831 __ bind(retry);
2832 __ ldrexd(dst_lo, addr);
2833 if (code == lir_xadd) {
2834 Register tmp_lo = tmp->as_register_lo();
2835 Register tmp_hi = tmp->as_register_hi();
2836
2837 assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
2838 assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
2839
2840 if (data->is_constant()) {
2841 jlong c = data->as_constant_ptr()->as_jlong();
2842 assert((jlong)((jint)c) == c, "overflow");
2843 assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi);
2844 __ adds(tmp_lo, dst_lo, (jint)c);
2845 __ adc(tmp_hi, dst_hi, 0);
2846 } else {
2847 Register new_val_lo = data->as_register_lo();
2848 Register new_val_hi = data->as_register_hi();
2849 __ adds(tmp_lo, dst_lo, new_val_lo);
2850 __ adc(tmp_hi, dst_hi, new_val_hi);
2851 assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi, new_val_lo, new_val_hi);
2852 }
2853 new_val_lo = tmp_lo;
2854 } else {
2855 new_val_lo = data->as_register_lo();
2856 Register new_val_hi = data->as_register_hi();
2857
2858 assert_different_registers(dst_lo, dst_hi, new_val_lo, new_val_hi);
2859 assert(new_val_hi->encoding() == new_val_lo->encoding() + 1, "non aligned register pair");
2860 assert((new_val_lo->encoding() & 0x1) == 0, "misaligned register pair");
2861 }
2862 __ strexd(Rtemp, new_val_lo, addr);
2863 } else {
2864 ShouldNotReachHere();
2865 }
2866
2867 __ cbnz_32(Rtemp, retry);
2868 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
2869
2870 }
2871
2872 #undef __