1 /*
   2  * Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.inline.hpp"
  27 #include "c1/c1_Compilation.hpp"
  28 #include "c1/c1_LIRAssembler.hpp"
  29 #include "c1/c1_MacroAssembler.hpp"
  30 #include "c1/c1_Runtime1.hpp"
  31 #include "c1/c1_ValueStack.hpp"
  32 #include "ci/ciArrayKlass.hpp"
  33 #include "ci/ciInstance.hpp"
  34 #include "gc/shared/collectedHeap.hpp"
  35 #include "memory/universe.hpp"
  36 #include "nativeInst_arm.hpp"
  37 #include "oops/objArrayKlass.hpp"
  38 #include "runtime/frame.inline.hpp"
  39 #include "runtime/sharedRuntime.hpp"
  40 #include "runtime/stubRoutines.hpp"
  41 #include "utilities/powerOfTwo.hpp"
  42 #include "vmreg_arm.inline.hpp"
  43 
  44 #define __ _masm->
  45 
  46 // Note: Rtemp usage is this file should not impact C2 and should be
  47 // correct as long as it is not implicitly used in lower layers (the
  48 // arm [macro]assembler) and used with care in the other C1 specific
  49 // files.
  50 
  51 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
  52   ShouldNotCallThis(); // Not used on ARM
  53   return false;
  54 }
  55 
  56 
  57 LIR_Opr LIR_Assembler::receiverOpr() {
  58   // The first register in Java calling conventions
  59   return FrameMap::R0_oop_opr;
  60 }
  61 
  62 LIR_Opr LIR_Assembler::osrBufferPointer() {
  63   return FrameMap::as_pointer_opr(R0);
  64 }
  65 
  66 #ifndef PRODUCT
  67 void LIR_Assembler::verify_reserved_argument_area_size(int args_count) {
  68   assert(args_count * wordSize <= frame_map()->reserved_argument_area_size(), "not enough space for arguments");
  69 }
  70 #endif // !PRODUCT
  71 
  72 void LIR_Assembler::store_parameter(jint c, int offset_from_sp_in_words) {
  73   assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
  74   int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
  75   assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
  76   __ mov_slow(Rtemp, c);
  77   __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
  78 }
  79 
  80 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_sp_in_words) {
  81   assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
  82   int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
  83   assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
  84   __ mov_metadata(Rtemp, m);
  85   __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
  86 }
  87 
  88 //--------------fpu register translations-----------------------
  89 
  90 
  91 void LIR_Assembler::breakpoint() {
  92   __ breakpoint();
  93 }
  94 
  95 void LIR_Assembler::push(LIR_Opr opr) {
  96   Unimplemented();
  97 }
  98 
  99 void LIR_Assembler::pop(LIR_Opr opr) {
 100   Unimplemented();
 101 }
 102 
 103 //-------------------------------------------
 104 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 105   Register base = addr->base()->as_pointer_register();
 106 
 107 
 108   if (addr->index()->is_illegal() || addr->index()->is_constant()) {
 109     int offset = addr->disp();
 110     if (addr->index()->is_constant()) {
 111       offset += addr->index()->as_constant_ptr()->as_jint() << addr->scale();
 112     }
 113 
 114     if ((offset <= -4096) || (offset >= 4096)) {
 115       BAILOUT_("offset not in range", Address(base));
 116     }
 117 
 118     return Address(base, offset);
 119 
 120   } else {
 121     assert(addr->disp() == 0, "can't have both");
 122     int scale = addr->scale();
 123 
 124     assert(addr->index()->is_single_cpu(), "should be");
 125     return scale >= 0 ? Address(base, addr->index()->as_register(), lsl, scale) :
 126                         Address(base, addr->index()->as_register(), lsr, -scale);
 127   }
 128 }
 129 
 130 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 131   Address base = as_Address(addr);
 132   assert(base.index() == noreg, "must be");
 133   if (base.disp() + BytesPerWord >= 4096) { BAILOUT_("offset not in range", Address(base.base(),0)); }
 134   return Address(base.base(), base.disp() + BytesPerWord);
 135 }
 136 
 137 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 138   return as_Address(addr);
 139 }
 140 
 141 
 142 void LIR_Assembler::osr_entry() {
 143   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 144   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 145   ValueStack* entry_state = osr_entry->end()->state();
 146   int number_of_locks = entry_state->locks_size();
 147 
 148   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 149   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 150 
 151   assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 152   int monitor_offset = (method()->max_locals() + 2 * (number_of_locks - 1)) * BytesPerWord;
 153   for (int i = 0; i < number_of_locks; i++) {
 154     int slot_offset = monitor_offset - (i * 2 * BytesPerWord);
 155     __ ldr(R1, Address(OSR_buf, slot_offset + 0*BytesPerWord));
 156     __ ldr(R2, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 157     __ str(R1, frame_map()->address_for_monitor_lock(i));
 158     __ str(R2, frame_map()->address_for_monitor_object(i));
 159   }
 160 }
 161 
 162 
 163 int LIR_Assembler::check_icache() {
 164   Register receiver = LIR_Assembler::receiverOpr()->as_register();
 165   int offset = __ offset();
 166   __ inline_cache_check(receiver, Ricklass);
 167   return offset;
 168 }
 169 
 170 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 171   ShouldNotReachHere(); // not implemented
 172 }
 173 
 174 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 175   jobject o = (jobject)Universe::non_oop_word();
 176   int index = __ oop_recorder()->allocate_oop_index(o);
 177 
 178   PatchingStub* patch = new PatchingStub(_masm, patching_id(info), index);
 179 
 180   __ patchable_mov_oop(reg, o, index);
 181   patching_epilog(patch, lir_patch_normal, reg, info);
 182 }
 183 
 184 
 185 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 186   Metadata* o = (Metadata*)Universe::non_oop_word();
 187   int index = __ oop_recorder()->allocate_metadata_index(o);
 188   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
 189 
 190   __ patchable_mov_metadata(reg, o, index);
 191   patching_epilog(patch, lir_patch_normal, reg, info);
 192 }
 193 
 194 
 195 int LIR_Assembler::initial_frame_size_in_bytes() const {
 196   // Subtracts two words to account for return address and link
 197   return frame_map()->framesize()*VMRegImpl::stack_slot_size - 2*wordSize;
 198 }
 199 
 200 
 201 int LIR_Assembler::emit_exception_handler() {
 202   // TODO: ARM
 203   __ nop(); // See comments in other ports
 204 
 205   address handler_base = __ start_a_stub(exception_handler_size());
 206   if (handler_base == NULL) {
 207     bailout("exception handler overflow");
 208     return -1;
 209   }
 210 
 211   int offset = code_offset();
 212 
 213   // check that there is really an exception
 214   __ verify_not_null_oop(Rexception_obj);
 215 
 216   __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
 217   __ should_not_reach_here();
 218 
 219   assert(code_offset() - offset <= exception_handler_size(), "overflow");
 220   __ end_a_stub();
 221 
 222   return offset;
 223 }
 224 
 225 // Emit the code to remove the frame from the stack in the exception
 226 // unwind path.
 227 int LIR_Assembler::emit_unwind_handler() {
 228 #ifndef PRODUCT
 229   if (CommentedAssembly) {
 230     _masm->block_comment("Unwind handler");
 231   }
 232 #endif
 233 
 234   int offset = code_offset();
 235 
 236   // Fetch the exception from TLS and clear out exception related thread state
 237   Register zero = __ zero_register(Rtemp);
 238   __ ldr(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
 239   __ str(zero, Address(Rthread, JavaThread::exception_oop_offset()));
 240   __ str(zero, Address(Rthread, JavaThread::exception_pc_offset()));
 241 
 242   __ bind(_unwind_handler_entry);
 243   __ verify_not_null_oop(Rexception_obj);
 244 
 245   // Preform needed unlocking
 246   MonitorExitStub* stub = NULL;
 247   if (method()->is_synchronized()) {
 248     monitor_address(0, FrameMap::R0_opr);
 249     stub = new MonitorExitStub(FrameMap::R0_opr, true, 0);
 250     __ unlock_object(R2, R1, R0, *stub->entry());
 251     __ bind(*stub->continuation());
 252   }
 253 
 254   // remove the activation and dispatch to the unwind handler
 255   __ remove_frame(initial_frame_size_in_bytes()); // restores FP and LR
 256   __ jump(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type, Rtemp);
 257 
 258   // Emit the slow path assembly
 259   if (stub != NULL) {
 260     stub->emit_code(this);
 261   }
 262 
 263   return offset;
 264 }
 265 
 266 
 267 int LIR_Assembler::emit_deopt_handler() {
 268   address handler_base = __ start_a_stub(deopt_handler_size());
 269   if (handler_base == NULL) {
 270     bailout("deopt handler overflow");
 271     return -1;
 272   }
 273 
 274   int offset = code_offset();
 275 
 276   __ mov_relative_address(LR, __ pc());
 277   __ push(LR); // stub expects LR to be saved
 278   __ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, noreg);
 279 
 280   assert(code_offset() - offset <= deopt_handler_size(), "overflow");
 281   __ end_a_stub();
 282 
 283   return offset;
 284 }
 285 
 286 
 287 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
 288   // Pop the frame before safepoint polling
 289   __ remove_frame(initial_frame_size_in_bytes());
 290   __ read_polling_page(Rtemp, relocInfo::poll_return_type);
 291   __ ret();
 292 }
 293 
 294 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 295 
 296   int offset = __ offset();
 297   __ get_polling_page(Rtemp);
 298   __ relocate(relocInfo::poll_type);
 299   add_debug_info_for_branch(info); // help pc_desc_at to find correct scope for current PC
 300   __ ldr(Rtemp, Address(Rtemp));
 301 
 302   return offset;
 303 }
 304 
 305 
 306 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 307   if (from_reg != to_reg) {
 308     __ mov(to_reg, from_reg);
 309   }
 310 }
 311 
 312 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 313   assert(src->is_constant() && dest->is_register(), "must be");
 314   LIR_Const* c = src->as_constant_ptr();
 315 
 316   switch (c->type()) {
 317     case T_ADDRESS:
 318     case T_INT:
 319       assert(patch_code == lir_patch_none, "no patching handled here");
 320       __ mov_slow(dest->as_register(), c->as_jint());
 321       break;
 322 
 323     case T_LONG:
 324       assert(patch_code == lir_patch_none, "no patching handled here");
 325       __ mov_slow(dest->as_register_lo(), c->as_jint_lo());
 326       __ mov_slow(dest->as_register_hi(), c->as_jint_hi());
 327       break;
 328 
 329     case T_OBJECT:
 330       if (patch_code == lir_patch_none) {
 331         __ mov_oop(dest->as_register(), c->as_jobject());
 332       } else {
 333         jobject2reg_with_patching(dest->as_register(), info);
 334       }
 335       break;
 336 
 337     case T_METADATA:
 338       if (patch_code == lir_patch_none) {
 339         __ mov_metadata(dest->as_register(), c->as_metadata());
 340       } else {
 341         klass2reg_with_patching(dest->as_register(), info);
 342       }
 343       break;
 344 
 345     case T_FLOAT:
 346       if (dest->is_single_fpu()) {
 347         __ mov_float(dest->as_float_reg(), c->as_jfloat());
 348       } else {
 349         // Simple getters can return float constant directly into r0
 350         __ mov_slow(dest->as_register(), c->as_jint_bits());
 351       }
 352       break;
 353 
 354     case T_DOUBLE:
 355       if (dest->is_double_fpu()) {
 356         __ mov_double(dest->as_double_reg(), c->as_jdouble());
 357       } else {
 358         // Simple getters can return double constant directly into r1r0
 359         __ mov_slow(dest->as_register_lo(), c->as_jint_lo_bits());
 360         __ mov_slow(dest->as_register_hi(), c->as_jint_hi_bits());
 361       }
 362       break;
 363 
 364     default:
 365       ShouldNotReachHere();
 366   }
 367 }
 368 
 369 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 370   assert(src->is_constant(), "must be");
 371   assert(dest->is_stack(), "must be");
 372   LIR_Const* c = src->as_constant_ptr();
 373 
 374   switch (c->type()) {
 375     case T_INT:  // fall through
 376     case T_FLOAT:
 377       __ mov_slow(Rtemp, c->as_jint_bits());
 378       __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
 379       break;
 380 
 381     case T_ADDRESS:
 382       __ mov_slow(Rtemp, c->as_jint());
 383       __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
 384       break;
 385 
 386     case T_OBJECT:
 387       __ mov_oop(Rtemp, c->as_jobject());
 388       __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
 389       break;
 390 
 391     case T_LONG:  // fall through
 392     case T_DOUBLE:
 393       __ mov_slow(Rtemp, c->as_jint_lo_bits());
 394       __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
 395       if (c->as_jint_hi_bits() != c->as_jint_lo_bits()) {
 396         __ mov_slow(Rtemp, c->as_jint_hi_bits());
 397       }
 398       __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
 399       break;
 400 
 401     default:
 402       ShouldNotReachHere();
 403   }
 404 }
 405 
 406 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
 407                               CodeEmitInfo* info, bool wide) {
 408   assert((src->as_constant_ptr()->type() == T_OBJECT && src->as_constant_ptr()->as_jobject() == NULL),"cannot handle otherwise");
 409   __ mov(Rtemp, 0);
 410 
 411   int null_check_offset = code_offset();
 412   __ str(Rtemp, as_Address(dest->as_address_ptr()));
 413 
 414   if (info != NULL) {
 415     assert(false, "arm32 didn't support this before, investigate if bug");
 416     add_debug_info_for_null_check(null_check_offset, info);
 417   }
 418 }
 419 
 420 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 421   assert(src->is_register() && dest->is_register(), "must be");
 422 
 423   if (src->is_single_cpu()) {
 424     if (dest->is_single_cpu()) {
 425       move_regs(src->as_register(), dest->as_register());
 426     } else if (dest->is_single_fpu()) {
 427       __ fmsr(dest->as_float_reg(), src->as_register());
 428     } else {
 429       ShouldNotReachHere();
 430     }
 431   } else if (src->is_double_cpu()) {
 432     if (dest->is_double_cpu()) {
 433       __ long_move(dest->as_register_lo(), dest->as_register_hi(), src->as_register_lo(), src->as_register_hi());
 434     } else {
 435       __ fmdrr(dest->as_double_reg(), src->as_register_lo(), src->as_register_hi());
 436     }
 437   } else if (src->is_single_fpu()) {
 438     if (dest->is_single_fpu()) {
 439       __ mov_float(dest->as_float_reg(), src->as_float_reg());
 440     } else if (dest->is_single_cpu()) {
 441       __ mov_fpr2gpr_float(dest->as_register(), src->as_float_reg());
 442     } else {
 443       ShouldNotReachHere();
 444     }
 445   } else if (src->is_double_fpu()) {
 446     if (dest->is_double_fpu()) {
 447       __ mov_double(dest->as_double_reg(), src->as_double_reg());
 448     } else if (dest->is_double_cpu()) {
 449       __ fmrrd(dest->as_register_lo(), dest->as_register_hi(), src->as_double_reg());
 450     } else {
 451       ShouldNotReachHere();
 452     }
 453   } else {
 454     ShouldNotReachHere();
 455   }
 456 }
 457 
 458 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 459   assert(src->is_register(), "should not call otherwise");
 460   assert(dest->is_stack(), "should not call otherwise");
 461 
 462   Address addr = dest->is_single_word() ?
 463     frame_map()->address_for_slot(dest->single_stack_ix()) :
 464     frame_map()->address_for_slot(dest->double_stack_ix());
 465 
 466   assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
 467   if (src->is_single_fpu() || src->is_double_fpu()) {
 468     if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
 469   }
 470 
 471   if (src->is_single_cpu()) {
 472     switch (type) {
 473       case T_OBJECT:
 474       case T_ARRAY:    __ verify_oop(src->as_register());   // fall through
 475       case T_ADDRESS:
 476       case T_METADATA: __ str(src->as_register(), addr);    break;
 477       case T_FLOAT:    // used in intBitsToFloat intrinsic implementation, fall through
 478       case T_INT:      __ str_32(src->as_register(), addr); break;
 479       default:
 480         ShouldNotReachHere();
 481     }
 482   } else if (src->is_double_cpu()) {
 483     __ str(src->as_register_lo(), addr);
 484     __ str(src->as_register_hi(), frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
 485   } else if (src->is_single_fpu()) {
 486     __ str_float(src->as_float_reg(), addr);
 487   } else if (src->is_double_fpu()) {
 488     __ str_double(src->as_double_reg(), addr);
 489   } else {
 490     ShouldNotReachHere();
 491   }
 492 }
 493 
 494 
 495 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
 496                             LIR_PatchCode patch_code, CodeEmitInfo* info,
 497                             bool pop_fpu_stack, bool wide) {
 498   LIR_Address* to_addr = dest->as_address_ptr();
 499   Register base_reg = to_addr->base()->as_pointer_register();
 500   const bool needs_patching = (patch_code != lir_patch_none);
 501 
 502   PatchingStub* patch = NULL;
 503   if (needs_patching) {
 504     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 505   }
 506 
 507   int null_check_offset = code_offset();
 508 
 509   switch (type) {
 510     case T_ARRAY:
 511     case T_OBJECT:
 512       if (UseCompressedOops && !wide) {
 513         ShouldNotReachHere();
 514       } else {
 515         __ str(src->as_register(), as_Address(to_addr));
 516       }
 517       break;
 518 
 519     case T_ADDRESS:
 520       __ str(src->as_pointer_register(), as_Address(to_addr));
 521       break;
 522 
 523     case T_BYTE:
 524     case T_BOOLEAN:
 525       __ strb(src->as_register(), as_Address(to_addr));
 526       break;
 527 
 528     case T_CHAR:
 529     case T_SHORT:
 530       __ strh(src->as_register(), as_Address(to_addr));
 531       break;
 532 
 533     case T_INT:
 534 #ifdef __SOFTFP__
 535     case T_FLOAT:
 536 #endif // __SOFTFP__
 537       __ str_32(src->as_register(), as_Address(to_addr));
 538       break;
 539 
 540 
 541 #ifdef __SOFTFP__
 542     case T_DOUBLE:
 543 #endif // __SOFTFP__
 544     case T_LONG: {
 545       Register from_lo = src->as_register_lo();
 546       Register from_hi = src->as_register_hi();
 547       if (to_addr->index()->is_register()) {
 548         assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
 549         assert(to_addr->disp() == 0, "Not yet supporting both");
 550         __ add(Rtemp, base_reg, to_addr->index()->as_register());
 551         base_reg = Rtemp;
 552         __ str(from_lo, Address(Rtemp));
 553         if (patch != NULL) {
 554           __ nop(); // see comment before patching_epilog for 2nd str
 555           patching_epilog(patch, lir_patch_low, base_reg, info);
 556           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 557           patch_code = lir_patch_high;
 558         }
 559         __ str(from_hi, Address(Rtemp, BytesPerWord));
 560       } else if (base_reg == from_lo) {
 561         __ str(from_hi, as_Address_hi(to_addr));
 562         if (patch != NULL) {
 563           __ nop(); // see comment before patching_epilog for 2nd str
 564           patching_epilog(patch, lir_patch_high, base_reg, info);
 565           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 566           patch_code = lir_patch_low;
 567         }
 568         __ str(from_lo, as_Address_lo(to_addr));
 569       } else {
 570         __ str(from_lo, as_Address_lo(to_addr));
 571         if (patch != NULL) {
 572           __ nop(); // see comment before patching_epilog for 2nd str
 573           patching_epilog(patch, lir_patch_low, base_reg, info);
 574           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 575           patch_code = lir_patch_high;
 576         }
 577         __ str(from_hi, as_Address_hi(to_addr));
 578       }
 579       break;
 580     }
 581 
 582 #ifndef __SOFTFP__
 583     case T_FLOAT:
 584       if (to_addr->index()->is_register()) {
 585         assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
 586         __ add(Rtemp, base_reg, to_addr->index()->as_register());
 587         if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
 588         __ fsts(src->as_float_reg(), Address(Rtemp, to_addr->disp()));
 589       } else {
 590         __ fsts(src->as_float_reg(), as_Address(to_addr));
 591       }
 592       break;
 593 
 594     case T_DOUBLE:
 595       if (to_addr->index()->is_register()) {
 596         assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
 597         __ add(Rtemp, base_reg, to_addr->index()->as_register());
 598         if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
 599         __ fstd(src->as_double_reg(), Address(Rtemp, to_addr->disp()));
 600       } else {
 601         __ fstd(src->as_double_reg(), as_Address(to_addr));
 602       }
 603       break;
 604 #endif // __SOFTFP__
 605 
 606 
 607     default:
 608       ShouldNotReachHere();
 609   }
 610 
 611   if (info != NULL) {
 612     add_debug_info_for_null_check(null_check_offset, info);
 613   }
 614 
 615   if (patch != NULL) {
 616     // Offset embedded into LDR/STR instruction may appear not enough
 617     // to address a field. So, provide a space for one more instruction
 618     // that will deal with larger offsets.
 619     __ nop();
 620     patching_epilog(patch, patch_code, base_reg, info);
 621   }
 622 }
 623 
 624 
 625 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
 626   assert(src->is_stack(), "should not call otherwise");
 627   assert(dest->is_register(), "should not call otherwise");
 628 
 629   Address addr = src->is_single_word() ?
 630     frame_map()->address_for_slot(src->single_stack_ix()) :
 631     frame_map()->address_for_slot(src->double_stack_ix());
 632 
 633   assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
 634   if (dest->is_single_fpu() || dest->is_double_fpu()) {
 635     if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
 636   }
 637 
 638   if (dest->is_single_cpu()) {
 639     switch (type) {
 640       case T_OBJECT:
 641       case T_ARRAY:
 642       case T_ADDRESS:
 643       case T_METADATA: __ ldr(dest->as_register(), addr); break;
 644       case T_FLOAT:    // used in floatToRawIntBits intrinsic implemenation
 645       case T_INT:      __ ldr_u32(dest->as_register(), addr); break;
 646       default:
 647         ShouldNotReachHere();
 648     }
 649     if ((type == T_OBJECT) || (type == T_ARRAY)) {
 650       __ verify_oop(dest->as_register());
 651     }
 652   } else if (dest->is_double_cpu()) {
 653     __ ldr(dest->as_register_lo(), addr);
 654     __ ldr(dest->as_register_hi(), frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
 655   } else if (dest->is_single_fpu()) {
 656     __ ldr_float(dest->as_float_reg(), addr);
 657   } else if (dest->is_double_fpu()) {
 658     __ ldr_double(dest->as_double_reg(), addr);
 659   } else {
 660     ShouldNotReachHere();
 661   }
 662 }
 663 
 664 
 665 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 666   if (src->is_single_stack()) {
 667     switch (src->type()) {
 668       case T_OBJECT:
 669       case T_ARRAY:
 670       case T_ADDRESS:
 671       case T_METADATA:
 672         __ ldr(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
 673         __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
 674         break;
 675 
 676       case T_INT:
 677       case T_FLOAT:
 678         __ ldr_u32(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
 679         __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
 680         break;
 681 
 682       default:
 683         ShouldNotReachHere();
 684     }
 685   } else {
 686     assert(src->is_double_stack(), "must be");
 687     __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes));
 688     __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
 689     __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
 690     __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
 691   }
 692 }
 693 
 694 
 695 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
 696                             LIR_PatchCode patch_code, CodeEmitInfo* info,
 697                             bool wide) {
 698   assert(src->is_address(), "should not call otherwise");
 699   assert(dest->is_register(), "should not call otherwise");
 700   LIR_Address* addr = src->as_address_ptr();
 701 
 702   Register base_reg = addr->base()->as_pointer_register();
 703 
 704   PatchingStub* patch = NULL;
 705   if (patch_code != lir_patch_none) {
 706     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 707   }
 708   if (info != NULL) {
 709     add_debug_info_for_null_check_here(info);
 710   }
 711 
 712   switch (type) {
 713     case T_OBJECT:  // fall through
 714     case T_ARRAY:
 715       if (UseCompressedOops && !wide) {
 716         __ ldr_u32(dest->as_register(), as_Address(addr));
 717       } else {
 718         __ ldr(dest->as_register(), as_Address(addr));
 719       }
 720       break;
 721 
 722     case T_ADDRESS:
 723       if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
 724         __ ldr_u32(dest->as_pointer_register(), as_Address(addr));
 725       } else {
 726         __ ldr(dest->as_pointer_register(), as_Address(addr));
 727       }
 728       break;
 729 
 730     case T_INT:
 731 #ifdef __SOFTFP__
 732     case T_FLOAT:
 733 #endif // __SOFTFP__
 734       __ ldr(dest->as_pointer_register(), as_Address(addr));
 735       break;
 736 
 737     case T_BOOLEAN:
 738       __ ldrb(dest->as_register(), as_Address(addr));
 739       break;
 740 
 741     case T_BYTE:
 742       __ ldrsb(dest->as_register(), as_Address(addr));
 743       break;
 744 
 745     case T_CHAR:
 746       __ ldrh(dest->as_register(), as_Address(addr));
 747       break;
 748 
 749     case T_SHORT:
 750       __ ldrsh(dest->as_register(), as_Address(addr));
 751       break;
 752 
 753 
 754 #ifdef __SOFTFP__
 755     case T_DOUBLE:
 756 #endif // __SOFTFP__
 757     case T_LONG: {
 758       Register to_lo = dest->as_register_lo();
 759       Register to_hi = dest->as_register_hi();
 760       if (addr->index()->is_register()) {
 761         assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
 762         assert(addr->disp() == 0, "Not yet supporting both");
 763         __ add(Rtemp, base_reg, addr->index()->as_register());
 764         base_reg = Rtemp;
 765         __ ldr(to_lo, Address(Rtemp));
 766         if (patch != NULL) {
 767           __ nop(); // see comment before patching_epilog for 2nd ldr
 768           patching_epilog(patch, lir_patch_low, base_reg, info);
 769           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 770           patch_code = lir_patch_high;
 771         }
 772         __ ldr(to_hi, Address(Rtemp, BytesPerWord));
 773       } else if (base_reg == to_lo) {
 774         __ ldr(to_hi, as_Address_hi(addr));
 775         if (patch != NULL) {
 776           __ nop(); // see comment before patching_epilog for 2nd ldr
 777           patching_epilog(patch, lir_patch_high, base_reg, info);
 778           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 779           patch_code = lir_patch_low;
 780         }
 781         __ ldr(to_lo, as_Address_lo(addr));
 782       } else {
 783         __ ldr(to_lo, as_Address_lo(addr));
 784         if (patch != NULL) {
 785           __ nop(); // see comment before patching_epilog for 2nd ldr
 786           patching_epilog(patch, lir_patch_low, base_reg, info);
 787           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 788           patch_code = lir_patch_high;
 789         }
 790         __ ldr(to_hi, as_Address_hi(addr));
 791       }
 792       break;
 793     }
 794 
 795 #ifndef __SOFTFP__
 796     case T_FLOAT:
 797       if (addr->index()->is_register()) {
 798         assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
 799         __ add(Rtemp, base_reg, addr->index()->as_register());
 800         if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
 801         __ flds(dest->as_float_reg(), Address(Rtemp, addr->disp()));
 802       } else {
 803         __ flds(dest->as_float_reg(), as_Address(addr));
 804       }
 805       break;
 806 
 807     case T_DOUBLE:
 808       if (addr->index()->is_register()) {
 809         assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
 810         __ add(Rtemp, base_reg, addr->index()->as_register());
 811         if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
 812         __ fldd(dest->as_double_reg(), Address(Rtemp, addr->disp()));
 813       } else {
 814         __ fldd(dest->as_double_reg(), as_Address(addr));
 815       }
 816       break;
 817 #endif // __SOFTFP__
 818 
 819 
 820     default:
 821       ShouldNotReachHere();
 822   }
 823 
 824   if (patch != NULL) {
 825     // Offset embedded into LDR/STR instruction may appear not enough
 826     // to address a field. So, provide a space for one more instruction
 827     // that will deal with larger offsets.
 828     __ nop();
 829     patching_epilog(patch, patch_code, base_reg, info);
 830   }
 831 
 832 }
 833 
 834 
 835 void LIR_Assembler::emit_op3(LIR_Op3* op) {
 836   bool is_32 = op->result_opr()->is_single_cpu();
 837 
 838   if (op->code() == lir_idiv && op->in_opr2()->is_constant() && is_32) {
 839     int c = op->in_opr2()->as_constant_ptr()->as_jint();
 840     assert(is_power_of_2(c), "non power-of-2 constant should be put in a register");
 841 
 842     Register left = op->in_opr1()->as_register();
 843     Register dest = op->result_opr()->as_register();
 844     if (c == 1) {
 845       __ mov(dest, left);
 846     } else if (c == 2) {
 847       __ add_32(dest, left, AsmOperand(left, lsr, 31));
 848       __ asr_32(dest, dest, 1);
 849     } else if (c != (int) 0x80000000) {
 850       int power = log2i_exact(c);
 851       __ asr_32(Rtemp, left, 31);
 852       __ add_32(dest, left, AsmOperand(Rtemp, lsr, 32-power)); // dest = left + (left < 0 ? 2^power - 1 : 0);
 853       __ asr_32(dest, dest, power);                            // dest = dest >>> power;
 854     } else {
 855       // x/0x80000000 is a special case, since dividend is a power of two, but is negative.
 856       // The only possible result values are 0 and 1, with 1 only for dividend == divisor == 0x80000000.
 857       __ cmp_32(left, c);
 858       __ mov(dest, 0, ne);
 859       __ mov(dest, 1, eq);
 860     }
 861   } else {
 862     assert(op->code() == lir_idiv || op->code() == lir_irem, "unexpected op3");
 863     __ call(StubRoutines::Arm::idiv_irem_entry(), relocInfo::runtime_call_type);
 864     add_debug_info_for_div0_here(op->info());
 865   }
 866 }
 867 
 868 
 869 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
 870 #ifdef ASSERT
 871   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
 872   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
 873   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
 874   assert(op->info() == NULL, "CodeEmitInfo?");
 875 #endif // ASSERT
 876 
 877 #ifdef __SOFTFP__
 878   assert (op->code() != lir_cond_float_branch, "this should be impossible");
 879 #else
 880   if (op->code() == lir_cond_float_branch) {
 881     __ fmstat();
 882     __ b(*(op->ublock()->label()), vs);
 883   }
 884 #endif // __SOFTFP__
 885 
 886   AsmCondition acond = al;
 887   switch (op->cond()) {
 888     case lir_cond_equal:        acond = eq; break;
 889     case lir_cond_notEqual:     acond = ne; break;
 890     case lir_cond_less:         acond = lt; break;
 891     case lir_cond_lessEqual:    acond = le; break;
 892     case lir_cond_greaterEqual: acond = ge; break;
 893     case lir_cond_greater:      acond = gt; break;
 894     case lir_cond_aboveEqual:   acond = hs; break;
 895     case lir_cond_belowEqual:   acond = ls; break;
 896     default: assert(op->cond() == lir_cond_always, "must be");
 897   }
 898   __ b(*(op->label()), acond);
 899 }
 900 
 901 
 902 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
 903   LIR_Opr src  = op->in_opr();
 904   LIR_Opr dest = op->result_opr();
 905 
 906   switch (op->bytecode()) {
 907     case Bytecodes::_i2l:
 908       move_regs(src->as_register(), dest->as_register_lo());
 909       __ mov(dest->as_register_hi(), AsmOperand(src->as_register(), asr, 31));
 910       break;
 911     case Bytecodes::_l2i:
 912       move_regs(src->as_register_lo(), dest->as_register());
 913       break;
 914     case Bytecodes::_i2b:
 915       __ sign_extend(dest->as_register(), src->as_register(), 8);
 916       break;
 917     case Bytecodes::_i2s:
 918       __ sign_extend(dest->as_register(), src->as_register(), 16);
 919       break;
 920     case Bytecodes::_i2c:
 921       __ zero_extend(dest->as_register(), src->as_register(), 16);
 922       break;
 923     case Bytecodes::_f2d:
 924       __ convert_f2d(dest->as_double_reg(), src->as_float_reg());
 925       break;
 926     case Bytecodes::_d2f:
 927       __ convert_d2f(dest->as_float_reg(), src->as_double_reg());
 928       break;
 929     case Bytecodes::_i2f:
 930       __ fmsr(Stemp, src->as_register());
 931       __ fsitos(dest->as_float_reg(), Stemp);
 932       break;
 933     case Bytecodes::_i2d:
 934       __ fmsr(Stemp, src->as_register());
 935       __ fsitod(dest->as_double_reg(), Stemp);
 936       break;
 937     case Bytecodes::_f2i:
 938       __ ftosizs(Stemp, src->as_float_reg());
 939       __ fmrs(dest->as_register(), Stemp);
 940       break;
 941     case Bytecodes::_d2i:
 942       __ ftosizd(Stemp, src->as_double_reg());
 943       __ fmrs(dest->as_register(), Stemp);
 944       break;
 945     default:
 946       ShouldNotReachHere();
 947   }
 948 }
 949 
 950 
 951 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
 952   if (op->init_check()) {
 953     Register tmp = op->tmp1()->as_register();
 954     __ ldrb(tmp, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
 955     add_debug_info_for_null_check_here(op->stub()->info());
 956     __ cmp(tmp, InstanceKlass::fully_initialized);
 957     __ b(*op->stub()->entry(), ne);
 958   }
 959   __ allocate_object(op->obj()->as_register(),
 960                      op->tmp1()->as_register(),
 961                      op->tmp2()->as_register(),
 962                      op->tmp3()->as_register(),
 963                      op->header_size(),
 964                      op->object_size(),
 965                      op->klass()->as_register(),
 966                      *op->stub()->entry());
 967   __ bind(*op->stub()->continuation());
 968 }
 969 
 970 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
 971   if (UseSlowPath ||
 972       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
 973       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
 974     __ b(*op->stub()->entry());
 975   } else {
 976     __ allocate_array(op->obj()->as_register(),
 977                       op->len()->as_register(),
 978                       op->tmp1()->as_register(),
 979                       op->tmp2()->as_register(),
 980                       op->tmp3()->as_register(),
 981                       arrayOopDesc::header_size(op->type()),
 982                       type2aelembytes(op->type()),
 983                       op->klass()->as_register(),
 984                       *op->stub()->entry());
 985   }
 986   __ bind(*op->stub()->continuation());
 987 }
 988 
 989 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
 990                                         ciMethodData *md, ciProfileData *data,
 991                                         Register recv, Register tmp1, Label* update_done) {
 992   assert_different_registers(mdo, recv, tmp1);
 993   uint i;
 994   for (i = 0; i < VirtualCallData::row_limit(); i++) {
 995     Label next_test;
 996     // See if the receiver is receiver[n].
 997     Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
 998                           mdo_offset_bias);
 999     __ ldr(tmp1, receiver_addr);
1000     __ verify_klass_ptr(tmp1);
1001     __ cmp(recv, tmp1);
1002     __ b(next_test, ne);
1003     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1004                       mdo_offset_bias);
1005     __ ldr(tmp1, data_addr);
1006     __ add(tmp1, tmp1, DataLayout::counter_increment);
1007     __ str(tmp1, data_addr);
1008     __ b(*update_done);
1009     __ bind(next_test);
1010   }
1011 
1012   // Didn't find receiver; find next empty slot and fill it in
1013   for (i = 0; i < VirtualCallData::row_limit(); i++) {
1014     Label next_test;
1015     Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
1016                       mdo_offset_bias);
1017     __ ldr(tmp1, recv_addr);
1018     __ cbnz(tmp1, next_test);
1019     __ str(recv, recv_addr);
1020     __ mov(tmp1, DataLayout::counter_increment);
1021     __ str(tmp1, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1022                          mdo_offset_bias));
1023     __ b(*update_done);
1024     __ bind(next_test);
1025   }
1026 }
1027 
1028 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
1029                                     ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
1030   md = method->method_data_or_null();
1031   assert(md != NULL, "Sanity");
1032   data = md->bci_to_data(bci);
1033   assert(data != NULL,       "need data for checkcast");
1034   assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1035   if (md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes() >= 4096) {
1036     // The offset is large so bias the mdo by the base of the slot so
1037     // that the ldr can use an immediate offset to reference the slots of the data
1038     mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
1039   }
1040 }
1041 
1042 // On 32-bit ARM, code before this helper should test obj for null (ZF should be set if obj is null).
1043 void LIR_Assembler::typecheck_profile_helper1(ciMethod* method, int bci,
1044                                               ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias,
1045                                               Register obj, Register mdo, Register data_val, Label* obj_is_null) {
1046   assert(method != NULL, "Should have method");
1047   assert_different_registers(obj, mdo, data_val);
1048   setup_md_access(method, bci, md, data, mdo_offset_bias);
1049   Label not_null;
1050   __ b(not_null, ne);
1051   __ mov_metadata(mdo, md->constant_encoding());
1052   if (mdo_offset_bias > 0) {
1053     __ mov_slow(data_val, mdo_offset_bias);
1054     __ add(mdo, mdo, data_val);
1055   }
1056   Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
1057   __ ldrb(data_val, flags_addr);
1058   __ orr(data_val, data_val, (uint)BitData::null_seen_byte_constant());
1059   __ strb(data_val, flags_addr);
1060   __ b(*obj_is_null);
1061   __ bind(not_null);
1062 }
1063 
1064 void LIR_Assembler::typecheck_profile_helper2(ciMethodData* md, ciProfileData* data, int mdo_offset_bias,
1065                                               Register mdo, Register recv, Register value, Register tmp1,
1066                                               Label* profile_cast_success, Label* profile_cast_failure,
1067                                               Label* success, Label* failure) {
1068   assert_different_registers(mdo, value, tmp1);
1069   __ bind(*profile_cast_success);
1070   __ mov_metadata(mdo, md->constant_encoding());
1071   if (mdo_offset_bias > 0) {
1072     __ mov_slow(tmp1, mdo_offset_bias);
1073     __ add(mdo, mdo, tmp1);
1074   }
1075   __ load_klass(recv, value);
1076   type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
1077   __ b(*success);
1078   // Cast failure case
1079   __ bind(*profile_cast_failure);
1080   __ mov_metadata(mdo, md->constant_encoding());
1081   if (mdo_offset_bias > 0) {
1082     __ mov_slow(tmp1, mdo_offset_bias);
1083     __ add(mdo, mdo, tmp1);
1084   }
1085   Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
1086   __ ldr(tmp1, data_addr);
1087   __ sub(tmp1, tmp1, DataLayout::counter_increment);
1088   __ str(tmp1, data_addr);
1089   __ b(*failure);
1090 }
1091 
1092 // Sets `res` to true, if `cond` holds.
1093 static void set_instanceof_result(MacroAssembler* _masm, Register res, AsmCondition cond) {
1094   __ mov(res, 1, cond);
1095 }
1096 
1097 
1098 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1099   // TODO: ARM - can be more effective with one more register
1100   switch (op->code()) {
1101     case lir_store_check: {
1102       CodeStub* stub = op->stub();
1103       Register value = op->object()->as_register();
1104       Register array = op->array()->as_register();
1105       Register klass_RInfo = op->tmp1()->as_register();
1106       Register k_RInfo = op->tmp2()->as_register();
1107       assert_different_registers(klass_RInfo, k_RInfo, Rtemp);
1108       if (op->should_profile()) {
1109         assert_different_registers(value, klass_RInfo, k_RInfo, Rtemp);
1110       }
1111 
1112       // check if it needs to be profiled
1113       ciMethodData* md;
1114       ciProfileData* data;
1115       int mdo_offset_bias = 0;
1116       Label profile_cast_success, profile_cast_failure, done;
1117       Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1118       Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1119 
1120       if (op->should_profile()) {
1121         __ cmp(value, 0);
1122         typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, value, k_RInfo, Rtemp, &done);
1123       } else {
1124         __ cbz(value, done);
1125       }
1126       assert_different_registers(k_RInfo, value);
1127       add_debug_info_for_null_check_here(op->info_for_exception());
1128       __ load_klass(k_RInfo, array);
1129       __ load_klass(klass_RInfo, value);
1130       __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1131       __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1132       // check for immediate positive hit
1133       __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1134       __ cmp(klass_RInfo, k_RInfo);
1135       __ cond_cmp(Rtemp, k_RInfo, ne);
1136       __ b(*success_target, eq);
1137       // check for immediate negative hit
1138       __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1139       __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1140       __ b(*failure_target, ne);
1141       // slow case
1142       assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1143       __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1144       __ cbz(R0, *failure_target);
1145       if (op->should_profile()) {
1146         Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1147         if (mdo == value) {
1148           mdo = k_RInfo;
1149           recv = klass_RInfo;
1150         }
1151         typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, value, tmp1,
1152                                   &profile_cast_success, &profile_cast_failure,
1153                                   &done, stub->entry());
1154       }
1155       __ bind(done);
1156       break;
1157     }
1158 
1159     case lir_checkcast: {
1160       CodeStub* stub = op->stub();
1161       Register obj = op->object()->as_register();
1162       Register res = op->result_opr()->as_register();
1163       Register klass_RInfo = op->tmp1()->as_register();
1164       Register k_RInfo = op->tmp2()->as_register();
1165       ciKlass* k = op->klass();
1166       assert_different_registers(res, k_RInfo, klass_RInfo, Rtemp);
1167 
1168       if (stub->is_simple_exception_stub()) {
1169       // TODO: ARM - Late binding is used to prevent confusion of register allocator
1170       assert(stub->is_exception_throw_stub(), "must be");
1171       ((SimpleExceptionStub*)stub)->set_obj(op->result_opr());
1172       }
1173       ciMethodData* md;
1174       ciProfileData* data;
1175       int mdo_offset_bias = 0;
1176 
1177       Label done;
1178 
1179       Label profile_cast_failure, profile_cast_success;
1180       Label *failure_target = op->should_profile() ? &profile_cast_failure : op->stub()->entry();
1181       Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1182 
1183 
1184       __ movs(res, obj);
1185       if (op->should_profile()) {
1186         typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1187       } else {
1188         __ b(done, eq);
1189       }
1190       if (k->is_loaded()) {
1191         __ mov_metadata(k_RInfo, k->constant_encoding());
1192       } else if (k_RInfo != obj) {
1193         klass2reg_with_patching(k_RInfo, op->info_for_patch());
1194         __ movs(res, obj);
1195       } else {
1196         // Patching doesn't update "res" register after GC, so do patching first
1197         klass2reg_with_patching(Rtemp, op->info_for_patch());
1198         __ movs(res, obj);
1199         __ mov(k_RInfo, Rtemp);
1200       }
1201       __ load_klass(klass_RInfo, res, ne);
1202 
1203       if (op->fast_check()) {
1204         __ cmp(klass_RInfo, k_RInfo, ne);
1205         __ b(*failure_target, ne);
1206       } else if (k->is_loaded()) {
1207         __ b(*success_target, eq);
1208         __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1209         if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1210           __ cmp(Rtemp, k_RInfo);
1211           __ b(*failure_target, ne);
1212         } else {
1213           __ cmp(klass_RInfo, k_RInfo);
1214           __ cmp(Rtemp, k_RInfo, ne);
1215           __ b(*success_target, eq);
1216           assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1217           __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1218           __ cbz(R0, *failure_target);
1219         }
1220       } else {
1221         __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1222         __ b(*success_target, eq);
1223         // check for immediate positive hit
1224         __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1225         __ cmp(klass_RInfo, k_RInfo);
1226         __ cmp(Rtemp, k_RInfo, ne);
1227         __ b(*success_target, eq);
1228         // check for immediate negative hit
1229         __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1230         __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1231         __ b(*failure_target, ne);
1232         // slow case
1233         assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1234         __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1235         __ cbz(R0, *failure_target);
1236       }
1237 
1238       if (op->should_profile()) {
1239         Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1240         typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1241                                   &profile_cast_success, &profile_cast_failure,
1242                                   &done, stub->entry());
1243       }
1244       __ bind(done);
1245       break;
1246     }
1247 
1248     case lir_instanceof: {
1249       Register obj = op->object()->as_register();
1250       Register res = op->result_opr()->as_register();
1251       Register klass_RInfo = op->tmp1()->as_register();
1252       Register k_RInfo = op->tmp2()->as_register();
1253       ciKlass* k = op->klass();
1254       assert_different_registers(res, klass_RInfo, k_RInfo, Rtemp);
1255 
1256       ciMethodData* md;
1257       ciProfileData* data;
1258       int mdo_offset_bias = 0;
1259 
1260       Label done;
1261 
1262       Label profile_cast_failure, profile_cast_success;
1263       Label *failure_target = op->should_profile() ? &profile_cast_failure : &done;
1264       Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1265 
1266       __ movs(res, obj);
1267 
1268       if (op->should_profile()) {
1269         typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1270       } else {
1271         __ b(done, eq);
1272       }
1273 
1274       if (k->is_loaded()) {
1275         __ mov_metadata(k_RInfo, k->constant_encoding());
1276       } else {
1277         op->info_for_patch()->add_register_oop(FrameMap::as_oop_opr(res));
1278         klass2reg_with_patching(k_RInfo, op->info_for_patch());
1279       }
1280       __ load_klass(klass_RInfo, res);
1281 
1282       if (!op->should_profile()) {
1283         __ mov(res, 0);
1284       }
1285 
1286       if (op->fast_check()) {
1287         __ cmp(klass_RInfo, k_RInfo);
1288         if (!op->should_profile()) {
1289           set_instanceof_result(_masm, res, eq);
1290         } else {
1291           __ b(profile_cast_failure, ne);
1292         }
1293       } else if (k->is_loaded()) {
1294         __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1295         if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1296           __ cmp(Rtemp, k_RInfo);
1297           if (!op->should_profile()) {
1298             set_instanceof_result(_masm, res, eq);
1299           } else {
1300             __ b(profile_cast_failure, ne);
1301           }
1302         } else {
1303           __ cmp(klass_RInfo, k_RInfo);
1304           __ cond_cmp(Rtemp, k_RInfo, ne);
1305           if (!op->should_profile()) {
1306             set_instanceof_result(_masm, res, eq);
1307           }
1308           __ b(*success_target, eq);
1309           assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1310           __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1311           if (!op->should_profile()) {
1312             move_regs(R0, res);
1313           } else {
1314             __ cbz(R0, *failure_target);
1315           }
1316         }
1317       } else {
1318         __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1319         // check for immediate positive hit
1320         __ cmp(klass_RInfo, k_RInfo);
1321         if (!op->should_profile()) {
1322           __ ldr(res, Address(klass_RInfo, Rtemp), ne);
1323           __ cond_cmp(res, k_RInfo, ne);
1324           set_instanceof_result(_masm, res, eq);
1325         } else {
1326           __ ldr(Rtemp, Address(klass_RInfo, Rtemp), ne);
1327           __ cond_cmp(Rtemp, k_RInfo, ne);
1328         }
1329         __ b(*success_target, eq);
1330         // check for immediate negative hit
1331         if (op->should_profile()) {
1332           __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1333         }
1334         __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1335         if (!op->should_profile()) {
1336           __ mov(res, 0, ne);
1337         }
1338         __ b(*failure_target, ne);
1339         // slow case
1340         assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1341         __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1342         if (!op->should_profile()) {
1343           move_regs(R0, res);
1344         }
1345         if (op->should_profile()) {
1346           __ cbz(R0, *failure_target);
1347         }
1348       }
1349 
1350       if (op->should_profile()) {
1351         Label done_ok, done_failure;
1352         Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1353         typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1354                                   &profile_cast_success, &profile_cast_failure,
1355                                   &done_ok, &done_failure);
1356         __ bind(done_failure);
1357         __ mov(res, 0);
1358         __ b(done);
1359         __ bind(done_ok);
1360         __ mov(res, 1);
1361       }
1362       __ bind(done);
1363       break;
1364     }
1365     default:
1366       ShouldNotReachHere();
1367   }
1368 }
1369 
1370 
1371 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1372   //   if (*addr == cmpval) {
1373   //     *addr = newval;
1374   //     dest = 1;
1375   //   } else {
1376   //     dest = 0;
1377   //   }
1378   // FIXME: membar_release
1379   __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
1380   Register addr = op->addr()->is_register() ?
1381     op->addr()->as_pointer_register() :
1382     op->addr()->as_address_ptr()->base()->as_pointer_register();
1383   assert(op->addr()->is_register() || op->addr()->as_address_ptr()->disp() == 0, "unexpected disp");
1384   assert(op->addr()->is_register() || op->addr()->as_address_ptr()->index() == LIR_OprDesc::illegalOpr(), "unexpected index");
1385   if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
1386     Register cmpval = op->cmp_value()->as_register();
1387     Register newval = op->new_value()->as_register();
1388     Register dest = op->result_opr()->as_register();
1389     assert_different_registers(dest, addr, cmpval, newval, Rtemp);
1390 
1391     __ atomic_cas_bool(cmpval, newval, addr, 0, Rtemp); // Rtemp free by default at C1 LIR layer
1392     __ mov(dest, 1, eq);
1393     __ mov(dest, 0, ne);
1394   } else if (op->code() == lir_cas_long) {
1395     assert(VM_Version::supports_cx8(), "wrong machine");
1396     Register cmp_value_lo = op->cmp_value()->as_register_lo();
1397     Register cmp_value_hi = op->cmp_value()->as_register_hi();
1398     Register new_value_lo = op->new_value()->as_register_lo();
1399     Register new_value_hi = op->new_value()->as_register_hi();
1400     Register dest = op->result_opr()->as_register();
1401     Register tmp_lo = op->tmp1()->as_register_lo();
1402     Register tmp_hi = op->tmp1()->as_register_hi();
1403 
1404     assert_different_registers(tmp_lo, tmp_hi, cmp_value_lo, cmp_value_hi, dest, new_value_lo, new_value_hi, addr);
1405     assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
1406     assert(new_value_hi->encoding() == new_value_lo->encoding() + 1, "non aligned register pair");
1407     assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
1408     assert((new_value_lo->encoding() & 0x1) == 0, "misaligned register pair");
1409     __ atomic_cas64(tmp_lo, tmp_hi, dest, cmp_value_lo, cmp_value_hi,
1410                     new_value_lo, new_value_hi, addr, 0);
1411   } else {
1412     Unimplemented();
1413   }
1414   // FIXME: is full membar really needed instead of just membar_acquire?
1415   __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
1416 }
1417 
1418 
1419 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1420   AsmCondition acond = al;
1421   AsmCondition ncond = nv;
1422   if (opr1 != opr2) {
1423     switch (condition) {
1424       case lir_cond_equal:        acond = eq; ncond = ne; break;
1425       case lir_cond_notEqual:     acond = ne; ncond = eq; break;
1426       case lir_cond_less:         acond = lt; ncond = ge; break;
1427       case lir_cond_lessEqual:    acond = le; ncond = gt; break;
1428       case lir_cond_greaterEqual: acond = ge; ncond = lt; break;
1429       case lir_cond_greater:      acond = gt; ncond = le; break;
1430       case lir_cond_aboveEqual:   acond = hs; ncond = lo; break;
1431       case lir_cond_belowEqual:   acond = ls; ncond = hi; break;
1432       default: ShouldNotReachHere();
1433     }
1434   }
1435 
1436   for (;;) {                         // two iterations only
1437     if (opr1 == result) {
1438       // do nothing
1439     } else if (opr1->is_single_cpu()) {
1440       __ mov(result->as_register(), opr1->as_register(), acond);
1441     } else if (opr1->is_double_cpu()) {
1442       __ long_move(result->as_register_lo(), result->as_register_hi(),
1443                    opr1->as_register_lo(), opr1->as_register_hi(), acond);
1444     } else if (opr1->is_single_stack()) {
1445       __ ldr(result->as_register(), frame_map()->address_for_slot(opr1->single_stack_ix()), acond);
1446     } else if (opr1->is_double_stack()) {
1447       __ ldr(result->as_register_lo(),
1448              frame_map()->address_for_slot(opr1->double_stack_ix(), lo_word_offset_in_bytes), acond);
1449       __ ldr(result->as_register_hi(),
1450              frame_map()->address_for_slot(opr1->double_stack_ix(), hi_word_offset_in_bytes), acond);
1451     } else if (opr1->is_illegal()) {
1452       // do nothing: this part of the cmove has been optimized away in the peephole optimizer
1453     } else {
1454       assert(opr1->is_constant(), "must be");
1455       LIR_Const* c = opr1->as_constant_ptr();
1456 
1457       switch (c->type()) {
1458         case T_INT:
1459           __ mov_slow(result->as_register(), c->as_jint(), acond);
1460           break;
1461         case T_LONG:
1462           __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1463           __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1464           break;
1465         case T_OBJECT:
1466           __ mov_oop(result->as_register(), c->as_jobject(), 0, acond);
1467           break;
1468         case T_FLOAT:
1469 #ifdef __SOFTFP__
1470           // not generated now.
1471           __ mov_slow(result->as_register(), c->as_jint(), acond);
1472 #else
1473           __ mov_float(result->as_float_reg(), c->as_jfloat(), acond);
1474 #endif // __SOFTFP__
1475           break;
1476         case T_DOUBLE:
1477 #ifdef __SOFTFP__
1478           // not generated now.
1479           __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1480           __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1481 #else
1482           __ mov_double(result->as_double_reg(), c->as_jdouble(), acond);
1483 #endif // __SOFTFP__
1484           break;
1485         default:
1486           ShouldNotReachHere();
1487       }
1488     }
1489 
1490     // Negate the condition and repeat the algorithm with the second operand
1491     if (opr1 == opr2) { break; }
1492     opr1 = opr2;
1493     acond = ncond;
1494   }
1495 }
1496 
1497 #ifdef ASSERT
1498 static int reg_size(LIR_Opr op) {
1499   switch (op->type()) {
1500   case T_FLOAT:
1501   case T_INT:      return BytesPerInt;
1502   case T_LONG:
1503   case T_DOUBLE:   return BytesPerLong;
1504   case T_OBJECT:
1505   case T_ARRAY:
1506   case T_METADATA: return BytesPerWord;
1507   case T_ADDRESS:
1508   case T_ILLEGAL:  // fall through
1509   default: ShouldNotReachHere(); return -1;
1510   }
1511 }
1512 #endif
1513 
1514 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1515   assert(info == NULL, "unused on this code path");
1516   assert(dest->is_register(), "wrong items state");
1517 
1518   if (right->is_address()) {
1519     // special case for adding shifted/extended register
1520     const Register res = dest->as_pointer_register();
1521     const Register lreg = left->as_pointer_register();
1522     const LIR_Address* addr = right->as_address_ptr();
1523 
1524     assert(addr->base()->as_pointer_register() == lreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1525 
1526     int scale = addr->scale();
1527     AsmShift shift = lsl;
1528 
1529 
1530     assert(reg_size(addr->base()) == reg_size(addr->index()), "should be");
1531     assert(reg_size(addr->base()) == reg_size(dest), "should be");
1532     assert(reg_size(dest) == wordSize, "should be");
1533 
1534     AsmOperand operand(addr->index()->as_pointer_register(), shift, scale);
1535     switch (code) {
1536       case lir_add: __ add(res, lreg, operand); break;
1537       case lir_sub: __ sub(res, lreg, operand); break;
1538       default: ShouldNotReachHere();
1539     }
1540 
1541   } else if (left->is_address()) {
1542     assert(code == lir_sub && right->is_single_cpu(), "special case used by strength_reduce_multiply()");
1543     const LIR_Address* addr = left->as_address_ptr();
1544     const Register res = dest->as_register();
1545     const Register rreg = right->as_register();
1546     assert(addr->base()->as_register() == rreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1547     __ rsb(res, rreg, AsmOperand(addr->index()->as_register(), lsl, addr->scale()));
1548 
1549   } else if (dest->is_single_cpu()) {
1550     assert(left->is_single_cpu(), "unexpected left operand");
1551 
1552     const Register res = dest->as_register();
1553     const Register lreg = left->as_register();
1554 
1555     if (right->is_single_cpu()) {
1556       const Register rreg = right->as_register();
1557       switch (code) {
1558         case lir_add: __ add_32(res, lreg, rreg); break;
1559         case lir_sub: __ sub_32(res, lreg, rreg); break;
1560         case lir_mul: __ mul_32(res, lreg, rreg); break;
1561         default: ShouldNotReachHere();
1562       }
1563     } else {
1564       assert(right->is_constant(), "must be");
1565       const jint c = right->as_constant_ptr()->as_jint();
1566       if (!Assembler::is_arith_imm_in_range(c)) {
1567         BAILOUT("illegal arithmetic operand");
1568       }
1569       switch (code) {
1570         case lir_add: __ add_32(res, lreg, c); break;
1571         case lir_sub: __ sub_32(res, lreg, c); break;
1572         default: ShouldNotReachHere();
1573       }
1574     }
1575 
1576   } else if (dest->is_double_cpu()) {
1577     Register res_lo = dest->as_register_lo();
1578     Register res_hi = dest->as_register_hi();
1579     Register lreg_lo = left->as_register_lo();
1580     Register lreg_hi = left->as_register_hi();
1581     if (right->is_double_cpu()) {
1582       Register rreg_lo = right->as_register_lo();
1583       Register rreg_hi = right->as_register_hi();
1584       if (res_lo == lreg_hi || res_lo == rreg_hi) {
1585         res_lo = Rtemp;
1586       }
1587       switch (code) {
1588         case lir_add:
1589           __ adds(res_lo, lreg_lo, rreg_lo);
1590           __ adc(res_hi, lreg_hi, rreg_hi);
1591           break;
1592         case lir_sub:
1593           __ subs(res_lo, lreg_lo, rreg_lo);
1594           __ sbc(res_hi, lreg_hi, rreg_hi);
1595           break;
1596         default:
1597           ShouldNotReachHere();
1598       }
1599     } else {
1600       assert(right->is_constant(), "must be");
1601       assert((right->as_constant_ptr()->as_jlong() >> 32) == 0, "out of range");
1602       const jint c = (jint) right->as_constant_ptr()->as_jlong();
1603       if (res_lo == lreg_hi) {
1604         res_lo = Rtemp;
1605       }
1606       switch (code) {
1607         case lir_add:
1608           __ adds(res_lo, lreg_lo, c);
1609           __ adc(res_hi, lreg_hi, 0);
1610           break;
1611         case lir_sub:
1612           __ subs(res_lo, lreg_lo, c);
1613           __ sbc(res_hi, lreg_hi, 0);
1614           break;
1615         default:
1616           ShouldNotReachHere();
1617       }
1618     }
1619     move_regs(res_lo, dest->as_register_lo());
1620 
1621   } else if (dest->is_single_fpu()) {
1622     assert(left->is_single_fpu(), "must be");
1623     assert(right->is_single_fpu(), "must be");
1624     const FloatRegister res = dest->as_float_reg();
1625     const FloatRegister lreg = left->as_float_reg();
1626     const FloatRegister rreg = right->as_float_reg();
1627     switch (code) {
1628       case lir_add: __ add_float(res, lreg, rreg); break;
1629       case lir_sub: __ sub_float(res, lreg, rreg); break;
1630       case lir_mul: __ mul_float(res, lreg, rreg); break;
1631       case lir_div: __ div_float(res, lreg, rreg); break;
1632       default: ShouldNotReachHere();
1633     }
1634   } else if (dest->is_double_fpu()) {
1635     assert(left->is_double_fpu(), "must be");
1636     assert(right->is_double_fpu(), "must be");
1637     const FloatRegister res = dest->as_double_reg();
1638     const FloatRegister lreg = left->as_double_reg();
1639     const FloatRegister rreg = right->as_double_reg();
1640     switch (code) {
1641       case lir_add: __ add_double(res, lreg, rreg); break;
1642       case lir_sub: __ sub_double(res, lreg, rreg); break;
1643       case lir_mul: __ mul_double(res, lreg, rreg); break;
1644       case lir_div: __ div_double(res, lreg, rreg); break;
1645       default: ShouldNotReachHere();
1646     }
1647   } else {
1648     ShouldNotReachHere();
1649   }
1650 }
1651 
1652 
1653 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1654   switch (code) {
1655     case lir_abs:
1656       __ abs_double(dest->as_double_reg(), value->as_double_reg());
1657       break;
1658     case lir_sqrt:
1659       __ sqrt_double(dest->as_double_reg(), value->as_double_reg());
1660       break;
1661     default:
1662       ShouldNotReachHere();
1663   }
1664 }
1665 
1666 
1667 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1668   assert(dest->is_register(), "wrong items state");
1669   assert(left->is_register(), "wrong items state");
1670 
1671   if (dest->is_single_cpu()) {
1672 
1673     const Register res = dest->as_register();
1674     const Register lreg = left->as_register();
1675 
1676     if (right->is_single_cpu()) {
1677       const Register rreg = right->as_register();
1678       switch (code) {
1679         case lir_logic_and: __ and_32(res, lreg, rreg); break;
1680         case lir_logic_or:  __ orr_32(res, lreg, rreg); break;
1681         case lir_logic_xor: __ eor_32(res, lreg, rreg); break;
1682         default: ShouldNotReachHere();
1683       }
1684     } else {
1685       assert(right->is_constant(), "must be");
1686       const uint c = (uint)right->as_constant_ptr()->as_jint();
1687       switch (code) {
1688         case lir_logic_and: __ and_32(res, lreg, c); break;
1689         case lir_logic_or:  __ orr_32(res, lreg, c); break;
1690         case lir_logic_xor: __ eor_32(res, lreg, c); break;
1691         default: ShouldNotReachHere();
1692       }
1693     }
1694   } else {
1695     assert(dest->is_double_cpu(), "should be");
1696     Register res_lo = dest->as_register_lo();
1697 
1698     assert (dest->type() == T_LONG, "unexpected result type");
1699     assert (left->type() == T_LONG, "unexpected left type");
1700     assert (right->type() == T_LONG, "unexpected right type");
1701 
1702     const Register res_hi = dest->as_register_hi();
1703     const Register lreg_lo = left->as_register_lo();
1704     const Register lreg_hi = left->as_register_hi();
1705 
1706     if (right->is_register()) {
1707       const Register rreg_lo = right->as_register_lo();
1708       const Register rreg_hi = right->as_register_hi();
1709       if (res_lo == lreg_hi || res_lo == rreg_hi) {
1710         res_lo = Rtemp; // Temp register helps to avoid overlap between result and input
1711       }
1712       switch (code) {
1713         case lir_logic_and:
1714           __ andr(res_lo, lreg_lo, rreg_lo);
1715           __ andr(res_hi, lreg_hi, rreg_hi);
1716           break;
1717         case lir_logic_or:
1718           __ orr(res_lo, lreg_lo, rreg_lo);
1719           __ orr(res_hi, lreg_hi, rreg_hi);
1720           break;
1721         case lir_logic_xor:
1722           __ eor(res_lo, lreg_lo, rreg_lo);
1723           __ eor(res_hi, lreg_hi, rreg_hi);
1724           break;
1725         default:
1726           ShouldNotReachHere();
1727       }
1728       move_regs(res_lo, dest->as_register_lo());
1729     } else {
1730       assert(right->is_constant(), "must be");
1731       const jint c_lo = (jint) right->as_constant_ptr()->as_jlong();
1732       const jint c_hi = (jint) (right->as_constant_ptr()->as_jlong() >> 32);
1733       // Case for logic_or from do_ClassIDIntrinsic()
1734       if (c_hi == 0 && AsmOperand::is_rotated_imm(c_lo)) {
1735         switch (code) {
1736           case lir_logic_and:
1737             __ andr(res_lo, lreg_lo, c_lo);
1738             __ mov(res_hi, 0);
1739             break;
1740           case lir_logic_or:
1741             __ orr(res_lo, lreg_lo, c_lo);
1742             break;
1743           case lir_logic_xor:
1744             __ eor(res_lo, lreg_lo, c_lo);
1745             break;
1746         default:
1747           ShouldNotReachHere();
1748         }
1749       } else if (code == lir_logic_and &&
1750                  c_hi == -1 &&
1751                  (AsmOperand::is_rotated_imm(c_lo) ||
1752                   AsmOperand::is_rotated_imm(~c_lo))) {
1753         // Another case which handles logic_and from do_ClassIDIntrinsic()
1754         if (AsmOperand::is_rotated_imm(c_lo)) {
1755           __ andr(res_lo, lreg_lo, c_lo);
1756         } else {
1757           __ bic(res_lo, lreg_lo, ~c_lo);
1758         }
1759         if (res_hi != lreg_hi) {
1760           __ mov(res_hi, lreg_hi);
1761         }
1762       } else {
1763         BAILOUT("64 bit constant cannot be inlined");
1764       }
1765     }
1766   }
1767 }
1768 
1769 
1770 
1771 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1772   if (opr1->is_single_cpu()) {
1773     if (opr2->is_constant()) {
1774       switch (opr2->as_constant_ptr()->type()) {
1775         case T_INT: {
1776           const jint c = opr2->as_constant_ptr()->as_jint();
1777           if (Assembler::is_arith_imm_in_range(c)) {
1778             __ cmp_32(opr1->as_register(), c);
1779           } else if (Assembler::is_arith_imm_in_range(-c)) {
1780             __ cmn_32(opr1->as_register(), -c);
1781           } else {
1782             // This can happen when compiling lookupswitch
1783             __ mov_slow(Rtemp, c);
1784             __ cmp_32(opr1->as_register(), Rtemp);
1785           }
1786           break;
1787         }
1788         case T_OBJECT:
1789           assert(opr2->as_constant_ptr()->as_jobject() == NULL, "cannot handle otherwise");
1790           __ cmp(opr1->as_register(), 0);
1791           break;
1792         case T_METADATA:
1793           assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "Only equality tests");
1794           assert(opr2->as_constant_ptr()->as_metadata() == NULL, "cannot handle otherwise");
1795           __ cmp(opr1->as_register(), 0);
1796           break;
1797         default:
1798           ShouldNotReachHere();
1799       }
1800     } else if (opr2->is_single_cpu()) {
1801       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1802         assert(opr2->type() == T_OBJECT || opr2->type() == T_ARRAY, "incompatibe type");
1803         __ cmpoop(opr1->as_register(), opr2->as_register());
1804       } else if (opr1->type() == T_METADATA || opr1->type() == T_ADDRESS) {
1805         assert(opr2->type() == T_METADATA || opr2->type() == T_ADDRESS, "incompatibe type");
1806         __ cmp(opr1->as_register(), opr2->as_register());
1807       } else {
1808         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_METADATA && opr2->type() != T_ADDRESS, "incompatibe type");
1809         __ cmp_32(opr1->as_register(), opr2->as_register());
1810       }
1811     } else {
1812       ShouldNotReachHere();
1813     }
1814   } else if (opr1->is_double_cpu()) {
1815     Register xlo = opr1->as_register_lo();
1816     Register xhi = opr1->as_register_hi();
1817     if (opr2->is_constant() && opr2->as_jlong() == 0) {
1818       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "cannot handle otherwise");
1819       __ orrs(Rtemp, xlo, xhi);
1820     } else if (opr2->is_register()) {
1821       Register ylo = opr2->as_register_lo();
1822       Register yhi = opr2->as_register_hi();
1823       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1824         __ teq(xhi, yhi);
1825         __ teq(xlo, ylo, eq);
1826       } else {
1827         __ subs(xlo, xlo, ylo);
1828         __ sbcs(xhi, xhi, yhi);
1829       }
1830     } else {
1831       ShouldNotReachHere();
1832     }
1833   } else if (opr1->is_single_fpu()) {
1834     if (opr2->is_constant()) {
1835       assert(opr2->as_jfloat() == 0.0f, "cannot handle otherwise");
1836       __ cmp_zero_float(opr1->as_float_reg());
1837     } else {
1838       __ cmp_float(opr1->as_float_reg(), opr2->as_float_reg());
1839     }
1840   } else if (opr1->is_double_fpu()) {
1841     if (opr2->is_constant()) {
1842       assert(opr2->as_jdouble() == 0.0, "cannot handle otherwise");
1843       __ cmp_zero_double(opr1->as_double_reg());
1844     } else {
1845       __ cmp_double(opr1->as_double_reg(), opr2->as_double_reg());
1846     }
1847   } else {
1848     ShouldNotReachHere();
1849   }
1850 }
1851 
1852 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1853   const Register res = dst->as_register();
1854   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1855     comp_op(lir_cond_unknown, left, right, op);
1856     __ fmstat();
1857     if (code == lir_ucmp_fd2i) {  // unordered is less
1858       __ mvn(res, 0, lt);
1859       __ mov(res, 1, ge);
1860     } else {                      // unordered is greater
1861       __ mov(res, 1, cs);
1862       __ mvn(res, 0, cc);
1863     }
1864     __ mov(res, 0, eq);
1865 
1866   } else {
1867     assert(code == lir_cmp_l2i, "must be");
1868 
1869     Label done;
1870     const Register xlo = left->as_register_lo();
1871     const Register xhi = left->as_register_hi();
1872     const Register ylo = right->as_register_lo();
1873     const Register yhi = right->as_register_hi();
1874     __ cmp(xhi, yhi);
1875     __ mov(res, 1, gt);
1876     __ mvn(res, 0, lt);
1877     __ b(done, ne);
1878     __ subs(res, xlo, ylo);
1879     __ mov(res, 1, hi);
1880     __ mvn(res, 0, lo);
1881     __ bind(done);
1882   }
1883 }
1884 
1885 
1886 void LIR_Assembler::align_call(LIR_Code code) {
1887   // Not needed
1888 }
1889 
1890 
1891 void LIR_Assembler::call(LIR_OpJavaCall *op, relocInfo::relocType rtype) {
1892   int ret_addr_offset = __ patchable_call(op->addr(), rtype);
1893   assert(ret_addr_offset == __ offset(), "embedded return address not allowed");
1894   add_call_info_here(op->info());
1895 }
1896 
1897 
1898 void LIR_Assembler::ic_call(LIR_OpJavaCall *op) {
1899   bool near_range = __ cache_fully_reachable();
1900   address oop_address = pc();
1901 
1902   bool use_movw = VM_Version::supports_movw();
1903 
1904   // Ricklass may contain something that is not a metadata pointer so
1905   // mov_metadata can't be used
1906   InlinedAddress value((address)Universe::non_oop_word());
1907   InlinedAddress addr(op->addr());
1908   if (use_movw) {
1909     __ movw(Ricklass, ((unsigned int)Universe::non_oop_word()) & 0xffff);
1910     __ movt(Ricklass, ((unsigned int)Universe::non_oop_word()) >> 16);
1911   } else {
1912     // No movw/movt, must be load a pc relative value but no
1913     // relocation so no metadata table to load from.
1914     // Use a b instruction rather than a bl, inline constant after the
1915     // branch, use a PC relative ldr to load the constant, arrange for
1916     // the call to return after the constant(s).
1917     __ ldr_literal(Ricklass, value);
1918   }
1919   __ relocate(virtual_call_Relocation::spec(oop_address));
1920   if (near_range && use_movw) {
1921     __ bl(op->addr());
1922   } else {
1923     Label call_return;
1924     __ adr(LR, call_return);
1925     if (near_range) {
1926       __ b(op->addr());
1927     } else {
1928       __ indirect_jump(addr, Rtemp);
1929       __ bind_literal(addr);
1930     }
1931     if (!use_movw) {
1932       __ bind_literal(value);
1933     }
1934     __ bind(call_return);
1935   }
1936   add_call_info(code_offset(), op->info());
1937 }
1938 
1939 void LIR_Assembler::emit_static_call_stub() {
1940   address call_pc = __ pc();
1941   address stub = __ start_a_stub(call_stub_size());
1942   if (stub == NULL) {
1943     BAILOUT("static call stub overflow");
1944   }
1945 
1946   DEBUG_ONLY(int offset = code_offset();)
1947 
1948   InlinedMetadata metadata_literal(NULL);
1949   __ relocate(static_stub_Relocation::spec(call_pc));
1950   // If not a single instruction, NativeMovConstReg::next_instruction_address()
1951   // must jump over the whole following ldr_literal.
1952   // (See CompiledStaticCall::set_to_interpreted())
1953 #ifdef ASSERT
1954   address ldr_site = __ pc();
1955 #endif
1956   __ ldr_literal(Rmethod, metadata_literal);
1957   assert(nativeMovConstReg_at(ldr_site)->next_instruction_address() == __ pc(), "Fix ldr_literal or its parsing");
1958   bool near_range = __ cache_fully_reachable();
1959   InlinedAddress dest((address)-1);
1960   if (near_range) {
1961     address branch_site = __ pc();
1962     __ b(branch_site); // b to self maps to special NativeJump -1 destination
1963   } else {
1964     __ indirect_jump(dest, Rtemp);
1965   }
1966   __ bind_literal(metadata_literal); // includes spec_for_immediate reloc
1967   if (!near_range) {
1968     __ bind_literal(dest); // special NativeJump -1 destination
1969   }
1970 
1971   assert(code_offset() - offset <= call_stub_size(), "overflow");
1972   __ end_a_stub();
1973 }
1974 
1975 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1976   assert(exceptionOop->as_register() == Rexception_obj, "must match");
1977   assert(exceptionPC->as_register()  == Rexception_pc, "must match");
1978   info->add_register_oop(exceptionOop);
1979 
1980   Runtime1::StubID handle_id = compilation()->has_fpu_code() ?
1981                                Runtime1::handle_exception_id :
1982                                Runtime1::handle_exception_nofpu_id;
1983   Label return_address;
1984   __ adr(Rexception_pc, return_address);
1985   __ call(Runtime1::entry_for(handle_id), relocInfo::runtime_call_type);
1986   __ bind(return_address);
1987   add_call_info_here(info);  // for exception handler
1988 }
1989 
1990 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1991   assert(exceptionOop->as_register() == Rexception_obj, "must match");
1992   __ b(_unwind_handler_entry);
1993 }
1994 
1995 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
1996   AsmShift shift = lsl;
1997   switch (code) {
1998     case lir_shl:  shift = lsl; break;
1999     case lir_shr:  shift = asr; break;
2000     case lir_ushr: shift = lsr; break;
2001     default: ShouldNotReachHere();
2002   }
2003 
2004   if (dest->is_single_cpu()) {
2005     __ andr(Rtemp, count->as_register(), 31);
2006     __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, Rtemp));
2007   } else if (dest->is_double_cpu()) {
2008     Register dest_lo = dest->as_register_lo();
2009     Register dest_hi = dest->as_register_hi();
2010     Register src_lo  = left->as_register_lo();
2011     Register src_hi  = left->as_register_hi();
2012     Register Rcount  = count->as_register();
2013     // Resolve possible register conflicts
2014     if (shift == lsl && dest_hi == src_lo) {
2015       dest_hi = Rtemp;
2016     } else if (shift != lsl && dest_lo == src_hi) {
2017       dest_lo = Rtemp;
2018     } else if (dest_lo == src_lo && dest_hi == src_hi) {
2019       dest_lo = Rtemp;
2020     } else if (dest_lo == Rcount || dest_hi == Rcount) {
2021       Rcount = Rtemp;
2022     }
2023     __ andr(Rcount, count->as_register(), 63);
2024     __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, Rcount);
2025     move_regs(dest_lo, dest->as_register_lo());
2026     move_regs(dest_hi, dest->as_register_hi());
2027   } else {
2028     ShouldNotReachHere();
2029   }
2030 }
2031 
2032 
2033 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2034   AsmShift shift = lsl;
2035   switch (code) {
2036     case lir_shl:  shift = lsl; break;
2037     case lir_shr:  shift = asr; break;
2038     case lir_ushr: shift = lsr; break;
2039     default: ShouldNotReachHere();
2040   }
2041 
2042   if (dest->is_single_cpu()) {
2043     count &= 31;
2044     if (count != 0) {
2045       __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, count));
2046     } else {
2047       move_regs(left->as_register(), dest->as_register());
2048     }
2049   } else if (dest->is_double_cpu()) {
2050     count &= 63;
2051     if (count != 0) {
2052       Register dest_lo = dest->as_register_lo();
2053       Register dest_hi = dest->as_register_hi();
2054       Register src_lo  = left->as_register_lo();
2055       Register src_hi  = left->as_register_hi();
2056       // Resolve possible register conflicts
2057       if (shift == lsl && dest_hi == src_lo) {
2058         dest_hi = Rtemp;
2059       } else if (shift != lsl && dest_lo == src_hi) {
2060         dest_lo = Rtemp;
2061       }
2062       __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, count);
2063       move_regs(dest_lo, dest->as_register_lo());
2064       move_regs(dest_hi, dest->as_register_hi());
2065     } else {
2066       __ long_move(dest->as_register_lo(), dest->as_register_hi(),
2067                    left->as_register_lo(), left->as_register_hi());
2068     }
2069   } else {
2070     ShouldNotReachHere();
2071   }
2072 }
2073 
2074 
2075 // Saves 4 given registers in reserved argument area.
2076 void LIR_Assembler::save_in_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2077   verify_reserved_argument_area_size(4);
2078   __ stmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4));
2079 }
2080 
2081 // Restores 4 given registers from reserved argument area.
2082 void LIR_Assembler::restore_from_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2083   __ ldmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4), no_writeback);
2084 }
2085 
2086 
2087 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2088   ciArrayKlass* default_type = op->expected_type();
2089   Register src = op->src()->as_register();
2090   Register src_pos = op->src_pos()->as_register();
2091   Register dst = op->dst()->as_register();
2092   Register dst_pos = op->dst_pos()->as_register();
2093   Register length  = op->length()->as_register();
2094   Register tmp = op->tmp()->as_register();
2095   Register tmp2 = Rtemp;
2096 
2097   assert(src == R0 && src_pos == R1 && dst == R2 && dst_pos == R3, "code assumption");
2098 
2099   CodeStub* stub = op->stub();
2100 
2101   int flags = op->flags();
2102   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2103   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2104 
2105   // If we don't know anything or it's an object array, just go through the generic arraycopy
2106   if (default_type == NULL) {
2107 
2108     // save arguments, because they will be killed by a runtime call
2109     save_in_reserved_area(R0, R1, R2, R3);
2110 
2111     // pass length argument on SP[0]
2112     __ str(length, Address(SP, -2*wordSize, pre_indexed));  // 2 words for a proper stack alignment
2113 
2114     address copyfunc_addr = StubRoutines::generic_arraycopy();
2115     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2116 #ifndef PRODUCT
2117     if (PrintC1Statistics) {
2118       __ inc_counter((address)&Runtime1::_generic_arraycopystub_cnt, tmp, tmp2);
2119     }
2120 #endif // !PRODUCT
2121     // the stub is in the code cache so close enough
2122     __ call(copyfunc_addr, relocInfo::runtime_call_type);
2123 
2124     __ add(SP, SP, 2*wordSize);
2125 
2126     __ cbz_32(R0, *stub->continuation());
2127 
2128     __ mvn_32(tmp, R0);
2129     restore_from_reserved_area(R0, R1, R2, R3);  // load saved arguments in slow case only
2130     __ sub_32(length, length, tmp);
2131     __ add_32(src_pos, src_pos, tmp);
2132     __ add_32(dst_pos, dst_pos, tmp);
2133 
2134     __ b(*stub->entry());
2135 
2136     __ bind(*stub->continuation());
2137     return;
2138   }
2139 
2140   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(),
2141          "must be true at this point");
2142   int elem_size = type2aelembytes(basic_type);
2143   int shift = exact_log2(elem_size);
2144 
2145   // Check for NULL
2146   if (flags & LIR_OpArrayCopy::src_null_check) {
2147     if (flags & LIR_OpArrayCopy::dst_null_check) {
2148       __ cmp(src, 0);
2149       __ cond_cmp(dst, 0, ne);  // make one instruction shorter if both checks are needed
2150       __ b(*stub->entry(), eq);
2151     } else {
2152       __ cbz(src, *stub->entry());
2153     }
2154   } else if (flags & LIR_OpArrayCopy::dst_null_check) {
2155     __ cbz(dst, *stub->entry());
2156   }
2157 
2158   // If the compiler was not able to prove that exact type of the source or the destination
2159   // of the arraycopy is an array type, check at runtime if the source or the destination is
2160   // an instance type.
2161   if (flags & LIR_OpArrayCopy::type_check) {
2162     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2163       __ load_klass(tmp, dst);
2164       __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2165       __ mov_slow(tmp, Klass::_lh_neutral_value);
2166       __ cmp_32(tmp2, tmp);
2167       __ b(*stub->entry(), ge);
2168     }
2169 
2170     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2171       __ load_klass(tmp, src);
2172       __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2173       __ mov_slow(tmp, Klass::_lh_neutral_value);
2174       __ cmp_32(tmp2, tmp);
2175       __ b(*stub->entry(), ge);
2176     }
2177   }
2178 
2179   // Check if negative
2180   const int all_positive_checks = LIR_OpArrayCopy::src_pos_positive_check |
2181                                   LIR_OpArrayCopy::dst_pos_positive_check |
2182                                   LIR_OpArrayCopy::length_positive_check;
2183   switch (flags & all_positive_checks) {
2184     case LIR_OpArrayCopy::src_pos_positive_check:
2185       __ branch_if_negative_32(src_pos, *stub->entry());
2186       break;
2187     case LIR_OpArrayCopy::dst_pos_positive_check:
2188       __ branch_if_negative_32(dst_pos, *stub->entry());
2189       break;
2190     case LIR_OpArrayCopy::length_positive_check:
2191       __ branch_if_negative_32(length, *stub->entry());
2192       break;
2193     case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::dst_pos_positive_check:
2194       __ branch_if_any_negative_32(src_pos, dst_pos, tmp, *stub->entry());
2195       break;
2196     case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2197       __ branch_if_any_negative_32(src_pos, length, tmp, *stub->entry());
2198       break;
2199     case LIR_OpArrayCopy::dst_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2200       __ branch_if_any_negative_32(dst_pos, length, tmp, *stub->entry());
2201       break;
2202     case all_positive_checks:
2203       __ branch_if_any_negative_32(src_pos, dst_pos, length, tmp, *stub->entry());
2204       break;
2205     default:
2206       assert((flags & all_positive_checks) == 0, "the last option");
2207   }
2208 
2209   // Range checks
2210   if (flags & LIR_OpArrayCopy::src_range_check) {
2211     __ ldr_s32(tmp2, Address(src, arrayOopDesc::length_offset_in_bytes()));
2212     __ add_32(tmp, src_pos, length);
2213     __ cmp_32(tmp, tmp2);
2214     __ b(*stub->entry(), hi);
2215   }
2216   if (flags & LIR_OpArrayCopy::dst_range_check) {
2217     __ ldr_s32(tmp2, Address(dst, arrayOopDesc::length_offset_in_bytes()));
2218     __ add_32(tmp, dst_pos, length);
2219     __ cmp_32(tmp, tmp2);
2220     __ b(*stub->entry(), hi);
2221   }
2222 
2223   // Check if src and dst are of the same type
2224   if (flags & LIR_OpArrayCopy::type_check) {
2225     // We don't know the array types are compatible
2226     if (basic_type != T_OBJECT) {
2227       // Simple test for basic type arrays
2228       if (UseCompressedClassPointers) {
2229         // We don't need decode because we just need to compare
2230         __ ldr_u32(tmp, Address(src, oopDesc::klass_offset_in_bytes()));
2231         __ ldr_u32(tmp2, Address(dst, oopDesc::klass_offset_in_bytes()));
2232         __ cmp_32(tmp, tmp2);
2233       } else {
2234         __ load_klass(tmp, src);
2235         __ load_klass(tmp2, dst);
2236         __ cmp(tmp, tmp2);
2237       }
2238       __ b(*stub->entry(), ne);
2239     } else {
2240       // For object arrays, if src is a sub class of dst then we can
2241       // safely do the copy.
2242       Label cont, slow;
2243 
2244       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2245 
2246       __ load_klass(tmp, src);
2247       __ load_klass(tmp2, dst);
2248 
2249       // We are at a call so all live registers are saved before we
2250       // get here
2251       assert_different_registers(tmp, tmp2, R6, altFP_7_11);
2252 
2253       __ check_klass_subtype_fast_path(tmp, tmp2, R6, altFP_7_11, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2254 
2255       __ mov(R6, R0);
2256       __ mov(altFP_7_11, R1);
2257       __ mov(R0, tmp);
2258       __ mov(R1, tmp2);
2259       __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); // does not blow any registers except R0, LR and Rtemp
2260       __ cmp_32(R0, 0);
2261       __ mov(R0, R6);
2262       __ mov(R1, altFP_7_11);
2263 
2264       if (copyfunc_addr != NULL) { // use stub if available
2265         // src is not a sub class of dst so we have to do a
2266         // per-element check.
2267 
2268         __ b(cont, ne);
2269 
2270         __ bind(slow);
2271 
2272         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2273         if ((flags & mask) != mask) {
2274           // Check that at least both of them object arrays.
2275           assert(flags & mask, "one of the two should be known to be an object array");
2276 
2277           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2278             __ load_klass(tmp, src);
2279           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2280             __ load_klass(tmp, dst);
2281           }
2282           int lh_offset = in_bytes(Klass::layout_helper_offset());
2283 
2284           __ ldr_u32(tmp2, Address(tmp, lh_offset));
2285 
2286           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2287           __ mov_slow(tmp, objArray_lh);
2288           __ cmp_32(tmp, tmp2);
2289           __ b(*stub->entry(), ne);
2290         }
2291 
2292         save_in_reserved_area(R0, R1, R2, R3);
2293 
2294         Register src_ptr = R0;
2295         Register dst_ptr = R1;
2296         Register len     = R2;
2297         Register chk_off = R3;
2298         Register super_k = tmp;
2299 
2300         __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2301         __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2302 
2303         __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2304         __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2305         __ load_klass(tmp, dst);
2306 
2307         int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2308         int sco_offset = in_bytes(Klass::super_check_offset_offset());
2309 
2310         __ ldr(super_k, Address(tmp, ek_offset));
2311 
2312         __ mov(len, length);
2313         __ ldr_u32(chk_off, Address(super_k, sco_offset));
2314         __ push(super_k);
2315 
2316         __ call(copyfunc_addr, relocInfo::runtime_call_type);
2317 
2318 #ifndef PRODUCT
2319         if (PrintC1Statistics) {
2320           Label failed;
2321           __ cbnz_32(R0, failed);
2322           __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, tmp, tmp2);
2323           __ bind(failed);
2324         }
2325 #endif // PRODUCT
2326 
2327         __ add(SP, SP, wordSize);  // Drop super_k argument
2328 
2329         __ cbz_32(R0, *stub->continuation());
2330         __ mvn_32(tmp, R0);
2331 
2332         // load saved arguments in slow case only
2333         restore_from_reserved_area(R0, R1, R2, R3);
2334 
2335         __ sub_32(length, length, tmp);
2336         __ add_32(src_pos, src_pos, tmp);
2337         __ add_32(dst_pos, dst_pos, tmp);
2338 
2339 #ifndef PRODUCT
2340         if (PrintC1Statistics) {
2341           __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, tmp, tmp2);
2342         }
2343 #endif
2344 
2345         __ b(*stub->entry());
2346 
2347         __ bind(cont);
2348       } else {
2349         __ b(*stub->entry(), eq);
2350         __ bind(cont);
2351       }
2352     }
2353   }
2354 
2355 #ifndef PRODUCT
2356   if (PrintC1Statistics) {
2357     address counter = Runtime1::arraycopy_count_address(basic_type);
2358     __ inc_counter(counter, tmp, tmp2);
2359   }
2360 #endif // !PRODUCT
2361 
2362   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2363   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2364   const char *name;
2365   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2366 
2367   Register src_ptr = R0;
2368   Register dst_ptr = R1;
2369   Register len     = R2;
2370 
2371   __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2372   __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2373 
2374   __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2375   __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2376 
2377   __ mov(len, length);
2378 
2379   __ call(entry, relocInfo::runtime_call_type);
2380 
2381   __ bind(*stub->continuation());
2382 }
2383 
2384 #ifdef ASSERT
2385  // emit run-time assertion
2386 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2387   assert(op->code() == lir_assert, "must be");
2388 
2389   if (op->in_opr1()->is_valid()) {
2390     assert(op->in_opr2()->is_valid(), "both operands must be valid");
2391     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2392   } else {
2393     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2394     assert(op->condition() == lir_cond_always, "no other conditions allowed");
2395   }
2396 
2397   Label ok;
2398   if (op->condition() != lir_cond_always) {
2399     AsmCondition acond = al;
2400     switch (op->condition()) {
2401       case lir_cond_equal:        acond = eq; break;
2402       case lir_cond_notEqual:     acond = ne; break;
2403       case lir_cond_less:         acond = lt; break;
2404       case lir_cond_lessEqual:    acond = le; break;
2405       case lir_cond_greaterEqual: acond = ge; break;
2406       case lir_cond_greater:      acond = gt; break;
2407       case lir_cond_aboveEqual:   acond = hs; break;
2408       case lir_cond_belowEqual:   acond = ls; break;
2409       default:                    ShouldNotReachHere();
2410     }
2411     __ b(ok, acond);
2412   }
2413   if (op->halt()) {
2414     const char* str = __ code_string(op->msg());
2415     __ stop(str);
2416   } else {
2417     breakpoint();
2418   }
2419   __ bind(ok);
2420 }
2421 #endif // ASSERT
2422 
2423 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2424   fatal("CRC32 intrinsic is not implemented on this platform");
2425 }
2426 
2427 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2428   Register obj = op->obj_opr()->as_pointer_register();
2429   Register hdr = op->hdr_opr()->as_pointer_register();
2430   Register lock = op->lock_opr()->as_pointer_register();
2431 
2432   if (!UseFastLocking) {
2433     __ b(*op->stub()->entry());
2434   } else if (op->code() == lir_lock) {
2435     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2436     int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry());
2437     if (op->info() != NULL) {
2438       add_debug_info_for_null_check(null_check_offset, op->info());
2439     }
2440   } else if (op->code() == lir_unlock) {
2441     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2442   } else {
2443     ShouldNotReachHere();
2444   }
2445   __ bind(*op->stub()->continuation());
2446 }
2447 
2448 
2449 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2450   ciMethod* method = op->profiled_method();
2451   int bci          = op->profiled_bci();
2452   ciMethod* callee = op->profiled_callee();
2453 
2454   // Update counter for all call types
2455   ciMethodData* md = method->method_data_or_null();
2456   assert(md != NULL, "Sanity");
2457   ciProfileData* data = md->bci_to_data(bci);
2458   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2459   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2460   Register mdo  = op->mdo()->as_register();
2461   assert(op->tmp1()->is_register(), "tmp1 must be allocated");
2462   Register tmp1 = op->tmp1()->as_pointer_register();
2463   assert_different_registers(mdo, tmp1);
2464   __ mov_metadata(mdo, md->constant_encoding());
2465   int mdo_offset_bias = 0;
2466   int max_offset = 4096;
2467   if (md->byte_offset_of_slot(data, CounterData::count_offset()) + data->size_in_bytes() >= max_offset) {
2468     // The offset is large so bias the mdo by the base of the slot so
2469     // that the ldr can use an immediate offset to reference the slots of the data
2470     mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2471     __ mov_slow(tmp1, mdo_offset_bias);
2472     __ add(mdo, mdo, tmp1);
2473   }
2474 
2475   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2476   // Perform additional virtual call profiling for invokevirtual and
2477   // invokeinterface bytecodes
2478   if (op->should_profile_receiver_type()) {
2479     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2480     Register recv = op->recv()->as_register();
2481     assert_different_registers(mdo, tmp1, recv);
2482     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2483     ciKlass* known_klass = op->known_holder();
2484     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2485       // We know the type that will be seen at this call site; we can
2486       // statically update the MethodData* rather than needing to do
2487       // dynamic tests on the receiver type
2488 
2489       // NOTE: we should probably put a lock around this search to
2490       // avoid collisions by concurrent compilations
2491       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2492       uint i;
2493       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2494         ciKlass* receiver = vc_data->receiver(i);
2495         if (known_klass->equals(receiver)) {
2496           Address data_addr(mdo, md->byte_offset_of_slot(data,
2497                                                          VirtualCallData::receiver_count_offset(i)) -
2498                             mdo_offset_bias);
2499           __ ldr(tmp1, data_addr);
2500           __ add(tmp1, tmp1, DataLayout::counter_increment);
2501           __ str(tmp1, data_addr);
2502           return;
2503         }
2504       }
2505 
2506       // Receiver type not found in profile data; select an empty slot
2507 
2508       // Note that this is less efficient than it should be because it
2509       // always does a write to the receiver part of the
2510       // VirtualCallData rather than just the first time
2511       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2512         ciKlass* receiver = vc_data->receiver(i);
2513         if (receiver == NULL) {
2514           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2515                             mdo_offset_bias);
2516           __ mov_metadata(tmp1, known_klass->constant_encoding());
2517           __ str(tmp1, recv_addr);
2518           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2519                             mdo_offset_bias);
2520           __ ldr(tmp1, data_addr);
2521           __ add(tmp1, tmp1, DataLayout::counter_increment);
2522           __ str(tmp1, data_addr);
2523           return;
2524         }
2525       }
2526     } else {
2527       __ load_klass(recv, recv);
2528       Label update_done;
2529       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2530       // Receiver did not match any saved receiver and there is no empty row for it.
2531       // Increment total counter to indicate polymorphic case.
2532       __ ldr(tmp1, counter_addr);
2533       __ add(tmp1, tmp1, DataLayout::counter_increment);
2534       __ str(tmp1, counter_addr);
2535 
2536       __ bind(update_done);
2537     }
2538   } else {
2539     // Static call
2540     __ ldr(tmp1, counter_addr);
2541     __ add(tmp1, tmp1, DataLayout::counter_increment);
2542     __ str(tmp1, counter_addr);
2543   }
2544 }
2545 
2546 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2547   fatal("Type profiling not implemented on this platform");
2548 }
2549 
2550 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
2551   Unimplemented();
2552 }
2553 
2554 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2555   Unimplemented();
2556 }
2557 
2558 
2559 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2560   Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2561   __ add_slow(dst->as_pointer_register(), mon_addr.base(), mon_addr.disp());
2562 }
2563 
2564 
2565 void LIR_Assembler::align_backward_branch_target() {
2566   // Some ARM processors do better with 8-byte branch target alignment
2567   __ align(8);
2568 }
2569 
2570 
2571 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2572   // tmp must be unused
2573   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2574 
2575   if (left->is_single_cpu()) {
2576     assert (dest->type() == T_INT, "unexpected result type");
2577     assert (left->type() == T_INT, "unexpected left type");
2578     __ neg_32(dest->as_register(), left->as_register());
2579   } else if (left->is_double_cpu()) {
2580     Register dest_lo = dest->as_register_lo();
2581     Register dest_hi = dest->as_register_hi();
2582     Register src_lo = left->as_register_lo();
2583     Register src_hi = left->as_register_hi();
2584     if (dest_lo == src_hi) {
2585       dest_lo = Rtemp;
2586     }
2587     __ rsbs(dest_lo, src_lo, 0);
2588     __ rsc(dest_hi, src_hi, 0);
2589     move_regs(dest_lo, dest->as_register_lo());
2590   } else if (left->is_single_fpu()) {
2591     __ neg_float(dest->as_float_reg(), left->as_float_reg());
2592   } else if (left->is_double_fpu()) {
2593     __ neg_double(dest->as_double_reg(), left->as_double_reg());
2594   } else {
2595     ShouldNotReachHere();
2596   }
2597 }
2598 
2599 
2600 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2601   assert(patch_code == lir_patch_none, "Patch code not supported");
2602   LIR_Address* addr = addr_opr->as_address_ptr();
2603   if (addr->index()->is_illegal()) {
2604     jint c = addr->disp();
2605     if (!Assembler::is_arith_imm_in_range(c)) {
2606       BAILOUT("illegal arithmetic operand");
2607     }
2608     __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), c);
2609   } else {
2610     assert(addr->disp() == 0, "cannot handle otherwise");
2611     __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(),
2612            AsmOperand(addr->index()->as_pointer_register(), lsl, addr->scale()));
2613   }
2614 }
2615 
2616 
2617 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2618   assert(!tmp->is_valid(), "don't need temporary");
2619   __ call(dest);
2620   if (info != NULL) {
2621     add_call_info_here(info);
2622   }
2623 }
2624 
2625 
2626 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2627   assert(src->is_double_cpu() && dest->is_address() ||
2628          src->is_address() && dest->is_double_cpu(),
2629          "Simple move_op is called for all other cases");
2630 
2631   int null_check_offset;
2632   if (dest->is_address()) {
2633     // Store
2634     const LIR_Address* addr = dest->as_address_ptr();
2635     const Register src_lo = src->as_register_lo();
2636     const Register src_hi = src->as_register_hi();
2637     assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2638 
2639     if (src_lo < src_hi) {
2640       null_check_offset = __ offset();
2641       __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(src_hi));
2642     } else {
2643       assert(src_lo < Rtemp, "Rtemp is higher than any allocatable register");
2644       __ mov(Rtemp, src_hi);
2645       null_check_offset = __ offset();
2646       __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(Rtemp));
2647     }
2648   } else {
2649     // Load
2650     const LIR_Address* addr = src->as_address_ptr();
2651     const Register dest_lo = dest->as_register_lo();
2652     const Register dest_hi = dest->as_register_hi();
2653     assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2654 
2655     null_check_offset = __ offset();
2656     if (dest_lo < dest_hi) {
2657       __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(dest_hi));
2658     } else {
2659       assert(dest_lo < Rtemp, "Rtemp is higher than any allocatable register");
2660       __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(Rtemp));
2661       __ mov(dest_hi, Rtemp);
2662     }
2663   }
2664 
2665   if (info != NULL) {
2666     add_debug_info_for_null_check(null_check_offset, info);
2667   }
2668 }
2669 
2670 
2671 void LIR_Assembler::membar() {
2672   __ membar(MacroAssembler::StoreLoad, Rtemp);
2673 }
2674 
2675 void LIR_Assembler::membar_acquire() {
2676   __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::LoadLoad | MacroAssembler::LoadStore), Rtemp);
2677 }
2678 
2679 void LIR_Assembler::membar_release() {
2680   __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2681 }
2682 
2683 void LIR_Assembler::membar_loadload() {
2684   __ membar(MacroAssembler::LoadLoad, Rtemp);
2685 }
2686 
2687 void LIR_Assembler::membar_storestore() {
2688   __ membar(MacroAssembler::StoreStore, Rtemp);
2689 }
2690 
2691 void LIR_Assembler::membar_loadstore() {
2692   __ membar(MacroAssembler::LoadStore, Rtemp);
2693 }
2694 
2695 void LIR_Assembler::membar_storeload() {
2696   __ membar(MacroAssembler::StoreLoad, Rtemp);
2697 }
2698 
2699 void LIR_Assembler::on_spin_wait() {
2700   Unimplemented();
2701 }
2702 
2703 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2704   // Not used on ARM
2705   Unimplemented();
2706 }
2707 
2708 void LIR_Assembler::peephole(LIR_List* lir) {
2709   LIR_OpList* inst = lir->instructions_list();
2710   const int inst_length = inst->length();
2711   for (int i = 0; i < inst_length; i++) {
2712     LIR_Op* op = inst->at(i);
2713     switch (op->code()) {
2714       case lir_cmp: {
2715         // Replace:
2716         //   cmp rX, y
2717         //   cmove [EQ] y, z, rX
2718         // with
2719         //   cmp rX, y
2720         //   cmove [EQ] illegalOpr, z, rX
2721         //
2722         // or
2723         //   cmp rX, y
2724         //   cmove [NE] z, y, rX
2725         // with
2726         //   cmp rX, y
2727         //   cmove [NE] z, illegalOpr, rX
2728         //
2729         // moves from illegalOpr should be removed when converting LIR to native assembly
2730 
2731         LIR_Op2* cmp = op->as_Op2();
2732         assert(cmp != NULL, "cmp LIR instruction is not an op2");
2733 
2734         if (i + 1 < inst_length) {
2735           LIR_Op2* cmove = inst->at(i + 1)->as_Op2();
2736           if (cmove != NULL && cmove->code() == lir_cmove) {
2737             LIR_Opr cmove_res = cmove->result_opr();
2738             bool res_is_op1 = cmove_res == cmp->in_opr1();
2739             bool res_is_op2 = cmove_res == cmp->in_opr2();
2740             LIR_Opr cmp_res, cmp_arg;
2741             if (res_is_op1) {
2742               cmp_res = cmp->in_opr1();
2743               cmp_arg = cmp->in_opr2();
2744             } else if (res_is_op2) {
2745               cmp_res = cmp->in_opr2();
2746               cmp_arg = cmp->in_opr1();
2747             } else {
2748               cmp_res = LIR_OprFact::illegalOpr;
2749               cmp_arg = LIR_OprFact::illegalOpr;
2750             }
2751 
2752             if (cmp_res != LIR_OprFact::illegalOpr) {
2753               LIR_Condition cond = cmove->condition();
2754               if (cond == lir_cond_equal && cmove->in_opr1() == cmp_arg) {
2755                 cmove->set_in_opr1(LIR_OprFact::illegalOpr);
2756               } else if (cond == lir_cond_notEqual && cmove->in_opr2() == cmp_arg) {
2757                 cmove->set_in_opr2(LIR_OprFact::illegalOpr);
2758               }
2759             }
2760           }
2761         }
2762         break;
2763       }
2764 
2765       default:
2766         break;
2767     }
2768   }
2769 }
2770 
2771 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2772   assert(src->is_address(), "sanity");
2773   Address addr = as_Address(src->as_address_ptr());
2774 
2775   if (code == lir_xchg) {
2776   } else {
2777     assert (!data->is_oop(), "xadd for oops");
2778   }
2779 
2780   __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2781 
2782   Label retry;
2783   __ bind(retry);
2784 
2785   if (data->type() == T_INT || data->is_oop()) {
2786     Register dst = dest->as_register();
2787     Register new_val = noreg;
2788     __ ldrex(dst, addr);
2789     if (code == lir_xadd) {
2790       Register tmp_reg = tmp->as_register();
2791       if (data->is_constant()) {
2792         assert_different_registers(dst, tmp_reg);
2793         __ add_32(tmp_reg, dst, data->as_constant_ptr()->as_jint());
2794       } else {
2795         assert_different_registers(dst, tmp_reg, data->as_register());
2796         __ add_32(tmp_reg, dst, data->as_register());
2797       }
2798       new_val = tmp_reg;
2799     } else {
2800       if (UseCompressedOops && data->is_oop()) {
2801         new_val = tmp->as_pointer_register();
2802       } else {
2803         new_val = data->as_register();
2804       }
2805       assert_different_registers(dst, new_val);
2806     }
2807     __ strex(Rtemp, new_val, addr);
2808 
2809   } else if (data->type() == T_LONG) {
2810     Register dst_lo = dest->as_register_lo();
2811     Register new_val_lo = noreg;
2812     Register dst_hi = dest->as_register_hi();
2813 
2814     assert(dst_hi->encoding() == dst_lo->encoding() + 1, "non aligned register pair");
2815     assert((dst_lo->encoding() & 0x1) == 0, "misaligned register pair");
2816 
2817     __ bind(retry);
2818     __ ldrexd(dst_lo, addr);
2819     if (code == lir_xadd) {
2820       Register tmp_lo = tmp->as_register_lo();
2821       Register tmp_hi = tmp->as_register_hi();
2822 
2823       assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
2824       assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
2825 
2826       if (data->is_constant()) {
2827         jlong c = data->as_constant_ptr()->as_jlong();
2828         assert((jlong)((jint)c) == c, "overflow");
2829         assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi);
2830         __ adds(tmp_lo, dst_lo, (jint)c);
2831         __ adc(tmp_hi, dst_hi, 0);
2832       } else {
2833         Register new_val_lo = data->as_register_lo();
2834         Register new_val_hi = data->as_register_hi();
2835         __ adds(tmp_lo, dst_lo, new_val_lo);
2836         __ adc(tmp_hi, dst_hi, new_val_hi);
2837         assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi, new_val_lo, new_val_hi);
2838       }
2839       new_val_lo = tmp_lo;
2840     } else {
2841       new_val_lo = data->as_register_lo();
2842       Register new_val_hi = data->as_register_hi();
2843 
2844       assert_different_registers(dst_lo, dst_hi, new_val_lo, new_val_hi);
2845       assert(new_val_hi->encoding() == new_val_lo->encoding() + 1, "non aligned register pair");
2846       assert((new_val_lo->encoding() & 0x1) == 0, "misaligned register pair");
2847     }
2848     __ strexd(Rtemp, new_val_lo, addr);
2849   } else {
2850     ShouldNotReachHere();
2851   }
2852 
2853   __ cbnz_32(Rtemp, retry);
2854   __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
2855 
2856 }
2857 
2858 #undef __