1 /*
2 * Copyright (c) 2008, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef CPU_ARM_MACROASSEMBLER_ARM_HPP
26 #define CPU_ARM_MACROASSEMBLER_ARM_HPP
27
28 #include "code/relocInfo.hpp"
29 #include "utilities/powerOfTwo.hpp"
30
31 // Introduced AddressLiteral and its subclasses to ease portability from
32 // x86 and avoid relocation issues
33 class AddressLiteral {
34 RelocationHolder _rspec;
35 // Typically we use AddressLiterals we want to use their rval
36 // However in some situations we want the lval (effect address) of the item.
37 // We provide a special factory for making those lvals.
38 bool _is_lval;
39
40 address _target;
41
42 private:
43 static relocInfo::relocType reloc_for_target(address target) {
44 // Used for ExternalAddress or when the type is not specified
45 // Sometimes ExternalAddress is used for values which aren't
46 // exactly addresses, like the card table base.
47 // external_word_type can't be used for values in the first page
48 // so just skip the reloc in that case.
49 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
50 }
51
52 void set_rspec(relocInfo::relocType rtype);
53
54 protected:
55 // creation
56 AddressLiteral()
57 : _is_lval(false),
58 _target(nullptr)
59 {}
60
61 public:
62
63 AddressLiteral(address target, relocInfo::relocType rtype) {
64 _is_lval = false;
65 _target = target;
66 set_rspec(rtype);
67 }
68
69 AddressLiteral(address target, RelocationHolder const& rspec)
70 : _rspec(rspec),
71 _is_lval(false),
72 _target(target)
73 {}
74
75 AddressLiteral(address target) {
76 _is_lval = false;
77 _target = target;
78 set_rspec(reloc_for_target(target));
79 }
80
81 AddressLiteral addr() {
82 AddressLiteral ret = *this;
83 ret._is_lval = true;
84 return ret;
85 }
86
87 private:
88
89 address target() { return _target; }
90 bool is_lval() { return _is_lval; }
91
92 relocInfo::relocType reloc() const { return _rspec.type(); }
93 const RelocationHolder& rspec() const { return _rspec; }
94
95 friend class Assembler;
96 friend class MacroAssembler;
97 friend class Address;
98 friend class LIR_Assembler;
99 friend class InlinedAddress;
100 };
101
102 class ExternalAddress: public AddressLiteral {
103
104 public:
105
106 ExternalAddress(address target) : AddressLiteral(target) {}
107
108 };
109
110 class InternalAddress: public AddressLiteral {
111
112 public:
113
114 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
115
116 };
117
118 // Inlined constants, for use with ldr_literal / bind_literal
119 // Note: InlinedInteger not supported (use move_slow(Register,int[,cond]))
120 class InlinedLiteral: StackObj {
121 public:
122 Label label; // need to be public for direct access with &
123 InlinedLiteral() {
124 }
125 };
126
127 class InlinedMetadata: public InlinedLiteral {
128 private:
129 Metadata *_data;
130
131 public:
132 InlinedMetadata(Metadata *data): InlinedLiteral() {
133 _data = data;
134 }
135 Metadata *data() { return _data; }
136 };
137
138 // Currently unused
139 // class InlinedOop: public InlinedLiteral {
140 // private:
141 // jobject _jobject;
142 //
143 // public:
144 // InlinedOop(jobject target): InlinedLiteral() {
145 // _jobject = target;
146 // }
147 // jobject jobject() { return _jobject; }
148 // };
149
150 class InlinedAddress: public InlinedLiteral {
151 private:
152 AddressLiteral _literal;
153
154 public:
155
156 InlinedAddress(jobject object): InlinedLiteral(), _literal((address)object, relocInfo::oop_type) {
157 ShouldNotReachHere(); // use mov_oop (or implement InlinedOop)
158 }
159
160 InlinedAddress(Metadata *data): InlinedLiteral(), _literal((address)data, relocInfo::metadata_type) {
161 ShouldNotReachHere(); // use InlinedMetadata or mov_metadata
162 }
163
164 InlinedAddress(address target, const RelocationHolder &rspec): InlinedLiteral(), _literal(target, rspec) {
165 assert(rspec.type() != relocInfo::oop_type, "Do not use InlinedAddress for oops");
166 assert(rspec.type() != relocInfo::metadata_type, "Do not use InlinedAddress for metadatas");
167 }
168
169 InlinedAddress(address target, relocInfo::relocType rtype): InlinedLiteral(), _literal(target, rtype) {
170 assert(rtype != relocInfo::oop_type, "Do not use InlinedAddress for oops");
171 assert(rtype != relocInfo::metadata_type, "Do not use InlinedAddress for metadatas");
172 }
173
174 // Note: default is relocInfo::none for InlinedAddress
175 InlinedAddress(address target): InlinedLiteral(), _literal(target, relocInfo::none) {
176 }
177
178 address target() { return _literal.target(); }
179
180 const RelocationHolder& rspec() const { return _literal.rspec(); }
181 };
182
183 class InlinedString: public InlinedLiteral {
184 private:
185 const char* _msg;
186
187 public:
188 InlinedString(const char* msg): InlinedLiteral() {
189 _msg = msg;
190 }
191 const char* msg() { return _msg; }
192 };
193
194 class MacroAssembler: public Assembler {
195 protected:
196
197 // Support for VM calls
198 //
199
200 // This is the base routine called by the different versions of call_VM_leaf.
201 void call_VM_leaf_helper(address entry_point, int number_of_arguments);
202
203 // This is the base routine called by the different versions of call_VM. The interpreter
204 // may customize this version by overriding it for its purposes (e.g., to save/restore
205 // additional registers when doing a VM call).
206 virtual void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions);
207 public:
208
209 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
210
211 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
212 // The implementation is only non-empty for the InterpreterMacroAssembler,
213 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
214 virtual void check_and_handle_popframe() {}
215 virtual void check_and_handle_earlyret() {}
216
217 // By default, we do not need relocation information for non
218 // patchable absolute addresses. However, when needed by some
219 // extensions, ignore_non_patchable_relocations can be modified,
220 // returning false to preserve all relocation information.
221 inline bool ignore_non_patchable_relocations() { return true; }
222
223 void align(int modulus);
224 void align(int modulus, int target);
225
226 // Support for VM calls
227 //
228 // It is imperative that all calls into the VM are handled via the call_VM methods.
229 // They make sure that the stack linkage is setup correctly. call_VM's correspond
230 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
231
232 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true);
233 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
234 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
235 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
236
237 // The following methods are required by templateTable.cpp,
238 // but not used on ARM.
239 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
240 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
241 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
242 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
243
244 // Note: The super_call_VM calls are not used on ARM
245
246 // Raw call, without saving/restoring registers, exception handling, etc.
247 // Mainly used from various stubs.
248 // Note: if 'save_R9_if_scratched' is true, call_VM may on some
249 // platforms save values on the stack. Set it to false (and handle
250 // R9 in the callers) if the top of the stack must not be modified
251 // by call_VM.
252 void call_VM(address entry_point, bool save_R9_if_scratched);
253
254 void call_VM_leaf(address entry_point);
255 void call_VM_leaf(address entry_point, Register arg_1);
256 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
257 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
258 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
259
260 void get_vm_result_oop(Register oop_result, Register tmp);
261 void get_vm_result_metadata(Register metadata_result, Register tmp);
262
263 // Always sets/resets sp, which default to SP if (last_sp == noreg)
264 // Optionally sets/resets fp (use noreg to avoid setting it)
265 // Optionally sets/resets pc depending on save_last_java_pc flag
266 // Note: when saving PC, set_last_Java_frame returns PC's offset in the code section
267 // (for oop_maps offset computation)
268 int set_last_Java_frame(Register last_sp, Register last_fp, bool save_last_java_pc, Register tmp);
269 void reset_last_Java_frame(Register tmp);
270 // status set in set_last_Java_frame for reset_last_Java_frame
271 bool _fp_saved;
272 bool _pc_saved;
273
274 #ifdef PRODUCT
275 #define BLOCK_COMMENT(str) /* nothing */
276 #define STOP(error) __ stop(error)
277 #else
278 #define BLOCK_COMMENT(str) __ block_comment(str)
279 #define STOP(error) __ block_comment(error); __ stop(error)
280 #endif
281
282 void lookup_virtual_method(Register recv_klass,
283 Register vtable_index,
284 Register method_result);
285
286 // Test sub_klass against super_klass, with fast and slow paths.
287
288 // The fast path produces a tri-state answer: yes / no / maybe-slow.
289 // One of the three labels can be null, meaning take the fall-through.
290 // No registers are killed, except temp_regs.
291 void check_klass_subtype_fast_path(Register sub_klass,
292 Register super_klass,
293 Register temp_reg,
294 Register temp_reg2,
295 Label* L_success,
296 Label* L_failure,
297 Label* L_slow_path);
298
299 // The rest of the type check; must be wired to a corresponding fast path.
300 // It does not repeat the fast path logic, so don't use it standalone.
301 // temp_reg3 can be noreg, if no temps are available.
302 // Updates the sub's secondary super cache as necessary.
303 // If set_cond_codes:
304 // - condition codes will be Z on success, NZ on failure.
305 // - temp_reg will be 0 on success, non-0 on failure
306 void check_klass_subtype_slow_path(Register sub_klass,
307 Register super_klass,
308 Register temp_reg,
309 Register temp_reg2,
310 Register temp_reg3, // auto assigned if noreg
311 Label* L_success,
312 Label* L_failure,
313 bool set_cond_codes = false);
314
315 // Simplified, combined version, good for typical uses.
316 // temp_reg3 can be noreg, if no temps are available. It is used only on slow path.
317 // Falls through on failure.
318 void check_klass_subtype(Register sub_klass,
319 Register super_klass,
320 Register temp_reg,
321 Register temp_reg2,
322 Register temp_reg3, // auto assigned on slow path if noreg
323 Label& L_success);
324
325 // Returns address of receiver parameter, using tmp as base register. tmp and params_count can be the same.
326 Address receiver_argument_address(Register params_base, Register params_count, Register tmp);
327
328 void _verify_oop(Register reg, const char* s, const char* file, int line);
329 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
330
331 // TODO: verify method and klass metadata (compare against vptr?)
332 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
333 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}
334
335 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
336 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop ", __FILE__, __LINE__)
337 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
338 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
339
340 void null_check(Register reg, Register tmp, int offset = -1);
341 inline void null_check(Register reg) { null_check(reg, noreg, -1); } // for C1 lir_null_check
342
343 // Puts address of allocated object into register `obj` and end of allocated object into register `obj_end`.
344 void tlab_allocate(Register obj, Register obj_end, Register tmp1,
345 RegisterOrConstant size_expression, Label& slow_case);
346
347 void zero_memory(Register start, Register end, Register tmp);
348
349 static bool needs_explicit_null_check(intptr_t offset);
350 static bool uses_implicit_null_check(void* address);
351
352 void arm_stack_overflow_check(int frame_size_in_bytes, Register tmp);
353 void arm_stack_overflow_check(Register Rsize, Register tmp);
354
355 void bang_stack_with_offset(int offset) {
356 ShouldNotReachHere();
357 }
358
359 void resolve_jobject(Register value, Register tmp1, Register tmp2);
360 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
361
362 void nop() {
363 mov(R0, R0);
364 }
365
366 void push(Register rd, AsmCondition cond = al) {
367 assert(rd != SP, "unpredictable instruction");
368 str(rd, Address(SP, -wordSize, pre_indexed), cond);
369 }
370
371 void push(RegisterSet reg_set, AsmCondition cond = al) {
372 assert(!reg_set.contains(SP), "unpredictable instruction");
373 stmdb(SP, reg_set, writeback, cond);
374 }
375
376 void pop(Register rd, AsmCondition cond = al) {
377 assert(rd != SP, "unpredictable instruction");
378 ldr(rd, Address(SP, wordSize, post_indexed), cond);
379 }
380
381 void pop(RegisterSet reg_set, AsmCondition cond = al) {
382 assert(!reg_set.contains(SP), "unpredictable instruction");
383 ldmia(SP, reg_set, writeback, cond);
384 }
385
386 void fpushd(FloatRegister fd, AsmCondition cond = al) {
387 fstmdbd(SP, FloatRegisterSet(fd), writeback, cond);
388 }
389
390 void fpushs(FloatRegister fd, AsmCondition cond = al) {
391 fstmdbs(SP, FloatRegisterSet(fd), writeback, cond);
392 }
393
394 void fpopd(FloatRegister fd, AsmCondition cond = al) {
395 fldmiad(SP, FloatRegisterSet(fd), writeback, cond);
396 }
397
398 void fpops(FloatRegister fd, AsmCondition cond = al) {
399 fldmias(SP, FloatRegisterSet(fd), writeback, cond);
400 }
401
402 void fpush(FloatRegisterSet reg_set) {
403 fstmdbd(SP, reg_set, writeback);
404 }
405
406 void fpop(FloatRegisterSet reg_set) {
407 fldmiad(SP, reg_set, writeback);
408 }
409
410 void fpush_hardfp(FloatRegisterSet reg_set) {
411 #ifndef __SOFTFP__
412 fpush(reg_set);
413 #endif
414 }
415
416 void fpop_hardfp(FloatRegisterSet reg_set) {
417 #ifndef __SOFTFP__
418 fpop(reg_set);
419 #endif
420 }
421
422 // Order access primitives
423 enum Membar_mask_bits {
424 StoreStore = 1 << 3,
425 LoadStore = 1 << 2,
426 StoreLoad = 1 << 1,
427 LoadLoad = 1 << 0
428 };
429
430 void membar(Membar_mask_bits mask,
431 Register tmp,
432 bool preserve_flags = true,
433 Register load_tgt = noreg);
434
435 void breakpoint(AsmCondition cond = al);
436 void stop(const char* msg);
437 // prints msg and continues
438 void warn(const char* msg);
439 void unimplemented(const char* what = "");
440 void should_not_reach_here() { stop("should not reach here"); }
441 static void debug(const char* msg, const intx* registers);
442
443 // Create a walkable frame to help tracking down who called this code.
444 // Returns the frame size in words.
445 int should_not_call_this() {
446 raw_push(FP, LR);
447 should_not_reach_here();
448 flush();
449 return 2; // frame_size_in_words (FP+LR)
450 }
451
452 int save_all_registers();
453 void restore_all_registers();
454 int save_caller_save_registers();
455 void restore_caller_save_registers();
456
457 void add_rc(Register dst, Register arg1, RegisterOrConstant arg2);
458
459 // add_slow and mov_slow are used to manipulate offsets larger than 1024,
460 // these functions are not expected to handle all possible constants,
461 // only those that can really occur during compilation
462 void add_slow(Register rd, Register rn, int c);
463 void sub_slow(Register rd, Register rn, int c);
464
465
466 void mov_slow(Register rd, intptr_t c, AsmCondition cond = al);
467 void mov_slow(Register rd, const char *string);
468 void mov_slow(Register rd, address addr);
469
470 void patchable_mov_oop(Register rd, jobject o, int oop_index) {
471 mov_oop(rd, o, oop_index);
472 }
473 void mov_oop(Register rd, jobject o, int index = 0, AsmCondition cond = al);
474
475 void patchable_mov_metadata(Register rd, Metadata* o, int index) {
476 mov_metadata(rd, o, index);
477 }
478 void mov_metadata(Register rd, Metadata* o, int index = 0);
479
480 void mov_float(FloatRegister fd, jfloat c, AsmCondition cond = al);
481 void mov_double(FloatRegister fd, jdouble c, AsmCondition cond = al);
482
483
484 // Note: this variant of mov_address assumes the address moves with
485 // the code. Do *not* implement it with non-relocated instructions,
486 // unless PC-relative.
487 void mov_relative_address(Register rd, address addr, AsmCondition cond = al) {
488 int offset = addr - pc() - 8;
489 assert((offset & 3) == 0, "bad alignment");
490 if (offset >= 0) {
491 assert(AsmOperand::is_rotated_imm(offset), "addr too far");
492 add(rd, PC, offset, cond);
493 } else {
494 assert(AsmOperand::is_rotated_imm(-offset), "addr too far");
495 sub(rd, PC, -offset, cond);
496 }
497 }
498
499 // Runtime address that may vary from one execution to another.
500 // Warning: do not implement as a PC relative address.
501 void mov_address(Register rd, address addr) {
502 mov_address(rd, addr, RelocationHolder::none);
503 }
504
505 // rspec can be RelocationHolder::none (for ignored symbolic Relocation).
506 // In that case, the address is absolute and the generated code need
507 // not be relocable.
508 void mov_address(Register rd, address addr, RelocationHolder const& rspec) {
509 assert(rspec.type() != relocInfo::runtime_call_type, "do not use mov_address for runtime calls");
510 assert(rspec.type() != relocInfo::static_call_type, "do not use mov_address for relocable calls");
511 if (rspec.type() == relocInfo::none) {
512 // absolute address, relocation not needed
513 mov_slow(rd, (intptr_t)addr);
514 return;
515 }
516 if (VM_Version::supports_movw()) {
517 relocate(rspec);
518 int c = (int)addr;
519 movw(rd, c & 0xffff);
520 if ((unsigned int)c >> 16) {
521 movt(rd, (unsigned int)c >> 16);
522 }
523 return;
524 }
525 Label skip_literal;
526 InlinedAddress addr_literal(addr, rspec);
527 ldr_literal(rd, addr_literal);
528 b(skip_literal);
529 bind_literal(addr_literal);
530 bind(skip_literal);
531 }
532
533 // Note: Do not define mov_address for a Label
534 //
535 // Load from addresses potentially within the code are now handled
536 // InlinedLiteral subclasses (to allow more flexibility on how the
537 // ldr_literal is performed).
538
539 void ldr_literal(Register rd, InlinedAddress& L) {
540 assert(L.rspec().type() != relocInfo::runtime_call_type, "avoid ldr_literal for calls");
541 assert(L.rspec().type() != relocInfo::static_call_type, "avoid ldr_literal for calls");
542 relocate(L.rspec());
543 ldr(rd, Address(PC, target(L.label) - pc() - 8));
544 }
545
546 void ldr_literal(Register rd, InlinedString& L) {
547 const char* msg = L.msg();
548 if (code()->consts()->contains((address)msg)) {
549 // string address moves with the code
550 ldr(rd, Address(PC, ((address)msg) - pc() - 8));
551 return;
552 }
553 // Warning: use external strings with care. They are not relocated
554 // if the code moves. If needed, use code_string to move them
555 // to the consts section.
556 ldr(rd, Address(PC, target(L.label) - pc() - 8));
557 }
558
559 void ldr_literal(Register rd, InlinedMetadata& L) {
560 // relocation done in the bind_literal for metadatas
561 ldr(rd, Address(PC, target(L.label) - pc() - 8));
562 }
563
564 void bind_literal(InlinedAddress& L) {
565 bind(L.label);
566 assert(L.rspec().type() != relocInfo::metadata_type, "Must use InlinedMetadata");
567 // We currently do not use oop 'bound' literals.
568 // If the code evolves and the following assert is triggered,
569 // we need to implement InlinedOop (see InlinedMetadata).
570 assert(L.rspec().type() != relocInfo::oop_type, "Inlined oops not supported");
571 // Note: relocation is handled by relocate calls in ldr_literal
572 AbstractAssembler::emit_address((address)L.target());
573 }
574
575 void bind_literal(InlinedString& L) {
576 const char* msg = L.msg();
577 if (code()->consts()->contains((address)msg)) {
578 // The Label should not be used; avoid binding it
579 // to detect errors.
580 return;
581 }
582 bind(L.label);
583 AbstractAssembler::emit_address((address)L.msg());
584 }
585
586 void bind_literal(InlinedMetadata& L) {
587 bind(L.label);
588 relocate(metadata_Relocation::spec_for_immediate());
589 AbstractAssembler::emit_address((address)L.data());
590 }
591
592 void ldr_label(Register rd, Label& L) {
593 ldr(rd, Address(PC, target(L) - pc() - 8));
594 }
595
596 void resolve_oop_handle(Register result);
597 void load_mirror(Register mirror, Register method, Register tmp);
598
599 void enter() {
600 raw_push(FP, LR);
601 mov(FP, SP);
602 }
603
604 void leave() {
605 mov(SP, FP);
606 raw_pop(FP, LR);
607 }
608
609 #define ARM_INSTR_1(common_mnemonic, arm32_mnemonic, arg_type) \
610 void common_mnemonic(arg_type arg) { \
611 arm32_mnemonic(arg); \
612 }
613
614 #define ARM_INSTR_2(common_mnemonic, arm32_mnemonic, arg1_type, arg2_type) \
615 void common_mnemonic(arg1_type arg1, arg2_type arg2) { \
616 arm32_mnemonic(arg1, arg2); \
617 }
618
619 #define ARM_INSTR_3(common_mnemonic, arm32_mnemonic, arg1_type, arg2_type, arg3_type) \
620 void common_mnemonic(arg1_type arg1, arg2_type arg2, arg3_type arg3) { \
621 arm32_mnemonic(arg1, arg2, arg3); \
622 }
623
624 ARM_INSTR_1(jump, bx, Register)
625 ARM_INSTR_1(call, blx, Register)
626
627 ARM_INSTR_2(cbz_32, cbz, Register, Label&)
628 ARM_INSTR_2(cbnz_32, cbnz, Register, Label&)
629
630 ARM_INSTR_2(ldr_u32, ldr, Register, Address)
631 ARM_INSTR_2(ldr_s32, ldr, Register, Address)
632 ARM_INSTR_2(str_32, str, Register, Address)
633
634 ARM_INSTR_2(mvn_32, mvn, Register, Register)
635 ARM_INSTR_2(cmp_32, cmp, Register, Register)
636 ARM_INSTR_2(neg_32, neg, Register, Register)
637 ARM_INSTR_2(clz_32, clz, Register, Register)
638 ARM_INSTR_2(rbit_32, rbit, Register, Register)
639
640 ARM_INSTR_2(cmp_32, cmp, Register, int)
641 ARM_INSTR_2(cmn_32, cmn, Register, int)
642
643 ARM_INSTR_3(add_32, add, Register, Register, Register)
644 ARM_INSTR_3(sub_32, sub, Register, Register, Register)
645 ARM_INSTR_3(subs_32, subs, Register, Register, Register)
646 ARM_INSTR_3(mul_32, mul, Register, Register, Register)
647 ARM_INSTR_3(and_32, andr, Register, Register, Register)
648 ARM_INSTR_3(orr_32, orr, Register, Register, Register)
649 ARM_INSTR_3(eor_32, eor, Register, Register, Register)
650
651 ARM_INSTR_3(add_32, add, Register, Register, AsmOperand)
652 ARM_INSTR_3(sub_32, sub, Register, Register, AsmOperand)
653 ARM_INSTR_3(orr_32, orr, Register, Register, AsmOperand)
654 ARM_INSTR_3(eor_32, eor, Register, Register, AsmOperand)
655 ARM_INSTR_3(and_32, andr, Register, Register, AsmOperand)
656
657
658 ARM_INSTR_3(add_32, add, Register, Register, int)
659 ARM_INSTR_3(adds_32, adds, Register, Register, int)
660 ARM_INSTR_3(sub_32, sub, Register, Register, int)
661 ARM_INSTR_3(subs_32, subs, Register, Register, int)
662
663 ARM_INSTR_2(tst_32, tst, Register, unsigned int)
664 ARM_INSTR_2(tst_32, tst, Register, AsmOperand)
665
666 ARM_INSTR_3(and_32, andr, Register, Register, uint)
667 ARM_INSTR_3(orr_32, orr, Register, Register, uint)
668 ARM_INSTR_3(eor_32, eor, Register, Register, uint)
669
670 ARM_INSTR_1(cmp_zero_float, fcmpzs, FloatRegister)
671 ARM_INSTR_1(cmp_zero_double, fcmpzd, FloatRegister)
672
673 ARM_INSTR_2(ldr_float, flds, FloatRegister, Address)
674 ARM_INSTR_2(str_float, fsts, FloatRegister, Address)
675 ARM_INSTR_2(mov_float, fcpys, FloatRegister, FloatRegister)
676 ARM_INSTR_2(neg_float, fnegs, FloatRegister, FloatRegister)
677 ARM_INSTR_2(abs_float, fabss, FloatRegister, FloatRegister)
678 ARM_INSTR_2(sqrt_float, fsqrts, FloatRegister, FloatRegister)
679 ARM_INSTR_2(cmp_float, fcmps, FloatRegister, FloatRegister)
680
681 ARM_INSTR_3(add_float, fadds, FloatRegister, FloatRegister, FloatRegister)
682 ARM_INSTR_3(sub_float, fsubs, FloatRegister, FloatRegister, FloatRegister)
683 ARM_INSTR_3(mul_float, fmuls, FloatRegister, FloatRegister, FloatRegister)
684 ARM_INSTR_3(div_float, fdivs, FloatRegister, FloatRegister, FloatRegister)
685
686 ARM_INSTR_2(ldr_double, fldd, FloatRegister, Address)
687 ARM_INSTR_2(str_double, fstd, FloatRegister, Address)
688 ARM_INSTR_2(mov_double, fcpyd, FloatRegister, FloatRegister)
689 ARM_INSTR_2(neg_double, fnegd, FloatRegister, FloatRegister)
690 ARM_INSTR_2(cmp_double, fcmpd, FloatRegister, FloatRegister)
691 ARM_INSTR_2(abs_double, fabsd, FloatRegister, FloatRegister)
692 ARM_INSTR_2(sqrt_double, fsqrtd, FloatRegister, FloatRegister)
693
694 ARM_INSTR_3(add_double, faddd, FloatRegister, FloatRegister, FloatRegister)
695 ARM_INSTR_3(sub_double, fsubd, FloatRegister, FloatRegister, FloatRegister)
696 ARM_INSTR_3(mul_double, fmuld, FloatRegister, FloatRegister, FloatRegister)
697 ARM_INSTR_3(div_double, fdivd, FloatRegister, FloatRegister, FloatRegister)
698
699 ARM_INSTR_2(convert_f2d, fcvtds, FloatRegister, FloatRegister)
700 ARM_INSTR_2(convert_d2f, fcvtsd, FloatRegister, FloatRegister)
701
702 ARM_INSTR_2(mov_fpr2gpr_float, fmrs, Register, FloatRegister)
703
704 #undef ARM_INSTR_1
705 #undef ARM_INSTR_2
706 #undef ARM_INSTR_3
707
708
709
710 void tbz(Register rt, int bit, Label& L) {
711 assert(0 <= bit && bit < BitsPerWord, "bit number is out of range");
712 tst(rt, 1 << bit);
713 b(L, eq);
714 }
715
716 void tbnz(Register rt, int bit, Label& L) {
717 assert(0 <= bit && bit < BitsPerWord, "bit number is out of range");
718 tst(rt, 1 << bit);
719 b(L, ne);
720 }
721
722 void cbz(Register rt, Label& L) {
723 cmp(rt, 0);
724 b(L, eq);
725 }
726
727 void cbz(Register rt, address target) {
728 cmp(rt, 0);
729 b(target, eq);
730 }
731
732 void cbnz(Register rt, Label& L) {
733 cmp(rt, 0);
734 b(L, ne);
735 }
736
737 void ret(Register dst = LR) {
738 bx(dst);
739 }
740
741
742 Register zero_register(Register tmp) {
743 mov(tmp, 0);
744 return tmp;
745 }
746
747 void logical_shift_left(Register dst, Register src, int shift) {
748 mov(dst, AsmOperand(src, lsl, shift));
749 }
750
751 void logical_shift_left_32(Register dst, Register src, int shift) {
752 mov(dst, AsmOperand(src, lsl, shift));
753 }
754
755 void logical_shift_right(Register dst, Register src, int shift) {
756 mov(dst, AsmOperand(src, lsr, shift));
757 }
758
759 void arith_shift_right(Register dst, Register src, int shift) {
760 mov(dst, AsmOperand(src, asr, shift));
761 }
762
763 void asr_32(Register dst, Register src, int shift) {
764 mov(dst, AsmOperand(src, asr, shift));
765 }
766
767 // If <cond> holds, compares r1 and r2. Otherwise, flags are set so that <cond> does not hold.
768 void cond_cmp(Register r1, Register r2, AsmCondition cond) {
769 cmp(r1, r2, cond);
770 }
771
772 // If <cond> holds, compares r and imm. Otherwise, flags are set so that <cond> does not hold.
773 void cond_cmp(Register r, int imm, AsmCondition cond) {
774 cmp(r, imm, cond);
775 }
776
777 void align_reg(Register dst, Register src, int align) {
778 assert (is_power_of_2(align), "should be");
779 bic(dst, src, align-1);
780 }
781
782 void prefetch_read(Address addr) {
783 pld(addr);
784 }
785
786 void raw_push(Register r1, Register r2) {
787 assert(r1->encoding() < r2->encoding(), "should be ordered");
788 push(RegisterSet(r1) | RegisterSet(r2));
789 }
790
791 void raw_pop(Register r1, Register r2) {
792 assert(r1->encoding() < r2->encoding(), "should be ordered");
793 pop(RegisterSet(r1) | RegisterSet(r2));
794 }
795
796 void raw_push(Register r1, Register r2, Register r3) {
797 assert(r1->encoding() < r2->encoding() && r2->encoding() < r3->encoding(), "should be ordered");
798 push(RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3));
799 }
800
801 void raw_pop(Register r1, Register r2, Register r3) {
802 assert(r1->encoding() < r2->encoding() && r2->encoding() < r3->encoding(), "should be ordered");
803 pop(RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3));
804 }
805
806 // Restores registers r1 and r2 previously saved by raw_push(r1, r2, ret_addr) and returns by ret_addr. Clobbers LR.
807 void raw_pop_and_ret(Register r1, Register r2) {
808 raw_pop(r1, r2, PC);
809 }
810
811 void indirect_jump(Address addr, Register scratch) {
812 ldr(PC, addr);
813 }
814
815 void indirect_jump(InlinedAddress& literal, Register scratch) {
816 ldr_literal(PC, literal);
817 }
818
819 void neg(Register dst, Register src) {
820 rsb(dst, src, 0);
821 }
822
823 void branch_if_negative_32(Register r, Label& L) {
824 // TODO: This function and branch_if_any_negative_32 could possibly
825 // be revised after the aarch64 removal.
826 // tbnz is not used instead of tst & b.mi because destination may be out of tbnz range (+-32KB)
827 // since these methods are used in LIR_Assembler::emit_arraycopy() to jump to stub entry.
828 tst_32(r, r);
829 b(L, mi);
830 }
831
832 void branch_if_any_negative_32(Register r1, Register r2, Register tmp, Label& L) {
833 orrs(tmp, r1, r2);
834 b(L, mi);
835 }
836
837 void branch_if_any_negative_32(Register r1, Register r2, Register r3, Register tmp, Label& L) {
838 orr_32(tmp, r1, r2);
839 orrs(tmp, tmp, r3);
840 b(L, mi);
841 }
842
843 void add_ptr_scaled_int32(Register dst, Register r1, Register r2, int shift) {
844 add(dst, r1, AsmOperand(r2, lsl, shift));
845 }
846
847 void sub_ptr_scaled_int32(Register dst, Register r1, Register r2, int shift) {
848 sub(dst, r1, AsmOperand(r2, lsl, shift));
849 }
850
851 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
852 void c2bool(Register x);
853
854 // klass oop manipulations if compressed
855
856 void load_klass(Register dst_klass, Register src_oop, AsmCondition cond = al);
857
858 void store_klass(Register src_klass, Register dst_oop);
859
860
861 // oop manipulations
862
863 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg, Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
864 void store_heap_oop(Address obj, Register new_val, Register tmp1 = noreg, Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
865 void store_heap_oop_null(Address obj, Register new_val, Register tmp1 = noreg, Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
866
867 void access_load_at(BasicType type, DecoratorSet decorators, Address src, Register dst, Register tmp1, Register tmp2, Register tmp3);
868 void access_store_at(BasicType type, DecoratorSet decorators, Address obj, Register new_val, Register tmp1, Register tmp2, Register tmp3, bool is_null);
869
870 void ldr_global_ptr(Register reg, address address_of_global);
871 void ldr_global_s32(Register reg, address address_of_global);
872 void ldrb_global(Register reg, address address_of_global);
873
874 // address_placeholder_instruction is invalid instruction and is used
875 // as placeholder in code for address of label
876 enum { address_placeholder_instruction = 0xFFFFFFFF };
877
878 void emit_address(Label& L) {
879 assert(!L.is_bound(), "otherwise address will not be patched");
880 target(L); // creates relocation which will be patched later
881
882 assert ((offset() & (wordSize-1)) == 0, "should be aligned by word size");
883
884 AbstractAssembler::emit_address((address)address_placeholder_instruction);
885 }
886
887 void b(address target, AsmCondition cond = al) {
888 Assembler::b(target, cond); \
889 }
890 void b(Label& L, AsmCondition cond = al) {
891 // internal jumps
892 Assembler::b(target(L), cond);
893 }
894
895 void bl(address target, AsmCondition cond = al) {
896 Assembler::bl(target, cond);
897 }
898 void bl(Label& L, AsmCondition cond = al) {
899 // internal calls
900 Assembler::bl(target(L), cond);
901 }
902
903 void adr(Register dest, Label& L, AsmCondition cond = al) {
904 int delta = target(L) - pc() - 8;
905 if (delta >= 0) {
906 add(dest, PC, delta, cond);
907 } else {
908 sub(dest, PC, -delta, cond);
909 }
910 }
911
912 // Variable-length jump and calls. We now distinguish only the
913 // patchable case from the other cases. Patchable must be
914 // distinguised from relocable. Relocable means the generated code
915 // containing the jump/call may move. Patchable means that the
916 // targeted address may be changed later.
917
918 // Non patchable versions.
919 // - used only for relocInfo::runtime_call_type and relocInfo::none
920 // - may use relative or absolute format (do not use relocInfo::none
921 // if the generated code may move)
922 // - the implementation takes into account switch to THUMB mode if the
923 // destination is a THUMB address
924 // - the implementation supports far targets
925 //
926 // To reduce regression risk, scratch still defaults to noreg on
927 // arm32. This results in patchable instructions. However, if
928 // patching really matters, the call sites should be modified and
929 // use patchable_call or patchable_jump. If patching is not required
930 // and if a register can be cloberred, it should be explicitly
931 // specified to allow future optimizations.
932 void jump(address target,
933 relocInfo::relocType rtype = relocInfo::runtime_call_type,
934 Register scratch = noreg, AsmCondition cond = al);
935
936 void call(address target,
937 RelocationHolder rspec, AsmCondition cond = al);
938
939 void call(address target,
940 relocInfo::relocType rtype = relocInfo::runtime_call_type,
941 AsmCondition cond = al) {
942 call(target, Relocation::spec_simple(rtype), cond);
943 }
944
945 void jump(AddressLiteral dest) {
946 jump(dest.target(), dest.reloc());
947 }
948 void jump(address dest, relocInfo::relocType rtype, AsmCondition cond) {
949 jump(dest, rtype, Rtemp, cond);
950 }
951
952 void call(AddressLiteral dest) {
953 call(dest.target(), dest.reloc());
954 }
955
956 // Patchable version:
957 // - set_destination can be used to atomically change the target
958 //
959 // The targets for patchable_jump and patchable_call must be in the
960 // code cache.
961 // [ including possible extensions of the code cache, like AOT code ]
962 //
963 // To reduce regression risk, scratch still defaults to noreg on
964 // arm32. If a register can be cloberred, it should be explicitly
965 // specified to allow future optimizations.
966 void patchable_jump(address target,
967 relocInfo::relocType rtype = relocInfo::runtime_call_type,
968 Register scratch = noreg, AsmCondition cond = al
969 );
970
971 // patchable_call may scratch Rtemp
972 int patchable_call(address target,
973 RelocationHolder const& rspec,
974 bool c2 = false);
975
976 int patchable_call(address target,
977 relocInfo::relocType rtype,
978 bool c2 = false) {
979 return patchable_call(target, Relocation::spec_simple(rtype), c2);
980 }
981
982
983 static bool _reachable_from_cache(address target);
984 static bool _cache_fully_reachable();
985 bool cache_fully_reachable();
986 bool reachable_from_cache(address target);
987
988 void zero_extend(Register rd, Register rn, int bits);
989 void sign_extend(Register rd, Register rn, int bits);
990
991 inline void zap_high_non_significant_bits(Register r) {
992 }
993
994 void cmpoop(Register obj1, Register obj2);
995
996 void long_move(Register rd_lo, Register rd_hi,
997 Register rn_lo, Register rn_hi,
998 AsmCondition cond = al);
999 void long_shift(Register rd_lo, Register rd_hi,
1000 Register rn_lo, Register rn_hi,
1001 AsmShift shift, Register count);
1002 void long_shift(Register rd_lo, Register rd_hi,
1003 Register rn_lo, Register rn_hi,
1004 AsmShift shift, int count);
1005
1006 void atomic_cas(Register tmpreg1, Register tmpreg2, Register oldval, Register newval, Register base, int offset);
1007 void atomic_cas_bool(Register oldval, Register newval, Register base, int offset, Register tmpreg);
1008 void atomic_cas64(Register temp_lo, Register temp_hi, Register temp_result, Register oldval_lo, Register oldval_hi, Register newval_lo, Register newval_hi, Register base, int offset);
1009
1010 void cas_for_lock_acquire(Register oldval, Register newval, Register base, Register tmp, Label &slow_case, bool allow_fallthrough_on_failure = false, bool one_shot = false);
1011 void cas_for_lock_release(Register oldval, Register newval, Register base, Register tmp, Label &slow_case, bool allow_fallthrough_on_failure = false, bool one_shot = false);
1012
1013 // Attempt to fast-lock an object
1014 // Registers:
1015 // - obj: the object to be locked
1016 // - t1, t2, t3: temp registers. If corresponding bit in savemask is set, they get saved, otherwise blown.
1017 // Result:
1018 // - Success: fallthrough
1019 // - Error: break to slow, Z cleared.
1020 void fast_lock(Register obj, Register t1, Register t2, Register t3, unsigned savemask, Label& slow);
1021
1022 // Attempt to fast-unlock an object
1023 // Registers:
1024 // - obj: the object to be unlocked
1025 // - t1, t2, t3: temp registers. If corresponding bit in savemask is set, they get saved, otherwise blown.
1026 // Result:
1027 // - Success: fallthrough
1028 // - Error: break to slow, Z cleared.
1029 void fast_unlock(Register obj, Register t1, Register t2, Register t3, unsigned savemask, Label& slow);
1030
1031 #ifndef PRODUCT
1032 // Preserves flags and all registers.
1033 // On SMP the updated value might not be visible to external observers without a synchronization barrier
1034 void cond_atomic_inc32(AsmCondition cond, int* counter_addr);
1035 #endif // !PRODUCT
1036
1037 // unconditional non-atomic increment
1038 void inc_counter(address counter_addr, Register tmpreg1, Register tmpreg2);
1039 void inc_counter(uint* counter_addr, Register tmpreg1, Register tmpreg2) {
1040 inc_counter((address) counter_addr, tmpreg1, tmpreg2);
1041 }
1042
1043 void pd_patch_instruction(address branch, address target, const char* file, int line);
1044
1045 // Loading and storing values by size and signed-ness;
1046 // size must not exceed wordSize (i.e. 8-byte values are not supported on 32-bit ARM);
1047 // each of these calls generates exactly one load or store instruction,
1048 // so src can be pre- or post-indexed address.
1049 // 32-bit ARM variants also support conditional execution
1050 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, AsmCondition cond = al);
1051 void store_sized_value(Register src, Address dst, size_t size_in_bytes, AsmCondition cond = al);
1052
1053 void lookup_interface_method(Register recv_klass,
1054 Register intf_klass,
1055 RegisterOrConstant itable_index,
1056 Register method_result,
1057 Register temp_reg1,
1058 Register temp_reg2,
1059 Label& L_no_such_interface);
1060
1061
1062 void floating_cmp(Register dst);
1063
1064 // improved x86 portability (minimizing source code changes)
1065
1066 void ldr_literal(Register rd, AddressLiteral addr) {
1067 relocate(addr.rspec());
1068 ldr(rd, Address(PC, addr.target() - pc() - 8));
1069 }
1070
1071 void lea(Register Rd, AddressLiteral addr) {
1072 // Never dereferenced, as on x86 (lval status ignored)
1073 mov_address(Rd, addr.target(), addr.rspec());
1074 }
1075
1076 void restore_default_fp_mode();
1077
1078 void safepoint_poll(Register tmp1, Label& slow_path);
1079 void get_polling_page(Register dest);
1080 void read_polling_page(Register dest, relocInfo::relocType rtype);
1081
1082 static int ic_check_size();
1083 int ic_check(int end_alignment);
1084 };
1085
1086
1087 // The purpose of this class is to build several code fragments of the same size
1088 // in order to allow fast table branch.
1089
1090 class FixedSizeCodeBlock {
1091 public:
1092 FixedSizeCodeBlock(MacroAssembler* masm, int size_in_instrs, bool enabled);
1093 ~FixedSizeCodeBlock();
1094
1095 private:
1096 MacroAssembler* _masm;
1097 address _start;
1098 int _size_in_instrs;
1099 bool _enabled;
1100 };
1101
1102
1103 #endif // CPU_ARM_MACROASSEMBLER_ARM_HPP