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/*
! * Copyright (c) 2008, 2025, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
/*
! * Copyright (c) 2008, 2026, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
__ pop(RegisterSet(R0, R3) | R9 | LR);
__ bind(skip);
}
! void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
! int total_args_passed, int comp_args_on_stack,
- const BasicType *sig_bt, const VMRegPair *regs) {
// TODO: ARM - May be can use ldm to load arguments
const Register tmp = Rtemp; // avoid erasing R5_mh
// Next assert may not be needed but safer. Extra analysis required
// if this there is not enough free registers and we need to use R5 here.
__ pop(RegisterSet(R0, R3) | R9 | LR);
__ bind(skip);
}
! void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm, int comp_args_on_stack, const GrowableArray<SigEntry>* sig, const VMRegPair *regs) {
!
// TODO: ARM - May be can use ldm to load arguments
const Register tmp = Rtemp; // avoid erasing R5_mh
// Next assert may not be needed but safer. Extra analysis required
// if this there is not enough free registers and we need to use R5 here.
if (comp_args_on_stack) {
__ sub_slow(SP, SP, comp_args_on_stack * VMRegImpl::stack_slot_size);
}
__ bic(SP, SP, StackAlignmentInBytes - 1);
for (int i = 0; i < total_args_passed; i++) {
! if (sig_bt[i] == T_VOID) {
! assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
continue;
}
assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), "must be ordered");
int arg_offset = Interpreter::expr_offset_in_bytes(total_args_passed - 1 - i);
if (comp_args_on_stack) {
__ sub_slow(SP, SP, comp_args_on_stack * VMRegImpl::stack_slot_size);
}
__ bic(SP, SP, StackAlignmentInBytes - 1);
+ int total_args_passed = sig->length();
for (int i = 0; i < total_args_passed; i++) {
! BasicType bt = sig->at(i)._bt;
! if (bt == T_VOID) {
+ assert(i > 0 && (sig->at(i - 1)._bt == T_LONG || sig->at(i - 1)._bt == T_DOUBLE), "missing half");
continue;
}
assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), "must be ordered");
int arg_offset = Interpreter::expr_offset_in_bytes(total_args_passed - 1 - i);
__ ldr(Rmethod, callee_target_addr);
__ ldr(PC, Address(Rmethod, Method::from_compiled_offset()));
}
! static void gen_c2i_adapter(MacroAssembler *masm,
- int total_args_passed, int comp_args_on_stack,
- const BasicType *sig_bt, const VMRegPair *regs,
Label& skip_fixup) {
// TODO: ARM - May be can use stm to deoptimize arguments
const Register tmp = Rtemp;
patch_callers_callsite(masm);
__ bind(skip_fixup);
__ mov(Rsender_sp, SP); // not yet saved
int extraspace = total_args_passed * Interpreter::stackElementSize;
if (extraspace) {
__ sub_slow(SP, SP, extraspace);
}
for (int i = 0; i < total_args_passed; i++) {
! if (sig_bt[i] == T_VOID) {
! assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
continue;
}
int stack_offset = (total_args_passed - 1 - i) * Interpreter::stackElementSize;
VMReg r_1 = regs[i].first();
__ ldr(Rmethod, callee_target_addr);
__ ldr(PC, Address(Rmethod, Method::from_compiled_offset()));
}
! static void gen_c2i_adapter(MacroAssembler *masm, int comp_args_on_stack, const GrowableArray<SigEntry>* sig, const VMRegPair *regs,
Label& skip_fixup) {
// TODO: ARM - May be can use stm to deoptimize arguments
const Register tmp = Rtemp;
patch_callers_callsite(masm);
__ bind(skip_fixup);
__ mov(Rsender_sp, SP); // not yet saved
+ int total_args_passed = sig->length();
int extraspace = total_args_passed * Interpreter::stackElementSize;
if (extraspace) {
__ sub_slow(SP, SP, extraspace);
}
for (int i = 0; i < total_args_passed; i++) {
! BasicType bt = sig->at(i)._bt;
! if (bt == T_VOID) {
+ assert(i > 0 && (sig->at(i - 1)._bt == T_LONG || sig->at(i - 1)._bt == T_DOUBLE), "missing half");
continue;
}
int stack_offset = (total_args_passed - 1 - i) * Interpreter::stackElementSize;
VMReg r_1 = regs[i].first();
__ ldr(PC, Address(Rmethod, Method::interpreter_entry_offset()));
}
! void SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
- int total_args_passed,
int comp_args_on_stack,
! const BasicType *sig_bt,
! const VMRegPair *regs,
! address entry_address[AdapterBlob::ENTRY_COUNT]) {
entry_address[AdapterBlob::I2C] = __ pc();
! gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
entry_address[AdapterBlob::C2I_Unverified] = __ pc();
Label skip_fixup;
const Register receiver = R0;
const Register holder_klass = Rtemp; // XXX should be OK for C2 but not 100% sure
__ ldr(PC, Address(Rmethod, Method::interpreter_entry_offset()));
}
! void SharedRuntime::generate_i2c2i_adapters(MacroAssembler* masm,
int comp_args_on_stack,
! const GrowableArray<SigEntry>* sig,
! const VMRegPair* regs,
! const GrowableArray<SigEntry>* sig_cc,
+ const VMRegPair* regs_cc,
+ const GrowableArray<SigEntry>* sig_cc_ro,
+ const VMRegPair* regs_cc_ro,
+ address entry_address[AdapterBlob::ENTRY_COUNT],
+ AdapterBlob*& new_adapter,
+ bool allocate_code_blob) {
+
entry_address[AdapterBlob::I2C] = __ pc();
! gen_i2c_adapter(masm, comp_args_on_stack, sig, regs);
entry_address[AdapterBlob::C2I_Unverified] = __ pc();
Label skip_fixup;
const Register receiver = R0;
const Register holder_klass = Rtemp; // XXX should be OK for C2 but not 100% sure
__ b(skip_fixup, eq);
__ jump(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type, noreg, ne);
entry_address[AdapterBlob::C2I] = __ pc();
entry_address[AdapterBlob::C2I_No_Clinit_Check] = nullptr;
! gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
return;
}
static int reg2offset_in(VMReg r) {
__ b(skip_fixup, eq);
__ jump(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type, noreg, ne);
entry_address[AdapterBlob::C2I] = __ pc();
entry_address[AdapterBlob::C2I_No_Clinit_Check] = nullptr;
! gen_c2i_adapter(masm, comp_args_on_stack, sig, regs, skip_fixup);
return;
}
static int reg2offset_in(VMReg r) {
false);
return stub;
}
#endif // INCLUDE_JFR
+
+ const uint SharedRuntime::java_return_convention_max_int = 0; // Argument::n_int_register_parameters_j;
+ const uint SharedRuntime::java_return_convention_max_float = 0; // Argument::n_float_register_parameters_j;
+
+ int SharedRuntime::java_return_convention(const BasicType *sig_bt, VMRegPair *regs, int total_args_passed) {
+ Unimplemented();
+ return 0;
+ }
+
+ BufferedInlineTypeBlob* SharedRuntime::generate_buffered_inline_type_adapter(const InlineKlass* vk) {
+ Unimplemented();
+ return nullptr;
+ }
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