1 /*
2 * Copyright (c) 2008, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.inline.hpp"
26 #include "code/compiledIC.hpp"
27 #include "code/debugInfoRec.hpp"
28 #include "code/vtableStubs.hpp"
29 #include "compiler/oopMap.hpp"
30 #include "gc/shared/barrierSetAssembler.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "logging/log.hpp"
33 #include "memory/resourceArea.hpp"
34 #include "oops/klass.inline.hpp"
35 #include "prims/methodHandles.hpp"
36 #include "runtime/jniHandles.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/safepointMechanism.hpp"
39 #include "runtime/stubRoutines.hpp"
40 #include "runtime/timerTrace.hpp"
41 #include "runtime/vframeArray.hpp"
42 #include "utilities/align.hpp"
43 #include "utilities/powerOfTwo.hpp"
44 #include "vmreg_arm.inline.hpp"
45 #ifdef COMPILER1
46 #include "c1/c1_Runtime1.hpp"
47 #endif
48 #ifdef COMPILER2
49 #include "opto/runtime.hpp"
50 #endif
51
52 #define __ masm->
53
54 class RegisterSaver {
55 public:
56
57 // Special registers:
58 // 32-bit ARM 64-bit ARM
59 // Rthread: R10 R28
60 // LR: R14 R30
61
62 // Rthread is callee saved in the C ABI and never changed by compiled code:
63 // no need to save it.
64
65 // 2 slots for LR: the one at LR_offset and an other one at R14/R30_offset.
66 // The one at LR_offset is a return address that is needed by stack walking.
67 // A c2 method uses LR as a standard register so it may be live when we
68 // branch to the runtime. The slot at R14/R30_offset is for the value of LR
69 // in case it's live in the method we are coming from.
70
71
72 enum RegisterLayout {
73 fpu_save_size = FloatRegister::number_of_registers,
74 #ifndef __SOFTFP__
75 D0_offset = 0,
76 #endif
77 R0_offset = fpu_save_size,
78 R1_offset,
79 R2_offset,
80 R3_offset,
81 R4_offset,
82 R5_offset,
83 R6_offset,
84 #if (FP_REG_NUM != 7)
85 // if not saved as FP
86 R7_offset,
87 #endif
88 R8_offset,
89 R9_offset,
90 #if (FP_REG_NUM != 11)
91 // if not saved as FP
92 R11_offset,
93 #endif
94 R12_offset,
95 R14_offset,
96 FP_offset,
97 LR_offset,
98 reg_save_size,
99
100 Rmethod_offset = R9_offset,
101 Rtemp_offset = R12_offset,
102 };
103
104 // all regs but Rthread (R10), FP (R7 or R11), SP and PC
105 // (altFP_7_11 is the one among R7 and R11 which is not FP)
106 #define SAVED_BASE_REGS (RegisterSet(R0, R6) | RegisterSet(R8, R9) | RegisterSet(R12) | R14 | altFP_7_11)
107
108
109 // When LR may be live in the nmethod from which we are coming
110 // then lr_saved is true, the return address is saved before the
111 // call to save_live_register by the caller and LR contains the
112 // live value.
113
114 static OopMap* save_live_registers(MacroAssembler* masm,
115 int* total_frame_words,
116 bool lr_saved = false);
117 static void restore_live_registers(MacroAssembler* masm, bool restore_lr = true);
118
119 };
120
121
122
123
124 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm,
125 int* total_frame_words,
126 bool lr_saved) {
127 *total_frame_words = reg_save_size;
128
129 OopMapSet *oop_maps = new OopMapSet();
130 OopMap* map = new OopMap(VMRegImpl::slots_per_word * (*total_frame_words), 0);
131
132 if (lr_saved) {
133 __ push(RegisterSet(FP));
134 } else {
135 __ push(RegisterSet(FP) | RegisterSet(LR));
136 }
137 __ push(SAVED_BASE_REGS);
138 if (HaveVFP) {
139 if (VM_Version::has_vfp3_32()) {
140 __ fpush(FloatRegisterSet(D16, 16));
141 } else {
142 if (FloatRegister::number_of_registers > 32) {
143 assert(FloatRegister::number_of_registers == 64, "nb fp registers should be 64");
144 __ sub(SP, SP, 32 * wordSize);
145 }
146 }
147 __ fpush(FloatRegisterSet(D0, 16));
148 } else {
149 __ sub(SP, SP, fpu_save_size * wordSize);
150 }
151
152 int i;
153 int j=0;
154 for (i = R0_offset; i <= R9_offset; i++) {
155 if (j == FP_REG_NUM) {
156 // skip the FP register, managed below.
157 j++;
158 }
159 map->set_callee_saved(VMRegImpl::stack2reg(i), as_Register(j)->as_VMReg());
160 j++;
161 }
162 assert(j == R10->encoding(), "must be");
163 #if (FP_REG_NUM != 11)
164 // add R11, if not managed as FP
165 map->set_callee_saved(VMRegImpl::stack2reg(R11_offset), R11->as_VMReg());
166 #endif
167 map->set_callee_saved(VMRegImpl::stack2reg(R12_offset), R12->as_VMReg());
168 map->set_callee_saved(VMRegImpl::stack2reg(R14_offset), R14->as_VMReg());
169 if (HaveVFP) {
170 for (i = 0; i < (VM_Version::has_vfp3_32() ? 64 : 32); i+=2) {
171 map->set_callee_saved(VMRegImpl::stack2reg(i), as_FloatRegister(i)->as_VMReg());
172 map->set_callee_saved(VMRegImpl::stack2reg(i + 1), as_FloatRegister(i)->as_VMReg()->next());
173 }
174 }
175
176 return map;
177 }
178
179 void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_lr) {
180 if (HaveVFP) {
181 __ fpop(FloatRegisterSet(D0, 16));
182 if (VM_Version::has_vfp3_32()) {
183 __ fpop(FloatRegisterSet(D16, 16));
184 } else {
185 if (FloatRegister::number_of_registers > 32) {
186 assert(FloatRegister::number_of_registers == 64, "nb fp registers should be 64");
187 __ add(SP, SP, 32 * wordSize);
188 }
189 }
190 } else {
191 __ add(SP, SP, fpu_save_size * wordSize);
192 }
193 __ pop(SAVED_BASE_REGS);
194 if (restore_lr) {
195 __ pop(RegisterSet(FP) | RegisterSet(LR));
196 } else {
197 __ pop(RegisterSet(FP));
198 }
199 }
200
201
202 static void push_result_registers(MacroAssembler* masm, BasicType ret_type) {
203 #ifdef __ABI_HARD__
204 if (ret_type == T_DOUBLE || ret_type == T_FLOAT) {
205 __ sub(SP, SP, 8);
206 __ fstd(D0, Address(SP));
207 return;
208 }
209 #endif // __ABI_HARD__
210 __ raw_push(R0, R1);
211 }
212
213 static void pop_result_registers(MacroAssembler* masm, BasicType ret_type) {
214 #ifdef __ABI_HARD__
215 if (ret_type == T_DOUBLE || ret_type == T_FLOAT) {
216 __ fldd(D0, Address(SP));
217 __ add(SP, SP, 8);
218 return;
219 }
220 #endif // __ABI_HARD__
221 __ raw_pop(R0, R1);
222 }
223
224 static void push_param_registers(MacroAssembler* masm, int fp_regs_in_arguments) {
225 // R1-R3 arguments need to be saved, but we push 4 registers for 8-byte alignment
226 __ push(RegisterSet(R0, R3));
227
228 // preserve arguments
229 // Likely not needed as the locking code won't probably modify volatile FP registers,
230 // but there is no way to guarantee that
231 if (fp_regs_in_arguments) {
232 // convert fp_regs_in_arguments to a number of double registers
233 int double_regs_num = (fp_regs_in_arguments + 1) >> 1;
234 __ fpush_hardfp(FloatRegisterSet(D0, double_regs_num));
235 }
236 }
237
238 static void pop_param_registers(MacroAssembler* masm, int fp_regs_in_arguments) {
239 if (fp_regs_in_arguments) {
240 int double_regs_num = (fp_regs_in_arguments + 1) >> 1;
241 __ fpop_hardfp(FloatRegisterSet(D0, double_regs_num));
242 }
243 __ pop(RegisterSet(R0, R3));
244 }
245
246
247
248 // Is vector's size (in bytes) bigger than a size saved by default?
249 // All vector registers are saved by default on ARM.
250 bool SharedRuntime::is_wide_vector(int size) {
251 return false;
252 }
253
254 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
255 VMRegPair *regs,
256 int total_args_passed) {
257 int slot = 0;
258 int ireg = 0;
259 #ifdef __ABI_HARD__
260 int fp_slot = 0;
261 int single_fpr_slot = 0;
262 #endif // __ABI_HARD__
263 for (int i = 0; i < total_args_passed; i++) {
264 switch (sig_bt[i]) {
265 case T_SHORT:
266 case T_CHAR:
267 case T_BYTE:
268 case T_BOOLEAN:
269 case T_INT:
270 case T_ARRAY:
271 case T_OBJECT:
272 case T_ADDRESS:
273 case T_METADATA:
274 #ifndef __ABI_HARD__
275 case T_FLOAT:
276 #endif // !__ABI_HARD__
277 if (ireg < 4) {
278 Register r = as_Register(ireg);
279 regs[i].set1(r->as_VMReg());
280 ireg++;
281 } else {
282 regs[i].set1(VMRegImpl::stack2reg(slot));
283 slot++;
284 }
285 break;
286 case T_LONG:
287 #ifndef __ABI_HARD__
288 case T_DOUBLE:
289 #endif // !__ABI_HARD__
290 assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
291 if (ireg <= 2) {
292 #if (ALIGN_WIDE_ARGUMENTS == 1)
293 if(ireg & 1) ireg++; // Aligned location required
294 #endif
295 Register r1 = as_Register(ireg);
296 Register r2 = as_Register(ireg + 1);
297 regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
298 ireg += 2;
299 #if (ALIGN_WIDE_ARGUMENTS == 0)
300 } else if (ireg == 3) {
301 // uses R3 + one stack slot
302 Register r = as_Register(ireg);
303 regs[i].set_pair(VMRegImpl::stack2reg(slot), r->as_VMReg());
304 ireg += 1;
305 slot += 1;
306 #endif
307 } else {
308 if (slot & 1) slot++; // Aligned location required
309 regs[i].set_pair(VMRegImpl::stack2reg(slot+1), VMRegImpl::stack2reg(slot));
310 slot += 2;
311 ireg = 4;
312 }
313 break;
314 case T_VOID:
315 regs[i].set_bad();
316 break;
317 #ifdef __ABI_HARD__
318 case T_FLOAT:
319 if ((fp_slot < 16)||(single_fpr_slot & 1)) {
320 if ((single_fpr_slot & 1) == 0) {
321 single_fpr_slot = fp_slot;
322 fp_slot += 2;
323 }
324 FloatRegister r = as_FloatRegister(single_fpr_slot);
325 single_fpr_slot++;
326 regs[i].set1(r->as_VMReg());
327 } else {
328 regs[i].set1(VMRegImpl::stack2reg(slot));
329 slot++;
330 }
331 break;
332 case T_DOUBLE:
333 assert(ALIGN_WIDE_ARGUMENTS == 1, "ABI_HARD not supported with unaligned wide arguments");
334 if (fp_slot <= 14) {
335 FloatRegister r1 = as_FloatRegister(fp_slot);
336 FloatRegister r2 = as_FloatRegister(fp_slot+1);
337 regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
338 fp_slot += 2;
339 } else {
340 if(slot & 1) slot++;
341 regs[i].set_pair(VMRegImpl::stack2reg(slot+1), VMRegImpl::stack2reg(slot));
342 slot += 2;
343 single_fpr_slot = 16;
344 }
345 break;
346 #endif // __ABI_HARD__
347 default:
348 ShouldNotReachHere();
349 }
350 }
351 return slot;
352 }
353
354 int SharedRuntime::vector_calling_convention(VMRegPair *regs,
355 uint num_bits,
356 uint total_args_passed) {
357 Unimplemented();
358 return 0;
359 }
360
361 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
362 VMRegPair *regs,
363 int total_args_passed) {
364 #ifdef __SOFTFP__
365 // soft float is the same as the C calling convention.
366 return c_calling_convention(sig_bt, regs, nullptr, total_args_passed);
367 #endif // __SOFTFP__
368 int slot = 0;
369 int ireg = 0;
370 int freg = 0;
371 int single_fpr = 0;
372
373 for (int i = 0; i < total_args_passed; i++) {
374 switch (sig_bt[i]) {
375 case T_SHORT:
376 case T_CHAR:
377 case T_BYTE:
378 case T_BOOLEAN:
379 case T_INT:
380 case T_ARRAY:
381 case T_OBJECT:
382 case T_ADDRESS:
383 if (ireg < 4) {
384 Register r = as_Register(ireg++);
385 regs[i].set1(r->as_VMReg());
386 } else {
387 regs[i].set1(VMRegImpl::stack2reg(slot++));
388 }
389 break;
390 case T_FLOAT:
391 // C2 utilizes S14/S15 for mem-mem moves
392 if ((freg < 16 COMPILER2_PRESENT(-2)) || (single_fpr & 1)) {
393 if ((single_fpr & 1) == 0) {
394 single_fpr = freg;
395 freg += 2;
396 }
397 FloatRegister r = as_FloatRegister(single_fpr++);
398 regs[i].set1(r->as_VMReg());
399 } else {
400 regs[i].set1(VMRegImpl::stack2reg(slot++));
401 }
402 break;
403 case T_DOUBLE:
404 // C2 utilizes S14/S15 for mem-mem moves
405 if (freg <= 14 COMPILER2_PRESENT(-2)) {
406 FloatRegister r1 = as_FloatRegister(freg);
407 FloatRegister r2 = as_FloatRegister(freg + 1);
408 regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
409 freg += 2;
410 } else {
411 // Keep internally the aligned calling convention,
412 // ignoring ALIGN_WIDE_ARGUMENTS
413 if (slot & 1) slot++;
414 regs[i].set_pair(VMRegImpl::stack2reg(slot + 1), VMRegImpl::stack2reg(slot));
415 slot += 2;
416 single_fpr = 16;
417 }
418 break;
419 case T_LONG:
420 // Keep internally the aligned calling convention,
421 // ignoring ALIGN_WIDE_ARGUMENTS
422 if (ireg <= 2) {
423 if (ireg & 1) ireg++;
424 Register r1 = as_Register(ireg);
425 Register r2 = as_Register(ireg + 1);
426 regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
427 ireg += 2;
428 } else {
429 if (slot & 1) slot++;
430 regs[i].set_pair(VMRegImpl::stack2reg(slot + 1), VMRegImpl::stack2reg(slot));
431 slot += 2;
432 ireg = 4;
433 }
434 break;
435 case T_VOID:
436 regs[i].set_bad();
437 break;
438 default:
439 ShouldNotReachHere();
440 }
441 }
442
443 return slot;
444 }
445
446 static void patch_callers_callsite(MacroAssembler *masm) {
447 Label skip;
448
449 __ ldr(Rtemp, Address(Rmethod, Method::code_offset()));
450 __ cbz(Rtemp, skip);
451
452 // Pushing an even number of registers for stack alignment.
453 // Selecting R9, which had to be saved anyway for some platforms.
454 __ push(RegisterSet(R0, R3) | R9 | LR);
455 __ fpush_hardfp(FloatRegisterSet(D0, 8));
456
457 __ mov(R0, Rmethod);
458 __ mov(R1, LR);
459 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
460
461 __ fpop_hardfp(FloatRegisterSet(D0, 8));
462 __ pop(RegisterSet(R0, R3) | R9 | LR);
463
464 __ bind(skip);
465 }
466
467 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm, int comp_args_on_stack, const GrowableArray<SigEntry>* sig, const VMRegPair *regs) {
468
469 // TODO: ARM - May be can use ldm to load arguments
470 const Register tmp = Rtemp; // avoid erasing R5_mh
471
472 // Next assert may not be needed but safer. Extra analysis required
473 // if this there is not enough free registers and we need to use R5 here.
474 assert_different_registers(tmp, R5_mh);
475
476 // 6243940 We might end up in handle_wrong_method if
477 // the callee is deoptimized as we race thru here. If that
478 // happens we don't want to take a safepoint because the
479 // caller frame will look interpreted and arguments are now
480 // "compiled" so it is much better to make this transition
481 // invisible to the stack walking code. Unfortunately if
482 // we try and find the callee by normal means a safepoint
483 // is possible. So we stash the desired callee in the thread
484 // and the vm will find there should this case occur.
485 Address callee_target_addr(Rthread, JavaThread::callee_target_offset());
486 __ str(Rmethod, callee_target_addr);
487
488
489 assert_different_registers(tmp, R0, R1, R2, R3, Rsender_sp, Rmethod);
490
491 const Register initial_sp = Rmethod; // temporarily scratched
492
493 // Old code was modifying R4 but this looks unsafe (particularly with JSR292)
494 assert_different_registers(tmp, R0, R1, R2, R3, Rsender_sp, initial_sp);
495
496 __ mov(initial_sp, SP);
497
498 if (comp_args_on_stack) {
499 __ sub_slow(SP, SP, comp_args_on_stack * VMRegImpl::stack_slot_size);
500 }
501 __ bic(SP, SP, StackAlignmentInBytes - 1);
502
503 int total_args_passed = sig->length();
504 for (int i = 0; i < total_args_passed; i++) {
505 BasicType bt = sig->at(i)._bt;
506 if (bt == T_VOID) {
507 assert(i > 0 && (sig->at(i - 1)._bt == T_LONG || sig->at(i - 1)._bt == T_DOUBLE), "missing half");
508 continue;
509 }
510 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), "must be ordered");
511 int arg_offset = Interpreter::expr_offset_in_bytes(total_args_passed - 1 - i);
512
513 VMReg r_1 = regs[i].first();
514 VMReg r_2 = regs[i].second();
515 if (r_1->is_stack()) {
516 int stack_offset = r_1->reg2stack() * VMRegImpl::stack_slot_size;
517 if (!r_2->is_valid()) {
518 __ ldr(tmp, Address(initial_sp, arg_offset));
519 __ str(tmp, Address(SP, stack_offset));
520 } else {
521 __ ldr(tmp, Address(initial_sp, arg_offset - Interpreter::stackElementSize));
522 __ str(tmp, Address(SP, stack_offset));
523 __ ldr(tmp, Address(initial_sp, arg_offset));
524 __ str(tmp, Address(SP, stack_offset + wordSize));
525 }
526 } else if (r_1->is_Register()) {
527 if (!r_2->is_valid()) {
528 __ ldr(r_1->as_Register(), Address(initial_sp, arg_offset));
529 } else {
530 __ ldr(r_1->as_Register(), Address(initial_sp, arg_offset - Interpreter::stackElementSize));
531 __ ldr(r_2->as_Register(), Address(initial_sp, arg_offset));
532 }
533 } else if (r_1->is_FloatRegister()) {
534 #ifdef __SOFTFP__
535 ShouldNotReachHere();
536 #endif // __SOFTFP__
537 if (!r_2->is_valid()) {
538 __ flds(r_1->as_FloatRegister(), Address(initial_sp, arg_offset));
539 } else {
540 __ fldd(r_1->as_FloatRegister(), Address(initial_sp, arg_offset - Interpreter::stackElementSize));
541 }
542 } else {
543 assert(!r_1->is_valid() && !r_2->is_valid(), "must be");
544 }
545 }
546
547 // restore Rmethod (scratched for initial_sp)
548 __ ldr(Rmethod, callee_target_addr);
549 __ ldr(PC, Address(Rmethod, Method::from_compiled_offset()));
550
551 }
552
553 static void gen_c2i_adapter(MacroAssembler *masm, int comp_args_on_stack, const GrowableArray<SigEntry>* sig, const VMRegPair *regs,
554 Label& skip_fixup) {
555 // TODO: ARM - May be can use stm to deoptimize arguments
556 const Register tmp = Rtemp;
557
558 patch_callers_callsite(masm);
559 __ bind(skip_fixup);
560
561 __ mov(Rsender_sp, SP); // not yet saved
562
563
564 int total_args_passed = sig->length();
565 int extraspace = total_args_passed * Interpreter::stackElementSize;
566 if (extraspace) {
567 __ sub_slow(SP, SP, extraspace);
568 }
569
570 for (int i = 0; i < total_args_passed; i++) {
571 BasicType bt = sig->at(i)._bt;
572 if (bt == T_VOID) {
573 assert(i > 0 && (sig->at(i - 1)._bt == T_LONG || sig->at(i - 1)._bt == T_DOUBLE), "missing half");
574 continue;
575 }
576 int stack_offset = (total_args_passed - 1 - i) * Interpreter::stackElementSize;
577
578 VMReg r_1 = regs[i].first();
579 VMReg r_2 = regs[i].second();
580 if (r_1->is_stack()) {
581 int arg_offset = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
582 if (!r_2->is_valid()) {
583 __ ldr(tmp, Address(SP, arg_offset));
584 __ str(tmp, Address(SP, stack_offset));
585 } else {
586 __ ldr(tmp, Address(SP, arg_offset));
587 __ str(tmp, Address(SP, stack_offset - Interpreter::stackElementSize));
588 __ ldr(tmp, Address(SP, arg_offset + wordSize));
589 __ str(tmp, Address(SP, stack_offset));
590 }
591 } else if (r_1->is_Register()) {
592 if (!r_2->is_valid()) {
593 __ str(r_1->as_Register(), Address(SP, stack_offset));
594 } else {
595 __ str(r_1->as_Register(), Address(SP, stack_offset - Interpreter::stackElementSize));
596 __ str(r_2->as_Register(), Address(SP, stack_offset));
597 }
598 } else if (r_1->is_FloatRegister()) {
599 #ifdef __SOFTFP__
600 ShouldNotReachHere();
601 #endif // __SOFTFP__
602 if (!r_2->is_valid()) {
603 __ fsts(r_1->as_FloatRegister(), Address(SP, stack_offset));
604 } else {
605 __ fstd(r_1->as_FloatRegister(), Address(SP, stack_offset - Interpreter::stackElementSize));
606 }
607 } else {
608 assert(!r_1->is_valid() && !r_2->is_valid(), "must be");
609 }
610 }
611
612 __ ldr(PC, Address(Rmethod, Method::interpreter_entry_offset()));
613
614 }
615
616 void SharedRuntime::generate_i2c2i_adapters(MacroAssembler* masm,
617 int comp_args_on_stack,
618 const GrowableArray<SigEntry>* sig,
619 const VMRegPair* regs,
620 const GrowableArray<SigEntry>* sig_cc,
621 const VMRegPair* regs_cc,
622 const GrowableArray<SigEntry>* sig_cc_ro,
623 const VMRegPair* regs_cc_ro,
624 address entry_address[AdapterBlob::ENTRY_COUNT],
625 AdapterBlob*& new_adapter,
626 bool allocate_code_blob) {
627
628 entry_address[AdapterBlob::I2C] = __ pc();
629 gen_i2c_adapter(masm, comp_args_on_stack, sig, regs);
630
631 entry_address[AdapterBlob::C2I_Unverified] = __ pc();
632 Label skip_fixup;
633 const Register receiver = R0;
634 const Register holder_klass = Rtemp; // XXX should be OK for C2 but not 100% sure
635
636 __ ic_check(1 /* end_alignment */);
637 __ ldr(Rmethod, Address(Ricklass, CompiledICData::speculated_method_offset()));
638
639 __ ldr(Rtemp, Address(Rmethod, Method::code_offset()), eq);
640 __ cmp(Rtemp, 0, eq);
641 __ b(skip_fixup, eq);
642 __ jump(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type, noreg, ne);
643
644 entry_address[AdapterBlob::C2I] = __ pc();
645 entry_address[AdapterBlob::C2I_No_Clinit_Check] = nullptr;
646 gen_c2i_adapter(masm, comp_args_on_stack, sig, regs, skip_fixup);
647 return;
648 }
649
650
651 static int reg2offset_in(VMReg r) {
652 // Account for saved FP and LR
653 return r->reg2stack() * VMRegImpl::stack_slot_size + 2*wordSize;
654 }
655
656 static int reg2offset_out(VMReg r) {
657 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
658 }
659
660
661 static void verify_oop_args(MacroAssembler* masm,
662 const methodHandle& method,
663 const BasicType* sig_bt,
664 const VMRegPair* regs) {
665 Register temp_reg = Rmethod; // not part of any compiled calling seq
666 if (VerifyOops) {
667 for (int i = 0; i < method->size_of_parameters(); i++) {
668 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
669 VMReg r = regs[i].first();
670 assert(r->is_valid(), "bad oop arg");
671 if (r->is_stack()) {
672 __ ldr(temp_reg, Address(SP, r->reg2stack() * VMRegImpl::stack_slot_size));
673 __ verify_oop(temp_reg);
674 } else {
675 __ verify_oop(r->as_Register());
676 }
677 }
678 }
679 }
680 }
681
682 static void gen_special_dispatch(MacroAssembler* masm,
683 const methodHandle& method,
684 const BasicType* sig_bt,
685 const VMRegPair* regs) {
686 verify_oop_args(masm, method, sig_bt, regs);
687 vmIntrinsics::ID iid = method->intrinsic_id();
688
689 // Now write the args into the outgoing interpreter space
690 bool has_receiver = false;
691 Register receiver_reg = noreg;
692 int member_arg_pos = -1;
693 Register member_reg = noreg;
694 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid);
695 if (ref_kind != 0) {
696 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument
697 member_reg = Rmethod; // known to be free at this point
698 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
699 } else if (iid == vmIntrinsics::_invokeBasic) {
700 has_receiver = true;
701 } else {
702 fatal("unexpected intrinsic id %d", vmIntrinsics::as_int(iid));
703 }
704
705 if (member_reg != noreg) {
706 // Load the member_arg into register, if necessary.
707 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs);
708 VMReg r = regs[member_arg_pos].first();
709 if (r->is_stack()) {
710 __ ldr(member_reg, Address(SP, r->reg2stack() * VMRegImpl::stack_slot_size));
711 } else {
712 // no data motion is needed
713 member_reg = r->as_Register();
714 }
715 }
716
717 if (has_receiver) {
718 // Make sure the receiver is loaded into a register.
719 assert(method->size_of_parameters() > 0, "oob");
720 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
721 VMReg r = regs[0].first();
722 assert(r->is_valid(), "bad receiver arg");
723 if (r->is_stack()) {
724 // Porting note: This assumes that compiled calling conventions always
725 // pass the receiver oop in a register. If this is not true on some
726 // platform, pick a temp and load the receiver from stack.
727 assert(false, "receiver always in a register");
728 receiver_reg = j_rarg0; // known to be free at this point
729 __ ldr(receiver_reg, Address(SP, r->reg2stack() * VMRegImpl::stack_slot_size));
730 } else {
731 // no data motion is needed
732 receiver_reg = r->as_Register();
733 }
734 }
735
736 // Figure out which address we are really jumping to:
737 MethodHandles::generate_method_handle_dispatch(masm, iid,
738 receiver_reg, member_reg, /*for_compiler_entry:*/ true);
739 }
740
741 // ---------------------------------------------------------------------------
742 // Generate a native wrapper for a given method. The method takes arguments
743 // in the Java compiled code convention, marshals them to the native
744 // convention (handlizes oops, etc), transitions to native, makes the call,
745 // returns to java state (possibly blocking), unhandlizes any result and
746 // returns.
747 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
748 const methodHandle& method,
749 int compile_id,
750 BasicType* in_sig_bt,
751 VMRegPair* in_regs,
752 BasicType ret_type) {
753 if (method->is_method_handle_intrinsic()) {
754 vmIntrinsics::ID iid = method->intrinsic_id();
755 intptr_t start = (intptr_t)__ pc();
756 int vep_offset = ((intptr_t)__ pc()) - start;
757 gen_special_dispatch(masm,
758 method,
759 in_sig_bt,
760 in_regs);
761 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
762 __ flush();
763 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually
764 return nmethod::new_native_nmethod(method,
765 compile_id,
766 masm->code(),
767 vep_offset,
768 frame_complete,
769 stack_slots / VMRegImpl::slots_per_word,
770 in_ByteSize(-1),
771 in_ByteSize(-1),
772 (OopMapSet*)nullptr);
773 }
774 // Arguments for JNI method include JNIEnv and Class if static
775
776 // Usage of Rtemp should be OK since scratched by native call
777
778 bool method_is_static = method->is_static();
779
780 const int total_in_args = method->size_of_parameters();
781 int total_c_args = total_in_args + (method_is_static ? 2 : 1);
782
783 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
784 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
785
786 int argc = 0;
787 out_sig_bt[argc++] = T_ADDRESS;
788 if (method_is_static) {
789 out_sig_bt[argc++] = T_OBJECT;
790 }
791
792 int i;
793 for (i = 0; i < total_in_args; i++) {
794 out_sig_bt[argc++] = in_sig_bt[i];
795 }
796
797 int out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
798 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
799 // Since object arguments need to be wrapped, we must preserve space
800 // for those object arguments which come in registers (GPR_PARAMS maximum)
801 // plus one more slot for Klass handle (for static methods)
802 int oop_handle_offset = stack_slots;
803 stack_slots += (GPR_PARAMS + 1) * VMRegImpl::slots_per_word;
804
805 // Plus a lock if needed
806 int lock_slot_offset = 0;
807 if (method->is_synchronized()) {
808 lock_slot_offset = stack_slots;
809 assert(sizeof(BasicLock) == wordSize, "adjust this code");
810 stack_slots += VMRegImpl::slots_per_word;
811 }
812
813 // Space to save return address and FP
814 stack_slots += 2 * VMRegImpl::slots_per_word;
815
816 // Calculate the final stack size taking account of alignment
817 stack_slots = align_up(stack_slots, StackAlignmentInBytes / VMRegImpl::stack_slot_size);
818 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
819 int lock_slot_fp_offset = stack_size - 2 * wordSize -
820 lock_slot_offset * VMRegImpl::stack_slot_size;
821
822 // Unverified entry point
823 address start = __ pc();
824
825 const Register receiver = R0; // see receiverOpr()
826 __ verify_oop(receiver);
827 // Inline cache check
828 __ ic_check(CodeEntryAlignment /* end_alignment */);
829
830 // Verified entry point
831 int vep_offset = __ pc() - start;
832
833 if ((InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) || (method->intrinsic_id() == vmIntrinsics::_identityHashCode)) {
834 // Object.hashCode, System.identityHashCode can pull the hashCode from the header word
835 // instead of doing a full VM transition once it's been computed.
836 Label slow_case;
837 const Register obj_reg = R0;
838
839 // Unlike for Object.hashCode, System.identityHashCode is static method and
840 // gets object as argument instead of the receiver.
841 if (method->intrinsic_id() == vmIntrinsics::_identityHashCode) {
842 assert(method->is_static(), "method should be static");
843 // return 0 for null reference input, return val = R0 = obj_reg = 0
844 __ cmp(obj_reg, 0);
845 __ bx(LR, eq);
846 }
847
848 __ ldr(Rtemp, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
849
850 assert(markWord::unlocked_value == 1, "adjust this code");
851 __ tbz(Rtemp, exact_log2(markWord::unlocked_value), slow_case);
852
853 __ bics(Rtemp, Rtemp, ~markWord::hash_mask_in_place);
854 __ mov(R0, AsmOperand(Rtemp, lsr, markWord::hash_shift), ne);
855 __ bx(LR, ne);
856
857 __ bind(slow_case);
858 }
859
860 // Bang stack pages
861 __ arm_stack_overflow_check(stack_size, Rtemp);
862
863 // Setup frame linkage
864 __ raw_push(FP, LR);
865 __ mov(FP, SP);
866 __ sub_slow(SP, SP, stack_size - 2*wordSize);
867
868 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
869 assert(bs != nullptr, "Sanity");
870 bs->nmethod_entry_barrier(masm);
871
872 int frame_complete = __ pc() - start;
873
874 OopMapSet* oop_maps = new OopMapSet();
875 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
876 const int extra_args = method_is_static ? 2 : 1;
877 int receiver_offset = -1;
878 int fp_regs_in_arguments = 0;
879
880 for (i = total_in_args; --i >= 0; ) {
881 switch (in_sig_bt[i]) {
882 case T_ARRAY:
883 case T_OBJECT: {
884 VMReg src = in_regs[i].first();
885 VMReg dst = out_regs[i + extra_args].first();
886 if (src->is_stack()) {
887 assert(dst->is_stack(), "must be");
888 assert(i != 0, "Incoming receiver is always in a register");
889 __ ldr(Rtemp, Address(FP, reg2offset_in(src)));
890 __ cmp(Rtemp, 0);
891 __ add(Rtemp, FP, reg2offset_in(src), ne);
892 __ str(Rtemp, Address(SP, reg2offset_out(dst)));
893 int offset_in_older_frame = src->reg2stack() + SharedRuntime::out_preserve_stack_slots();
894 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
895 } else {
896 int offset = oop_handle_offset * VMRegImpl::stack_slot_size;
897 __ str(src->as_Register(), Address(SP, offset));
898 map->set_oop(VMRegImpl::stack2reg(oop_handle_offset));
899 if ((i == 0) && (!method_is_static)) {
900 receiver_offset = offset;
901 }
902 oop_handle_offset += VMRegImpl::slots_per_word;
903
904 if (dst->is_stack()) {
905 __ movs(Rtemp, src->as_Register());
906 __ add(Rtemp, SP, offset, ne);
907 __ str(Rtemp, Address(SP, reg2offset_out(dst)));
908 } else {
909 __ movs(dst->as_Register(), src->as_Register());
910 __ add(dst->as_Register(), SP, offset, ne);
911 }
912 }
913 }
914
915 case T_VOID:
916 break;
917
918
919 #ifdef __SOFTFP__
920 case T_DOUBLE:
921 #endif
922 case T_LONG: {
923 VMReg src_1 = in_regs[i].first();
924 VMReg src_2 = in_regs[i].second();
925 VMReg dst_1 = out_regs[i + extra_args].first();
926 VMReg dst_2 = out_regs[i + extra_args].second();
927 #if (ALIGN_WIDE_ARGUMENTS == 0)
928 // C convention can mix a register and a stack slot for a
929 // 64-bits native argument.
930
931 // Note: following code should work independently of whether
932 // the Java calling convention follows C convention or whether
933 // it aligns 64-bit values.
934 if (dst_2->is_Register()) {
935 if (src_1->as_Register() != dst_1->as_Register()) {
936 assert(src_1->as_Register() != dst_2->as_Register() &&
937 src_2->as_Register() != dst_2->as_Register(), "must be");
938 __ mov(dst_2->as_Register(), src_2->as_Register());
939 __ mov(dst_1->as_Register(), src_1->as_Register());
940 } else {
941 assert(src_2->as_Register() == dst_2->as_Register(), "must be");
942 }
943 } else if (src_2->is_Register()) {
944 if (dst_1->is_Register()) {
945 // dst mixes a register and a stack slot
946 assert(dst_2->is_stack() && src_1->is_Register() && src_2->is_Register(), "must be");
947 assert(src_1->as_Register() != dst_1->as_Register(), "must be");
948 __ str(src_2->as_Register(), Address(SP, reg2offset_out(dst_2)));
949 __ mov(dst_1->as_Register(), src_1->as_Register());
950 } else {
951 // registers to stack slots
952 assert(dst_2->is_stack() && src_1->is_Register() && src_2->is_Register(), "must be");
953 __ str(src_1->as_Register(), Address(SP, reg2offset_out(dst_1)));
954 __ str(src_2->as_Register(), Address(SP, reg2offset_out(dst_2)));
955 }
956 } else if (src_1->is_Register()) {
957 if (dst_1->is_Register()) {
958 // src and dst must be R3 + stack slot
959 assert(dst_1->as_Register() == src_1->as_Register(), "must be");
960 __ ldr(Rtemp, Address(FP, reg2offset_in(src_2)));
961 __ str(Rtemp, Address(SP, reg2offset_out(dst_2)));
962 } else {
963 // <R3,stack> -> <stack,stack>
964 assert(dst_2->is_stack() && src_2->is_stack(), "must be");
965 __ ldr(LR, Address(FP, reg2offset_in(src_2)));
966 __ str(src_1->as_Register(), Address(SP, reg2offset_out(dst_1)));
967 __ str(LR, Address(SP, reg2offset_out(dst_2)));
968 }
969 } else {
970 assert(src_2->is_stack() && dst_1->is_stack() && dst_2->is_stack(), "must be");
971 __ ldr(Rtemp, Address(FP, reg2offset_in(src_1)));
972 __ ldr(LR, Address(FP, reg2offset_in(src_2)));
973 __ str(Rtemp, Address(SP, reg2offset_out(dst_1)));
974 __ str(LR, Address(SP, reg2offset_out(dst_2)));
975 }
976 #else // ALIGN_WIDE_ARGUMENTS
977 if (src_1->is_stack()) {
978 assert(src_2->is_stack() && dst_1->is_stack() && dst_2->is_stack(), "must be");
979 __ ldr(Rtemp, Address(FP, reg2offset_in(src_1)));
980 __ ldr(LR, Address(FP, reg2offset_in(src_2)));
981 __ str(Rtemp, Address(SP, reg2offset_out(dst_1)));
982 __ str(LR, Address(SP, reg2offset_out(dst_2)));
983 } else if (dst_1->is_stack()) {
984 assert(dst_2->is_stack() && src_1->is_Register() && src_2->is_Register(), "must be");
985 __ str(src_1->as_Register(), Address(SP, reg2offset_out(dst_1)));
986 __ str(src_2->as_Register(), Address(SP, reg2offset_out(dst_2)));
987 } else if (src_1->as_Register() == dst_1->as_Register()) {
988 assert(src_2->as_Register() == dst_2->as_Register(), "must be");
989 } else {
990 assert(src_1->as_Register() != dst_2->as_Register() &&
991 src_2->as_Register() != dst_2->as_Register(), "must be");
992 __ mov(dst_2->as_Register(), src_2->as_Register());
993 __ mov(dst_1->as_Register(), src_1->as_Register());
994 }
995 #endif // ALIGN_WIDE_ARGUMENTS
996 break;
997 }
998
999 #if (!defined __SOFTFP__ && !defined __ABI_HARD__)
1000 case T_FLOAT: {
1001 VMReg src = in_regs[i].first();
1002 VMReg dst = out_regs[i + extra_args].first();
1003 if (src->is_stack()) {
1004 assert(dst->is_stack(), "must be");
1005 __ ldr(Rtemp, Address(FP, reg2offset_in(src)));
1006 __ str(Rtemp, Address(SP, reg2offset_out(dst)));
1007 } else if (dst->is_stack()) {
1008 __ fsts(src->as_FloatRegister(), Address(SP, reg2offset_out(dst)));
1009 } else {
1010 assert(src->is_FloatRegister() && dst->is_Register(), "must be");
1011 __ fmrs(dst->as_Register(), src->as_FloatRegister());
1012 }
1013 break;
1014 }
1015
1016 case T_DOUBLE: {
1017 VMReg src_1 = in_regs[i].first();
1018 VMReg src_2 = in_regs[i].second();
1019 VMReg dst_1 = out_regs[i + extra_args].first();
1020 VMReg dst_2 = out_regs[i + extra_args].second();
1021 if (src_1->is_stack()) {
1022 assert(src_2->is_stack() && dst_1->is_stack() && dst_2->is_stack(), "must be");
1023 __ ldr(Rtemp, Address(FP, reg2offset_in(src_1)));
1024 __ ldr(LR, Address(FP, reg2offset_in(src_2)));
1025 __ str(Rtemp, Address(SP, reg2offset_out(dst_1)));
1026 __ str(LR, Address(SP, reg2offset_out(dst_2)));
1027 } else if (dst_1->is_stack()) {
1028 assert(dst_2->is_stack() && src_1->is_FloatRegister(), "must be");
1029 __ fstd(src_1->as_FloatRegister(), Address(SP, reg2offset_out(dst_1)));
1030 #if (ALIGN_WIDE_ARGUMENTS == 0)
1031 } else if (dst_2->is_stack()) {
1032 assert(! src_2->is_stack(), "must be"); // assuming internal java convention is aligned
1033 // double register must go into R3 + one stack slot
1034 __ fmrrd(dst_1->as_Register(), Rtemp, src_1->as_FloatRegister());
1035 __ str(Rtemp, Address(SP, reg2offset_out(dst_2)));
1036 #endif
1037 } else {
1038 assert(src_1->is_FloatRegister() && dst_1->is_Register() && dst_2->is_Register(), "must be");
1039 __ fmrrd(dst_1->as_Register(), dst_2->as_Register(), src_1->as_FloatRegister());
1040 }
1041 break;
1042 }
1043 #endif // __SOFTFP__
1044
1045 #ifdef __ABI_HARD__
1046 case T_FLOAT: {
1047 VMReg src = in_regs[i].first();
1048 VMReg dst = out_regs[i + extra_args].first();
1049 if (src->is_stack()) {
1050 if (dst->is_stack()) {
1051 __ ldr(Rtemp, Address(FP, reg2offset_in(src)));
1052 __ str(Rtemp, Address(SP, reg2offset_out(dst)));
1053 } else {
1054 // C2 Java calling convention does not populate S14 and S15, therefore
1055 // those need to be loaded from stack here
1056 __ flds(dst->as_FloatRegister(), Address(FP, reg2offset_in(src)));
1057 fp_regs_in_arguments++;
1058 }
1059 } else {
1060 assert(src->is_FloatRegister(), "must be");
1061 fp_regs_in_arguments++;
1062 }
1063 break;
1064 }
1065 case T_DOUBLE: {
1066 VMReg src_1 = in_regs[i].first();
1067 VMReg src_2 = in_regs[i].second();
1068 VMReg dst_1 = out_regs[i + extra_args].first();
1069 VMReg dst_2 = out_regs[i + extra_args].second();
1070 if (src_1->is_stack()) {
1071 if (dst_1->is_stack()) {
1072 assert(dst_2->is_stack(), "must be");
1073 __ ldr(Rtemp, Address(FP, reg2offset_in(src_1)));
1074 __ ldr(LR, Address(FP, reg2offset_in(src_2)));
1075 __ str(Rtemp, Address(SP, reg2offset_out(dst_1)));
1076 __ str(LR, Address(SP, reg2offset_out(dst_2)));
1077 } else {
1078 // C2 Java calling convention does not populate S14 and S15, therefore
1079 // those need to be loaded from stack here
1080 __ fldd(dst_1->as_FloatRegister(), Address(FP, reg2offset_in(src_1)));
1081 fp_regs_in_arguments += 2;
1082 }
1083 } else {
1084 assert(src_1->is_FloatRegister() && src_2->is_FloatRegister(), "must be");
1085 fp_regs_in_arguments += 2;
1086 }
1087 break;
1088 }
1089 #endif // __ABI_HARD__
1090
1091 default: {
1092 assert(in_sig_bt[i] != T_ADDRESS, "found T_ADDRESS in java args");
1093 VMReg src = in_regs[i].first();
1094 VMReg dst = out_regs[i + extra_args].first();
1095 if (src->is_stack()) {
1096 assert(dst->is_stack(), "must be");
1097 __ ldr(Rtemp, Address(FP, reg2offset_in(src)));
1098 __ str(Rtemp, Address(SP, reg2offset_out(dst)));
1099 } else if (dst->is_stack()) {
1100 __ str(src->as_Register(), Address(SP, reg2offset_out(dst)));
1101 } else {
1102 assert(src->is_Register() && dst->is_Register(), "must be");
1103 __ mov(dst->as_Register(), src->as_Register());
1104 }
1105 }
1106 }
1107 }
1108
1109 // Get Klass mirror
1110 int klass_offset = -1;
1111 if (method_is_static) {
1112 klass_offset = oop_handle_offset * VMRegImpl::stack_slot_size;
1113 __ mov_oop(Rtemp, JNIHandles::make_local(method->method_holder()->java_mirror()));
1114 __ add(c_rarg1, SP, klass_offset);
1115 __ str(Rtemp, Address(SP, klass_offset));
1116 map->set_oop(VMRegImpl::stack2reg(oop_handle_offset));
1117 }
1118
1119 // the PC offset given to add_gc_map must match the PC saved in set_last_Java_frame
1120 int pc_offset = __ set_last_Java_frame(SP, FP, true, Rtemp);
1121 assert(((__ pc()) - start) == __ offset(), "warning: start differs from code_begin");
1122 oop_maps->add_gc_map(pc_offset, map);
1123
1124 // Order last_Java_pc store with the thread state transition (to _thread_in_native)
1125 __ membar(MacroAssembler::StoreStore, Rtemp);
1126
1127 // RedefineClasses() tracing support for obsolete method entry
1128 if (log_is_enabled(Trace, redefine, class, obsolete)) {
1129 __ save_caller_save_registers();
1130 __ mov(R0, Rthread);
1131 __ mov_metadata(R1, method());
1132 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), R0, R1);
1133 __ restore_caller_save_registers();
1134 }
1135
1136 const Register sync_handle = R5;
1137 const Register sync_obj = R6;
1138 const Register basic_lock = altFP_7_11;
1139 const Register tmp = R8;
1140
1141 Label slow_lock, lock_done, fast_lock;
1142 if (method->is_synchronized()) {
1143 // The first argument is a handle to sync object (a class or an instance)
1144 __ ldr(sync_obj, Address(R1));
1145 // Remember the handle for the unlocking code
1146 __ mov(sync_handle, R1);
1147
1148 log_trace(fastlock)("SharedRuntime lock fast");
1149 __ fast_lock(sync_obj /* object */, basic_lock /* t1 */, tmp /* t2 */, Rtemp /* t3 */,
1150 0x7 /* savemask */, slow_lock);
1151 // Fall through to lock_done
1152 __ bind(lock_done);
1153 }
1154
1155 // Get JNIEnv*
1156 __ add(c_rarg0, Rthread, in_bytes(JavaThread::jni_environment_offset()));
1157
1158 // Perform thread state transition
1159 __ mov(Rtemp, _thread_in_native);
1160 __ str(Rtemp, Address(Rthread, JavaThread::thread_state_offset()));
1161
1162 // Finally, call the native method
1163 __ call(method->native_function());
1164
1165 // Set FPSCR/FPCR to a known state
1166 if (AlwaysRestoreFPU) {
1167 __ restore_default_fp_mode();
1168 }
1169
1170 // Ensure a Boolean result is mapped to 0..1
1171 if (ret_type == T_BOOLEAN) {
1172 __ c2bool(R0);
1173 }
1174
1175 // Do a safepoint check while thread is in transition state
1176 Label call_safepoint_runtime, return_to_java;
1177 __ mov(Rtemp, _thread_in_native_trans);
1178 __ str_32(Rtemp, Address(Rthread, JavaThread::thread_state_offset()));
1179
1180 // make sure the store is observed before reading the SafepointSynchronize state and further mem refs
1181 if (!UseSystemMemoryBarrier) {
1182 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
1183 }
1184
1185 __ safepoint_poll(R2, call_safepoint_runtime);
1186 __ ldr_u32(R3, Address(Rthread, JavaThread::suspend_flags_offset()));
1187 __ cmp(R3, 0);
1188 __ b(call_safepoint_runtime, ne);
1189
1190 __ bind(return_to_java);
1191
1192 // Perform thread state transition and reguard stack yellow pages if needed
1193 Label reguard, reguard_done;
1194 __ mov(Rtemp, _thread_in_Java);
1195 __ ldr_s32(R2, Address(Rthread, JavaThread::stack_guard_state_offset()));
1196 __ str_32(Rtemp, Address(Rthread, JavaThread::thread_state_offset()));
1197
1198 __ cmp(R2, StackOverflow::stack_guard_yellow_reserved_disabled);
1199 __ b(reguard, eq);
1200 __ bind(reguard_done);
1201
1202 Label slow_unlock, unlock_done;
1203 if (method->is_synchronized()) {
1204 log_trace(fastlock)("SharedRuntime unlock fast");
1205 __ fast_unlock(sync_obj, R2 /* t1 */, tmp /* t2 */, Rtemp /* t3 */,
1206 7 /* savemask */, slow_unlock);
1207 // Fall through
1208
1209 __ bind(unlock_done);
1210 }
1211
1212 // Set last java frame and handle block to zero
1213 __ ldr(LR, Address(Rthread, JavaThread::active_handles_offset()));
1214 __ reset_last_Java_frame(Rtemp); // sets Rtemp to 0 on 32-bit ARM
1215
1216 __ str_32(Rtemp, Address(LR, JNIHandleBlock::top_offset()));
1217 if (CheckJNICalls) {
1218 __ str(__ zero_register(Rtemp), Address(Rthread, JavaThread::pending_jni_exception_check_fn_offset()));
1219 }
1220
1221 // Unbox oop result, e.g. JNIHandles::resolve value in R0.
1222 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
1223 __ resolve_jobject(R0, // value
1224 Rtemp, // tmp1
1225 R1_tmp); // tmp2
1226 }
1227
1228 // Any exception pending?
1229 __ ldr(Rtemp, Address(Rthread, Thread::pending_exception_offset()));
1230 __ mov(SP, FP);
1231
1232 __ cmp(Rtemp, 0);
1233 // Pop the frame and return if no exception pending
1234 __ pop(RegisterSet(FP) | RegisterSet(PC), eq);
1235 // Pop the frame and forward the exception. Rexception_pc contains return address.
1236 __ ldr(FP, Address(SP, wordSize, post_indexed), ne);
1237 __ ldr(Rexception_pc, Address(SP, wordSize, post_indexed), ne);
1238 __ jump(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type, Rtemp);
1239
1240 // Safepoint operation and/or pending suspend request is in progress.
1241 // Save the return values and call the runtime function by hand.
1242 __ bind(call_safepoint_runtime);
1243 push_result_registers(masm, ret_type);
1244 __ mov(R0, Rthread);
1245 __ call(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans));
1246 pop_result_registers(masm, ret_type);
1247 __ b(return_to_java);
1248
1249 // Reguard stack pages. Save native results around a call to C runtime.
1250 __ bind(reguard);
1251 push_result_registers(masm, ret_type);
1252 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
1253 pop_result_registers(masm, ret_type);
1254 __ b(reguard_done);
1255
1256 if (method->is_synchronized()) {
1257 // Locking slow case
1258 __ bind(slow_lock);
1259
1260 push_param_registers(masm, fp_regs_in_arguments);
1261
1262 // last_Java_frame is already set, so do call_VM manually; no exception can occur
1263 __ mov(R0, sync_obj);
1264 __ mov(R1, basic_lock);
1265 __ mov(R2, Rthread);
1266 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C));
1267
1268 pop_param_registers(masm, fp_regs_in_arguments);
1269
1270 __ b(lock_done);
1271
1272 // Unlocking slow case
1273 __ bind(slow_unlock);
1274
1275 push_result_registers(masm, ret_type);
1276
1277 // Clear pending exception before reentering VM.
1278 // Can store the oop in register since it is a leaf call.
1279 assert_different_registers(Rtmp_save1, sync_obj, basic_lock);
1280 __ ldr(Rtmp_save1, Address(Rthread, Thread::pending_exception_offset()));
1281 Register zero = __ zero_register(Rtemp);
1282 __ str(zero, Address(Rthread, Thread::pending_exception_offset()));
1283 __ mov(R0, sync_obj);
1284 __ mov(R1, basic_lock);
1285 __ mov(R2, Rthread);
1286 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C));
1287 __ str(Rtmp_save1, Address(Rthread, Thread::pending_exception_offset()));
1288
1289 pop_result_registers(masm, ret_type);
1290
1291 __ b(unlock_done);
1292 }
1293
1294 __ flush();
1295 return nmethod::new_native_nmethod(method,
1296 compile_id,
1297 masm->code(),
1298 vep_offset,
1299 frame_complete,
1300 stack_slots / VMRegImpl::slots_per_word,
1301 in_ByteSize(method_is_static ? klass_offset : receiver_offset),
1302 in_ByteSize(lock_slot_offset * VMRegImpl::stack_slot_size),
1303 oop_maps);
1304 }
1305
1306 // this function returns the adjust size (in number of words) to a c2i adapter
1307 // activation for use during deoptimization
1308 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
1309 int extra_locals_size = (callee_locals - callee_parameters) * Interpreter::stackElementWords;
1310 return extra_locals_size;
1311 }
1312
1313
1314 // Number of stack slots between incoming argument block and the start of
1315 // a new frame. The PROLOG must add this many slots to the stack. The
1316 // EPILOG must remove this many slots.
1317 // FP + LR
1318 uint SharedRuntime::in_preserve_stack_slots() {
1319 return 2 * VMRegImpl::slots_per_word;
1320 }
1321
1322 uint SharedRuntime::out_preserve_stack_slots() {
1323 return 0;
1324 }
1325
1326 VMReg SharedRuntime::thread_register() {
1327 Unimplemented();
1328 return nullptr;
1329 }
1330
1331 //------------------------------generate_deopt_blob----------------------------
1332 void SharedRuntime::generate_deopt_blob() {
1333 ResourceMark rm;
1334 const char* name = SharedRuntime::stub_name(StubId::shared_deopt_id);
1335 CodeBuffer buffer(name, 1024, 1024);
1336 int frame_size_in_words;
1337 OopMapSet* oop_maps;
1338 int reexecute_offset;
1339 int exception_in_tls_offset;
1340 int exception_offset;
1341
1342 MacroAssembler* masm = new MacroAssembler(&buffer);
1343 Label cont;
1344 const Register Rkind = R9; // caller-saved
1345 const Register Rublock = R6;
1346 const Register Rsender = altFP_7_11;
1347 assert_different_registers(Rkind, Rublock, Rsender, Rexception_obj, Rexception_pc, R0, R1, R2, R3, R8, Rtemp);
1348
1349 address start = __ pc();
1350
1351 oop_maps = new OopMapSet();
1352 // LR saved by caller (can be live in c2 method)
1353
1354 // A deopt is a case where LR may be live in the c2 nmethod. So it's
1355 // not possible to call the deopt blob from the nmethod and pass the
1356 // address of the deopt handler of the nmethod in LR. What happens
1357 // now is that the caller of the deopt blob pushes the current
1358 // address so the deopt blob doesn't have to do it. This way LR can
1359 // be preserved, contains the live value from the nmethod and is
1360 // saved at R14/R30_offset here.
1361 OopMap* map = RegisterSaver::save_live_registers(masm, &frame_size_in_words, true);
1362 __ mov(Rkind, Deoptimization::Unpack_deopt);
1363 __ b(cont);
1364
1365 exception_offset = __ pc() - start;
1366
1367 // Transfer Rexception_obj & Rexception_pc in TLS and fall thru to the
1368 // exception_in_tls_offset entry point.
1369 __ str(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
1370 __ str(Rexception_pc, Address(Rthread, JavaThread::exception_pc_offset()));
1371 // Force return value to null to avoid confusing the escape analysis
1372 // logic. Everything is dead here anyway.
1373 __ mov(R0, 0);
1374
1375 exception_in_tls_offset = __ pc() - start;
1376
1377 // Exception data is in JavaThread structure
1378 // Patch the return address of the current frame
1379 __ ldr(LR, Address(Rthread, JavaThread::exception_pc_offset()));
1380 (void) RegisterSaver::save_live_registers(masm, &frame_size_in_words);
1381 {
1382 const Register Rzero = __ zero_register(Rtemp); // XXX should be OK for C2 but not 100% sure
1383 __ str(Rzero, Address(Rthread, JavaThread::exception_pc_offset()));
1384 }
1385 __ mov(Rkind, Deoptimization::Unpack_exception);
1386 __ b(cont);
1387
1388 reexecute_offset = __ pc() - start;
1389
1390 (void) RegisterSaver::save_live_registers(masm, &frame_size_in_words);
1391 __ mov(Rkind, Deoptimization::Unpack_reexecute);
1392
1393 // Calculate UnrollBlock and save the result in Rublock
1394 __ bind(cont);
1395 __ mov(R0, Rthread);
1396 __ mov(R1, Rkind);
1397
1398 int pc_offset = __ set_last_Java_frame(SP, FP, false, Rtemp); // note: FP may not need to be saved (not on x86)
1399 assert(((__ pc()) - start) == __ offset(), "warning: start differs from code_begin");
1400 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info));
1401 if (pc_offset == -1) {
1402 pc_offset = __ offset();
1403 }
1404 oop_maps->add_gc_map(pc_offset, map);
1405 __ reset_last_Java_frame(Rtemp); // Rtemp free since scratched by far call
1406
1407 __ mov(Rublock, R0);
1408
1409 // Reload Rkind from the UnrollBlock (might have changed)
1410 __ ldr_s32(Rkind, Address(Rublock, Deoptimization::UnrollBlock::unpack_kind_offset()));
1411 Label noException;
1412 __ cmp_32(Rkind, Deoptimization::Unpack_exception); // Was exception pending?
1413 __ b(noException, ne);
1414 // handle exception case
1415 #ifdef ASSERT
1416 // assert that exception_pc is zero in tls
1417 { Label L;
1418 __ ldr(Rexception_pc, Address(Rthread, JavaThread::exception_pc_offset()));
1419 __ cbz(Rexception_pc, L);
1420 __ stop("exception pc should be null");
1421 __ bind(L);
1422 }
1423 #endif
1424 __ ldr(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
1425 __ verify_oop(Rexception_obj);
1426 {
1427 const Register Rzero = __ zero_register(Rtemp);
1428 __ str(Rzero, Address(Rthread, JavaThread::exception_oop_offset()));
1429 }
1430
1431 __ bind(noException);
1432
1433 // This frame is going away. Fetch return value, so we can move it to
1434 // a new frame.
1435 __ ldr(R0, Address(SP, RegisterSaver::R0_offset * wordSize));
1436 __ ldr(R1, Address(SP, RegisterSaver::R1_offset * wordSize));
1437 #ifndef __SOFTFP__
1438 __ ldr_double(D0, Address(SP, RegisterSaver::D0_offset * wordSize));
1439 #endif
1440 // pop frame
1441 __ add(SP, SP, RegisterSaver::reg_save_size * wordSize);
1442
1443 // Set initial stack state before pushing interpreter frames
1444 __ ldr_s32(Rtemp, Address(Rublock, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset()));
1445 __ ldr(R2, Address(Rublock, Deoptimization::UnrollBlock::frame_pcs_offset()));
1446 __ ldr(R3, Address(Rublock, Deoptimization::UnrollBlock::frame_sizes_offset()));
1447
1448 __ add(SP, SP, Rtemp);
1449
1450 #ifdef ASSERT
1451 // Compilers generate code that bang the stack by as much as the
1452 // interpreter would need. So this stack banging should never
1453 // trigger a fault. Verify that it does not on non product builds.
1454 // See if it is enough stack to push deoptimized frames.
1455 //
1456 // The compiled method that we are deoptimizing was popped from the stack.
1457 // If the stack bang results in a stack overflow, we don't return to the
1458 // method that is being deoptimized. The stack overflow exception is
1459 // propagated to the caller of the deoptimized method. Need to get the pc
1460 // from the caller in LR and restore FP.
1461 __ ldr(LR, Address(R2, 0));
1462 __ ldr(FP, Address(Rublock, Deoptimization::UnrollBlock::initial_info_offset()));
1463 __ ldr_s32(R8, Address(Rublock, Deoptimization::UnrollBlock::total_frame_sizes_offset()));
1464 __ arm_stack_overflow_check(R8, Rtemp);
1465 #endif
1466 __ ldr_s32(R8, Address(Rublock, Deoptimization::UnrollBlock::number_of_frames_offset()));
1467
1468 // Pick up the initial fp we should save
1469 // XXX Note: was ldr(FP, Address(FP));
1470
1471 // The compiler no longer uses FP as a frame pointer for the
1472 // compiled code. It can be used by the allocator in C2 or to
1473 // memorize the original SP for JSR292 call sites.
1474
1475 // Hence, ldr(FP, Address(FP)) is probably not correct. For x86,
1476 // Deoptimization::fetch_unroll_info computes the right FP value and
1477 // stores it in Rublock.initial_info. This has been activated for ARM.
1478 __ ldr(FP, Address(Rublock, Deoptimization::UnrollBlock::initial_info_offset()));
1479
1480 __ ldr_s32(Rtemp, Address(Rublock, Deoptimization::UnrollBlock::caller_adjustment_offset()));
1481 __ mov(Rsender, SP);
1482 __ sub(SP, SP, Rtemp);
1483
1484 // Push interpreter frames in a loop
1485 Label loop;
1486 __ bind(loop);
1487 __ ldr(LR, Address(R2, wordSize, post_indexed)); // load frame pc
1488 __ ldr(Rtemp, Address(R3, wordSize, post_indexed)); // load frame size
1489
1490 __ raw_push(FP, LR); // create new frame
1491 __ mov(FP, SP);
1492 __ sub(Rtemp, Rtemp, 2*wordSize);
1493
1494 __ sub(SP, SP, Rtemp);
1495
1496 __ str(Rsender, Address(FP, frame::interpreter_frame_sender_sp_offset * wordSize));
1497 __ mov(LR, 0);
1498 __ str(LR, Address(FP, frame::interpreter_frame_last_sp_offset * wordSize));
1499
1500 __ subs(R8, R8, 1); // decrement counter
1501 __ mov(Rsender, SP);
1502 __ b(loop, ne);
1503
1504 // Re-push self-frame
1505 __ ldr(LR, Address(R2));
1506 __ raw_push(FP, LR);
1507 __ mov(FP, SP);
1508 __ sub(SP, SP, (frame_size_in_words - 2) * wordSize);
1509
1510 // Restore frame locals after moving the frame
1511 __ str(R0, Address(SP, RegisterSaver::R0_offset * wordSize));
1512 __ str(R1, Address(SP, RegisterSaver::R1_offset * wordSize));
1513
1514 #ifndef __SOFTFP__
1515 __ str_double(D0, Address(SP, RegisterSaver::D0_offset * wordSize));
1516 #endif // !__SOFTFP__
1517
1518 #ifdef ASSERT
1519 // Reload Rkind from the UnrollBlock and check that it was not overwritten (Rkind is not callee-saved)
1520 { Label L;
1521 __ ldr_s32(Rtemp, Address(Rublock, Deoptimization::UnrollBlock::unpack_kind_offset()));
1522 __ cmp_32(Rkind, Rtemp);
1523 __ b(L, eq);
1524 __ stop("Rkind was overwritten");
1525 __ bind(L);
1526 }
1527 #endif
1528
1529 // Call unpack_frames with proper arguments
1530 __ mov(R0, Rthread);
1531 __ mov(R1, Rkind);
1532
1533 pc_offset = __ set_last_Java_frame(SP, FP, true, Rtemp);
1534 assert(((__ pc()) - start) == __ offset(), "warning: start differs from code_begin");
1535 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames));
1536 if (pc_offset == -1) {
1537 pc_offset = __ offset();
1538 }
1539 oop_maps->add_gc_map(pc_offset, new OopMap(frame_size_in_words * VMRegImpl::slots_per_word, 0));
1540 __ reset_last_Java_frame(Rtemp); // Rtemp free since scratched by far call
1541
1542 // Collect return values, pop self-frame and jump to interpreter
1543 __ ldr(R0, Address(SP, RegisterSaver::R0_offset * wordSize));
1544 __ ldr(R1, Address(SP, RegisterSaver::R1_offset * wordSize));
1545 // Interpreter floats controlled by __SOFTFP__, but compiler
1546 // float return value registers controlled by __ABI_HARD__
1547 // This matters for vfp-sflt builds.
1548 #ifndef __SOFTFP__
1549 // Interpreter hard float
1550 #ifdef __ABI_HARD__
1551 // Compiler float return value in FP registers
1552 __ ldr_double(D0, Address(SP, RegisterSaver::D0_offset * wordSize));
1553 #else
1554 // Compiler float return value in integer registers,
1555 // copy to D0 for interpreter (S0 <-- R0)
1556 __ fmdrr(D0_tos, R0, R1);
1557 #endif
1558 #endif // !__SOFTFP__
1559 __ mov(SP, FP);
1560
1561 __ pop(RegisterSet(FP) | RegisterSet(PC));
1562
1563 __ flush();
1564
1565 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset,
1566 reexecute_offset, frame_size_in_words);
1567 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
1568 }
1569
1570 //------------------------------generate_handler_blob------
1571 //
1572 // Generate a special Compile2Runtime blob that saves all registers,
1573 // setup oopmap, and calls safepoint code to stop the compiled code for
1574 // a safepoint.
1575 //
1576 SafepointBlob* SharedRuntime::generate_handler_blob(StubId id, address call_ptr) {
1577 assert(StubRoutines::forward_exception_entry() != nullptr, "must be generated before");
1578 assert(is_polling_page_id(id), "expected a polling page stub id");
1579
1580 ResourceMark rm;
1581 const char* name = SharedRuntime::stub_name(id);
1582 CodeBuffer buffer(name, 256, 256);
1583 int frame_size_words;
1584 OopMapSet* oop_maps;
1585
1586 bool cause_return = (id == StubId::shared_polling_page_return_handler_id);
1587
1588 MacroAssembler* masm = new MacroAssembler(&buffer);
1589 address start = __ pc();
1590 oop_maps = new OopMapSet();
1591
1592 if (!cause_return) {
1593 __ sub(SP, SP, 4); // make room for LR which may still be live
1594 // here if we are coming from a c2 method
1595 }
1596
1597 OopMap* map = RegisterSaver::save_live_registers(masm, &frame_size_words, !cause_return);
1598 if (!cause_return) {
1599 // update saved PC with correct value
1600 // need 2 steps because LR can be live in c2 method
1601 __ ldr(LR, Address(Rthread, JavaThread::saved_exception_pc_offset()));
1602 __ str(LR, Address(SP, RegisterSaver::LR_offset * wordSize));
1603 }
1604
1605 __ mov(R0, Rthread);
1606 int pc_offset = __ set_last_Java_frame(SP, FP, false, Rtemp); // note: FP may not need to be saved (not on x86)
1607 assert(((__ pc()) - start) == __ offset(), "warning: start differs from code_begin");
1608 __ call(call_ptr);
1609 if (pc_offset == -1) {
1610 pc_offset = __ offset();
1611 }
1612 oop_maps->add_gc_map(pc_offset, map);
1613 __ reset_last_Java_frame(Rtemp); // Rtemp free since scratched by far call
1614
1615 if (!cause_return) {
1616 // If our stashed return pc was modified by the runtime we avoid touching it
1617 __ ldr(R3_tmp, Address(Rthread, JavaThread::saved_exception_pc_offset()));
1618 __ ldr(R2_tmp, Address(SP, RegisterSaver::LR_offset * wordSize));
1619 __ cmp(R2_tmp, R3_tmp);
1620 // Adjust return pc forward to step over the safepoint poll instruction
1621 __ add(R2_tmp, R2_tmp, 4, eq);
1622 __ str(R2_tmp, Address(SP, RegisterSaver::LR_offset * wordSize), eq);
1623
1624 // Check for pending exception
1625 __ ldr(Rtemp, Address(Rthread, Thread::pending_exception_offset()));
1626 __ cmp(Rtemp, 0);
1627
1628 RegisterSaver::restore_live_registers(masm, false);
1629 __ pop(PC, eq);
1630 __ pop(Rexception_pc);
1631 } else {
1632 // Check for pending exception
1633 __ ldr(Rtemp, Address(Rthread, Thread::pending_exception_offset()));
1634 __ cmp(Rtemp, 0);
1635
1636 RegisterSaver::restore_live_registers(masm);
1637 __ bx(LR, eq);
1638 __ mov(Rexception_pc, LR);
1639 }
1640
1641 __ jump(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type, Rtemp);
1642
1643 __ flush();
1644
1645 return SafepointBlob::create(&buffer, oop_maps, frame_size_words);
1646 }
1647
1648 RuntimeStub* SharedRuntime::generate_resolve_blob(StubId id, address destination) {
1649 assert(StubRoutines::forward_exception_entry() != nullptr, "must be generated before");
1650 assert(is_resolve_id(id), "expected a resolve stub id");
1651
1652 ResourceMark rm;
1653 const char* name = SharedRuntime::stub_name(id);
1654 CodeBuffer buffer(name, 1000, 512);
1655 int frame_size_words;
1656 OopMapSet *oop_maps;
1657 int frame_complete;
1658
1659 MacroAssembler* masm = new MacroAssembler(&buffer);
1660 Label pending_exception;
1661
1662 int start = __ offset();
1663
1664 oop_maps = new OopMapSet();
1665 OopMap* map = RegisterSaver::save_live_registers(masm, &frame_size_words);
1666
1667 frame_complete = __ offset();
1668
1669 __ mov(R0, Rthread);
1670
1671 int pc_offset = __ set_last_Java_frame(SP, FP, false, Rtemp);
1672 assert(start == 0, "warning: start differs from code_begin");
1673 __ call(destination);
1674 if (pc_offset == -1) {
1675 pc_offset = __ offset();
1676 }
1677 oop_maps->add_gc_map(pc_offset, map);
1678 __ reset_last_Java_frame(Rtemp); // Rtemp free since scratched by far call
1679
1680 __ ldr(R1, Address(Rthread, Thread::pending_exception_offset()));
1681 __ cbnz(R1, pending_exception);
1682
1683 // Overwrite saved register values
1684
1685 // Place metadata result of VM call into Rmethod
1686 __ get_vm_result_metadata(R1, Rtemp);
1687 __ str(R1, Address(SP, RegisterSaver::Rmethod_offset * wordSize));
1688
1689 // Place target address (VM call result) into Rtemp
1690 __ str(R0, Address(SP, RegisterSaver::Rtemp_offset * wordSize));
1691
1692 RegisterSaver::restore_live_registers(masm);
1693 __ jump(Rtemp);
1694
1695 __ bind(pending_exception);
1696
1697 RegisterSaver::restore_live_registers(masm);
1698 const Register Rzero = __ zero_register(Rtemp);
1699 __ str(Rzero, Address(Rthread, JavaThread::vm_result_metadata_offset()));
1700 __ mov(Rexception_pc, LR);
1701 __ jump(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type, Rtemp);
1702
1703 __ flush();
1704
1705 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
1706 }
1707
1708 //------------------------------------------------------------------------------------------------------------------------
1709 // Continuation point for throwing of implicit exceptions that are not handled in
1710 // the current activation. Fabricates an exception oop and initiates normal
1711 // exception dispatching in this frame.
1712 RuntimeStub* SharedRuntime::generate_throw_exception(StubId id, address runtime_entry) {
1713 assert(is_throw_id(id), "expected a throw stub id");
1714
1715 const char* name = SharedRuntime::stub_name(id);
1716
1717 int insts_size = 128;
1718 int locs_size = 32;
1719
1720 ResourceMark rm;
1721 const char* timer_msg = "SharedRuntime generate_throw_exception";
1722 TraceTime timer(timer_msg, TRACETIME_LOG(Info, startuptime));
1723
1724 CodeBuffer code(name, insts_size, locs_size);
1725 OopMapSet* oop_maps;
1726 int frame_size;
1727 int frame_complete;
1728
1729 oop_maps = new OopMapSet();
1730 MacroAssembler* masm = new MacroAssembler(&code);
1731
1732 address start = __ pc();
1733
1734 frame_size = 2;
1735 __ mov(Rexception_pc, LR);
1736 __ raw_push(FP, LR);
1737
1738 frame_complete = __ pc() - start;
1739
1740 // Any extra arguments are already supposed to be R1 and R2
1741 __ mov(R0, Rthread);
1742
1743 int pc_offset = __ set_last_Java_frame(SP, FP, false, Rtemp);
1744 assert(((__ pc()) - start) == __ offset(), "warning: start differs from code_begin");
1745 __ call(runtime_entry);
1746 if (pc_offset == -1) {
1747 pc_offset = __ offset();
1748 }
1749
1750 // Generate oop map
1751 OopMap* map = new OopMap(frame_size*VMRegImpl::slots_per_word, 0);
1752 oop_maps->add_gc_map(pc_offset, map);
1753 __ reset_last_Java_frame(Rtemp); // Rtemp free since scratched by far call
1754
1755 __ raw_pop(FP, LR);
1756 __ jump(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type, Rtemp);
1757
1758 RuntimeStub* stub = RuntimeStub::new_runtime_stub(name, &code, frame_complete,
1759 frame_size, oop_maps, false);
1760 return stub;
1761 }
1762
1763 #if INCLUDE_JFR
1764
1765 // For c2: c_rarg0 is junk, call to runtime to write a checkpoint.
1766 // It returns a jobject handle to the event writer.
1767 // The handle is dereferenced and the return value is the event writer oop.
1768 RuntimeStub* SharedRuntime::generate_jfr_write_checkpoint() {
1769 enum layout {
1770 r1_off,
1771 r2_off,
1772 return_off,
1773 framesize // inclusive of return address
1774 };
1775
1776 const char* name = SharedRuntime::stub_name(StubId::shared_jfr_write_checkpoint_id);
1777 CodeBuffer code(name, 512, 64);
1778 MacroAssembler* masm = new MacroAssembler(&code);
1779
1780 address start = __ pc();
1781 __ raw_push(R1, R2, LR);
1782 address the_pc = __ pc();
1783
1784 int frame_complete = the_pc - start;
1785
1786 __ set_last_Java_frame(SP, FP, true, Rtemp);
1787 __ mov(c_rarg0, Rthread);
1788 __ call_VM_leaf(CAST_FROM_FN_PTR(address, JfrIntrinsicSupport::write_checkpoint), c_rarg0);
1789 __ reset_last_Java_frame(Rtemp);
1790
1791 // R0 is jobject handle result, unpack and process it through a barrier.
1792 __ resolve_global_jobject(R0, Rtemp, R1);
1793
1794 __ raw_pop(R1, R2, LR);
1795 __ ret();
1796
1797 OopMapSet* oop_maps = new OopMapSet();
1798 OopMap* map = new OopMap(framesize, 1);
1799 oop_maps->add_gc_map(frame_complete, map);
1800
1801 RuntimeStub* stub =
1802 RuntimeStub::new_runtime_stub(name,
1803 &code,
1804 frame_complete,
1805 (framesize >> (LogBytesPerWord - LogBytesPerInt)),
1806 oop_maps,
1807 false);
1808 return stub;
1809 }
1810
1811 // For c2: call to return a leased buffer.
1812 RuntimeStub* SharedRuntime::generate_jfr_return_lease() {
1813 enum layout {
1814 r1_off,
1815 r2_off,
1816 return_off,
1817 framesize // inclusive of return address
1818 };
1819
1820 const char* name = SharedRuntime::stub_name(StubId::shared_jfr_return_lease_id);
1821 CodeBuffer code(name, 512, 64);
1822 MacroAssembler* masm = new MacroAssembler(&code);
1823
1824 address start = __ pc();
1825 __ raw_push(R1, R2, LR);
1826 address the_pc = __ pc();
1827
1828 int frame_complete = the_pc - start;
1829
1830 __ set_last_Java_frame(SP, FP, true, Rtemp);
1831 __ mov(c_rarg0, Rthread);
1832 __ call_VM_leaf(CAST_FROM_FN_PTR(address, JfrIntrinsicSupport::return_lease), c_rarg0);
1833 __ reset_last_Java_frame(Rtemp);
1834
1835 __ raw_pop(R1, R2, LR);
1836 __ ret();
1837
1838 OopMapSet* oop_maps = new OopMapSet();
1839 OopMap* map = new OopMap(framesize, 1);
1840 oop_maps->add_gc_map(frame_complete, map);
1841
1842 RuntimeStub* stub =
1843 RuntimeStub::new_runtime_stub(name,
1844 &code,
1845 frame_complete,
1846 (framesize >> (LogBytesPerWord - LogBytesPerInt)),
1847 oop_maps,
1848 false);
1849 return stub;
1850 }
1851
1852 #endif // INCLUDE_JFR
1853
1854 const uint SharedRuntime::java_return_convention_max_int = 0; // Argument::n_int_register_parameters_j;
1855 const uint SharedRuntime::java_return_convention_max_float = 0; // Argument::n_float_register_parameters_j;
1856
1857 int SharedRuntime::java_return_convention(const BasicType *sig_bt, VMRegPair *regs, int total_args_passed) {
1858 Unimplemented();
1859 return 0;
1860 }
1861
1862 BufferedInlineTypeBlob* SharedRuntime::generate_buffered_inline_type_adapter(const InlineKlass* vk) {
1863 Unimplemented();
1864 return nullptr;
1865 }