1 /*
2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2024 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "memory/universe.hpp"
37 #include "nativeInst_ppc.hpp"
38 #include "oops/compressedOops.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/os.inline.hpp"
42 #include "runtime/safepointMechanism.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "runtime/vm_version.hpp"
46 #include "utilities/macros.hpp"
47 #include "utilities/powerOfTwo.hpp"
48
49 #define __ _masm->
50
51
52 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
53
54
55 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
56 Unimplemented(); return false; // Currently not used on this platform.
57 }
58
59
60 LIR_Opr LIR_Assembler::receiverOpr() {
61 return FrameMap::R3_oop_opr;
62 }
63
64
65 LIR_Opr LIR_Assembler::osrBufferPointer() {
66 return FrameMap::R3_opr;
67 }
68
69
70 // This specifies the stack pointer decrement needed to build the frame.
71 int LIR_Assembler::initial_frame_size_in_bytes() const {
72 return in_bytes(frame_map()->framesize_in_bytes());
73 }
74
75
76 // Inline cache check: the inline cached class is in inline_cache_reg;
77 // we fetch the class of the receiver and compare it with the cached class.
78 // If they do not match we jump to slow case.
79 int LIR_Assembler::check_icache() {
80 return __ ic_check(CodeEntryAlignment);
81 }
82
83 void LIR_Assembler::clinit_barrier(ciMethod* method) {
84 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
85
86 Label L_skip_barrier;
87 Register klass = R20;
88
89 metadata2reg(method->holder()->constant_encoding(), klass);
90 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
91
92 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
93 __ mtctr(klass);
94 __ bctr();
95
96 __ bind(L_skip_barrier);
97 }
98
99 void LIR_Assembler::osr_entry() {
100 // On-stack-replacement entry sequence:
101 //
102 // 1. Create a new compiled activation.
103 // 2. Initialize local variables in the compiled activation. The expression
104 // stack must be empty at the osr_bci; it is not initialized.
105 // 3. Jump to the continuation address in compiled code to resume execution.
106
107 // OSR entry point
108 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
109 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
110 ValueStack* entry_state = osr_entry->end()->state();
111 int number_of_locks = entry_state->locks_size();
112
113 // Create a frame for the compiled activation.
114 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
115
116 // OSR buffer is
117 //
118 // locals[nlocals-1..0]
119 // monitors[number_of_locks-1..0]
120 //
121 // Locals is a direct copy of the interpreter frame so in the osr buffer
122 // the first slot in the local array is the last local from the interpreter
123 // and the last slot is local[0] (receiver) from the interpreter.
124 //
125 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
126 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
127 // in the interpreter frame (the method lock if a sync method).
128
129 // Initialize monitors in the compiled activation.
130 // R3: pointer to osr buffer
131 //
132 // All other registers are dead at this point and the locals will be
133 // copied into place by code emitted in the IR.
134
135 Register OSR_buf = osrBufferPointer()->as_register();
136 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
137 int monitor_offset = BytesPerWord * method()->max_locals() +
138 (2 * BytesPerWord) * (number_of_locks - 1);
139 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
140 // the OSR buffer using 2 word entries: first the lock and then
141 // the oop.
142 for (int i = 0; i < number_of_locks; i++) {
143 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
144 #ifdef ASSERT
145 // Verify the interpreter's monitor has a non-null object.
146 {
147 Label L;
148 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
149 __ cmpdi(CCR0, R0, 0);
150 __ bne(CCR0, L);
151 __ stop("locked object is null");
152 __ bind(L);
153 }
154 #endif // ASSERT
155 // Copy the lock field into the compiled activation.
156 Address ml = frame_map()->address_for_monitor_lock(i),
157 mo = frame_map()->address_for_monitor_object(i);
158 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
159 __ ld(R0, slot_offset + 0, OSR_buf);
160 __ std(R0, ml.disp(), ml.base());
161 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
162 __ std(R0, mo.disp(), mo.base());
163 }
164 }
165 }
166
167
168 int LIR_Assembler::emit_exception_handler() {
169 // Generate code for the exception handler.
170 address handler_base = __ start_a_stub(exception_handler_size());
171
172 if (handler_base == nullptr) {
173 // Not enough space left for the handler.
174 bailout("exception handler overflow");
175 return -1;
176 }
177
178 int offset = code_offset();
179 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(C1StubId::handle_exception_from_callee_id));
180 //__ load_const_optimized(R0, entry_point);
181 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
182 __ mtctr(R0);
183 __ bctr();
184
185 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
186 __ end_a_stub();
187
188 return offset;
189 }
190
191
192 // Emit the code to remove the frame from the stack in the exception
193 // unwind path.
194 int LIR_Assembler::emit_unwind_handler() {
195 _masm->block_comment("Unwind handler");
196
197 int offset = code_offset();
198 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
199 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
200
201 // Fetch the exception from TLS and clear out exception related thread state.
202 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
203 __ li(R0, 0);
204 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
205 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
206
207 __ bind(_unwind_handler_entry);
208 __ verify_not_null_oop(Rexception);
209 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
210
211 // Perform needed unlocking
212 MonitorExitStub* stub = nullptr;
213 if (method()->is_synchronized()) {
214 monitor_address(0, FrameMap::R4_opr);
215 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
216 if (LockingMode == LM_MONITOR) {
217 __ b(*stub->entry());
218 } else {
219 __ unlock_object(R5, R6, R4, *stub->entry());
220 }
221 __ bind(*stub->continuation());
222 }
223
224 if (compilation()->env()->dtrace_method_probes()) {
225 Unimplemented();
226 }
227
228 // Dispatch to the unwind logic.
229 address unwind_stub = Runtime1::entry_for(C1StubId::unwind_exception_id);
230 //__ load_const_optimized(R0, unwind_stub);
231 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
232 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
233 __ mtctr(R0);
234 __ bctr();
235
236 // Emit the slow path assembly.
237 if (stub != nullptr) {
238 stub->emit_code(this);
239 }
240
241 return offset;
242 }
243
244
245 int LIR_Assembler::emit_deopt_handler() {
246 // Generate code for deopt handler.
247 address handler_base = __ start_a_stub(deopt_handler_size());
248
249 if (handler_base == nullptr) {
250 // Not enough space left for the handler.
251 bailout("deopt handler overflow");
252 return -1;
253 }
254
255 int offset = code_offset();
256 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
257
258 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
259 __ end_a_stub();
260
261 return offset;
262 }
263
264
265 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
266 if (o == nullptr) {
267 __ li(reg, 0);
268 } else {
269 AddressLiteral addrlit = __ constant_oop_address(o);
270 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
271 }
272 }
273
274
275 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
276 // Allocate a new index in table to hold the object once it's been patched.
277 int oop_index = __ oop_recorder()->allocate_oop_index(nullptr);
278 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
279
280 AddressLiteral addrlit((address)nullptr, oop_Relocation::spec(oop_index));
281 __ load_const(reg, addrlit, R0);
282
283 patching_epilog(patch, lir_patch_normal, reg, info);
284 }
285
286
287 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
288 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
289 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
290 }
291
292
293 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
294 // Allocate a new index in table to hold the klass once it's been patched.
295 int index = __ oop_recorder()->allocate_metadata_index(nullptr);
296 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
297
298 AddressLiteral addrlit((address)nullptr, metadata_Relocation::spec(index));
299 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
300 __ load_const(reg, addrlit, R0);
301
302 patching_epilog(patch, lir_patch_normal, reg, info);
303 }
304
305
306 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
307 const bool is_int = result->is_single_cpu();
308 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
309 Register Rdivisor = noreg;
310 Register Rscratch = temp->as_register();
311 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
312 long divisor = -1;
313
314 if (right->is_register()) {
315 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
316 } else {
317 divisor = is_int ? right->as_constant_ptr()->as_jint()
318 : right->as_constant_ptr()->as_jlong();
319 }
320
321 assert(Rdividend != Rscratch, "");
322 assert(Rdivisor != Rscratch, "");
323 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
324
325 if (Rdivisor == noreg) {
326 if (divisor == 1) { // stupid, but can happen
327 if (code == lir_idiv) {
328 __ mr_if_needed(Rresult, Rdividend);
329 } else {
330 __ li(Rresult, 0);
331 }
332
333 } else if (is_power_of_2(divisor)) {
334 // Convert division by a power of two into some shifts and logical operations.
335 int log2 = log2i_exact(divisor);
336
337 // Round towards 0.
338 if (divisor == 2) {
339 if (is_int) {
340 __ srwi(Rscratch, Rdividend, 31);
341 } else {
342 __ srdi(Rscratch, Rdividend, 63);
343 }
344 } else {
345 if (is_int) {
346 __ srawi(Rscratch, Rdividend, 31);
347 } else {
348 __ sradi(Rscratch, Rdividend, 63);
349 }
350 __ clrldi(Rscratch, Rscratch, 64-log2);
351 }
352 __ add(Rscratch, Rdividend, Rscratch);
353
354 if (code == lir_idiv) {
355 if (is_int) {
356 __ srawi(Rresult, Rscratch, log2);
357 } else {
358 __ sradi(Rresult, Rscratch, log2);
359 }
360 } else { // lir_irem
361 __ clrrdi(Rscratch, Rscratch, log2);
362 __ sub(Rresult, Rdividend, Rscratch);
363 }
364
365 } else if (divisor == -1) {
366 if (code == lir_idiv) {
367 __ neg(Rresult, Rdividend);
368 } else {
369 __ li(Rresult, 0);
370 }
371
372 } else {
373 __ load_const_optimized(Rscratch, divisor);
374 if (code == lir_idiv) {
375 if (is_int) {
376 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
377 } else {
378 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
379 }
380 } else {
381 assert(Rscratch != R0, "need both");
382 if (is_int) {
383 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
384 __ mullw(Rscratch, R0, Rscratch);
385 } else {
386 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
387 __ mulld(Rscratch, R0, Rscratch);
388 }
389 __ sub(Rresult, Rdividend, Rscratch);
390 }
391
392 }
393 return;
394 }
395
396 Label regular, done;
397 if (is_int) {
398 __ cmpwi(CCR0, Rdivisor, -1);
399 } else {
400 __ cmpdi(CCR0, Rdivisor, -1);
401 }
402 __ bne(CCR0, regular);
403 if (code == lir_idiv) {
404 __ neg(Rresult, Rdividend);
405 __ b(done);
406 __ bind(regular);
407 if (is_int) {
408 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
409 } else {
410 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
411 }
412 } else { // lir_irem
413 __ li(Rresult, 0);
414 __ b(done);
415 __ bind(regular);
416 if (is_int) {
417 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
418 __ mullw(Rscratch, Rscratch, Rdivisor);
419 } else {
420 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
421 __ mulld(Rscratch, Rscratch, Rdivisor);
422 }
423 __ sub(Rresult, Rdividend, Rscratch);
424 }
425 __ bind(done);
426 }
427
428
429 void LIR_Assembler::emit_op3(LIR_Op3* op) {
430 switch (op->code()) {
431 case lir_idiv:
432 case lir_irem:
433 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
434 op->result_opr(), op->info());
435 break;
436 case lir_fmad:
437 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
438 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
439 break;
440 case lir_fmaf:
441 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
442 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
443 break;
444 default: ShouldNotReachHere(); break;
445 }
446 }
447
448
449 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
450 #ifdef ASSERT
451 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
452 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
453 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
454 assert(op->info() == nullptr, "shouldn't have CodeEmitInfo");
455 #endif
456
457 Label *L = op->label();
458 if (op->cond() == lir_cond_always) {
459 __ b(*L);
460 } else {
461 Label done;
462 bool is_unordered = false;
463 if (op->code() == lir_cond_float_branch) {
464 assert(op->ublock() != nullptr, "must have unordered successor");
465 is_unordered = true;
466 } else {
467 assert(op->code() == lir_branch, "just checking");
468 }
469
470 bool positive = false;
471 Assembler::Condition cond = Assembler::equal;
472 switch (op->cond()) {
473 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
474 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
475 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
476 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
477 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
478 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
479 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
480 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
481 default: ShouldNotReachHere();
482 }
483 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
484 int bi = Assembler::bi0(BOOL_RESULT, cond);
485 if (is_unordered) {
486 if (positive) {
487 if (op->ublock() == op->block()) {
488 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
489 }
490 } else {
491 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
492 }
493 }
494 __ bc_far_optimized(bo, bi, *L);
495 __ bind(done);
496 }
497 }
498
499
500 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
501 Bytecodes::Code code = op->bytecode();
502 LIR_Opr src = op->in_opr(),
503 dst = op->result_opr();
504
505 switch(code) {
506 case Bytecodes::_i2l: {
507 __ extsw(dst->as_register_lo(), src->as_register());
508 break;
509 }
510 case Bytecodes::_l2i: {
511 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
512 break;
513 }
514 case Bytecodes::_i2b: {
515 __ extsb(dst->as_register(), src->as_register());
516 break;
517 }
518 case Bytecodes::_i2c: {
519 __ clrldi(dst->as_register(), src->as_register(), 64-16);
520 break;
521 }
522 case Bytecodes::_i2s: {
523 __ extsh(dst->as_register(), src->as_register());
524 break;
525 }
526 case Bytecodes::_i2d:
527 case Bytecodes::_l2d: {
528 bool src_in_memory = !VM_Version::has_mtfprd();
529 FloatRegister rdst = dst->as_double_reg();
530 FloatRegister rsrc;
531 if (src_in_memory) {
532 rsrc = src->as_double_reg(); // via mem
533 } else {
534 // move src to dst register
535 if (code == Bytecodes::_i2d) {
536 __ mtfprwa(rdst, src->as_register());
537 } else {
538 __ mtfprd(rdst, src->as_register_lo());
539 }
540 rsrc = rdst;
541 }
542 __ fcfid(rdst, rsrc);
543 break;
544 }
545 case Bytecodes::_i2f:
546 case Bytecodes::_l2f: {
547 bool src_in_memory = !VM_Version::has_mtfprd();
548 FloatRegister rdst = dst->as_float_reg();
549 FloatRegister rsrc;
550 if (src_in_memory) {
551 rsrc = src->as_double_reg(); // via mem
552 } else {
553 // move src to dst register
554 if (code == Bytecodes::_i2f) {
555 __ mtfprwa(rdst, src->as_register());
556 } else {
557 __ mtfprd(rdst, src->as_register_lo());
558 }
559 rsrc = rdst;
560 }
561 if (VM_Version::has_fcfids()) {
562 __ fcfids(rdst, rsrc);
563 } else {
564 assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
565 __ fcfid(rdst, rsrc);
566 __ frsp(rdst, rdst);
567 }
568 break;
569 }
570 case Bytecodes::_f2d: {
571 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
572 break;
573 }
574 case Bytecodes::_d2f: {
575 __ frsp(dst->as_float_reg(), src->as_double_reg());
576 break;
577 }
578 case Bytecodes::_d2i:
579 case Bytecodes::_f2i: {
580 bool dst_in_memory = !VM_Version::has_mtfprd();
581 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
582 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
583 Label L;
584 // Result must be 0 if value is NaN; test by comparing value to itself.
585 __ fcmpu(CCR0, rsrc, rsrc);
586 if (dst_in_memory) {
587 __ li(R0, 0); // 0 in case of NAN
588 __ std(R0, addr.disp(), addr.base());
589 } else {
590 __ li(dst->as_register(), 0);
591 }
592 __ bso(CCR0, L);
593 __ fctiwz(rsrc, rsrc); // USE_KILL
594 if (dst_in_memory) {
595 __ stfd(rsrc, addr.disp(), addr.base());
596 } else {
597 __ mffprd(dst->as_register(), rsrc);
598 }
599 __ bind(L);
600 break;
601 }
602 case Bytecodes::_d2l:
603 case Bytecodes::_f2l: {
604 bool dst_in_memory = !VM_Version::has_mtfprd();
605 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
606 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
607 Label L;
608 // Result must be 0 if value is NaN; test by comparing value to itself.
609 __ fcmpu(CCR0, rsrc, rsrc);
610 if (dst_in_memory) {
611 __ li(R0, 0); // 0 in case of NAN
612 __ std(R0, addr.disp(), addr.base());
613 } else {
614 __ li(dst->as_register_lo(), 0);
615 }
616 __ bso(CCR0, L);
617 __ fctidz(rsrc, rsrc); // USE_KILL
618 if (dst_in_memory) {
619 __ stfd(rsrc, addr.disp(), addr.base());
620 } else {
621 __ mffprd(dst->as_register_lo(), rsrc);
622 }
623 __ bind(L);
624 break;
625 }
626
627 default: ShouldNotReachHere();
628 }
629 }
630
631
632 void LIR_Assembler::align_call(LIR_Code) {
633 // do nothing since all instructions are word aligned on ppc
634 }
635
636
637 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
638 int start_offset = __ offset();
639 // Put the entry point as a constant into the constant pool.
640 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
641 if (entry_point_toc_addr == nullptr) {
642 bailout("const section overflow");
643 return false;
644 }
645 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
646
647 // Emit the trampoline stub which will be related to the branch-and-link below.
648 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
649 if (!stub) {
650 bailout("no space for trampoline stub");
651 return false;
652 }
653 return true;
654 }
655
656
657 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
658 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
659
660 bool success = emit_trampoline_stub_for_call(op->addr());
661 if (!success) { return; }
662
663 __ relocate(rtype);
664 // Note: At this point we do not have the address of the trampoline
665 // stub, and the entry point might be too far away for bl, so __ pc()
666 // serves as dummy and the bl will be patched later.
667 __ code()->set_insts_mark();
668 __ bl(__ pc());
669 add_call_info(code_offset(), op->info());
670 __ post_call_nop();
671 }
672
673
674 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
675 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
676
677 // Virtual call relocation will point to ic load.
678 address virtual_call_meta_addr = __ pc();
679 // Load a clear inline cache.
680 AddressLiteral empty_ic((address) Universe::non_oop_word());
681 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
682 if (!success) {
683 bailout("const section overflow");
684 return;
685 }
686 // Call to fixup routine. Fixup routine uses ScopeDesc info
687 // to determine who we intended to call.
688 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
689
690 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
691 if (!success) { return; }
692
693 // Note: At this point we do not have the address of the trampoline
694 // stub, and the entry point might be too far away for bl, so __ pc()
695 // serves as dummy and the bl will be patched later.
696 __ bl(__ pc());
697 add_call_info(code_offset(), op->info());
698 __ post_call_nop();
699 }
700
701 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
702 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
703 __ null_check(addr, stub->entry());
704 append_code_stub(stub);
705 }
706
707
708 // Attention: caller must encode oop if needed
709 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
710 int store_offset;
711 if (!Assembler::is_simm16(offset)) {
712 // For offsets larger than a simm16 we setup the offset.
713 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
714 __ load_const_optimized(R0, offset);
715 store_offset = store(from_reg, base, R0, type, wide);
716 } else {
717 store_offset = code_offset();
718 switch (type) {
719 case T_BOOLEAN: // fall through
720 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
721 case T_CHAR :
722 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
723 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
724 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
725 case T_ADDRESS:
726 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
727 case T_ARRAY : // fall through
728 case T_OBJECT:
729 {
730 if (UseCompressedOops && !wide) {
731 // Encoding done in caller
732 __ stw(from_reg->as_register(), offset, base);
733 __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
734 } else {
735 __ std(from_reg->as_register(), offset, base);
736 if (VerifyOops) {
737 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
738 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
739 }
740 }
741 break;
742 }
743 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
744 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
745 default : ShouldNotReachHere();
746 }
747 }
748 return store_offset;
749 }
750
751
752 // Attention: caller must encode oop if needed
753 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
754 int store_offset = code_offset();
755 switch (type) {
756 case T_BOOLEAN: // fall through
757 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
758 case T_CHAR :
759 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
760 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
761 case T_LONG :
762 #ifdef _LP64
763 __ stdx(from_reg->as_register_lo(), base, disp);
764 #else
765 Unimplemented();
766 #endif
767 break;
768 case T_ADDRESS:
769 __ stdx(from_reg->as_register(), base, disp);
770 break;
771 case T_ARRAY : // fall through
772 case T_OBJECT:
773 {
774 if (UseCompressedOops && !wide) {
775 // Encoding done in caller.
776 __ stwx(from_reg->as_register(), base, disp);
777 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
778 } else {
779 __ stdx(from_reg->as_register(), base, disp);
780 if (VerifyOops) {
781 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
782 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
783 }
784 }
785 break;
786 }
787 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
788 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
789 default : ShouldNotReachHere();
790 }
791 return store_offset;
792 }
793
794
795 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
796 int load_offset;
797 if (!Assembler::is_simm16(offset)) {
798 // For offsets larger than a simm16 we setup the offset.
799 __ load_const_optimized(R0, offset);
800 load_offset = load(base, R0, to_reg, type, wide);
801 } else {
802 load_offset = code_offset();
803 switch(type) {
804 case T_BOOLEAN: // fall through
805 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
806 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
807 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
808 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
809 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
810 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
811 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
812 case T_ADDRESS:
813 __ ld(to_reg->as_register(), offset, base);
814 break;
815 case T_ARRAY : // fall through
816 case T_OBJECT:
817 {
818 if (UseCompressedOops && !wide) {
819 __ lwz(to_reg->as_register(), offset, base);
820 __ decode_heap_oop(to_reg->as_register());
821 } else {
822 __ ld(to_reg->as_register(), offset, base);
823 }
824 break;
825 }
826 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
827 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
828 default : ShouldNotReachHere();
829 }
830 }
831 return load_offset;
832 }
833
834
835 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
836 int load_offset = code_offset();
837 switch(type) {
838 case T_BOOLEAN: // fall through
839 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
840 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
841 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
842 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
843 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
844 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
845 case T_ARRAY : // fall through
846 case T_OBJECT:
847 {
848 if (UseCompressedOops && !wide) {
849 __ lwzx(to_reg->as_register(), base, disp);
850 __ decode_heap_oop(to_reg->as_register());
851 } else {
852 __ ldx(to_reg->as_register(), base, disp);
853 }
854 break;
855 }
856 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
857 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
858 case T_LONG :
859 #ifdef _LP64
860 __ ldx(to_reg->as_register_lo(), base, disp);
861 #else
862 Unimplemented();
863 #endif
864 break;
865 default : ShouldNotReachHere();
866 }
867 return load_offset;
868 }
869
870
871 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
872 LIR_Const* c = src->as_constant_ptr();
873 Register src_reg = R0;
874 switch (c->type()) {
875 case T_INT:
876 case T_FLOAT: {
877 int value = c->as_jint_bits();
878 __ load_const_optimized(src_reg, value);
879 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
880 __ stw(src_reg, addr.disp(), addr.base());
881 break;
882 }
883 case T_ADDRESS: {
884 int value = c->as_jint_bits();
885 __ load_const_optimized(src_reg, value);
886 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
887 __ std(src_reg, addr.disp(), addr.base());
888 break;
889 }
890 case T_OBJECT: {
891 jobject2reg(c->as_jobject(), src_reg);
892 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
893 __ std(src_reg, addr.disp(), addr.base());
894 break;
895 }
896 case T_LONG:
897 case T_DOUBLE: {
898 int value = c->as_jlong_bits();
899 __ load_const_optimized(src_reg, value);
900 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
901 __ std(src_reg, addr.disp(), addr.base());
902 break;
903 }
904 default:
905 Unimplemented();
906 }
907 }
908
909
910 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
911 LIR_Const* c = src->as_constant_ptr();
912 LIR_Address* addr = dest->as_address_ptr();
913 Register base = addr->base()->as_pointer_register();
914 LIR_Opr tmp = LIR_OprFact::illegalOpr;
915 int offset = -1;
916 // Null check for large offsets in LIRGenerator::do_StoreField.
917 bool needs_explicit_null_check = !ImplicitNullChecks;
918
919 if (info != nullptr && needs_explicit_null_check) {
920 explicit_null_check(base, info);
921 }
922
923 switch (c->type()) {
924 case T_FLOAT: type = T_INT;
925 case T_INT:
926 case T_ADDRESS: {
927 tmp = FrameMap::R0_opr;
928 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
929 break;
930 }
931 case T_DOUBLE: type = T_LONG;
932 case T_LONG: {
933 tmp = FrameMap::R0_long_opr;
934 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
935 break;
936 }
937 case T_OBJECT: {
938 tmp = FrameMap::R0_opr;
939 if (UseCompressedOops && !wide && c->as_jobject() != nullptr) {
940 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
941 // Don't care about sign extend (will use stw).
942 __ lis(R0, 0); // Will get patched.
943 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
944 __ ori(R0, R0, 0); // Will get patched.
945 } else {
946 jobject2reg(c->as_jobject(), R0);
947 }
948 break;
949 }
950 default:
951 Unimplemented();
952 }
953
954 // Handle either reg+reg or reg+disp address.
955 if (addr->index()->is_valid()) {
956 assert(addr->disp() == 0, "must be zero");
957 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
958 } else {
959 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
960 offset = store(tmp, base, addr->disp(), type, wide);
961 }
962
963 if (info != nullptr) {
964 assert(offset != -1, "offset should've been set");
965 if (!needs_explicit_null_check) {
966 add_debug_info_for_null_check(offset, info);
967 }
968 }
969 }
970
971
972 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
973 LIR_Const* c = src->as_constant_ptr();
974 LIR_Opr to_reg = dest;
975
976 switch (c->type()) {
977 case T_INT: {
978 assert(patch_code == lir_patch_none, "no patching handled here");
979 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
980 break;
981 }
982 case T_ADDRESS: {
983 assert(patch_code == lir_patch_none, "no patching handled here");
984 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
985 break;
986 }
987 case T_LONG: {
988 assert(patch_code == lir_patch_none, "no patching handled here");
989 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
990 break;
991 }
992
993 case T_OBJECT: {
994 if (patch_code == lir_patch_none) {
995 jobject2reg(c->as_jobject(), to_reg->as_register());
996 } else {
997 jobject2reg_with_patching(to_reg->as_register(), info);
998 }
999 break;
1000 }
1001
1002 case T_METADATA:
1003 {
1004 if (patch_code == lir_patch_none) {
1005 metadata2reg(c->as_metadata(), to_reg->as_register());
1006 } else {
1007 klass2reg_with_patching(to_reg->as_register(), info);
1008 }
1009 }
1010 break;
1011
1012 case T_FLOAT:
1013 {
1014 if (to_reg->is_single_fpu()) {
1015 address const_addr = __ float_constant(c->as_jfloat());
1016 if (const_addr == nullptr) {
1017 bailout("const section overflow");
1018 break;
1019 }
1020 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1021 __ relocate(rspec);
1022 __ load_const(R0, const_addr);
1023 __ lfsx(to_reg->as_float_reg(), R0);
1024 } else {
1025 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1026 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1027 }
1028 }
1029 break;
1030
1031 case T_DOUBLE:
1032 {
1033 if (to_reg->is_double_fpu()) {
1034 address const_addr = __ double_constant(c->as_jdouble());
1035 if (const_addr == nullptr) {
1036 bailout("const section overflow");
1037 break;
1038 }
1039 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1040 __ relocate(rspec);
1041 __ load_const(R0, const_addr);
1042 __ lfdx(to_reg->as_double_reg(), R0);
1043 } else {
1044 assert(to_reg->is_double_cpu(), "Must be a long register.");
1045 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1046 }
1047 }
1048 break;
1049
1050 default:
1051 ShouldNotReachHere();
1052 }
1053 }
1054
1055
1056 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1057 Unimplemented(); return Address();
1058 }
1059
1060
1061 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1062 if (addr->index()->is_illegal()) {
1063 return (RegisterOrConstant)(addr->disp());
1064 } else {
1065 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1066 }
1067 }
1068
1069
1070 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1071 const Register tmp = R0;
1072 switch (type) {
1073 case T_INT:
1074 case T_FLOAT: {
1075 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1076 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1077 __ lwz(tmp, from.disp(), from.base());
1078 __ stw(tmp, to.disp(), to.base());
1079 break;
1080 }
1081 case T_ADDRESS:
1082 case T_OBJECT: {
1083 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1084 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1085 __ ld(tmp, from.disp(), from.base());
1086 __ std(tmp, to.disp(), to.base());
1087 break;
1088 }
1089 case T_LONG:
1090 case T_DOUBLE: {
1091 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1092 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1093 __ ld(tmp, from.disp(), from.base());
1094 __ std(tmp, to.disp(), to.base());
1095 break;
1096 }
1097
1098 default:
1099 ShouldNotReachHere();
1100 }
1101 }
1102
1103
1104 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1105 Unimplemented(); return Address();
1106 }
1107
1108
1109 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1110 Unimplemented(); return Address();
1111 }
1112
1113
1114 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1115 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1116
1117 assert(type != T_METADATA, "load of metadata ptr not supported");
1118 LIR_Address* addr = src_opr->as_address_ptr();
1119 LIR_Opr to_reg = dest;
1120
1121 Register src = addr->base()->as_pointer_register();
1122 Register disp_reg = noreg;
1123 int disp_value = addr->disp();
1124 bool needs_patching = (patch_code != lir_patch_none);
1125 // null check for large offsets in LIRGenerator::do_LoadField
1126 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1127
1128 if (info != nullptr && needs_explicit_null_check) {
1129 explicit_null_check(src, info);
1130 }
1131
1132 if (addr->base()->type() == T_OBJECT) {
1133 __ verify_oop(src, FILE_AND_LINE);
1134 }
1135
1136 PatchingStub* patch = nullptr;
1137 if (needs_patching) {
1138 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1139 assert(!to_reg->is_double_cpu() ||
1140 patch_code == lir_patch_none ||
1141 patch_code == lir_patch_normal, "patching doesn't match register");
1142 }
1143
1144 if (addr->index()->is_illegal()) {
1145 if (!Assembler::is_simm16(disp_value)) {
1146 if (needs_patching) {
1147 __ load_const32(R0, 0); // patchable int
1148 } else {
1149 __ load_const_optimized(R0, disp_value);
1150 }
1151 disp_reg = R0;
1152 }
1153 } else {
1154 disp_reg = addr->index()->as_pointer_register();
1155 assert(disp_value == 0, "can't handle 3 operand addresses");
1156 }
1157
1158 // Remember the offset of the load. The patching_epilog must be done
1159 // before the call to add_debug_info, otherwise the PcDescs don't get
1160 // entered in increasing order.
1161 int offset;
1162
1163 if (disp_reg == noreg) {
1164 assert(Assembler::is_simm16(disp_value), "should have set this up");
1165 offset = load(src, disp_value, to_reg, type, wide);
1166 } else {
1167 offset = load(src, disp_reg, to_reg, type, wide);
1168 }
1169
1170 if (patch != nullptr) {
1171 patching_epilog(patch, patch_code, src, info);
1172 }
1173 if (info != nullptr && !needs_explicit_null_check) {
1174 add_debug_info_for_null_check(offset, info);
1175 }
1176 }
1177
1178
1179 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1180 Address addr;
1181 if (src->is_single_word()) {
1182 addr = frame_map()->address_for_slot(src->single_stack_ix());
1183 } else if (src->is_double_word()) {
1184 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1185 }
1186
1187 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1188 }
1189
1190
1191 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1192 Address addr;
1193 if (dest->is_single_word()) {
1194 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1195 } else if (dest->is_double_word()) {
1196 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1197 }
1198
1199 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1200 }
1201
1202
1203 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1204 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1205 if (from_reg->is_double_fpu()) {
1206 // double to double moves
1207 assert(to_reg->is_double_fpu(), "should match");
1208 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1209 } else {
1210 // float to float moves
1211 assert(to_reg->is_single_fpu(), "should match");
1212 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1213 }
1214 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1215 if (from_reg->is_double_cpu()) {
1216 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1217 } else if (to_reg->is_double_cpu()) {
1218 // int to int moves
1219 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1220 } else {
1221 // int to int moves
1222 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1223 }
1224 } else {
1225 ShouldNotReachHere();
1226 }
1227 if (is_reference_type(to_reg->type())) {
1228 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1229 }
1230 }
1231
1232
1233 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1234 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1235 bool wide) {
1236 assert(type != T_METADATA, "store of metadata ptr not supported");
1237 LIR_Address* addr = dest->as_address_ptr();
1238
1239 Register src = addr->base()->as_pointer_register();
1240 Register disp_reg = noreg;
1241 int disp_value = addr->disp();
1242 bool needs_patching = (patch_code != lir_patch_none);
1243 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1244 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1245 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1246 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1247 // Null check for large offsets in LIRGenerator::do_StoreField.
1248 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1249
1250 if (info != nullptr && needs_explicit_null_check) {
1251 explicit_null_check(src, info);
1252 }
1253
1254 if (addr->base()->is_oop_register()) {
1255 __ verify_oop(src, FILE_AND_LINE);
1256 }
1257
1258 PatchingStub* patch = nullptr;
1259 if (needs_patching) {
1260 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1261 assert(!from_reg->is_double_cpu() ||
1262 patch_code == lir_patch_none ||
1263 patch_code == lir_patch_normal, "patching doesn't match register");
1264 }
1265
1266 if (addr->index()->is_illegal()) {
1267 if (load_disp) {
1268 disp_reg = use_R29 ? R29_TOC : R0;
1269 if (needs_patching) {
1270 __ load_const32(disp_reg, 0); // patchable int
1271 } else {
1272 __ load_const_optimized(disp_reg, disp_value);
1273 }
1274 }
1275 } else {
1276 disp_reg = addr->index()->as_pointer_register();
1277 assert(disp_value == 0, "can't handle 3 operand addresses");
1278 }
1279
1280 // remember the offset of the store. The patching_epilog must be done
1281 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1282 // entered in increasing order.
1283 int offset;
1284
1285 if (compress_oop) {
1286 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1287 from_reg = FrameMap::as_opr(co);
1288 }
1289
1290 if (disp_reg == noreg) {
1291 assert(Assembler::is_simm16(disp_value), "should have set this up");
1292 offset = store(from_reg, src, disp_value, type, wide);
1293 } else {
1294 offset = store(from_reg, src, disp_reg, type, wide);
1295 }
1296
1297 if (use_R29) {
1298 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1299 }
1300
1301 if (patch != nullptr) {
1302 patching_epilog(patch, patch_code, src, info);
1303 }
1304
1305 if (info != nullptr && !needs_explicit_null_check) {
1306 add_debug_info_for_null_check(offset, info);
1307 }
1308 }
1309
1310
1311 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1312 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1313 const Register temp = R12;
1314
1315 // Pop the stack before the safepoint code.
1316 int frame_size = initial_frame_size_in_bytes();
1317 if (Assembler::is_simm(frame_size, 16)) {
1318 __ addi(R1_SP, R1_SP, frame_size);
1319 } else {
1320 __ pop_frame();
1321 }
1322
1323 // Restore return pc relative to callers' sp.
1324 __ ld(return_pc, _abi0(lr), R1_SP);
1325 // Move return pc to LR.
1326 __ mtlr(return_pc);
1327
1328 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1329 __ reserved_stack_check(return_pc);
1330 }
1331
1332 // We need to mark the code position where the load from the safepoint
1333 // polling page was emitted as relocInfo::poll_return_type here.
1334 if (!UseSIGTRAP) {
1335 code_stub->set_safepoint_offset(__ offset());
1336 __ relocate(relocInfo::poll_return_type);
1337 }
1338 __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1339
1340 // Return.
1341 __ blr();
1342 }
1343
1344
1345 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1346 const Register poll_addr = tmp->as_register();
1347 __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1348 if (info != nullptr) {
1349 add_debug_info_for_branch(info);
1350 }
1351 int offset = __ offset();
1352 __ relocate(relocInfo::poll_type);
1353 __ load_from_polling_page(poll_addr);
1354
1355 return offset;
1356 }
1357
1358
1359 void LIR_Assembler::emit_static_call_stub() {
1360 address call_pc = __ pc();
1361 address stub = __ start_a_stub(static_call_stub_size());
1362 if (stub == nullptr) {
1363 bailout("static call stub overflow");
1364 return;
1365 }
1366
1367 // For java_to_interp stubs we use R11_scratch1 as scratch register
1368 // and in call trampoline stubs we use R12_scratch2. This way we
1369 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1370 const Register reg_scratch = R11_scratch1;
1371
1372 // Create a static stub relocation which relates this stub
1373 // with the call instruction at insts_call_instruction_offset in the
1374 // instructions code-section.
1375 int start = __ offset();
1376 __ relocate(static_stub_Relocation::spec(call_pc));
1377
1378 // Now, create the stub's code:
1379 // - load the TOC
1380 // - load the inline cache oop from the constant pool
1381 // - load the call target from the constant pool
1382 // - call
1383 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1384 AddressLiteral ic = __ allocate_metadata_address((Metadata *)nullptr);
1385 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1386
1387 if (ReoptimizeCallSequences) {
1388 __ b64_patchable((address)-1, relocInfo::none);
1389 } else {
1390 AddressLiteral a((address)-1);
1391 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1392 __ mtctr(reg_scratch);
1393 __ bctr();
1394 }
1395 if (!success) {
1396 bailout("const section overflow");
1397 return;
1398 }
1399
1400 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1401 __ end_a_stub();
1402 }
1403
1404
1405 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1406 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1407 if (opr1->is_single_fpu()) {
1408 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1409 } else if (opr1->is_double_fpu()) {
1410 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1411 } else if (opr1->is_single_cpu()) {
1412 if (opr2->is_constant()) {
1413 switch (opr2->as_constant_ptr()->type()) {
1414 case T_INT:
1415 {
1416 jint con = opr2->as_constant_ptr()->as_jint();
1417 if (unsigned_comp) {
1418 if (Assembler::is_uimm(con, 16)) {
1419 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1420 } else {
1421 __ load_const_optimized(R0, con);
1422 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1423 }
1424 } else {
1425 if (Assembler::is_simm(con, 16)) {
1426 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1427 } else {
1428 __ load_const_optimized(R0, con);
1429 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1430 }
1431 }
1432 }
1433 break;
1434
1435 case T_OBJECT:
1436 // There are only equal/notequal comparisons on objects.
1437 {
1438 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1439 jobject con = opr2->as_constant_ptr()->as_jobject();
1440 if (con == nullptr) {
1441 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1442 } else {
1443 jobject2reg(con, R0);
1444 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1445 }
1446 }
1447 break;
1448
1449 case T_METADATA:
1450 // We only need, for now, comparison with null for metadata.
1451 {
1452 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1453 Metadata* p = opr2->as_constant_ptr()->as_metadata();
1454 if (p == nullptr) {
1455 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1456 } else {
1457 ShouldNotReachHere();
1458 }
1459 }
1460 break;
1461
1462 default:
1463 ShouldNotReachHere();
1464 break;
1465 }
1466 } else {
1467 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1468 if (is_reference_type(opr1->type())) {
1469 // There are only equal/notequal comparisons on objects.
1470 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1471 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1472 } else {
1473 if (unsigned_comp) {
1474 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1475 } else {
1476 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1477 }
1478 }
1479 }
1480 } else if (opr1->is_double_cpu()) {
1481 if (opr2->is_constant()) {
1482 jlong con = opr2->as_constant_ptr()->as_jlong();
1483 if (unsigned_comp) {
1484 if (Assembler::is_uimm(con, 16)) {
1485 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1486 } else {
1487 __ load_const_optimized(R0, con);
1488 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1489 }
1490 } else {
1491 if (Assembler::is_simm(con, 16)) {
1492 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1493 } else {
1494 __ load_const_optimized(R0, con);
1495 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1496 }
1497 }
1498 } else if (opr2->is_register()) {
1499 if (unsigned_comp) {
1500 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1501 } else {
1502 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1503 }
1504 } else {
1505 ShouldNotReachHere();
1506 }
1507 } else {
1508 ShouldNotReachHere();
1509 }
1510 }
1511
1512
1513 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1514 const Register Rdst = dst->as_register();
1515 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1516 bool is_unordered_less = (code == lir_ucmp_fd2i);
1517 if (left->is_single_fpu()) {
1518 __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1519 } else if (left->is_double_fpu()) {
1520 __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1521 } else {
1522 ShouldNotReachHere();
1523 }
1524 __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1525 } else if (code == lir_cmp_l2i) {
1526 __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1527 __ set_cmp3(Rdst); // set result as follows: <: -1, =: 0, >: 1
1528 } else {
1529 ShouldNotReachHere();
1530 }
1531 }
1532
1533
1534 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1535 if (src->is_constant()) {
1536 lasm->const2reg(src, dst, lir_patch_none, nullptr);
1537 } else if (src->is_register()) {
1538 lasm->reg2reg(src, dst);
1539 } else if (src->is_stack()) {
1540 lasm->stack2reg(src, dst, dst->type());
1541 } else {
1542 ShouldNotReachHere();
1543 }
1544 }
1545
1546 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1547 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1548 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
1549
1550 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1551 load_to_reg(this, opr1, result); // Condition doesn't matter.
1552 return;
1553 }
1554
1555 bool positive = false;
1556 Assembler::Condition cond = Assembler::equal;
1557 switch (condition) {
1558 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1559 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1560 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1561 case lir_cond_belowEqual:
1562 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1563 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1564 case lir_cond_aboveEqual:
1565 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1566 default: ShouldNotReachHere();
1567 }
1568
1569 // Try to use isel on >=Power7.
1570 if (VM_Version::has_isel() && result->is_cpu_register()) {
1571 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1572 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1573
1574 // We can use result_reg to load one operand if not already in register.
1575 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1576 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1577
1578 if (first != second) {
1579 if (!o1_is_reg) {
1580 load_to_reg(this, opr1, result);
1581 }
1582
1583 if (!o2_is_reg) {
1584 load_to_reg(this, opr2, result);
1585 }
1586
1587 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1588 return;
1589 }
1590 } // isel
1591
1592 load_to_reg(this, opr1, result);
1593
1594 Label skip;
1595 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1596 int bi = Assembler::bi0(BOOL_RESULT, cond);
1597 __ bc(bo, bi, skip);
1598
1599 load_to_reg(this, opr2, result);
1600 __ bind(skip);
1601 }
1602
1603
1604 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1605 CodeEmitInfo* info, bool pop_fpu_stack) {
1606 assert(info == nullptr, "unused on this code path");
1607 assert(left->is_register(), "wrong items state");
1608 assert(dest->is_register(), "wrong items state");
1609
1610 if (right->is_register()) {
1611 if (dest->is_float_kind()) {
1612
1613 FloatRegister lreg, rreg, res;
1614 if (right->is_single_fpu()) {
1615 lreg = left->as_float_reg();
1616 rreg = right->as_float_reg();
1617 res = dest->as_float_reg();
1618 switch (code) {
1619 case lir_add: __ fadds(res, lreg, rreg); break;
1620 case lir_sub: __ fsubs(res, lreg, rreg); break;
1621 case lir_mul: __ fmuls(res, lreg, rreg); break;
1622 case lir_div: __ fdivs(res, lreg, rreg); break;
1623 default: ShouldNotReachHere();
1624 }
1625 } else {
1626 lreg = left->as_double_reg();
1627 rreg = right->as_double_reg();
1628 res = dest->as_double_reg();
1629 switch (code) {
1630 case lir_add: __ fadd(res, lreg, rreg); break;
1631 case lir_sub: __ fsub(res, lreg, rreg); break;
1632 case lir_mul: __ fmul(res, lreg, rreg); break;
1633 case lir_div: __ fdiv(res, lreg, rreg); break;
1634 default: ShouldNotReachHere();
1635 }
1636 }
1637
1638 } else if (dest->is_double_cpu()) {
1639
1640 Register dst_lo = dest->as_register_lo();
1641 Register op1_lo = left->as_pointer_register();
1642 Register op2_lo = right->as_pointer_register();
1643
1644 switch (code) {
1645 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1646 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1647 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1648 default: ShouldNotReachHere();
1649 }
1650 } else {
1651 assert (right->is_single_cpu(), "Just Checking");
1652
1653 Register lreg = left->as_register();
1654 Register res = dest->as_register();
1655 Register rreg = right->as_register();
1656 switch (code) {
1657 case lir_add: __ add (res, lreg, rreg); break;
1658 case lir_sub: __ sub (res, lreg, rreg); break;
1659 case lir_mul: __ mullw(res, lreg, rreg); break;
1660 default: ShouldNotReachHere();
1661 }
1662 }
1663 } else {
1664 assert (right->is_constant(), "must be constant");
1665
1666 if (dest->is_single_cpu()) {
1667 Register lreg = left->as_register();
1668 Register res = dest->as_register();
1669 int simm16 = right->as_constant_ptr()->as_jint();
1670
1671 switch (code) {
1672 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1673 simm16 = -simm16;
1674 case lir_add: if (res == lreg && simm16 == 0) break;
1675 __ addi(res, lreg, simm16); break;
1676 case lir_mul: if (res == lreg && simm16 == 1) break;
1677 __ mulli(res, lreg, simm16); break;
1678 default: ShouldNotReachHere();
1679 }
1680 } else {
1681 Register lreg = left->as_pointer_register();
1682 Register res = dest->as_register_lo();
1683 long con = right->as_constant_ptr()->as_jlong();
1684 assert(Assembler::is_simm16(con), "must be simm16");
1685
1686 switch (code) {
1687 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1688 con = -con;
1689 case lir_add: if (res == lreg && con == 0) break;
1690 __ addi(res, lreg, (int)con); break;
1691 case lir_mul: if (res == lreg && con == 1) break;
1692 __ mulli(res, lreg, (int)con); break;
1693 default: ShouldNotReachHere();
1694 }
1695 }
1696 }
1697 }
1698
1699
1700 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1701 switch (code) {
1702 case lir_sqrt: {
1703 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1704 break;
1705 }
1706 case lir_abs: {
1707 __ fabs(dest->as_double_reg(), value->as_double_reg());
1708 break;
1709 }
1710 default: {
1711 ShouldNotReachHere();
1712 break;
1713 }
1714 }
1715 }
1716
1717
1718 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1719 if (right->is_constant()) { // see do_LogicOp
1720 long uimm;
1721 Register d, l;
1722 if (dest->is_single_cpu()) {
1723 uimm = right->as_constant_ptr()->as_jint();
1724 d = dest->as_register();
1725 l = left->as_register();
1726 } else {
1727 uimm = right->as_constant_ptr()->as_jlong();
1728 d = dest->as_register_lo();
1729 l = left->as_register_lo();
1730 }
1731 long uimms = (unsigned long)uimm >> 16,
1732 uimmss = (unsigned long)uimm >> 32;
1733
1734 switch (code) {
1735 case lir_logic_and:
1736 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1737 __ andi(d, l, uimm); // special cases
1738 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1739 else { __ andi_(d, l, uimm); }
1740 break;
1741
1742 case lir_logic_or:
1743 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1744 else { __ ori(d, l, uimm); }
1745 break;
1746
1747 case lir_logic_xor:
1748 if (uimm == -1) { __ nand(d, l, l); } // special case
1749 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1750 else { __ xori(d, l, uimm); }
1751 break;
1752
1753 default: ShouldNotReachHere();
1754 }
1755 } else {
1756 assert(right->is_register(), "right should be in register");
1757
1758 if (dest->is_single_cpu()) {
1759 switch (code) {
1760 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1761 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1762 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1763 default: ShouldNotReachHere();
1764 }
1765 } else {
1766 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1767 left->as_register_lo();
1768 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1769 right->as_register_lo();
1770
1771 switch (code) {
1772 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1773 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1774 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1775 default: ShouldNotReachHere();
1776 }
1777 }
1778 }
1779 }
1780
1781
1782 int LIR_Assembler::shift_amount(BasicType t) {
1783 int elem_size = type2aelembytes(t);
1784 switch (elem_size) {
1785 case 1 : return 0;
1786 case 2 : return 1;
1787 case 4 : return 2;
1788 case 8 : return 3;
1789 }
1790 ShouldNotReachHere();
1791 return -1;
1792 }
1793
1794
1795 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1796 info->add_register_oop(exceptionOop);
1797
1798 // Reuse the debug info from the safepoint poll for the throw op itself.
1799 address pc_for_athrow = __ pc();
1800 int pc_for_athrow_offset = __ offset();
1801 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1802 //__ relocate(rspec);
1803 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1804 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1805 add_call_info(pc_for_athrow_offset, info); // for exception handler
1806
1807 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? C1StubId::handle_exception_id
1808 : C1StubId::handle_exception_nofpu_id);
1809 //__ load_const_optimized(R0, stub);
1810 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1811 __ mtctr(R0);
1812 __ bctr();
1813 }
1814
1815
1816 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1817 // Note: Not used with EnableDebuggingOnDemand.
1818 assert(exceptionOop->as_register() == R3, "should match");
1819 __ b(_unwind_handler_entry);
1820 }
1821
1822
1823 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1824 Register src = op->src()->as_register();
1825 Register dst = op->dst()->as_register();
1826 Register src_pos = op->src_pos()->as_register();
1827 Register dst_pos = op->dst_pos()->as_register();
1828 Register length = op->length()->as_register();
1829 Register tmp = op->tmp()->as_register();
1830 Register tmp2 = R0;
1831
1832 int flags = op->flags();
1833 ciArrayKlass* default_type = op->expected_type();
1834 BasicType basic_type = (default_type != nullptr) ? default_type->element_type()->basic_type() : T_ILLEGAL;
1835 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1836
1837 // Set up the arraycopy stub information.
1838 ArrayCopyStub* stub = op->stub();
1839
1840 // Always do stub if no type information is available. It's ok if
1841 // the known type isn't loaded since the code sanity checks
1842 // in debug mode and the type isn't required when we know the exact type
1843 // also check that the type is an array type.
1844 if (default_type == nullptr) {
1845 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1846 length->is_nonvolatile(), "must preserve");
1847 address copyfunc_addr = StubRoutines::generic_arraycopy();
1848 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
1849
1850 // 3 parms are int. Convert to long.
1851 __ mr(R3_ARG1, src);
1852 __ extsw(R4_ARG2, src_pos);
1853 __ mr(R5_ARG3, dst);
1854 __ extsw(R6_ARG4, dst_pos);
1855 __ extsw(R7_ARG5, length);
1856
1857 #ifndef PRODUCT
1858 if (PrintC1Statistics) {
1859 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1860 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1861 __ lwz(R11_scratch1, simm16_offs, tmp);
1862 __ addi(R11_scratch1, R11_scratch1, 1);
1863 __ stw(R11_scratch1, simm16_offs, tmp);
1864 }
1865 #endif
1866 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
1867
1868 __ nand(tmp, R3_RET, R3_RET);
1869 __ subf(length, tmp, length);
1870 __ add(src_pos, tmp, src_pos);
1871 __ add(dst_pos, tmp, dst_pos);
1872
1873 __ cmpwi(CCR0, R3_RET, 0);
1874 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1875 __ bind(*stub->continuation());
1876 return;
1877 }
1878
1879 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
1880 Label cont, slow, copyfunc;
1881
1882 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1883 LIR_OpArrayCopy::dst_null_check |
1884 LIR_OpArrayCopy::src_pos_positive_check |
1885 LIR_OpArrayCopy::dst_pos_positive_check |
1886 LIR_OpArrayCopy::length_positive_check);
1887
1888 // Use only one conditional branch for simple checks.
1889 if (simple_check_flag_set) {
1890 ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1891
1892 // Make sure src and dst are non-null.
1893 if (flags & LIR_OpArrayCopy::src_null_check) {
1894 __ cmpdi(combined_check, src, 0);
1895 tmp_check = CCR0;
1896 }
1897
1898 if (flags & LIR_OpArrayCopy::dst_null_check) {
1899 __ cmpdi(tmp_check, dst, 0);
1900 if (tmp_check != combined_check) {
1901 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1902 }
1903 tmp_check = CCR0;
1904 }
1905
1906 // Clear combined_check.eq if not already used.
1907 if (tmp_check == combined_check) {
1908 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1909 tmp_check = CCR0;
1910 }
1911
1912 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1913 // Test src_pos register.
1914 __ cmpwi(tmp_check, src_pos, 0);
1915 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1916 }
1917
1918 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1919 // Test dst_pos register.
1920 __ cmpwi(tmp_check, dst_pos, 0);
1921 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1922 }
1923
1924 if (flags & LIR_OpArrayCopy::length_positive_check) {
1925 // Make sure length isn't negative.
1926 __ cmpwi(tmp_check, length, 0);
1927 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1928 }
1929
1930 __ beq(combined_check, slow);
1931 }
1932
1933 // If the compiler was not able to prove that exact type of the source or the destination
1934 // of the arraycopy is an array type, check at runtime if the source or the destination is
1935 // an instance type.
1936 if (flags & LIR_OpArrayCopy::type_check) {
1937 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1938 __ load_klass(tmp, dst);
1939 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1940 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1941 __ bge(CCR0, slow);
1942 }
1943
1944 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1945 __ load_klass(tmp, src);
1946 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1947 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1948 __ bge(CCR0, slow);
1949 }
1950 }
1951
1952 // Higher 32bits must be null.
1953 __ extsw(length, length);
1954
1955 __ extsw(src_pos, src_pos);
1956 if (flags & LIR_OpArrayCopy::src_range_check) {
1957 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1958 __ add(tmp, length, src_pos);
1959 __ cmpld(CCR0, tmp2, tmp);
1960 __ ble(CCR0, slow);
1961 }
1962
1963 __ extsw(dst_pos, dst_pos);
1964 if (flags & LIR_OpArrayCopy::dst_range_check) {
1965 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1966 __ add(tmp, length, dst_pos);
1967 __ cmpld(CCR0, tmp2, tmp);
1968 __ ble(CCR0, slow);
1969 }
1970
1971 int shift = shift_amount(basic_type);
1972
1973 if (!(flags & LIR_OpArrayCopy::type_check)) {
1974 if (stub != nullptr) {
1975 __ b(cont);
1976 __ bind(slow);
1977 __ b(*stub->entry());
1978 }
1979 } else {
1980 // We don't know the array types are compatible.
1981 if (basic_type != T_OBJECT) {
1982 // Simple test for basic type arrays.
1983 if (UseCompressedClassPointers) {
1984 // We don't need decode because we just need to compare.
1985 __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
1986 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1987 __ cmpw(CCR0, tmp, tmp2);
1988 } else {
1989 __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
1990 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1991 __ cmpd(CCR0, tmp, tmp2);
1992 }
1993 __ beq(CCR0, cont);
1994 } else {
1995 // For object arrays, if src is a sub class of dst then we can
1996 // safely do the copy.
1997 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1998
1999 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
2000 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
2001
2002 __ load_klass(sub_klass, src);
2003 __ load_klass(super_klass, dst);
2004
2005 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
2006 &cont, copyfunc_addr != nullptr ? ©func : &slow, nullptr);
2007
2008 address slow_stc = Runtime1::entry_for(C1StubId::slow_subtype_check_id);
2009 //__ load_const_optimized(tmp, slow_stc, tmp2);
2010 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2011 __ mtctr(tmp);
2012 __ bctrl(); // sets CR0
2013 __ beq(CCR0, cont);
2014
2015 if (copyfunc_addr != nullptr) { // Use stub if available.
2016 __ bind(copyfunc);
2017 // Src is not a sub class of dst so we have to do a
2018 // per-element check.
2019 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2020 if ((flags & mask) != mask) {
2021 assert(flags & mask, "one of the two should be known to be an object array");
2022
2023 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2024 __ load_klass(tmp, src);
2025 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2026 __ load_klass(tmp, dst);
2027 }
2028
2029 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2030
2031 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2032 __ load_const_optimized(tmp, objArray_lh);
2033 __ cmpw(CCR0, tmp, tmp2);
2034 __ bne(CCR0, slow);
2035 }
2036
2037 Register src_ptr = R3_ARG1;
2038 Register dst_ptr = R4_ARG2;
2039 Register len = R5_ARG3;
2040 Register chk_off = R6_ARG4;
2041 Register super_k = R7_ARG5;
2042
2043 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2044 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2045 if (shift == 0) {
2046 __ add(src_ptr, src_pos, src_ptr);
2047 __ add(dst_ptr, dst_pos, dst_ptr);
2048 } else {
2049 __ sldi(tmp, src_pos, shift);
2050 __ sldi(tmp2, dst_pos, shift);
2051 __ add(src_ptr, tmp, src_ptr);
2052 __ add(dst_ptr, tmp2, dst_ptr);
2053 }
2054
2055 __ load_klass(tmp, dst);
2056 __ mr(len, length);
2057
2058 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2059 __ ld(super_k, ek_offset, tmp);
2060
2061 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2062 __ lwz(chk_off, sco_offset, super_k);
2063
2064 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
2065
2066 #ifndef PRODUCT
2067 if (PrintC1Statistics) {
2068 Label failed;
2069 __ cmpwi(CCR0, R3_RET, 0);
2070 __ bne(CCR0, failed);
2071 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2072 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2073 __ lwz(R11_scratch1, simm16_offs, tmp);
2074 __ addi(R11_scratch1, R11_scratch1, 1);
2075 __ stw(R11_scratch1, simm16_offs, tmp);
2076 __ bind(failed);
2077 }
2078 #endif
2079
2080 __ nand(tmp, R3_RET, R3_RET);
2081 __ cmpwi(CCR0, R3_RET, 0);
2082 __ beq(CCR0, *stub->continuation());
2083
2084 #ifndef PRODUCT
2085 if (PrintC1Statistics) {
2086 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2087 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2088 __ lwz(R11_scratch1, simm16_offs, tmp);
2089 __ addi(R11_scratch1, R11_scratch1, 1);
2090 __ stw(R11_scratch1, simm16_offs, tmp);
2091 }
2092 #endif
2093
2094 __ subf(length, tmp, length);
2095 __ add(src_pos, tmp, src_pos);
2096 __ add(dst_pos, tmp, dst_pos);
2097 }
2098 }
2099 __ bind(slow);
2100 __ b(*stub->entry());
2101 }
2102 __ bind(cont);
2103
2104 #ifdef ASSERT
2105 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2106 // Sanity check the known type with the incoming class. For the
2107 // primitive case the types must match exactly with src.klass and
2108 // dst.klass each exactly matching the default type. For the
2109 // object array case, if no type check is needed then either the
2110 // dst type is exactly the expected type and the src type is a
2111 // subtype which we can't check or src is the same array as dst
2112 // but not necessarily exactly of type default_type.
2113 Label known_ok, halt;
2114 metadata2reg(default_type->constant_encoding(), tmp);
2115 if (UseCompressedClassPointers) {
2116 // Tmp holds the default type. It currently comes uncompressed after the
2117 // load of a constant, so encode it.
2118 __ encode_klass_not_null(tmp);
2119 // Load the raw value of the dst klass, since we will be comparing
2120 // uncompressed values directly.
2121 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2122 __ cmpw(CCR0, tmp, tmp2);
2123 if (basic_type != T_OBJECT) {
2124 __ bne(CCR0, halt);
2125 // Load the raw value of the src klass.
2126 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2127 __ cmpw(CCR0, tmp, tmp2);
2128 __ beq(CCR0, known_ok);
2129 } else {
2130 __ beq(CCR0, known_ok);
2131 __ cmpw(CCR0, src, dst);
2132 __ beq(CCR0, known_ok);
2133 }
2134 } else {
2135 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2136 __ cmpd(CCR0, tmp, tmp2);
2137 if (basic_type != T_OBJECT) {
2138 __ bne(CCR0, halt);
2139 // Load the raw value of the src klass.
2140 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2141 __ cmpd(CCR0, tmp, tmp2);
2142 __ beq(CCR0, known_ok);
2143 } else {
2144 __ beq(CCR0, known_ok);
2145 __ cmpd(CCR0, src, dst);
2146 __ beq(CCR0, known_ok);
2147 }
2148 }
2149 __ bind(halt);
2150 __ stop("incorrect type information in arraycopy");
2151 __ bind(known_ok);
2152 }
2153 #endif
2154
2155 #ifndef PRODUCT
2156 if (PrintC1Statistics) {
2157 address counter = Runtime1::arraycopy_count_address(basic_type);
2158 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2159 __ lwz(R11_scratch1, simm16_offs, tmp);
2160 __ addi(R11_scratch1, R11_scratch1, 1);
2161 __ stw(R11_scratch1, simm16_offs, tmp);
2162 }
2163 #endif
2164
2165 Register src_ptr = R3_ARG1;
2166 Register dst_ptr = R4_ARG2;
2167 Register len = R5_ARG3;
2168
2169 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2170 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2171 if (shift == 0) {
2172 __ add(src_ptr, src_pos, src_ptr);
2173 __ add(dst_ptr, dst_pos, dst_ptr);
2174 } else {
2175 __ sldi(tmp, src_pos, shift);
2176 __ sldi(tmp2, dst_pos, shift);
2177 __ add(src_ptr, tmp, src_ptr);
2178 __ add(dst_ptr, tmp2, dst_ptr);
2179 }
2180
2181 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2182 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2183 const char *name;
2184 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2185
2186 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2187 __ mr(len, length);
2188 __ call_c(entry, relocInfo::runtime_call_type);
2189
2190 if (stub != nullptr) {
2191 __ bind(*stub->continuation());
2192 }
2193 }
2194
2195
2196 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2197 if (dest->is_single_cpu()) {
2198 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2199 #ifdef _LP64
2200 if (left->type() == T_OBJECT) {
2201 switch (code) {
2202 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2203 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2204 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2205 default: ShouldNotReachHere();
2206 }
2207 } else
2208 #endif
2209 switch (code) {
2210 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2211 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2212 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2213 default: ShouldNotReachHere();
2214 }
2215 } else {
2216 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2217 switch (code) {
2218 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2219 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2220 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2221 default: ShouldNotReachHere();
2222 }
2223 }
2224 }
2225
2226
2227 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2228 #ifdef _LP64
2229 if (left->type() == T_OBJECT) {
2230 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2231 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2232 else {
2233 switch (code) {
2234 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2235 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2236 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2237 default: ShouldNotReachHere();
2238 }
2239 }
2240 return;
2241 }
2242 #endif
2243
2244 if (dest->is_single_cpu()) {
2245 count = count & 0x1F; // Java spec
2246 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2247 else {
2248 switch (code) {
2249 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2250 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2251 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2252 default: ShouldNotReachHere();
2253 }
2254 }
2255 } else if (dest->is_double_cpu()) {
2256 count = count & 63; // Java spec
2257 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2258 else {
2259 switch (code) {
2260 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2261 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2262 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2263 default: ShouldNotReachHere();
2264 }
2265 }
2266 } else {
2267 ShouldNotReachHere();
2268 }
2269 }
2270
2271
2272 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2273 if (op->init_check()) {
2274 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2275 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2276 } else {
2277 add_debug_info_for_null_check_here(op->stub()->info());
2278 }
2279 __ lbz(op->tmp1()->as_register(),
2280 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2281 // acquire barrier included in membar_storestore() which follows the allocation immediately.
2282 __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2283 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2284 }
2285 __ allocate_object(op->obj()->as_register(),
2286 op->tmp1()->as_register(),
2287 op->tmp2()->as_register(),
2288 op->tmp3()->as_register(),
2289 op->header_size(),
2290 op->object_size(),
2291 op->klass()->as_register(),
2292 *op->stub()->entry());
2293
2294 __ bind(*op->stub()->continuation());
2295 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2296 }
2297
2298
2299 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2300 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2301 if (UseSlowPath ||
2302 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2303 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2304 __ b(*op->stub()->entry());
2305 } else {
2306 __ allocate_array(op->obj()->as_register(),
2307 op->len()->as_register(),
2308 op->tmp1()->as_register(),
2309 op->tmp2()->as_register(),
2310 op->tmp3()->as_register(),
2311 arrayOopDesc::base_offset_in_bytes(op->type()),
2312 type2aelembytes(op->type()),
2313 op->klass()->as_register(),
2314 *op->stub()->entry(),
2315 op->zero_array());
2316 }
2317 __ bind(*op->stub()->continuation());
2318 }
2319
2320
2321 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2322 ciMethodData *md, ciProfileData *data,
2323 Register recv, Register tmp1, Label* update_done) {
2324 uint i;
2325 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2326 Label next_test;
2327 // See if the receiver is receiver[n].
2328 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2329 __ verify_klass_ptr(tmp1);
2330 __ cmpd(CCR0, recv, tmp1);
2331 __ bne(CCR0, next_test);
2332
2333 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2334 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2335 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2336 __ b(*update_done);
2337
2338 __ bind(next_test);
2339 }
2340
2341 // Didn't find receiver; find next empty slot and fill it in.
2342 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2343 Label next_test;
2344 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2345 __ cmpdi(CCR0, tmp1, 0);
2346 __ bne(CCR0, next_test);
2347 __ li(tmp1, DataLayout::counter_increment);
2348 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2349 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2350 __ b(*update_done);
2351
2352 __ bind(next_test);
2353 }
2354 }
2355
2356
2357 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2358 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2359 md = method->method_data_or_null();
2360 assert(md != nullptr, "Sanity");
2361 data = md->bci_to_data(bci);
2362 assert(data != nullptr, "need data for checkcast");
2363 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2364 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2365 // The offset is large so bias the mdo by the base of the slot so
2366 // that the ld can use simm16s to reference the slots of the data.
2367 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2368 }
2369 }
2370
2371
2372 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2373 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2374 Register k_RInfo = op->tmp1()->as_register();
2375 Register klass_RInfo = op->tmp2()->as_register();
2376 Register Rtmp1 = op->tmp3()->as_register();
2377 Register dst = op->result_opr()->as_register();
2378 ciKlass* k = op->klass();
2379 bool should_profile = op->should_profile();
2380 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2381 bool reg_conflict = false;
2382 if (obj == k_RInfo) {
2383 k_RInfo = dst;
2384 reg_conflict = true;
2385 } else if (obj == klass_RInfo) {
2386 klass_RInfo = dst;
2387 reg_conflict = true;
2388 } else if (obj == Rtmp1) {
2389 Rtmp1 = dst;
2390 reg_conflict = true;
2391 }
2392 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2393
2394 ciMethodData* md = nullptr;
2395 ciProfileData* data = nullptr;
2396 int mdo_offset_bias = 0;
2397 if (should_profile) {
2398 ciMethod* method = op->profiled_method();
2399 assert(method != nullptr, "Should have method");
2400 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2401
2402 Register mdo = k_RInfo;
2403 Register data_val = Rtmp1;
2404 Label not_null;
2405 metadata2reg(md->constant_encoding(), mdo);
2406 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2407 __ cmpdi(CCR0, obj, 0);
2408 __ bne(CCR0, not_null);
2409 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2410 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2411 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2412 __ b(*obj_is_null);
2413 __ bind(not_null);
2414
2415 Label update_done;
2416 Register recv = klass_RInfo;
2417 __ load_klass(recv, obj);
2418 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2419 const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2420 __ ld(Rtmp1, slot_offset, mdo);
2421 __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2422 __ std(Rtmp1, slot_offset, mdo);
2423 __ bind(update_done);
2424 } else {
2425 __ cmpdi(CCR0, obj, 0);
2426 __ beq(CCR0, *obj_is_null);
2427 }
2428
2429 // get object class
2430 __ load_klass(klass_RInfo, obj);
2431
2432 if (k->is_loaded()) {
2433 metadata2reg(k->constant_encoding(), k_RInfo);
2434 } else {
2435 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2436 }
2437
2438 if (op->fast_check()) {
2439 assert_different_registers(klass_RInfo, k_RInfo);
2440 __ cmpd(CCR0, k_RInfo, klass_RInfo);
2441 __ beq(CCR0, *success);
2442 // Fall through to failure case.
2443 } else {
2444 bool need_slow_path = true;
2445 if (k->is_loaded()) {
2446 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2447 need_slow_path = false;
2448 }
2449 // Perform the fast part of the checking logic.
2450 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success : nullptr),
2451 failure, nullptr, RegisterOrConstant(k->super_check_offset()));
2452 } else {
2453 // Perform the fast part of the checking logic.
2454 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success, failure);
2455 }
2456 if (!need_slow_path) {
2457 __ b(*success);
2458 } else {
2459 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2460 address entry = Runtime1::entry_for(C1StubId::slow_subtype_check_id);
2461 // Stub needs fixed registers (tmp1-3).
2462 Register original_k_RInfo = op->tmp1()->as_register();
2463 Register original_klass_RInfo = op->tmp2()->as_register();
2464 Register original_Rtmp1 = op->tmp3()->as_register();
2465 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2466 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2467 __ mr_if_needed(original_k_RInfo, k_RInfo);
2468 __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2469 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2470 //__ load_const_optimized(original_Rtmp1, entry, R0);
2471 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2472 __ mtctr(original_Rtmp1);
2473 __ bctrl(); // sets CR0
2474 if (keep_obj_alive) { __ mr(obj, dst); }
2475 __ beq(CCR0, *success);
2476 // Fall through to failure case.
2477 }
2478 }
2479
2480 __ bind(*failure);
2481 }
2482
2483
2484 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2485 LIR_Code code = op->code();
2486 if (code == lir_store_check) {
2487 Register value = op->object()->as_register();
2488 Register array = op->array()->as_register();
2489 Register k_RInfo = op->tmp1()->as_register();
2490 Register klass_RInfo = op->tmp2()->as_register();
2491 Register Rtmp1 = op->tmp3()->as_register();
2492 bool should_profile = op->should_profile();
2493
2494 __ verify_oop(value, FILE_AND_LINE);
2495 CodeStub* stub = op->stub();
2496 // Check if it needs to be profiled.
2497 ciMethodData* md = nullptr;
2498 ciProfileData* data = nullptr;
2499 int mdo_offset_bias = 0;
2500 if (should_profile) {
2501 ciMethod* method = op->profiled_method();
2502 assert(method != nullptr, "Should have method");
2503 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2504 }
2505
2506 Label done;
2507
2508 if (should_profile) {
2509 Label not_null;
2510 Register mdo = k_RInfo;
2511 Register data_val = Rtmp1;
2512 metadata2reg(md->constant_encoding(), mdo);
2513 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2514 __ cmpdi(CCR0, value, 0);
2515 __ bne(CCR0, not_null);
2516 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2517 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2518 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2519 __ b(done);
2520 __ bind(not_null);
2521
2522 Label update_done;
2523 Register recv = klass_RInfo;
2524 __ load_klass(recv, value);
2525 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2526 const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2527 __ ld(Rtmp1, slot_offset, mdo);
2528 __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2529 __ std(Rtmp1, slot_offset, mdo);
2530 __ bind(update_done);
2531 } else {
2532 __ cmpdi(CCR0, value, 0);
2533 __ beq(CCR0, done);
2534 }
2535 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2536 explicit_null_check(array, op->info_for_exception());
2537 } else {
2538 add_debug_info_for_null_check_here(op->info_for_exception());
2539 }
2540 __ load_klass(k_RInfo, array);
2541 __ load_klass(klass_RInfo, value);
2542
2543 Label failure;
2544
2545 // Get instance klass.
2546 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2547 // Perform the fast part of the checking logic.
2548 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, &done, &failure, nullptr);
2549
2550 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2551 const address slow_path = Runtime1::entry_for(C1StubId::slow_subtype_check_id);
2552 //__ load_const_optimized(R0, slow_path);
2553 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2554 __ mtctr(R0);
2555 __ bctrl(); // sets CR0
2556 __ beq(CCR0, done);
2557
2558 __ bind(failure);
2559 __ b(*stub->entry());
2560 __ align(32, 12);
2561 __ bind(done);
2562
2563 } else if (code == lir_checkcast) {
2564 Label success, failure;
2565 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2566 __ b(*op->stub()->entry());
2567 __ align(32, 12);
2568 __ bind(success);
2569 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2570 } else if (code == lir_instanceof) {
2571 Register dst = op->result_opr()->as_register();
2572 Label success, failure, done;
2573 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2574 __ li(dst, 0);
2575 __ b(done);
2576 __ align(32, 12);
2577 __ bind(success);
2578 __ li(dst, 1);
2579 __ bind(done);
2580 } else {
2581 ShouldNotReachHere();
2582 }
2583 }
2584
2585
2586 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2587 Register addr = op->addr()->as_pointer_register();
2588 Register cmp_value = noreg, new_value = noreg;
2589 bool is_64bit = false;
2590
2591 if (op->code() == lir_cas_long) {
2592 cmp_value = op->cmp_value()->as_register_lo();
2593 new_value = op->new_value()->as_register_lo();
2594 is_64bit = true;
2595 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2596 cmp_value = op->cmp_value()->as_register();
2597 new_value = op->new_value()->as_register();
2598 if (op->code() == lir_cas_obj) {
2599 if (UseCompressedOops) {
2600 Register t1 = op->tmp1()->as_register();
2601 Register t2 = op->tmp2()->as_register();
2602 cmp_value = __ encode_heap_oop(t1, cmp_value);
2603 new_value = __ encode_heap_oop(t2, new_value);
2604 } else {
2605 is_64bit = true;
2606 }
2607 }
2608 } else {
2609 Unimplemented();
2610 }
2611
2612 // There might be a volatile load before this Unsafe CAS.
2613 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2614 __ sync();
2615 } else {
2616 __ lwsync();
2617 }
2618
2619 if (is_64bit) {
2620 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2621 MacroAssembler::MemBarNone,
2622 MacroAssembler::cmpxchgx_hint_atomic_update(),
2623 noreg, nullptr, /*check without ldarx first*/true);
2624 } else {
2625 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2626 MacroAssembler::MemBarNone,
2627 MacroAssembler::cmpxchgx_hint_atomic_update(),
2628 noreg, nullptr, /*check without ldarx first*/true);
2629 }
2630
2631 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2632 __ isync();
2633 } else {
2634 __ sync();
2635 }
2636 }
2637
2638 void LIR_Assembler::breakpoint() {
2639 __ illtrap();
2640 }
2641
2642
2643 void LIR_Assembler::push(LIR_Opr opr) {
2644 Unimplemented();
2645 }
2646
2647 void LIR_Assembler::pop(LIR_Opr opr) {
2648 Unimplemented();
2649 }
2650
2651
2652 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2653 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2654 Register dst = dst_opr->as_register();
2655 Register reg = mon_addr.base();
2656 int offset = mon_addr.disp();
2657 // Compute pointer to BasicLock.
2658 __ add_const_optimized(dst, reg, offset);
2659 }
2660
2661
2662 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2663 Register obj = op->obj_opr()->as_register();
2664 Register hdr = op->hdr_opr()->as_register();
2665 Register lock = op->lock_opr()->as_register();
2666
2667 // Obj may not be an oop.
2668 if (op->code() == lir_lock) {
2669 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2670 if (LockingMode != LM_MONITOR) {
2671 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2672 // Add debug info for NullPointerException only if one is possible.
2673 if (op->info() != nullptr) {
2674 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2675 explicit_null_check(obj, op->info());
2676 } else {
2677 add_debug_info_for_null_check_here(op->info());
2678 }
2679 }
2680 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2681 } else {
2682 // always do slow locking
2683 // note: The slow locking code could be inlined here, however if we use
2684 // slow locking, speed doesn't matter anyway and this solution is
2685 // simpler and requires less duplicated code - additionally, the
2686 // slow locking code is the same in either case which simplifies
2687 // debugging.
2688 if (op->info() != nullptr) {
2689 add_debug_info_for_null_check_here(op->info());
2690 __ null_check(obj);
2691 }
2692 __ b(*op->stub()->entry());
2693 }
2694 } else {
2695 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2696 if (LockingMode != LM_MONITOR) {
2697 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2698 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2699 } else {
2700 // always do slow unlocking
2701 // note: The slow unlocking code could be inlined here, however if we use
2702 // slow unlocking, speed doesn't matter anyway and this solution is
2703 // simpler and requires less duplicated code - additionally, the
2704 // slow unlocking code is the same in either case which simplifies
2705 // debugging.
2706 __ b(*op->stub()->entry());
2707 }
2708 }
2709 __ bind(*op->stub()->continuation());
2710 }
2711
2712 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2713 Register obj = op->obj()->as_pointer_register();
2714 Register result = op->result_opr()->as_pointer_register();
2715
2716 CodeEmitInfo* info = op->info();
2717 if (info != nullptr) {
2718 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2719 explicit_null_check(obj, info);
2720 } else {
2721 add_debug_info_for_null_check_here(info);
2722 }
2723 }
2724
2725 if (UseCompressedClassPointers) {
2726 __ lwz(result, oopDesc::klass_offset_in_bytes(), obj);
2727 __ decode_klass_not_null(result);
2728 } else {
2729 __ ld(result, oopDesc::klass_offset_in_bytes(), obj);
2730 }
2731 }
2732
2733 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2734 ciMethod* method = op->profiled_method();
2735 int bci = op->profiled_bci();
2736 ciMethod* callee = op->profiled_callee();
2737
2738 // Update counter for all call types.
2739 ciMethodData* md = method->method_data_or_null();
2740 assert(md != nullptr, "Sanity");
2741 ciProfileData* data = md->bci_to_data(bci);
2742 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2743 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2744 Register mdo = op->mdo()->as_register();
2745 #ifdef _LP64
2746 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2747 Register tmp1 = op->tmp1()->as_register_lo();
2748 #else
2749 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2750 Register tmp1 = op->tmp1()->as_register();
2751 #endif
2752 metadata2reg(md->constant_encoding(), mdo);
2753 int mdo_offset_bias = 0;
2754 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2755 data->size_in_bytes())) {
2756 // The offset is large so bias the mdo by the base of the slot so
2757 // that the ld can use simm16s to reference the slots of the data.
2758 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2759 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2760 }
2761
2762 // Perform additional virtual call profiling for invokevirtual and
2763 // invokeinterface bytecodes
2764 if (op->should_profile_receiver_type()) {
2765 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2766 Register recv = op->recv()->as_register();
2767 assert_different_registers(mdo, tmp1, recv);
2768 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2769 ciKlass* known_klass = op->known_holder();
2770 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2771 // We know the type that will be seen at this call site; we can
2772 // statically update the MethodData* rather than needing to do
2773 // dynamic tests on the receiver type.
2774
2775 // NOTE: we should probably put a lock around this search to
2776 // avoid collisions by concurrent compilations.
2777 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2778 uint i;
2779 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2780 ciKlass* receiver = vc_data->receiver(i);
2781 if (known_klass->equals(receiver)) {
2782 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2783 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2784 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2785 return;
2786 }
2787 }
2788
2789 // Receiver type not found in profile data; select an empty slot.
2790
2791 // Note that this is less efficient than it should be because it
2792 // always does a write to the receiver part of the
2793 // VirtualCallData rather than just the first time.
2794 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2795 ciKlass* receiver = vc_data->receiver(i);
2796 if (receiver == nullptr) {
2797 metadata2reg(known_klass->constant_encoding(), tmp1);
2798 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2799
2800 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2801 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2802 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2803 return;
2804 }
2805 }
2806 } else {
2807 __ load_klass(recv, recv);
2808 Label update_done;
2809 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2810 // Receiver did not match any saved receiver and there is no empty row for it.
2811 // Increment total counter to indicate polymorphic case.
2812 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2813 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2814 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2815
2816 __ bind(update_done);
2817 }
2818 } else {
2819 // Static call
2820 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2821 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2822 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2823 }
2824 }
2825
2826
2827 void LIR_Assembler::align_backward_branch_target() {
2828 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2829 }
2830
2831
2832 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2833 Unimplemented();
2834 }
2835
2836
2837 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2838 // tmp must be unused
2839 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2840 assert(left->is_register(), "can only handle registers");
2841
2842 if (left->is_single_cpu()) {
2843 __ neg(dest->as_register(), left->as_register());
2844 } else if (left->is_single_fpu()) {
2845 __ fneg(dest->as_float_reg(), left->as_float_reg());
2846 } else if (left->is_double_fpu()) {
2847 __ fneg(dest->as_double_reg(), left->as_double_reg());
2848 } else {
2849 assert (left->is_double_cpu(), "Must be a long");
2850 __ neg(dest->as_register_lo(), left->as_register_lo());
2851 }
2852 }
2853
2854
2855 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2856 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2857 // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2858 if (dest == Runtime1::entry_for(C1StubId::register_finalizer_id) ||
2859 dest == Runtime1::entry_for(C1StubId::new_multi_array_id )) {
2860 //__ load_const_optimized(R0, dest);
2861 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2862 __ mtctr(R0);
2863 __ bctrl();
2864 assert(info != nullptr, "sanity");
2865 add_call_info_here(info);
2866 __ post_call_nop();
2867 return;
2868 }
2869
2870 __ call_c(dest, relocInfo::runtime_call_type);
2871 if (info != nullptr) {
2872 add_call_info_here(info);
2873 }
2874 assert(__ last_calls_return_pc() == __ pc(), "pcn not at return pc");
2875 __ post_call_nop();
2876 }
2877
2878
2879 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2880 ShouldNotReachHere(); // Not needed on _LP64.
2881 }
2882
2883 void LIR_Assembler::membar() {
2884 __ fence();
2885 }
2886
2887 void LIR_Assembler::membar_acquire() {
2888 __ acquire();
2889 }
2890
2891 void LIR_Assembler::membar_release() {
2892 __ release();
2893 }
2894
2895 void LIR_Assembler::membar_loadload() {
2896 __ membar(Assembler::LoadLoad);
2897 }
2898
2899 void LIR_Assembler::membar_storestore() {
2900 __ membar(Assembler::StoreStore);
2901 }
2902
2903 void LIR_Assembler::membar_loadstore() {
2904 __ membar(Assembler::LoadStore);
2905 }
2906
2907 void LIR_Assembler::membar_storeload() {
2908 __ membar(Assembler::StoreLoad);
2909 }
2910
2911 void LIR_Assembler::on_spin_wait() {
2912 Unimplemented();
2913 }
2914
2915 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2916 LIR_Address* addr = addr_opr->as_address_ptr();
2917 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2918
2919 if (addr->index()->is_illegal()) {
2920 if (patch_code != lir_patch_none) {
2921 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2922 __ load_const32(R0, 0); // patchable int
2923 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2924 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2925 } else {
2926 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2927 }
2928 } else {
2929 assert(patch_code == lir_patch_none, "Patch code not supported");
2930 assert(addr->disp() == 0, "can't have both: index and disp");
2931 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2932 }
2933 }
2934
2935
2936 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2937 ShouldNotReachHere();
2938 }
2939
2940
2941 #ifdef ASSERT
2942 // Emit run-time assertion.
2943 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2944 Unimplemented();
2945 }
2946 #endif
2947
2948
2949 void LIR_Assembler::peephole(LIR_List* lir) {
2950 // Optimize instruction pairs before emitting.
2951 LIR_OpList* inst = lir->instructions_list();
2952 for (int i = 1; i < inst->length(); i++) {
2953 LIR_Op* op = inst->at(i);
2954
2955 // 2 register-register-moves
2956 if (op->code() == lir_move) {
2957 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2958 res2 = ((LIR_Op1*)op)->result_opr();
2959 if (in2->is_register() && res2->is_register()) {
2960 LIR_Op* prev = inst->at(i - 1);
2961 if (prev && prev->code() == lir_move) {
2962 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2963 res1 = ((LIR_Op1*)prev)->result_opr();
2964 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2965 inst->remove_at(i);
2966 }
2967 }
2968 }
2969 }
2970
2971 }
2972 return;
2973 }
2974
2975
2976 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2977 const LIR_Address *addr = src->as_address_ptr();
2978 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2979 const Register Rptr = addr->base()->as_pointer_register(),
2980 Rtmp = tmp->as_register();
2981 Register Robj = noreg;
2982 if (data->is_oop()) {
2983 if (UseCompressedOops) {
2984 Robj = __ encode_heap_oop(Rtmp, data->as_register());
2985 } else {
2986 Robj = data->as_register();
2987 if (Robj == dest->as_register()) { // May happen with ZGC.
2988 __ mr(Rtmp, Robj);
2989 Robj = Rtmp;
2990 }
2991 }
2992 }
2993
2994 // There might be a volatile load before this Unsafe OP.
2995 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2996 __ sync();
2997 } else {
2998 __ lwsync();
2999 }
3000
3001 Label Lretry;
3002 __ bind(Lretry);
3003
3004 if (data->type() == T_INT) {
3005 const Register Rold = dest->as_register(),
3006 Rsrc = data->as_register();
3007 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3008 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3009 if (code == lir_xadd) {
3010 __ add(Rtmp, Rsrc, Rold);
3011 __ stwcx_(Rtmp, Rptr);
3012 } else {
3013 __ stwcx_(Rsrc, Rptr);
3014 }
3015 } else if (data->is_oop()) {
3016 assert(code == lir_xchg, "xadd for oops");
3017 const Register Rold = dest->as_register();
3018 assert_different_registers(Rptr, Rold, Robj);
3019 if (UseCompressedOops) {
3020 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3021 __ stwcx_(Robj, Rptr);
3022 } else {
3023 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3024 __ stdcx_(Robj, Rptr);
3025 }
3026 } else if (data->type() == T_LONG) {
3027 const Register Rold = dest->as_register_lo(),
3028 Rsrc = data->as_register_lo();
3029 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3030 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3031 if (code == lir_xadd) {
3032 __ add(Rtmp, Rsrc, Rold);
3033 __ stdcx_(Rtmp, Rptr);
3034 } else {
3035 __ stdcx_(Rsrc, Rptr);
3036 }
3037 } else {
3038 ShouldNotReachHere();
3039 }
3040
3041 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3042 __ bne_predict_not_taken(CCR0, Lretry);
3043 } else {
3044 __ bne( CCR0, Lretry);
3045 }
3046
3047 if (UseCompressedOops && data->is_oop()) {
3048 __ decode_heap_oop(dest->as_register());
3049 }
3050
3051 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
3052 __ isync();
3053 } else {
3054 __ sync();
3055 }
3056 }
3057
3058
3059 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3060 Register obj = op->obj()->as_register();
3061 Register tmp = op->tmp()->as_pointer_register();
3062 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3063 ciKlass* exact_klass = op->exact_klass();
3064 intptr_t current_klass = op->current_klass();
3065 bool not_null = op->not_null();
3066 bool no_conflict = op->no_conflict();
3067
3068 Label Lupdate, Ldo_update, Ldone;
3069
3070 bool do_null = !not_null;
3071 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3072 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3073
3074 assert(do_null || do_update, "why are we here?");
3075 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3076
3077 __ verify_oop(obj, FILE_AND_LINE);
3078
3079 if (do_null) {
3080 if (!TypeEntries::was_null_seen(current_klass)) {
3081 __ cmpdi(CCR0, obj, 0);
3082 __ bne(CCR0, Lupdate);
3083 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3084 __ ori(R0, R0, TypeEntries::null_seen);
3085 if (do_update) {
3086 __ b(Ldo_update);
3087 } else {
3088 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3089 }
3090 } else {
3091 if (do_update) {
3092 __ cmpdi(CCR0, obj, 0);
3093 __ beq(CCR0, Ldone);
3094 }
3095 }
3096 #ifdef ASSERT
3097 } else {
3098 __ cmpdi(CCR0, obj, 0);
3099 __ bne(CCR0, Lupdate);
3100 __ stop("unexpected null obj");
3101 #endif
3102 }
3103
3104 __ bind(Lupdate);
3105 if (do_update) {
3106 Label Lnext;
3107 const Register klass = R29_TOC; // kill and reload
3108 bool klass_reg_used = false;
3109 #ifdef ASSERT
3110 if (exact_klass != nullptr) {
3111 Label ok;
3112 klass_reg_used = true;
3113 __ load_klass(klass, obj);
3114 metadata2reg(exact_klass->constant_encoding(), R0);
3115 __ cmpd(CCR0, klass, R0);
3116 __ beq(CCR0, ok);
3117 __ stop("exact klass and actual klass differ");
3118 __ bind(ok);
3119 }
3120 #endif
3121
3122 if (!no_conflict) {
3123 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3124 klass_reg_used = true;
3125 if (exact_klass != nullptr) {
3126 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3127 metadata2reg(exact_klass->constant_encoding(), klass);
3128 } else {
3129 __ load_klass(klass, obj);
3130 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3131 }
3132
3133 // Like InterpreterMacroAssembler::profile_obj_type
3134 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3135 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3136 __ cmpd(CCR1, R0, klass);
3137 // Klass seen before, nothing to do (regardless of unknown bit).
3138 //beq(CCR1, do_nothing);
3139
3140 __ andi_(R0, tmp, TypeEntries::type_unknown);
3141 // Already unknown. Nothing to do anymore.
3142 //bne(CCR0, do_nothing);
3143 __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3144 __ beq(CCR0, Lnext);
3145
3146 if (TypeEntries::is_type_none(current_klass)) {
3147 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3148 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3149 __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3150 }
3151
3152 } else {
3153 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3154 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3155
3156 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3157 __ andi_(R0, tmp, TypeEntries::type_unknown);
3158 // Already unknown. Nothing to do anymore.
3159 __ bne(CCR0, Lnext);
3160 }
3161
3162 // Different than before. Cannot keep accurate profile.
3163 __ ori(R0, tmp, TypeEntries::type_unknown);
3164 } else {
3165 // There's a single possible klass at this profile point
3166 assert(exact_klass != nullptr, "should be");
3167 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3168
3169 if (TypeEntries::is_type_none(current_klass)) {
3170 klass_reg_used = true;
3171 metadata2reg(exact_klass->constant_encoding(), klass);
3172
3173 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3174 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3175 __ cmpd(CCR1, R0, klass);
3176 // Klass seen before, nothing to do (regardless of unknown bit).
3177 __ beq(CCR1, Lnext);
3178 #ifdef ASSERT
3179 {
3180 Label ok;
3181 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3182 __ beq(CCR0, ok); // First time here.
3183
3184 __ stop("unexpected profiling mismatch");
3185 __ bind(ok);
3186 }
3187 #endif
3188 // First time here. Set profile type.
3189 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3190 } else {
3191 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3192 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3193
3194 // Already unknown. Nothing to do anymore.
3195 __ andi_(R0, tmp, TypeEntries::type_unknown);
3196 __ bne(CCR0, Lnext);
3197
3198 // Different than before. Cannot keep accurate profile.
3199 __ ori(R0, tmp, TypeEntries::type_unknown);
3200 }
3201 }
3202
3203 __ bind(Ldo_update);
3204 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3205
3206 __ bind(Lnext);
3207 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3208 }
3209 __ bind(Ldone);
3210 }
3211
3212
3213 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3214 assert(op->crc()->is_single_cpu(), "crc must be register");
3215 assert(op->val()->is_single_cpu(), "byte value must be register");
3216 assert(op->result_opr()->is_single_cpu(), "result must be register");
3217 Register crc = op->crc()->as_register();
3218 Register val = op->val()->as_register();
3219 Register res = op->result_opr()->as_register();
3220
3221 assert_different_registers(val, crc, res);
3222
3223 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3224 __ kernel_crc32_singleByteReg(crc, val, res, true);
3225 __ mr(res, crc);
3226 }
3227
3228 #undef __