1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2025 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "memory/universe.hpp"
36 #include "nativeInst_ppc.hpp"
37 #include "oops/compressedOops.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/frame.inline.hpp"
40 #include "runtime/os.inline.hpp"
41 #include "runtime/safepointMechanism.inline.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "runtime/stubRoutines.hpp"
44 #include "runtime/vm_version.hpp"
45 #include "utilities/macros.hpp"
46 #include "utilities/powerOfTwo.hpp"
47
48 #define __ _masm->
49
50
51 const ConditionRegister LIR_Assembler::BOOL_RESULT = CR5;
52
53
54 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
55 Unimplemented(); return false; // Currently not used on this platform.
56 }
57
58
59 LIR_Opr LIR_Assembler::receiverOpr() {
60 return FrameMap::R3_oop_opr;
61 }
62
63
64 LIR_Opr LIR_Assembler::osrBufferPointer() {
65 return FrameMap::R3_opr;
66 }
67
68
69 // This specifies the stack pointer decrement needed to build the frame.
70 int LIR_Assembler::initial_frame_size_in_bytes() const {
71 return in_bytes(frame_map()->framesize_in_bytes());
72 }
73
74
75 // Inline cache check: the inline cached class is in inline_cache_reg;
76 // we fetch the class of the receiver and compare it with the cached class.
77 // If they do not match we jump to slow case.
78 int LIR_Assembler::check_icache() {
79 return __ ic_check(CodeEntryAlignment);
80 }
81
82 void LIR_Assembler::clinit_barrier(ciMethod* method) {
83 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
84
85 Label L_skip_barrier;
86 Register klass = R20;
87
88 metadata2reg(method->holder()->constant_encoding(), klass);
89 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
90
91 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
92 __ mtctr(klass);
93 __ bctr();
94
95 __ bind(L_skip_barrier);
96 }
97
98 void LIR_Assembler::osr_entry() {
99 // On-stack-replacement entry sequence:
100 //
101 // 1. Create a new compiled activation.
102 // 2. Initialize local variables in the compiled activation. The expression
103 // stack must be empty at the osr_bci; it is not initialized.
104 // 3. Jump to the continuation address in compiled code to resume execution.
105
106 // OSR entry point
107 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
108 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
109 ValueStack* entry_state = osr_entry->end()->state();
110 int number_of_locks = entry_state->locks_size();
111
112 // Create a frame for the compiled activation.
113 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
114
115 // OSR buffer is
116 //
117 // locals[nlocals-1..0]
118 // monitors[number_of_locks-1..0]
119 //
120 // Locals is a direct copy of the interpreter frame so in the osr buffer
121 // the first slot in the local array is the last local from the interpreter
122 // and the last slot is local[0] (receiver) from the interpreter.
123 //
124 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
125 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
126 // in the interpreter frame (the method lock if a sync method).
127
128 // Initialize monitors in the compiled activation.
129 // R3: pointer to osr buffer
130 //
131 // All other registers are dead at this point and the locals will be
132 // copied into place by code emitted in the IR.
133
134 Register OSR_buf = osrBufferPointer()->as_register();
135 {
136 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
137
138 const int locals_space = BytesPerWord * method()->max_locals();
139 int monitor_offset = locals_space + (2 * BytesPerWord) * (number_of_locks - 1);
140 bool use_OSR_bias = false;
141
142 if (!Assembler::is_simm16(monitor_offset + BytesPerWord) && number_of_locks > 0) {
143 // Offsets too large for ld instructions. Use bias.
144 __ add_const_optimized(OSR_buf, OSR_buf, locals_space);
145 monitor_offset -= locals_space;
146 use_OSR_bias = true;
147 }
148
149 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
150 // the OSR buffer using 2 word entries: first the lock and then
151 // the oop.
152 for (int i = 0; i < number_of_locks; i++) {
153 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
154 #ifdef ASSERT
155 // Verify the interpreter's monitor has a non-null object.
156 {
157 Label L;
158 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
159 __ cmpdi(CR0, R0, 0);
160 __ bne(CR0, L);
161 __ stop("locked object is null");
162 __ bind(L);
163 }
164 #endif // ASSERT
165 // Copy the lock field into the compiled activation.
166 Address ml = frame_map()->address_for_monitor_lock(i),
167 mo = frame_map()->address_for_monitor_object(i);
168 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
169 __ ld(R0, slot_offset + 0, OSR_buf);
170 __ std(R0, ml);
171 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
172 __ std(R0, mo);
173 }
174
175 if (use_OSR_bias) {
176 // Restore.
177 __ sub_const_optimized(OSR_buf, OSR_buf, locals_space);
178 }
179 }
180 }
181
182
183 int LIR_Assembler::emit_exception_handler() {
184 // Generate code for the exception handler.
185 address handler_base = __ start_a_stub(exception_handler_size());
186
187 if (handler_base == nullptr) {
188 // Not enough space left for the handler.
189 bailout("exception handler overflow");
190 return -1;
191 }
192
193 int offset = code_offset();
194 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(C1StubId::handle_exception_from_callee_id));
195 //__ load_const_optimized(R0, entry_point);
196 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
197 __ mtctr(R0);
198 __ bctr();
199
200 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
201 __ end_a_stub();
202
203 return offset;
204 }
205
206
207 // Emit the code to remove the frame from the stack in the exception
208 // unwind path.
209 int LIR_Assembler::emit_unwind_handler() {
210 _masm->block_comment("Unwind handler");
211
212 int offset = code_offset();
213 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
214 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
215
216 // Fetch the exception from TLS and clear out exception related thread state.
217 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
218 __ li(R0, 0);
219 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
220 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
221
222 __ bind(_unwind_handler_entry);
223 __ verify_not_null_oop(Rexception);
224 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
225
226 // Perform needed unlocking
227 MonitorExitStub* stub = nullptr;
228 if (method()->is_synchronized()) {
229 monitor_address(0, FrameMap::R4_opr);
230 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
231 if (LockingMode == LM_MONITOR) {
232 __ b(*stub->entry());
233 } else {
234 __ unlock_object(R5, R6, R4, *stub->entry());
235 }
236 __ bind(*stub->continuation());
237 }
238
239 if (compilation()->env()->dtrace_method_probes()) {
240 Unimplemented();
241 }
242
243 // Dispatch to the unwind logic.
244 address unwind_stub = Runtime1::entry_for(C1StubId::unwind_exception_id);
245 //__ load_const_optimized(R0, unwind_stub);
246 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
247 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
248 __ mtctr(R0);
249 __ bctr();
250
251 // Emit the slow path assembly.
252 if (stub != nullptr) {
253 stub->emit_code(this);
254 }
255
256 return offset;
257 }
258
259
260 int LIR_Assembler::emit_deopt_handler() {
261 // Generate code for deopt handler.
262 address handler_base = __ start_a_stub(deopt_handler_size());
263
264 if (handler_base == nullptr) {
265 // Not enough space left for the handler.
266 bailout("deopt handler overflow");
267 return -1;
268 }
269
270 int offset = code_offset();
271 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
272
273 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
274 __ end_a_stub();
275
276 return offset;
277 }
278
279
280 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
281 if (o == nullptr) {
282 __ li(reg, 0);
283 } else {
284 AddressLiteral addrlit = __ constant_oop_address(o);
285 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
286 }
287 }
288
289
290 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
291 // Allocate a new index in table to hold the object once it's been patched.
292 int oop_index = __ oop_recorder()->allocate_oop_index(nullptr);
293 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
294
295 AddressLiteral addrlit((address)nullptr, oop_Relocation::spec(oop_index));
296 __ load_const(reg, addrlit, R0);
297
298 patching_epilog(patch, lir_patch_normal, reg, info);
299 }
300
301
302 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
303 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
304 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
305 }
306
307
308 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
309 // Allocate a new index in table to hold the klass once it's been patched.
310 int index = __ oop_recorder()->allocate_metadata_index(nullptr);
311 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
312
313 AddressLiteral addrlit((address)nullptr, metadata_Relocation::spec(index));
314 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
315 __ load_const(reg, addrlit, R0);
316
317 patching_epilog(patch, lir_patch_normal, reg, info);
318 }
319
320
321 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
322 const bool is_int = result->is_single_cpu();
323 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
324 Register Rdivisor = noreg;
325 Register Rscratch = temp->as_register();
326 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
327 long divisor = -1;
328
329 if (right->is_register()) {
330 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
331 } else {
332 divisor = is_int ? right->as_constant_ptr()->as_jint()
333 : right->as_constant_ptr()->as_jlong();
334 }
335
336 assert(Rdividend != Rscratch, "");
337 assert(Rdivisor != Rscratch, "");
338 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
339
340 if (Rdivisor == noreg) {
341 if (divisor == 1) { // stupid, but can happen
342 if (code == lir_idiv) {
343 __ mr_if_needed(Rresult, Rdividend);
344 } else {
345 __ li(Rresult, 0);
346 }
347
348 } else if (is_power_of_2(divisor)) {
349 // Convert division by a power of two into some shifts and logical operations.
350 int log2 = log2i_exact(divisor);
351
352 // Round towards 0.
353 if (divisor == 2) {
354 if (is_int) {
355 __ srwi(Rscratch, Rdividend, 31);
356 } else {
357 __ srdi(Rscratch, Rdividend, 63);
358 }
359 } else {
360 if (is_int) {
361 __ srawi(Rscratch, Rdividend, 31);
362 } else {
363 __ sradi(Rscratch, Rdividend, 63);
364 }
365 __ clrldi(Rscratch, Rscratch, 64-log2);
366 }
367 __ add(Rscratch, Rdividend, Rscratch);
368
369 if (code == lir_idiv) {
370 if (is_int) {
371 __ srawi(Rresult, Rscratch, log2);
372 } else {
373 __ sradi(Rresult, Rscratch, log2);
374 }
375 } else { // lir_irem
376 __ clrrdi(Rscratch, Rscratch, log2);
377 __ sub(Rresult, Rdividend, Rscratch);
378 }
379
380 } else if (divisor == -1) {
381 if (code == lir_idiv) {
382 __ neg(Rresult, Rdividend);
383 } else {
384 __ li(Rresult, 0);
385 }
386
387 } else {
388 __ load_const_optimized(Rscratch, divisor);
389 if (code == lir_idiv) {
390 if (is_int) {
391 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
392 } else {
393 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
394 }
395 } else {
396 assert(Rscratch != R0, "need both");
397 if (is_int) {
398 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
399 __ mullw(Rscratch, R0, Rscratch);
400 } else {
401 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
402 __ mulld(Rscratch, R0, Rscratch);
403 }
404 __ sub(Rresult, Rdividend, Rscratch);
405 }
406
407 }
408 return;
409 }
410
411 Label regular, done;
412 if (is_int) {
413 __ cmpwi(CR0, Rdivisor, -1);
414 } else {
415 __ cmpdi(CR0, Rdivisor, -1);
416 }
417 __ bne(CR0, regular);
418 if (code == lir_idiv) {
419 __ neg(Rresult, Rdividend);
420 __ b(done);
421 __ bind(regular);
422 if (is_int) {
423 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
424 } else {
425 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
426 }
427 } else { // lir_irem
428 __ li(Rresult, 0);
429 __ b(done);
430 __ bind(regular);
431 if (is_int) {
432 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
433 __ mullw(Rscratch, Rscratch, Rdivisor);
434 } else {
435 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
436 __ mulld(Rscratch, Rscratch, Rdivisor);
437 }
438 __ sub(Rresult, Rdividend, Rscratch);
439 }
440 __ bind(done);
441 }
442
443
444 void LIR_Assembler::emit_op3(LIR_Op3* op) {
445 switch (op->code()) {
446 case lir_idiv:
447 case lir_irem:
448 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
449 op->result_opr(), op->info());
450 break;
451 case lir_fmad:
452 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
453 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
454 break;
455 case lir_fmaf:
456 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
457 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
458 break;
459 default: ShouldNotReachHere(); break;
460 }
461 }
462
463
464 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
465 #ifdef ASSERT
466 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
467 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
468 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
469 assert(op->info() == nullptr, "shouldn't have CodeEmitInfo");
470 #endif
471
472 Label *L = op->label();
473 if (op->cond() == lir_cond_always) {
474 __ b(*L);
475 } else {
476 Label done;
477 bool is_unordered = false;
478 if (op->code() == lir_cond_float_branch) {
479 assert(op->ublock() != nullptr, "must have unordered successor");
480 is_unordered = true;
481 } else {
482 assert(op->code() == lir_branch, "just checking");
483 }
484
485 bool positive = false;
486 Assembler::Condition cond = Assembler::equal;
487 switch (op->cond()) {
488 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
489 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
490 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
491 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
492 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
493 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
494 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
495 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
496 default: ShouldNotReachHere();
497 }
498 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
499 int bi = Assembler::bi0(BOOL_RESULT, cond);
500 if (is_unordered) {
501 if (positive) {
502 if (op->ublock() == op->block()) {
503 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
504 }
505 } else {
506 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
507 }
508 }
509 __ bc_far_optimized(bo, bi, *L);
510 __ bind(done);
511 }
512 }
513
514
515 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
516 Bytecodes::Code code = op->bytecode();
517 LIR_Opr src = op->in_opr(),
518 dst = op->result_opr();
519
520 switch(code) {
521 case Bytecodes::_i2l: {
522 __ extsw(dst->as_register_lo(), src->as_register());
523 break;
524 }
525 case Bytecodes::_l2i: {
526 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
527 break;
528 }
529 case Bytecodes::_i2b: {
530 __ extsb(dst->as_register(), src->as_register());
531 break;
532 }
533 case Bytecodes::_i2c: {
534 __ clrldi(dst->as_register(), src->as_register(), 64-16);
535 break;
536 }
537 case Bytecodes::_i2s: {
538 __ extsh(dst->as_register(), src->as_register());
539 break;
540 }
541 case Bytecodes::_i2d:{
542 FloatRegister rdst = dst->as_double_reg();
543 // move src to dst register
544 __ mtfprwa(rdst, src->as_register());
545 __ fcfid(rdst, rdst);
546 break;
547 }
548 case Bytecodes::_l2d: {
549 FloatRegister rdst = dst->as_double_reg();
550 // move src to dst register
551 __ mtfprd(rdst, src->as_register_lo());
552 __ fcfid(rdst, rdst);
553 break;
554 }
555 case Bytecodes::_i2f:{
556 FloatRegister rdst = dst->as_float_reg();
557 // move src to dst register
558 __ mtfprwa(rdst, src->as_register());
559 __ fcfids(rdst, rdst);
560 break;
561 }
562 case Bytecodes::_l2f: {
563 FloatRegister rdst = dst->as_float_reg();
564 // move src to dst register
565 __ mtfprd(rdst, src->as_register_lo());
566 __ fcfids(rdst, rdst);
567 break;
568 }
569 case Bytecodes::_f2d: {
570 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
571 break;
572 }
573 case Bytecodes::_d2f: {
574 __ frsp(dst->as_float_reg(), src->as_double_reg());
575 break;
576 }
577 case Bytecodes::_d2i:
578 case Bytecodes::_f2i: {
579 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
580 Label L;
581 // Result must be 0 if value is NaN; test by comparing value to itself.
582 __ fcmpu(CR0, rsrc, rsrc);
583 __ li(dst->as_register(), 0);
584 __ bso(CR0, L);
585 __ fctiwz(rsrc, rsrc); // USE_KILL
586 __ mffprd(dst->as_register(), rsrc);
587 __ bind(L);
588 break;
589 }
590 case Bytecodes::_d2l:
591 case Bytecodes::_f2l: {
592 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
593 Label L;
594 // Result must be 0 if value is NaN; test by comparing value to itself.
595 __ fcmpu(CR0, rsrc, rsrc);
596 __ li(dst->as_register_lo(), 0);
597 __ bso(CR0, L);
598 __ fctidz(rsrc, rsrc); // USE_KILL
599 __ mffprd(dst->as_register_lo(), rsrc);
600 __ bind(L);
601 break;
602 }
603
604 default: ShouldNotReachHere();
605 }
606 }
607
608
609 void LIR_Assembler::align_call(LIR_Code) {
610 // do nothing since all instructions are word aligned on ppc
611 }
612
613
614 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
615 int start_offset = __ offset();
616 // Put the entry point as a constant into the constant pool.
617 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
618 if (entry_point_toc_addr == nullptr) {
619 bailout("const section overflow");
620 return false;
621 }
622 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
623
624 // Emit the trampoline stub which will be related to the branch-and-link below.
625 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
626 if (!stub) {
627 bailout("no space for trampoline stub");
628 return false;
629 }
630 return true;
631 }
632
633
634 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
635 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
636
637 bool success = emit_trampoline_stub_for_call(op->addr());
638 if (!success) { return; }
639
640 __ relocate(rtype);
641 // Note: At this point we do not have the address of the trampoline
642 // stub, and the entry point might be too far away for bl, so __ pc()
643 // serves as dummy and the bl will be patched later.
644 __ code()->set_insts_mark();
645 __ bl(__ pc());
646 add_call_info(code_offset(), op->info());
647 __ post_call_nop();
648 }
649
650
651 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
652 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
653
654 // Virtual call relocation will point to ic load.
655 address virtual_call_meta_addr = __ pc();
656 // Load a clear inline cache.
657 AddressLiteral empty_ic((address) Universe::non_oop_word());
658 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
659 if (!success) {
660 bailout("const section overflow");
661 return;
662 }
663 // Call to fixup routine. Fixup routine uses ScopeDesc info
664 // to determine who we intended to call.
665 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
666
667 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
668 if (!success) { return; }
669
670 // Note: At this point we do not have the address of the trampoline
671 // stub, and the entry point might be too far away for bl, so __ pc()
672 // serves as dummy and the bl will be patched later.
673 __ bl(__ pc());
674 add_call_info(code_offset(), op->info());
675 __ post_call_nop();
676 }
677
678 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
679 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
680 __ null_check(addr, stub->entry());
681 append_code_stub(stub);
682 }
683
684
685 // Attention: caller must encode oop if needed
686 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
687 int store_offset;
688 if (!Assembler::is_simm16(offset)) {
689 // For offsets larger than a simm16 we setup the offset.
690 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
691 __ load_const_optimized(R0, offset);
692 store_offset = store(from_reg, base, R0, type, wide);
693 } else {
694 store_offset = code_offset();
695 switch (type) {
696 case T_BOOLEAN: // fall through
697 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
698 case T_CHAR :
699 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
700 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
701 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
702 case T_ADDRESS:
703 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
704 case T_ARRAY : // fall through
705 case T_OBJECT:
706 {
707 if (UseCompressedOops && !wide) {
708 // Encoding done in caller
709 __ stw(from_reg->as_register(), offset, base);
710 __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
711 } else {
712 __ std(from_reg->as_register(), offset, base);
713 if (VerifyOops) {
714 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
715 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
716 }
717 }
718 break;
719 }
720 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
721 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
722 default : ShouldNotReachHere();
723 }
724 }
725 return store_offset;
726 }
727
728
729 // Attention: caller must encode oop if needed
730 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
731 int store_offset = code_offset();
732 switch (type) {
733 case T_BOOLEAN: // fall through
734 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
735 case T_CHAR :
736 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
737 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
738 case T_LONG :
739 #ifdef _LP64
740 __ stdx(from_reg->as_register_lo(), base, disp);
741 #else
742 Unimplemented();
743 #endif
744 break;
745 case T_ADDRESS:
746 __ stdx(from_reg->as_register(), base, disp);
747 break;
748 case T_ARRAY : // fall through
749 case T_OBJECT:
750 {
751 if (UseCompressedOops && !wide) {
752 // Encoding done in caller.
753 __ stwx(from_reg->as_register(), base, disp);
754 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
755 } else {
756 __ stdx(from_reg->as_register(), base, disp);
757 if (VerifyOops) {
758 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
759 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
760 }
761 }
762 break;
763 }
764 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
765 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
766 default : ShouldNotReachHere();
767 }
768 return store_offset;
769 }
770
771
772 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
773 int load_offset;
774 if (!Assembler::is_simm16(offset)) {
775 // For offsets larger than a simm16 we setup the offset.
776 __ load_const_optimized(R0, offset);
777 load_offset = load(base, R0, to_reg, type, wide);
778 } else {
779 load_offset = code_offset();
780 switch(type) {
781 case T_BOOLEAN: // fall through
782 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
783 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
784 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
785 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
786 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
787 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
788 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
789 case T_ADDRESS:
790 __ ld(to_reg->as_register(), offset, base);
791 break;
792 case T_ARRAY : // fall through
793 case T_OBJECT:
794 {
795 if (UseCompressedOops && !wide) {
796 __ lwz(to_reg->as_register(), offset, base);
797 __ decode_heap_oop(to_reg->as_register());
798 } else {
799 __ ld(to_reg->as_register(), offset, base);
800 }
801 break;
802 }
803 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
804 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
805 default : ShouldNotReachHere();
806 }
807 }
808 return load_offset;
809 }
810
811
812 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
813 int load_offset = code_offset();
814 switch(type) {
815 case T_BOOLEAN: // fall through
816 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
817 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
818 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
819 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
820 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
821 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
822 case T_ARRAY : // fall through
823 case T_OBJECT:
824 {
825 if (UseCompressedOops && !wide) {
826 __ lwzx(to_reg->as_register(), base, disp);
827 __ decode_heap_oop(to_reg->as_register());
828 } else {
829 __ ldx(to_reg->as_register(), base, disp);
830 }
831 break;
832 }
833 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
834 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
835 case T_LONG :
836 #ifdef _LP64
837 __ ldx(to_reg->as_register_lo(), base, disp);
838 #else
839 Unimplemented();
840 #endif
841 break;
842 default : ShouldNotReachHere();
843 }
844 return load_offset;
845 }
846
847
848 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
849 LIR_Const* c = src->as_constant_ptr();
850 Register src_reg = R0;
851 switch (c->type()) {
852 case T_INT:
853 case T_FLOAT: {
854 int value = c->as_jint_bits();
855 __ load_const_optimized(src_reg, value);
856 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
857 __ stw(src_reg, addr);
858 break;
859 }
860 case T_ADDRESS: {
861 int value = c->as_jint_bits();
862 __ load_const_optimized(src_reg, value);
863 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
864 __ std(src_reg, addr);
865 break;
866 }
867 case T_OBJECT: {
868 jobject2reg(c->as_jobject(), src_reg);
869 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
870 __ std(src_reg, addr);
871 break;
872 }
873 case T_LONG:
874 case T_DOUBLE: {
875 int value = c->as_jlong_bits();
876 __ load_const_optimized(src_reg, value);
877 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
878 __ std(src_reg, addr);
879 break;
880 }
881 default:
882 Unimplemented();
883 }
884 }
885
886
887 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
888 LIR_Const* c = src->as_constant_ptr();
889 LIR_Address* addr = dest->as_address_ptr();
890 Register base = addr->base()->as_pointer_register();
891 LIR_Opr tmp = LIR_OprFact::illegalOpr;
892 int offset = -1;
893 // Null check for large offsets in LIRGenerator::do_StoreField.
894 bool needs_explicit_null_check = !ImplicitNullChecks;
895
896 if (info != nullptr && needs_explicit_null_check) {
897 explicit_null_check(base, info);
898 }
899
900 switch (c->type()) {
901 case T_FLOAT: type = T_INT;
902 case T_INT:
903 case T_ADDRESS: {
904 tmp = FrameMap::R0_opr;
905 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
906 break;
907 }
908 case T_DOUBLE: type = T_LONG;
909 case T_LONG: {
910 tmp = FrameMap::R0_long_opr;
911 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
912 break;
913 }
914 case T_OBJECT: {
915 tmp = FrameMap::R0_opr;
916 if (UseCompressedOops && !wide && c->as_jobject() != nullptr) {
917 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
918 // Don't care about sign extend (will use stw).
919 __ lis(R0, 0); // Will get patched.
920 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
921 __ ori(R0, R0, 0); // Will get patched.
922 } else {
923 jobject2reg(c->as_jobject(), R0);
924 }
925 break;
926 }
927 default:
928 Unimplemented();
929 }
930
931 // Handle either reg+reg or reg+disp address.
932 if (addr->index()->is_valid()) {
933 assert(addr->disp() == 0, "must be zero");
934 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
935 } else {
936 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
937 offset = store(tmp, base, addr->disp(), type, wide);
938 }
939
940 if (info != nullptr) {
941 assert(offset != -1, "offset should've been set");
942 if (!needs_explicit_null_check) {
943 add_debug_info_for_null_check(offset, info);
944 }
945 }
946 }
947
948
949 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
950 LIR_Const* c = src->as_constant_ptr();
951 LIR_Opr to_reg = dest;
952
953 switch (c->type()) {
954 case T_INT: {
955 assert(patch_code == lir_patch_none, "no patching handled here");
956 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
957 break;
958 }
959 case T_ADDRESS: {
960 assert(patch_code == lir_patch_none, "no patching handled here");
961 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
962 break;
963 }
964 case T_LONG: {
965 assert(patch_code == lir_patch_none, "no patching handled here");
966 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
967 break;
968 }
969
970 case T_OBJECT: {
971 if (patch_code == lir_patch_none) {
972 jobject2reg(c->as_jobject(), to_reg->as_register());
973 } else {
974 jobject2reg_with_patching(to_reg->as_register(), info);
975 }
976 break;
977 }
978
979 case T_METADATA:
980 {
981 if (patch_code == lir_patch_none) {
982 metadata2reg(c->as_metadata(), to_reg->as_register());
983 } else {
984 klass2reg_with_patching(to_reg->as_register(), info);
985 }
986 }
987 break;
988
989 case T_FLOAT:
990 {
991 if (to_reg->is_single_fpu()) {
992 address const_addr = __ float_constant(c->as_jfloat());
993 if (const_addr == nullptr) {
994 bailout("const section overflow");
995 break;
996 }
997 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
998 __ relocate(rspec);
999 __ load_const(R0, const_addr);
1000 __ lfsx(to_reg->as_float_reg(), R0);
1001 } else {
1002 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1003 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1004 }
1005 }
1006 break;
1007
1008 case T_DOUBLE:
1009 {
1010 if (to_reg->is_double_fpu()) {
1011 address const_addr = __ double_constant(c->as_jdouble());
1012 if (const_addr == nullptr) {
1013 bailout("const section overflow");
1014 break;
1015 }
1016 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1017 __ relocate(rspec);
1018 __ load_const(R0, const_addr);
1019 __ lfdx(to_reg->as_double_reg(), R0);
1020 } else {
1021 assert(to_reg->is_double_cpu(), "Must be a long register.");
1022 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1023 }
1024 }
1025 break;
1026
1027 default:
1028 ShouldNotReachHere();
1029 }
1030 }
1031
1032
1033 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1034 Unimplemented(); return Address();
1035 }
1036
1037
1038 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1039 if (addr->index()->is_illegal()) {
1040 return (RegisterOrConstant)(addr->disp());
1041 } else {
1042 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1043 }
1044 }
1045
1046
1047 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1048 const Register tmp = R0;
1049 switch (type) {
1050 case T_INT:
1051 case T_FLOAT: {
1052 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1053 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1054 __ lwz(tmp, from);
1055 __ stw(tmp, to);
1056 break;
1057 }
1058 case T_ADDRESS:
1059 case T_OBJECT: {
1060 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1061 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1062 __ ld(tmp, from);
1063 __ std(tmp, to);
1064 break;
1065 }
1066 case T_LONG:
1067 case T_DOUBLE: {
1068 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1069 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1070 __ ld(tmp, from);
1071 __ std(tmp, to);
1072 break;
1073 }
1074
1075 default:
1076 ShouldNotReachHere();
1077 }
1078 }
1079
1080
1081 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1082 Unimplemented(); return Address();
1083 }
1084
1085
1086 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1087 Unimplemented(); return Address();
1088 }
1089
1090
1091 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1092 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1093
1094 assert(type != T_METADATA, "load of metadata ptr not supported");
1095 LIR_Address* addr = src_opr->as_address_ptr();
1096 LIR_Opr to_reg = dest;
1097
1098 Register src = addr->base()->as_pointer_register();
1099 Register disp_reg = noreg;
1100 int disp_value = addr->disp();
1101 bool needs_patching = (patch_code != lir_patch_none);
1102 // null check for large offsets in LIRGenerator::do_LoadField
1103 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1104
1105 if (info != nullptr && needs_explicit_null_check) {
1106 explicit_null_check(src, info);
1107 }
1108
1109 if (addr->base()->type() == T_OBJECT) {
1110 __ verify_oop(src, FILE_AND_LINE);
1111 }
1112
1113 PatchingStub* patch = nullptr;
1114 if (needs_patching) {
1115 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1116 assert(!to_reg->is_double_cpu() ||
1117 patch_code == lir_patch_none ||
1118 patch_code == lir_patch_normal, "patching doesn't match register");
1119 }
1120
1121 if (addr->index()->is_illegal()) {
1122 if (!Assembler::is_simm16(disp_value)) {
1123 if (needs_patching) {
1124 __ load_const32(R0, 0); // patchable int
1125 } else {
1126 __ load_const_optimized(R0, disp_value);
1127 }
1128 disp_reg = R0;
1129 }
1130 } else {
1131 disp_reg = addr->index()->as_pointer_register();
1132 assert(disp_value == 0, "can't handle 3 operand addresses");
1133 }
1134
1135 // Remember the offset of the load. The patching_epilog must be done
1136 // before the call to add_debug_info, otherwise the PcDescs don't get
1137 // entered in increasing order.
1138 int offset;
1139
1140 if (disp_reg == noreg) {
1141 assert(Assembler::is_simm16(disp_value), "should have set this up");
1142 offset = load(src, disp_value, to_reg, type, wide);
1143 } else {
1144 offset = load(src, disp_reg, to_reg, type, wide);
1145 }
1146
1147 if (patch != nullptr) {
1148 patching_epilog(patch, patch_code, src, info);
1149 }
1150 if (info != nullptr && !needs_explicit_null_check) {
1151 add_debug_info_for_null_check(offset, info);
1152 }
1153 }
1154
1155
1156 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1157 Address addr;
1158 if (src->is_single_word()) {
1159 addr = frame_map()->address_for_slot(src->single_stack_ix());
1160 } else if (src->is_double_word()) {
1161 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1162 }
1163
1164 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1165 }
1166
1167
1168 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type) {
1169 Address addr;
1170 if (dest->is_single_word()) {
1171 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1172 } else if (dest->is_double_word()) {
1173 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1174 }
1175
1176 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1177 }
1178
1179
1180 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1181 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1182 if (from_reg->is_double_fpu()) {
1183 // double to double moves
1184 assert(to_reg->is_double_fpu(), "should match");
1185 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1186 } else {
1187 // float to float moves
1188 assert(to_reg->is_single_fpu(), "should match");
1189 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1190 }
1191 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1192 if (from_reg->is_double_cpu()) {
1193 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1194 } else if (to_reg->is_double_cpu()) {
1195 // int to int moves
1196 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1197 } else {
1198 // int to int moves
1199 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1200 }
1201 } else {
1202 ShouldNotReachHere();
1203 }
1204 if (is_reference_type(to_reg->type())) {
1205 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1206 }
1207 }
1208
1209
1210 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1211 LIR_PatchCode patch_code, CodeEmitInfo* info,
1212 bool wide) {
1213 assert(type != T_METADATA, "store of metadata ptr not supported");
1214 LIR_Address* addr = dest->as_address_ptr();
1215
1216 Register src = addr->base()->as_pointer_register();
1217 Register disp_reg = noreg;
1218 int disp_value = addr->disp();
1219 bool needs_patching = (patch_code != lir_patch_none);
1220 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1221 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1222 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1223 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1224 // Null check for large offsets in LIRGenerator::do_StoreField.
1225 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1226
1227 if (info != nullptr && needs_explicit_null_check) {
1228 explicit_null_check(src, info);
1229 }
1230
1231 if (addr->base()->is_oop_register()) {
1232 __ verify_oop(src, FILE_AND_LINE);
1233 }
1234
1235 PatchingStub* patch = nullptr;
1236 if (needs_patching) {
1237 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1238 assert(!from_reg->is_double_cpu() ||
1239 patch_code == lir_patch_none ||
1240 patch_code == lir_patch_normal, "patching doesn't match register");
1241 }
1242
1243 if (addr->index()->is_illegal()) {
1244 if (load_disp) {
1245 disp_reg = use_R29 ? R29_TOC : R0;
1246 if (needs_patching) {
1247 __ load_const32(disp_reg, 0); // patchable int
1248 } else {
1249 __ load_const_optimized(disp_reg, disp_value);
1250 }
1251 }
1252 } else {
1253 disp_reg = addr->index()->as_pointer_register();
1254 assert(disp_value == 0, "can't handle 3 operand addresses");
1255 }
1256
1257 // remember the offset of the store. The patching_epilog must be done
1258 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1259 // entered in increasing order.
1260 int offset;
1261
1262 if (compress_oop) {
1263 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1264 from_reg = FrameMap::as_opr(co);
1265 }
1266
1267 if (disp_reg == noreg) {
1268 assert(Assembler::is_simm16(disp_value), "should have set this up");
1269 offset = store(from_reg, src, disp_value, type, wide);
1270 } else {
1271 offset = store(from_reg, src, disp_reg, type, wide);
1272 }
1273
1274 if (use_R29) {
1275 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1276 }
1277
1278 if (patch != nullptr) {
1279 patching_epilog(patch, patch_code, src, info);
1280 }
1281
1282 if (info != nullptr && !needs_explicit_null_check) {
1283 add_debug_info_for_null_check(offset, info);
1284 }
1285 }
1286
1287
1288 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1289 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1290 const Register temp = R12;
1291
1292 // Pop the stack before the safepoint code.
1293 int frame_size = initial_frame_size_in_bytes();
1294 if (Assembler::is_simm(frame_size, 16)) {
1295 __ addi(R1_SP, R1_SP, frame_size);
1296 } else {
1297 __ pop_frame();
1298 }
1299
1300 // Restore return pc relative to callers' sp.
1301 __ ld(return_pc, _abi0(lr), R1_SP);
1302 // Move return pc to LR.
1303 __ mtlr(return_pc);
1304
1305 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1306 __ reserved_stack_check(return_pc);
1307 }
1308
1309 // We need to mark the code position where the load from the safepoint
1310 // polling page was emitted as relocInfo::poll_return_type here.
1311 if (!UseSIGTRAP) {
1312 code_stub->set_safepoint_offset(__ offset());
1313 __ relocate(relocInfo::poll_return_type);
1314 }
1315 __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1316
1317 // Return.
1318 __ blr();
1319 }
1320
1321
1322 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1323 const Register poll_addr = tmp->as_register();
1324 __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1325 if (info != nullptr) {
1326 add_debug_info_for_branch(info);
1327 }
1328 int offset = __ offset();
1329 __ relocate(relocInfo::poll_type);
1330 __ load_from_polling_page(poll_addr);
1331
1332 return offset;
1333 }
1334
1335
1336 void LIR_Assembler::emit_static_call_stub() {
1337 address call_pc = __ pc();
1338 address stub = __ start_a_stub(static_call_stub_size());
1339 if (stub == nullptr) {
1340 bailout("static call stub overflow");
1341 return;
1342 }
1343
1344 // For java_to_interp stubs we use R11_scratch1 as scratch register
1345 // and in call trampoline stubs we use R12_scratch2. This way we
1346 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1347 const Register reg_scratch = R11_scratch1;
1348
1349 // Create a static stub relocation which relates this stub
1350 // with the call instruction at insts_call_instruction_offset in the
1351 // instructions code-section.
1352 int start = __ offset();
1353 __ relocate(static_stub_Relocation::spec(call_pc));
1354
1355 // Now, create the stub's code:
1356 // - load the TOC
1357 // - load the inline cache oop from the constant pool
1358 // - load the call target from the constant pool
1359 // - call
1360 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1361 AddressLiteral ic = __ allocate_metadata_address((Metadata *)nullptr);
1362 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1363
1364 if (ReoptimizeCallSequences) {
1365 __ b64_patchable((address)-1, relocInfo::none);
1366 } else {
1367 AddressLiteral a((address)-1);
1368 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1369 __ mtctr(reg_scratch);
1370 __ bctr();
1371 }
1372 if (!success) {
1373 bailout("const section overflow");
1374 return;
1375 }
1376
1377 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1378 __ end_a_stub();
1379 }
1380
1381
1382 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1383 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1384 if (opr1->is_single_fpu()) {
1385 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1386 } else if (opr1->is_double_fpu()) {
1387 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1388 } else if (opr1->is_single_cpu()) {
1389 if (opr2->is_constant()) {
1390 switch (opr2->as_constant_ptr()->type()) {
1391 case T_INT:
1392 {
1393 jint con = opr2->as_constant_ptr()->as_jint();
1394 if (unsigned_comp) {
1395 if (Assembler::is_uimm(con, 16)) {
1396 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1397 } else {
1398 __ load_const_optimized(R0, con);
1399 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1400 }
1401 } else {
1402 if (Assembler::is_simm(con, 16)) {
1403 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1404 } else {
1405 __ load_const_optimized(R0, con);
1406 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1407 }
1408 }
1409 }
1410 break;
1411
1412 case T_OBJECT:
1413 // There are only equal/notequal comparisons on objects.
1414 {
1415 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1416 jobject con = opr2->as_constant_ptr()->as_jobject();
1417 if (con == nullptr) {
1418 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1419 } else {
1420 jobject2reg(con, R0);
1421 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1422 }
1423 }
1424 break;
1425
1426 case T_METADATA:
1427 // We only need, for now, comparison with null for metadata.
1428 {
1429 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1430 Metadata* p = opr2->as_constant_ptr()->as_metadata();
1431 if (p == nullptr) {
1432 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1433 } else {
1434 ShouldNotReachHere();
1435 }
1436 }
1437 break;
1438
1439 default:
1440 ShouldNotReachHere();
1441 break;
1442 }
1443 } else {
1444 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1445 if (is_reference_type(opr1->type())) {
1446 // There are only equal/notequal comparisons on objects.
1447 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1448 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1449 } else {
1450 if (unsigned_comp) {
1451 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1452 } else {
1453 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1454 }
1455 }
1456 }
1457 } else if (opr1->is_double_cpu()) {
1458 if (opr2->is_constant()) {
1459 jlong con = opr2->as_constant_ptr()->as_jlong();
1460 if (unsigned_comp) {
1461 if (Assembler::is_uimm(con, 16)) {
1462 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1463 } else {
1464 __ load_const_optimized(R0, con);
1465 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1466 }
1467 } else {
1468 if (Assembler::is_simm(con, 16)) {
1469 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1470 } else {
1471 __ load_const_optimized(R0, con);
1472 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1473 }
1474 }
1475 } else if (opr2->is_register()) {
1476 if (unsigned_comp) {
1477 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1478 } else {
1479 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1480 }
1481 } else {
1482 ShouldNotReachHere();
1483 }
1484 } else {
1485 ShouldNotReachHere();
1486 }
1487 }
1488
1489
1490 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1491 const Register Rdst = dst->as_register();
1492 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1493 bool is_unordered_less = (code == lir_ucmp_fd2i);
1494 if (left->is_single_fpu()) {
1495 __ fcmpu(CR0, left->as_float_reg(), right->as_float_reg());
1496 } else if (left->is_double_fpu()) {
1497 __ fcmpu(CR0, left->as_double_reg(), right->as_double_reg());
1498 } else {
1499 ShouldNotReachHere();
1500 }
1501 __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1502 } else if (code == lir_cmp_l2i) {
1503 __ cmpd(CR0, left->as_register_lo(), right->as_register_lo());
1504 __ set_cmp3(Rdst); // set result as follows: <: -1, =: 0, >: 1
1505 } else {
1506 ShouldNotReachHere();
1507 }
1508 }
1509
1510
1511 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1512 if (src->is_constant()) {
1513 lasm->const2reg(src, dst, lir_patch_none, nullptr);
1514 } else if (src->is_register()) {
1515 lasm->reg2reg(src, dst);
1516 } else if (src->is_stack()) {
1517 lasm->stack2reg(src, dst, dst->type());
1518 } else {
1519 ShouldNotReachHere();
1520 }
1521 }
1522
1523 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1524 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1525 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
1526
1527 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1528 load_to_reg(this, opr1, result); // Condition doesn't matter.
1529 return;
1530 }
1531
1532 bool positive = false;
1533 Assembler::Condition cond = Assembler::equal;
1534 switch (condition) {
1535 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1536 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1537 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1538 case lir_cond_belowEqual:
1539 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1540 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1541 case lir_cond_aboveEqual:
1542 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1543 default: ShouldNotReachHere();
1544 }
1545
1546 if (result->is_cpu_register()) {
1547 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1548 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1549
1550 // We can use result_reg to load one operand if not already in register.
1551 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1552 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1553
1554 if (first != second) {
1555 if (!o1_is_reg) {
1556 load_to_reg(this, opr1, result);
1557 }
1558
1559 if (!o2_is_reg) {
1560 load_to_reg(this, opr2, result);
1561 }
1562
1563 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1564 return;
1565 }
1566 } // isel
1567
1568 load_to_reg(this, opr1, result);
1569
1570 Label skip;
1571 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1572 int bi = Assembler::bi0(BOOL_RESULT, cond);
1573 __ bc(bo, bi, skip);
1574
1575 load_to_reg(this, opr2, result);
1576 __ bind(skip);
1577 }
1578
1579
1580 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1581 CodeEmitInfo* info) {
1582 assert(info == nullptr, "unused on this code path");
1583 assert(left->is_register(), "wrong items state");
1584 assert(dest->is_register(), "wrong items state");
1585
1586 if (right->is_register()) {
1587 if (dest->is_float_kind()) {
1588
1589 FloatRegister lreg, rreg, res;
1590 if (right->is_single_fpu()) {
1591 lreg = left->as_float_reg();
1592 rreg = right->as_float_reg();
1593 res = dest->as_float_reg();
1594 switch (code) {
1595 case lir_add: __ fadds(res, lreg, rreg); break;
1596 case lir_sub: __ fsubs(res, lreg, rreg); break;
1597 case lir_mul: __ fmuls(res, lreg, rreg); break;
1598 case lir_div: __ fdivs(res, lreg, rreg); break;
1599 default: ShouldNotReachHere();
1600 }
1601 } else {
1602 lreg = left->as_double_reg();
1603 rreg = right->as_double_reg();
1604 res = dest->as_double_reg();
1605 switch (code) {
1606 case lir_add: __ fadd(res, lreg, rreg); break;
1607 case lir_sub: __ fsub(res, lreg, rreg); break;
1608 case lir_mul: __ fmul(res, lreg, rreg); break;
1609 case lir_div: __ fdiv(res, lreg, rreg); break;
1610 default: ShouldNotReachHere();
1611 }
1612 }
1613
1614 } else if (dest->is_double_cpu()) {
1615
1616 Register dst_lo = dest->as_register_lo();
1617 Register op1_lo = left->as_pointer_register();
1618 Register op2_lo = right->as_pointer_register();
1619
1620 switch (code) {
1621 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1622 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1623 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1624 default: ShouldNotReachHere();
1625 }
1626 } else {
1627 assert (right->is_single_cpu(), "Just Checking");
1628
1629 Register lreg = left->as_register();
1630 Register res = dest->as_register();
1631 Register rreg = right->as_register();
1632 switch (code) {
1633 case lir_add: __ add (res, lreg, rreg); break;
1634 case lir_sub: __ sub (res, lreg, rreg); break;
1635 case lir_mul: __ mullw(res, lreg, rreg); break;
1636 default: ShouldNotReachHere();
1637 }
1638 }
1639 } else {
1640 assert (right->is_constant(), "must be constant");
1641
1642 if (dest->is_single_cpu()) {
1643 Register lreg = left->as_register();
1644 Register res = dest->as_register();
1645 int simm16 = right->as_constant_ptr()->as_jint();
1646
1647 switch (code) {
1648 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1649 simm16 = -simm16;
1650 case lir_add: if (res == lreg && simm16 == 0) break;
1651 __ addi(res, lreg, simm16); break;
1652 case lir_mul: if (res == lreg && simm16 == 1) break;
1653 __ mulli(res, lreg, simm16); break;
1654 default: ShouldNotReachHere();
1655 }
1656 } else {
1657 Register lreg = left->as_pointer_register();
1658 Register res = dest->as_register_lo();
1659 long con = right->as_constant_ptr()->as_jlong();
1660 assert(Assembler::is_simm16(con), "must be simm16");
1661
1662 switch (code) {
1663 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1664 con = -con;
1665 case lir_add: if (res == lreg && con == 0) break;
1666 __ addi(res, lreg, (int)con); break;
1667 case lir_mul: if (res == lreg && con == 1) break;
1668 __ mulli(res, lreg, (int)con); break;
1669 default: ShouldNotReachHere();
1670 }
1671 }
1672 }
1673 }
1674
1675
1676 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1677 switch (code) {
1678 case lir_sqrt: {
1679 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1680 break;
1681 }
1682 case lir_abs: {
1683 __ fabs(dest->as_double_reg(), value->as_double_reg());
1684 break;
1685 }
1686 case lir_f2hf: {
1687 __ f2hf(dest.as_register(), value.as_float_reg(), tmp.as_float_reg());
1688 break;
1689 }
1690 case lir_hf2f: {
1691 __ hf2f(dest->as_float_reg(), value.as_register());
1692 break;
1693 }
1694 default: {
1695 ShouldNotReachHere();
1696 break;
1697 }
1698 }
1699 }
1700
1701
1702 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1703 if (right->is_constant()) { // see do_LogicOp
1704 long uimm;
1705 Register d, l;
1706 if (dest->is_single_cpu()) {
1707 uimm = right->as_constant_ptr()->as_jint();
1708 d = dest->as_register();
1709 l = left->as_register();
1710 } else {
1711 uimm = right->as_constant_ptr()->as_jlong();
1712 d = dest->as_register_lo();
1713 l = left->as_register_lo();
1714 }
1715 long uimms = (unsigned long)uimm >> 16,
1716 uimmss = (unsigned long)uimm >> 32;
1717
1718 switch (code) {
1719 case lir_logic_and:
1720 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1721 __ andi(d, l, uimm); // special cases
1722 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1723 else { __ andi_(d, l, uimm); }
1724 break;
1725
1726 case lir_logic_or:
1727 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1728 else { __ ori(d, l, uimm); }
1729 break;
1730
1731 case lir_logic_xor:
1732 if (uimm == -1) { __ nand(d, l, l); } // special case
1733 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1734 else { __ xori(d, l, uimm); }
1735 break;
1736
1737 default: ShouldNotReachHere();
1738 }
1739 } else {
1740 assert(right->is_register(), "right should be in register");
1741
1742 if (dest->is_single_cpu()) {
1743 switch (code) {
1744 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1745 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1746 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1747 default: ShouldNotReachHere();
1748 }
1749 } else {
1750 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1751 left->as_register_lo();
1752 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1753 right->as_register_lo();
1754
1755 switch (code) {
1756 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1757 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1758 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1759 default: ShouldNotReachHere();
1760 }
1761 }
1762 }
1763 }
1764
1765
1766 int LIR_Assembler::shift_amount(BasicType t) {
1767 int elem_size = type2aelembytes(t);
1768 switch (elem_size) {
1769 case 1 : return 0;
1770 case 2 : return 1;
1771 case 4 : return 2;
1772 case 8 : return 3;
1773 }
1774 ShouldNotReachHere();
1775 return -1;
1776 }
1777
1778
1779 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1780 info->add_register_oop(exceptionOop);
1781
1782 // Reuse the debug info from the safepoint poll for the throw op itself.
1783 address pc_for_athrow = __ pc();
1784 int pc_for_athrow_offset = __ offset();
1785 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1786 //__ relocate(rspec);
1787 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1788 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1789 add_call_info(pc_for_athrow_offset, info); // for exception handler
1790
1791 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? C1StubId::handle_exception_id
1792 : C1StubId::handle_exception_nofpu_id);
1793 //__ load_const_optimized(R0, stub);
1794 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1795 __ mtctr(R0);
1796 __ bctr();
1797 }
1798
1799
1800 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1801 // Note: Not used with EnableDebuggingOnDemand.
1802 assert(exceptionOop->as_register() == R3, "should match");
1803 __ b(_unwind_handler_entry);
1804 }
1805
1806
1807 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1808 Register src = op->src()->as_register();
1809 Register dst = op->dst()->as_register();
1810 Register src_pos = op->src_pos()->as_register();
1811 Register dst_pos = op->dst_pos()->as_register();
1812 Register length = op->length()->as_register();
1813 Register tmp = op->tmp()->as_register();
1814 Register tmp2 = R0;
1815
1816 int flags = op->flags();
1817 ciArrayKlass* default_type = op->expected_type();
1818 BasicType basic_type = (default_type != nullptr) ? default_type->element_type()->basic_type() : T_ILLEGAL;
1819 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1820
1821 // Set up the arraycopy stub information.
1822 ArrayCopyStub* stub = op->stub();
1823
1824 // Always do stub if no type information is available. It's ok if
1825 // the known type isn't loaded since the code sanity checks
1826 // in debug mode and the type isn't required when we know the exact type
1827 // also check that the type is an array type.
1828 if (default_type == nullptr) {
1829 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1830 length->is_nonvolatile(), "must preserve");
1831 address copyfunc_addr = StubRoutines::generic_arraycopy();
1832 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
1833
1834 // 3 parms are int. Convert to long.
1835 __ mr(R3_ARG1, src);
1836 __ extsw(R4_ARG2, src_pos);
1837 __ mr(R5_ARG3, dst);
1838 __ extsw(R6_ARG4, dst_pos);
1839 __ extsw(R7_ARG5, length);
1840
1841 #ifndef PRODUCT
1842 if (PrintC1Statistics) {
1843 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1844 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1845 __ lwz(R11_scratch1, simm16_offs, tmp);
1846 __ addi(R11_scratch1, R11_scratch1, 1);
1847 __ stw(R11_scratch1, simm16_offs, tmp);
1848 }
1849 #endif
1850 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
1851
1852 __ nand(tmp, R3_RET, R3_RET);
1853 __ subf(length, tmp, length);
1854 __ add(src_pos, tmp, src_pos);
1855 __ add(dst_pos, tmp, dst_pos);
1856
1857 __ cmpwi(CR0, R3_RET, 0);
1858 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CR0, Assembler::less), *stub->entry());
1859 __ bind(*stub->continuation());
1860 return;
1861 }
1862
1863 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
1864 Label cont, slow, copyfunc;
1865
1866 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1867 LIR_OpArrayCopy::dst_null_check |
1868 LIR_OpArrayCopy::src_pos_positive_check |
1869 LIR_OpArrayCopy::dst_pos_positive_check |
1870 LIR_OpArrayCopy::length_positive_check);
1871
1872 // Use only one conditional branch for simple checks.
1873 if (simple_check_flag_set) {
1874 ConditionRegister combined_check = CR1, tmp_check = CR1;
1875
1876 // Make sure src and dst are non-null.
1877 if (flags & LIR_OpArrayCopy::src_null_check) {
1878 __ cmpdi(combined_check, src, 0);
1879 tmp_check = CR0;
1880 }
1881
1882 if (flags & LIR_OpArrayCopy::dst_null_check) {
1883 __ cmpdi(tmp_check, dst, 0);
1884 if (tmp_check != combined_check) {
1885 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1886 }
1887 tmp_check = CR0;
1888 }
1889
1890 // Clear combined_check.eq if not already used.
1891 if (tmp_check == combined_check) {
1892 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1893 tmp_check = CR0;
1894 }
1895
1896 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1897 // Test src_pos register.
1898 __ cmpwi(tmp_check, src_pos, 0);
1899 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1900 }
1901
1902 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1903 // Test dst_pos register.
1904 __ cmpwi(tmp_check, dst_pos, 0);
1905 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1906 }
1907
1908 if (flags & LIR_OpArrayCopy::length_positive_check) {
1909 // Make sure length isn't negative.
1910 __ cmpwi(tmp_check, length, 0);
1911 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1912 }
1913
1914 __ beq(combined_check, slow);
1915 }
1916
1917 // If the compiler was not able to prove that exact type of the source or the destination
1918 // of the arraycopy is an array type, check at runtime if the source or the destination is
1919 // an instance type.
1920 if (flags & LIR_OpArrayCopy::type_check) {
1921 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1922 __ load_klass(tmp, dst);
1923 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1924 __ cmpwi(CR0, tmp2, Klass::_lh_neutral_value);
1925 __ bge(CR0, slow);
1926 }
1927
1928 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1929 __ load_klass(tmp, src);
1930 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1931 __ cmpwi(CR0, tmp2, Klass::_lh_neutral_value);
1932 __ bge(CR0, slow);
1933 }
1934 }
1935
1936 // Higher 32bits must be null.
1937 __ extsw(length, length);
1938
1939 __ extsw(src_pos, src_pos);
1940 if (flags & LIR_OpArrayCopy::src_range_check) {
1941 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1942 __ add(tmp, length, src_pos);
1943 __ cmpld(CR0, tmp2, tmp);
1944 __ ble(CR0, slow);
1945 }
1946
1947 __ extsw(dst_pos, dst_pos);
1948 if (flags & LIR_OpArrayCopy::dst_range_check) {
1949 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1950 __ add(tmp, length, dst_pos);
1951 __ cmpld(CR0, tmp2, tmp);
1952 __ ble(CR0, slow);
1953 }
1954
1955 int shift = shift_amount(basic_type);
1956
1957 if (!(flags & LIR_OpArrayCopy::type_check)) {
1958 if (stub != nullptr) {
1959 __ b(cont);
1960 __ bind(slow);
1961 __ b(*stub->entry());
1962 }
1963 } else {
1964 // We don't know the array types are compatible.
1965 if (basic_type != T_OBJECT) {
1966 // Simple test for basic type arrays.
1967 __ cmp_klasses_from_objects(CR0, src, dst, tmp, tmp2);
1968 __ beq(CR0, cont);
1969 } else {
1970 // For object arrays, if src is a sub class of dst then we can
1971 // safely do the copy.
1972 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1973
1974 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
1975 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
1976
1977 __ load_klass(sub_klass, src);
1978 __ load_klass(super_klass, dst);
1979
1980 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
1981 &cont, copyfunc_addr != nullptr ? ©func : &slow, nullptr);
1982
1983 address slow_stc = Runtime1::entry_for(C1StubId::slow_subtype_check_id);
1984 //__ load_const_optimized(tmp, slow_stc, tmp2);
1985 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
1986 __ mtctr(tmp);
1987 __ bctrl(); // sets CR0
1988 __ beq(CR0, cont);
1989
1990 if (copyfunc_addr != nullptr) { // Use stub if available.
1991 __ bind(copyfunc);
1992 // Src is not a sub class of dst so we have to do a
1993 // per-element check.
1994 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
1995 if ((flags & mask) != mask) {
1996 assert(flags & mask, "one of the two should be known to be an object array");
1997
1998 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1999 __ load_klass(tmp, src);
2000 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2001 __ load_klass(tmp, dst);
2002 }
2003
2004 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2005
2006 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2007 __ load_const_optimized(tmp, objArray_lh);
2008 __ cmpw(CR0, tmp, tmp2);
2009 __ bne(CR0, slow);
2010 }
2011
2012 Register src_ptr = R3_ARG1;
2013 Register dst_ptr = R4_ARG2;
2014 Register len = R5_ARG3;
2015 Register chk_off = R6_ARG4;
2016 Register super_k = R7_ARG5;
2017
2018 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2019 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2020 if (shift == 0) {
2021 __ add(src_ptr, src_pos, src_ptr);
2022 __ add(dst_ptr, dst_pos, dst_ptr);
2023 } else {
2024 __ sldi(tmp, src_pos, shift);
2025 __ sldi(tmp2, dst_pos, shift);
2026 __ add(src_ptr, tmp, src_ptr);
2027 __ add(dst_ptr, tmp2, dst_ptr);
2028 }
2029
2030 __ load_klass(tmp, dst);
2031 __ mr(len, length);
2032
2033 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2034 __ ld(super_k, ek_offset, tmp);
2035
2036 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2037 __ lwz(chk_off, sco_offset, super_k);
2038
2039 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
2040
2041 #ifndef PRODUCT
2042 if (PrintC1Statistics) {
2043 Label failed;
2044 __ cmpwi(CR0, R3_RET, 0);
2045 __ bne(CR0, failed);
2046 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2047 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2048 __ lwz(R11_scratch1, simm16_offs, tmp);
2049 __ addi(R11_scratch1, R11_scratch1, 1);
2050 __ stw(R11_scratch1, simm16_offs, tmp);
2051 __ bind(failed);
2052 }
2053 #endif
2054
2055 __ nand(tmp, R3_RET, R3_RET);
2056 __ cmpwi(CR0, R3_RET, 0);
2057 __ beq(CR0, *stub->continuation());
2058
2059 #ifndef PRODUCT
2060 if (PrintC1Statistics) {
2061 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2062 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2063 __ lwz(R11_scratch1, simm16_offs, tmp);
2064 __ addi(R11_scratch1, R11_scratch1, 1);
2065 __ stw(R11_scratch1, simm16_offs, tmp);
2066 }
2067 #endif
2068
2069 __ subf(length, tmp, length);
2070 __ add(src_pos, tmp, src_pos);
2071 __ add(dst_pos, tmp, dst_pos);
2072 }
2073 }
2074 __ bind(slow);
2075 __ b(*stub->entry());
2076 }
2077 __ bind(cont);
2078
2079 #ifdef ASSERT
2080 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2081 // Sanity check the known type with the incoming class. For the
2082 // primitive case the types must match exactly with src.klass and
2083 // dst.klass each exactly matching the default type. For the
2084 // object array case, if no type check is needed then either the
2085 // dst type is exactly the expected type and the src type is a
2086 // subtype which we can't check or src is the same array as dst
2087 // but not necessarily exactly of type default_type.
2088 Label known_ok, halt;
2089 metadata2reg(default_type->constant_encoding(), tmp);
2090 __ cmp_klass(CR0, dst, tmp, R11_scratch1, R12_scratch2);
2091 if (basic_type != T_OBJECT) {
2092 __ bne(CR0, halt);
2093 __ cmp_klass(CR0, src, tmp, R11_scratch1, R12_scratch2);
2094 __ beq(CR0, known_ok);
2095 } else {
2096 __ beq(CR0, known_ok);
2097 __ cmpw(CR0, src, dst);
2098 __ beq(CR0, known_ok);
2099 }
2100 __ bind(halt);
2101 __ stop("incorrect type information in arraycopy");
2102 __ bind(known_ok);
2103 }
2104 #endif
2105
2106 #ifndef PRODUCT
2107 if (PrintC1Statistics) {
2108 address counter = Runtime1::arraycopy_count_address(basic_type);
2109 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2110 __ lwz(R11_scratch1, simm16_offs, tmp);
2111 __ addi(R11_scratch1, R11_scratch1, 1);
2112 __ stw(R11_scratch1, simm16_offs, tmp);
2113 }
2114 #endif
2115
2116 Register src_ptr = R3_ARG1;
2117 Register dst_ptr = R4_ARG2;
2118 Register len = R5_ARG3;
2119
2120 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2121 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2122 if (shift == 0) {
2123 __ add(src_ptr, src_pos, src_ptr);
2124 __ add(dst_ptr, dst_pos, dst_ptr);
2125 } else {
2126 __ sldi(tmp, src_pos, shift);
2127 __ sldi(tmp2, dst_pos, shift);
2128 __ add(src_ptr, tmp, src_ptr);
2129 __ add(dst_ptr, tmp2, dst_ptr);
2130 }
2131
2132 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2133 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2134 const char *name;
2135 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2136
2137 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2138 __ mr(len, length);
2139 __ call_c(entry, relocInfo::runtime_call_type);
2140
2141 if (stub != nullptr) {
2142 __ bind(*stub->continuation());
2143 }
2144 }
2145
2146
2147 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2148 if (dest->is_single_cpu()) {
2149 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2150 #ifdef _LP64
2151 if (left->type() == T_OBJECT) {
2152 switch (code) {
2153 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2154 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2155 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2156 default: ShouldNotReachHere();
2157 }
2158 } else
2159 #endif
2160 switch (code) {
2161 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2162 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2163 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2164 default: ShouldNotReachHere();
2165 }
2166 } else {
2167 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2168 switch (code) {
2169 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2170 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2171 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2172 default: ShouldNotReachHere();
2173 }
2174 }
2175 }
2176
2177
2178 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2179 #ifdef _LP64
2180 if (left->type() == T_OBJECT) {
2181 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2182 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2183 else {
2184 switch (code) {
2185 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2186 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2187 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2188 default: ShouldNotReachHere();
2189 }
2190 }
2191 return;
2192 }
2193 #endif
2194
2195 if (dest->is_single_cpu()) {
2196 count = count & 0x1F; // Java spec
2197 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2198 else {
2199 switch (code) {
2200 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2201 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2202 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2203 default: ShouldNotReachHere();
2204 }
2205 }
2206 } else if (dest->is_double_cpu()) {
2207 count = count & 63; // Java spec
2208 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2209 else {
2210 switch (code) {
2211 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2212 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2213 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2214 default: ShouldNotReachHere();
2215 }
2216 }
2217 } else {
2218 ShouldNotReachHere();
2219 }
2220 }
2221
2222
2223 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2224 if (op->init_check()) {
2225 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2226 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2227 } else {
2228 add_debug_info_for_null_check_here(op->stub()->info());
2229 }
2230 __ lbz(op->tmp1()->as_register(),
2231 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2232 // acquire barrier included in membar_storestore() which follows the allocation immediately.
2233 __ cmpwi(CR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2234 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CR0, Assembler::equal), *op->stub()->entry());
2235 }
2236 __ allocate_object(op->obj()->as_register(),
2237 op->tmp1()->as_register(),
2238 op->tmp2()->as_register(),
2239 op->tmp3()->as_register(),
2240 op->header_size(),
2241 op->object_size(),
2242 op->klass()->as_register(),
2243 *op->stub()->entry());
2244
2245 __ bind(*op->stub()->continuation());
2246 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2247 }
2248
2249
2250 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2251 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2252 if (UseSlowPath ||
2253 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2254 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2255 __ b(*op->stub()->entry());
2256 } else {
2257 __ allocate_array(op->obj()->as_register(),
2258 op->len()->as_register(),
2259 op->tmp1()->as_register(),
2260 op->tmp2()->as_register(),
2261 op->tmp3()->as_register(),
2262 arrayOopDesc::base_offset_in_bytes(op->type()),
2263 type2aelembytes(op->type()),
2264 op->klass()->as_register(),
2265 *op->stub()->entry(),
2266 op->zero_array());
2267 }
2268 __ bind(*op->stub()->continuation());
2269 }
2270
2271
2272 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2273 ciMethodData *md, ciProfileData *data,
2274 Register recv, Register tmp1, Label* update_done) {
2275 uint i;
2276 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2277 Label next_test;
2278 // See if the receiver is receiver[n].
2279 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2280 __ verify_klass_ptr(tmp1);
2281 __ cmpd(CR0, recv, tmp1);
2282 __ bne(CR0, next_test);
2283
2284 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2285 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2286 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2287 __ b(*update_done);
2288
2289 __ bind(next_test);
2290 }
2291
2292 // Didn't find receiver; find next empty slot and fill it in.
2293 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2294 Label next_test;
2295 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2296 __ cmpdi(CR0, tmp1, 0);
2297 __ bne(CR0, next_test);
2298 __ li(tmp1, DataLayout::counter_increment);
2299 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2300 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2301 __ b(*update_done);
2302
2303 __ bind(next_test);
2304 }
2305 }
2306
2307
2308 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2309 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2310 md = method->method_data_or_null();
2311 assert(md != nullptr, "Sanity");
2312 data = md->bci_to_data(bci);
2313 assert(data != nullptr, "need data for checkcast");
2314 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2315 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2316 // The offset is large so bias the mdo by the base of the slot so
2317 // that the ld can use simm16s to reference the slots of the data.
2318 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2319 }
2320 }
2321
2322
2323 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2324 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2325 Register k_RInfo = op->tmp1()->as_register();
2326 Register klass_RInfo = op->tmp2()->as_register();
2327 Register Rtmp1 = op->tmp3()->as_register();
2328 Register dst = op->result_opr()->as_register();
2329 ciKlass* k = op->klass();
2330 bool should_profile = op->should_profile();
2331 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2332 bool reg_conflict = false;
2333 if (obj == k_RInfo) {
2334 k_RInfo = dst;
2335 reg_conflict = true;
2336 } else if (obj == klass_RInfo) {
2337 klass_RInfo = dst;
2338 reg_conflict = true;
2339 } else if (obj == Rtmp1) {
2340 Rtmp1 = dst;
2341 reg_conflict = true;
2342 }
2343 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2344
2345 ciMethodData* md = nullptr;
2346 ciProfileData* data = nullptr;
2347 int mdo_offset_bias = 0;
2348 if (should_profile) {
2349 ciMethod* method = op->profiled_method();
2350 assert(method != nullptr, "Should have method");
2351 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2352
2353 Register mdo = k_RInfo;
2354 Register data_val = Rtmp1;
2355 Label not_null;
2356 metadata2reg(md->constant_encoding(), mdo);
2357 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2358 __ cmpdi(CR0, obj, 0);
2359 __ bne(CR0, not_null);
2360 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2361 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2362 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2363 __ b(*obj_is_null);
2364 __ bind(not_null);
2365
2366 Label update_done;
2367 Register recv = klass_RInfo;
2368 __ load_klass(recv, obj);
2369 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2370 const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2371 __ ld(Rtmp1, slot_offset, mdo);
2372 __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2373 __ std(Rtmp1, slot_offset, mdo);
2374 __ bind(update_done);
2375 } else {
2376 __ cmpdi(CR0, obj, 0);
2377 __ beq(CR0, *obj_is_null);
2378 }
2379
2380 // get object class
2381 __ load_klass(klass_RInfo, obj);
2382
2383 if (k->is_loaded()) {
2384 metadata2reg(k->constant_encoding(), k_RInfo);
2385 } else {
2386 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2387 }
2388
2389 if (op->fast_check()) {
2390 assert_different_registers(klass_RInfo, k_RInfo);
2391 __ cmpd(CR0, k_RInfo, klass_RInfo);
2392 __ beq(CR0, *success);
2393 // Fall through to failure case.
2394 } else {
2395 bool need_slow_path = true;
2396 if (k->is_loaded()) {
2397 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2398 need_slow_path = false;
2399 }
2400 // Perform the fast part of the checking logic.
2401 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success : nullptr),
2402 failure, nullptr, RegisterOrConstant(k->super_check_offset()));
2403 } else {
2404 // Perform the fast part of the checking logic.
2405 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success, failure);
2406 }
2407 if (!need_slow_path) {
2408 __ b(*success);
2409 } else {
2410 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2411 address entry = Runtime1::entry_for(C1StubId::slow_subtype_check_id);
2412 // Stub needs fixed registers (tmp1-3).
2413 Register original_k_RInfo = op->tmp1()->as_register();
2414 Register original_klass_RInfo = op->tmp2()->as_register();
2415 Register original_Rtmp1 = op->tmp3()->as_register();
2416 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2417 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2418 __ mr_if_needed(original_k_RInfo, k_RInfo);
2419 __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2420 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2421 //__ load_const_optimized(original_Rtmp1, entry, R0);
2422 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2423 __ mtctr(original_Rtmp1);
2424 __ bctrl(); // sets CR0
2425 if (keep_obj_alive) { __ mr(obj, dst); }
2426 __ beq(CR0, *success);
2427 // Fall through to failure case.
2428 }
2429 }
2430
2431 __ bind(*failure);
2432 }
2433
2434
2435 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2436 LIR_Code code = op->code();
2437 if (code == lir_store_check) {
2438 Register value = op->object()->as_register();
2439 Register array = op->array()->as_register();
2440 Register k_RInfo = op->tmp1()->as_register();
2441 Register klass_RInfo = op->tmp2()->as_register();
2442 Register Rtmp1 = op->tmp3()->as_register();
2443 bool should_profile = op->should_profile();
2444
2445 __ verify_oop(value, FILE_AND_LINE);
2446 CodeStub* stub = op->stub();
2447 // Check if it needs to be profiled.
2448 ciMethodData* md = nullptr;
2449 ciProfileData* data = nullptr;
2450 int mdo_offset_bias = 0;
2451 if (should_profile) {
2452 ciMethod* method = op->profiled_method();
2453 assert(method != nullptr, "Should have method");
2454 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2455 }
2456
2457 Label done;
2458
2459 if (should_profile) {
2460 Label not_null;
2461 Register mdo = k_RInfo;
2462 Register data_val = Rtmp1;
2463 metadata2reg(md->constant_encoding(), mdo);
2464 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2465 __ cmpdi(CR0, value, 0);
2466 __ bne(CR0, not_null);
2467 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2468 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2469 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2470 __ b(done);
2471 __ bind(not_null);
2472
2473 Label update_done;
2474 Register recv = klass_RInfo;
2475 __ load_klass(recv, value);
2476 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, &update_done);
2477 const int slot_offset = md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias;
2478 __ ld(Rtmp1, slot_offset, mdo);
2479 __ addi(Rtmp1, Rtmp1, DataLayout::counter_increment);
2480 __ std(Rtmp1, slot_offset, mdo);
2481 __ bind(update_done);
2482 } else {
2483 __ cmpdi(CR0, value, 0);
2484 __ beq(CR0, done);
2485 }
2486 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2487 explicit_null_check(array, op->info_for_exception());
2488 } else {
2489 add_debug_info_for_null_check_here(op->info_for_exception());
2490 }
2491 __ load_klass(k_RInfo, array);
2492 __ load_klass(klass_RInfo, value);
2493
2494 Label failure;
2495
2496 // Get instance klass.
2497 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2498 // Perform the fast part of the checking logic.
2499 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, &done, &failure, nullptr);
2500
2501 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2502 const address slow_path = Runtime1::entry_for(C1StubId::slow_subtype_check_id);
2503 //__ load_const_optimized(R0, slow_path);
2504 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2505 __ mtctr(R0);
2506 __ bctrl(); // sets CR0
2507 __ beq(CR0, done);
2508
2509 __ bind(failure);
2510 __ b(*stub->entry());
2511 __ align(32, 12);
2512 __ bind(done);
2513
2514 } else if (code == lir_checkcast) {
2515 Label success, failure;
2516 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2517 __ b(*op->stub()->entry());
2518 __ align(32, 12);
2519 __ bind(success);
2520 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2521 } else if (code == lir_instanceof) {
2522 Register dst = op->result_opr()->as_register();
2523 Label success, failure, done;
2524 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2525 __ li(dst, 0);
2526 __ b(done);
2527 __ align(32, 12);
2528 __ bind(success);
2529 __ li(dst, 1);
2530 __ bind(done);
2531 } else {
2532 ShouldNotReachHere();
2533 }
2534 }
2535
2536
2537 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2538 Register addr = op->addr()->as_pointer_register();
2539 Register cmp_value = noreg, new_value = noreg;
2540 bool is_64bit = false;
2541
2542 if (op->code() == lir_cas_long) {
2543 cmp_value = op->cmp_value()->as_register_lo();
2544 new_value = op->new_value()->as_register_lo();
2545 is_64bit = true;
2546 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2547 cmp_value = op->cmp_value()->as_register();
2548 new_value = op->new_value()->as_register();
2549 if (op->code() == lir_cas_obj) {
2550 if (UseCompressedOops) {
2551 Register t1 = op->tmp1()->as_register();
2552 Register t2 = op->tmp2()->as_register();
2553 cmp_value = __ encode_heap_oop(t1, cmp_value);
2554 new_value = __ encode_heap_oop(t2, new_value);
2555 } else {
2556 is_64bit = true;
2557 }
2558 }
2559 } else {
2560 Unimplemented();
2561 }
2562
2563 // There might be a volatile load before this Unsafe CAS.
2564 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2565 __ sync();
2566 } else {
2567 __ lwsync();
2568 }
2569
2570 if (is_64bit) {
2571 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2572 MacroAssembler::MemBarNone,
2573 MacroAssembler::cmpxchgx_hint_atomic_update(),
2574 noreg, nullptr, /*check without ldarx first*/true);
2575 } else {
2576 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2577 MacroAssembler::MemBarNone,
2578 MacroAssembler::cmpxchgx_hint_atomic_update(),
2579 noreg, nullptr, /*check without ldarx first*/true);
2580 }
2581
2582 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2583 __ isync();
2584 } else {
2585 __ sync();
2586 }
2587 }
2588
2589 void LIR_Assembler::breakpoint() {
2590 __ illtrap();
2591 }
2592
2593
2594 void LIR_Assembler::push(LIR_Opr opr) {
2595 Unimplemented();
2596 }
2597
2598 void LIR_Assembler::pop(LIR_Opr opr) {
2599 Unimplemented();
2600 }
2601
2602
2603 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2604 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2605 Register dst = dst_opr->as_register();
2606 Register reg = mon_addr.base();
2607 int offset = mon_addr.disp();
2608 // Compute pointer to BasicLock.
2609 __ add_const_optimized(dst, reg, offset);
2610 }
2611
2612
2613 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2614 Register obj = op->obj_opr()->as_register();
2615 Register hdr = op->hdr_opr()->as_register();
2616 Register lock = op->lock_opr()->as_register();
2617
2618 // Obj may not be an oop.
2619 if (op->code() == lir_lock) {
2620 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2621 if (LockingMode != LM_MONITOR) {
2622 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2623 // Add debug info for NullPointerException only if one is possible.
2624 if (op->info() != nullptr) {
2625 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2626 explicit_null_check(obj, op->info());
2627 } else {
2628 add_debug_info_for_null_check_here(op->info());
2629 }
2630 }
2631 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2632 } else {
2633 // always do slow locking
2634 // note: The slow locking code could be inlined here, however if we use
2635 // slow locking, speed doesn't matter anyway and this solution is
2636 // simpler and requires less duplicated code - additionally, the
2637 // slow locking code is the same in either case which simplifies
2638 // debugging.
2639 if (op->info() != nullptr) {
2640 add_debug_info_for_null_check_here(op->info());
2641 __ null_check(obj);
2642 }
2643 __ b(*op->stub()->entry());
2644 }
2645 } else {
2646 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2647 if (LockingMode != LM_MONITOR) {
2648 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2649 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2650 } else {
2651 // always do slow unlocking
2652 // note: The slow unlocking code could be inlined here, however if we use
2653 // slow unlocking, speed doesn't matter anyway and this solution is
2654 // simpler and requires less duplicated code - additionally, the
2655 // slow unlocking code is the same in either case which simplifies
2656 // debugging.
2657 __ b(*op->stub()->entry());
2658 }
2659 }
2660 __ bind(*op->stub()->continuation());
2661 }
2662
2663 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2664 Register obj = op->obj()->as_pointer_register();
2665 Register result = op->result_opr()->as_pointer_register();
2666
2667 CodeEmitInfo* info = op->info();
2668 if (info != nullptr) {
2669 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2670 explicit_null_check(obj, info);
2671 } else {
2672 add_debug_info_for_null_check_here(info);
2673 }
2674 }
2675
2676 __ load_klass(result, obj);
2677 }
2678
2679 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2680 ciMethod* method = op->profiled_method();
2681 int bci = op->profiled_bci();
2682 ciMethod* callee = op->profiled_callee();
2683
2684 // Update counter for all call types.
2685 ciMethodData* md = method->method_data_or_null();
2686 assert(md != nullptr, "Sanity");
2687 ciProfileData* data = md->bci_to_data(bci);
2688 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2689 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2690 Register mdo = op->mdo()->as_register();
2691 #ifdef _LP64
2692 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2693 Register tmp1 = op->tmp1()->as_register_lo();
2694 #else
2695 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2696 Register tmp1 = op->tmp1()->as_register();
2697 #endif
2698 metadata2reg(md->constant_encoding(), mdo);
2699 int mdo_offset_bias = 0;
2700 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2701 data->size_in_bytes())) {
2702 // The offset is large so bias the mdo by the base of the slot so
2703 // that the ld can use simm16s to reference the slots of the data.
2704 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2705 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2706 }
2707
2708 // Perform additional virtual call profiling for invokevirtual and
2709 // invokeinterface bytecodes
2710 if (op->should_profile_receiver_type()) {
2711 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2712 Register recv = op->recv()->as_register();
2713 assert_different_registers(mdo, tmp1, recv);
2714 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2715 ciKlass* known_klass = op->known_holder();
2716 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2717 // We know the type that will be seen at this call site; we can
2718 // statically update the MethodData* rather than needing to do
2719 // dynamic tests on the receiver type.
2720
2721 // NOTE: we should probably put a lock around this search to
2722 // avoid collisions by concurrent compilations.
2723 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2724 uint i;
2725 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2726 ciKlass* receiver = vc_data->receiver(i);
2727 if (known_klass->equals(receiver)) {
2728 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2729 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2730 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2731 return;
2732 }
2733 }
2734
2735 // Receiver type not found in profile data; select an empty slot.
2736
2737 // Note that this is less efficient than it should be because it
2738 // always does a write to the receiver part of the
2739 // VirtualCallData rather than just the first time.
2740 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2741 ciKlass* receiver = vc_data->receiver(i);
2742 if (receiver == nullptr) {
2743 metadata2reg(known_klass->constant_encoding(), tmp1);
2744 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2745
2746 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2747 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2748 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2749 return;
2750 }
2751 }
2752 } else {
2753 __ load_klass(recv, recv);
2754 Label update_done;
2755 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2756 // Receiver did not match any saved receiver and there is no empty row for it.
2757 // Increment total counter to indicate polymorphic case.
2758 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2759 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2760 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2761
2762 __ bind(update_done);
2763 }
2764 } else {
2765 // Static call
2766 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2767 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2768 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2769 }
2770 }
2771
2772
2773 void LIR_Assembler::align_backward_branch_target() {
2774 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2775 }
2776
2777
2778 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2779 Unimplemented();
2780 }
2781
2782
2783 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2784 // tmp must be unused
2785 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2786 assert(left->is_register(), "can only handle registers");
2787
2788 if (left->is_single_cpu()) {
2789 __ neg(dest->as_register(), left->as_register());
2790 } else if (left->is_single_fpu()) {
2791 __ fneg(dest->as_float_reg(), left->as_float_reg());
2792 } else if (left->is_double_fpu()) {
2793 __ fneg(dest->as_double_reg(), left->as_double_reg());
2794 } else {
2795 assert (left->is_double_cpu(), "Must be a long");
2796 __ neg(dest->as_register_lo(), left->as_register_lo());
2797 }
2798 }
2799
2800
2801 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2802 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2803 // Stubs: Called via rt_call, but dest is a stub address (no FunctionDescriptor).
2804 if (dest == Runtime1::entry_for(C1StubId::register_finalizer_id) ||
2805 dest == Runtime1::entry_for(C1StubId::new_multi_array_id ) ||
2806 dest == Runtime1::entry_for(C1StubId::is_instance_of_id )) {
2807 assert(CodeCache::contains(dest), "simplified call is only for special C1 stubs");
2808 //__ load_const_optimized(R0, dest);
2809 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2810 __ mtctr(R0);
2811 __ bctrl();
2812 if (info != nullptr) {
2813 add_call_info_here(info);
2814 __ post_call_nop();
2815 }
2816 return;
2817 }
2818
2819 __ call_c(dest, relocInfo::runtime_call_type);
2820 assert(__ last_calls_return_pc() == __ pc(), "pcn not at return pc");
2821 if (info != nullptr) {
2822 add_call_info_here(info);
2823 __ post_call_nop();
2824 }
2825 }
2826
2827
2828 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2829 ShouldNotReachHere(); // Not needed on _LP64.
2830 }
2831
2832 void LIR_Assembler::membar() {
2833 __ fence();
2834 }
2835
2836 void LIR_Assembler::membar_acquire() {
2837 __ acquire();
2838 }
2839
2840 void LIR_Assembler::membar_release() {
2841 __ release();
2842 }
2843
2844 void LIR_Assembler::membar_loadload() {
2845 __ membar(Assembler::LoadLoad);
2846 }
2847
2848 void LIR_Assembler::membar_storestore() {
2849 __ membar(Assembler::StoreStore);
2850 }
2851
2852 void LIR_Assembler::membar_loadstore() {
2853 __ membar(Assembler::LoadStore);
2854 }
2855
2856 void LIR_Assembler::membar_storeload() {
2857 __ membar(Assembler::StoreLoad);
2858 }
2859
2860 void LIR_Assembler::on_spin_wait() {
2861 Unimplemented();
2862 }
2863
2864 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2865 LIR_Address* addr = addr_opr->as_address_ptr();
2866 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2867
2868 if (addr->index()->is_illegal()) {
2869 if (patch_code != lir_patch_none) {
2870 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2871 __ load_const32(R0, 0); // patchable int
2872 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2873 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2874 } else {
2875 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2876 }
2877 } else {
2878 assert(patch_code == lir_patch_none, "Patch code not supported");
2879 assert(addr->disp() == 0, "can't have both: index and disp");
2880 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2881 }
2882 }
2883
2884
2885 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2886 ShouldNotReachHere();
2887 }
2888
2889
2890 #ifdef ASSERT
2891 // Emit run-time assertion.
2892 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2893 Unimplemented();
2894 }
2895 #endif
2896
2897
2898 void LIR_Assembler::peephole(LIR_List* lir) {
2899 // Optimize instruction pairs before emitting.
2900 LIR_OpList* inst = lir->instructions_list();
2901 for (int i = 1; i < inst->length(); i++) {
2902 LIR_Op* op = inst->at(i);
2903
2904 // 2 register-register-moves
2905 if (op->code() == lir_move) {
2906 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2907 res2 = ((LIR_Op1*)op)->result_opr();
2908 if (in2->is_register() && res2->is_register()) {
2909 LIR_Op* prev = inst->at(i - 1);
2910 if (prev && prev->code() == lir_move) {
2911 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2912 res1 = ((LIR_Op1*)prev)->result_opr();
2913 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2914 inst->remove_at(i);
2915 }
2916 }
2917 }
2918 }
2919
2920 }
2921 return;
2922 }
2923
2924
2925 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2926 const LIR_Address *addr = src->as_address_ptr();
2927 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2928 const Register Rptr = addr->base()->as_pointer_register(),
2929 Rtmp = tmp->as_register();
2930 Register Robj = noreg;
2931 if (data->is_oop()) {
2932 if (UseCompressedOops) {
2933 Robj = __ encode_heap_oop(Rtmp, data->as_register());
2934 } else {
2935 Robj = data->as_register();
2936 if (Robj == dest->as_register()) { // May happen with ZGC.
2937 __ mr(Rtmp, Robj);
2938 Robj = Rtmp;
2939 }
2940 }
2941 }
2942
2943 // There might be a volatile load before this Unsafe OP.
2944 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2945 __ sync();
2946 } else {
2947 __ lwsync();
2948 }
2949
2950 Label Lretry;
2951 __ bind(Lretry);
2952
2953 if (data->type() == T_INT) {
2954 const Register Rold = dest->as_register(),
2955 Rsrc = data->as_register();
2956 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2957 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2958 if (code == lir_xadd) {
2959 __ add(Rtmp, Rsrc, Rold);
2960 __ stwcx_(Rtmp, Rptr);
2961 } else {
2962 __ stwcx_(Rsrc, Rptr);
2963 }
2964 } else if (data->is_oop()) {
2965 assert(code == lir_xchg, "xadd for oops");
2966 const Register Rold = dest->as_register();
2967 assert_different_registers(Rptr, Rold, Robj);
2968 if (UseCompressedOops) {
2969 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2970 __ stwcx_(Robj, Rptr);
2971 } else {
2972 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2973 __ stdcx_(Robj, Rptr);
2974 }
2975 } else if (data->type() == T_LONG) {
2976 const Register Rold = dest->as_register_lo(),
2977 Rsrc = data->as_register_lo();
2978 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2979 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2980 if (code == lir_xadd) {
2981 __ add(Rtmp, Rsrc, Rold);
2982 __ stdcx_(Rtmp, Rptr);
2983 } else {
2984 __ stdcx_(Rsrc, Rptr);
2985 }
2986 } else {
2987 ShouldNotReachHere();
2988 }
2989
2990 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
2991 __ bne_predict_not_taken(CR0, Lretry);
2992 } else {
2993 __ bne( CR0, Lretry);
2994 }
2995
2996 if (UseCompressedOops && data->is_oop()) {
2997 __ decode_heap_oop(dest->as_register());
2998 }
2999
3000 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
3001 __ isync();
3002 } else {
3003 __ sync();
3004 }
3005 }
3006
3007
3008 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3009 Register obj = op->obj()->as_register();
3010 Register tmp = op->tmp()->as_pointer_register();
3011 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3012 ciKlass* exact_klass = op->exact_klass();
3013 intptr_t current_klass = op->current_klass();
3014 bool not_null = op->not_null();
3015 bool no_conflict = op->no_conflict();
3016
3017 Label Lupdate, Ldo_update, Ldone;
3018
3019 bool do_null = !not_null;
3020 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3021 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3022
3023 assert(do_null || do_update, "why are we here?");
3024 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3025
3026 __ verify_oop(obj, FILE_AND_LINE);
3027
3028 if (do_null) {
3029 if (!TypeEntries::was_null_seen(current_klass)) {
3030 __ cmpdi(CR0, obj, 0);
3031 __ bne(CR0, Lupdate);
3032 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3033 __ ori(R0, R0, TypeEntries::null_seen);
3034 if (do_update) {
3035 __ b(Ldo_update);
3036 } else {
3037 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3038 }
3039 } else {
3040 if (do_update) {
3041 __ cmpdi(CR0, obj, 0);
3042 __ beq(CR0, Ldone);
3043 }
3044 }
3045 #ifdef ASSERT
3046 } else {
3047 __ cmpdi(CR0, obj, 0);
3048 __ bne(CR0, Lupdate);
3049 __ stop("unexpected null obj");
3050 #endif
3051 }
3052
3053 __ bind(Lupdate);
3054 if (do_update) {
3055 Label Lnext;
3056 const Register klass = R29_TOC; // kill and reload
3057 bool klass_reg_used = false;
3058 #ifdef ASSERT
3059 if (exact_klass != nullptr) {
3060 Label ok;
3061 klass_reg_used = true;
3062 __ load_klass(klass, obj);
3063 metadata2reg(exact_klass->constant_encoding(), R0);
3064 __ cmpd(CR0, klass, R0);
3065 __ beq(CR0, ok);
3066 __ stop("exact klass and actual klass differ");
3067 __ bind(ok);
3068 }
3069 #endif
3070
3071 if (!no_conflict) {
3072 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3073 klass_reg_used = true;
3074 if (exact_klass != nullptr) {
3075 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3076 metadata2reg(exact_klass->constant_encoding(), klass);
3077 } else {
3078 __ load_klass(klass, obj);
3079 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3080 }
3081
3082 // Like InterpreterMacroAssembler::profile_obj_type
3083 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3084 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3085 __ cmpd(CR1, R0, klass);
3086 // Klass seen before, nothing to do (regardless of unknown bit).
3087 //beq(CR1, do_nothing);
3088
3089 __ andi_(R0, tmp, TypeEntries::type_unknown);
3090 // Already unknown. Nothing to do anymore.
3091 //bne(CR0, do_nothing);
3092 __ crorc(CR0, Assembler::equal, CR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3093 __ beq(CR0, Lnext);
3094
3095 if (TypeEntries::is_type_none(current_klass)) {
3096 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3097 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3098 __ beq(CR0, Ldo_update); // First time here. Set profile type.
3099 }
3100
3101 } else {
3102 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3103 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3104
3105 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3106 __ andi_(R0, tmp, TypeEntries::type_unknown);
3107 // Already unknown. Nothing to do anymore.
3108 __ bne(CR0, Lnext);
3109 }
3110
3111 // Different than before. Cannot keep accurate profile.
3112 __ ori(R0, tmp, TypeEntries::type_unknown);
3113 } else {
3114 // There's a single possible klass at this profile point
3115 assert(exact_klass != nullptr, "should be");
3116 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3117
3118 if (TypeEntries::is_type_none(current_klass)) {
3119 klass_reg_used = true;
3120 metadata2reg(exact_klass->constant_encoding(), klass);
3121
3122 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3123 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3124 __ cmpd(CR1, R0, klass);
3125 // Klass seen before, nothing to do (regardless of unknown bit).
3126 __ beq(CR1, Lnext);
3127 #ifdef ASSERT
3128 {
3129 Label ok;
3130 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3131 __ beq(CR0, ok); // First time here.
3132
3133 __ stop("unexpected profiling mismatch");
3134 __ bind(ok);
3135 }
3136 #endif
3137 // First time here. Set profile type.
3138 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3139 } else {
3140 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3141 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3142
3143 // Already unknown. Nothing to do anymore.
3144 __ andi_(R0, tmp, TypeEntries::type_unknown);
3145 __ bne(CR0, Lnext);
3146
3147 // Different than before. Cannot keep accurate profile.
3148 __ ori(R0, tmp, TypeEntries::type_unknown);
3149 }
3150 }
3151
3152 __ bind(Ldo_update);
3153 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3154
3155 __ bind(Lnext);
3156 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3157 }
3158 __ bind(Ldone);
3159 }
3160
3161
3162 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3163 assert(op->crc()->is_single_cpu(), "crc must be register");
3164 assert(op->val()->is_single_cpu(), "byte value must be register");
3165 assert(op->result_opr()->is_single_cpu(), "result must be register");
3166 Register crc = op->crc()->as_register();
3167 Register val = op->val()->as_register();
3168 Register res = op->result_opr()->as_register();
3169
3170 assert_different_registers(val, crc, res);
3171
3172 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3173 __ kernel_crc32_singleByteReg(crc, val, res, true);
3174 __ mr(res, crc);
3175 }
3176
3177 #undef __