1 /*
   2  * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2012, 2021 SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_MacroAssembler.hpp"
  31 #include "c1/c1_Runtime1.hpp"
  32 #include "c1/c1_ValueStack.hpp"
  33 #include "ci/ciArrayKlass.hpp"
  34 #include "ci/ciInstance.hpp"
  35 #include "gc/shared/collectedHeap.hpp"
  36 #include "memory/universe.hpp"
  37 #include "nativeInst_ppc.hpp"
  38 #include "oops/compressedOops.hpp"
  39 #include "oops/objArrayKlass.hpp"
  40 #include "runtime/frame.inline.hpp"
  41 #include "runtime/safepointMechanism.inline.hpp"
  42 #include "runtime/sharedRuntime.hpp"
  43 #include "runtime/stubRoutines.hpp"
  44 #include "runtime/vm_version.hpp"
  45 #include "utilities/powerOfTwo.hpp"
  46 
  47 #define __ _masm->
  48 
  49 
  50 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
  51 
  52 
  53 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
  54   Unimplemented(); return false; // Currently not used on this platform.
  55 }
  56 
  57 
  58 LIR_Opr LIR_Assembler::receiverOpr() {
  59   return FrameMap::R3_oop_opr;
  60 }
  61 
  62 
  63 LIR_Opr LIR_Assembler::osrBufferPointer() {
  64   return FrameMap::R3_opr;
  65 }
  66 
  67 
  68 // This specifies the stack pointer decrement needed to build the frame.
  69 int LIR_Assembler::initial_frame_size_in_bytes() const {
  70   return in_bytes(frame_map()->framesize_in_bytes());
  71 }
  72 
  73 
  74 // Inline cache check: the inline cached class is in inline_cache_reg;
  75 // we fetch the class of the receiver and compare it with the cached class.
  76 // If they do not match we jump to slow case.
  77 int LIR_Assembler::check_icache() {
  78   int offset = __ offset();
  79   __ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
  80   return offset;
  81 }
  82 
  83 void LIR_Assembler::clinit_barrier(ciMethod* method) {
  84   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
  85 
  86   Label L_skip_barrier;
  87   Register klass = R20;
  88 
  89   metadata2reg(method->holder()->constant_encoding(), klass);
  90   __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
  91 
  92   __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
  93   __ mtctr(klass);
  94   __ bctr();
  95 
  96   __ bind(L_skip_barrier);
  97 }
  98 
  99 void LIR_Assembler::osr_entry() {
 100   // On-stack-replacement entry sequence:
 101   //
 102   //   1. Create a new compiled activation.
 103   //   2. Initialize local variables in the compiled activation. The expression
 104   //      stack must be empty at the osr_bci; it is not initialized.
 105   //   3. Jump to the continuation address in compiled code to resume execution.
 106 
 107   // OSR entry point
 108   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 109   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 110   ValueStack* entry_state = osr_entry->end()->state();
 111   int number_of_locks = entry_state->locks_size();
 112 
 113   // Create a frame for the compiled activation.
 114   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 115 
 116   // OSR buffer is
 117   //
 118   // locals[nlocals-1..0]
 119   // monitors[number_of_locks-1..0]
 120   //
 121   // Locals is a direct copy of the interpreter frame so in the osr buffer
 122   // the first slot in the local array is the last local from the interpreter
 123   // and the last slot is local[0] (receiver) from the interpreter.
 124   //
 125   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 126   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 127   // in the interpreter frame (the method lock if a sync method).
 128 
 129   // Initialize monitors in the compiled activation.
 130   //   R3: pointer to osr buffer
 131   //
 132   // All other registers are dead at this point and the locals will be
 133   // copied into place by code emitted in the IR.
 134 
 135   Register OSR_buf = osrBufferPointer()->as_register();
 136   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 137     int monitor_offset = BytesPerWord * method()->max_locals() +
 138       (2 * BytesPerWord) * (number_of_locks - 1);
 139     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 140     // the OSR buffer using 2 word entries: first the lock and then
 141     // the oop.
 142     for (int i = 0; i < number_of_locks; i++) {
 143       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 144 #ifdef ASSERT
 145       // Verify the interpreter's monitor has a non-null object.
 146       {
 147         Label L;
 148         __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
 149         __ cmpdi(CCR0, R0, 0);
 150         __ bne(CCR0, L);
 151         __ stop("locked object is NULL");
 152         __ bind(L);
 153       }
 154 #endif // ASSERT
 155       // Copy the lock field into the compiled activation.
 156       Address ml = frame_map()->address_for_monitor_lock(i),
 157               mo = frame_map()->address_for_monitor_object(i);
 158       assert(ml.index() == noreg && mo.index() == noreg, "sanity");
 159       __ ld(R0, slot_offset + 0, OSR_buf);
 160       __ std(R0, ml.disp(), ml.base());
 161       __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
 162       __ std(R0, mo.disp(), mo.base());
 163     }
 164   }
 165 }
 166 
 167 
 168 int LIR_Assembler::emit_exception_handler() {
 169   // If the last instruction is a call (typically to do a throw which
 170   // is coming at the end after block reordering) the return address
 171   // must still point into the code area in order to avoid assertion
 172   // failures when searching for the corresponding bci => add a nop
 173   // (was bug 5/14/1999 - gri).
 174   __ nop();
 175 
 176   // Generate code for the exception handler.
 177   address handler_base = __ start_a_stub(exception_handler_size());
 178 
 179   if (handler_base == NULL) {
 180     // Not enough space left for the handler.
 181     bailout("exception handler overflow");
 182     return -1;
 183   }
 184 
 185   int offset = code_offset();
 186   address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
 187   //__ load_const_optimized(R0, entry_point);
 188   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
 189   __ mtctr(R0);
 190   __ bctr();
 191 
 192   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 193   __ end_a_stub();
 194 
 195   return offset;
 196 }
 197 
 198 
 199 // Emit the code to remove the frame from the stack in the exception
 200 // unwind path.
 201 int LIR_Assembler::emit_unwind_handler() {
 202   _masm->block_comment("Unwind handler");
 203 
 204   int offset = code_offset();
 205   bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
 206   const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
 207 
 208   // Fetch the exception from TLS and clear out exception related thread state.
 209   __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
 210   __ li(R0, 0);
 211   __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
 212   __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
 213 
 214   __ bind(_unwind_handler_entry);
 215   __ verify_not_null_oop(Rexception);
 216   if (preserve_exception) { __ mr(Rexception_save, Rexception); }
 217 
 218   // Perform needed unlocking
 219   MonitorExitStub* stub = NULL;
 220   if (method()->is_synchronized()) {
 221     monitor_address(0, FrameMap::R4_opr);
 222     stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
 223     __ unlock_object(R5, R6, R4, *stub->entry());
 224     __ bind(*stub->continuation());
 225   }
 226 
 227   if (compilation()->env()->dtrace_method_probes()) {
 228     Unimplemented();
 229   }
 230 
 231   // Dispatch to the unwind logic.
 232   address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
 233   //__ load_const_optimized(R0, unwind_stub);
 234   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
 235   if (preserve_exception) { __ mr(Rexception, Rexception_save); }
 236   __ mtctr(R0);
 237   __ bctr();
 238 
 239   // Emit the slow path assembly.
 240   if (stub != NULL) {
 241     stub->emit_code(this);
 242   }
 243 
 244   return offset;
 245 }
 246 
 247 
 248 int LIR_Assembler::emit_deopt_handler() {
 249   // If the last instruction is a call (typically to do a throw which
 250   // is coming at the end after block reordering) the return address
 251   // must still point into the code area in order to avoid assertion
 252   // failures when searching for the corresponding bci => add a nop
 253   // (was bug 5/14/1999 - gri).
 254   __ nop();
 255 
 256   // Generate code for deopt handler.
 257   address handler_base = __ start_a_stub(deopt_handler_size());
 258 
 259   if (handler_base == NULL) {
 260     // Not enough space left for the handler.
 261     bailout("deopt handler overflow");
 262     return -1;
 263   }
 264 
 265   int offset = code_offset();
 266   __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
 267 
 268   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 269   __ end_a_stub();
 270 
 271   return offset;
 272 }
 273 
 274 
 275 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 276   if (o == NULL) {
 277     __ li(reg, 0);
 278   } else {
 279     AddressLiteral addrlit = __ constant_oop_address(o);
 280     __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
 281   }
 282 }
 283 
 284 
 285 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 286   // Allocate a new index in table to hold the object once it's been patched.
 287   int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
 288   PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
 289 
 290   AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index));
 291   __ load_const(reg, addrlit, R0);
 292 
 293   patching_epilog(patch, lir_patch_normal, reg, info);
 294 }
 295 
 296 
 297 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
 298   AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
 299   __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
 300 }
 301 
 302 
 303 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
 304   // Allocate a new index in table to hold the klass once it's been patched.
 305   int index = __ oop_recorder()->allocate_metadata_index(NULL);
 306   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
 307 
 308   AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
 309   assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
 310   __ load_const(reg, addrlit, R0);
 311 
 312   patching_epilog(patch, lir_patch_normal, reg, info);
 313 }
 314 
 315 
 316 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
 317   const bool is_int = result->is_single_cpu();
 318   Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
 319   Register Rdivisor  = noreg;
 320   Register Rscratch  = temp->as_register();
 321   Register Rresult   = is_int ? result->as_register() : result->as_register_lo();
 322   long divisor = -1;
 323 
 324   if (right->is_register()) {
 325     Rdivisor = is_int ? right->as_register() : right->as_register_lo();
 326   } else {
 327     divisor = is_int ? right->as_constant_ptr()->as_jint()
 328                      : right->as_constant_ptr()->as_jlong();
 329   }
 330 
 331   assert(Rdividend != Rscratch, "");
 332   assert(Rdivisor  != Rscratch, "");
 333   assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
 334 
 335   if (Rdivisor == noreg) {
 336     if (divisor == 1) { // stupid, but can happen
 337       if (code == lir_idiv) {
 338         __ mr_if_needed(Rresult, Rdividend);
 339       } else {
 340         __ li(Rresult, 0);
 341       }
 342 
 343     } else if (is_power_of_2(divisor)) {
 344       // Convert division by a power of two into some shifts and logical operations.
 345       int log2 = log2i_exact(divisor);
 346 
 347       // Round towards 0.
 348       if (divisor == 2) {
 349         if (is_int) {
 350           __ srwi(Rscratch, Rdividend, 31);
 351         } else {
 352           __ srdi(Rscratch, Rdividend, 63);
 353         }
 354       } else {
 355         if (is_int) {
 356           __ srawi(Rscratch, Rdividend, 31);
 357         } else {
 358           __ sradi(Rscratch, Rdividend, 63);
 359         }
 360         __ clrldi(Rscratch, Rscratch, 64-log2);
 361       }
 362       __ add(Rscratch, Rdividend, Rscratch);
 363 
 364       if (code == lir_idiv) {
 365         if (is_int) {
 366           __ srawi(Rresult, Rscratch, log2);
 367         } else {
 368           __ sradi(Rresult, Rscratch, log2);
 369         }
 370       } else { // lir_irem
 371         __ clrrdi(Rscratch, Rscratch, log2);
 372         __ sub(Rresult, Rdividend, Rscratch);
 373       }
 374 
 375     } else if (divisor == -1) {
 376       if (code == lir_idiv) {
 377         __ neg(Rresult, Rdividend);
 378       } else {
 379         __ li(Rresult, 0);
 380       }
 381 
 382     } else {
 383       __ load_const_optimized(Rscratch, divisor);
 384       if (code == lir_idiv) {
 385         if (is_int) {
 386           __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
 387         } else {
 388           __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
 389         }
 390       } else {
 391         assert(Rscratch != R0, "need both");
 392         if (is_int) {
 393           __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
 394           __ mullw(Rscratch, R0, Rscratch);
 395         } else {
 396           __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
 397           __ mulld(Rscratch, R0, Rscratch);
 398         }
 399         __ sub(Rresult, Rdividend, Rscratch);
 400       }
 401 
 402     }
 403     return;
 404   }
 405 
 406   Label regular, done;
 407   if (is_int) {
 408     __ cmpwi(CCR0, Rdivisor, -1);
 409   } else {
 410     __ cmpdi(CCR0, Rdivisor, -1);
 411   }
 412   __ bne(CCR0, regular);
 413   if (code == lir_idiv) {
 414     __ neg(Rresult, Rdividend);
 415     __ b(done);
 416     __ bind(regular);
 417     if (is_int) {
 418       __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
 419     } else {
 420       __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
 421     }
 422   } else { // lir_irem
 423     __ li(Rresult, 0);
 424     __ b(done);
 425     __ bind(regular);
 426     if (is_int) {
 427       __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
 428       __ mullw(Rscratch, Rscratch, Rdivisor);
 429     } else {
 430       __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
 431       __ mulld(Rscratch, Rscratch, Rdivisor);
 432     }
 433     __ sub(Rresult, Rdividend, Rscratch);
 434   }
 435   __ bind(done);
 436 }
 437 
 438 
 439 void LIR_Assembler::emit_op3(LIR_Op3* op) {
 440   switch (op->code()) {
 441   case lir_idiv:
 442   case lir_irem:
 443     arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
 444                     op->result_opr(), op->info());
 445     break;
 446   case lir_fmad:
 447     __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
 448              op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
 449     break;
 450   case lir_fmaf:
 451     __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
 452               op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
 453     break;
 454   default: ShouldNotReachHere(); break;
 455   }
 456 }
 457 
 458 
 459 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
 460 #ifdef ASSERT
 461   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
 462   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
 463   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
 464   assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
 465 #endif
 466 
 467   Label *L = op->label();
 468   if (op->cond() == lir_cond_always) {
 469     __ b(*L);
 470   } else {
 471     Label done;
 472     bool is_unordered = false;
 473     if (op->code() == lir_cond_float_branch) {
 474       assert(op->ublock() != NULL, "must have unordered successor");
 475       is_unordered = true;
 476     } else {
 477       assert(op->code() == lir_branch, "just checking");
 478     }
 479 
 480     bool positive = false;
 481     Assembler::Condition cond = Assembler::equal;
 482     switch (op->cond()) {
 483       case lir_cond_equal:        positive = true ; cond = Assembler::equal  ; is_unordered = false; break;
 484       case lir_cond_notEqual:     positive = false; cond = Assembler::equal  ; is_unordered = false; break;
 485       case lir_cond_less:         positive = true ; cond = Assembler::less   ; break;
 486       case lir_cond_belowEqual:   assert(op->code() != lir_cond_float_branch, ""); // fallthru
 487       case lir_cond_lessEqual:    positive = false; cond = Assembler::greater; break;
 488       case lir_cond_greater:      positive = true ; cond = Assembler::greater; break;
 489       case lir_cond_aboveEqual:   assert(op->code() != lir_cond_float_branch, ""); // fallthru
 490       case lir_cond_greaterEqual: positive = false; cond = Assembler::less   ; break;
 491       default:                    ShouldNotReachHere();
 492     }
 493     int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
 494     int bi = Assembler::bi0(BOOL_RESULT, cond);
 495     if (is_unordered) {
 496       if (positive) {
 497         if (op->ublock() == op->block()) {
 498           __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
 499         }
 500       } else {
 501         if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
 502       }
 503     }
 504     __ bc_far_optimized(bo, bi, *L);
 505     __ bind(done);
 506   }
 507 }
 508 
 509 
 510 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
 511   Bytecodes::Code code = op->bytecode();
 512   LIR_Opr src = op->in_opr(),
 513           dst = op->result_opr();
 514 
 515   switch(code) {
 516     case Bytecodes::_i2l: {
 517       __ extsw(dst->as_register_lo(), src->as_register());
 518       break;
 519     }
 520     case Bytecodes::_l2i: {
 521       __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
 522       break;
 523     }
 524     case Bytecodes::_i2b: {
 525       __ extsb(dst->as_register(), src->as_register());
 526       break;
 527     }
 528     case Bytecodes::_i2c: {
 529       __ clrldi(dst->as_register(), src->as_register(), 64-16);
 530       break;
 531     }
 532     case Bytecodes::_i2s: {
 533       __ extsh(dst->as_register(), src->as_register());
 534       break;
 535     }
 536     case Bytecodes::_i2d:
 537     case Bytecodes::_l2d: {
 538       bool src_in_memory = !VM_Version::has_mtfprd();
 539       FloatRegister rdst = dst->as_double_reg();
 540       FloatRegister rsrc;
 541       if (src_in_memory) {
 542         rsrc = src->as_double_reg(); // via mem
 543       } else {
 544         // move src to dst register
 545         if (code == Bytecodes::_i2d) {
 546           __ mtfprwa(rdst, src->as_register());
 547         } else {
 548           __ mtfprd(rdst, src->as_register_lo());
 549         }
 550         rsrc = rdst;
 551       }
 552       __ fcfid(rdst, rsrc);
 553       break;
 554     }
 555     case Bytecodes::_i2f:
 556     case Bytecodes::_l2f: {
 557       bool src_in_memory = !VM_Version::has_mtfprd();
 558       FloatRegister rdst = dst->as_float_reg();
 559       FloatRegister rsrc;
 560       if (src_in_memory) {
 561         rsrc = src->as_double_reg(); // via mem
 562       } else {
 563         // move src to dst register
 564         if (code == Bytecodes::_i2f) {
 565           __ mtfprwa(rdst, src->as_register());
 566         } else {
 567           __ mtfprd(rdst, src->as_register_lo());
 568         }
 569         rsrc = rdst;
 570       }
 571       if (VM_Version::has_fcfids()) {
 572         __ fcfids(rdst, rsrc);
 573       } else {
 574         assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
 575         __ fcfid(rdst, rsrc);
 576         __ frsp(rdst, rdst);
 577       }
 578       break;
 579     }
 580     case Bytecodes::_f2d: {
 581       __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
 582       break;
 583     }
 584     case Bytecodes::_d2f: {
 585       __ frsp(dst->as_float_reg(), src->as_double_reg());
 586       break;
 587     }
 588     case Bytecodes::_d2i:
 589     case Bytecodes::_f2i: {
 590       bool dst_in_memory = !VM_Version::has_mtfprd();
 591       FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
 592       Address       addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
 593       Label L;
 594       // Result must be 0 if value is NaN; test by comparing value to itself.
 595       __ fcmpu(CCR0, rsrc, rsrc);
 596       if (dst_in_memory) {
 597         __ li(R0, 0); // 0 in case of NAN
 598         __ std(R0, addr.disp(), addr.base());
 599       } else {
 600         __ li(dst->as_register(), 0);
 601       }
 602       __ bso(CCR0, L);
 603       __ fctiwz(rsrc, rsrc); // USE_KILL
 604       if (dst_in_memory) {
 605         __ stfd(rsrc, addr.disp(), addr.base());
 606       } else {
 607         __ mffprd(dst->as_register(), rsrc);
 608       }
 609       __ bind(L);
 610       break;
 611     }
 612     case Bytecodes::_d2l:
 613     case Bytecodes::_f2l: {
 614       bool dst_in_memory = !VM_Version::has_mtfprd();
 615       FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
 616       Address       addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
 617       Label L;
 618       // Result must be 0 if value is NaN; test by comparing value to itself.
 619       __ fcmpu(CCR0, rsrc, rsrc);
 620       if (dst_in_memory) {
 621         __ li(R0, 0); // 0 in case of NAN
 622         __ std(R0, addr.disp(), addr.base());
 623       } else {
 624         __ li(dst->as_register_lo(), 0);
 625       }
 626       __ bso(CCR0, L);
 627       __ fctidz(rsrc, rsrc); // USE_KILL
 628       if (dst_in_memory) {
 629         __ stfd(rsrc, addr.disp(), addr.base());
 630       } else {
 631         __ mffprd(dst->as_register_lo(), rsrc);
 632       }
 633       __ bind(L);
 634       break;
 635     }
 636 
 637     default: ShouldNotReachHere();
 638   }
 639 }
 640 
 641 
 642 void LIR_Assembler::align_call(LIR_Code) {
 643   // do nothing since all instructions are word aligned on ppc
 644 }
 645 
 646 
 647 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
 648   int start_offset = __ offset();
 649   // Put the entry point as a constant into the constant pool.
 650   const address entry_point_toc_addr   = __ address_constant(target, RelocationHolder::none);
 651   if (entry_point_toc_addr == NULL) {
 652     bailout("const section overflow");
 653     return false;
 654   }
 655   const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
 656 
 657   // Emit the trampoline stub which will be related to the branch-and-link below.
 658   address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
 659   if (!stub) {
 660     bailout("no space for trampoline stub");
 661     return false;
 662   }
 663   return true;
 664 }
 665 
 666 
 667 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 668   assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
 669 
 670   bool success = emit_trampoline_stub_for_call(op->addr());
 671   if (!success) { return; }
 672 
 673   __ relocate(rtype);
 674   // Note: At this point we do not have the address of the trampoline
 675   // stub, and the entry point might be too far away for bl, so __ pc()
 676   // serves as dummy and the bl will be patched later.
 677   __ code()->set_insts_mark();
 678   __ bl(__ pc());
 679   add_call_info(code_offset(), op->info());
 680 }
 681 
 682 
 683 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 684   __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
 685 
 686   // Virtual call relocation will point to ic load.
 687   address virtual_call_meta_addr = __ pc();
 688   // Load a clear inline cache.
 689   AddressLiteral empty_ic((address) Universe::non_oop_word());
 690   bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
 691   if (!success) {
 692     bailout("const section overflow");
 693     return;
 694   }
 695   // Call to fixup routine. Fixup routine uses ScopeDesc info
 696   // to determine who we intended to call.
 697   __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
 698 
 699   success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
 700   if (!success) { return; }
 701 
 702   // Note: At this point we do not have the address of the trampoline
 703   // stub, and the entry point might be too far away for bl, so __ pc()
 704   // serves as dummy and the bl will be patched later.
 705   __ bl(__ pc());
 706   add_call_info(code_offset(), op->info());
 707 }
 708 
 709 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
 710   ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
 711   __ null_check(addr, stub->entry());
 712   append_code_stub(stub);
 713 }
 714 
 715 
 716 // Attention: caller must encode oop if needed
 717 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
 718   int store_offset;
 719   if (!Assembler::is_simm16(offset)) {
 720     // For offsets larger than a simm16 we setup the offset.
 721     assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
 722     __ load_const_optimized(R0, offset);
 723     store_offset = store(from_reg, base, R0, type, wide);
 724   } else {
 725     store_offset = code_offset();
 726     switch (type) {
 727       case T_BOOLEAN: // fall through
 728       case T_BYTE  : __ stb(from_reg->as_register(), offset, base); break;
 729       case T_CHAR  :
 730       case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
 731       case T_INT   : __ stw(from_reg->as_register(), offset, base); break;
 732       case T_LONG  : __ std(from_reg->as_register_lo(), offset, base); break;
 733       case T_ADDRESS:
 734       case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
 735       case T_ARRAY : // fall through
 736       case T_OBJECT:
 737         {
 738           if (UseCompressedOops && !wide) {
 739             // Encoding done in caller
 740             __ stw(from_reg->as_register(), offset, base);
 741             __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
 742           } else {
 743             __ std(from_reg->as_register(), offset, base);
 744             __ verify_oop(from_reg->as_register(), FILE_AND_LINE);
 745           }
 746           break;
 747         }
 748       case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
 749       case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
 750       default      : ShouldNotReachHere();
 751     }
 752   }
 753   return store_offset;
 754 }
 755 
 756 
 757 // Attention: caller must encode oop if needed
 758 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
 759   int store_offset = code_offset();
 760   switch (type) {
 761     case T_BOOLEAN: // fall through
 762     case T_BYTE  : __ stbx(from_reg->as_register(), base, disp); break;
 763     case T_CHAR  :
 764     case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
 765     case T_INT   : __ stwx(from_reg->as_register(), base, disp); break;
 766     case T_LONG  :
 767 #ifdef _LP64
 768       __ stdx(from_reg->as_register_lo(), base, disp);
 769 #else
 770       Unimplemented();
 771 #endif
 772       break;
 773     case T_ADDRESS:
 774       __ stdx(from_reg->as_register(), base, disp);
 775       break;
 776     case T_ARRAY : // fall through
 777     case T_OBJECT:
 778       {
 779         if (UseCompressedOops && !wide) {
 780           // Encoding done in caller.
 781           __ stwx(from_reg->as_register(), base, disp);
 782           __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
 783         } else {
 784           __ stdx(from_reg->as_register(), base, disp);
 785           __ verify_oop(from_reg->as_register(), FILE_AND_LINE); // kills R0
 786         }
 787         break;
 788       }
 789     case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
 790     case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
 791     default      : ShouldNotReachHere();
 792   }
 793   return store_offset;
 794 }
 795 
 796 
 797 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
 798   int load_offset;
 799   if (!Assembler::is_simm16(offset)) {
 800     // For offsets larger than a simm16 we setup the offset.
 801     __ load_const_optimized(R0, offset);
 802     load_offset = load(base, R0, to_reg, type, wide);
 803   } else {
 804     load_offset = code_offset();
 805     switch(type) {
 806       case T_BOOLEAN: // fall through
 807       case T_BYTE  :   __ lbz(to_reg->as_register(), offset, base);
 808                        __ extsb(to_reg->as_register(), to_reg->as_register()); break;
 809       case T_CHAR  :   __ lhz(to_reg->as_register(), offset, base); break;
 810       case T_SHORT :   __ lha(to_reg->as_register(), offset, base); break;
 811       case T_INT   :   __ lwa(to_reg->as_register(), offset, base); break;
 812       case T_LONG  :   __ ld(to_reg->as_register_lo(), offset, base); break;
 813       case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
 814       case T_ADDRESS:
 815         if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
 816           __ lwz(to_reg->as_register(), offset, base);
 817           __ decode_klass_not_null(to_reg->as_register());
 818         } else {
 819           __ ld(to_reg->as_register(), offset, base);
 820         }
 821         break;
 822       case T_ARRAY : // fall through
 823       case T_OBJECT:
 824         {
 825           if (UseCompressedOops && !wide) {
 826             __ lwz(to_reg->as_register(), offset, base);
 827             __ decode_heap_oop(to_reg->as_register());
 828           } else {
 829             __ ld(to_reg->as_register(), offset, base);
 830           }
 831           __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
 832           break;
 833         }
 834       case T_FLOAT:  __ lfs(to_reg->as_float_reg(), offset, base); break;
 835       case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
 836       default      : ShouldNotReachHere();
 837     }
 838   }
 839   return load_offset;
 840 }
 841 
 842 
 843 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
 844   int load_offset = code_offset();
 845   switch(type) {
 846     case T_BOOLEAN: // fall through
 847     case T_BYTE  :  __ lbzx(to_reg->as_register(), base, disp);
 848                     __ extsb(to_reg->as_register(), to_reg->as_register()); break;
 849     case T_CHAR  :  __ lhzx(to_reg->as_register(), base, disp); break;
 850     case T_SHORT :  __ lhax(to_reg->as_register(), base, disp); break;
 851     case T_INT   :  __ lwax(to_reg->as_register(), base, disp); break;
 852     case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
 853     case T_ARRAY : // fall through
 854     case T_OBJECT:
 855       {
 856         if (UseCompressedOops && !wide) {
 857           __ lwzx(to_reg->as_register(), base, disp);
 858           __ decode_heap_oop(to_reg->as_register());
 859         } else {
 860           __ ldx(to_reg->as_register(), base, disp);
 861         }
 862         __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
 863         break;
 864       }
 865     case T_FLOAT:  __ lfsx(to_reg->as_float_reg() , base, disp); break;
 866     case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
 867     case T_LONG  :
 868 #ifdef _LP64
 869       __ ldx(to_reg->as_register_lo(), base, disp);
 870 #else
 871       Unimplemented();
 872 #endif
 873       break;
 874     default      : ShouldNotReachHere();
 875   }
 876   return load_offset;
 877 }
 878 
 879 
 880 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 881   LIR_Const* c = src->as_constant_ptr();
 882   Register src_reg = R0;
 883   switch (c->type()) {
 884     case T_INT:
 885     case T_FLOAT: {
 886       int value = c->as_jint_bits();
 887       __ load_const_optimized(src_reg, value);
 888       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 889       __ stw(src_reg, addr.disp(), addr.base());
 890       break;
 891     }
 892     case T_ADDRESS: {
 893       int value = c->as_jint_bits();
 894       __ load_const_optimized(src_reg, value);
 895       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 896       __ std(src_reg, addr.disp(), addr.base());
 897       break;
 898     }
 899     case T_OBJECT: {
 900       jobject2reg(c->as_jobject(), src_reg);
 901       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 902       __ std(src_reg, addr.disp(), addr.base());
 903       break;
 904     }
 905     case T_LONG:
 906     case T_DOUBLE: {
 907       int value = c->as_jlong_bits();
 908       __ load_const_optimized(src_reg, value);
 909       Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
 910       __ std(src_reg, addr.disp(), addr.base());
 911       break;
 912     }
 913     default:
 914       Unimplemented();
 915   }
 916 }
 917 
 918 
 919 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 920   LIR_Const* c = src->as_constant_ptr();
 921   LIR_Address* addr = dest->as_address_ptr();
 922   Register base = addr->base()->as_pointer_register();
 923   LIR_Opr tmp = LIR_OprFact::illegalOpr;
 924   int offset = -1;
 925   // Null check for large offsets in LIRGenerator::do_StoreField.
 926   bool needs_explicit_null_check = !ImplicitNullChecks;
 927 
 928   if (info != NULL && needs_explicit_null_check) {
 929     explicit_null_check(base, info);
 930   }
 931 
 932   switch (c->type()) {
 933     case T_FLOAT: type = T_INT;
 934     case T_INT:
 935     case T_ADDRESS: {
 936       tmp = FrameMap::R0_opr;
 937       __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
 938       break;
 939     }
 940     case T_DOUBLE: type = T_LONG;
 941     case T_LONG: {
 942       tmp = FrameMap::R0_long_opr;
 943       __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
 944       break;
 945     }
 946     case T_OBJECT: {
 947       tmp = FrameMap::R0_opr;
 948       if (UseCompressedOops && !wide && c->as_jobject() != NULL) {
 949         AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
 950         __ lis(R0, oop_addr.value() >> 16); // Don't care about sign extend (will use stw).
 951         __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
 952         __ ori(R0, R0, oop_addr.value() & 0xffff);
 953       } else {
 954         jobject2reg(c->as_jobject(), R0);
 955       }
 956       break;
 957     }
 958     default:
 959       Unimplemented();
 960   }
 961 
 962   // Handle either reg+reg or reg+disp address.
 963   if (addr->index()->is_valid()) {
 964     assert(addr->disp() == 0, "must be zero");
 965     offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
 966   } else {
 967     assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
 968     offset = store(tmp, base, addr->disp(), type, wide);
 969   }
 970 
 971   if (info != NULL) {
 972     assert(offset != -1, "offset should've been set");
 973     if (!needs_explicit_null_check) {
 974       add_debug_info_for_null_check(offset, info);
 975     }
 976   }
 977 }
 978 
 979 
 980 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 981   LIR_Const* c = src->as_constant_ptr();
 982   LIR_Opr to_reg = dest;
 983 
 984   switch (c->type()) {
 985     case T_INT: {
 986       assert(patch_code == lir_patch_none, "no patching handled here");
 987       __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
 988       break;
 989     }
 990     case T_ADDRESS: {
 991       assert(patch_code == lir_patch_none, "no patching handled here");
 992       __ load_const_optimized(dest->as_register(), c->as_jint(), R0);  // Yes, as_jint ...
 993       break;
 994     }
 995     case T_LONG: {
 996       assert(patch_code == lir_patch_none, "no patching handled here");
 997       __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
 998       break;
 999     }
1000 
1001     case T_OBJECT: {
1002       if (patch_code == lir_patch_none) {
1003         jobject2reg(c->as_jobject(), to_reg->as_register());
1004       } else {
1005         jobject2reg_with_patching(to_reg->as_register(), info);
1006       }
1007       break;
1008     }
1009 
1010     case T_METADATA:
1011       {
1012         if (patch_code == lir_patch_none) {
1013           metadata2reg(c->as_metadata(), to_reg->as_register());
1014         } else {
1015           klass2reg_with_patching(to_reg->as_register(), info);
1016         }
1017       }
1018       break;
1019 
1020     case T_FLOAT:
1021       {
1022         if (to_reg->is_single_fpu()) {
1023           address const_addr = __ float_constant(c->as_jfloat());
1024           if (const_addr == NULL) {
1025             bailout("const section overflow");
1026             break;
1027           }
1028           RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1029           __ relocate(rspec);
1030           __ load_const(R0, const_addr);
1031           __ lfsx(to_reg->as_float_reg(), R0);
1032         } else {
1033           assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1034           __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1035         }
1036       }
1037       break;
1038 
1039     case T_DOUBLE:
1040       {
1041         if (to_reg->is_double_fpu()) {
1042           address const_addr = __ double_constant(c->as_jdouble());
1043           if (const_addr == NULL) {
1044             bailout("const section overflow");
1045             break;
1046           }
1047           RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1048           __ relocate(rspec);
1049           __ load_const(R0, const_addr);
1050           __ lfdx(to_reg->as_double_reg(), R0);
1051         } else {
1052           assert(to_reg->is_double_cpu(), "Must be a long register.");
1053           __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1054         }
1055       }
1056       break;
1057 
1058     default:
1059       ShouldNotReachHere();
1060   }
1061 }
1062 
1063 
1064 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1065   Unimplemented(); return Address();
1066 }
1067 
1068 
1069 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1070   if (addr->index()->is_illegal()) {
1071     return (RegisterOrConstant)(addr->disp());
1072   } else {
1073     return (RegisterOrConstant)(addr->index()->as_pointer_register());
1074   }
1075 }
1076 
1077 
1078 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1079   const Register tmp = R0;
1080   switch (type) {
1081     case T_INT:
1082     case T_FLOAT: {
1083       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1084       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1085       __ lwz(tmp, from.disp(), from.base());
1086       __ stw(tmp, to.disp(), to.base());
1087       break;
1088     }
1089     case T_ADDRESS:
1090     case T_OBJECT: {
1091       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1092       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1093       __ ld(tmp, from.disp(), from.base());
1094       __ std(tmp, to.disp(), to.base());
1095       break;
1096     }
1097     case T_LONG:
1098     case T_DOUBLE: {
1099       Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1100       Address to   = frame_map()->address_for_double_slot(dest->double_stack_ix());
1101       __ ld(tmp, from.disp(), from.base());
1102       __ std(tmp, to.disp(), to.base());
1103       break;
1104     }
1105 
1106     default:
1107       ShouldNotReachHere();
1108   }
1109 }
1110 
1111 
1112 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1113   Unimplemented(); return Address();
1114 }
1115 
1116 
1117 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1118   Unimplemented(); return Address();
1119 }
1120 
1121 
1122 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1123                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1124 
1125   assert(type != T_METADATA, "load of metadata ptr not supported");
1126   LIR_Address* addr = src_opr->as_address_ptr();
1127   LIR_Opr to_reg = dest;
1128 
1129   Register src = addr->base()->as_pointer_register();
1130   Register disp_reg = noreg;
1131   int disp_value = addr->disp();
1132   bool needs_patching = (patch_code != lir_patch_none);
1133   // null check for large offsets in LIRGenerator::do_LoadField
1134   bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1135 
1136   if (info != NULL && needs_explicit_null_check) {
1137     explicit_null_check(src, info);
1138   }
1139 
1140   if (addr->base()->type() == T_OBJECT) {
1141     __ verify_oop(src, FILE_AND_LINE);
1142   }
1143 
1144   PatchingStub* patch = NULL;
1145   if (needs_patching) {
1146     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1147     assert(!to_reg->is_double_cpu() ||
1148            patch_code == lir_patch_none ||
1149            patch_code == lir_patch_normal, "patching doesn't match register");
1150   }
1151 
1152   if (addr->index()->is_illegal()) {
1153     if (!Assembler::is_simm16(disp_value)) {
1154       if (needs_patching) {
1155         __ load_const32(R0, 0); // patchable int
1156       } else {
1157         __ load_const_optimized(R0, disp_value);
1158       }
1159       disp_reg = R0;
1160     }
1161   } else {
1162     disp_reg = addr->index()->as_pointer_register();
1163     assert(disp_value == 0, "can't handle 3 operand addresses");
1164   }
1165 
1166   // Remember the offset of the load. The patching_epilog must be done
1167   // before the call to add_debug_info, otherwise the PcDescs don't get
1168   // entered in increasing order.
1169   int offset;
1170 
1171   if (disp_reg == noreg) {
1172     assert(Assembler::is_simm16(disp_value), "should have set this up");
1173     offset = load(src, disp_value, to_reg, type, wide);
1174   } else {
1175     offset = load(src, disp_reg, to_reg, type, wide);
1176   }
1177 
1178   if (patch != NULL) {
1179     patching_epilog(patch, patch_code, src, info);
1180   }
1181   if (info != NULL && !needs_explicit_null_check) {
1182     add_debug_info_for_null_check(offset, info);
1183   }
1184 }
1185 
1186 
1187 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1188   Address addr;
1189   if (src->is_single_word()) {
1190     addr = frame_map()->address_for_slot(src->single_stack_ix());
1191   } else if (src->is_double_word())  {
1192     addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1193   }
1194 
1195   load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1196 }
1197 
1198 
1199 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1200   Address addr;
1201   if (dest->is_single_word()) {
1202     addr = frame_map()->address_for_slot(dest->single_stack_ix());
1203   } else if (dest->is_double_word())  {
1204     addr = frame_map()->address_for_slot(dest->double_stack_ix());
1205   }
1206 
1207   store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1208 }
1209 
1210 
1211 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1212   if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1213     if (from_reg->is_double_fpu()) {
1214       // double to double moves
1215       assert(to_reg->is_double_fpu(), "should match");
1216       __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1217     } else {
1218       // float to float moves
1219       assert(to_reg->is_single_fpu(), "should match");
1220       __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1221     }
1222   } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1223     if (from_reg->is_double_cpu()) {
1224       __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1225     } else if (to_reg->is_double_cpu()) {
1226       // int to int moves
1227       __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1228     } else {
1229       // int to int moves
1230       __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1231     }
1232   } else {
1233     ShouldNotReachHere();
1234   }
1235   if (is_reference_type(to_reg->type())) {
1236     __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1237   }
1238 }
1239 
1240 
1241 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1242                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1243                             bool wide) {
1244   assert(type != T_METADATA, "store of metadata ptr not supported");
1245   LIR_Address* addr = dest->as_address_ptr();
1246 
1247   Register src = addr->base()->as_pointer_register();
1248   Register disp_reg = noreg;
1249   int disp_value = addr->disp();
1250   bool needs_patching = (patch_code != lir_patch_none);
1251   bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1252                       CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1253   bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1254   bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1255   // Null check for large offsets in LIRGenerator::do_StoreField.
1256   bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1257 
1258   if (info != NULL && needs_explicit_null_check) {
1259     explicit_null_check(src, info);
1260   }
1261 
1262   if (addr->base()->is_oop_register()) {
1263     __ verify_oop(src, FILE_AND_LINE);
1264   }
1265 
1266   PatchingStub* patch = NULL;
1267   if (needs_patching) {
1268     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1269     assert(!from_reg->is_double_cpu() ||
1270            patch_code == lir_patch_none ||
1271            patch_code == lir_patch_normal, "patching doesn't match register");
1272   }
1273 
1274   if (addr->index()->is_illegal()) {
1275     if (load_disp) {
1276       disp_reg = use_R29 ? R29_TOC : R0;
1277       if (needs_patching) {
1278         __ load_const32(disp_reg, 0); // patchable int
1279       } else {
1280         __ load_const_optimized(disp_reg, disp_value);
1281       }
1282     }
1283   } else {
1284     disp_reg = addr->index()->as_pointer_register();
1285     assert(disp_value == 0, "can't handle 3 operand addresses");
1286   }
1287 
1288   // remember the offset of the store. The patching_epilog must be done
1289   // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1290   // entered in increasing order.
1291   int offset;
1292 
1293   if (compress_oop) {
1294     Register co = __ encode_heap_oop(R0, from_reg->as_register());
1295     from_reg = FrameMap::as_opr(co);
1296   }
1297 
1298   if (disp_reg == noreg) {
1299     assert(Assembler::is_simm16(disp_value), "should have set this up");
1300     offset = store(from_reg, src, disp_value, type, wide);
1301   } else {
1302     offset = store(from_reg, src, disp_reg, type, wide);
1303   }
1304 
1305   if (use_R29) {
1306     __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1307   }
1308 
1309   if (patch != NULL) {
1310     patching_epilog(patch, patch_code, src, info);
1311   }
1312 
1313   if (info != NULL && !needs_explicit_null_check) {
1314     add_debug_info_for_null_check(offset, info);
1315   }
1316 }
1317 
1318 
1319 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1320   const Register return_pc = R31;  // Must survive C-call to enable_stack_reserved_zone().
1321   const Register temp      = R12;
1322 
1323   // Pop the stack before the safepoint code.
1324   int frame_size = initial_frame_size_in_bytes();
1325   if (Assembler::is_simm(frame_size, 16)) {
1326     __ addi(R1_SP, R1_SP, frame_size);
1327   } else {
1328     __ pop_frame();
1329   }
1330 
1331   // Restore return pc relative to callers' sp.
1332   __ ld(return_pc, _abi0(lr), R1_SP);
1333   // Move return pc to LR.
1334   __ mtlr(return_pc);
1335 
1336   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1337     __ reserved_stack_check(return_pc);
1338   }
1339 
1340   // We need to mark the code position where the load from the safepoint
1341   // polling page was emitted as relocInfo::poll_return_type here.
1342   if (!UseSIGTRAP) {
1343     code_stub->set_safepoint_offset(__ offset());
1344     __ relocate(relocInfo::poll_return_type);
1345   }
1346   __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1347 
1348   // Return.
1349   __ blr();
1350 }
1351 
1352 
1353 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1354   const Register poll_addr = tmp->as_register();
1355   __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1356   if (info != NULL) {
1357     add_debug_info_for_branch(info);
1358   }
1359   int offset = __ offset();
1360   __ relocate(relocInfo::poll_type);
1361   __ load_from_polling_page(poll_addr);
1362 
1363   return offset;
1364 }
1365 
1366 
1367 void LIR_Assembler::emit_static_call_stub() {
1368   address call_pc = __ pc();
1369   address stub = __ start_a_stub(static_call_stub_size());
1370   if (stub == NULL) {
1371     bailout("static call stub overflow");
1372     return;
1373   }
1374 
1375   // For java_to_interp stubs we use R11_scratch1 as scratch register
1376   // and in call trampoline stubs we use R12_scratch2. This way we
1377   // can distinguish them (see is_NativeCallTrampolineStub_at()).
1378   const Register reg_scratch = R11_scratch1;
1379 
1380   // Create a static stub relocation which relates this stub
1381   // with the call instruction at insts_call_instruction_offset in the
1382   // instructions code-section.
1383   int start = __ offset();
1384   __ relocate(static_stub_Relocation::spec(call_pc));
1385 
1386   // Now, create the stub's code:
1387   // - load the TOC
1388   // - load the inline cache oop from the constant pool
1389   // - load the call target from the constant pool
1390   // - call
1391   __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1392   AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL);
1393   bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1394 
1395   if (ReoptimizeCallSequences) {
1396     __ b64_patchable((address)-1, relocInfo::none);
1397   } else {
1398     AddressLiteral a((address)-1);
1399     success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1400     __ mtctr(reg_scratch);
1401     __ bctr();
1402   }
1403   if (!success) {
1404     bailout("const section overflow");
1405     return;
1406   }
1407 
1408   assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1409   __ end_a_stub();
1410 }
1411 
1412 
1413 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1414   bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1415   if (opr1->is_single_fpu()) {
1416     __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1417   } else if (opr1->is_double_fpu()) {
1418     __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1419   } else if (opr1->is_single_cpu()) {
1420     if (opr2->is_constant()) {
1421       switch (opr2->as_constant_ptr()->type()) {
1422         case T_INT:
1423           {
1424             jint con = opr2->as_constant_ptr()->as_jint();
1425             if (unsigned_comp) {
1426               if (Assembler::is_uimm(con, 16)) {
1427                 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1428               } else {
1429                 __ load_const_optimized(R0, con);
1430                 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1431               }
1432             } else {
1433               if (Assembler::is_simm(con, 16)) {
1434                 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1435               } else {
1436                 __ load_const_optimized(R0, con);
1437                 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1438               }
1439             }
1440           }
1441           break;
1442 
1443         case T_OBJECT:
1444           // There are only equal/notequal comparisons on objects.
1445           {
1446             assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1447             jobject con = opr2->as_constant_ptr()->as_jobject();
1448             if (con == NULL) {
1449               __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1450             } else {
1451               jobject2reg(con, R0);
1452               __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1453             }
1454           }
1455           break;
1456 
1457         case T_METADATA:
1458           // We only need, for now, comparison with NULL for metadata.
1459           {
1460             assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1461             Metadata* p = opr2->as_constant_ptr()->as_metadata();
1462             if (p == NULL) {
1463               __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1464             } else {
1465               ShouldNotReachHere();
1466             }
1467           }
1468           break;
1469 
1470         default:
1471           ShouldNotReachHere();
1472           break;
1473       }
1474     } else {
1475       assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1476       if (is_reference_type(opr1->type())) {
1477         // There are only equal/notequal comparisons on objects.
1478         assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1479         __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1480       } else {
1481         if (unsigned_comp) {
1482           __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1483         } else {
1484           __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1485         }
1486       }
1487     }
1488   } else if (opr1->is_double_cpu()) {
1489     if (opr2->is_constant()) {
1490       jlong con = opr2->as_constant_ptr()->as_jlong();
1491       if (unsigned_comp) {
1492         if (Assembler::is_uimm(con, 16)) {
1493           __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1494         } else {
1495           __ load_const_optimized(R0, con);
1496           __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1497         }
1498       } else {
1499         if (Assembler::is_simm(con, 16)) {
1500           __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1501         } else {
1502           __ load_const_optimized(R0, con);
1503           __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1504         }
1505       }
1506     } else if (opr2->is_register()) {
1507       if (unsigned_comp) {
1508         __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1509       } else {
1510         __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1511       }
1512     } else {
1513       ShouldNotReachHere();
1514     }
1515   } else {
1516     ShouldNotReachHere();
1517   }
1518 }
1519 
1520 
1521 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1522   const Register Rdst = dst->as_register();
1523   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1524     bool is_unordered_less = (code == lir_ucmp_fd2i);
1525     if (left->is_single_fpu()) {
1526       __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1527     } else if (left->is_double_fpu()) {
1528       __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1529     } else {
1530       ShouldNotReachHere();
1531     }
1532     __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1533   } else if (code == lir_cmp_l2i) {
1534     __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1535     __ set_cmp3(Rdst);  // set result as follows: <: -1, =: 0, >: 1
1536   } else {
1537     ShouldNotReachHere();
1538   }
1539 }
1540 
1541 
1542 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1543   if (src->is_constant()) {
1544     lasm->const2reg(src, dst, lir_patch_none, NULL);
1545   } else if (src->is_register()) {
1546     lasm->reg2reg(src, dst);
1547   } else if (src->is_stack()) {
1548     lasm->stack2reg(src, dst, dst->type());
1549   } else {
1550     ShouldNotReachHere();
1551   }
1552 }
1553 
1554 
1555 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1556   if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1557     load_to_reg(this, opr1, result); // Condition doesn't matter.
1558     return;
1559   }
1560 
1561   bool positive = false;
1562   Assembler::Condition cond = Assembler::equal;
1563   switch (condition) {
1564     case lir_cond_equal:        positive = true ; cond = Assembler::equal  ; break;
1565     case lir_cond_notEqual:     positive = false; cond = Assembler::equal  ; break;
1566     case lir_cond_less:         positive = true ; cond = Assembler::less   ; break;
1567     case lir_cond_belowEqual:
1568     case lir_cond_lessEqual:    positive = false; cond = Assembler::greater; break;
1569     case lir_cond_greater:      positive = true ; cond = Assembler::greater; break;
1570     case lir_cond_aboveEqual:
1571     case lir_cond_greaterEqual: positive = false; cond = Assembler::less   ; break;
1572     default:                    ShouldNotReachHere();
1573   }
1574 
1575   // Try to use isel on >=Power7.
1576   if (VM_Version::has_isel() && result->is_cpu_register()) {
1577     bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1578     const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1579 
1580     // We can use result_reg to load one operand if not already in register.
1581     Register first  = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1582              second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1583 
1584     if (first != second) {
1585       if (!o1_is_reg) {
1586         load_to_reg(this, opr1, result);
1587       }
1588 
1589       if (!o2_is_reg) {
1590         load_to_reg(this, opr2, result);
1591       }
1592 
1593       __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1594       return;
1595     }
1596   } // isel
1597 
1598   load_to_reg(this, opr1, result);
1599 
1600   Label skip;
1601   int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1602   int bi = Assembler::bi0(BOOL_RESULT, cond);
1603   __ bc(bo, bi, skip);
1604 
1605   load_to_reg(this, opr2, result);
1606   __ bind(skip);
1607 }
1608 
1609 
1610 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1611                              CodeEmitInfo* info, bool pop_fpu_stack) {
1612   assert(info == NULL, "unused on this code path");
1613   assert(left->is_register(), "wrong items state");
1614   assert(dest->is_register(), "wrong items state");
1615 
1616   if (right->is_register()) {
1617     if (dest->is_float_kind()) {
1618 
1619       FloatRegister lreg, rreg, res;
1620       if (right->is_single_fpu()) {
1621         lreg = left->as_float_reg();
1622         rreg = right->as_float_reg();
1623         res  = dest->as_float_reg();
1624         switch (code) {
1625           case lir_add: __ fadds(res, lreg, rreg); break;
1626           case lir_sub: __ fsubs(res, lreg, rreg); break;
1627           case lir_mul: __ fmuls(res, lreg, rreg); break;
1628           case lir_div: __ fdivs(res, lreg, rreg); break;
1629           default: ShouldNotReachHere();
1630         }
1631       } else {
1632         lreg = left->as_double_reg();
1633         rreg = right->as_double_reg();
1634         res  = dest->as_double_reg();
1635         switch (code) {
1636           case lir_add: __ fadd(res, lreg, rreg); break;
1637           case lir_sub: __ fsub(res, lreg, rreg); break;
1638           case lir_mul: __ fmul(res, lreg, rreg); break;
1639           case lir_div: __ fdiv(res, lreg, rreg); break;
1640           default: ShouldNotReachHere();
1641         }
1642       }
1643 
1644     } else if (dest->is_double_cpu()) {
1645 
1646       Register dst_lo = dest->as_register_lo();
1647       Register op1_lo = left->as_pointer_register();
1648       Register op2_lo = right->as_pointer_register();
1649 
1650       switch (code) {
1651         case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1652         case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1653         case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1654         default: ShouldNotReachHere();
1655       }
1656     } else {
1657       assert (right->is_single_cpu(), "Just Checking");
1658 
1659       Register lreg = left->as_register();
1660       Register res  = dest->as_register();
1661       Register rreg = right->as_register();
1662       switch (code) {
1663         case lir_add:  __ add  (res, lreg, rreg); break;
1664         case lir_sub:  __ sub  (res, lreg, rreg); break;
1665         case lir_mul:  __ mullw(res, lreg, rreg); break;
1666         default: ShouldNotReachHere();
1667       }
1668     }
1669   } else {
1670     assert (right->is_constant(), "must be constant");
1671 
1672     if (dest->is_single_cpu()) {
1673       Register lreg = left->as_register();
1674       Register res  = dest->as_register();
1675       int    simm16 = right->as_constant_ptr()->as_jint();
1676 
1677       switch (code) {
1678         case lir_sub:  assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1679                        simm16 = -simm16;
1680         case lir_add:  if (res == lreg && simm16 == 0) break;
1681                        __ addi(res, lreg, simm16); break;
1682         case lir_mul:  if (res == lreg && simm16 == 1) break;
1683                        __ mulli(res, lreg, simm16); break;
1684         default: ShouldNotReachHere();
1685       }
1686     } else {
1687       Register lreg = left->as_pointer_register();
1688       Register res  = dest->as_register_lo();
1689       long con = right->as_constant_ptr()->as_jlong();
1690       assert(Assembler::is_simm16(con), "must be simm16");
1691 
1692       switch (code) {
1693         case lir_sub:  assert(Assembler::is_simm16(-con), "cannot encode");  // see do_ArithmeticOp_Long
1694                        con = -con;
1695         case lir_add:  if (res == lreg && con == 0) break;
1696                        __ addi(res, lreg, (int)con); break;
1697         case lir_mul:  if (res == lreg && con == 1) break;
1698                        __ mulli(res, lreg, (int)con); break;
1699         default: ShouldNotReachHere();
1700       }
1701     }
1702   }
1703 }
1704 
1705 
1706 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1707   switch (code) {
1708     case lir_sqrt: {
1709       __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1710       break;
1711     }
1712     case lir_abs: {
1713       __ fabs(dest->as_double_reg(), value->as_double_reg());
1714       break;
1715     }
1716     default: {
1717       ShouldNotReachHere();
1718       break;
1719     }
1720   }
1721 }
1722 
1723 
1724 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1725   if (right->is_constant()) { // see do_LogicOp
1726     long uimm;
1727     Register d, l;
1728     if (dest->is_single_cpu()) {
1729       uimm = right->as_constant_ptr()->as_jint();
1730       d = dest->as_register();
1731       l = left->as_register();
1732     } else {
1733       uimm = right->as_constant_ptr()->as_jlong();
1734       d = dest->as_register_lo();
1735       l = left->as_register_lo();
1736     }
1737     long uimms  = (unsigned long)uimm >> 16,
1738          uimmss = (unsigned long)uimm >> 32;
1739 
1740     switch (code) {
1741       case lir_logic_and:
1742         if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1743           __ andi(d, l, uimm); // special cases
1744         } else if (uimms != 0) { __ andis_(d, l, uimms); }
1745         else { __ andi_(d, l, uimm); }
1746         break;
1747 
1748       case lir_logic_or:
1749         if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1750         else { __ ori(d, l, uimm); }
1751         break;
1752 
1753       case lir_logic_xor:
1754         if (uimm == -1) { __ nand(d, l, l); } // special case
1755         else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1756         else { __ xori(d, l, uimm); }
1757         break;
1758 
1759       default: ShouldNotReachHere();
1760     }
1761   } else {
1762     assert(right->is_register(), "right should be in register");
1763 
1764     if (dest->is_single_cpu()) {
1765       switch (code) {
1766         case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1767         case lir_logic_or:  __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1768         case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1769         default: ShouldNotReachHere();
1770       }
1771     } else {
1772       Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1773                                                                         left->as_register_lo();
1774       Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1775                                                                           right->as_register_lo();
1776 
1777       switch (code) {
1778         case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1779         case lir_logic_or:  __ orr (dest->as_register_lo(), l, r); break;
1780         case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1781         default: ShouldNotReachHere();
1782       }
1783     }
1784   }
1785 }
1786 
1787 
1788 int LIR_Assembler::shift_amount(BasicType t) {
1789   int elem_size = type2aelembytes(t);
1790   switch (elem_size) {
1791     case 1 : return 0;
1792     case 2 : return 1;
1793     case 4 : return 2;
1794     case 8 : return 3;
1795   }
1796   ShouldNotReachHere();
1797   return -1;
1798 }
1799 
1800 
1801 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1802   info->add_register_oop(exceptionOop);
1803 
1804   // Reuse the debug info from the safepoint poll for the throw op itself.
1805   address pc_for_athrow = __ pc();
1806   int pc_for_athrow_offset = __ offset();
1807   //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1808   //__ relocate(rspec);
1809   //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1810   __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1811   add_call_info(pc_for_athrow_offset, info); // for exception handler
1812 
1813   address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1814                                                                    : Runtime1::handle_exception_nofpu_id);
1815   //__ load_const_optimized(R0, stub);
1816   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1817   __ mtctr(R0);
1818   __ bctr();
1819 }
1820 
1821 
1822 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1823   // Note: Not used with EnableDebuggingOnDemand.
1824   assert(exceptionOop->as_register() == R3, "should match");
1825   __ b(_unwind_handler_entry);
1826 }
1827 
1828 
1829 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1830   Register src = op->src()->as_register();
1831   Register dst = op->dst()->as_register();
1832   Register src_pos = op->src_pos()->as_register();
1833   Register dst_pos = op->dst_pos()->as_register();
1834   Register length  = op->length()->as_register();
1835   Register tmp = op->tmp()->as_register();
1836   Register tmp2 = R0;
1837 
1838   int flags = op->flags();
1839   ciArrayKlass* default_type = op->expected_type();
1840   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1841   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1842 
1843   // Set up the arraycopy stub information.
1844   ArrayCopyStub* stub = op->stub();
1845   const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame.
1846 
1847   // Always do stub if no type information is available. It's ok if
1848   // the known type isn't loaded since the code sanity checks
1849   // in debug mode and the type isn't required when we know the exact type
1850   // also check that the type is an array type.
1851   if (op->expected_type() == NULL) {
1852     assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1853            length->is_nonvolatile(), "must preserve");
1854     address copyfunc_addr = StubRoutines::generic_arraycopy();
1855     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
1856 
1857     // 3 parms are int. Convert to long.
1858     __ mr(R3_ARG1, src);
1859     __ extsw(R4_ARG2, src_pos);
1860     __ mr(R5_ARG3, dst);
1861     __ extsw(R6_ARG4, dst_pos);
1862     __ extsw(R7_ARG5, length);
1863 
1864 #ifndef PRODUCT
1865     if (PrintC1Statistics) {
1866       address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1867       int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1868       __ lwz(R11_scratch1, simm16_offs, tmp);
1869       __ addi(R11_scratch1, R11_scratch1, 1);
1870       __ stw(R11_scratch1, simm16_offs, tmp);
1871     }
1872 #endif
1873     __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
1874 
1875     __ nand(tmp, R3_RET, R3_RET);
1876     __ subf(length, tmp, length);
1877     __ add(src_pos, tmp, src_pos);
1878     __ add(dst_pos, tmp, dst_pos);
1879 
1880     __ cmpwi(CCR0, R3_RET, 0);
1881     __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1882     __ bind(*stub->continuation());
1883     return;
1884   }
1885 
1886   assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1887   Label cont, slow, copyfunc;
1888 
1889   bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1890                                         LIR_OpArrayCopy::dst_null_check |
1891                                         LIR_OpArrayCopy::src_pos_positive_check |
1892                                         LIR_OpArrayCopy::dst_pos_positive_check |
1893                                         LIR_OpArrayCopy::length_positive_check);
1894 
1895   // Use only one conditional branch for simple checks.
1896   if (simple_check_flag_set) {
1897     ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1898 
1899     // Make sure src and dst are non-null.
1900     if (flags & LIR_OpArrayCopy::src_null_check) {
1901       __ cmpdi(combined_check, src, 0);
1902       tmp_check = CCR0;
1903     }
1904 
1905     if (flags & LIR_OpArrayCopy::dst_null_check) {
1906       __ cmpdi(tmp_check, dst, 0);
1907       if (tmp_check != combined_check) {
1908         __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1909       }
1910       tmp_check = CCR0;
1911     }
1912 
1913     // Clear combined_check.eq if not already used.
1914     if (tmp_check == combined_check) {
1915       __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1916       tmp_check = CCR0;
1917     }
1918 
1919     if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1920       // Test src_pos register.
1921       __ cmpwi(tmp_check, src_pos, 0);
1922       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1923     }
1924 
1925     if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1926       // Test dst_pos register.
1927       __ cmpwi(tmp_check, dst_pos, 0);
1928       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1929     }
1930 
1931     if (flags & LIR_OpArrayCopy::length_positive_check) {
1932       // Make sure length isn't negative.
1933       __ cmpwi(tmp_check, length, 0);
1934       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1935     }
1936 
1937     __ beq(combined_check, slow);
1938   }
1939 
1940   // If the compiler was not able to prove that exact type of the source or the destination
1941   // of the arraycopy is an array type, check at runtime if the source or the destination is
1942   // an instance type.
1943   if (flags & LIR_OpArrayCopy::type_check) {
1944     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1945       __ load_klass(tmp, dst);
1946       __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1947       __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1948       __ bge(CCR0, slow);
1949     }
1950 
1951     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1952       __ load_klass(tmp, src);
1953       __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1954       __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1955       __ bge(CCR0, slow);
1956     }
1957   }
1958 
1959   // Higher 32bits must be null.
1960   __ extsw(length, length);
1961 
1962   __ extsw(src_pos, src_pos);
1963   if (flags & LIR_OpArrayCopy::src_range_check) {
1964     __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1965     __ add(tmp, length, src_pos);
1966     __ cmpld(CCR0, tmp2, tmp);
1967     __ ble(CCR0, slow);
1968   }
1969 
1970   __ extsw(dst_pos, dst_pos);
1971   if (flags & LIR_OpArrayCopy::dst_range_check) {
1972     __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1973     __ add(tmp, length, dst_pos);
1974     __ cmpld(CCR0, tmp2, tmp);
1975     __ ble(CCR0, slow);
1976   }
1977 
1978   int shift = shift_amount(basic_type);
1979 
1980   if (!(flags & LIR_OpArrayCopy::type_check)) {
1981     __ b(cont);
1982   } else {
1983     // We don't know the array types are compatible.
1984     if (basic_type != T_OBJECT) {
1985       // Simple test for basic type arrays.
1986       if (UseCompressedClassPointers) {
1987         // We don't need decode because we just need to compare.
1988         __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
1989         __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1990         __ cmpw(CCR0, tmp, tmp2);
1991       } else {
1992         __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
1993         __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1994         __ cmpd(CCR0, tmp, tmp2);
1995       }
1996       __ beq(CCR0, cont);
1997     } else {
1998       // For object arrays, if src is a sub class of dst then we can
1999       // safely do the copy.
2000       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2001 
2002       const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
2003       assert_different_registers(tmp, tmp2, sub_klass, super_klass);
2004 
2005       __ load_klass(sub_klass, src);
2006       __ load_klass(super_klass, dst);
2007 
2008       __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
2009                                        &cont, copyfunc_addr != NULL ? &copyfunc : &slow, NULL);
2010 
2011       address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2012       //__ load_const_optimized(tmp, slow_stc, tmp2);
2013       __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2014       __ mtctr(tmp);
2015       __ bctrl(); // sets CR0
2016       __ beq(CCR0, cont);
2017 
2018       if (copyfunc_addr != NULL) { // Use stub if available.
2019         __ bind(copyfunc);
2020         // Src is not a sub class of dst so we have to do a
2021         // per-element check.
2022         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2023         if ((flags & mask) != mask) {
2024           assert(flags & mask, "one of the two should be known to be an object array");
2025 
2026           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2027             __ load_klass(tmp, src);
2028           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2029             __ load_klass(tmp, dst);
2030           }
2031 
2032           __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2033 
2034           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2035           __ load_const_optimized(tmp, objArray_lh);
2036           __ cmpw(CCR0, tmp, tmp2);
2037           __ bne(CCR0, slow);
2038         }
2039 
2040         Register src_ptr = R3_ARG1;
2041         Register dst_ptr = R4_ARG2;
2042         Register len     = R5_ARG3;
2043         Register chk_off = R6_ARG4;
2044         Register super_k = R7_ARG5;
2045 
2046         __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2047         __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2048         if (shift == 0) {
2049           __ add(src_ptr, src_pos, src_ptr);
2050           __ add(dst_ptr, dst_pos, dst_ptr);
2051         } else {
2052           __ sldi(tmp, src_pos, shift);
2053           __ sldi(tmp2, dst_pos, shift);
2054           __ add(src_ptr, tmp, src_ptr);
2055           __ add(dst_ptr, tmp2, dst_ptr);
2056         }
2057 
2058         __ load_klass(tmp, dst);
2059         __ mr(len, length);
2060 
2061         int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2062         __ ld(super_k, ek_offset, tmp);
2063 
2064         int sco_offset = in_bytes(Klass::super_check_offset_offset());
2065         __ lwz(chk_off, sco_offset, super_k);
2066 
2067         __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
2068 
2069 #ifndef PRODUCT
2070         if (PrintC1Statistics) {
2071           Label failed;
2072           __ cmpwi(CCR0, R3_RET, 0);
2073           __ bne(CCR0, failed);
2074           address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2075           int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2076           __ lwz(R11_scratch1, simm16_offs, tmp);
2077           __ addi(R11_scratch1, R11_scratch1, 1);
2078           __ stw(R11_scratch1, simm16_offs, tmp);
2079           __ bind(failed);
2080         }
2081 #endif
2082 
2083         __ nand(tmp, R3_RET, R3_RET);
2084         __ cmpwi(CCR0, R3_RET, 0);
2085         __ beq(CCR0, *stub->continuation());
2086 
2087 #ifndef PRODUCT
2088         if (PrintC1Statistics) {
2089           address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2090           int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2091           __ lwz(R11_scratch1, simm16_offs, tmp);
2092           __ addi(R11_scratch1, R11_scratch1, 1);
2093           __ stw(R11_scratch1, simm16_offs, tmp);
2094         }
2095 #endif
2096 
2097         __ subf(length, tmp, length);
2098         __ add(src_pos, tmp, src_pos);
2099         __ add(dst_pos, tmp, dst_pos);
2100       }
2101     }
2102   }
2103   __ bind(slow);
2104   __ b(*stub->entry());
2105   __ bind(cont);
2106 
2107 #ifdef ASSERT
2108   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2109     // Sanity check the known type with the incoming class. For the
2110     // primitive case the types must match exactly with src.klass and
2111     // dst.klass each exactly matching the default type. For the
2112     // object array case, if no type check is needed then either the
2113     // dst type is exactly the expected type and the src type is a
2114     // subtype which we can't check or src is the same array as dst
2115     // but not necessarily exactly of type default_type.
2116     Label known_ok, halt;
2117     metadata2reg(op->expected_type()->constant_encoding(), tmp);
2118     if (UseCompressedClassPointers) {
2119       // Tmp holds the default type. It currently comes uncompressed after the
2120       // load of a constant, so encode it.
2121       __ encode_klass_not_null(tmp);
2122       // Load the raw value of the dst klass, since we will be comparing
2123       // uncompressed values directly.
2124       __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2125       __ cmpw(CCR0, tmp, tmp2);
2126       if (basic_type != T_OBJECT) {
2127         __ bne(CCR0, halt);
2128         // Load the raw value of the src klass.
2129         __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2130         __ cmpw(CCR0, tmp, tmp2);
2131         __ beq(CCR0, known_ok);
2132       } else {
2133         __ beq(CCR0, known_ok);
2134         __ cmpw(CCR0, src, dst);
2135         __ beq(CCR0, known_ok);
2136       }
2137     } else {
2138       __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2139       __ cmpd(CCR0, tmp, tmp2);
2140       if (basic_type != T_OBJECT) {
2141         __ bne(CCR0, halt);
2142         // Load the raw value of the src klass.
2143         __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2144         __ cmpd(CCR0, tmp, tmp2);
2145         __ beq(CCR0, known_ok);
2146       } else {
2147         __ beq(CCR0, known_ok);
2148         __ cmpd(CCR0, src, dst);
2149         __ beq(CCR0, known_ok);
2150       }
2151     }
2152     __ bind(halt);
2153     __ stop("incorrect type information in arraycopy");
2154     __ bind(known_ok);
2155   }
2156 #endif
2157 
2158 #ifndef PRODUCT
2159   if (PrintC1Statistics) {
2160     address counter = Runtime1::arraycopy_count_address(basic_type);
2161     int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2162     __ lwz(R11_scratch1, simm16_offs, tmp);
2163     __ addi(R11_scratch1, R11_scratch1, 1);
2164     __ stw(R11_scratch1, simm16_offs, tmp);
2165   }
2166 #endif
2167 
2168   Register src_ptr = R3_ARG1;
2169   Register dst_ptr = R4_ARG2;
2170   Register len     = R5_ARG3;
2171 
2172   __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2173   __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2174   if (shift == 0) {
2175     __ add(src_ptr, src_pos, src_ptr);
2176     __ add(dst_ptr, dst_pos, dst_ptr);
2177   } else {
2178     __ sldi(tmp, src_pos, shift);
2179     __ sldi(tmp2, dst_pos, shift);
2180     __ add(src_ptr, tmp, src_ptr);
2181     __ add(dst_ptr, tmp2, dst_ptr);
2182   }
2183 
2184   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2185   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2186   const char *name;
2187   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2188 
2189   // Arraycopy stubs takes a length in number of elements, so don't scale it.
2190   __ mr(len, length);
2191   __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0);
2192 
2193   __ bind(*stub->continuation());
2194 }
2195 
2196 
2197 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2198   if (dest->is_single_cpu()) {
2199     __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2200 #ifdef _LP64
2201     if (left->type() == T_OBJECT) {
2202       switch (code) {
2203         case lir_shl:  __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2204         case lir_shr:  __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2205         case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2206         default: ShouldNotReachHere();
2207       }
2208     } else
2209 #endif
2210       switch (code) {
2211         case lir_shl:  __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2212         case lir_shr:  __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2213         case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2214         default: ShouldNotReachHere();
2215       }
2216   } else {
2217     __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2218     switch (code) {
2219       case lir_shl:  __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2220       case lir_shr:  __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2221       case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2222       default: ShouldNotReachHere();
2223     }
2224   }
2225 }
2226 
2227 
2228 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2229 #ifdef _LP64
2230   if (left->type() == T_OBJECT) {
2231     count = count & 63;  // Shouldn't shift by more than sizeof(intptr_t).
2232     if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2233     else {
2234       switch (code) {
2235         case lir_shl:  __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2236         case lir_shr:  __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2237         case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2238         default: ShouldNotReachHere();
2239       }
2240     }
2241     return;
2242   }
2243 #endif
2244 
2245   if (dest->is_single_cpu()) {
2246     count = count & 0x1F; // Java spec
2247     if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2248     else {
2249       switch (code) {
2250         case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2251         case lir_shr:  __ srawi(dest->as_register(), left->as_register(), count); break;
2252         case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2253         default: ShouldNotReachHere();
2254       }
2255     }
2256   } else if (dest->is_double_cpu()) {
2257     count = count & 63; // Java spec
2258     if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2259     else {
2260       switch (code) {
2261         case lir_shl:  __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2262         case lir_shr:  __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2263         case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2264         default: ShouldNotReachHere();
2265       }
2266     }
2267   } else {
2268     ShouldNotReachHere();
2269   }
2270 }
2271 
2272 
2273 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2274   if (op->init_check()) {
2275     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2276       explicit_null_check(op->klass()->as_register(), op->stub()->info());
2277     } else {
2278       add_debug_info_for_null_check_here(op->stub()->info());
2279     }
2280     __ lbz(op->tmp1()->as_register(),
2281            in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2282     __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2283     __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2284   }
2285   __ allocate_object(op->obj()->as_register(),
2286                      op->tmp1()->as_register(),
2287                      op->tmp2()->as_register(),
2288                      op->tmp3()->as_register(),
2289                      op->header_size(),
2290                      op->object_size(),
2291                      op->klass()->as_register(),
2292                      *op->stub()->entry());
2293 
2294   __ bind(*op->stub()->continuation());
2295   __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2296 }
2297 
2298 
2299 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2300   LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2301   if (UseSlowPath ||
2302       (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2303       (!UseFastNewTypeArray   && (!is_reference_type(op->type())))) {
2304     __ b(*op->stub()->entry());
2305   } else {
2306     __ allocate_array(op->obj()->as_register(),
2307                       op->len()->as_register(),
2308                       op->tmp1()->as_register(),
2309                       op->tmp2()->as_register(),
2310                       op->tmp3()->as_register(),
2311                       arrayOopDesc::header_size(op->type()),
2312                       type2aelembytes(op->type()),
2313                       op->klass()->as_register(),
2314                       *op->stub()->entry());
2315   }
2316   __ bind(*op->stub()->continuation());
2317 }
2318 
2319 
2320 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2321                                         ciMethodData *md, ciProfileData *data,
2322                                         Register recv, Register tmp1, Label* update_done) {
2323   uint i;
2324   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2325     Label next_test;
2326     // See if the receiver is receiver[n].
2327     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2328     __ verify_klass_ptr(tmp1);
2329     __ cmpd(CCR0, recv, tmp1);
2330     __ bne(CCR0, next_test);
2331 
2332     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2333     __ addi(tmp1, tmp1, DataLayout::counter_increment);
2334     __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2335     __ b(*update_done);
2336 
2337     __ bind(next_test);
2338   }
2339 
2340   // Didn't find receiver; find next empty slot and fill it in.
2341   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2342     Label next_test;
2343     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2344     __ cmpdi(CCR0, tmp1, 0);
2345     __ bne(CCR0, next_test);
2346     __ li(tmp1, DataLayout::counter_increment);
2347     __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2348     __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2349     __ b(*update_done);
2350 
2351     __ bind(next_test);
2352   }
2353 }
2354 
2355 
2356 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2357                                     ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2358   md = method->method_data_or_null();
2359   assert(md != NULL, "Sanity");
2360   data = md->bci_to_data(bci);
2361   assert(data != NULL,       "need data for checkcast");
2362   assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2363   if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2364     // The offset is large so bias the mdo by the base of the slot so
2365     // that the ld can use simm16s to reference the slots of the data.
2366     mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2367   }
2368 }
2369 
2370 
2371 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2372   const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2373   Register k_RInfo = op->tmp1()->as_register();
2374   Register klass_RInfo = op->tmp2()->as_register();
2375   Register Rtmp1 = op->tmp3()->as_register();
2376   Register dst = op->result_opr()->as_register();
2377   ciKlass* k = op->klass();
2378   bool should_profile = op->should_profile();
2379   // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2380   bool reg_conflict = false;
2381   if (obj == k_RInfo) {
2382     k_RInfo = dst;
2383     reg_conflict = true;
2384   } else if (obj == klass_RInfo) {
2385     klass_RInfo = dst;
2386     reg_conflict = true;
2387   } else if (obj == Rtmp1) {
2388     Rtmp1 = dst;
2389     reg_conflict = true;
2390   }
2391   assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2392 
2393   __ cmpdi(CCR0, obj, 0);
2394 
2395   ciMethodData* md = NULL;
2396   ciProfileData* data = NULL;
2397   int mdo_offset_bias = 0;
2398   if (should_profile) {
2399     ciMethod* method = op->profiled_method();
2400     assert(method != NULL, "Should have method");
2401     setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2402 
2403     Register mdo      = k_RInfo;
2404     Register data_val = Rtmp1;
2405     Label not_null;
2406     __ bne(CCR0, not_null);
2407     metadata2reg(md->constant_encoding(), mdo);
2408     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2409     __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2410     __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2411     __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2412     __ b(*obj_is_null);
2413     __ bind(not_null);
2414   } else {
2415     __ beq(CCR0, *obj_is_null);
2416   }
2417 
2418   // get object class
2419   __ load_klass(klass_RInfo, obj);
2420 
2421   if (k->is_loaded()) {
2422     metadata2reg(k->constant_encoding(), k_RInfo);
2423   } else {
2424     klass2reg_with_patching(k_RInfo, op->info_for_patch());
2425   }
2426 
2427   Label profile_cast_failure, failure_restore_obj, profile_cast_success;
2428   Label *failure_target = should_profile ? &profile_cast_failure : failure;
2429   Label *success_target = should_profile ? &profile_cast_success : success;
2430 
2431   if (op->fast_check()) {
2432     assert_different_registers(klass_RInfo, k_RInfo);
2433     __ cmpd(CCR0, k_RInfo, klass_RInfo);
2434     if (should_profile) {
2435       __ bne(CCR0, *failure_target);
2436       // Fall through to success case.
2437     } else {
2438       __ beq(CCR0, *success);
2439       // Fall through to failure case.
2440     }
2441   } else {
2442     bool need_slow_path = true;
2443     if (k->is_loaded()) {
2444       if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2445         need_slow_path = false;
2446       }
2447       // Perform the fast part of the checking logic.
2448       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL),
2449                                        failure_target, NULL, RegisterOrConstant(k->super_check_offset()));
2450     } else {
2451       // Perform the fast part of the checking logic.
2452       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target);
2453     }
2454     if (!need_slow_path) {
2455       if (!should_profile) { __ b(*success); }
2456     } else {
2457       // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2458       address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2459       // Stub needs fixed registers (tmp1-3).
2460       Register original_k_RInfo = op->tmp1()->as_register();
2461       Register original_klass_RInfo = op->tmp2()->as_register();
2462       Register original_Rtmp1 = op->tmp3()->as_register();
2463       bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2464       bool keep_klass_RInfo_alive = (obj == original_klass_RInfo) && should_profile;
2465       if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2466       __ mr_if_needed(original_k_RInfo, k_RInfo);
2467       __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2468       if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2469       //__ load_const_optimized(original_Rtmp1, entry, R0);
2470       __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2471       __ mtctr(original_Rtmp1);
2472       __ bctrl(); // sets CR0
2473       if (keep_obj_alive) {
2474         if (keep_klass_RInfo_alive) { __ mr(R0, obj); }
2475         __ mr(obj, dst);
2476       }
2477       if (should_profile) {
2478         __ bne(CCR0, *failure_target);
2479         if (keep_klass_RInfo_alive) { __ mr(klass_RInfo, keep_obj_alive ? R0 : obj); }
2480         // Fall through to success case.
2481       } else {
2482         __ beq(CCR0, *success);
2483         // Fall through to failure case.
2484       }
2485     }
2486   }
2487 
2488   if (should_profile) {
2489     Register mdo = k_RInfo, recv = klass_RInfo;
2490     assert_different_registers(mdo, recv, Rtmp1);
2491     __ bind(profile_cast_success);
2492     metadata2reg(md->constant_encoding(), mdo);
2493     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2494     type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success);
2495     __ b(*success);
2496 
2497     // Cast failure case.
2498     __ bind(profile_cast_failure);
2499     metadata2reg(md->constant_encoding(), mdo);
2500     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2501     __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2502     __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment);
2503     __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2504   }
2505 
2506   __ bind(*failure);
2507 }
2508 
2509 
2510 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2511   LIR_Code code = op->code();
2512   if (code == lir_store_check) {
2513     Register value = op->object()->as_register();
2514     Register array = op->array()->as_register();
2515     Register k_RInfo = op->tmp1()->as_register();
2516     Register klass_RInfo = op->tmp2()->as_register();
2517     Register Rtmp1 = op->tmp3()->as_register();
2518     bool should_profile = op->should_profile();
2519 
2520     __ verify_oop(value, FILE_AND_LINE);
2521     CodeStub* stub = op->stub();
2522     // Check if it needs to be profiled.
2523     ciMethodData* md = NULL;
2524     ciProfileData* data = NULL;
2525     int mdo_offset_bias = 0;
2526     if (should_profile) {
2527       ciMethod* method = op->profiled_method();
2528       assert(method != NULL, "Should have method");
2529       setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2530     }
2531     Label profile_cast_success, failure, done;
2532     Label *success_target = should_profile ? &profile_cast_success : &done;
2533 
2534     __ cmpdi(CCR0, value, 0);
2535     if (should_profile) {
2536       Label not_null;
2537       __ bne(CCR0, not_null);
2538       Register mdo      = k_RInfo;
2539       Register data_val = Rtmp1;
2540       metadata2reg(md->constant_encoding(), mdo);
2541       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2542       __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2543       __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2544       __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2545       __ b(done);
2546       __ bind(not_null);
2547     } else {
2548       __ beq(CCR0, done);
2549     }
2550     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2551       explicit_null_check(array, op->info_for_exception());
2552     } else {
2553       add_debug_info_for_null_check_here(op->info_for_exception());
2554     }
2555     __ load_klass(k_RInfo, array);
2556     __ load_klass(klass_RInfo, value);
2557 
2558     // Get instance klass.
2559     __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2560     // Perform the fast part of the checking logic.
2561     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL);
2562 
2563     // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2564     const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2565     //__ load_const_optimized(R0, slow_path);
2566     __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2567     __ mtctr(R0);
2568     __ bctrl(); // sets CR0
2569     if (!should_profile) {
2570       __ beq(CCR0, done);
2571       __ bind(failure);
2572     } else {
2573       __ bne(CCR0, failure);
2574       // Fall through to the success case.
2575 
2576       Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2577       assert_different_registers(value, mdo, recv, tmp1);
2578       __ bind(profile_cast_success);
2579       metadata2reg(md->constant_encoding(), mdo);
2580       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2581       __ load_klass(recv, value);
2582       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2583       __ b(done);
2584 
2585       // Cast failure case.
2586       __ bind(failure);
2587       metadata2reg(md->constant_encoding(), mdo);
2588       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2589       Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2590       __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2591       __ addi(tmp1, tmp1, -DataLayout::counter_increment);
2592       __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2593     }
2594     __ b(*stub->entry());
2595     __ bind(done);
2596 
2597   } else if (code == lir_checkcast) {
2598     Label success, failure;
2599     emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2600     __ b(*op->stub()->entry());
2601     __ align(32, 12);
2602     __ bind(success);
2603     __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2604   } else if (code == lir_instanceof) {
2605     Register dst = op->result_opr()->as_register();
2606     Label success, failure, done;
2607     emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2608     __ li(dst, 0);
2609     __ b(done);
2610     __ align(32, 12);
2611     __ bind(success);
2612     __ li(dst, 1);
2613     __ bind(done);
2614   } else {
2615     ShouldNotReachHere();
2616   }
2617 }
2618 
2619 
2620 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2621   Register addr = op->addr()->as_pointer_register();
2622   Register cmp_value = noreg, new_value = noreg;
2623   bool is_64bit = false;
2624 
2625   if (op->code() == lir_cas_long) {
2626     cmp_value = op->cmp_value()->as_register_lo();
2627     new_value = op->new_value()->as_register_lo();
2628     is_64bit = true;
2629   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2630     cmp_value = op->cmp_value()->as_register();
2631     new_value = op->new_value()->as_register();
2632     if (op->code() == lir_cas_obj) {
2633       if (UseCompressedOops) {
2634         Register t1 = op->tmp1()->as_register();
2635         Register t2 = op->tmp2()->as_register();
2636         cmp_value = __ encode_heap_oop(t1, cmp_value);
2637         new_value = __ encode_heap_oop(t2, new_value);
2638       } else {
2639         is_64bit = true;
2640       }
2641     }
2642   } else {
2643     Unimplemented();
2644   }
2645 
2646   if (is_64bit) {
2647     __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2648                 MacroAssembler::MemBarNone,
2649                 MacroAssembler::cmpxchgx_hint_atomic_update(),
2650                 noreg, NULL, /*check without ldarx first*/true);
2651   } else {
2652     __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2653                 MacroAssembler::MemBarNone,
2654                 MacroAssembler::cmpxchgx_hint_atomic_update(),
2655                 noreg, /*check without ldarx first*/true);
2656   }
2657 
2658   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2659     __ isync();
2660   } else {
2661     __ sync();
2662   }
2663 }
2664 
2665 void LIR_Assembler::breakpoint() {
2666   __ illtrap();
2667 }
2668 
2669 
2670 void LIR_Assembler::push(LIR_Opr opr) {
2671   Unimplemented();
2672 }
2673 
2674 void LIR_Assembler::pop(LIR_Opr opr) {
2675   Unimplemented();
2676 }
2677 
2678 
2679 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2680   Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2681   Register dst = dst_opr->as_register();
2682   Register reg = mon_addr.base();
2683   int offset = mon_addr.disp();
2684   // Compute pointer to BasicLock.
2685   __ add_const_optimized(dst, reg, offset);
2686 }
2687 
2688 
2689 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2690   Register obj = op->obj_opr()->as_register();
2691   Register hdr = op->hdr_opr()->as_register();
2692   Register lock = op->lock_opr()->as_register();
2693 
2694   // Obj may not be an oop.
2695   if (op->code() == lir_lock) {
2696     MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2697     if (UseFastLocking) {
2698       assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2699       // Add debug info for NullPointerException only if one is possible.
2700       if (op->info() != NULL) {
2701         if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2702           explicit_null_check(obj, op->info());
2703         } else {
2704           add_debug_info_for_null_check_here(op->info());
2705         }
2706       }
2707       __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2708     } else {
2709       // always do slow locking
2710       // note: The slow locking code could be inlined here, however if we use
2711       //       slow locking, speed doesn't matter anyway and this solution is
2712       //       simpler and requires less duplicated code - additionally, the
2713       //       slow locking code is the same in either case which simplifies
2714       //       debugging.
2715       __ b(*op->stub()->entry());
2716     }
2717   } else {
2718     assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2719     if (UseFastLocking) {
2720       assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2721       __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2722     } else {
2723       // always do slow unlocking
2724       // note: The slow unlocking code could be inlined here, however if we use
2725       //       slow unlocking, speed doesn't matter anyway and this solution is
2726       //       simpler and requires less duplicated code - additionally, the
2727       //       slow unlocking code is the same in either case which simplifies
2728       //       debugging.
2729       __ b(*op->stub()->entry());
2730     }
2731   }
2732   __ bind(*op->stub()->continuation());
2733 }
2734 
2735 
2736 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2737   ciMethod* method = op->profiled_method();
2738   int bci          = op->profiled_bci();
2739   ciMethod* callee = op->profiled_callee();
2740 
2741   // Update counter for all call types.
2742   ciMethodData* md = method->method_data_or_null();
2743   assert(md != NULL, "Sanity");
2744   ciProfileData* data = md->bci_to_data(bci);
2745   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2746   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2747   Register mdo = op->mdo()->as_register();
2748 #ifdef _LP64
2749   assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2750   Register tmp1 = op->tmp1()->as_register_lo();
2751 #else
2752   assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2753   Register tmp1 = op->tmp1()->as_register();
2754 #endif
2755   metadata2reg(md->constant_encoding(), mdo);
2756   int mdo_offset_bias = 0;
2757   if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2758                             data->size_in_bytes())) {
2759     // The offset is large so bias the mdo by the base of the slot so
2760     // that the ld can use simm16s to reference the slots of the data.
2761     mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2762     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2763   }
2764 
2765   // Perform additional virtual call profiling for invokevirtual and
2766   // invokeinterface bytecodes
2767   if (op->should_profile_receiver_type()) {
2768     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2769     Register recv = op->recv()->as_register();
2770     assert_different_registers(mdo, tmp1, recv);
2771     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2772     ciKlass* known_klass = op->known_holder();
2773     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2774       // We know the type that will be seen at this call site; we can
2775       // statically update the MethodData* rather than needing to do
2776       // dynamic tests on the receiver type.
2777 
2778       // NOTE: we should probably put a lock around this search to
2779       // avoid collisions by concurrent compilations.
2780       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2781       uint i;
2782       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2783         ciKlass* receiver = vc_data->receiver(i);
2784         if (known_klass->equals(receiver)) {
2785           __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2786           __ addi(tmp1, tmp1, DataLayout::counter_increment);
2787           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2788           return;
2789         }
2790       }
2791 
2792       // Receiver type not found in profile data; select an empty slot.
2793 
2794       // Note that this is less efficient than it should be because it
2795       // always does a write to the receiver part of the
2796       // VirtualCallData rather than just the first time.
2797       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2798         ciKlass* receiver = vc_data->receiver(i);
2799         if (receiver == NULL) {
2800           metadata2reg(known_klass->constant_encoding(), tmp1);
2801           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2802 
2803           __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2804           __ addi(tmp1, tmp1, DataLayout::counter_increment);
2805           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2806           return;
2807         }
2808       }
2809     } else {
2810       __ load_klass(recv, recv);
2811       Label update_done;
2812       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2813       // Receiver did not match any saved receiver and there is no empty row for it.
2814       // Increment total counter to indicate polymorphic case.
2815       __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2816       __ addi(tmp1, tmp1, DataLayout::counter_increment);
2817       __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2818 
2819       __ bind(update_done);
2820     }
2821   } else {
2822     // Static call
2823     __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2824     __ addi(tmp1, tmp1, DataLayout::counter_increment);
2825     __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2826   }
2827 }
2828 
2829 
2830 void LIR_Assembler::align_backward_branch_target() {
2831   __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2832 }
2833 
2834 
2835 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2836   Unimplemented();
2837 }
2838 
2839 
2840 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2841   // tmp must be unused
2842   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2843   assert(left->is_register(), "can only handle registers");
2844 
2845   if (left->is_single_cpu()) {
2846     __ neg(dest->as_register(), left->as_register());
2847   } else if (left->is_single_fpu()) {
2848     __ fneg(dest->as_float_reg(), left->as_float_reg());
2849   } else if (left->is_double_fpu()) {
2850     __ fneg(dest->as_double_reg(), left->as_double_reg());
2851   } else {
2852     assert (left->is_double_cpu(), "Must be a long");
2853     __ neg(dest->as_register_lo(), left->as_register_lo());
2854   }
2855 }
2856 
2857 
2858 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2859                             const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2860   // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2861   if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) ||
2862       dest == Runtime1::entry_for(Runtime1::new_multi_array_id   )) {
2863     //__ load_const_optimized(R0, dest);
2864     __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2865     __ mtctr(R0);
2866     __ bctrl();
2867     assert(info != NULL, "sanity");
2868     add_call_info_here(info);
2869     return;
2870   }
2871 
2872   __ call_c_with_frame_resize(dest, /*no resizing*/ 0);
2873   if (info != NULL) {
2874     add_call_info_here(info);
2875   }
2876 }
2877 
2878 
2879 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2880   ShouldNotReachHere(); // Not needed on _LP64.
2881 }
2882 
2883 void LIR_Assembler::membar() {
2884   __ fence();
2885 }
2886 
2887 void LIR_Assembler::membar_acquire() {
2888   __ acquire();
2889 }
2890 
2891 void LIR_Assembler::membar_release() {
2892   __ release();
2893 }
2894 
2895 void LIR_Assembler::membar_loadload() {
2896   __ membar(Assembler::LoadLoad);
2897 }
2898 
2899 void LIR_Assembler::membar_storestore() {
2900   __ membar(Assembler::StoreStore);
2901 }
2902 
2903 void LIR_Assembler::membar_loadstore() {
2904   __ membar(Assembler::LoadStore);
2905 }
2906 
2907 void LIR_Assembler::membar_storeload() {
2908   __ membar(Assembler::StoreLoad);
2909 }
2910 
2911 void LIR_Assembler::on_spin_wait() {
2912   Unimplemented();
2913 }
2914 
2915 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2916   LIR_Address* addr = addr_opr->as_address_ptr();
2917   assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2918 
2919   if (addr->index()->is_illegal()) {
2920     if (patch_code != lir_patch_none) {
2921       PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2922       __ load_const32(R0, 0); // patchable int
2923       __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2924       patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2925     } else {
2926       __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2927     }
2928   } else {
2929     assert(patch_code == lir_patch_none, "Patch code not supported");
2930     assert(addr->disp() == 0, "can't have both: index and disp");
2931     __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2932   }
2933 }
2934 
2935 
2936 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2937   ShouldNotReachHere();
2938 }
2939 
2940 
2941 #ifdef ASSERT
2942 // Emit run-time assertion.
2943 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2944   Unimplemented();
2945 }
2946 #endif
2947 
2948 
2949 void LIR_Assembler::peephole(LIR_List* lir) {
2950   // Optimize instruction pairs before emitting.
2951   LIR_OpList* inst = lir->instructions_list();
2952   for (int i = 1; i < inst->length(); i++) {
2953     LIR_Op* op = inst->at(i);
2954 
2955     // 2 register-register-moves
2956     if (op->code() == lir_move) {
2957       LIR_Opr in2  = ((LIR_Op1*)op)->in_opr(),
2958               res2 = ((LIR_Op1*)op)->result_opr();
2959       if (in2->is_register() && res2->is_register()) {
2960         LIR_Op* prev = inst->at(i - 1);
2961         if (prev && prev->code() == lir_move) {
2962           LIR_Opr in1  = ((LIR_Op1*)prev)->in_opr(),
2963                   res1 = ((LIR_Op1*)prev)->result_opr();
2964           if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2965             inst->remove_at(i);
2966           }
2967         }
2968       }
2969     }
2970 
2971   }
2972   return;
2973 }
2974 
2975 
2976 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2977   const LIR_Address *addr = src->as_address_ptr();
2978   assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2979   const Register Rptr = addr->base()->as_pointer_register(),
2980                  Rtmp = tmp->as_register();
2981   Register Rco = noreg;
2982   if (UseCompressedOops && data->is_oop()) {
2983     Rco = __ encode_heap_oop(Rtmp, data->as_register());
2984   }
2985 
2986   Label Lretry;
2987   __ bind(Lretry);
2988 
2989   if (data->type() == T_INT) {
2990     const Register Rold = dest->as_register(),
2991                    Rsrc = data->as_register();
2992     assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2993     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2994     if (code == lir_xadd) {
2995       __ add(Rtmp, Rsrc, Rold);
2996       __ stwcx_(Rtmp, Rptr);
2997     } else {
2998       __ stwcx_(Rsrc, Rptr);
2999     }
3000   } else if (data->is_oop()) {
3001     assert(code == lir_xchg, "xadd for oops");
3002     const Register Rold = dest->as_register();
3003     if (UseCompressedOops) {
3004       assert_different_registers(Rptr, Rold, Rco);
3005       __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3006       __ stwcx_(Rco, Rptr);
3007     } else {
3008       const Register Robj = data->as_register();
3009       assert_different_registers(Rptr, Rold, Robj);
3010       __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3011       __ stdcx_(Robj, Rptr);
3012     }
3013   } else if (data->type() == T_LONG) {
3014     const Register Rold = dest->as_register_lo(),
3015                    Rsrc = data->as_register_lo();
3016     assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3017     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3018     if (code == lir_xadd) {
3019       __ add(Rtmp, Rsrc, Rold);
3020       __ stdcx_(Rtmp, Rptr);
3021     } else {
3022       __ stdcx_(Rsrc, Rptr);
3023     }
3024   } else {
3025     ShouldNotReachHere();
3026   }
3027 
3028   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3029     __ bne_predict_not_taken(CCR0, Lretry);
3030   } else {
3031     __ bne(                  CCR0, Lretry);
3032   }
3033 
3034   if (UseCompressedOops && data->is_oop()) {
3035     __ decode_heap_oop(dest->as_register());
3036   }
3037 }
3038 
3039 
3040 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3041   Register obj = op->obj()->as_register();
3042   Register tmp = op->tmp()->as_pointer_register();
3043   LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3044   ciKlass* exact_klass = op->exact_klass();
3045   intptr_t current_klass = op->current_klass();
3046   bool not_null = op->not_null();
3047   bool no_conflict = op->no_conflict();
3048 
3049   Label Lupdate, Ldo_update, Ldone;
3050 
3051   bool do_null = !not_null;
3052   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3053   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3054 
3055   assert(do_null || do_update, "why are we here?");
3056   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3057 
3058   __ verify_oop(obj, FILE_AND_LINE);
3059 
3060   if (do_null) {
3061     if (!TypeEntries::was_null_seen(current_klass)) {
3062       __ cmpdi(CCR0, obj, 0);
3063       __ bne(CCR0, Lupdate);
3064       __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3065       __ ori(R0, R0, TypeEntries::null_seen);
3066       if (do_update) {
3067         __ b(Ldo_update);
3068       } else {
3069         __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3070       }
3071     } else {
3072       if (do_update) {
3073         __ cmpdi(CCR0, obj, 0);
3074         __ beq(CCR0, Ldone);
3075       }
3076     }
3077 #ifdef ASSERT
3078   } else {
3079     __ cmpdi(CCR0, obj, 0);
3080     __ bne(CCR0, Lupdate);
3081     __ stop("unexpect null obj");
3082 #endif
3083   }
3084 
3085   __ bind(Lupdate);
3086   if (do_update) {
3087     Label Lnext;
3088     const Register klass = R29_TOC; // kill and reload
3089     bool klass_reg_used = false;
3090 #ifdef ASSERT
3091     if (exact_klass != NULL) {
3092       Label ok;
3093       klass_reg_used = true;
3094       __ load_klass(klass, obj);
3095       metadata2reg(exact_klass->constant_encoding(), R0);
3096       __ cmpd(CCR0, klass, R0);
3097       __ beq(CCR0, ok);
3098       __ stop("exact klass and actual klass differ");
3099       __ bind(ok);
3100     }
3101 #endif
3102 
3103     if (!no_conflict) {
3104       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3105         klass_reg_used = true;
3106         if (exact_klass != NULL) {
3107           __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3108           metadata2reg(exact_klass->constant_encoding(), klass);
3109         } else {
3110           __ load_klass(klass, obj);
3111           __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3112         }
3113 
3114         // Like InterpreterMacroAssembler::profile_obj_type
3115         __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3116         // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3117         __ cmpd(CCR1, R0, klass);
3118         // Klass seen before, nothing to do (regardless of unknown bit).
3119         //beq(CCR1, do_nothing);
3120 
3121         __ andi_(R0, klass, TypeEntries::type_unknown);
3122         // Already unknown. Nothing to do anymore.
3123         //bne(CCR0, do_nothing);
3124         __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3125         __ beq(CCR0, Lnext);
3126 
3127         if (TypeEntries::is_type_none(current_klass)) {
3128           __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3129           __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3130           __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3131         }
3132 
3133       } else {
3134         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3135                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3136 
3137         __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3138         __ andi_(R0, tmp, TypeEntries::type_unknown);
3139         // Already unknown. Nothing to do anymore.
3140         __ bne(CCR0, Lnext);
3141       }
3142 
3143       // Different than before. Cannot keep accurate profile.
3144       __ ori(R0, tmp, TypeEntries::type_unknown);
3145     } else {
3146       // There's a single possible klass at this profile point
3147       assert(exact_klass != NULL, "should be");
3148       __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3149 
3150       if (TypeEntries::is_type_none(current_klass)) {
3151         klass_reg_used = true;
3152         metadata2reg(exact_klass->constant_encoding(), klass);
3153 
3154         __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3155         // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3156         __ cmpd(CCR1, R0, klass);
3157         // Klass seen before, nothing to do (regardless of unknown bit).
3158         __ beq(CCR1, Lnext);
3159 #ifdef ASSERT
3160         {
3161           Label ok;
3162           __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3163           __ beq(CCR0, ok); // First time here.
3164 
3165           __ stop("unexpected profiling mismatch");
3166           __ bind(ok);
3167         }
3168 #endif
3169         // First time here. Set profile type.
3170         __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3171       } else {
3172         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3173                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3174 
3175         // Already unknown. Nothing to do anymore.
3176         __ andi_(R0, tmp, TypeEntries::type_unknown);
3177         __ bne(CCR0, Lnext);
3178 
3179         // Different than before. Cannot keep accurate profile.
3180         __ ori(R0, tmp, TypeEntries::type_unknown);
3181       }
3182     }
3183 
3184     __ bind(Ldo_update);
3185     __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3186 
3187     __ bind(Lnext);
3188     if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3189   }
3190   __ bind(Ldone);
3191 }
3192 
3193 
3194 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3195   assert(op->crc()->is_single_cpu(), "crc must be register");
3196   assert(op->val()->is_single_cpu(), "byte value must be register");
3197   assert(op->result_opr()->is_single_cpu(), "result must be register");
3198   Register crc = op->crc()->as_register();
3199   Register val = op->val()->as_register();
3200   Register res = op->result_opr()->as_register();
3201 
3202   assert_different_registers(val, crc, res);
3203 
3204   __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3205   __ kernel_crc32_singleByteReg(crc, val, res, true);
3206   __ mr(res, crc);
3207 }
3208 
3209 #undef __