1 /*
2 * Copyright (c) 2000, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2026 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "memory/universe.hpp"
36 #include "nativeInst_ppc.hpp"
37 #include "oops/compressedOops.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/frame.inline.hpp"
40 #include "runtime/os.inline.hpp"
41 #include "runtime/safepointMechanism.inline.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "runtime/stubRoutines.hpp"
44 #include "runtime/vm_version.hpp"
45 #include "utilities/macros.hpp"
46 #include "utilities/powerOfTwo.hpp"
47
48 #define __ _masm->
49
50
51 const ConditionRegister LIR_Assembler::BOOL_RESULT = CR5;
52
53
54 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
55 Unimplemented(); return false; // Currently not used on this platform.
56 }
57
58
59 LIR_Opr LIR_Assembler::receiverOpr() {
60 return FrameMap::R3_oop_opr;
61 }
62
63
64 LIR_Opr LIR_Assembler::osrBufferPointer() {
65 return FrameMap::R3_opr;
66 }
67
68
69 // This specifies the stack pointer decrement needed to build the frame.
70 int LIR_Assembler::initial_frame_size_in_bytes() const {
71 return in_bytes(frame_map()->framesize_in_bytes());
72 }
73
74
75 // Inline cache check: the inline cached class is in inline_cache_reg;
76 // we fetch the class of the receiver and compare it with the cached class.
77 // If they do not match we jump to slow case.
78 int LIR_Assembler::check_icache() {
79 return __ ic_check(CodeEntryAlignment);
80 }
81
82 void LIR_Assembler::clinit_barrier(ciMethod* method) {
83 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
84
85 Label L_skip_barrier;
86 Register klass = R20;
87
88 metadata2reg(method->holder()->constant_encoding(), klass);
89 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
90
91 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
92 __ mtctr(klass);
93 __ bctr();
94
95 __ bind(L_skip_barrier);
96 }
97
98 void LIR_Assembler::osr_entry() {
99 // On-stack-replacement entry sequence:
100 //
101 // 1. Create a new compiled activation.
102 // 2. Initialize local variables in the compiled activation. The expression
103 // stack must be empty at the osr_bci; it is not initialized.
104 // 3. Jump to the continuation address in compiled code to resume execution.
105
106 // OSR entry point
107 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
108 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
109 ValueStack* entry_state = osr_entry->end()->state();
110 int number_of_locks = entry_state->locks_size();
111
112 // Create a frame for the compiled activation.
113 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
114
115 // OSR buffer is
116 //
117 // locals[nlocals-1..0]
118 // monitors[number_of_locks-1..0]
119 //
120 // Locals is a direct copy of the interpreter frame so in the osr buffer
121 // the first slot in the local array is the last local from the interpreter
122 // and the last slot is local[0] (receiver) from the interpreter.
123 //
124 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
125 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
126 // in the interpreter frame (the method lock if a sync method).
127
128 // Initialize monitors in the compiled activation.
129 // R3: pointer to osr buffer
130 //
131 // All other registers are dead at this point and the locals will be
132 // copied into place by code emitted in the IR.
133
134 Register OSR_buf = osrBufferPointer()->as_register();
135 {
136 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
137
138 const int locals_space = BytesPerWord * method()->max_locals();
139 int monitor_offset = locals_space + (2 * BytesPerWord) * (number_of_locks - 1);
140 bool use_OSR_bias = false;
141
142 if (!Assembler::is_simm16(monitor_offset + BytesPerWord) && number_of_locks > 0) {
143 // Offsets too large for ld instructions. Use bias.
144 __ add_const_optimized(OSR_buf, OSR_buf, locals_space);
145 monitor_offset -= locals_space;
146 use_OSR_bias = true;
147 }
148
149 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
150 // the OSR buffer using 2 word entries: first the lock and then
151 // the oop.
152 for (int i = 0; i < number_of_locks; i++) {
153 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
154 #ifdef ASSERT
155 // Verify the interpreter's monitor has a non-null object.
156 {
157 Label L;
158 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
159 __ cmpdi(CR0, R0, 0);
160 __ bne(CR0, L);
161 __ stop("locked object is null");
162 __ bind(L);
163 }
164 #endif // ASSERT
165 // Copy the lock field into the compiled activation.
166 Address ml = frame_map()->address_for_monitor_lock(i),
167 mo = frame_map()->address_for_monitor_object(i);
168 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
169 __ ld(R0, slot_offset + 0, OSR_buf);
170 __ std(R0, ml);
171 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
172 __ std(R0, mo);
173 }
174
175 if (use_OSR_bias) {
176 // Restore.
177 __ sub_const_optimized(OSR_buf, OSR_buf, locals_space);
178 }
179 }
180 }
181
182
183 int LIR_Assembler::emit_exception_handler() {
184 // Generate code for the exception handler.
185 address handler_base = __ start_a_stub(exception_handler_size());
186
187 if (handler_base == nullptr) {
188 // Not enough space left for the handler.
189 bailout("exception handler overflow");
190 return -1;
191 }
192
193 int offset = code_offset();
194 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id));
195 //__ load_const_optimized(R0, entry_point);
196 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
197 __ mtctr(R0);
198 __ bctr();
199
200 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
201 __ end_a_stub();
202
203 return offset;
204 }
205
206
207 // Emit the code to remove the frame from the stack in the exception
208 // unwind path.
209 int LIR_Assembler::emit_unwind_handler() {
210 _masm->block_comment("Unwind handler");
211
212 int offset = code_offset();
213 bool preserve_exception = method()->is_synchronized();
214 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
215
216 // Fetch the exception from TLS and clear out exception related thread state.
217 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
218 __ li(R0, 0);
219 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
220 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
221
222 __ bind(_unwind_handler_entry);
223 __ verify_not_null_oop(Rexception);
224 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
225
226 // Perform needed unlocking
227 MonitorExitStub* stub = nullptr;
228 if (method()->is_synchronized()) {
229 monitor_address(0, FrameMap::R4_opr);
230 stub = new MonitorExitStub(FrameMap::R4_opr, 0);
231 __ unlock_object(R5, R6, R4, *stub->entry());
232 __ bind(*stub->continuation());
233 }
234
235 // Dispatch to the unwind logic.
236 address unwind_stub = Runtime1::entry_for(StubId::c1_unwind_exception_id);
237 //__ load_const_optimized(R0, unwind_stub);
238 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
239 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
240 __ mtctr(R0);
241 __ bctr();
242
243 // Emit the slow path assembly.
244 if (stub != nullptr) {
245 stub->emit_code(this);
246 }
247
248 return offset;
249 }
250
251
252 int LIR_Assembler::emit_deopt_handler() {
253 // Generate code for deopt handler.
254 address handler_base = __ start_a_stub(deopt_handler_size());
255
256 if (handler_base == nullptr) {
257 // Not enough space left for the handler.
258 bailout("deopt handler overflow");
259 return -1;
260 }
261
262 int offset = code_offset();
263 Label start;
264
265 __ bind(start);
266 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
267 int entry_offset = __ offset();
268 __ b(start);
269
270 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
271 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
272 "out of bounds read in post-call NOP check");
273 __ end_a_stub();
274
275 return entry_offset;
276 }
277
278
279 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
280 if (o == nullptr) {
281 __ li(reg, 0);
282 } else {
283 AddressLiteral addrlit = __ constant_oop_address(o);
284 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
285 }
286 }
287
288
289 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
290 // Allocate a new index in table to hold the object once it's been patched.
291 int oop_index = __ oop_recorder()->allocate_oop_index(nullptr);
292 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
293
294 AddressLiteral addrlit((address)nullptr, oop_Relocation::spec(oop_index));
295 __ load_const(reg, addrlit, R0);
296
297 patching_epilog(patch, lir_patch_normal, reg, info);
298 }
299
300
301 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
302 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
303 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
304 }
305
306
307 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
308 // Allocate a new index in table to hold the klass once it's been patched.
309 int index = __ oop_recorder()->allocate_metadata_index(nullptr);
310 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
311
312 AddressLiteral addrlit((address)nullptr, metadata_Relocation::spec(index));
313 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
314 __ load_const(reg, addrlit, R0);
315
316 patching_epilog(patch, lir_patch_normal, reg, info);
317 }
318
319
320 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
321 const bool is_int = result->is_single_cpu();
322 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
323 Register Rdivisor = noreg;
324 Register Rscratch = temp->as_register();
325 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
326 long divisor = -1;
327
328 if (right->is_register()) {
329 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
330 } else {
331 divisor = is_int ? right->as_constant_ptr()->as_jint()
332 : right->as_constant_ptr()->as_jlong();
333 }
334
335 assert(Rdividend != Rscratch, "");
336 assert(Rdivisor != Rscratch, "");
337 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
338
339 if (Rdivisor == noreg) {
340 if (divisor == 1) { // stupid, but can happen
341 if (code == lir_idiv) {
342 __ mr_if_needed(Rresult, Rdividend);
343 } else {
344 __ li(Rresult, 0);
345 }
346
347 } else if (is_power_of_2(divisor)) {
348 // Convert division by a power of two into some shifts and logical operations.
349 int log2 = log2i_exact(divisor);
350
351 // Round towards 0.
352 if (divisor == 2) {
353 if (is_int) {
354 __ srwi(Rscratch, Rdividend, 31);
355 } else {
356 __ srdi(Rscratch, Rdividend, 63);
357 }
358 } else {
359 if (is_int) {
360 __ srawi(Rscratch, Rdividend, 31);
361 } else {
362 __ sradi(Rscratch, Rdividend, 63);
363 }
364 __ clrldi(Rscratch, Rscratch, 64-log2);
365 }
366 __ add(Rscratch, Rdividend, Rscratch);
367
368 if (code == lir_idiv) {
369 if (is_int) {
370 __ srawi(Rresult, Rscratch, log2);
371 } else {
372 __ sradi(Rresult, Rscratch, log2);
373 }
374 } else { // lir_irem
375 __ clrrdi(Rscratch, Rscratch, log2);
376 __ sub(Rresult, Rdividend, Rscratch);
377 }
378
379 } else if (divisor == -1) {
380 if (code == lir_idiv) {
381 __ neg(Rresult, Rdividend);
382 } else {
383 __ li(Rresult, 0);
384 }
385
386 } else {
387 __ load_const_optimized(Rscratch, divisor);
388 if (code == lir_idiv) {
389 if (is_int) {
390 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
391 } else {
392 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
393 }
394 } else {
395 assert(Rscratch != R0, "need both");
396 if (is_int) {
397 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
398 __ mullw(Rscratch, R0, Rscratch);
399 } else {
400 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
401 __ mulld(Rscratch, R0, Rscratch);
402 }
403 __ sub(Rresult, Rdividend, Rscratch);
404 }
405
406 }
407 return;
408 }
409
410 Label regular, done;
411 if (is_int) {
412 __ cmpwi(CR0, Rdivisor, -1);
413 } else {
414 __ cmpdi(CR0, Rdivisor, -1);
415 }
416 __ bne(CR0, regular);
417 if (code == lir_idiv) {
418 __ neg(Rresult, Rdividend);
419 __ b(done);
420 __ bind(regular);
421 if (is_int) {
422 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
423 } else {
424 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
425 }
426 } else { // lir_irem
427 __ li(Rresult, 0);
428 __ b(done);
429 __ bind(regular);
430 if (is_int) {
431 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
432 __ mullw(Rscratch, Rscratch, Rdivisor);
433 } else {
434 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
435 __ mulld(Rscratch, Rscratch, Rdivisor);
436 }
437 __ sub(Rresult, Rdividend, Rscratch);
438 }
439 __ bind(done);
440 }
441
442
443 void LIR_Assembler::emit_op3(LIR_Op3* op) {
444 switch (op->code()) {
445 case lir_idiv:
446 case lir_irem:
447 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
448 op->result_opr(), op->info());
449 break;
450 case lir_fmad:
451 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
452 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
453 break;
454 case lir_fmaf:
455 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
456 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
457 break;
458 default: ShouldNotReachHere(); break;
459 }
460 }
461
462
463 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
464 #ifdef ASSERT
465 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
466 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
467 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
468 assert(op->info() == nullptr, "shouldn't have CodeEmitInfo");
469 #endif
470
471 Label *L = op->label();
472 if (op->cond() == lir_cond_always) {
473 __ b(*L);
474 } else {
475 Label done;
476 bool is_unordered = false;
477 if (op->code() == lir_cond_float_branch) {
478 assert(op->ublock() != nullptr, "must have unordered successor");
479 is_unordered = true;
480 } else {
481 assert(op->code() == lir_branch, "just checking");
482 }
483
484 bool positive = false;
485 Assembler::Condition cond = Assembler::equal;
486 switch (op->cond()) {
487 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
488 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
489 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
490 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
491 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
492 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
493 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
494 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
495 default: ShouldNotReachHere();
496 }
497 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
498 int bi = Assembler::bi0(BOOL_RESULT, cond);
499 if (is_unordered) {
500 if (positive) {
501 if (op->ublock() == op->block()) {
502 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
503 }
504 } else {
505 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
506 }
507 }
508 __ bc_far_optimized(bo, bi, *L);
509 __ bind(done);
510 }
511 }
512
513
514 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
515 Bytecodes::Code code = op->bytecode();
516 LIR_Opr src = op->in_opr(),
517 dst = op->result_opr();
518
519 switch(code) {
520 case Bytecodes::_i2l: {
521 __ extsw(dst->as_register_lo(), src->as_register());
522 break;
523 }
524 case Bytecodes::_l2i: {
525 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
526 break;
527 }
528 case Bytecodes::_i2b: {
529 __ extsb(dst->as_register(), src->as_register());
530 break;
531 }
532 case Bytecodes::_i2c: {
533 __ clrldi(dst->as_register(), src->as_register(), 64-16);
534 break;
535 }
536 case Bytecodes::_i2s: {
537 __ extsh(dst->as_register(), src->as_register());
538 break;
539 }
540 case Bytecodes::_i2d:{
541 FloatRegister rdst = dst->as_double_reg();
542 // move src to dst register
543 __ mtfprwa(rdst, src->as_register());
544 __ fcfid(rdst, rdst);
545 break;
546 }
547 case Bytecodes::_l2d: {
548 FloatRegister rdst = dst->as_double_reg();
549 // move src to dst register
550 __ mtfprd(rdst, src->as_register_lo());
551 __ fcfid(rdst, rdst);
552 break;
553 }
554 case Bytecodes::_i2f:{
555 FloatRegister rdst = dst->as_float_reg();
556 // move src to dst register
557 __ mtfprwa(rdst, src->as_register());
558 __ fcfids(rdst, rdst);
559 break;
560 }
561 case Bytecodes::_l2f: {
562 FloatRegister rdst = dst->as_float_reg();
563 // move src to dst register
564 __ mtfprd(rdst, src->as_register_lo());
565 __ fcfids(rdst, rdst);
566 break;
567 }
568 case Bytecodes::_f2d: {
569 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
570 break;
571 }
572 case Bytecodes::_d2f: {
573 __ frsp(dst->as_float_reg(), src->as_double_reg());
574 break;
575 }
576 case Bytecodes::_d2i:
577 case Bytecodes::_f2i: {
578 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
579 Label L;
580 // Result must be 0 if value is NaN; test by comparing value to itself.
581 __ fcmpu(CR0, rsrc, rsrc);
582 __ li(dst->as_register(), 0);
583 __ bso(CR0, L);
584 __ fctiwz(rsrc, rsrc); // USE_KILL
585 __ mffprd(dst->as_register(), rsrc);
586 __ bind(L);
587 break;
588 }
589 case Bytecodes::_d2l:
590 case Bytecodes::_f2l: {
591 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
592 Label L;
593 // Result must be 0 if value is NaN; test by comparing value to itself.
594 __ fcmpu(CR0, rsrc, rsrc);
595 __ li(dst->as_register_lo(), 0);
596 __ bso(CR0, L);
597 __ fctidz(rsrc, rsrc); // USE_KILL
598 __ mffprd(dst->as_register_lo(), rsrc);
599 __ bind(L);
600 break;
601 }
602
603 default: ShouldNotReachHere();
604 }
605 }
606
607
608 void LIR_Assembler::align_call(LIR_Code) {
609 // do nothing since all instructions are word aligned on ppc
610 }
611
612 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
613 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
614
615 address call_pc = __ trampoline_call(AddressLiteral(op->addr(), rtype));
616 if (call_pc == nullptr) {
617 bailout("const/stub overflow in call with trampoline");
618 return;
619 }
620 add_call_info(code_offset(), op->info());
621 __ post_call_nop();
622 }
623
624 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
625 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
626 bool success = __ ic_call(R2_TOC, op->addr());
627 if (!success) {
628 bailout("const/stub overflow in ic_call with trampoline");
629 return;
630 }
631 add_call_info(code_offset(), op->info());
632 __ post_call_nop();
633 }
634
635 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
636 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
637 __ null_check(addr, stub->entry());
638 append_code_stub(stub);
639 }
640
641
642 // Attention: caller must encode oop if needed
643 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
644 int store_offset;
645 if (!Assembler::is_simm16(offset)) {
646 // For offsets larger than a simm16 we setup the offset.
647 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
648 __ load_const_optimized(R0, offset);
649 store_offset = store(from_reg, base, R0, type, wide);
650 } else {
651 store_offset = code_offset();
652 switch (type) {
653 case T_BOOLEAN: // fall through
654 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
655 case T_CHAR :
656 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
657 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
658 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
659 case T_ADDRESS:
660 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
661 case T_ARRAY : // fall through
662 case T_OBJECT:
663 {
664 if (UseCompressedOops && !wide) {
665 // Encoding done in caller
666 __ stw(from_reg->as_register(), offset, base);
667 __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
668 } else {
669 __ std(from_reg->as_register(), offset, base);
670 if (VerifyOops) {
671 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
672 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
673 }
674 }
675 break;
676 }
677 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
678 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
679 default : ShouldNotReachHere();
680 }
681 }
682 return store_offset;
683 }
684
685
686 // Attention: caller must encode oop if needed
687 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
688 int store_offset = code_offset();
689 switch (type) {
690 case T_BOOLEAN: // fall through
691 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
692 case T_CHAR :
693 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
694 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
695 case T_LONG :
696 #ifdef _LP64
697 __ stdx(from_reg->as_register_lo(), base, disp);
698 #else
699 Unimplemented();
700 #endif
701 break;
702 case T_ADDRESS:
703 __ stdx(from_reg->as_register(), base, disp);
704 break;
705 case T_ARRAY : // fall through
706 case T_OBJECT:
707 {
708 if (UseCompressedOops && !wide) {
709 // Encoding done in caller.
710 __ stwx(from_reg->as_register(), base, disp);
711 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
712 } else {
713 __ stdx(from_reg->as_register(), base, disp);
714 if (VerifyOops) {
715 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
716 bs->check_oop(_masm, from_reg->as_register(), FILE_AND_LINE); // kills R0
717 }
718 }
719 break;
720 }
721 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
722 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
723 default : ShouldNotReachHere();
724 }
725 return store_offset;
726 }
727
728
729 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
730 int load_offset;
731 if (!Assembler::is_simm16(offset)) {
732 // For offsets larger than a simm16 we setup the offset.
733 __ load_const_optimized(R0, offset);
734 load_offset = load(base, R0, to_reg, type, wide);
735 } else {
736 load_offset = code_offset();
737 switch(type) {
738 case T_BOOLEAN: // fall through
739 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
740 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
741 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
742 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
743 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
744 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
745 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
746 case T_ADDRESS:
747 __ ld(to_reg->as_register(), offset, base);
748 break;
749 case T_ARRAY : // fall through
750 case T_OBJECT:
751 {
752 if (UseCompressedOops && !wide) {
753 __ lwz(to_reg->as_register(), offset, base);
754 __ decode_heap_oop(to_reg->as_register());
755 } else {
756 __ ld(to_reg->as_register(), offset, base);
757 }
758 break;
759 }
760 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
761 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
762 default : ShouldNotReachHere();
763 }
764 }
765 return load_offset;
766 }
767
768
769 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
770 int load_offset = code_offset();
771 switch(type) {
772 case T_BOOLEAN: // fall through
773 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
774 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
775 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
776 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
777 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
778 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
779 case T_ARRAY : // fall through
780 case T_OBJECT:
781 {
782 if (UseCompressedOops && !wide) {
783 __ lwzx(to_reg->as_register(), base, disp);
784 __ decode_heap_oop(to_reg->as_register());
785 } else {
786 __ ldx(to_reg->as_register(), base, disp);
787 }
788 break;
789 }
790 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
791 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
792 case T_LONG :
793 #ifdef _LP64
794 __ ldx(to_reg->as_register_lo(), base, disp);
795 #else
796 Unimplemented();
797 #endif
798 break;
799 default : ShouldNotReachHere();
800 }
801 return load_offset;
802 }
803
804
805 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
806 LIR_Const* c = src->as_constant_ptr();
807 Register src_reg = R0;
808 switch (c->type()) {
809 case T_INT:
810 case T_FLOAT: {
811 int value = c->as_jint_bits();
812 __ load_const_optimized(src_reg, value);
813 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
814 __ stw(src_reg, addr);
815 break;
816 }
817 case T_ADDRESS: {
818 int value = c->as_jint_bits();
819 __ load_const_optimized(src_reg, value);
820 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
821 __ std(src_reg, addr);
822 break;
823 }
824 case T_OBJECT: {
825 jobject2reg(c->as_jobject(), src_reg);
826 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
827 __ std(src_reg, addr);
828 break;
829 }
830 case T_LONG:
831 case T_DOUBLE: {
832 int value = c->as_jlong_bits();
833 __ load_const_optimized(src_reg, value);
834 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
835 __ std(src_reg, addr);
836 break;
837 }
838 default:
839 Unimplemented();
840 }
841 }
842
843
844 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
845 LIR_Const* c = src->as_constant_ptr();
846 LIR_Address* addr = dest->as_address_ptr();
847 Register base = addr->base()->as_pointer_register();
848 LIR_Opr tmp = LIR_OprFact::illegalOpr;
849 int offset = -1;
850 // Null check for large offsets in LIRGenerator::do_StoreField.
851 bool needs_explicit_null_check = !ImplicitNullChecks;
852
853 if (info != nullptr && needs_explicit_null_check) {
854 explicit_null_check(base, info);
855 }
856
857 switch (c->type()) {
858 case T_FLOAT: type = T_INT;
859 case T_INT:
860 case T_ADDRESS: {
861 tmp = FrameMap::R0_opr;
862 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
863 break;
864 }
865 case T_DOUBLE: type = T_LONG;
866 case T_LONG: {
867 tmp = FrameMap::R0_long_opr;
868 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
869 break;
870 }
871 case T_OBJECT: {
872 tmp = FrameMap::R0_opr;
873 if (UseCompressedOops && !wide && c->as_jobject() != nullptr) {
874 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
875 // Don't care about sign extend (will use stw).
876 __ lis(R0, 0); // Will get patched.
877 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
878 __ ori(R0, R0, 0); // Will get patched.
879 } else {
880 jobject2reg(c->as_jobject(), R0);
881 }
882 break;
883 }
884 default:
885 Unimplemented();
886 }
887
888 // Handle either reg+reg or reg+disp address.
889 if (addr->index()->is_valid()) {
890 assert(addr->disp() == 0, "must be zero");
891 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
892 } else {
893 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
894 offset = store(tmp, base, addr->disp(), type, wide);
895 }
896
897 if (info != nullptr) {
898 assert(offset != -1, "offset should've been set");
899 if (!needs_explicit_null_check) {
900 add_debug_info_for_null_check(offset, info);
901 }
902 }
903 }
904
905
906 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
907 LIR_Const* c = src->as_constant_ptr();
908 LIR_Opr to_reg = dest;
909
910 switch (c->type()) {
911 case T_INT: {
912 assert(patch_code == lir_patch_none, "no patching handled here");
913 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
914 break;
915 }
916 case T_ADDRESS: {
917 assert(patch_code == lir_patch_none, "no patching handled here");
918 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
919 break;
920 }
921 case T_LONG: {
922 assert(patch_code == lir_patch_none, "no patching handled here");
923 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
924 break;
925 }
926
927 case T_OBJECT: {
928 if (patch_code == lir_patch_none) {
929 jobject2reg(c->as_jobject(), to_reg->as_register());
930 } else {
931 jobject2reg_with_patching(to_reg->as_register(), info);
932 }
933 break;
934 }
935
936 case T_METADATA:
937 {
938 if (patch_code == lir_patch_none) {
939 metadata2reg(c->as_metadata(), to_reg->as_register());
940 } else {
941 klass2reg_with_patching(to_reg->as_register(), info);
942 }
943 }
944 break;
945
946 case T_FLOAT:
947 {
948 if (to_reg->is_single_fpu()) {
949 address const_addr = __ float_constant(c->as_jfloat());
950 if (const_addr == nullptr) {
951 bailout("const section overflow");
952 break;
953 }
954 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
955 __ relocate(rspec);
956 __ load_const(R0, const_addr);
957 __ lfsx(to_reg->as_float_reg(), R0);
958 } else {
959 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
960 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
961 }
962 }
963 break;
964
965 case T_DOUBLE:
966 {
967 if (to_reg->is_double_fpu()) {
968 address const_addr = __ double_constant(c->as_jdouble());
969 if (const_addr == nullptr) {
970 bailout("const section overflow");
971 break;
972 }
973 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
974 __ relocate(rspec);
975 __ load_const(R0, const_addr);
976 __ lfdx(to_reg->as_double_reg(), R0);
977 } else {
978 assert(to_reg->is_double_cpu(), "Must be a long register.");
979 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
980 }
981 }
982 break;
983
984 default:
985 ShouldNotReachHere();
986 }
987 }
988
989
990 Address LIR_Assembler::as_Address(LIR_Address* addr) {
991 Unimplemented(); return Address();
992 }
993
994
995 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
996 if (addr->index()->is_illegal()) {
997 return (RegisterOrConstant)(addr->disp());
998 } else {
999 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1000 }
1001 }
1002
1003
1004 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1005 const Register tmp = R0;
1006 switch (type) {
1007 case T_INT:
1008 case T_FLOAT: {
1009 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1010 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1011 __ lwz(tmp, from);
1012 __ stw(tmp, to);
1013 break;
1014 }
1015 case T_ADDRESS:
1016 case T_OBJECT: {
1017 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1018 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1019 __ ld(tmp, from);
1020 __ std(tmp, to);
1021 break;
1022 }
1023 case T_LONG:
1024 case T_DOUBLE: {
1025 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1026 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1027 __ ld(tmp, from);
1028 __ std(tmp, to);
1029 break;
1030 }
1031
1032 default:
1033 ShouldNotReachHere();
1034 }
1035 }
1036
1037
1038 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1039 Unimplemented(); return Address();
1040 }
1041
1042
1043 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1044 Unimplemented(); return Address();
1045 }
1046
1047
1048 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1049 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1050
1051 assert(type != T_METADATA, "load of metadata ptr not supported");
1052 LIR_Address* addr = src_opr->as_address_ptr();
1053 LIR_Opr to_reg = dest;
1054
1055 Register src = addr->base()->as_pointer_register();
1056 Register disp_reg = noreg;
1057 int disp_value = addr->disp();
1058 bool needs_patching = (patch_code != lir_patch_none);
1059 // null check for large offsets in LIRGenerator::do_LoadField
1060 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1061
1062 if (info != nullptr && needs_explicit_null_check) {
1063 explicit_null_check(src, info);
1064 }
1065
1066 if (addr->base()->type() == T_OBJECT) {
1067 __ verify_oop(src, FILE_AND_LINE);
1068 }
1069
1070 PatchingStub* patch = nullptr;
1071 if (needs_patching) {
1072 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1073 assert(!to_reg->is_double_cpu() ||
1074 patch_code == lir_patch_none ||
1075 patch_code == lir_patch_normal, "patching doesn't match register");
1076 }
1077
1078 if (addr->index()->is_illegal()) {
1079 if (!Assembler::is_simm16(disp_value)) {
1080 if (needs_patching) {
1081 __ load_const32(R0, 0); // patchable int
1082 } else {
1083 __ load_const_optimized(R0, disp_value);
1084 }
1085 disp_reg = R0;
1086 }
1087 } else {
1088 disp_reg = addr->index()->as_pointer_register();
1089 assert(disp_value == 0, "can't handle 3 operand addresses");
1090 }
1091
1092 // Remember the offset of the load. The patching_epilog must be done
1093 // before the call to add_debug_info, otherwise the PcDescs don't get
1094 // entered in increasing order.
1095 int offset;
1096
1097 if (disp_reg == noreg) {
1098 assert(Assembler::is_simm16(disp_value), "should have set this up");
1099 offset = load(src, disp_value, to_reg, type, wide);
1100 } else {
1101 offset = load(src, disp_reg, to_reg, type, wide);
1102 }
1103
1104 if (patch != nullptr) {
1105 patching_epilog(patch, patch_code, src, info);
1106 }
1107 if (info != nullptr && !needs_explicit_null_check) {
1108 add_debug_info_for_null_check(offset, info);
1109 }
1110 }
1111
1112
1113 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1114 Address addr;
1115 if (src->is_single_word()) {
1116 addr = frame_map()->address_for_slot(src->single_stack_ix());
1117 } else if (src->is_double_word()) {
1118 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1119 }
1120
1121 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1122 }
1123
1124
1125 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type) {
1126 Address addr;
1127 if (dest->is_single_word()) {
1128 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1129 } else if (dest->is_double_word()) {
1130 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1131 }
1132
1133 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1134 }
1135
1136
1137 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1138 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1139 if (from_reg->is_double_fpu()) {
1140 // double to double moves
1141 assert(to_reg->is_double_fpu(), "should match");
1142 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1143 } else {
1144 // float to float moves
1145 assert(to_reg->is_single_fpu(), "should match");
1146 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1147 }
1148 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1149 if (from_reg->is_double_cpu()) {
1150 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1151 } else if (to_reg->is_double_cpu()) {
1152 // int to int moves
1153 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1154 } else {
1155 // int to int moves
1156 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1157 }
1158 } else {
1159 ShouldNotReachHere();
1160 }
1161 if (is_reference_type(to_reg->type())) {
1162 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1163 }
1164 }
1165
1166
1167 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1168 LIR_PatchCode patch_code, CodeEmitInfo* info,
1169 bool wide) {
1170 assert(type != T_METADATA, "store of metadata ptr not supported");
1171 LIR_Address* addr = dest->as_address_ptr();
1172
1173 Register src = addr->base()->as_pointer_register();
1174 Register disp_reg = noreg;
1175 int disp_value = addr->disp();
1176 bool needs_patching = (patch_code != lir_patch_none);
1177 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1178 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1179 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1180 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1181 // Null check for large offsets in LIRGenerator::do_StoreField.
1182 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1183
1184 if (info != nullptr && needs_explicit_null_check) {
1185 explicit_null_check(src, info);
1186 }
1187
1188 if (addr->base()->is_oop_register()) {
1189 __ verify_oop(src, FILE_AND_LINE);
1190 }
1191
1192 PatchingStub* patch = nullptr;
1193 if (needs_patching) {
1194 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1195 assert(!from_reg->is_double_cpu() ||
1196 patch_code == lir_patch_none ||
1197 patch_code == lir_patch_normal, "patching doesn't match register");
1198 }
1199
1200 if (addr->index()->is_illegal()) {
1201 if (load_disp) {
1202 disp_reg = use_R29 ? R29_TOC : R0;
1203 if (needs_patching) {
1204 __ load_const32(disp_reg, 0); // patchable int
1205 } else {
1206 __ load_const_optimized(disp_reg, disp_value);
1207 }
1208 }
1209 } else {
1210 disp_reg = addr->index()->as_pointer_register();
1211 assert(disp_value == 0, "can't handle 3 operand addresses");
1212 }
1213
1214 // remember the offset of the store. The patching_epilog must be done
1215 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1216 // entered in increasing order.
1217 int offset;
1218
1219 if (compress_oop) {
1220 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1221 from_reg = FrameMap::as_opr(co);
1222 }
1223
1224 if (disp_reg == noreg) {
1225 assert(Assembler::is_simm16(disp_value), "should have set this up");
1226 offset = store(from_reg, src, disp_value, type, wide);
1227 } else {
1228 offset = store(from_reg, src, disp_reg, type, wide);
1229 }
1230
1231 if (use_R29) {
1232 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1233 }
1234
1235 if (patch != nullptr) {
1236 patching_epilog(patch, patch_code, src, info);
1237 }
1238
1239 if (info != nullptr && !needs_explicit_null_check) {
1240 add_debug_info_for_null_check(offset, info);
1241 }
1242 }
1243
1244
1245 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1246 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1247 const Register temp = R12;
1248
1249 // Pop the stack before the safepoint code.
1250 int frame_size = initial_frame_size_in_bytes();
1251 if (Assembler::is_simm(frame_size, 16)) {
1252 __ addi(R1_SP, R1_SP, frame_size);
1253 } else {
1254 __ pop_frame();
1255 }
1256
1257 // Restore return pc relative to callers' sp.
1258 __ ld(return_pc, _abi0(lr), R1_SP);
1259 // Move return pc to LR.
1260 __ mtlr(return_pc);
1261
1262 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1263 __ reserved_stack_check(return_pc);
1264 }
1265
1266 // We need to mark the code position where the load from the safepoint
1267 // polling page was emitted as relocInfo::poll_return_type here.
1268 if (!UseSIGTRAP) {
1269 code_stub->set_safepoint_offset(__ offset());
1270 __ relocate(relocInfo::poll_return_type);
1271 }
1272 __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1273
1274 // Return.
1275 __ blr();
1276 }
1277
1278
1279 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1280 const Register poll_addr = tmp->as_register();
1281 __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1282 if (info != nullptr) {
1283 add_debug_info_for_branch(info);
1284 }
1285 int offset = __ offset();
1286 __ relocate(relocInfo::poll_type);
1287 __ load_from_polling_page(poll_addr);
1288
1289 return offset;
1290 }
1291
1292
1293 void LIR_Assembler::emit_static_call_stub() {
1294 address call_pc = __ pc();
1295 address stub = __ start_a_stub(static_call_stub_size());
1296 if (stub == nullptr) {
1297 bailout("static call stub overflow");
1298 return;
1299 }
1300
1301 // For java_to_interp stubs we use R11_scratch1 as scratch register
1302 // and in call trampoline stubs we use R12_scratch2. This way we
1303 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1304 const Register reg_scratch = R11_scratch1;
1305
1306 // Create a static stub relocation which relates this stub
1307 // with the call instruction at insts_call_instruction_offset in the
1308 // instructions code-section.
1309 int start = __ offset();
1310 __ relocate(static_stub_Relocation::spec(call_pc));
1311
1312 // Now, create the stub's code:
1313 // - load the TOC
1314 // - load the inline cache oop from the constant pool
1315 // - load the call target from the constant pool
1316 // - call
1317 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1318 AddressLiteral ic = __ allocate_metadata_address((Metadata *)nullptr);
1319 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1320
1321 if (ReoptimizeCallSequences) {
1322 __ b64_patchable((address)-1, relocInfo::none);
1323 } else {
1324 AddressLiteral a((address)-1);
1325 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1326 __ mtctr(reg_scratch);
1327 __ bctr();
1328 }
1329 if (!success) {
1330 bailout("const section overflow");
1331 return;
1332 }
1333
1334 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1335 __ end_a_stub();
1336 }
1337
1338
1339 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1340 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1341 if (opr1->is_single_fpu()) {
1342 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1343 } else if (opr1->is_double_fpu()) {
1344 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1345 } else if (opr1->is_single_cpu()) {
1346 if (opr2->is_constant()) {
1347 switch (opr2->as_constant_ptr()->type()) {
1348 case T_INT:
1349 {
1350 jint con = opr2->as_constant_ptr()->as_jint();
1351 if (unsigned_comp) {
1352 if (Assembler::is_uimm(con, 16)) {
1353 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1354 } else {
1355 __ load_const_optimized(R0, con);
1356 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1357 }
1358 } else {
1359 if (Assembler::is_simm(con, 16)) {
1360 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1361 } else {
1362 __ load_const_optimized(R0, con);
1363 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1364 }
1365 }
1366 }
1367 break;
1368
1369 case T_OBJECT:
1370 // There are only equal/notequal comparisons on objects.
1371 {
1372 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1373 jobject con = opr2->as_constant_ptr()->as_jobject();
1374 if (con == nullptr) {
1375 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1376 } else {
1377 jobject2reg(con, R0);
1378 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1379 }
1380 }
1381 break;
1382
1383 case T_METADATA:
1384 // We only need, for now, comparison with null for metadata.
1385 {
1386 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1387 Metadata* p = opr2->as_constant_ptr()->as_metadata();
1388 if (p == nullptr) {
1389 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1390 } else {
1391 ShouldNotReachHere();
1392 }
1393 }
1394 break;
1395
1396 default:
1397 ShouldNotReachHere();
1398 break;
1399 }
1400 } else {
1401 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1402 if (is_reference_type(opr1->type())) {
1403 // There are only equal/notequal comparisons on objects.
1404 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1405 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1406 } else {
1407 if (unsigned_comp) {
1408 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1409 } else {
1410 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1411 }
1412 }
1413 }
1414 } else if (opr1->is_double_cpu()) {
1415 if (opr2->is_constant()) {
1416 jlong con = opr2->as_constant_ptr()->as_jlong();
1417 if (unsigned_comp) {
1418 if (Assembler::is_uimm(con, 16)) {
1419 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1420 } else {
1421 __ load_const_optimized(R0, con);
1422 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1423 }
1424 } else {
1425 if (Assembler::is_simm(con, 16)) {
1426 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1427 } else {
1428 __ load_const_optimized(R0, con);
1429 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1430 }
1431 }
1432 } else if (opr2->is_register()) {
1433 if (unsigned_comp) {
1434 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1435 } else {
1436 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1437 }
1438 } else {
1439 ShouldNotReachHere();
1440 }
1441 } else {
1442 ShouldNotReachHere();
1443 }
1444 }
1445
1446
1447 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1448 const Register Rdst = dst->as_register();
1449 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1450 bool is_unordered_less = (code == lir_ucmp_fd2i);
1451 if (left->is_single_fpu()) {
1452 __ fcmpu(CR0, left->as_float_reg(), right->as_float_reg());
1453 } else if (left->is_double_fpu()) {
1454 __ fcmpu(CR0, left->as_double_reg(), right->as_double_reg());
1455 } else {
1456 ShouldNotReachHere();
1457 }
1458 __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1459 } else if (code == lir_cmp_l2i) {
1460 __ cmpd(CR0, left->as_register_lo(), right->as_register_lo());
1461 __ set_cmp3(Rdst); // set result as follows: <: -1, =: 0, >: 1
1462 } else {
1463 ShouldNotReachHere();
1464 }
1465 }
1466
1467
1468 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1469 if (src->is_constant()) {
1470 lasm->const2reg(src, dst, lir_patch_none, nullptr);
1471 } else if (src->is_register()) {
1472 lasm->reg2reg(src, dst);
1473 } else if (src->is_stack()) {
1474 lasm->stack2reg(src, dst, dst->type());
1475 } else {
1476 ShouldNotReachHere();
1477 }
1478 }
1479
1480 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1481 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1482 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
1483
1484 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1485 load_to_reg(this, opr1, result); // Condition doesn't matter.
1486 return;
1487 }
1488
1489 bool positive = false;
1490 Assembler::Condition cond = Assembler::equal;
1491 switch (condition) {
1492 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1493 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1494 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1495 case lir_cond_belowEqual:
1496 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1497 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1498 case lir_cond_aboveEqual:
1499 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1500 default: ShouldNotReachHere();
1501 }
1502
1503 if (result->is_cpu_register()) {
1504 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1505 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1506
1507 // We can use result_reg to load one operand if not already in register.
1508 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1509 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1510
1511 if (first != second) {
1512 if (!o1_is_reg) {
1513 load_to_reg(this, opr1, result);
1514 }
1515
1516 if (!o2_is_reg) {
1517 load_to_reg(this, opr2, result);
1518 }
1519
1520 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1521 return;
1522 }
1523 } // isel
1524
1525 load_to_reg(this, opr1, result);
1526
1527 Label skip;
1528 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1529 int bi = Assembler::bi0(BOOL_RESULT, cond);
1530 __ bc(bo, bi, skip);
1531
1532 load_to_reg(this, opr2, result);
1533 __ bind(skip);
1534 }
1535
1536
1537 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1538 CodeEmitInfo* info) {
1539 assert(info == nullptr, "unused on this code path");
1540 assert(left->is_register(), "wrong items state");
1541 assert(dest->is_register(), "wrong items state");
1542
1543 if (right->is_register()) {
1544 if (dest->is_float_kind()) {
1545
1546 FloatRegister lreg, rreg, res;
1547 if (right->is_single_fpu()) {
1548 lreg = left->as_float_reg();
1549 rreg = right->as_float_reg();
1550 res = dest->as_float_reg();
1551 switch (code) {
1552 case lir_add: __ fadds(res, lreg, rreg); break;
1553 case lir_sub: __ fsubs(res, lreg, rreg); break;
1554 case lir_mul: __ fmuls(res, lreg, rreg); break;
1555 case lir_div: __ fdivs(res, lreg, rreg); break;
1556 default: ShouldNotReachHere();
1557 }
1558 } else {
1559 lreg = left->as_double_reg();
1560 rreg = right->as_double_reg();
1561 res = dest->as_double_reg();
1562 switch (code) {
1563 case lir_add: __ fadd(res, lreg, rreg); break;
1564 case lir_sub: __ fsub(res, lreg, rreg); break;
1565 case lir_mul: __ fmul(res, lreg, rreg); break;
1566 case lir_div: __ fdiv(res, lreg, rreg); break;
1567 default: ShouldNotReachHere();
1568 }
1569 }
1570
1571 } else if (dest->is_double_cpu()) {
1572
1573 Register dst_lo = dest->as_register_lo();
1574 Register op1_lo = left->as_pointer_register();
1575 Register op2_lo = right->as_pointer_register();
1576
1577 switch (code) {
1578 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1579 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1580 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1581 default: ShouldNotReachHere();
1582 }
1583 } else {
1584 assert (right->is_single_cpu(), "Just Checking");
1585
1586 Register lreg = left->as_register();
1587 Register res = dest->as_register();
1588 Register rreg = right->as_register();
1589 switch (code) {
1590 case lir_add: __ add (res, lreg, rreg); break;
1591 case lir_sub: __ sub (res, lreg, rreg); break;
1592 case lir_mul: __ mullw(res, lreg, rreg); break;
1593 default: ShouldNotReachHere();
1594 }
1595 }
1596 } else {
1597 assert (right->is_constant(), "must be constant");
1598
1599 if (dest->is_single_cpu()) {
1600 Register lreg = left->as_register();
1601 Register res = dest->as_register();
1602 int simm16 = right->as_constant_ptr()->as_jint();
1603
1604 switch (code) {
1605 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1606 simm16 = -simm16;
1607 case lir_add: if (res == lreg && simm16 == 0) break;
1608 __ addi(res, lreg, simm16); break;
1609 case lir_mul: if (res == lreg && simm16 == 1) break;
1610 __ mulli(res, lreg, simm16); break;
1611 default: ShouldNotReachHere();
1612 }
1613 } else {
1614 Register lreg = left->as_pointer_register();
1615 Register res = dest->as_register_lo();
1616 long con = right->as_constant_ptr()->as_jlong();
1617 assert(Assembler::is_simm16(con), "must be simm16");
1618
1619 switch (code) {
1620 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1621 con = -con;
1622 case lir_add: if (res == lreg && con == 0) break;
1623 __ addi(res, lreg, (int)con); break;
1624 case lir_mul: if (res == lreg && con == 1) break;
1625 __ mulli(res, lreg, (int)con); break;
1626 default: ShouldNotReachHere();
1627 }
1628 }
1629 }
1630 }
1631
1632
1633 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1634 switch (code) {
1635 case lir_sqrt: {
1636 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1637 break;
1638 }
1639 case lir_abs: {
1640 __ fabs(dest->as_double_reg(), value->as_double_reg());
1641 break;
1642 }
1643 case lir_f2hf: {
1644 __ f2hf(dest.as_register(), value.as_float_reg(), tmp.as_float_reg());
1645 break;
1646 }
1647 case lir_hf2f: {
1648 __ hf2f(dest->as_float_reg(), value.as_register());
1649 break;
1650 }
1651 default: {
1652 ShouldNotReachHere();
1653 break;
1654 }
1655 }
1656 }
1657
1658
1659 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1660 if (right->is_constant()) { // see do_LogicOp
1661 long uimm;
1662 Register d, l;
1663 if (dest->is_single_cpu()) {
1664 uimm = right->as_constant_ptr()->as_jint();
1665 d = dest->as_register();
1666 l = left->as_register();
1667 } else {
1668 uimm = right->as_constant_ptr()->as_jlong();
1669 d = dest->as_register_lo();
1670 l = left->as_register_lo();
1671 }
1672 long uimms = (unsigned long)uimm >> 16;
1673
1674 switch (code) {
1675 case lir_logic_and:
1676 if (Assembler::andi_supports(uimm)) {
1677 __ andi(d, l, uimm); // includes andis_ and special cases
1678 } else { // for operands which are not generated by LIRGenerator::do_LogicOp
1679 __ load_const_optimized(R0, uimm);
1680 __ andr(d, l, R0);
1681 }
1682 break;
1683
1684 case lir_logic_or:
1685 if (Assembler::is_uimm(uimm, 16)) {
1686 __ ori(d, l, uimm);
1687 } else if ((uimm & 0xFFFF) == 0 && Assembler::is_uimm(uimms, 16)) {
1688 __ oris(d, l, uimms);
1689 } else { // for operands which are not generated by LIRGenerator::do_LogicOp
1690 __ load_const_optimized(R0, uimm);
1691 __ orr(d, l, R0);
1692 }
1693 break;
1694
1695 case lir_logic_xor:
1696 if (Assembler::is_uimm(uimm, 16)) {
1697 __ xori(d, l, uimm);
1698 } else if ((uimm & 0xFFFF) == 0 && Assembler::is_uimm(uimms, 16)) {
1699 __ xoris(d, l, uimms);
1700 } else if (uimm == -1) {
1701 __ nand(d, l, l); // special case
1702 } else { // for operands which are not generated by LIRGenerator::do_LogicOp
1703 __ load_const_optimized(R0, uimm);
1704 __ xorr(d, l, R0);
1705 }
1706 break;
1707
1708 default: ShouldNotReachHere();
1709 }
1710 } else {
1711 assert(right->is_register(), "right should be in register");
1712
1713 if (dest->is_single_cpu()) {
1714 switch (code) {
1715 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1716 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1717 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1718 default: ShouldNotReachHere();
1719 }
1720 } else {
1721 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1722 left->as_register_lo();
1723 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1724 right->as_register_lo();
1725
1726 switch (code) {
1727 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1728 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1729 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1730 default: ShouldNotReachHere();
1731 }
1732 }
1733 }
1734 }
1735
1736
1737 int LIR_Assembler::shift_amount(BasicType t) {
1738 int elem_size = type2aelembytes(t);
1739 switch (elem_size) {
1740 case 1 : return 0;
1741 case 2 : return 1;
1742 case 4 : return 2;
1743 case 8 : return 3;
1744 }
1745 ShouldNotReachHere();
1746 return -1;
1747 }
1748
1749
1750 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1751 info->add_register_oop(exceptionOop);
1752
1753 // Reuse the debug info from the safepoint poll for the throw op itself.
1754 address pc_for_athrow = __ pc();
1755 int pc_for_athrow_offset = __ offset();
1756 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1757 //__ relocate(rspec);
1758 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1759 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1760 add_call_info(pc_for_athrow_offset, info); // for exception handler
1761
1762 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? StubId::c1_handle_exception_id
1763 : StubId::c1_handle_exception_nofpu_id);
1764 //__ load_const_optimized(R0, stub);
1765 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1766 __ mtctr(R0);
1767 __ bctr();
1768 }
1769
1770
1771 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1772 // Note: Not used with EnableDebuggingOnDemand.
1773 assert(exceptionOop->as_register() == R3, "should match");
1774 __ b(_unwind_handler_entry);
1775 }
1776
1777
1778 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1779 Register src = op->src()->as_register();
1780 Register dst = op->dst()->as_register();
1781 Register src_pos = op->src_pos()->as_register();
1782 Register dst_pos = op->dst_pos()->as_register();
1783 Register length = op->length()->as_register();
1784 Register tmp = op->tmp()->as_register();
1785 Register tmp2 = R0;
1786
1787 int flags = op->flags();
1788 ciArrayKlass* default_type = op->expected_type();
1789 BasicType basic_type = (default_type != nullptr) ? default_type->element_type()->basic_type() : T_ILLEGAL;
1790 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1791
1792 // Set up the arraycopy stub information.
1793 ArrayCopyStub* stub = op->stub();
1794
1795 // Always do stub if no type information is available. It's ok if
1796 // the known type isn't loaded since the code sanity checks
1797 // in debug mode and the type isn't required when we know the exact type
1798 // also check that the type is an array type.
1799 if (default_type == nullptr) {
1800 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1801 length->is_nonvolatile(), "must preserve");
1802 address copyfunc_addr = StubRoutines::generic_arraycopy();
1803 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
1804
1805 // 3 parms are int. Convert to long.
1806 __ mr(R3_ARG1, src);
1807 __ extsw(R4_ARG2, src_pos);
1808 __ mr(R5_ARG3, dst);
1809 __ extsw(R6_ARG4, dst_pos);
1810 __ extsw(R7_ARG5, length);
1811
1812 #ifndef PRODUCT
1813 if (PrintC1Statistics) {
1814 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1815 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1816 __ lwz(R11_scratch1, simm16_offs, tmp);
1817 __ addi(R11_scratch1, R11_scratch1, 1);
1818 __ stw(R11_scratch1, simm16_offs, tmp);
1819 }
1820 #endif
1821 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
1822
1823 __ nand(tmp, R3_RET, R3_RET);
1824 __ subf(length, tmp, length);
1825 __ add(src_pos, tmp, src_pos);
1826 __ add(dst_pos, tmp, dst_pos);
1827
1828 __ cmpwi(CR0, R3_RET, 0);
1829 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CR0, Assembler::less), *stub->entry());
1830 __ bind(*stub->continuation());
1831 return;
1832 }
1833
1834 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
1835 Label cont, slow, copyfunc;
1836
1837 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1838 LIR_OpArrayCopy::dst_null_check |
1839 LIR_OpArrayCopy::src_pos_positive_check |
1840 LIR_OpArrayCopy::dst_pos_positive_check |
1841 LIR_OpArrayCopy::length_positive_check);
1842
1843 // Use only one conditional branch for simple checks.
1844 if (simple_check_flag_set) {
1845 ConditionRegister combined_check = CR1, tmp_check = CR1;
1846
1847 // Make sure src and dst are non-null.
1848 if (flags & LIR_OpArrayCopy::src_null_check) {
1849 __ cmpdi(combined_check, src, 0);
1850 tmp_check = CR0;
1851 }
1852
1853 if (flags & LIR_OpArrayCopy::dst_null_check) {
1854 __ cmpdi(tmp_check, dst, 0);
1855 if (tmp_check != combined_check) {
1856 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1857 }
1858 tmp_check = CR0;
1859 }
1860
1861 // Clear combined_check.eq if not already used.
1862 if (tmp_check == combined_check) {
1863 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1864 tmp_check = CR0;
1865 }
1866
1867 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1868 // Test src_pos register.
1869 __ cmpwi(tmp_check, src_pos, 0);
1870 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1871 }
1872
1873 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1874 // Test dst_pos register.
1875 __ cmpwi(tmp_check, dst_pos, 0);
1876 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1877 }
1878
1879 if (flags & LIR_OpArrayCopy::length_positive_check) {
1880 // Make sure length isn't negative.
1881 __ cmpwi(tmp_check, length, 0);
1882 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1883 }
1884
1885 __ beq(combined_check, slow);
1886 }
1887
1888 // If the compiler was not able to prove that exact type of the source or the destination
1889 // of the arraycopy is an array type, check at runtime if the source or the destination is
1890 // an instance type.
1891 if (flags & LIR_OpArrayCopy::type_check) {
1892 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1893 __ load_klass(tmp, dst);
1894 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1895 __ cmpwi(CR0, tmp2, Klass::_lh_neutral_value);
1896 __ bge(CR0, slow);
1897 }
1898
1899 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1900 __ load_klass(tmp, src);
1901 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1902 __ cmpwi(CR0, tmp2, Klass::_lh_neutral_value);
1903 __ bge(CR0, slow);
1904 }
1905 }
1906
1907 // Higher 32bits must be null.
1908 __ extsw(length, length);
1909
1910 __ extsw(src_pos, src_pos);
1911 if (flags & LIR_OpArrayCopy::src_range_check) {
1912 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1913 __ add(tmp, length, src_pos);
1914 __ cmpld(CR0, tmp2, tmp);
1915 __ ble(CR0, slow);
1916 }
1917
1918 __ extsw(dst_pos, dst_pos);
1919 if (flags & LIR_OpArrayCopy::dst_range_check) {
1920 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1921 __ add(tmp, length, dst_pos);
1922 __ cmpld(CR0, tmp2, tmp);
1923 __ ble(CR0, slow);
1924 }
1925
1926 int shift = shift_amount(basic_type);
1927
1928 if (!(flags & LIR_OpArrayCopy::type_check)) {
1929 if (stub != nullptr) {
1930 __ b(cont);
1931 __ bind(slow);
1932 __ b(*stub->entry());
1933 }
1934 } else {
1935 // We don't know the array types are compatible.
1936 if (basic_type != T_OBJECT) {
1937 // Simple test for basic type arrays.
1938 __ cmp_klasses_from_objects(CR0, src, dst, tmp, tmp2);
1939 __ beq(CR0, cont);
1940 } else {
1941 // For object arrays, if src is a sub class of dst then we can
1942 // safely do the copy.
1943 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1944
1945 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
1946 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
1947
1948 __ load_klass(sub_klass, src);
1949 __ load_klass(super_klass, dst);
1950
1951 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
1952 &cont, copyfunc_addr != nullptr ? ©func : &slow, nullptr);
1953
1954 address slow_stc = Runtime1::entry_for(StubId::c1_slow_subtype_check_id);
1955 //__ load_const_optimized(tmp, slow_stc, tmp2);
1956 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
1957 __ mtctr(tmp);
1958 __ bctrl(); // sets CR0
1959 __ beq(CR0, cont);
1960
1961 if (copyfunc_addr != nullptr) { // Use stub if available.
1962 __ bind(copyfunc);
1963 // Src is not a sub class of dst so we have to do a
1964 // per-element check.
1965 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
1966 if ((flags & mask) != mask) {
1967 assert(flags & mask, "one of the two should be known to be an object array");
1968
1969 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1970 __ load_klass(tmp, src);
1971 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1972 __ load_klass(tmp, dst);
1973 }
1974
1975 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1976
1977 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
1978 __ load_const_optimized(tmp, objArray_lh);
1979 __ cmpw(CR0, tmp, tmp2);
1980 __ bne(CR0, slow);
1981 }
1982
1983 Register src_ptr = R3_ARG1;
1984 Register dst_ptr = R4_ARG2;
1985 Register len = R5_ARG3;
1986 Register chk_off = R6_ARG4;
1987 Register super_k = R7_ARG5;
1988
1989 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
1990 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
1991 if (shift == 0) {
1992 __ add(src_ptr, src_pos, src_ptr);
1993 __ add(dst_ptr, dst_pos, dst_ptr);
1994 } else {
1995 __ sldi(tmp, src_pos, shift);
1996 __ sldi(tmp2, dst_pos, shift);
1997 __ add(src_ptr, tmp, src_ptr);
1998 __ add(dst_ptr, tmp2, dst_ptr);
1999 }
2000
2001 __ load_klass(tmp, dst);
2002 __ mr(len, length);
2003
2004 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2005 __ ld(super_k, ek_offset, tmp);
2006
2007 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2008 __ lwz(chk_off, sco_offset, super_k);
2009
2010 __ call_c(copyfunc_addr, relocInfo::runtime_call_type);
2011
2012 #ifndef PRODUCT
2013 if (PrintC1Statistics) {
2014 Label failed;
2015 __ cmpwi(CR0, R3_RET, 0);
2016 __ bne(CR0, failed);
2017 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2018 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2019 __ lwz(R11_scratch1, simm16_offs, tmp);
2020 __ addi(R11_scratch1, R11_scratch1, 1);
2021 __ stw(R11_scratch1, simm16_offs, tmp);
2022 __ bind(failed);
2023 }
2024 #endif
2025
2026 __ nand(tmp, R3_RET, R3_RET);
2027 __ cmpwi(CR0, R3_RET, 0);
2028 __ beq(CR0, *stub->continuation());
2029
2030 #ifndef PRODUCT
2031 if (PrintC1Statistics) {
2032 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2033 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2034 __ lwz(R11_scratch1, simm16_offs, tmp);
2035 __ addi(R11_scratch1, R11_scratch1, 1);
2036 __ stw(R11_scratch1, simm16_offs, tmp);
2037 }
2038 #endif
2039
2040 __ subf(length, tmp, length);
2041 __ add(src_pos, tmp, src_pos);
2042 __ add(dst_pos, tmp, dst_pos);
2043 }
2044 }
2045 __ bind(slow);
2046 __ b(*stub->entry());
2047 }
2048 __ bind(cont);
2049
2050 #ifdef ASSERT
2051 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2052 // Sanity check the known type with the incoming class. For the
2053 // primitive case the types must match exactly with src.klass and
2054 // dst.klass each exactly matching the default type. For the
2055 // object array case, if no type check is needed then either the
2056 // dst type is exactly the expected type and the src type is a
2057 // subtype which we can't check or src is the same array as dst
2058 // but not necessarily exactly of type default_type.
2059 Label known_ok, halt;
2060 metadata2reg(default_type->constant_encoding(), tmp);
2061 __ cmp_klass(CR0, dst, tmp, R11_scratch1, R12_scratch2);
2062 if (basic_type != T_OBJECT) {
2063 __ bne(CR0, halt);
2064 __ cmp_klass(CR0, src, tmp, R11_scratch1, R12_scratch2);
2065 __ beq(CR0, known_ok);
2066 } else {
2067 __ beq(CR0, known_ok);
2068 __ cmpw(CR0, src, dst);
2069 __ beq(CR0, known_ok);
2070 }
2071 __ bind(halt);
2072 __ stop("incorrect type information in arraycopy");
2073 __ bind(known_ok);
2074 }
2075 #endif
2076
2077 #ifndef PRODUCT
2078 if (PrintC1Statistics) {
2079 address counter = Runtime1::arraycopy_count_address(basic_type);
2080 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2081 __ lwz(R11_scratch1, simm16_offs, tmp);
2082 __ addi(R11_scratch1, R11_scratch1, 1);
2083 __ stw(R11_scratch1, simm16_offs, tmp);
2084 }
2085 #endif
2086
2087 Register src_ptr = R3_ARG1;
2088 Register dst_ptr = R4_ARG2;
2089 Register len = R5_ARG3;
2090
2091 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2092 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2093 if (shift == 0) {
2094 __ add(src_ptr, src_pos, src_ptr);
2095 __ add(dst_ptr, dst_pos, dst_ptr);
2096 } else {
2097 __ sldi(tmp, src_pos, shift);
2098 __ sldi(tmp2, dst_pos, shift);
2099 __ add(src_ptr, tmp, src_ptr);
2100 __ add(dst_ptr, tmp2, dst_ptr);
2101 }
2102
2103 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2104 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2105 const char *name;
2106 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2107
2108 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2109 __ mr(len, length);
2110 __ call_c(entry, relocInfo::runtime_call_type);
2111
2112 if (stub != nullptr) {
2113 __ bind(*stub->continuation());
2114 }
2115 }
2116
2117
2118 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2119 if (dest->is_single_cpu()) {
2120 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2121 #ifdef _LP64
2122 if (left->type() == T_OBJECT) {
2123 switch (code) {
2124 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2125 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2126 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2127 default: ShouldNotReachHere();
2128 }
2129 } else
2130 #endif
2131 switch (code) {
2132 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2133 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2134 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2135 default: ShouldNotReachHere();
2136 }
2137 } else {
2138 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2139 switch (code) {
2140 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2141 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2142 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2143 default: ShouldNotReachHere();
2144 }
2145 }
2146 }
2147
2148
2149 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2150 #ifdef _LP64
2151 if (left->type() == T_OBJECT) {
2152 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2153 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2154 else {
2155 switch (code) {
2156 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2157 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2158 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2159 default: ShouldNotReachHere();
2160 }
2161 }
2162 return;
2163 }
2164 #endif
2165
2166 if (dest->is_single_cpu()) {
2167 count = count & 0x1F; // Java spec
2168 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2169 else {
2170 switch (code) {
2171 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2172 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2173 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2174 default: ShouldNotReachHere();
2175 }
2176 }
2177 } else if (dest->is_double_cpu()) {
2178 count = count & 63; // Java spec
2179 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2180 else {
2181 switch (code) {
2182 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2183 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2184 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2185 default: ShouldNotReachHere();
2186 }
2187 }
2188 } else {
2189 ShouldNotReachHere();
2190 }
2191 }
2192
2193
2194 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2195 if (op->init_check()) {
2196 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2197 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2198 } else {
2199 add_debug_info_for_null_check_here(op->stub()->info());
2200 }
2201 __ lbz(op->tmp1()->as_register(),
2202 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2203 // acquire barrier included in membar_storestore() which follows the allocation immediately.
2204 __ cmpwi(CR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2205 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CR0, Assembler::equal), *op->stub()->entry());
2206 }
2207 __ allocate_object(op->obj()->as_register(),
2208 op->tmp1()->as_register(),
2209 op->tmp2()->as_register(),
2210 op->tmp3()->as_register(),
2211 op->header_size(),
2212 op->object_size(),
2213 op->klass()->as_register(),
2214 *op->stub()->entry());
2215
2216 __ bind(*op->stub()->continuation());
2217 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2218 }
2219
2220
2221 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2222 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2223 if (UseSlowPath ||
2224 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2225 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2226 __ b(*op->stub()->entry());
2227 } else {
2228 __ allocate_array(op->obj()->as_register(),
2229 op->len()->as_register(),
2230 op->tmp1()->as_register(),
2231 op->tmp2()->as_register(),
2232 op->tmp3()->as_register(),
2233 arrayOopDesc::base_offset_in_bytes(op->type()),
2234 type2aelembytes(op->type()),
2235 op->klass()->as_register(),
2236 *op->stub()->entry(),
2237 op->zero_array());
2238 }
2239 __ bind(*op->stub()->continuation());
2240 }
2241
2242
2243 // kills recv
2244 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2245 ciMethodData *md, ciProfileData *data,
2246 Register recv, Register tmp) {
2247 int mdp_offset = md->byte_offset_of_slot(data, in_ByteSize(0)) - mdo_offset_bias;
2248 __ profile_receiver_type(recv, mdo, mdp_offset, tmp, noreg);
2249 }
2250
2251
2252 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2253 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2254 md = method->method_data_or_null();
2255 assert(md != nullptr, "Sanity");
2256 data = md->bci_to_data(bci);
2257 assert(data != nullptr, "need data for checkcast");
2258 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2259 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2260 // The offset is large so bias the mdo by the base of the slot so
2261 // that the ld can use simm16s to reference the slots of the data.
2262 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2263 }
2264 }
2265
2266
2267 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2268 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2269 Register k_RInfo = op->tmp1()->as_register();
2270 Register klass_RInfo = op->tmp2()->as_register();
2271 Register Rtmp1 = op->tmp3()->as_register();
2272 Register dst = op->result_opr()->as_register();
2273 ciKlass* k = op->klass();
2274 bool should_profile = op->should_profile();
2275 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2276 bool reg_conflict = false;
2277 if (obj == k_RInfo) {
2278 k_RInfo = dst;
2279 reg_conflict = true;
2280 } else if (obj == klass_RInfo) {
2281 klass_RInfo = dst;
2282 reg_conflict = true;
2283 } else if (obj == Rtmp1) {
2284 Rtmp1 = dst;
2285 reg_conflict = true;
2286 }
2287 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2288
2289 ciMethodData* md = nullptr;
2290 ciProfileData* data = nullptr;
2291 int mdo_offset_bias = 0;
2292 if (should_profile) {
2293 ciMethod* method = op->profiled_method();
2294 assert(method != nullptr, "Should have method");
2295 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2296
2297 Register mdo = k_RInfo;
2298 Register data_val = Rtmp1;
2299 Label not_null;
2300 metadata2reg(md->constant_encoding(), mdo);
2301 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2302 __ cmpdi(CR0, obj, 0);
2303 __ bne(CR0, not_null);
2304 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2305 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2306 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2307 __ b(*obj_is_null);
2308 __ bind(not_null);
2309
2310 Register recv = klass_RInfo;
2311 __ load_klass(recv, obj);
2312 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1); // kills recv
2313 } else {
2314 __ cmpdi(CR0, obj, 0);
2315 __ beq(CR0, *obj_is_null);
2316 }
2317
2318 // get object class
2319 __ load_klass(klass_RInfo, obj);
2320
2321 if (k->is_loaded()) {
2322 metadata2reg(k->constant_encoding(), k_RInfo);
2323 } else {
2324 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2325 }
2326
2327 if (op->fast_check()) {
2328 assert_different_registers(klass_RInfo, k_RInfo);
2329 __ cmpd(CR0, k_RInfo, klass_RInfo);
2330 __ beq(CR0, *success);
2331 // Fall through to failure case.
2332 } else {
2333 bool need_slow_path = true;
2334 if (k->is_loaded()) {
2335 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2336 need_slow_path = false;
2337 }
2338 // Perform the fast part of the checking logic.
2339 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success : nullptr),
2340 failure, nullptr, RegisterOrConstant(k->super_check_offset()));
2341 } else {
2342 // Perform the fast part of the checking logic.
2343 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success, failure);
2344 }
2345 if (!need_slow_path) {
2346 __ b(*success);
2347 } else {
2348 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2349 address entry = Runtime1::entry_for(StubId::c1_slow_subtype_check_id);
2350 // Stub needs fixed registers (tmp1-3).
2351 Register original_k_RInfo = op->tmp1()->as_register();
2352 Register original_klass_RInfo = op->tmp2()->as_register();
2353 Register original_Rtmp1 = op->tmp3()->as_register();
2354 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2355 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2356 __ mr_if_needed(original_k_RInfo, k_RInfo);
2357 __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2358 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2359 //__ load_const_optimized(original_Rtmp1, entry, R0);
2360 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2361 __ mtctr(original_Rtmp1);
2362 __ bctrl(); // sets CR0
2363 if (keep_obj_alive) { __ mr(obj, dst); }
2364 __ beq(CR0, *success);
2365 // Fall through to failure case.
2366 }
2367 }
2368
2369 __ bind(*failure);
2370 }
2371
2372
2373 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2374 LIR_Code code = op->code();
2375 if (code == lir_store_check) {
2376 Register value = op->object()->as_register();
2377 Register array = op->array()->as_register();
2378 Register k_RInfo = op->tmp1()->as_register();
2379 Register klass_RInfo = op->tmp2()->as_register();
2380 Register Rtmp1 = op->tmp3()->as_register();
2381 bool should_profile = op->should_profile();
2382
2383 __ verify_oop(value, FILE_AND_LINE);
2384 CodeStub* stub = op->stub();
2385 // Check if it needs to be profiled.
2386 ciMethodData* md = nullptr;
2387 ciProfileData* data = nullptr;
2388 int mdo_offset_bias = 0;
2389 if (should_profile) {
2390 ciMethod* method = op->profiled_method();
2391 assert(method != nullptr, "Should have method");
2392 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2393 }
2394
2395 Label done;
2396
2397 if (should_profile) {
2398 Label not_null;
2399 Register mdo = k_RInfo;
2400 Register data_val = Rtmp1;
2401 metadata2reg(md->constant_encoding(), mdo);
2402 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2403 __ cmpdi(CR0, value, 0);
2404 __ bne(CR0, not_null);
2405 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2406 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2407 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2408 __ b(done);
2409 __ bind(not_null);
2410
2411 Register recv = klass_RInfo;
2412 __ load_klass(recv, value);
2413 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1); // kills recv
2414 } else {
2415 __ cmpdi(CR0, value, 0);
2416 __ beq(CR0, done);
2417 }
2418 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2419 explicit_null_check(array, op->info_for_exception());
2420 } else {
2421 add_debug_info_for_null_check_here(op->info_for_exception());
2422 }
2423 __ load_klass(k_RInfo, array);
2424 __ load_klass(klass_RInfo, value);
2425
2426 Label failure;
2427
2428 // Get instance klass.
2429 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2430 // Perform the fast part of the checking logic.
2431 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, &done, &failure, nullptr);
2432
2433 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2434 const address slow_path = Runtime1::entry_for(StubId::c1_slow_subtype_check_id);
2435 //__ load_const_optimized(R0, slow_path);
2436 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2437 __ mtctr(R0);
2438 __ bctrl(); // sets CR0
2439 __ beq(CR0, done);
2440
2441 __ bind(failure);
2442 __ b(*stub->entry());
2443 __ align(32, 12);
2444 __ bind(done);
2445
2446 } else if (code == lir_checkcast) {
2447 Label success, failure;
2448 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2449 __ b(*op->stub()->entry());
2450 __ align(32, 12);
2451 __ bind(success);
2452 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2453 } else if (code == lir_instanceof) {
2454 Register dst = op->result_opr()->as_register();
2455 Label success, failure, done;
2456 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2457 __ li(dst, 0);
2458 __ b(done);
2459 __ align(32, 12);
2460 __ bind(success);
2461 __ li(dst, 1);
2462 __ bind(done);
2463 } else {
2464 ShouldNotReachHere();
2465 }
2466 }
2467
2468
2469 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2470 Register addr = op->addr()->as_pointer_register();
2471 Register cmp_value = noreg, new_value = noreg;
2472 bool is_64bit = false;
2473
2474 if (op->code() == lir_cas_long) {
2475 cmp_value = op->cmp_value()->as_register_lo();
2476 new_value = op->new_value()->as_register_lo();
2477 is_64bit = true;
2478 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2479 cmp_value = op->cmp_value()->as_register();
2480 new_value = op->new_value()->as_register();
2481 if (op->code() == lir_cas_obj) {
2482 if (UseCompressedOops) {
2483 Register t1 = op->tmp1()->as_register();
2484 Register t2 = op->tmp2()->as_register();
2485 cmp_value = __ encode_heap_oop(t1, cmp_value);
2486 new_value = __ encode_heap_oop(t2, new_value);
2487 } else {
2488 is_64bit = true;
2489 }
2490 }
2491 } else {
2492 Unimplemented();
2493 }
2494
2495 // There might be a volatile load before this Unsafe CAS.
2496 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2497 __ sync();
2498 } else {
2499 __ lwsync();
2500 }
2501
2502 if (is_64bit) {
2503 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2504 MacroAssembler::MemBarNone,
2505 MacroAssembler::cmpxchgx_hint_atomic_update(),
2506 noreg, nullptr, /*check without ldarx first*/true);
2507 } else {
2508 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2509 MacroAssembler::MemBarNone,
2510 MacroAssembler::cmpxchgx_hint_atomic_update(),
2511 noreg, nullptr, /*check without ldarx first*/true);
2512 }
2513
2514 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2515 __ isync();
2516 } else {
2517 __ sync();
2518 }
2519 }
2520
2521 void LIR_Assembler::breakpoint() {
2522 __ illtrap();
2523 }
2524
2525
2526 void LIR_Assembler::push(LIR_Opr opr) {
2527 Unimplemented();
2528 }
2529
2530 void LIR_Assembler::pop(LIR_Opr opr) {
2531 Unimplemented();
2532 }
2533
2534
2535 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2536 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2537 Register dst = dst_opr->as_register();
2538 Register reg = mon_addr.base();
2539 int offset = mon_addr.disp();
2540 // Compute pointer to BasicLock.
2541 __ add_const_optimized(dst, reg, offset);
2542 }
2543
2544
2545 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2546 Register obj = op->obj_opr()->as_register();
2547 Register hdr = op->hdr_opr()->as_register();
2548 Register lock = op->lock_opr()->as_register();
2549
2550 // Obj may not be an oop.
2551 if (op->code() == lir_lock) {
2552 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2553 // Add debug info for NullPointerException only if one is possible.
2554 if (op->info() != nullptr) {
2555 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2556 explicit_null_check(obj, op->info());
2557 } else {
2558 add_debug_info_for_null_check_here(op->info());
2559 }
2560 }
2561 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2562 } else {
2563 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2564 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2565 }
2566 __ bind(*op->stub()->continuation());
2567 }
2568
2569 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2570 Register obj = op->obj()->as_pointer_register();
2571 Register result = op->result_opr()->as_pointer_register();
2572
2573 CodeEmitInfo* info = op->info();
2574 if (info != nullptr) {
2575 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2576 explicit_null_check(obj, info);
2577 } else {
2578 add_debug_info_for_null_check_here(info);
2579 }
2580 }
2581
2582 __ load_klass(result, obj);
2583 }
2584
2585 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2586 ciMethod* method = op->profiled_method();
2587 int bci = op->profiled_bci();
2588 ciMethod* callee = op->profiled_callee();
2589
2590 // Update counter for all call types.
2591 ciMethodData* md = method->method_data_or_null();
2592 assert(md != nullptr, "Sanity");
2593 ciProfileData* data = md->bci_to_data(bci);
2594 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2595 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2596 Register mdo = op->mdo()->as_register();
2597 #ifdef _LP64
2598 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2599 Register tmp1 = op->tmp1()->as_register_lo();
2600 #else
2601 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2602 Register tmp1 = op->tmp1()->as_register();
2603 #endif
2604 metadata2reg(md->constant_encoding(), mdo);
2605 int mdo_offset_bias = 0;
2606 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2607 data->size_in_bytes())) {
2608 // The offset is large so bias the mdo by the base of the slot so
2609 // that the ld can use simm16s to reference the slots of the data.
2610 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2611 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2612 }
2613
2614 // Perform additional virtual call profiling for invokevirtual and
2615 // invokeinterface bytecodes
2616 if (op->should_profile_receiver_type()) {
2617 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2618 Register recv = op->recv()->as_register();
2619 assert_different_registers(mdo, tmp1, recv);
2620 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2621 ciKlass* known_klass = op->known_holder();
2622 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2623 // We know the type that will be seen at this call site; we can
2624 // statically update the MethodData* rather than needing to do
2625 // dynamic tests on the receiver type.
2626 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2627 for (uint i = 0; i < VirtualCallData::row_limit(); i++) {
2628 ciKlass* receiver = vc_data->receiver(i);
2629 if (known_klass->equals(receiver)) {
2630 __ increment_mem64(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias,
2631 DataLayout::counter_increment, tmp1);
2632 return;
2633 }
2634 }
2635
2636 // Receiver type is not found in profile data.
2637 // Fall back to runtime helper to handle the rest at runtime.
2638 metadata2reg(known_klass->constant_encoding(), recv);
2639 } else {
2640 __ load_klass(recv, recv);
2641 }
2642 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1); // kills recv
2643 } else {
2644 // Static call
2645 __ increment_mem64(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias,
2646 DataLayout::counter_increment, tmp1);
2647 }
2648 }
2649
2650
2651 void LIR_Assembler::align_backward_branch_target() {
2652 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2653 }
2654
2655
2656 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2657 // tmp must be unused
2658 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2659 assert(left->is_register(), "can only handle registers");
2660
2661 if (left->is_single_cpu()) {
2662 __ neg(dest->as_register(), left->as_register());
2663 } else if (left->is_single_fpu()) {
2664 __ fneg(dest->as_float_reg(), left->as_float_reg());
2665 } else if (left->is_double_fpu()) {
2666 __ fneg(dest->as_double_reg(), left->as_double_reg());
2667 } else {
2668 assert (left->is_double_cpu(), "Must be a long");
2669 __ neg(dest->as_register_lo(), left->as_register_lo());
2670 }
2671 }
2672
2673
2674 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2675 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2676 // Stubs: Called via rt_call, but dest is a stub address (no FunctionDescriptor).
2677 if (dest == Runtime1::entry_for(StubId::c1_register_finalizer_id) ||
2678 dest == Runtime1::entry_for(StubId::c1_new_multi_array_id ) ||
2679 dest == Runtime1::entry_for(StubId::c1_is_instance_of_id )) {
2680 assert(CodeCache::contains(dest), "simplified call is only for special C1 stubs");
2681 //__ load_const_optimized(R0, dest);
2682 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2683 __ mtctr(R0);
2684 __ bctrl();
2685 if (info != nullptr) {
2686 add_call_info_here(info);
2687 __ post_call_nop();
2688 }
2689 return;
2690 }
2691
2692 __ call_c(dest, relocInfo::runtime_call_type);
2693 assert(__ last_calls_return_pc() == __ pc(), "pcn not at return pc");
2694 if (info != nullptr) {
2695 add_call_info_here(info);
2696 __ post_call_nop();
2697 }
2698 }
2699
2700
2701 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2702 ShouldNotReachHere(); // Not needed on _LP64.
2703 }
2704
2705 void LIR_Assembler::membar() {
2706 __ fence();
2707 }
2708
2709 void LIR_Assembler::membar_acquire() {
2710 __ acquire();
2711 }
2712
2713 void LIR_Assembler::membar_release() {
2714 __ release();
2715 }
2716
2717 void LIR_Assembler::membar_loadload() {
2718 __ membar(Assembler::LoadLoad);
2719 }
2720
2721 void LIR_Assembler::membar_storestore() {
2722 __ membar(Assembler::StoreStore);
2723 }
2724
2725 void LIR_Assembler::membar_loadstore() {
2726 __ membar(Assembler::LoadStore);
2727 }
2728
2729 void LIR_Assembler::membar_storeload() {
2730 __ membar(Assembler::StoreLoad);
2731 }
2732
2733 void LIR_Assembler::on_spin_wait() {
2734 // SMT priority hint: drop to low for the spin, then restore to medium so
2735 // subsequent code is not penalised.
2736 // Yield (or 27,27,27) is not used because it was never implemented on Power CPUs, see JDK-8201218.
2737 __ block_comment("spin_wait {");
2738 __ smt_prio_low();
2739 __ smt_prio_medium();
2740 __ block_comment("}");
2741 }
2742
2743 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2744 LIR_Address* addr = addr_opr->as_address_ptr();
2745 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2746
2747 if (addr->index()->is_illegal()) {
2748 if (patch_code != lir_patch_none) {
2749 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2750 __ load_const32(R0, 0); // patchable int
2751 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2752 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2753 } else {
2754 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2755 }
2756 } else {
2757 assert(patch_code == lir_patch_none, "Patch code not supported");
2758 assert(addr->disp() == 0, "can't have both: index and disp");
2759 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2760 }
2761 }
2762
2763
2764 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2765 ShouldNotReachHere();
2766 }
2767
2768
2769 #ifdef ASSERT
2770 // Emit run-time assertion.
2771 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2772 Unimplemented();
2773 }
2774 #endif
2775
2776
2777 void LIR_Assembler::peephole(LIR_List* lir) {
2778 // Optimize instruction pairs before emitting.
2779 LIR_OpList* inst = lir->instructions_list();
2780 for (int i = 1; i < inst->length(); i++) {
2781 LIR_Op* op = inst->at(i);
2782
2783 // 2 register-register-moves
2784 if (op->code() == lir_move) {
2785 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2786 res2 = ((LIR_Op1*)op)->result_opr();
2787 if (in2->is_register() && res2->is_register()) {
2788 LIR_Op* prev = inst->at(i - 1);
2789 if (prev && prev->code() == lir_move) {
2790 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2791 res1 = ((LIR_Op1*)prev)->result_opr();
2792 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2793 inst->remove_at(i);
2794 }
2795 }
2796 }
2797 }
2798
2799 }
2800 return;
2801 }
2802
2803
2804 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2805 const LIR_Address *addr = src->as_address_ptr();
2806 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2807 const Register Rptr = addr->base()->as_pointer_register(),
2808 Rtmp = tmp->as_register();
2809 Register Robj = noreg;
2810 if (data->is_oop()) {
2811 if (UseCompressedOops) {
2812 Robj = __ encode_heap_oop(Rtmp, data->as_register());
2813 } else {
2814 Robj = data->as_register();
2815 if (Robj == dest->as_register()) { // May happen with ZGC.
2816 __ mr(Rtmp, Robj);
2817 Robj = Rtmp;
2818 }
2819 }
2820 }
2821
2822 // There might be a volatile load before this Unsafe OP.
2823 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2824 __ sync();
2825 } else {
2826 __ lwsync();
2827 }
2828
2829 Label Lretry;
2830 __ bind(Lretry);
2831
2832 if (data->type() == T_INT) {
2833 const Register Rold = dest->as_register(),
2834 Rsrc = data->as_register();
2835 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2836 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2837 if (code == lir_xadd) {
2838 __ add(Rtmp, Rsrc, Rold);
2839 __ stwcx_(Rtmp, Rptr);
2840 } else {
2841 __ stwcx_(Rsrc, Rptr);
2842 }
2843 } else if (data->is_oop()) {
2844 assert(code == lir_xchg, "xadd for oops");
2845 const Register Rold = dest->as_register();
2846 assert_different_registers(Rptr, Rold, Robj);
2847 if (UseCompressedOops) {
2848 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2849 __ stwcx_(Robj, Rptr);
2850 } else {
2851 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2852 __ stdcx_(Robj, Rptr);
2853 }
2854 } else if (data->type() == T_LONG) {
2855 const Register Rold = dest->as_register_lo(),
2856 Rsrc = data->as_register_lo();
2857 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2858 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2859 if (code == lir_xadd) {
2860 __ add(Rtmp, Rsrc, Rold);
2861 __ stdcx_(Rtmp, Rptr);
2862 } else {
2863 __ stdcx_(Rsrc, Rptr);
2864 }
2865 } else {
2866 ShouldNotReachHere();
2867 }
2868
2869 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
2870 __ bne_predict_not_taken(CR0, Lretry);
2871 } else {
2872 __ bne( CR0, Lretry);
2873 }
2874
2875 if (UseCompressedOops && data->is_oop()) {
2876 __ decode_heap_oop(dest->as_register());
2877 }
2878
2879 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2880 __ isync();
2881 } else {
2882 __ sync();
2883 }
2884 }
2885
2886
2887 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2888 Register obj = op->obj()->as_register();
2889 Register tmp = op->tmp()->as_pointer_register();
2890 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
2891 ciKlass* exact_klass = op->exact_klass();
2892 intptr_t current_klass = op->current_klass();
2893 bool not_null = op->not_null();
2894 bool no_conflict = op->no_conflict();
2895
2896 Label Lupdate, Ldo_update, Ldone;
2897
2898 bool do_null = !not_null;
2899 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2900 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2901
2902 assert(do_null || do_update, "why are we here?");
2903 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2904
2905 __ verify_oop(obj, FILE_AND_LINE);
2906
2907 if (do_null) {
2908 if (!TypeEntries::was_null_seen(current_klass)) {
2909 __ cmpdi(CR0, obj, 0);
2910 __ bne(CR0, Lupdate);
2911 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
2912 __ ori(R0, R0, TypeEntries::null_seen);
2913 if (do_update) {
2914 __ b(Ldo_update);
2915 } else {
2916 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
2917 }
2918 } else {
2919 if (do_update) {
2920 __ cmpdi(CR0, obj, 0);
2921 __ beq(CR0, Ldone);
2922 }
2923 }
2924 #ifdef ASSERT
2925 } else {
2926 __ cmpdi(CR0, obj, 0);
2927 __ bne(CR0, Lupdate);
2928 __ stop("unexpected null obj");
2929 #endif
2930 }
2931
2932 __ bind(Lupdate);
2933 if (do_update) {
2934 Label Lnext;
2935 const Register klass = R29_TOC; // kill and reload
2936 bool klass_reg_used = false;
2937 #ifdef ASSERT
2938 if (exact_klass != nullptr) {
2939 Label ok;
2940 klass_reg_used = true;
2941 __ load_klass(klass, obj);
2942 metadata2reg(exact_klass->constant_encoding(), R0);
2943 __ cmpd(CR0, klass, R0);
2944 __ beq(CR0, ok);
2945 __ stop("exact klass and actual klass differ");
2946 __ bind(ok);
2947 }
2948 #endif
2949
2950 if (!no_conflict) {
2951 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2952 klass_reg_used = true;
2953 if (exact_klass != nullptr) {
2954 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
2955 metadata2reg(exact_klass->constant_encoding(), klass);
2956 } else {
2957 __ load_klass(klass, obj);
2958 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
2959 }
2960
2961 // Like InterpreterMacroAssembler::profile_obj_type
2962 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
2963 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
2964 __ cmpd(CR1, R0, klass);
2965 // Klass seen before, nothing to do (regardless of unknown bit).
2966 //beq(CR1, do_nothing);
2967
2968 __ andi_(R0, tmp, TypeEntries::type_unknown);
2969 // Already unknown. Nothing to do anymore.
2970 //bne(CR0, do_nothing);
2971 __ crorc(CR0, Assembler::equal, CR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
2972 __ beq(CR0, Lnext);
2973
2974 if (TypeEntries::is_type_none(current_klass)) {
2975 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
2976 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
2977 __ beq(CR0, Ldo_update); // First time here. Set profile type.
2978 }
2979
2980 } else {
2981 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2982 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2983
2984 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
2985 __ andi_(R0, tmp, TypeEntries::type_unknown);
2986 // Already unknown. Nothing to do anymore.
2987 __ bne(CR0, Lnext);
2988 }
2989
2990 // Different than before. Cannot keep accurate profile.
2991 __ ori(R0, tmp, TypeEntries::type_unknown);
2992 } else {
2993 // There's a single possible klass at this profile point
2994 assert(exact_klass != nullptr, "should be");
2995 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
2996
2997 if (TypeEntries::is_type_none(current_klass)) {
2998 klass_reg_used = true;
2999 metadata2reg(exact_klass->constant_encoding(), klass);
3000
3001 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3002 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3003 __ cmpd(CR1, R0, klass);
3004 // Klass seen before, nothing to do (regardless of unknown bit).
3005 __ beq(CR1, Lnext);
3006 #ifdef ASSERT
3007 {
3008 Label ok;
3009 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3010 __ beq(CR0, ok); // First time here.
3011
3012 __ stop("unexpected profiling mismatch");
3013 __ bind(ok);
3014 }
3015 #endif
3016 // First time here. Set profile type.
3017 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3018 } else {
3019 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3020 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3021
3022 // Already unknown. Nothing to do anymore.
3023 __ andi_(R0, tmp, TypeEntries::type_unknown);
3024 __ bne(CR0, Lnext);
3025
3026 // Different than before. Cannot keep accurate profile.
3027 __ ori(R0, tmp, TypeEntries::type_unknown);
3028 }
3029 }
3030
3031 __ bind(Ldo_update);
3032 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3033
3034 __ bind(Lnext);
3035 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3036 }
3037 __ bind(Ldone);
3038 }
3039
3040
3041 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3042 assert(op->crc()->is_single_cpu(), "crc must be register");
3043 assert(op->val()->is_single_cpu(), "byte value must be register");
3044 assert(op->result_opr()->is_single_cpu(), "result must be register");
3045 Register crc = op->crc()->as_register();
3046 Register val = op->val()->as_register();
3047 Register res = op->result_opr()->as_register();
3048
3049 assert_different_registers(val, crc, res);
3050
3051 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3052 __ kernel_crc32_singleByteReg(crc, val, res, true);
3053 __ mr(res, crc);
3054 }
3055
3056 #undef __